Giải pháp tối ưu công suất tiêu thụ cho các kiến trúc mạng trên chip luận án TS kỹ thuật điện, điện tử và viễn thông 95202

ĐẠI HỌC QUỐC GIA HÀ NỘI TRƯỜNG ĐẠI HỌC CÔNG NGHỆ Phan Hải Phong GIẢI PHÁP TỐI ƯU CÔNG SUẤT TIÊU THỤ CHO CÁC KIẾN TRÚC MẠNG TRÊN CHIP LUẬN ÁN TIẾN SỸ CÔNG NGHỆ ĐIỆN TỬ - VIỄN THÔNG Hà Nội – 2018 ĐẠI HỌC QUỐC GIA HÀ NỘI TRƯỜNG ĐẠI HỌC CÔNG NGHỆ Phan Hải Phong GIẢI PHÁP TỐI ƯU CÔNG SUẤT TIÊU THỤ CHO CÁC KIẾN TRÚC MẠNG TRÊN CHIP Chuyên ngành: Kỹ thuật điện tử Mã số: 9510302.01 LUẬN ÁN TIẾN SỸ CÔNG NGHỆ ĐIỆN TỬ - VIỄN THÔNG NGƯỜI HƯỚNG DẪN KHOA HỌC: PGS TS Trần Xn Tú Hà Nội – 2018 Cỉng tr…nh ÷ỉc ho n th nh t⁄i Khoa i»n tß - Vi„n thỉng v PhỈng th‰ nghi»m trång i”m H» thŁng t‰ch hỉp thỉng minh (SISLAB), Tr÷íng ⁄i håc Cỉng ngh», ⁄i hồc Quc gia H Ni Ngữới hữợng dÔn khoa hồc: PGS.TS Trƒn Xu¥n Tó Ph£n bi»n 1: PGS TS Ho ng V«n Phóc Ph£n bi»n 2: PGS TS Nguy„n Vô Th›ng Ph£n bi»n 3: PGS TS Nguy„n Ngåc Minh Lun Ăn ữổc bÊo vằ trữợc Hi ỗng cĐp nh nữợc chĐm lun Ăn tin s hồp ti: trữớng i håc Cæng ngh», ⁄i håc QuŁc Gia H 12 Nºi, v o hỗi 15 giớ 00 ng y 05 thĂng n«m 2018 Câ th” t…m hi”u lu“n ¡n t⁄i: - Thữ viằn Quc gia Viằt Nam - Trung tƠm Thổng tin - Th÷ vi»n, ⁄i håc QuŁc gia H Nºi L˝I CAM OAN T¡c gi£ xin cam oan to n bº nºi dung tr…nh b y lu“n ¡n v c¡c cỉng tr…nh nghi¶n cøu l cıa ri¶ng t¡c giÊ v ngữới hữợng dÔn khoa hồc l PGS.TS Trn Xu¥n Tó C¡c sŁ li»u v k‚t qu£ tr…nh b y lu“n ¡n l trung thüc v ch÷a tłng ÷ỉc cỉng bŁ b§t ký cỉng tr…nh n o trữợc õ LIC MèN ho n th nh lu“n ¡n n y tỉi xin gßi líi c£m ỡn chƠn th nh n PGS.TS Trn XuƠn Tú, ngữới  rĐt tn tnh hữợng dÔn v to mồi iãu ki»n thu“n lỉi nh§t cho tỉi suŁt qu¡ tr…nh thüc hi»n lu“n ¡n Tỉi xin ch¥n th nh c£m ìn c¡c thƒy cỉ, c¡c c¡n bº cıa PhỈng th‰ nghi»m trång i”m H» thŁng t‰ch hỉp thỉng minh, Tr÷íng ⁄i håc Cæng ngh», ⁄i håc QuŁc gia H Nºi v nhng hỉ trổ tt nhĐt m tổi cõ ữổc qu¡ tr…nh l m vi»c t⁄i phỈng th‰ nghi»m (lun Ăn ữổc thỹc hiằn khuổn kh ã t i QG.18.38) Xin ch¥n th nh c£m ìn c¡c thƒy cổ Khoa iằn tò Vin thổng, Trữớng i hồc Cæng ngh», °c bi»t l c¡c thƒy cæ ð Bº mổn iằn tò v K thut MĂy tnh  giÊng d⁄y v t⁄o måi i•u ki»n thu“n lỉi cho tỉi suŁt thíi gian håc t“p v nghi¶n cøu t⁄i Nh trữớng Tổi cụng chƠn th nh cÊm ỡn sỹ hỉ trổ cÊ vt chĐt v tinh thn ca Trữớng ⁄i håc Khoa håc ⁄i håc Hu‚; Khoa i»n tß Vi„n thỉng cıa Tr÷íng ⁄i håc Khoa håc ⁄i håc Hu‚ Xin c£m ìn gia …nh v b⁄n b– ¢ ln ð b¶n c⁄nh ” ºng vi¶n v gióp ï tæi ho n th nh lu“n ¡n n y H Nºi, th¡ng 12 n«m 2018 Phan H£i Phong Mưc lưc Möc löc Danh möc c¡c tł vi‚t t›t Danh s¡ch h…nh v‡ Danh s¡ch b£ng Mð ƒu Ph÷ìng ph¡p thit k vi mch theo hữợng cổng suĐt tiảu thử thĐp 1.1 Cổng suĐt tiảu thử trản mch tch hổp 1.1.1 1.1.2 1.2 Mºt sŁ ph÷ìng ph¡p thi‚t k‚ vi m⁄ch cỉng 1.2.1 1.2.2 1.2.3 1.3 Ph÷ìng ph¡p thi‚t k‚ a iằn Ăp nguỗn 1.3.1 1.3.2 1.4 Thu“t to¡n lỉ-g‰c mí 1.4.1 1.4.2 Mng trản chip v mt s vĐn ã vã ti ữu nông lữổng tiảu thử 2.1 Giợi thiằu chung vã mng trản chip 2.1.1 iv 2.1.2 2.2 Mºt sŁ gi£i ph¡p thi‚t k‚ m⁄ng trản chip theo hữợng giÊm cổng suĐt tiảu thử 2.2.1 2.2.2 2.2.3 2.2.4 Mæ h…nh bº i•u khi”n tƒn sŁ - i»n ¡p cho b nh tuyn ca mng trản chip 3.1 ã xuĐt mỉ h…nh bº i•u khi”n tƒn sŁ - i» 3.2 Thi‚t k‚ v mỉ h…nh ho¡ bº i•u khi”n tƒn 3.2.1 3.2.2 3.2.3 3.2.4 3.3 Mæ phäng ho⁄t ºng læ-g‰c cıa bº i•u k 3.3.1 3.3.2 3.3.3 3.3.4 3.3.5 Mỉ phäng v ¡nh gi¡ hi»u qu£ cıa bº i•u khi”n tƒn sŁ - i»n ¡p 4.1 Mæ phäng v ữợc lữổng cổng suĐt tiảu 4.1.1 4.1.2 Ănh giĂ hiằu qu£ cıa bº i•u khi”n tƒn sŁ 4.2.1 4.2.2 4.2 Kt lun v hữợng phĂt trin Danh mửc cổng trnh khoa håc cıa t¡c gi£ T i li»u tham kh£o v A A.1 Mt s m nguỗn VHDL lun ¡n A.1.1 A.1.2 A.1.3 A.1.4 vi Danh möc c¡c tł vi‚t t›t Tł vi‚t t›t AVS BU DSM DVFS FIFO GALS GS LPM LU MNI MPSoC NI NoC HFS IP RTL P&R PSU PPL PWM SAF SoC VCPIQ vii VCT VFC VFI VHDL VHSIC VOQ WH viii Danh mưc cỉng tr…nh khoa håc cıa t¡c gi£ C¡c cỉng tr…nh câ li¶n quan ‚n lu“n ¡n C1 Hai-Phong Phan, Xuan-Tu Tran, Thi‚t k‚ v mổ hnh hoĂ b xò lỵ lổ-gic mớ i•u khi”n tƒn sŁ - i»n ¡p , In Proceeding of the 2014 National Conference on Electronics, Communications and Information Technology (REV-ECIT 2014), pp 48-53, Nha Trang, Viet Nam, 2014, ISBN: 978-604-67-0349-5 C2 Hai-Phong Phan, Xuan-Tu Tran, A Fuzzy-Logic based VoltageFrequency Controller for Network-on-Chip Routers , In Proceedings of the 11th IEEE Conference on PhD Research in Microelectronics and Electronics (IEEE PRIME 2015), pp 192-195, July 2015, Glasgow, Scotland, ISBN: 978-1-4799-8229-5 J1 Hai-Phong Phan, Xuan-Tu Tran, Design and Modeling of a VoltageFrequency Controller for Network-on-Chip Routers base on Fuzzy-Logic , VNU Journal of Science: Computer Science and Communication Engineering, pp 56-65, 2015, ISSN:0866-8612 C3 Hai-Phong Phan, Xuan-Tu Tran, Fuzzy-Logic based Low Power Solution for Network-on-Chip Architectures , In Proceedings of the 2016 International Conference on Advanced Technologies for Communications (ATC 2016), pp 334338, 12-14 October 2016, Hanoi, Vietnam, ISBN: 978-1-5090-2711-8 C4 Hai-Phong Phan, Xuan-Tu Tran, Tomohiro Yoneda, Power Consumption Estimation using VNOC2.0 Simulator for a Fuzzy-Logic based Low Power Network-on-Chip , In Proceedings of the 2017 IEEE International Conference on IC Design and Technology (IEEE ICICDT 2017), pp 1-4, 23-25 May 2017, Austin, Texas, USA, ISBN: 978-1-5090-4502-0 95 C¡c cỉng tr…nh kh¡c ¢ cỉng bŁ qu¡ tr…nh l m nghi¶n cøu sinh C5 Hai-Phong Phan, Hung K Nguyen, Duy-Hieu Bui, Nam-Khanh Dang, Xuan-Tu Tran, System-on-Chip Testbed for Validating the Hardware Design of H.264/AVC Encoder , In Proceeding of the National Conference on Electronics and Communications (REV 2013), pp 51-55, Ha Noi, Viet Nam, 2013 C6 Tung Nguyen, Duy-Hieu Bui, Hai-Phong Phan, Trong-Trinh Dang, Xuan-Tu Tran HighPerformance Adaption of ARM Processor into Network-on-Chip Ar-chitectures In Proceedings of the 26th IEEE System-on-Chip Conference (IEEE SOCC 2013), pp 222-227, September 2013, Erlangen, Germany ISSN: 2164-1706 C7 Thanh-Vu Le Van, Hai-Phong Phan, Xuan-Tu Tran (2014), High-Level Model-ing of a Novel Reconfigurable Network-on-Chip Router , in Proceeding of the First NAFOSTED Conference on Information and Computer Science (NICS 2014), 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