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January 2006 1Verilog Digital System Design Copyright Z. Navabi, 2006 Verilog Digital System Design Verilog Digital System Design Z. Navabi, McGraw-Hill, 2005 Z. Navabi, McGraw-Hill, 2005 Chapter 4 Chapter 4 Combinational Circuit Combinational Circuit Description Description Prepared by : Prepared by : Homa Alemzadeh - Nima Tayebi Homa Alemzadeh - Nima Tayebi January 2006 2Verilog Digital System Design Copyright Z. Navabi, 2006 4.1 Module Wires 4.1 Module Wires 4.1.1 Ports 4.1.1 Ports 4.1.2 Interconnections 4.1.2 Interconnections 4.1.3 Wire values and timing 4.1.3 Wire values and timing 4.1.4 A simple testbench 4.1.4 A simple testbench 4.2 Gate Level Logic 4.2 Gate Level Logic 4.2.1 Gate primitives 4.2.1 Gate primitives 4.2.2 User defined primitives 4.2.2 User defined primitives 4.2.3 Delay formats 4.2.3 Delay formats 4.2.4 Module parameters 4.2.4 Module parameters Combinational Circuit Combinational Circuit Description Description January 2006 3Verilog Digital System Design Copyright Z. Navabi, 2006 4.3 Hierarchical Structures 4.3 Hierarchical Structures 4.3.1 Simple hierarchies 4.3.1 Simple hierarchies 4.3.2 Vector declarations 4.3.2 Vector declarations 4.3.3 Iterative structures 4.3.3 Iterative structures 4.3.4 Module path delay 4.3.4 Module path delay 4.4 Describing Expressions with Assign Statements 4.4 Describing Expressions with Assign Statements 4.4.1 Bitwise operators 4.4.1 Bitwise operators 4.4.2 Concatenation operators 4.4.2 Concatenation operators 4.4.3 Vector operations 4.4.3 Vector operations 4.4.4 Conditional operation 4.4.4 Conditional operation 4.4.5 Arithmetic expressions in assignments 4.4.5 Arithmetic expressions in assignments 4.4.6 Functions in expressions 4.4.6 Functions in expressions 4.4.7 Bus structures 4.4.7 Bus structures 4.4.8 Net declaration assignment 4.4.8 Net declaration assignment Combinational Circuit Combinational Circuit Description Description January 2006 4Verilog Digital System Design Copyright Z. Navabi, 2006 4.5 Behavioral Combinational Descriptions 4.5 Behavioral Combinational Descriptions 4.5.1 Simple procedural blocks 4.5.1 Simple procedural blocks 4.5.2 Timing control 4.5.2 Timing control 4.5.3 Intra-assignment delay 4.5.3 Intra-assignment delay 4.5.4 Blocking and nonblocking assignments 4.5.4 Blocking and nonblocking assignments 4.5.5 Procedural if-else 4.5.5 Procedural if-else 4.5.6 Procedural case statement 4.5.6 Procedural case statement 4.5.7 Procedural for statement 4.5.7 Procedural for statement 4.5.8 Procedural while loop 4.5.8 Procedural while loop 4.5.9 A multilevel description 4.5.9 A multilevel description Combinational Circuit Combinational Circuit Description Description January 2006 5Verilog Digital System Design Copyright Z. Navabi, 2006 4.6 Combinational Synthesis 4.6 Combinational Synthesis 4.6.1 Gate level synthesis 4.6.1 Gate level synthesis 4.6.2 Synthesizing continuous assignments 4.6.2 Synthesizing continuous assignments 4.6.3 Behavioral synthesis 4.6.3 Behavioral synthesis 4.6.4 Mixed synthesis 4.6.4 Mixed synthesis 4.7 Summary 4.7 Summary Combinational Circuit Combinational Circuit Description Description January 2006 6Verilog Digital System Design Copyright Z. Navabi, 2006 Module Wires Module Wires  Wires or Wires or net net s are used for interconnection of substructures together, s are used for interconnection of substructures together, and interconnection of module ports to appropriate ports of a and interconnection of module ports to appropriate ports of a module’s substructures. module’s substructures.  By default module ports are wires ( By default module ports are wires ( net net ). ).  Wires have delays, can take ant of the four values ( Wires have delays, can take ant of the four values ( 0 0 , , 1 1 , , Z Z and and X X ). ). January 2006 7Verilog Digital System Design Copyright Z. Navabi, 2006 Module Wires Module Wires Module Module Wires Wires Ports Ports Interconnections Interconnections Wire Values Wire Values and Timing and Timing A Simple A Simple Testbench Testbench January 2006 8Verilog Digital System Design Copyright Z. Navabi, 2006 Ports Ports Module Module Wires Wires Ports Ports Interconnections Interconnections Wire Values Wire Values and Timing and Timing A Simple A Simple Testbench Testbench Ports Ports January 2006 9Verilog Digital System Design Copyright Z. Navabi, 2006 Ports Ports  Ports are allowed to be defined as Ports are allowed to be defined as input input , , output output or or inout inout . .  An An input input port is always a port is always a net net and can only be read. and can only be read.  An An output output is a is a net net by default, and can be declared as a by default, and can be declared as a reg reg if it is to be if it is to be assigned a value inside a procedural block. assigned a value inside a procedural block.  An An inout inout is a bidirectional port that can be written into or read from. is a bidirectional port that can be written into or read from. An An inout inout port is always a port is always a net net . . January 2006 10Verilog Digital System Design Copyright Z. Navabi, 2006 Ports Ports  A Simple Module A Simple Module `timescale `timescale 1ns/100ps 1ns/100ps module module Anding ( Anding ( input input a, b, a, b, output output y); y); and and (y, a, b); (y, a, b); endmodule endmodule Ports Ports [...]... A Testbench for TriMux January 2006 Verilog Digital System Design Copyright Z Navabi, 2006 20 Gate Level Logic Gate Level Logic Gate Primitives Delay Formats January 2006 User Defined Primitives Module Parameters Verilog Digital System Design Copyright Z Navabi, 2006 21 Gate Primitives Gate Level Logic Gate Gate Primitives Primitives Delay Formats January 2006 User Defined Primitives Module Parameters... Interconnections A Simple Testbench Verilog Digital System Design Copyright Z Navabi, 2006 14 Wire Values and Timing  A net used for a module port or an internal interconnection can take any of the four Verilog logic values, i.e., 0, 1, Z, and X  Such a value assigned to a net can have a delay, which may be specified by the assignment to the net or as part of its declaration  Multiple simultaneous assignments... ( im2, b, c ), ( im3, c, a ); or #(3, 5) (y, im1, im2, im3); endmodule  Majority Verilog Code January 2006 Verilog Digital System Design Copyright Z Navabi, 2006 26 User Defined Primitives Gate Level Logic Gate Primitives Delay Formats January 2006 User Defined User Defined Primitives Primitives Module Parameters Verilog Digital System Design Copyright Z Navabi, 2006 27 User Defined Primitives  ... primitive, a user-defined primitive (UDP) can be formed A combinational UDP can form a combinational function of up to 10 inputs and one output The definition of a UDP can only include a table in the form of a logical Truth Table A UDP output can only be specified as a 0 or a 1 The Z value cannot be specified, and an X happens for unspecified input combinations A UDP definition cannot include delay values, but... For all of them maj3 1 ? 1 : 1; produces the same output ? 1 1 : 1; endtable endprimitive  Majority UDP January 2006 Verilog Digital System Design Copyright Z Navabi, 2006 29 Delay Formats Gate Level Logic Gate Primitives Delay Delay Formats Formats January 2006 User Defined Primitives Module Parameters Verilog Digital System Design Copyright Z Navabi, 2006 30 Delay Formats      A two-value gate... c ); nand #(2:4:6, 3:5:7) (y, im1, im2, im3, im4); endmodule  Verilog Code Using min:typ:max Delay January 2006 Verilog Digital System Design Copyright Z Navabi, 2006 33 Module Parameters Gate Level Logic Gate Primitives Delay Formats January 2006 User Defined Primitives Module Module Parameters Parameters Verilog Digital System Design Copyright Z Navabi, 2006 34 Module Parameters   Parameters can . 4.1.4 A simple testbench 4.1.4 A simple testbench 4.2 Gate Level Logic 4.2 Gate Level Logic 4.2.1 Gate primitives 4.2.1 Gate primitives 4.2.2 User defined. internal interconnection can take any of the four Verilog logic values, i.e., any of the four Verilog logic values, i.e., 0 0 , , 1 1 , , Z Z , and ,