Tài liệu thiết kế logic khả trình doc

January 2006 1Verilog Digital System Design Copyright Z. Navabi, 2006 Verilog Digital System Design Verilog Digital System Design Z. Navabi, McGraw-Hill, 2005 Z. Navabi, McGraw-Hill, 2005 Chapter 1 Chapter 1 Digital System Design Digital System Design Automation with Verilog Automation with Verilog Prepared by: Prepared by: Homa Alemzadeh Homa Alemzadeh January 2006 2Verilog Digital System Design Copyright Z. Navabi, 2006 Digital System Design Digital System Design Automation with Verilog Automation with Verilog 1.1 Digital Design Flow 1.1 Digital Design Flow 1.1.1 Design entry 1.1.1 Design entry 1.1.2 Testbench in Verilog 1.1.2 Testbench in Verilog 1.1.3 Design validation 1.1.3 Design validation 1.1.4 Compilation and synthesis 1.1.4 Compilation and synthesis 1.1.5 Postsynthesis simulation 1.1.5 Postsynthesis simulation 1.1.6 Timing analysis 1.1.6 Timing analysis 1.1.7 Hardware generation 1.1.7 Hardware generation 1.2 Verilog HDL 1.2 Verilog HDL 1.2.1 Verilog evolution 1.2.1 Verilog evolution 1.2.2 Verilog attributes 1.2.2 Verilog attributes 1.2.3 The verilog language 1.2.3 The verilog language 1.3 Summary 1.3 Summary January 2006 3Verilog Digital System Design Copyright Z. Navabi, 2006 Digital System Design Digital System Design Automation with Verilog Automation with Verilog  As the size and complexity of digital systems increase, more computer As the size and complexity of digital systems increase, more computer aided design (CAD) tools are introduced into the hardware design aided design (CAD) tools are introduced into the hardware design process. process.  Early simulation and primitive hardware generation tools have given Early simulation and primitive hardware generation tools have given way to sophisticated design entry, verification, high-level synthesis, way to sophisticated design entry, verification, high-level synthesis, formal verification, and automatic hardware generation and device formal verification, and automatic hardware generation and device programming tools. programming tools.  Growth of design automation tools is largely due to hardware Growth of design automation tools is largely due to hardware description languages (HDLs) and design methodologies that are description languages (HDLs) and design methodologies that are based on these languages. based on these languages.  Based on HDLs, new digital system CAD tools have been developed Based on HDLs, new digital system CAD tools have been developed and are now widely used by hardware designers. and are now widely used by hardware designers.  One of the most widely used HDLs is the Verilog HDL. One of the most widely used HDLs is the Verilog HDL.  Because of its wide acceptance in digital design industry, Verilog has Because of its wide acceptance in digital design industry, Verilog has become a must-know for design engineers and students in computer- become a must-know for design engineers and students in computer- hardware-related fields. hardware-related fields. January 2006 4Verilog Digital System Design Copyright Z. Navabi, 2006 Digital Design Flow Digital Design Flow  FPLD Design Flow FPLD Design Flow January 2006 5Verilog Digital System Design Copyright Z. Navabi, 2006 Digital Design Flow Digital Design Flow  FPLD Design Flow FPLD Design Flow Design Entry Design Entry Phase Phase January 2006 6Verilog Digital System Design Copyright Z. Navabi, 2006 Digital Design Flow Digital Design Flow  Digital Design Flow begins with specification of the design at various Digital Design Flow begins with specification of the design at various levels of abstraction. levels of abstraction.  Design entry phase: Design entry phase: Specification of design as a mixture of behavioral Specification of design as a mixture of behavioral Verilog code, instantiation of Verilog modules, and bus and wire Verilog code, instantiation of Verilog modules, and bus and wire assignments assignments January 2006 7Verilog Digital System Design Copyright Z. Navabi, 2006 Digital Design Flow Digital Design Flow  FPLD Design Flow FPLD Design Flow (Continued) (Continued) Presynthesis Presynthesis Verification Verification January 2006 8Verilog Digital System Design Copyright Z. Navabi, 2006 Digital Design Flow Digital Design Flow  Presynthesis verification: Presynthesis verification: Generating testbenches for verification of the Generating testbenches for verification of the design and later for verifying the synthesis output design and later for verifying the synthesis output January 2006 9Verilog Digital System Design Copyright Z. Navabi, 2006 Digital Design Flow Digital Design Flow  FPLD Design Flow FPLD Design Flow (Continued) (Continued) Synthesis Process Synthesis Process January 2006 10Verilog Digital System Design Copyright Z. Navabi, 2006 Digital Design Flow Digital Design Flow  Synthesis process: Synthesis process: Translating the design into actual hardware of a Translating the design into actual hardware of a target device (FPLD, ASIC or custom IC) target device (FPLD, ASIC or custom IC) [...]... Z Navabi, 2006 13 Digital Design Flow  Digital Design Flow ends with generating netlist for an application specific integrated circuits (ASIC), layout for a custom IC, or a program for a programmable logic devices (PLD) January 2006 Verilog Digital System Design Copyright Z Navabi, 2006 14 Digital Design Flow Digital Design Flow Design Entry Testbench in Verilog Design Validation Compilation and Synthesis... High-level Verilog designs usually described at this level  Verilog constructs used in RT level design:  procedural statements for high-level behavioral description  continuous assignments for representing logic blocks, bus assignments, and bus and input/output interconnect specifications  instantiation statements for using lower-level components in an upper-level design January 2006 Verilog Digital System... correspondence A Verilog description for synthesis:  Cannot include signal and gate level timing specifications, file handling, and other language constructs that do not translate to sequential or combinational logic equations  Must follow certain styles of coding for combinational and sequential circuits Compilation process has three phases:  Analysis Phase  Synthesis Phase  Routing and Placement Phase January . layout for a custom IC, or a program for a programmable logic devices (PLD) program for a programmable logic devices (PLD) January 2006 15Verilog Digital System.  continuous assignments continuous assignments for representing logic blocks, bus for representing logic blocks, bus assignments, and bus and input/output interconnect