Optical Signal Processing Based on 4×4 Multimode Interference Structures

In the literature, there are some other approaches for realizing optical logic gates based on variety of material systems such as optical logic based on nonlinear materials [4, 5], Mach[r]

Optical Signal Processing Based on 4×4 Multimode Interference Structures

Duy-Tien Le1, Trung-Thanh Le1, and Laurence W Cahill2* 1International School, Vietnam National University (VNU-IS), Hanoi, Vietnam

2Department of Engineering, La Trobe University, Melbourne, Australia *Tel: (+613) 9479 3730, Fax: (+613)9471 0524, e-mail: l.cahill@latrobe.edu.au ABSTRACT

All-optical logic gates have attracted considerable attention over the past decade They have found application as adders, subtractors, header recognizers, parity checkers and in encryption systems In this paper, we present a new structure based on cascaded 4×4 and 2×2 multimode interference (MMI) couplers for implementing optical XOR, XNOR, NAND and OR logic gates The emphasis of the design is on optimising bandwidth and fabrication tolerance Such a design would be useful for optical label swapping and recognition in optical packet switching networks We use silicon on insulator (SOI) waveguides that are compatible with the CMOS technology, for designing the whole device The Beam Propagation Method (BPM) and the Eigenmode Expansion Method (EEM) are used for numerical simulations We show that the contrast ratios for logic and logic for XOR, XNOR, NAND, and OR gates are from 18 dB to 28 dB for a bandwidth of 30nm, respectively A large fabrication tolerance of ±500 nm can be achieved by using this structure

Keywords: optical logic gate, multimode interference, silicon on insulator, silicon photonics, beam propagation method

1 INTRODUCTION

All-optical logic gates have received considerable attention over the last ten years Optical logic gates have many possible applications in optical signal processing systems and optical switching networks Examples of potential applications include adders, subtractors, header recognizers, parity checkers, and encryption systems [1] In all-optical networks, there is a great need for implementing all-all-optical logic gates having small size, low power consumption and high-speed [2, 3] These requirements can be met by using photonic integrated circuits, especially silicon photonics In the literature, there are some other approaches for realizing optical logic gates based on variety of material systems such as optical logic based on nonlinear materials [4, 5], Mach-Zehnder interferometer with a nonlinear phase shifter [6-11], semiconductor optical amplifiers (SOAs)[12], microelectromechanical systems (MEMS) [13], MMI based photonic crystal [14, 15], periodic waveguide [16], plasmonic waveguide[17] and multimode interference waveguide [18] These methods require high power and/or complicated fabrication Over the last few years, we have presented a general theory for implementing optical signal processing based on MMI elements [19-22] For further development, we have proposed 2×2, 3×3 and 5×5 MMI based structures for implementing many optical logic gates including NAND, OR, AND, NOT, XNOR, and NOR gates [1]

In this study, we further develop a new scheme for realizing optical logic gates based on only one 4×4 MMI cascaded with a 2×2 MMI coupler The device has the advantage of ease of fabrication, large fabrication tolerance, high contrast ratio and compatibility with system-on-a- chip configuration

2 THEORY

Optical logic functions can be realized using the interference between two signals The principle of interference between two waves was first introduced by Young in the study of light [23] If two signals having the same polarization, the same normalized amplitude but different phases ϕ1 and ϕ2 respectively, interfere with each

other, the normalized power of the summed signal is expressed by [24]

2

1

cos [( ) / 2]

P∝ ϕ ϕ− (1)

The normalized power of the summed signal will become zero if the phases ϕ1 and ϕ2 satisfy the relation

ϕ ϕ− = π, 3π,…, (2n+1)π, where n is an integer Note that MMI structures naturally rely on interference for their operation The operation of an optical MMI coupler is based on the self-imaging principle [25, 26] Self-imaging is a property of a multimode waveguide whereby an input field is reproduced in single or multiple images at periodic intervals along the propagation direction of the waveguide We assume that the structure has

N input and N output access waveguides, all of which are identical single mode waveguides with width Wa

The input and output waveguides are located at position pi [27], given by

1

( )

2 MMI

i W

p i

N

The electrical field inside the MMI coupler can be expressed by [28]

2

( , ) exp( ) exp( )sin( )

4

M m

m MMI

m m

E p z jkz E j z p

W p p = = − Λ ∑ (3)

where i= ÷1 N, and N is the number of ports of MMI coupler Therefore, optical logic gates can be realized by solely using an MMI coupler along with phase shifters For optical logic gates based on the MMI principle, information is encoded at the input and the output in amplitude or in phase In this work, phase encoding of information is used for input signals and amplitude encoding is used for output signals We use the logic “1” is represented by 1e and logic “0” is represented by j0 0e To determine the logic level at the output of the j0

device, the power in the output waveguide needs to be compared to a threshold value This can be done electronically by connecting output ports to a photo-detector and a decision circuit Another approach is to use an optical threshold device based on active MMI couplers instead of using an electronic threshold device [29]

Figure 1(a) shows the proposed scheme for optical logic gate implementation based on 4×4 and 2×2 MMI structures By properly choosing the positions of input and output waveguides, the complex amplitude at output port y2 can be expressed by

2 0.5( 4) 0.5( 4) 0.5( 3) ( , )2

y = jx x+ + jx x− = jx x− + x + jx = f x x (4)

where x x1, are local oscillators and x x2, 3are input logic variables and y2 is the output logic variable Here we

assume that the wavelength and polarization of the local oscillation signals and information signals are the same

(a) (b) W = 500 nm

Figure 1: (a) Proposed scheme for optical logic gates: (b) Field profile of the waveguide

In this study, we use the SOI waveguide with a width of 500 nm, height of 220 nm and slab height of 90 nm for single mode operation The optical mode of the waveguide simulated by the EEM method is shown in Fig 1(b) From eq (4) we can achieve XOR, XNOR, OR and NAND logic gates by the following principles: (a) XOR gate:

To realize the XOR logic gate, we use the local oscillation inputs /2 1 j

x = ep and

4 j

x = e and we assume that a phase shifter of −p/ is used at the input port x3 The input signal is encoded by the phase information This

means that on input port x3, / 2p phase corresponds to logic and −p/ 2corresponds to logic For input port

x , 0-phase corresponds to logic and p-phase corresponds to logic As a result, the truth table for the XOR gate is shown in Table

(b) XNOR gate:

We use the local oscillation inputs /2 1 j

x = ep and j

x = e and we assume that a phase shifter of / 2p is used at the input port x3 For input port x3, a / 2p phase corresponds to logic and −p/ 2corresponds to logic

For input port x2, 0-phase corresponds to logic and p-phase corresponds to logic As a result, the truth table

for the XNOR gate is shown in Table

Table Truth table of the XOR logic gate

Input logic Output logic

2

x (phase) x3 (phase) y2 = f(x2, x3)

0 (0) 0 (−p / 2)

0 (0) 1 (p/ 2)

1 (p) (−p / 2)

1 (p) 1 (p/ 2)

Table Truth table of the XNOR logic gate

Input logic Output logic

2

x (phase) x3 (phase) y2 = f(x2, x3)

0 (0) 0 (p/ 2)

0 (0) 1 (-p / 2)

1 (p) (p/ 2)

1 (p) 1 (-p / 2)

(d) NAND gate:

We use the local oscillation inputs /2 1 j

x = ep and /2 j

x = ep For input ports

2

x and x3, 0-phase corresponds

to logic and p-phase corresponds to logic The truth table for the NAND gate is shown in Table

Table Truth table of the OR logic gate

Input logic Output logic

2

x (phase) x3 (phase) y2 = f(x2, x3)

0 (0) (0)

0 (0) (p)

1 (p) (0)

1 (p) (p)

Table Truth table of the NAND logic gate

Input logic Output logic

2

x (phase) x3 (phase) y2 = f(x2, x3)

0 (0) (0)

0 (0) (p)

1 (p) (0)

1 (p) (p)

3 SIMULATION RESULTS

In this section, light propagation through the logic gates is investigated The BPM method is used for the simulations Figure shows the field distributions of the XOR logic gate at a wavelength of 1.55 µm for input logic values of 00, 01, 10 and 11, respectively The simulations show that there is good agreement with the theoretical analysis given by Table

(a) Input 00 (b) Input 01

(c) Input 10 (b) Input 11

Figure XOR gate with input signals 00, 01, 10, 11

Figure shows the field distributions of the XNOR logic gate for input logic values of 00, 01, 10 and 11, respectively The simulations show that there is a good agreement with the theoretical results given by Table

(a) Input 00 (b) Input 01

(c) Input 10 (b) Input 11

Figure XNOR gate with input signals 00, 01, 10, 11

(a) Input 00 (b) Input 01

(c) Input 10 (b) Input 11

Figure OR gate with input signals 00, 01, 10, 11

Figure shows the field distributions of the NAND logic gate for input logic values of 00, 01, 10 and 11, respectively The simulations shows that there is good agreement with the theoretical analysis given by Table

(a) Input 00 (b) Input 01

(c) Input 10 (b) Input 11

Figure OR gate with input signals 00, 01, 10, 11

For a compact device, we use a width of àm for the 4ì4 MMI coupler The normalized output powers at output ports y3 and y4 for a signal at input port x4 are shown in Fig 6(a) The overall transmission of the structure

We evaluate the performance of the optical logic gates by using the contrast ratio (CR) For example, the optical XOR gate, the CR is expressed by

logi 10

logi

10log ( c )(dB)

c P CR

P

= (5)

As a result, the CR for the XOR gate is shown in Fig It is shown that for a bandwidth of 30nm from 1530 nm to 1560 nm, the CR varies from 18 dB to 28 dB

Figure 7: (a) Normalized output powers for logic and 0;(b) Contrast ratio

Figure shows the normalized output powers for a variation of the MMI length We can see that for a fabrication tolerance of ±500 nm, the variation in the normalized output powers of 0.02 can be achieved This results in a very large fabrication tolerance

Figure Normalized output powers with different lengths of the 4×4 MMI coupler

4 CONCLUSIONS

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