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The main contents of the chapter consist of the following: Multiple flip flops can be combined to form a data register, Shift registers allow data to be transported one bit at a time, registers also allow for parallel transfer.
Lecture 25 Shift Registers Overvie w ° Multiple flip flops can be combined to form a data register ° Shift registers allow data to be transported one bit at a time ° Registers also allow for parallel transfer • Many bits transferred at the same time ° Shift registers can be used with adders to build arithmetic units ° Remember: most digital hardware can be built from combinational logic (and, or, invert) and flip flops • Basic components of most computers Reg iste °rRegister: Group of Flip-Flops with °Par Ex: D Flip-Flops allel °Loa Holds a Word (Nibble) of Data °dLoads in Parallel on Clock Transition ° Asynchronous Clear (Reset) Reg iste The transfer of new information into a register is referred to as loading the register r All the bits of the register are loaded simultaneously with a single clock pulse, the loading is parallel with CP input acts as an enable signal that controls the Par loading of new information into the register When CP goes to 1, the input information is loaded into allel the register If CP remains at 0, the content of the Loa register is not changed d The load input goes through a buffer gate (to reduce loading) and through a series of AND gates to the Rand S inputs of each flip-flop Although If the load input is 0, both R and S are 0, and no change of state occurs with any clock pulse For each I that is equal to 1, the corresponding flip-flop inputs are S = 1, R = For each I that is equal to 0, the corresponding flip-flop inputs are S = 0, R = Thus, the input value is transferred into the register provided the load input is and the clear input is4 Reg iste °r Load Control = with • New data loaded Loa on next positive d clock edge Con °trol Load Control = • Old data reloaded on next positive clock edge The feedback connection in each flip-flop is necessary when a D type is used because a D flip-flop does not have a "no change" input condition Sequential-Logic Implementation Since registers are readily available as MSI circuits, it becomes convenient at times to employ a register as part of the sequential circuit The present state of the register and the external inputs determine the next state of the register and the values of external outputs Part of the combinational circuit determines the next state and the other part generates the outputs The next state value from the combinational circuit is loaded into the register with a clock pulse If the register has a load input, it must be set to I; otherwise, if the register has no load input, the next state value will be transferred automatically every clock pulse Example Design the sequential circuit whose state table is listed in Fig The state table specifies two flip-flops, A1 and A2; one input, x; and one output, y The next-state and output information is obtained directly from the table: Example Design the sequential circuit whose state table is listed in Fig The state table specifies two flip-flops, A1 and A2; one input, x; and one output, y The next-state and output information is obtained directly from the table: Example Design the sequential circuit whose state table is listed in Fig The state table specifies two flip-flops, A1 and A2; one input, x; and one output, y The next-state and output information is obtained directly from the table: Example Design the sequential circuit whose state table is listed in Fig The state table specifies two flip-flops, A1 and A2; one input, x; and one output, y The next-state and output information is obtained directly from the table: 10 Shif t °regi Parallel-to-serial conversion for serial transmission ster appl icati on parallel outputs parallel inputs serial transmission 19 Serial Transfer of Data ° Transfer from register X to register Y (negative clock edges for this example) 20 Patt ern ° Combinational function of input samples rec • in this case, recognizing the pattern 1001 on the single input ognsignal izer OUT OUT1 IN D Q D Q OUT2 D Q OUT3 OUT4 D Q CLK Clk IN OUT1 OUT2 OUT3 OUT4 OUT Before 1 1 0 0 0 0 0 2 0 1 0 0 0 0 3 0 0 1 0 0 0 4 1 0 0 1 0 0 0 1 0 0 1 1 21 Patt ern ° Combinational function of input samples rec • in this case, recognizing the pattern 100011 on the single input ognsignal izer • flip-Flops are required • clock pulses 22 Seri al °Add Slower than itio parallel n (D °Flip Low cost °Flo Share fast hardware on p)slow data ° Good for multiplexed data 23 Seri al Add ° Only one full itio adder n (D ° Reused Flip for each bit Flo ° Start with lowp) order bit addition ° Note that carry (Q) is saved ° Add multiple values • New values placed in shift register B 24 Seri al Add itio n (D Flip Flo p) ° Shift control used to stop addition ° Generally not a good idea to gate the clock ° Shift register can be arbitrary length ° FA can be built from combin logic 25 Design a serial adder using a sequential-logic procedure Two shift registers are required to store the binary numbers to be added serially serial outputs from the registers are designated by variables x and y Two inputs, x and y, that provide a pair of significant bits, an output S that generates the sum bit, and Hip-flop Q for storing the carry The present state of Q provides the present value of the carry The clock pulse that shift the registers enables flip-flop Q to load the next carry This carry is then used with the next pair of bits in x and y The state table that specifies the sequential circuit is given in Table 26 Design a serial adder using a sequential-logic procedure 27 Design a serial adder using a sequential-logic procedure 28 Design a serial adder using a sequential-logic procedure 29 Design a serial adder using a sequential-logic procedure 30 ° ° ° Uni ver Clearsal Shif Clock t Shift Reg • Right iste • Left r ° Load ° Read ° Control 31 ° ° ° Uni ver Clearsal Shif Clock t Shift Reg • Right iste • Left r ° Load ° Read ° Control 32 Summary ° Shift registers can be combined together to allow for data transfer ° Serial transfer used in modems and computer peripherals (e.g mouse) ° D flip flops allow for a simple design • Data clocked in during clock transition (rising or falling edge) ° Serial addition takes less chip area but is slow ° Universal shift register allows for many operations • The register is programmable • It allows for different operations at different times 33 ... Table 26 Design a serial adder using a sequential -logic procedure 27 Design a serial adder using a sequential -logic procedure 28 Design a serial adder using a sequential -logic procedure 29 Design. .. combin logic 25 Design a serial adder using a sequential -logic procedure Two shift registers are required to store the binary numbers to be added serially serial outputs from the registers are designated... a data register ° Shift registers allow data to be transported one bit at a time ° Registers also allow for parallel transfer • Many bits transferred at the same time ° Shift registers can be