Lecture Digital logic design - Lecture 3: Complements, number codes and registers. The main contents of the chapter consist of the following: Complement of numbers, addition and subtraction, binary coded decimal, gray codes for binary numbers, ASCII characters, moving towards hardware, storing data, processing data.
Digital Logic Design Lecture Complements, Number Codes and Registers Overvie w ° Complement of numbers • Addition and subtraction ° Binary coded decimal ° Gray codes for binary numbers ° ASCII characters ° Moving towards hardware • Storing data • Processing data Complements • In general, we (human beings) express negative numbers by placing a minus (-) sign at the left end of the number Similarly while representing the integers in binary format, we can leave the left-most bit be the sign bit If the leftmost bit is a zero, the integer is positive; if it is a one, it is negative • Zero is positive and -0 = • The top-most bit should tell us the sign of the integer • The negative of a negative integer is the original integer ie., -(-55) is 55 • x - y should give the same result as x + (-y) That is, - should give us the same result as + (-3) • Negative and positive numbers shouldn't be treated in different ways when we multiplication and division with them Complement ° If we consider only positive numbers, this would allow for all numbers from (naturally represented by 00000000) to and inclusively 255 (represented by 11111111) ° The most obvious solution is to spare the first bit as a sign indicator, thus leaving the last bits to represent the numbers ° This simple way to represent negative numbers has for it the equally simple way to compute the negative of a given number: just invert the first bit! Hence, the number 3, for example, represented as (00000011) will give (10000011) for -3 (we have just toggled the first bit) ° This simple way has a drawback: the negative of (00000000) is now (10000000), known as -0 Two’s Complement Representation • The two’s complement of a binary number involves inverting all bits and adding • 2’s comp of 00110011 is 11001101 • 2’s comp of 10101010 is 01010110 • For an n bit number N the 2’s complement is (2n-1) – N + • Called radix complement by Mano since 2’s complement for base (radix 2) • To find negative of 2’s complement number take the 2’s complement 000011002 = 1210 Sign bit Magnitude 111101002 = -1210 Sign bit Magnitude Two’s Complement Shortcuts ° Algorithm – Simply complement each bit and then add to the result • Finding the 2’s complement of (01100101)2 and of its 2’s complement… N = 01100101 [N] = 10011010 + 10011011 01100100 + - - 10011011 01100101 ° Algorithm – Starting with the least significant bit, copy all of the bits up to and including the first bit and then complementing the remaining bits • N =01100101 [N] =10011011 Fini te °Nu Machines that use 2’s complement arithmetic can mb represent integers in the range er Rep -2n-1 ? 100 @ A B C D E F G H I J K L M N O 101 P Q R S T U V W X Y Z [ \ ] ^ _ 110 ` a b c d e f g h i j k l m n 23 o 111 p q r s t u v w x y z { | } ~ DEL ASCII Code Numeric codes 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 000 NULL SOH STX ETX EDT ENQ ACK BEL BS HT LF VT FF CR SO SI 001 DLE DC1 DC2 DC3 DC4 NAK SYN ETB CAN EM SUB ESC FS GS RS US 010 ! " # $ % & ' ( ) * + , / 011 : ; < = > ? 100 @ A B C D E F G H I J K L M N O 101 P Q R S T U V W X Y Z [ \ ] ^ _ 110 ` a b c d e f g h i j k l m n 24 o 111 p q r s t u v w x y z { | } ~ DEL ASCII Code Punctuation, etc 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 000 NULL SOH STX ETX EDT ENQ ACK BEL BS HT LF VT FF CR SO SI 001 DLE DC1 DC2 DC3 DC4 NAK SYN ETB CAN EM SUB ESC FS GS RS US 010 ! " # $ % & ' ( ) * + , / 011 : ; < = > ? 100 @ A B C D E F G H I J K L M N O 101 P Q R S T U V W X Y Z [ \ ] ^ _ 25 110 ` a b c d e f g h i j k l m n o 111 p q r s t u v w x y z { | } ~ DEL ASCII Codes and Data Transmission ° ASCII Codes ° A – Z (26 codes), a – z (26 codes) ° 0-9 (10 codes), others (@#$%^&*….) ° Complete listing in Mano text ° Transmission susceptible to noise ° Typical transmission rates (1500 Kbps, 56.6 Kbps) ° How to keep data transmission accurate? Pari ty °Cod Parity codes are formed by concatenating a parity esbit, P to each code word of C ° In an odd-parity code, the parity bit is specified so that the total number of ones is odd ° In an even-parity code, the parity bit is specified so that the total number of ones is even P Information Bits 1 0 0 1 0 0 1 Added even parity bit Added odd parity bit Pari ty °Cod Concatenate a parity bit to the ASCII code for the e characters 0, X, and = to produce both odd-parity Exa and even-parity codes mpl e Character ASCII Odd-Parity ASCII Even-Parity ASCII 0110000 10110000 00110000 X 1011000 01011000 11011000 = 0111100 10111100 00111100 Binary Data Storage • Binary cells store individual bits of data • Multiple cells form a register • Data in registers can indicate different values • Hex (decimal) • BCD • ASCII Binary Cell 1 1 Register Transfer ° Data can move from register to register ° Digital logic used to process data ° We will learn to design this logic Register A Register B Digital Logic Circuits Register C Transfer of Information ° Data input at keyboard ° Shifted into place ° Stored in memory NOTE: Data input in ASCII Building a Computer ° We need processing ° We need storage ° We need communication ° You will learn to use and design these components Summary ° 2’s complement most important (only representation for zero) ° Important to understand treatment of sign bit for 1’s and 2’s complement ° Although 2’s complement most important, other number codes exist ° ASCII code used to represent characters (including those on the keyboard) ° Registers store binary data ... er Rep -2 n-1