Lecture Digital logic design - Lecture 10: Circuit analysis procedure

The main contents of the chapter consist of the following: Hazards, glitches, important concept – analyze digital circuits, given a circuit, create a truth table, create a minimized circuit, approaches, boolean expression approach, truth table approach, leads to minimized hardware, provides insights on how to design hardware.

Lecture 10 Circuit Analysis Procedure Overvie w ° Hazards • Glitches ° Important concept – analyze digital circuits • Given a circuit - Create a truth table - Create a minimized circuit ° Approaches • Boolean expression approach • Truth table approach ° Leads to minimized hardware ° Provides insights on how to design hardware Gate Delays ° When the input to a logic gate is changed, the output will not change immediately ° The switching elements within a gate take a finite time to react to a change (transition) in input ° As a result the change in the gate output is delayed w.r.t to the input change ° Such delay is called the propagation delay of the logic gate (tp) ° The propagation delay for a to output change (tpLH) may be different than the delay for a to change (tpHL) Gat e Del ays (co nt’d ) Digital signal: Important Terms (timing) ° Gate delay — time for change at input to cause change at output • delay – typical/nominal delay – max delay • careful designers design for both worst case and best case ° Rise time — time for output to transition from low to high voltage ° Fall time — time for output to transition from high to low voltage ° Pulse width — time that an output stays high or stays low between changes Effect of gate delays ° The analysis of combinational circuits ignoring delays can predict only the steady-state behavior of a circuits That is they predict a circuit’s output as a function of its inputs under the assumption that the inputs have been stable for a long time, relative to the delays into the circuit’s electronics ° Because of circuit delays, the transient behavior of a combinational logic circuit may differ from what is predicted by a steady-state analysis ° In particular a circuit’s output may produce a short pulse (often called a glitch) at a time when steady state analysis predicts that the output should not change Hazards and Glitches ° A glitch is an unwanted pulse at the output of a combinational logic network – a momentary change in an output that should not have changed ° A circuit with the potential for a glitch is said to have a hazard ° In other words a hazard is something intrinsic about a circuit; a circuit with hazard may or may not have a glitch depending on input patterns and the electric characteristics of the circuit When circuits have hazards ? ° Hazards are potential unwanted transients that occur in the output when different paths from input to output have different propagation delays Circuit Analysis   Analyze a logic circuit to determine its behavior For a two-level circuit, the analysis process is simple Boolean expression can often be written by inspection  For multi-level circuits, the process is more complex Cannot write a Boolean expression by inspection Must follow a procedure to implement the analysis Relationship Among Representations Any Boolean function that can be expressed as a truth table can be written as an expression in Boolean Algebra using AND, OR, NOT ? not u n iq u e B o o le a n E x p r e s s io n [ c o n v e n ie n t f o r   m a n ip u la tio n ] u n iq u e T r u th T a b le ? g a te r e p r e s e n ta tio n (s c h e m a tic ) not u n iq u e [ c lo s e  to im p le m e n ta to n ] How we convert from one to the other? Logic circuits ° Logic circuits for digital systems may be combinational or sequential ° Combinational circuit consists of logic gates whose outputs at any time are determined directly from the present combination of inputs without regard to previous inputs ° Combinational circuit performs a specific information-processing operation fully specified logically by a set of Boolean functions 10 Approach 2: Truth Table  Step 3: Determine outputs for function R + T = Out A B C A R S A 0 0 1 1 T B 0 1 0 1 C 1 1 R 0 0 0 S 0 1 1 1 T 0 1 Out 0 1 1 Out B C’ 25 Circuit Analysis More Difficult Example  Note labels on interior nodes  Multiple inputs (3) Multi-output (2) 26 To obtain FI as a function of A, B and C we form a series of substitutions as follows: 27 More Difficult Example: Truth Table  Remember to determine intermediate variables starting from the inputs  When all inputs determined for a gate, determine output  The truth table can be reduced using K-maps A 0 0 1 1 B 0 1 0 1 C 1 1 F2 0 1 1 F’2 1 1 0 T1 1 1 1 T2 0 0 0 T3 1 0 F1 1 0 28 29 Ana lysi s ° Boolean Expression Approach Pro A ced B ure C A B C ABC A+B+C AB'C'+A'BC'+A'B'C A B (A’+B’)(A’+C’)(B’+C’) A C B C F1 F2 AB+AC+BC F1=AB'C'+A'BC'+A'B'C+ABC F2=AB+AC+BC 30 Ana lysi s ° Truth Table Approach Pro A =ced 0 B= C =ure A= B= C= 0 A= B= 0 A C= =0 B C= =0 F1 F2 A  B  C 0   0   0 0        0 F1 0 F2 31 Ana lysi s ° Truth Table Approach Pro A =ced 0 B= C =ure A= B= C= 1 A= B= 0 A C= =1 B C= =1 F1 F1 F2 A  B  C 0   0   0 0 0   0   1 1        0 1 0 F2 32 Ana lysi s ° Truth Table Approach Pro A =ced 0 B= C =ure A= B= C= A= B= A C= =0 B C= =0 F1 F1 F2 A  B  C 0   0   0 0 0   0   1 0   1   0 1        0 1 0 F2 33 Ana lysi s ° Truth Table Approach Pro A =ced 0 B= C =ure A= B= C= 1 A= B= A C= =1 B C= =1 F1 F1 F2 A  B  C 0   0   0 0 0   0   1 0   1   0 0   1   1 0        1 0 F2 34 Ana lysi s ° Truth Table Approach Pro A =ced B= C =ure A= B= C= A= B= 0 A C= =0 B C= =0 F1 1 0 F1 F2 A  B  C 0   0   0 0 0   0   1 0   1   0 0   1   1 1   0   0 1        0 F2 35 Ana lysi s ° Truth Table Approach Pro A =ced B= C =ure A= B= C= 1 A= B= 0 A C= =1 B C= =1 F1 0 1 F1 F2 A  B  C 0   0   0 0 0   0   1 0   1   0 0   1   1 1   0   0 1   0   1 0        1 F2 36 Ana lysi s ° Truth Table Approach Pro A =ced B= C =ure A= B= C= A= B= 1 A C= =0 B C= =0 F1 0 F1 F2 A  B  C 0   0   0 0 0   0   1 0   1   0 0   1   1 1   0   0 1   0   1 1   1   0 0        1 F2 37 Ana lysi s ° Truth Table Approach Pro A =ced 1 B= C =ure A= B= C= 1 A= B= 1 A C= =1 B C= =1 F1 0 1 F2 F1 F2 A  B  C 0   0   0 0 0   0   1 0   1   0 0   1   1 1   0   0 1   0   1 1   1   0 1   1   1 1        1 B A 1 0 B C F1=AB'C'+A'BC'+A'B'C+ABC A 0 1 1 C F2=AB+AC+BC 38 Summary ° Important to be able to convert circuits into truth table and equation form • WHY? leads to minimized sum of product representation ° Two approaches illustrated • Approach 1: Create an equation with circuit output dependent on circuit inputs • Approach 2: Create a truth table which shows relationship between circuit inputs and circuit outputs ° Both results can then be minimized using K-maps ° Next time: develop a minimized SOP representation from a high level description 39 ... the circuit s electronics ° Because of circuit delays, the transient behavior of a combinational logic circuit may differ from what is predicted by a steady-state analysis ° In particular a circuit s...  Analyze a logic circuit to determine its behavior For a two-level circuit, the analysis process is simple Boolean expression can often be written by inspection  For multi-level circuits, the... we convert from one to the other? Logic circuits ° Logic circuits for digital systems may be combinational or sequential ° Combinational circuit consists of logic gates whose outputs at any time