The following will be discussed in this chapter: Datapaths must deal with input and output data values, necessary to control external interfaces, some datapaths require decision making, moving towards software, understanding the data and control path.
Lecture 32 Datapath Analysis Overvie w ° Datapaths must deal with input and output data values • Implement with tri-state buffers ° Necessary to control external interfaces • Perform repetitive operations ° Some datapaths require decision making • Control outputs implemented in ROM ° Moving towards software • Control implemented as a series of instructions ° Understanding the data and control path Datapath I/O ° A wire can be driven by only one tri-state at a time • If InPass is active, AluPass must be inactive • If AluPass is active, InPass must be inactive InPass LoadX Function OutPass X Y ALU LoadY AluPass Datapath I/O ° Two values enter from the left (A and B) • Need to perform (A+B)+A • In -> X (Load A) • In -> Y (Load B) • A+B -> Y • (A+B)+A -> Out Four steps and then repeat InPass OutPass Out In LoadX Function X Y ALU LoadY AluPass Implementing the Control ROM ° Two values enter from the left (A and B) • Need to perform (A+B)+A • In -> X (Load A) - State 00 • In -> Y (Load B) - State 01 • A+B -> Y - State 10 • (A+B)+A -> Out - State 11 ROM 0100010100 1000001100 1101101010 Addr 0001100011 PS 00 01 10 11 NS Control outputs PS NS Function 00 01 10 11 01 10 11 00 000 000 011 011 LoadX LoadY InPass AluPass OutPass 0 0 1 1 0 0 1 0 More Complicated Example ° Can we compute (A+B) (A-B)? ° Currently, no place for intermediate storage ° Solution: Add RAM to datapath InPass LoadX Function OutPass Y X ALU LoadY AluPass More Complicated Example ° Can we compute (A+B) (A-B)? • ° Need to add intermediate storage Typical sizes (1MB – 2GB) LoadX Function RAM Addr Read Write InPass OutPass Y X ALU Add RAM to the Datapath LoadY AluPass S 00 01 10 11 00 01 Implementing the Control ROM ° Two values enter from the left (A and B) • Need to perform (A+B) (A-B) • In -> X (Load A) - State 000 • In -> Y (Load B) - State 001 • A+B -> RAM[4] - State 010 • A-B -> X - State 011 • RAM[4] ->Y - State 100 • (A+B) (A-B) ->Out - State 101 NS 001 010 011 100 101 000 Function 000 000 011 010 000 110 LoadX LoadY InPass AluPass OutPass Addr Read Write 0 0 0 1 0 0 0 1 0 0 000 000 100 000 100 000 0 0 0 0 Does the Value of the Data Matter? ° Problem: Add A to itself until overflow occurs • Amount of steps depends on A Addr Read Write InPass LoadX RAM OutPass Y X LoadY OF Function ALU How can we determine if overflow occurred? AluPass ° Implementing the Control ROM using Conditions One value enters from the left Add A to itself until overflow occurs • In -> X, Y (Load A, B) - State - Next state • X+Y -> Out, X - State - Next state (1 if no overflow, if overflow) Include overflow (OF) bit as a ROM input Note that it doubles the size of the ROM PS OF NS 1 1 Function 000 000 011 011 LoadX LoadY InPass AluPass OutPass Addr Read Write 1 1 1 0 1 0 0 1 0 1 000 000 000 000 0 0 0 0 Bits in the ROM Each row indicates a ROM word 10 Counters ° Counter: A register that goes through a prescribed series of states ° Binary counter • Counter that follows a binary sequence • N bit binary counter counts in binary from n to 2n-1 ° Ripple counters triggered by initial Count signal ° Applications: • Watches • Clocks • Alarms • Web browser refresh 32 33 Timing Analysis ° Circuits not respond instantaneously to input changes ° Predictable delay in transferring inputs to outputs • Propagation delay ° Sequential circuits require a periodic clock ° Goal: analyze clock circuit to determine maximum clock frequency • Requires analysis of paths from flip-flop outputs to flip-flop inputs ° Even after inputs change, output signal of circuit maintains original output for short time 34 Timing Analysis ° Maximum clock frequency is a fundamental parameter in sequential computer systems ° Possible to determined clock frequency from propagation delays and setup time ° The longest path determines the clock frequenct ° All flip-flop to flip-flop paths must be checked ° Hold time are satisfied by examining contamination delays ° The shortest contamination delay path determines if hold times are met ° Check handout for more details and examples 35 36 RAM ° Memory is a collection of storage cells with associated input and output circuitry • Possible to read and write cells ° Random access memory (RAM) contains words of information ° Data accessed using a sequence of signals • Leads to timing waveforms ° Decoders are an important part of memories • Selects specific data in the RAM ° Static RAM loses values when circuit power is removed 37 38 Read-Only Memory (ROM) ° Read-only memory can normally only be read ° Internal organization similar to SRAM ° ROMs are effective at implementing truth tables • Any logic function can be implemented using ROMs ° Multiple single-bit functions embedded in a single ROM ° Also used in computer systems for initialization • ROM doesn’t lose storage value when power is removed ° Very useful for implementing FSMs 39 Rea d- of semiconductor devices ° An array Onl • diodes y • transistors Me • field effect transistors mor y ° 2N words by M bits (RO ° DataM) can be read but not changed • (normal operating conditions) Data is written to the ROM once, and read from the ROM many times A read-only memory (ROM) consists of an array of semiconductor devices that are interconnected to store a set of binary data Once binary data is stored in the ROM, it can be read out whenever desired, but the data that is stored cannot be changed under normal operating conditions 40 ROM ° ROMs are actually combinational devices, not sequential ones! • You can’t store arbitrary data into a ROM, so the same address will always contain the same data • You can think of a ROM as a combinational circuit that takes an address as input, and produces some data as the output ° A ROM table is basically just a truth table • The table shows what data is stored at each ROM address • You can generate that data combinationally, using the address as the input Add r e s s A A 1A 000 001 10 11 10 10 110 111 Dat a V V1V 000 10 110 10 10 000 11 11 41 42 Programmable Logic Array ° A ROM is potentially inefficient because it uses a decoder, which generates all possible minterms No circuit minimization is done ° Using a ROM to implement an n-input function requires: • An n-to-2n decoder, with n inverters and 2n n-input AND gates • An OR gate with up to 2n inputs • The number of gates roughly doubles for each additional ROM input ° A programmable logic array, or PLA, makes the decoder part of the ROM “programmable” too Instead of generating all minterms, you can choose which products (not necessarily minterms) to generate 43 44 ALU ° Main computation unit in most computer systems ° ALUs perform a variety of different functions • Add, subtract, OR, AND… ° Example: ALU chip (74LS382) • Has data and control inputs ° Individual chips can be chained together to make larger ALUs ° ALUs are important parts of datapaths • ROMs often are used in the control path ° Build a data and control path 45 Circuit Maker Simulator ° Circuit Implementation using Computer ° Circuit Analysis ° Rich Library ° Can Add your own component but need professional version ° Student Version have certain limitations 46 ... X (Load A) - State 000 • In -> Y (Load B) - State 001 • A+B -> RAM[4] - State 010 • A-B -> X - State 011 • RAM[4] -> Y - State 100 • (A+B) (A-B) -> Out - State 101 NS 001 010 011 100 101 000 Function... the left (A and B) • Need to perform (A+B)+A • In -> X (Load A) - State 00 • In -> Y (Load B) - State 01 • A+B -> Y - State 10 • (A+B)+A -> Out - State 11 ROM 0100010100 1000001100 1101101010 Addr... enters from the left Add A to itself until overflow occurs • In -> X, Y (Load A, B) - State - Next state • X+Y -> Out, X - State - Next state (1 if no overflow, if overflow) Include overflow (OF)