Lecture Digital logic design - Lecture 20: Sequential circuits: Latches

The following will be discussed in this chapter: Circuits require memory to store intermediate data; sequential circuits use a periodic signal to determine when to store values; single bit storage element is a flip flop; a basic type of flip flop is a latch; latches are made from logic gates.

0 Avoid 1 (set) 20 Characteristic Table ° In order to remember previous inputs, sequential circuits must have some sort of storage element This storage element is called “flip-flop” ° Flip-flop depends on previous inputs to the circuit ° The basic memory unit is called an SR flip-flop ° We can describe flip-flops using characteristic table SR Flip-Flop operation (BUILT WITH NOR GATES) Characteristic table Excitation table S R Action 0 1 Q(t) Q(t+1) S R Action Keep state 0 X No change Q=0 1 reset Q=1 0 set Unstable combinati on 1 X race conditio 21 Review: Steering Gates ° The flow of logic can be controlled with a logic gate Signal 10 °°10 Control The NAND as a steering gate inverts the input 22 Steering Gates ° A control input ‘0’ inhibits the signal 01 Signal °°10 Control 23 Steering Gates Signal 01 Control °°10 Signal °°10 Output Enabled (inverted) 24 Steering Gates Signal 10 Control °°10 Signal 101 °°10 Output Disabled 25 An SR latch with a control input ° Here is an SR latch with a control input C C S R S’ R’ Q 1 1 x 0 1 x 1 1 0 1 No  c h ang e No  c h ang e  ( r e s e t ) 1 ( s e t ) A vo id ! ° Notice the hierarchical design! • The dotted blue box is the S’R’ latch from the previous slide • The additional NAND gates are simply used to generate the correct inputs for the S’R’ latch ° The control input acts just like an enable 26 S-R Latch with NANDs S R Q   S    R    Q     Q’ Q’ 0 1 1 1 0 1 1 Disallowed Set Reset Store ° Latch made from cross-coupled NANDs ° Sometimes called S’-R’ latch ° Usually S=1 and R=1 ° S=0 and R=0 generates unpredictable results 27 S-R Latches 28 S-R Latch with control input ° Occasionally, desirable to avoid latch changes ° C = disables all latch state changes ° Control signal enables data change when C = ° Right side of circuit same as ordinary S-R latch 29 ... change when C = ° Right side of circuit same as ordinary S-R latch 29 NOR S-R Latch with Control Input Latch Latch is is level-sensitive level-sensitive,, in in regards regards to to C C Only stores... after data input has been removed ° S-R latches operate like cross-coupled inverters with control inputs (S = set, R = reset) ° With additional gates, an S-R latch can be converted to a D latch... just like an enable 26 S-R Latch with NANDs S R Q   S    R    Q     Q’ Q’ 0 1 1 1 0 1 1 Disallowed Set Reset Store ° Latch made from cross-coupled NANDs ° Sometimes called S’-R’ latch ° Usually S=1