ADAU Audio Codecs from analog device

Quad ADC with Diagnostics ADAU1977 Data Sheet FEATURES GENERAL DESCRIPTION Programmable microphone bias (5 V to V) with diagnostics Four 10 V rms capable direct-coupled differential inputs On-chip PLL for master clock Low EMI design 109 dB ADC dynamic range −95 dB THD + N Selectable digital high-pass filter 24-bit ADC with kHz to 192 kHz sample rates Digital volume control with autoramp function I2C/SPI control Software-controllable clickless mute Software power-down Right justified, left justified, I2S justified, and TDM modes Master and slave operation modes 40-lead LFCSP package Qualified for automotive applications The ADAU1977 incorporates four high performance analog-todigital converters (ADCs) with direct-coupled inputs capable of 10 V rms The ADC uses multibit sigma-delta (Σ-Δ) architecture with continuous time front end for low EMI The ADCs can be connected to the electret microphone (ECM) directly and provide the bias for powering the microphone Built-in diagnostic circuitry detects faults on input lines and includes comprehensive diagnostics for faults on microphone inputs The faults reported are short to battery, short to microphone bias, short to ground, short between positive and negative input pins, and open input terminals In addition, each diagnostic fault is available as an IRQ flag for ease in system design An I2C/SPI control port is also included The ADAU1977 uses only a single 3.3 V supply The part internally generates the microphone bias voltage The microphone bias is programmable in a few steps from V to V The low power architecture reduces the power consumption An on-chip PLL can derive the master clock from an external clock input or frame clock (sample rate clock) When fed with a frame clock, the PLL eliminates the need for a separate high frequency master clock in the system The ADAU1977 is available in a 40-lead LFCSP package APPLICATIONS Automotive audio systems Active noise cancellation system AVDD2 AVDD3 AVDD1 VBAT SW VBOOST_IN VBOOST_OUT FUNCTIONAL BLOCK DIAGRAM ADAU1977 BOOST CONVERTER IOUT 50mA PGND PROGRAMMABLE GAIN DECIMATOR/HPF DC CALIBRATION ATTENUATOR 14dB AIN1P AIN1N AIN2P AIN2N AIN3P AIN3N AIN4P ADC ADC ADC ADC AIN4N AGND1 VBAT AVDDx AGND3 AVDD2 BG REF DIAGNOSTICS I2C/SPI CONTROL PLL AGND2 SA_MODE PLL_FILT MCLKIN VREF DGND AGND3 AGND2 PGND LRCLK BCLK SDATAOUT1 SDATAOUT2 SCL/CCLK SDA/COUT ADDR1/CIN ADDR0/CLATCH FAULT PD/RST AGND2 AGNDx AGND1 IOVDD 10296-001 PROG BIAS DVDD AVDD1 AVDD3 MICBIAS MB_GND 3.3V TO 1.8V REGULATOR SERIAL AUDIO PORT 5V TO 9V Figure Rev C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use Specifications subject to change without notice No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective owners One Technology Way, P.O Box 9106, Norwood, MA 02062-9106, U.S.A Tel: 781.329.4700 ©2013–2014 Analog Devices, Inc All rights reserved Technical Support www.analog.com ADAU1977* Product Page Quick Links Last Content Update: 08/30/2016 Comparable Parts Tools and Simulations View a parametric search of comparable parts • ADAU1977 IBIS Model Evaluation Kits Design Resources • ADAU1977/ADAU1978/ADAU1979 Evaluation Board • ADSP-SC584 Evaluation Hardware for the ADSP-SC58x/ ADSP-2158x SHARC Family (349-ball CSPBGA) • ADUSB2EBZ Evaluation Board • • • • Documentation Discussions Data Sheet • ADAU1977: Quad ADC with Diagnostics Data Sheet User Guides • UG-600: Evaluating the ADAU1977/ADAU1978/ ADAU1979 View all ADAU1977 EngineerZone Discussions Software and Systems Requirements • ADAU1977 Sound CODEC Linux Driver ADAU1977 Material Declaration PCN-PDN Information Quality And Reliability Symbols and Footprints Sample and Buy Visit the product page to see pricing options Technical Support Submit a technical question or find your regional support number * This page was dynamically generated by Analog Devices, Inc and inserted into this data sheet Note: Dynamic changes to the content on this page does not constitute a change to the revision number of the product data sheet This content may be frequently modified ADAU1977 Data Sheet TABLE OF CONTENTS Features Register Details 37 Applications Master Power and Soft Reset Register 37 General Description PLL Control Register 38 Functional Block Diagram DC-to-DC Boost Converter Control Register 39 Revision History MICBIAS and Boost Control Register 40 Specifications Block Power Control and Serial Port Control Register 41 Analog Performance Specifications Serial Port Control Register1 42 Diagnostic and Fault Specifications Serial Port Control Register2 43 Digital Input/Output Specifications Channel Mapping for Output Serial Ports Register 44 Power Supply Specifications Channel Mapping for Output Serial Ports Register 46 Digital Filters Specifications Timing Specifications Serial Output Drive and Overtemperature Protection Control Register 48 Absolute Maximum Ratings 10 Post ADC Gain Channel Control Register 49 Thermal Resistance 10 Post ADC Gain Channel Control Register 50 ESD Caution 10 Post ADC Gain Channel Control Register 51 Pin Configuration and Function Descriptions 11 Post ADC Gain Channel Control Register 52 Typical Performance Characteristics 13 High-Pass Filter and DC Offset Control Register and Master Mute 53 Theory of Operation 15 Overview 15 Power Supply and Voltage Reference 15 Power-On Reset Sequence 15 PLL and Clock 16 DC-to-DC Boost Converter 17 Microphone Bias 18 Analog Inputs 18 ADC 22 ADC Summing Modes 22 Diagnostics 23 Serial Audio Data Output Ports—Data Format 25 Control Ports 30 I2C Mode 31 SPI Mode 34 Register Summary 36 Diagnostics Control Register 54 Diagnostics Report Register Channel 55 Diagnostics Report Register Channel 56 Diagnostics Report Register Channel 57 Diagnostics Report Register Channel 58 Diagnostics Interrupt Pin Control Register 59 Diagnostics Interrupt Pin Control Register 60 Diagnostics Adjustments Register 61 Diagnostics Adjustments Register 62 ADC Clipping Status Register 63 Digital DC High-Pass Filter and Calibration Register 64 Applications Circuit 65 Outline Dimensions 66 Ordering Guide 66 Automotive Products 66 Rev C | Page of 68 Data Sheet ADAU1977 REVISION HISTORY 1/14—Rev B to Rev C 3/13—Rev to Rev A Change to Features Section Change to Dynamic Range (A-Weighted) Parameter, Table Change to Figure 13 Change to Figure 36 32 Change to Figure 46 65 Changed CP-40-9 to CP-40-14 Universal Changes to Hysteresis AINxP and AINxN Shorted Together Parameter, Table Changes to Thermal Resistance Section and Table Changes to SPI Mode Section 32 Changes to Channel Mapping for Output Serial Ports Register Section and Table 34 44 Changes to Figure 46 63 Changes to Ordering Guide 64 9/13—Rev A to Rev B Changes to Figure Moved Revision History Section Changes to Figure 14 16 Changes to Figure 46 65 1/13—Revision 0: Initial Version Rev C | Page of 68 ADAU1977 Data Sheet SPECIFICATIONS Performance of all channels is identical, exclusive of the interchannel gain mismatch and interchannel phase deviation specifications AVDDx/IOVDD = 3.3 V; DVDD (internally generated) = 1.8 V; VBAT = 14.4 V; TA = −40°C to +105°C, unless otherwise noted; master clock = 12.288 MHz (48 kHz fS, 256 × fS mode); input sample rate = 48 kHz; measurement bandwidth = 20 Hz to 20 kHz; word width = 24 bits; load capacitance (digital output) = 20 pF; load current (digital output) = ±1 mA; digital input voltage high = 2.0 V; digital input voltage low = 0.8 V ANALOG PERFORMANCE SPECIFICATIONS Table Parameter LINE INPUT APPLICATION Full-Scale Differential Input Voltage Full-Scale Single-Ended Input Voltage MICROPHONE INPUT APPLICATION Differential Input Voltage QUASI DC INPUT Single-Ended Input Voltage Input Common-Mode Voltage Peak Input Voltage MICROPHONE BIAS Output Voltage Load Regulation Output Current Output Noise Power Supply Rejection Ratio (PSRR) Interchannel Isolation at MICBIAS Pin Start-Up Time BOOST CONVERTER Input Voltage Input Current Output Current Load Regulation Input Overcurrent Threshold Switching Frequency External Load Capacitor at VBOOST_OUT Pin ANALOG-TO-DIGITAL CONVERTERS Input Resistance Differential Single-Ended (Rin1977) ADC Resolution Dynamic Range (A-Weighted) Line Input Microphone Input Total Harmonic Distortion Plus Noise (THD + N) Test Conditions/Comments See Figure 46 DC-coupled, VCM at AINxP/AINxN = V DC-coupled, VCM at AINxP/AINxN = V See Figure 46, MICBIAS = 8.5 V DC-coupled, VCM at AINxP = 5.66 V, AINxN = 2.83 V Min Typ Max VCM at AINxP/AINxN pins VCM + V ac peak at AINxP/AINxN pins 0 14 V peak V dc V Programmable from V to V in steps of 0.5 V; the output voltage is within the specified load regulation From no load to maximum load of 25 mA at V From no load to maximum load of 45 mA at V At MICBIAS = V At MICBIAS = V 20 Hz to 20 kHz, MICBIAS = V 20 Hz to 20 kHz, MICBIAS = V 350 mV rms, kHz ripple on VBOOST_IN at 10 V Referred to full scale at kHz With CLOAD = nF V +1 +1 25 45 32 54 % % mA mA µV rms µV rms dB dB ms 3.63 10 V rms V rms V rms −1 −1 −1 +1 V mA mA mA mA % −1 +1 % 22 mA peak MHz MHz µF fS = 48 kHz L = 2.2 µH fS = 48 kHz, L = 4.7 µH 4.7 Between AINxP and AINxN Between AINxP and AINxN Input = kHz, −60 dBFS Referred to full-scale differential input = 10 V rms Referred to full-scale differential input = V rms Input = kHz, −1 dBFS (0 dBFS = 10 V rms input) Rev C | Page of 68 +0.2 +0.3 22 35 60 60 40 2.97 L = 4.7 µH, fSW = 1.536 MHz, MICBIAS = V at 45 mA load L = 2.2 µH, fSW = 3.072 MHz, MICBIAS = V at 45 mA load MICBIAS = V MICBIAS = V From no load to maximum load of 50 mA at MICBIAS =5V From no load to maximum load of 88 mA at MICBIAS =9V Unit 103 3.3 195 220 50 88 900 3.072 1.536 10 50 25 24 kΩ kΩ Bits 109 95 −95 dB dB dB −89 Data Sheet Parameter Digital Gain Post ADC Gain Error Interchannel Gain Mismatch Gain Drift Common-Mode Rejection Ratio (CMRR) Power Supply Rejection Ratio (PSRR) Interchannel Isolation Interchannel Phase Deviation REFERENCE Internal Reference Voltage Output Impedance ADC SERIAL PORT Output Sample Rate ADAU1977 Test Conditions/Comments Gain step size = 0.375 dB Min −35.625 −10 −0.25 Typ Max +60 +10 +0.25 Unit dB % dB ppm/°C dB dB dB dB Degrees 1.54 V kΩ 192 kHz 0.6 60 56 70 100 V rms, kHz V rms, 20 kHz 100 mV rms, kHz on AVDDx = 3.3 V VREF pin 1.47 1.50 20 For fS ranging from 44.1 kHz to 192 kHz DIAGNOSTIC AND FAULT SPECIFICATIONS Applicable to differential microphone input using MICBIAS on AINxP and AINxN pins Table Parameter INPUT VOLTAGE THRESHOLDS FOR FAULT DETECTION1 Hysteresis AINxP or AINxN Shorted to VBAT Hysteresis AINxP and AINxN Shorted Together Hysteresis AINxP or AINxN Shorted to Ground Hysteresis AINxP Shorted to MICBIAS Hysteresis AINxP or AINxN Open Circuit FAULT DURATION Test Conditions/ Comments Min Typ Max Unit SHT_B_TRIP = 10 SHT_B_TRIP = 01 SHT_B_TRIP = 00 SHT_B_TRIP = 11 SHT_T_TRIP = 00 0.79 × VBAT 0.84 × VBAT 0.89 × VBAT 0.93 × VBAT MICBIAS(0.5 ± 0.015) MICBIAS(0.5 ± 0.001) SHT_T_TRIP = 10 MICBIAS(0.5 ± 0.05) SHT_G_TRIP = 10 SHT_G_TRIP = 01 SHT_G_TRIP = 00 SHT_G_TRIP = 11 SHT_M_TRIP = 10 SHT_M_TRIP = 01 SHT_M_TRIP = 00 SHT_M_TRIP = 11 Refer to the AINxP shorted to MICBIAS and the AINxN shorted to ground specifications for upper and lower thresholds Programmable 0.04 × VREF 0.08 × VREF 0.12 × VREF 0.19 × VREF 0.82 × MICBIAS 0.87 × MICBIAS 0.92 × MICBIAS 0.95 × MICBIAS 0.86 × VBAT 0.91 × VBAT 0.96 × VBAT 0.99 × VBAT MICBIAS(0.5 ± 0.047) MICBIAS(0.5 ± 0.03) MICBIAS(0.5 ± 0.08) 0.13 × VREF 0.16 × VREF 0.22 × VREF 0.28 × VREF 0.89 × MICBIAS 0.94 × MICBIAS 1.0 × MICBIAS 1.0 × MICBIAS V V V V V SHT_T_TRIP = 01 0.85 × VBAT 0.9 × VBAT 0.95 × VBAT 0.975 × VBAT MICBIAS(0.5 ± 0.035) MICBIAS(0.5 ± 0.017) MICBIAS(0.5 ± 0.071) 0.1 × VREF 0.133 × VREF 0.2 × VREF 0.266 × VREF 0.85 × MICBIAS 0.9 × MICBIAS 0.95 × MICBIAS 0.975 × MICBIAS 10 100 150 ms V V V V V V V V V V The threshold limits are tested with VREF = 1.5 V, MICBIAS = V to 8.5 V, and VBAT = 11 V to 18 V set using an external source When VBAT ≤ MICBIAS, a short to VBAT cannot be distinguished from a short to MICBIAS, and reporting a short to VBAT fault takes precedence over a short to MICBIAS fault The AINxP open terminal fault cannot be distinguished from the AINxN open terminal fault because the voltage at the AINxP and AINxN pins remain at MICBIAS and ground, respectively, when either of these two terminals becomes open circuit Rev C | Page of 68 ADAU1977 Data Sheet DIGITAL INPUT/OUTPUT SPECIFICATIONS Table Parameter INPUT High Level Input Voltage (VIH) Low Level Input Voltage (VIL) Input Leakage Current Input Capacitance OUTPUT High Level Output Voltage (VOH) Low Level Output Voltage (VOL) Test Conditions/Comments Min Max Unit 0.3 × IOVDD ±10 V V µA pF 0.4 V V 0.7 × IOVDD IOH = mA IOL = mA IOVDD − 0.60 POWER SUPPLY SPECIFICATIONS L = 4.7 µH, AVDDx = 3.3 V, DVDD = 1.8 V, IOVDD = 3.3 V, fS = 48 kHz (master mode), unless otherwise noted Table Parameter DVDD AVDDx IOVDD VBAT IOVDD Current Normal Operation Power-Down AVDDx Current Normal Operation Power-Down Boost Converter Current Normal Operation Power-Down DVDD Current Normal Operation Power-Down VBAT Current Normal Operation Power-Down POWER DISSIPATION Normal Operation AVDDx Power-Down, All Supplies Test Conditions/Comments On-chip LDO Master clock = 256 fS fS = 48 kHz fS = 96 kHz fS = 192 kHz fS = 48 kHz to 192 kHz Min 1.62 3.0 1.62 Typ 1.8 3.3 3.3 14.4 Max 1.98 3.6 3.6 18 Unit V V V V 450 880 1.75 20 µA µA mA µA Boost off, 4-channel ADC, DVDD internal Boost on, 4-channel ADC, DVDD internal Boost off, 4-channel ADC, DVDD external Boost on, 4-channel ADC, DVDD external 14 14.5 9.6 10.1 270 mA mA mA mA µA Boost on, 4-channel ADC, MICBIAS = 8.5 V, no load Boost on, 4-channel ADC, MICBIAS = 8.5 V, 42 mA 34 168 180 mA mA µA DVDD external = 1.8 V 4.5 65 mA µA VBAT = 14.4 V 575 575 Master clock = 256 fS, 48 kHz DVDD internal, MICBIAS = 8.5 V at 42 mA load PD/RST pin held low 265 625 625 µA µA mW mW When VBAT ≤ MICBIAS, a short to VBAT cannot be distinguished from a short to MICBIAS, and reporting a short to VBAT fault takes precedence over a short to MICBIAS fault Rev C | Page of 68 Data Sheet ADAU1977 DIGITAL FILTERS SPECIFICATIONS Table Parameter ADC DECIMATION FILTER Pass Band Pass-Band Ripple Transition Band Stop Band Stop-Band Attenuation Group Delay HIGH-PASS FILTER Cutoff Frequency Phase Deviation Settling Time ADC DIGITAL GAIN Gain Step Size Mode All modes, typical at fS = 48 kHz Factor Min 0.4375 × fS Typ Max 21 ±0.015 24 27 0.5 × fS 0.5625 × fS 479 35 kHz dB kHz kHz dB µs µs 0.9375 10 Hz Degrees 79 fS = kHz to 96 kHz fS = 192 kHz All modes, typical at 48 kHz At −3 dB point At 20 Hz All modes 22.9844/fS 60 0.375 Rev C | Page of 68 Unit dB dB ADAU1977 Data Sheet TIMING SPECIFICATIONS Table Parameter INPUT MASTER CLOCK (MCLK) Duty Cycle fMCLK RESET Reset Pulse PLL Lock Time I2C PORT fSCL tSCLH tSCLL tSCS tSCH tDS tDH tSCR tSCF tSDR tSDF tBFT tSUSTO SPI PORT tCCPH tCCPL fCCLK tCDS tCDH tCLS tCLH tCLPH tCOE tCOD tCOTS ADC SERIAL PORT tABH tABL tALS tALH tABDD Limit at Min Max Unit Description 40 60 See Table 10 % MHz MCLKIN duty cycle; MCLKIN at 256 × fS, 384 × fS, 512 × fS, and 768 × fS MCLKIN frequency, PLL in MCLK mode 15 ns RST low 10 ms 400 kHz µs µs µs µs ns 300 300 300 300 ns ns ns ns µs µs SCL frequency SCL high SCL low Setup time; relevant for repeated start condition Hold time; after this period of time, the first clock pulse is generated Data setup time Data hold time SCL rise time SCL fall time SDA rise time SDA fall time Bus-free time; time between stop and start Setup time for stop condition 30 30 30 ns ns MHz ns ns ns ns ns ns ns ns CCLK high CCLK low CCLK frequency CIN setup to CCLK rising CIN hold from CCLK rising CLATCH setup to CCLK rising CLATCH hold from CCLK rising CLATCH high COUT enable from CLATCH falling COUT delay from CCLK falling COUT tristate from CLATCH rising 18 ns ns ns ns ns BCLK high, slave mode BCLK low, slave mode LRCLK setup to BCLK rising, slave mode LRCLK hold from BCLK rising, slave mode SDATAOUTx delay from BCLK falling 0.6 1.3 0.6 0.6 100 1.3 0.6 35 35 10 10 10 10 40 10 10 10 10 Rev C | Page of 68 Data Sheet ADAU1977 tALS LRCLK tALH tABH BCLK tABL SDATAOUTx LEFT JUSTIFIED MODE tABDD MSB MSB – tABDD SDATAOUTx I2S MODE MSB tABDD SDATAOUTx RIGHT JUSTIFIED MODE LSB MSB 8-BIT CLOCKS (24-BIT DATA) 12-BIT CLOCKS (20-BIT DATA) 10296-002 14-BIT CLOCKS (18-BIT DATA) 16-BIT CLOCKS (16-BIT DATA) Figure Serial Output Port Timing tCLH tCLS tCOE tCLPH tCCPL tCCPH CLATCH CCLK CIN tCDH tCDS 10296-003 tCOTS COUT tCOD Figure SPI Port Timing tSCH tDS tSDR STOP tSCH START SDA tSDF tSCLH tBFT tSCR tSCLL tDH tSCF tSCS Figure I2C Port Timing Rev C | Page of 68 tSUSTO 10296-004 SCL ADAU1977 Data Sheet DIAGNOSTICS CONTROL REGISTER Address: 0x10, Reset: 0x0F, Name: DIAG_CONTROL Table 41 Bit Descriptions for DIAG_CONTROL Bits [7:4] Bit Name RESERVED DIAG_EN4 Settings DIAG_EN3 1 DIAG_EN2 DIAG_EN1 Description Reserved Diagnostics Enable Channel Diagnostics Disabled Diagnostics Enabled Diagnostics Enable Channel Diagnostics Disabled Diagnostics Enabled Diagnostics Enable Channel Diagnostics Disabled Diagnostics Enabled Diagnostics Enable Channel Diagnostics Disabled Diagnostics Enabled Rev C | Page 54 of 68 Reset 0x0 0x1 Access RW RW 0x1 RW 0x1 RW 0x1 RW Data Sheet ADAU1977 DIAGNOSTICS REPORT REGISTER CHANNEL Address: 0x11, Reset: 0x00, Name: DIAG_STATUS1 Table 42 Bit Descriptions for DIAG_STATUS1 Bits Bit Name RESERVED MIC_SHORT1 Settings MICH_OPEN1 MICH_SB1 MICH_SG1 MICH_SMB1 1 MICL_SB1 MICL_SG1 Description Reserved Mic Terminals Shorted Normal Operation Mic Terminals Shorted Mic Open Connection Normal Operation Mic Open Connection Mic High Shorted to Supply Normal Operation Mic High Shorted to Supply Mic High Shorted to Ground Normal Operation Mic High Shorted to Ground Mic High Shorted to MICBIAS Normal Operation Mic High Shorted to MICBIAS Mic Low Shorted to Supply Normal Operation Mic Low Shorted to Supply Mic Low Shorted to Ground Normal Operation Mic Low Shorted to Ground Rev C | Page 55 of 68 Reset 0x0 0x0 Access RW R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R ADAU1977 Data Sheet DIAGNOSTICS REPORT REGISTER CHANNEL Address: 0x12, Reset: 0x00, Name: DIAG_STATUS2 Table 43 Bit Descriptions for DIAG_STATUS2 Bits Bit Name RESERVED MIC_SHORT2 Settings MIC_OPEN2 MICH_SB2 MICH_SG2 MICH_SMB2 1 MICL_SB2 MICL_SG2 Description Reserved Mic Terminals Shorted Normal Operation Mic Terminals Shorted Mic Open Connection Normal Operation Mic Open Connection Mic High Shorted to Supply Normal Operation Mic High Shorted to Supply Mic High Shorted to Ground Normal Operation Mic High Shorted to Ground Mic High Shorted to MICBIAS Normal operation Mic High Shorted to MICBIAS Mic Low Shorted to Supply Normal Operation Mic Low Shorted to Supply Mic Low Shorted to Ground Normal Operation Mic Low Shorted to Ground Rev C | Page 56 of 68 Reset 0x0 0x0 Access RW R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R Data Sheet ADAU1977 DIAGNOSTICS REPORT REGISTER CHANNEL Address: 0x13, Reset: 0x00, Name: DIAG_STATUS3 Table 44 Bit Descriptions for DIAG_STATUS3 Bits Bit Name RESERVED MIC_SHORT3 Settings MIC_OPEN3 MICH_SB3 MICH_SG3 MICH_SMB3 1 MICL_SB3 MICL_SG3 Description Reserved Mic Terminals Shorted Normal Operation Mic Terminals Shorted Mic Open Connection Normal Operation Mic Open Connection Mic High Shorted to Supply Normal Operation Mic High Shorted to Supply Mic High Shorted to Ground Normal Operation Mic High Shorted to Ground Mic High Shorted to MICBIAS Normal Operation Mic High Shorted to MICBIAS Mic Low Shorted to Supply Normal Operation Mic Low Shorted to Supply Mic Low Shorted to Ground Normal Operation Mic Low Shorted to Ground Rev C | Page 57 of 68 Reset 0x0 0x0 Access RW R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R ADAU1977 Data Sheet DIAGNOSTICS REPORT REGISTER CHANNEL Address: 0x14, Reset: 0x00, Name: DIAG_STATUS4 Table 45 Bit Descriptions for DIAG_STATUS4 Bits Bit Name RESERVED MIC_SHORT4 Settings MIC_OPEN4 MICH_SB4 MICH_SG4 MICH_SMB4 1 MICL_SB4 MICL_SG4 Description Reserved Mic Terminals Shorted Normal Operation Mic Terminals Shorted Mic Open Connection Normal Operation Mic Open Connection Mic High Shorted to Supply Normal Operation Mic High Shorted to Supply Mic High Shorted to Ground Normal Operation Mic High Shorted to Ground Mic High Shorted to MICBIAS Normal Operation Mic High Shorted to MICBIAS Mic Low Shorted to Supply Normal Operation Mic Low Shorted to Supply Mic Low Shorted to Ground Normal Operation Mic Low Shorted to Ground Rev C | Page 58 of 68 Reset 0x0 0x0 Access RW R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R Data Sheet ADAU1977 DIAGNOSTICS INTERRUPT PIN CONTROL REGISTER Address: 0x15, Reset: 0x20, Name: DIAG_IRQ1 Table 46 Bit Descriptions for DIAG_IRQ1 Bits Bit Name RESERVED IRQ_RESET Settings IRQ_DRIVE IRQ_POL DIAG_MASK4 DIAG_MASK3 1 DIAG_MASK2 DIAG_MASK1 Description Reserved FAULT Pin Reset Normal Operation Reset FAULT Pin FAULT Pin Drive Options FAULT Pin Always Driven FAULT Pin Only Driven During Fault, Otherwise High-Z FAULT Pin Polarity Faults Set FAULT Pin Low Faults Set FAULT Pin High FAULT Pin Mask for All Channel Faults Faults on Channel Trigger FAULT Pin Faults on Channel Do Not Trigger FAULT Pin FAULT Pin Mask for All Channel Faults Faults on Channel Trigger FAULT Pin Faults on Channel Do Not Trigger FAULT Pin FAULT Pin Mask for All Channel Faults Faults on Channel Trigger FAULT Pin Faults on Channel Do Not Trigger FAULT Pin FAULT Pin Mask for All Channel Faults Faults on Channel Trigger FAULT Pin Faults on Channel Do Not Trigger FAULT Pin Rev C | Page 59 of 68 Reset 0x0 0x0 Access RW RW 0x1 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW ADAU1977 Data Sheet DIAGNOSTICS INTERRUPT PIN CONTROL REGISTER Address: 0x16, Reset: 0x00, Name: DIAG_IRQ2 Table 47 Bit Descriptions for DIAG_IRQ2 Bits Bit Name BST_FAULT_MASK Settings MIC_SHORT_MASK MIC_OPEN_MASK MICH_SB_MASK MICH_SG_MASK 1 MICL_SB_MASK MICL_SG_MASK Description FAULT Pin Mask for Boost Faults Boost Faults Assert FAULT Pin Boost Faults Do Not Assert FAULT Pin FAULT Pin Mask for Mic Terminal Short Fault Faults Trigger FAULT Pin Faults Do Not Trigger FAULT Pin FAULT Pin Mask for Mic Open Connection Fault Faults Trigger FAULT Pin Faults Do Not Trigger FAULT Pin FAULT Pin Mask for Mic High Short to Supply Fault Faults Trigger FAULT Pin Faults Do Not Trigger FAULT Pin FAULT Pin Mask for Mic High Short to Ground Fault Faults Trigger FAULT Pin Faults Do Not Trigger FAULT Pin FAULT Pin Mask for Mic Low Short to Supply Fault Faults Trigger FAULT Pin Faults Do Not Trigger FAULT Pin FAULT Pin Mask for Mic Low Short to Ground Fault Faults Trigger FAULT Pin Faults Do Not Trigger FAULT Pin Rev C | Page 60 of 68 Reset 0x0 Access RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW Data Sheet ADAU1977 DIAGNOSTICS ADJUSTMENTS REGISTER Address: 0x17, Reset: 0x00, Name: DIAG_ADJUST1 Table 48 Bit Descriptions for DIAG_ADJUST1 Bits [7:6] Bit Name SHT_T_TRIP Settings 00 01 10 11 [5:4] SHT_M_TRIP 00 01 10 11 [3:2] SHT_G_TRIP 00 01 10 11 [1:0] SHT_B_TRIP 00 01 10 11 Description Short Fault to Other Terminal Trip Point Adjust 0.465 × MICBIAS to 0.535 × MICBIAS 0.483 × MICBIAS to 0.517 × MICBIAS 0.429 × MICBIAS to 0.571 × MICBIAS Reserved Short Fault to Mic Bias Trip Point Adjust 0.95 × MICBIAS 0.9 × MICBIAS 0.85 × MICBIAS 0.975 × MICBIAS Short Fault to Ground Trip Point Adjust 0.2 × VREF 0.133 × VREF 0.1 × VREF 0.266 × VREF Short Fault to Supply/Battery Trip Point Adjust 0.95 × VBAT 0.9 × VBAT 0.85 × VBAT 0.975 × VBAT Rev C | Page 61 of 68 Reset 0x0 Access RW 0x0 RW 0x0 RW 0x0 RW ADAU1977 Data Sheet DIAGNOSTICS ADJUSTMENTS REGISTER Address: 0x18, Reset: 0x20, Name: DIAG_ADJUST2 Table 49 Bit Descriptions for DIAG_ADJUST2 Bits [7:6] [5:4] Bit Name RESERVED FAULT_TO Settings 00 01 10 11 RESERVED HYST_SM_EN 1 HYST_SG_EN HYST_SB_EN Description Reserved Fault Timeout Adjust No Fault Timeout Period (That Is, the Time That the Fault Needs to Persist Before Being Reported) 50 ms Fault Timeout Period 100 ms Fault Timeout Period (Default) 150 ms Fault Timeout Period Reserved Hysteresis Short to MICBIAS Enable Disable Enable Hysteresis Short to Ground Enable Disable Enable Hysteresis Short to Battery Enable Disable Enable Rev C | Page 62 of 68 Reset 0x0 0x2 Access RW RW 0x0 0x0 RW RW 0x0 RW 0x0 RW Data Sheet ADAU1977 ADC CLIPPING STATUS REGISTER Address: 0x19, Reset: 0x00, Name: ASDC_CLIP Table 50 Bit Descriptions for ASDC_CLIP Bits [7:4] Bit Name RESERVED ADC_CLIP4 Settings ADC_CLIP3 1 ADC_CLIP2 ADC_CLIP1 Description Reserved ADC Channel Clip Status Normal Operation ADC Channel Clipping ADC Channel Clip Status Normal Operation ADC Channel Clipping ADC Channel Clip Status Normal Operation ADC Channel Clipping ADC Channel Clip Status Normal Operation ADC Channel Clipping Rev C | Page 63 of 68 Reset 0x0 0x0 Access RW R 0x0 R 0x0 R 0x0 R ADAU1977 Data Sheet DIGITAL DC HIGH-PASS FILTER AND CALIBRATION REGISTER Address: 0x1A, Reset: 0x00, Name: DC_HPF_CAL Table 51 Bit Descriptions for DC_HPF_CAL Bits Bit Name DC_SUB_C4 Settings DC_SUB_C3 DC_SUB_C2 DC_SUB_C1 DC_HPF_C4 DC_HPF_C3 1 DC_HPF_C2 DC_HPF_C1 Description Channel DC Subtraction from Calibration No DC Subtraction DC Value from DC Calibration Is Subtracted Channel DC Subtraction from Calibration No DC Subtraction DC Value from DC Calibration Is Subtracted Channel DC Subtraction from Calibration No DC Subtraction DC Value from DC Calibration Is Subtracted Channel DC Subtraction from Calibration No DC Subtraction DC Value from DC Calibration Is Subtracted Channel DC High-Pass Filter Enable HPF Off HPF On Channel DC High-Pass Filter Enable HPF Off HPF On Channel DC High-Pass Filter Enable HPF Off HPF On Channel DC High-Pass Filter Enable HPF Off HPF On Rev C | Page 64 of 68 Reset 0x0 Access RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW Data Sheet ADAU1977 APPLICATIONS CIRCUIT +14.4V AVDDx AVDD2 DIAGNOSTICS C1 TO C8 = 1000pF R1 TO R4 TYP = 500Ω ±0.1% BG REF PLL AGND2 AGND2 PGND AGND1 AGND2 AGND3 DGND VREF AGNDx MB_GND C18 10µF C19 0.1µF I2C/SPI CONTROL PLL_FILT R4 MCLKIN C1 C2 C3 C4 C5 C6 C7 C8 R2 SCL/CCLK SDA/COUT ADDR1/CIN ADDR0/CLATCH FAULT PD/RESET R13 R16 IOVDD R15 AGND3 AGND1 TO DSP R11 ADC VBAT LRCLK BCLK SDATAOUT1 SDATAOUT2 R12 ADC C7 0.1µF R9 ADC REXT +1.8V OR +3.3V R10 ADC ATTENUATOR 14dB MIC1 VAC = 2V DIFF MIC2 VAC = 2V DIFF LINE1 VCM = 7V, VAC = 10V DIFF LINE2 VCM = 7V, VAC = 10V DIFF C16 10µF MLCC X7R C15 0.1µF IOVDD SERIAL AUDIO PORT 4.7µH SW PGND AIN1+ AIN1– AIN2+ AIN2– AIN3+ AIN3– AIN4+ AIN4– DVDD ADAU1977 PROGRAMMABLE GAIN DECIMATOR/HPF DC CALIBRATION PROG BIAS 3.3V TO 1.8V REGULATOR SA_MODE R3 C14 0.1µF BOOST CONVERTER IOUT 50mA 5V TO 9V C9 10µF ELECTROLYTIC 1nF MAX MLCC R1 C13 0.1µF AVDD1 AVDD3 MICBIAS VBOOST_IN C10 10µF MLCC X7R VBOOST_OUT C11 0.1µF 10µF MLCC X7R C12 0.1µF AVDD1 AVDD3 AVDD2 VBAT (LOAD DUMP SUPRESSED) +3.3V MICROCONTROLLER R14 C21 C20 R17 +3.3V (AVDD2) NOTES R9, R10 = TYPICAL 2kΩ R11 THROUGH R14 USED FOR SETTING THE DEVICE IN I 2C MODE R15, R16 = TYPICAL 47kΩ PLL LOOP FILTER: R17 C20 C21 LRCLK MCLK 4.87kΩ 2200pF 39nF 1kΩ 390pF 5600pF FOR MORE INFORMATIONABOUT CALCUL ATING THEVALUE OF REXT, SEE THE POWER-ON RESET SEQUENCE SECTION Figure 46 Typical Application Schematic—Two Microphones, Two Line Inputs, I2C and I2S Mode Rev C | Page 65 of 68 10296-046 PLL INPUT OPTION ADAU1977 Data Sheet OUTLINE DIMENSIONS 0.30 0.25 0.18 31 40 30 0.50 BSC TOP VIEW 0.80 0.75 0.70 10 11 20 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE 4.05 3.90 SQ 3.75 EXPOSED PAD 21 0.45 0.40 0.35 PIN INDICATOR BOTTOM VIEW 0.25 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET COMPLIANT TO JEDEC STANDARDS MO-220-WJJD 05-06-2011-A PIN INDICATOR 6.10 6.00 SQ 5.90 Figure 47 40-Lead Lead Frame Chip Scale Package [LFCSP_WQ] mm × mm Body, Very Very Thin Quad (CP-40-14) Dimensions shown in millimeters ORDERING GUIDE Model 1, ADAU1977WBCPZ ADAU1977WBCPZ-R7 ADAU1977WBCPZ-RL EVAL-ADAU1977Z Temperature Range –40°C to +105°C –40°C to +105°C –40°C to +105°C Package Description 40-Lead LFCSP_WQ 40-Lead LFCSP_WQ, 7” Tape and Reel 40-Lead LFCSP_WQ, 13” Tape and Reel Evaluation Board Package Option CP-40-14 CP-40-14 CP-40-14 Z = RoHS Compliant Part W = Qualified for Automotive Applications AUTOMOTIVE PRODUCTS The ADAU1977W models are available with controlled manufacturing to support the quality and reliability requirements of automotive applications Note that these automotive models may have specifications that differ from the commercial models; therefore, designers should review the Specifications section of this data sheet carefully Only the automotive grade products shown are available for use in automotive applications Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for these models Rev C | Page 66 of 68 Data Sheet ADAU1977 NOTES Rev C | Page 67 of 68 ADAU1977 Data Sheet NOTES ©2013–2014 Analog Devices, Inc All rights reserved Trademarks and registered trademarks are the property of their respective owners D10296-0-1/14(C) Rev C | Page 68 of 68 ... pin to an analog 3.3 V supply Analog Input Channel Inverting Input Analog Input Channel Noninverting Input Analog Input Channel Inverting Input Analog Input Channel Noninverting Input Analog Input... rising CIN hold from CCLK rising CLATCH setup to CCLK rising CLATCH hold from CCLK rising CLATCH high COUT enable from CLATCH falling COUT delay from CCLK falling COUT tristate from CLATCH rising... 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