Apple macbook pro 13 a1708 X502MLB catz 820 00840 a

8 ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5% ALL CAPACITANCE VALUES ARE IN MICROFARADS ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ REV DESIGN: X502/MLB_CATZ ECN CK APPD DESCRIPTION OF REVISION DATE 0006782329 ENGINEERING RELEASED 2016-08-10 LAST CHANGE: Tue Aug 17:02:57 2016 LAST_MODIFICATION=Tue Aug D LAST_MODIFICATION=Tue Aug PAGE CSA CONTENTS 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 C B A 17:03:06 2016 10 11 12 13 14 15 16 18 19 20 22 23 24 25 26 27 28 29 30 31 32 33 34 35 37 38 39 40 48 50 51 SYNC Table of Contents BOM Configuration BOM Configuration PD Parts CPU GFX CPU MISC/JTAG/CFG/RSVD CPU LPDDR3 Interface CPU & PCH Power CPU & PCH Grounds CPU Core Decoupling CPU GT Decoupling PCH Decoupling PCH Audio/LPC/SPI/SMBus PCH Power Management PCH PCIE/USB/CLKS PCH SPI/UART/GPIO CPU/PCH Merged XDP Chipset Support Chipset Support LPDDR3 VREF Margining LPDDR3 DRAM Channel A (00-31) LPDDR3 DRAM Channel A (32-63) LPDDR3 DRAM Channel B (00-31) LPDDR3 DRAM Channel B (32-63) LPDDR3 DRAM Termination USB-C HIGH SPEED USB-C HIGH SPEED USB-C SUPPORT USB-C PORT CONTROLLER A USB-C PORT CONTROLLER B USB-C CONNECTOR A USB-C CONNECTOR B USB-C SUPPORT WIFI/BT MODULE WIFI/BT Module Support CAMERA OF CAMERA OF P1:KEYBOARD & TRACKPAD CONN SMC SMC Shared Support DATE PAULM 06/15/2015 PAULM 06/15/2015 PAULM 06/15/2015 PAULM 06/15/2015 PAULM 06/15/2015 PAULM 06/15/2015 PAULM 06/15/2015 PAULM 06/15/2015 PAULM 06/15/2015 17:03:06 2016 D PAGE CSA CONTENTS 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 52 53 54 55 56 58 61 62 63 64 66 69 70 71 72 73 74 76 77 78 79 80 81 82 84 85 86 99 100 102 103 104 500 SMC Project Support SMBus Connections Power Sensors High Side Power Sensors Load Side Power Sensors Extended Thermal Sensors SPI ROM & SWD Debug HDA BRIDGE JACK CODEC SPEAKER AMP JACK TRANSLATORS DC-IN & BATTERY CONNECTORS PBUS Supply & Battery Charger VReg CPU VCC Cntl CPU IMVP VCC & VCCSA IMVP VCCSA GT IMVP VCCGT VR - 5V S4, 3.3V S5 VR - OPC (EDRAM) PMIC IC & Power Control PMIC VCCPCH VCCIO 1.8V PMIC 1.2V 1.0V 0.6V RAIL DESENSE CAPS Power FETs LCD Backlight Driver eDP Display Connector SSD MODULE DEVELOPMENT ONLY Power Aliases NC_ AND NO_TEST SIGNALS Memory Signal Swaps FCT, ICT PROPERTIES =LAST SCHEMATIC PAGE= SYNC DATE PAULM 06/15/2015 PAULM 06/15/2015 PAULM 06/15/2015 PAULM 06/15/2015 PAULM 06/15/2015 PAULM 06/15/2015 PAULM 06/15/2015 AHAAGE 03/23/2016 AHAAGE 09/22/2015 AHAAGE 03/23/2016 C X362 06/23/2015 PAULM 06/15/2015 PAULM 06/15/2015 X502-EXP 12/03/2015 PAULM 06/15/2015 X502-EXP 12/03/2015 PAULM 06/15/2015 MICHKLEE 06/23/2015 B DOCUMENTS / BOARDS / ASSEMBLIES PART NUMBER QTY DESCRIPTION REFERENCE DES 051-02265 SCHEM,MLB_CATZ,X502 SCH 820-00875 PCBF,MLB_CATZ,X502 MLB 639-03266 CRITICAL Table of Contents BOM OPTION DRAWING TITLE SCHEM,MLB-CATZ,X502 CRITICAL DRAWING NUMBER Apple Inc PCBA,MLB_CATZ,XXXXX,X502 COMMON PARTS,MLB_CATZ,X502 CBOM CMN_PARTS_BOM 985-00239 DEV PARTS,MLB_CATZ,X502 DEV1 DEVELOPMENT_LIST NOTICE OF PROPRIETARY PROPERTY: BOM_COST_GROUP=NO COST ITEMS 051-02265 REVISION R 685-00125 A THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED 1.0.0 BRANCH PAGE SHEET 1 OF 500 OF 73 SIZE D Programmables (All Builds) Major ICs CPU PART NUMBER D QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION SMC 998-00235 IC,CPU,SKL-ULT,2+3E,42X24MM,BGA1356 U0500 CRITICAL CPU_SKL:BASE 998-04195 INTERPOSER,VTT ADAPTER,SKL-U,BGA1356 U0500 CRITICAL CPU_SKL:VTT_INTERPOSER 337S00168 CPU,SKYU,QJ8N,D0,QS,2/2,2.3,15W,BGA1356 U0500 CRITICAL CPU_SKL:2_2_QS_2.3 337S00170 CPU,SKYU,QJ8K,D0,QS,2/2,2.6,15W,BGA1356 U0500 CRITICAL CPU_SKL:2_2_QS_2.6 337S00149 CPU,SKYU,QJ57,J0,ES0,2/3,1.6,15W,BGA1356 U0500 CRITICAL CPU_SKL:2_3_ES0_GD 337S00150 CPU,SKYU,QJ58,J0,ES0,2/3,1.6,28W,BGA1356 U0500 CRITICAL CPU_SKL:2_3_ES0_BT 337S00219 CPU,SKYU,QK2T,K1,SQS,1.8,15W,.95,BGA1356 U0500 CRITICAL CPU_SKL:2_3_SQS_1G8 337S00220 CPU,SKYU,QKBY,K1,SQS,2.2,15W,1.05,BG1356 U0500 CRITICAL CPU_SKL:2_3_SQS_2G2 337S00222 CPU,SKYU,QK33,K1,SQS,2.0,15W,1.0,BG1356 U0500 CRITICAL CPU_SKL:2_3_SQS_2G0 337S00233 CPU,SKYU,QK32,K1,SQS,2.4,15W,BGA1356 U0500 CRITICAL CPU_SKL:2_3_SQS_2G4 337S00232 CPU,SKY,SR2JC,K1,PRQ,1.8,15W,BGA1356 U0500 CRITICAL CPU_SKL:2_3_PRQ_1G8 337S00239 CPU,SKY,SR2JM,K1,PRQ,2.0,15W,BGA1356 U0500 CRITICAL CPU_SKL:2_3_PRQ_2G0 337S00234 CPU,SKYU,SR2JL,K1,PRQ,2.4,15W,BGA1356 U0500 CRITICAL CPU_SKL:2_3_PRQ_2G4 338S1231 IC,SMC12,40MHZ/50DMIPS MCU,7X7,168BGA U5000 CRITICAL SMC:BLANK 341S00334 IC,SMC-B1,EXT (V2.31A18) POC,X502 U5000 CRITICAL SMC:POC 341S00429 IC,SMC-B1,EXT (V2.35A4) PROTO 1,X502 U5000 CRITICAL SMC:PROTO1 341S00517 IC,SMC-B1,EXT (V2.35A51) PROTO 2,X502 U5000 CRITICAL SMC:PROTO2 341S00562 IC,SMC-B1,EXT (V2.36A2) EVT,X502 U5000 CRITICAL SMC:EVT 341S00611 IC,SMC-B1,EXT (V2.36A33) PRE-DVT,X502 U5000 CRITICAL SMC:PREDVT 341S00633 IC,SMC-B1,EXT (V2.36A48) DVT,X502 U5000 CRITICAL SMC:DVT 341S00662 IC,SMC-B1,EXT (V2.36F58) PVT,X502 U5000 CRITICAL SMC:PVT IC,SPI SERIAL FLASH,64M BITS,3V,CSP,QE=1 U6100 CRITICAL BOOTROM:BLANK D EFI ROM 335S0959 MICRON TABLE_ALT_ITEM 335S00006 ALT_CMN 335S0959 ALL MACRONIX 341S00389 IC,EFI (V0072) PROTO 0,X502 U6100 CRITICAL BOOTROM:PROTO0 341S00452 IC,EFI (V0093) PROTO 0,X502 U6100 CRITICAL BOOTROM:PROTO1 341S00513 IC,EFI (V0114) PROTO 2,X502 U6100 CRITICAL BOOTROM:PROTO2 341S00543 IC,EFI (V0130) PROTO 2.2,X502 U6100 CRITICAL BOOTROM:PROTO2_2 341S00573 IC,EFI (V0143) EVT,X502 U6100 CRITICAL BOOTROM:EVT 341S00673 IC,EFI (V0173) PVT,X502 U6100 CRITICAL BOOTROM:PVT C C BT ROM ACE 335S00024 353S00422 IC,CD3215,USB PWR SWITCH,A0,6X6MM,BGA96 U3100,U3200 CRITICAL ACE:A0 353S00660 IC,CD3215,ACE,A1,USB PWR SWITCH,BGA96 U3100,U3200 CRITICAL ACE:A1 353S00807 IC,CD3215,ACE,B0,USB PWR SWITCH,BGA96 U3100,U3200 CRITICAL ACE:B0 353S00887 IC,CD3215,ACE,B0,USB PWR SW,BLNK,BGA96 U3100,U3200 CRITICAL ACE:B0_B (BOOT CODE: 0002.08.07) 353S00888 IC,CD3215,ACE,B0,USB PWR SW,OTP=2,BGA96 U3100,U3200 CRITICAL ACE:B0_2 (BOOT CODE: 0002.08.07) 353S00926 IC,CD3215,ACE,B03,USB PWR SW,BLNK,BGA96 U3100,U3200 CRITICAL ACE:B0_3 (BOOT CODE: 0002.08.08) 353S00961 IC,CD3215,ACE,C00,USB PWR SW,BLNK,BGA96 U3100,U3200 CRITICAL ACE:C0 335S0837 B IC,TBT,ALPINE RIDGE DP,QSJV,B1,6X6MM,BGA96 U2800 CRITICAL TBT_AR:B1_QS 998-04160 IC,TBT,ALP-RIDGE DP,SLL44-TRAY,B1,CSP337 U2800 CRITICAL TBT_AR:B1_PRQ_TRAY 338S00176 IC,TBT,ALPN-RIDGE DP,SLL43-T&R,B1,CSP337 U2800 CRITICAL TBT_AR:B1_PRQ 338S00229 IC,TBT,ALPINE RIDGE,QSTY,QS,C0,CSP337 U2800 CRITICAL TBT_AR:C0_QS 338S00249 IC,TBT,ALPINE RIDGE,QT5S,QS,C1,CSP337 U2800 CRITICAL TBT_AR:C1_QS 338S00254 IC,TBT,ALPINE RIDGE,SLLSM,PRQ,C1,CSP337 U2800 CRITICAL TBT_AR:C1_PRQ CRITICAL BT_ROM:BLANK ALT_CMN 335S00024 ALL ALTERNATE 341S00196 IC,BT ROM (V53) DVT,X261 U3770 CRITICAL BT_ROM:X261 341S00397 IC,BT ROM (V53) PROTO0,X502 U3770 CRITICAL BT_ROM:PROTO0 341S00397 IC,BT ROM (V53) PROTO0,X502 U3770 CRITICAL BT_ROM:PVT IC,MEMORY,EEPROM,4K,1.7V-5.5V,UDFN8 U3780 CRITICAL WIFI-ROM:BLANK WIFI ROM 335S0956 TABLE_ALT_ITEM TBT ALPINE RIDGE U3770 IC,FLASH,USON8,512KBIT,75MHZ TABLE_ALT_ITEM 335S00145 338S00160 ALT_CMN 335S0956 ALL ALTERNATE 341S00607 WIFI ROM (P175) PRE-DVT,WW1,X502 U3780 CRITICAL WIFI-ROM:MURATA-FCC 341S00608 WIFI ROM (P175) PRE-DVT,WW2,X502 U3780 CRITICAL WIFI-ROM:MURATA-ETSI 341S00609 WIFI ROM (P175) PRE-DVT,WW3,X502 U3780 CRITICAL WIFI-ROM:MURATA-APAC 341S00610 WIFI ROM (P175) PRE-DVT,IND,X502 U3780 CRITICAL WIFI-ROM:MURATA-IND 341S00636 WIFI ROM (P177) USI-WW1,X502 U3780 CRITICAL WIFI-ROM:USI-FCC 341S00637 WIFI ROM (P177) USI-WW2,X502 U3780 CRITICAL WIFI-ROM:USI-ETSI 341S00638 WIFI ROM (P177) USI-WW3,X502 U3780 CRITICAL WIFI-ROM:USI-APAC 341S00639 WIFI ROM (P177) USI-IND,X502 U3780 CRITICAL WIFI-ROM:USI-IND 335S00133 IC,SPI SERIAL FLASH,8MBITS,3.0V,USON8 U2890 CRITICAL AR_ROM:BLANK 341S00451 IC,NVM / AR (V0.8.15.E1) PROTO 1,X502 U2890 CRITICAL AR_ROM:PROTO1 341S00512 IC,NVM (VB1-10.11-E2.6.3) PROTO 2,X502 U2890 CRITICAL AR_ROM:PROTO2 341S00559 IC,NVM (V16.8) EVT,X502 U2890 CRITICAL AR_ROM:EVT 341S00606 IC,NVM (V1.5) PRE-DVT,X502 U2890 CRITICAL AR_ROM:PREDVT 341S00628 IC, NVM (V3.8), DVT, X502 U2890 CRITICAL AR_ROM:DVT 341S00661 IC, NVM (VTBD), PVT, X502 U2890 CRITICAL AR_ROM:PVT B WIRELESS MODULE 339S0250 MODULE,WIFI/BT,STELLA CIDRE,MUR,LGA80 U3700 CRITICAL WIRELESS:MURATA 339S0251 MODULE,WIFI/BT,STELLA CIDRE,USI,LGA80 U3700 CRITICAL WIRELESS:USI TBT ROM DESIGN: X502/MLB_CATZ LAST CHANGE: Thu Aug 21:00:42 2016 A SYNC_MASTER=PAULM PAGE TITLE SYNC_DATE=06/15/2015 BOM Configuration DRAWING NUMBER Apple Inc 051-02265 REVISION R NOTICE OF PROPRIETARY PROPERTY: BOM_COST_GROUP=NO COST ITEMS THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED 1.0.0 BRANCH PAGE SHEET OF 500 OF 73 SIZE D A Main DRAM Parts PART NUMBER D QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION 333S00101 IC,LPDDR3-1866,16GB,512MX32,25NM,BGA178 U2300,U2400,U2500,U2600 CRITICAL DRAM:HYNIX_8GB_1866 333S0784 IC,LPDDR3-1866,32GBIT,25NM,BGA178 U2300,U2400,U2500,U2600 CRITICAL DRAM:HYNIX_16GB_1866 333S00097 IC,LPDDR3-1866,16GB,512MX32,20NM,BGA178 333S00098 IC,LPDDR3-1866,32GB,1GX32,20NM,BGA178 333S00099 IC,LPDDR3-1866,16GB,512MX32,20NM,BGA178 333S00049 IC,SDRAM,LPDDR3-1866,32GBIT,20NM,BGA178 U2300,U2400,U2500,U2600 U2300,U2400,U2500,U2600 U2300,U2400,U2500,U2600 U2300,U2400,U2500,U2600 CRITICAL DRAM:MICRON_8GB_1866 CRITICAL DRAM:MICRON_16GB_1866 CRITICAL DRAM:SAMSUNG_8GB_1866 CRITICAL DRAM:SAMSUNG_16GB_1866 Alternate Parts More Alternate Parts TABLE_ALT_HEAD PART NUMBER ALTERNATE FOR PART NUMBER BOM OPTION REF DES 107S00015 107S00011 ALT_CMN ALL TABLE_ALT_HEAD COMMENTS: PART NUMBER ALTERNATE FOR PART NUMBER BOM OPTION REF DES 197S00046 197S00036 ALT_CMN ALL COMMENTS: TABLE_ALT_ITEM TABLE_ALT_ITEM TFT EPSON TABLE_ALT_ITEM 107S00087 107S00029 ALT_CMN ALL TABLE_ALT_ITEM YAGEO 197S00047 197S00036 ALT_CMN ALL KYOCERA TABLE_ALT_ITEM 107S00033 107S00034 ALT_CMN ALL TABLE_ALT_ITEM TFT 197S00048 197S00036 ALT_CMN ALL MURATA TABLE_ALT_ITEM 107S00071 107S00053 ALT_CMN ALL YAGEO 197S00053 197S00050 ALT_CMN ALL KYOCERA TABLE_ALT_ITEM 107S00044 107S00076 ALT_CMN ALL TABLE_ALT_ITEM CYNTEC 197S00054 197S00050 ALT_CMN ALL NDK TABLE_ALT_ITEM 107S00070 107S0085 ALT_CMN ALL TABLE_ALT_ITEM TDK 197S00055 197S00050 ALT_CMN ALL MURATA TABLE_ALT_ITEM 107S0248 107S0250 ALT_CMN ALL TABLE_ALT_ITEM TFT 311S00008 311S0271 ALT_CMN DIODES INC ALL TABLE_ALT_ITEM 107S0249 Main DRAM SPD Straps HYNIX MICRON SAMSUNG -RESERVED- ALT_CMN ALL TABLE_ALT_ITEM TFT 311S00060 311S0273 ALT_CMN ALL DIODES INC TABLE_ALT_ITEM 128S00009 PCH INTERNAL PULL-UPS ARE TO VCCGPPD = 3.3V RAMCFG1 (STUFF R) (STUFF R) (OPEN) (OPEN) 107S0251 128S00015 ALT_CMN ALL TABLE_ALT_ITEM KEMET 311S00004 311S0370 ALT_CMN ALL ON SEMI TABLE_ALT_ITEM RAMCFG0 (STUFF R) (OPEN) (STUFF R) (OPEN) RAMCFG2 (STUFF R) (OPEN) 8GB 16GB 2133 1867 RAMCFG3 (STUFF R) (OPEN) DIE A DIE B 128S00070 RAMCFG4 (STUFF R) (OPEN) 128S00015 ALT_CMN ALL TABLE_ALT_ITEM PANASONIC 311S00013 311S0508 ALT_CMN ALL DIODES INC TABLE_ALT_ITEM 128S00010 128S00011 ALT_CMN ALL TABLE_ALT_ITEM PANASONIC 311S00122 311S0543 ALT_CMN ALL DIODES INC TABLE_ALT_ITEM 128S00026 128S00011 ALT_CMN ALL TABLE_ALT_ITEM NEC 311S0596 311S0593 ALT_CMN ALL TI TABLE_ALT_ITEM 128S00031 128S00011 ALT_CMN ALL TABLE_ALT_ITEM ROHM 311S00097 311S00036 ALT_CMN ALL DIODES INC TABLE_ALT_ITEM 128S00058 128S00018 ALT_CMN ALL D TABLE_ALT_ITEM TABLE_ALT_ITEM ROHM 353S00711 353S2073 ALT_CMN ALL 353S00712 353S2216 ALT_CMN ALL ON SEMI TABLE_ALT_ITEM PART NUMBER 117S0006 C QTY DESCRIPTION REFERENCE DES RES,MF,1/20W,1K OHM,5,0201,SMD CRITICAL RES,MF,1/20W,1K OHM,5,0201,SMD R1330,R1331,R1334 117S0006 RES,MF,1/20W,1K OHM,5,0201,SMD R1331,R1332,R1334 117S0006 RES,MF,1/20W,1K OHM,5,0201,SMD R1331,R1334 117S0006 RES,MF,1/20W,1K OHM,5,0201,SMD R1330,R1332,R1334 117S0006 RES,MF,1/20W,1K OHM,5,0201,SMD R1330,R1334 128S00067 ALT_CMN ALL ROHM TABLE_ALT_ITEM 128S00062 DRAM:HYNIX_8GB_1866 R1330,R1331,R1332,R1334 117S0006 128S00069 BOM OPTION 128S00067 ALT_CMN ALL NEC TABLE_ALT_ITEM 128S0364 DRAM:HYNIX_16GB_1866 128S0264 ALT_CMN ALL TABLE_ALT_ITEM SANYO 2ND FACTORY ON SEMI TABLE_ALT_ITEM 128S0311 DRAM:MICRON_8GB_1866 128S0329 ALT_CMN ALL TABLE_ALT_ITEM NEC ALT TO SANYO 353S00107 353S3239 ALT_CMN ALL ON SEMI TABLE_ALT_ITEM 128S0325 DRAM:MICRON_16GB_1866 128S0397 ALT_CMN ALL TABLE_ALT_ITEM PANASONIC 353S00854 353S4342 ALT_CMN ALL ST MICRO TABLE_ALT_ITEM 131S00134 DRAM:SAMSUNG_8GB_1866 131S00041 ALT_CMN ALL TABLE_ALT_ITEM TAIYO YUDEN 353S00769 353S4398 ALT_CMN ALL DIODES INC TABLE_ALT_ITEM 132S00064 DRAM:SAMSUNG_16GB_1866 132S0409 ALT_CMN ALL TABLE_ALT_ITEM MURATA 353S00525 353S4471 ALT_CMN ALL VISHAY TABLE_ALT_ITEM 138S00077 138S00035 ALT_CMN ALL TAIYO YUDEN 371S0713 371S0558 ALT_CMN ALL DIODES INC TABLE_ALT_ITEM 138S00093 138S00035 ALT_CMN ALL TABLE_ALT_ITEM KYOCERA 371S00074 371S0602 ALT_CMN ALL INFINEON TABLE_ALT_ITEM 138S00084 138S00060 ALT_CMN ALL TABLE_ALT_ITEM TAIYO YUDEN 371S0704 371S00077 ALT_CMN ALL NXP TABLE_ALT_ITEM 138S0703 138S0648 ALT_CMN ALL TABLE_ALT_ITEM MURATA 371S00089 371S00085 ALT_CMN ALL DIODES INC TABLE_ALT_ITEM 138S0700 138S0641 ALT_CMN ALL TABLE_ALT_ITEM MURATA 372S0186 372S0185 ALT_CMN ALL NXP TABLE_ALT_ITEM 138S0689 138S0701 ALT_CMN ALL TABLE_ALT_ITEM MURATA 372S00016 372S00015 ALT_CMN ALL DIODES INC TABLE_ALT_ITEM 138S0864 138S0709 ALT_CMN ALL TABLE_ALT_ITEM MULTIPLE 376S1053 376S0604 ALT_CMN ALL DIODES INC TABLE_ALT_ITEM 138S1103 MLB VERSION ID STRAPS 138S0706 DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION 138S00106 CODE INVERT TO VALUE 138S00015 RES,MF,1/20W/1K OHM,5,0201,SMD RES,MF,1/20W/1K OHM,5,0201,SMD BOARD_ID:POC 138S0846 RES,MF,1/20W/1K OHM,5,0201,SMD R1690 BOARD_ID:PROTO0 R1691 BOARD_ID:PRE_PROTO1 138S00032 RES,MF,1/20W/1K OHM,5,0201,SMD 138S00049 RES,MF,1/20W/1K OHM,5,0201,SMD R1691,R1690 BOARD_ID:PROTO1 R1692 BOARD_ID:PROTO2 138S0775 RES,MF,1/20W/1K OHM,5,0201,SMD 138S00086 B RES,MF,1/20W/1K OHM,5,0201,SMD R1692,R1690 BOARD_ID:PROTO2_2 138S0738 RES,MF,1/20W/1K OHM,5,0201,SMD R1692,R1691 BOARD_ID:EVT R1692,R1691,R1690 BOARD_ID:PREDVT 152S00381 117S0006 RES,MF,1/20W/1K OHM,5,0201,SMD R1693 117S0006 RES,MF,1/20W/1K OHM,5,0201,SMD R1693,R1690 BOARD_ID:DVT BOARD_ID:DVT3 R1693,R1691 BOARD_ID:PVT RES,MF,1/20W/1K OHM,5,0201,SMD R1693,R1691,R1690 BOARD_ID:PRQ1 138S0754 ALT_CMN 376S0761 ALT_CMN ALL TOSHIBA TABLE_ALT_ITEM KYOCERA ALL 138S0777 ALT_CMN ALL 138S0811 ALT_CMN 376S00086 376S0761 ALT_CMN ALL DIODES INC TABLE_ALT_ITEM MULTIPLE ALL 138S0831 ALT_CMN 376S1080 376S0820 ALT_CMN ALL DIODES INC TABLE_ALT_ITEM SAMSUNG 376S00074 376S0855 ALT_CMN ALL TOSHIBA TABLE_ALT_ITEM TAIYO YUDEN ALL 138S0831 ALT_CMN ALL 138S0860 ALT_CMN 376S00146 376S1061 ALT_CMN ALL ROHM TABLE_ALT_ITEM KYOCERA ALL 138S0884 ALT_CMN 376S1089 376S1128 ALT_CMN ALL NXP TABLE_ALT_ITEM SAMSUNG ALL 138S1101 ALT_CMN 377S00031 377S0178 ALT_CMN ALL ON SEMI TABLE_ALT_ITEM TAIYO YUDEN 377S00048 377S00017 ALT_CMN ST MICRO ALL TABLE_ALT_ITEM SAMSUNG ALL 152S1129 ALT_CMN ALL 152S00343 152S1682 ALT_CMN ALL 152S00363 152S00048 ALT_CMN ALL 152S00358 377S0155 377S00011 ALT_CMN ON SEMI ALL TABLE_ALT_ITEM CHILISIN 740S0144 740S0118 ALT_CMN ALL LITTELFUSE 152S00208 ALT_CMN ALL 152S00367 152S00266 ALT_CMN MURATA 740S00028 740S0118 ALT_CMN ALL NEC 740S00003 740S0135 ALT_CMN ALL BUSSMANN TABLE_ALT_ITEM AEM, INC TABLE_ALT_ITEM CHILISIN ALL 740S00027 740S0159 ALT_CMN ALL BOURNS TABLE_ALT_ITEM NEC 740S00033 740S00002 ALT_CMN THINKING ALL TABLE_ALT_ITEM 152S00403 152S00322 ALT_CMN ALL B TABLE_ALT_ITEM TABLE_ALT_ITEM TABLE_5_ITEM 117S0006 376S00014 TABLE_ALT_ITEM TABLE_5_ITEM RES,MF,1/20W/1K OHM,5,0201,SMD MURATA TABLE_ALT_ITEM TABLE_5_ITEM ALL TABLE_ALT_ITEM TABLE_5_ITEM 117S0006 ALT_CMN TABLE_ALT_ITEM TABLE_5_ITEM 117S0006 138S0739 TABLE_ALT_ITEM TABLE_5_ITEM 117S0006 FAIRCHILD TABLE_ALT_ITEM TABLE_ALT_ITEM TABLE_5_ITEM 117S0006 ALL TABLE_ALT_ITEM TABLE_5_ITEM 117S0006 ALT_CMN TABLE_ALT_ITEM TABLE_5_ITEM 117S0006 376S0678 TABLE_ALT_ITEM TABLE_5_ITEM 117S0006 376S1106 TABLE_ALT_ITEM TABLE_5_ITEM 117S0006 TAIYO YUDEN TABLE_ALT_ITEM TABLE_5_ITEM 117S0006 ALL TABLE_ALT_ITEM TABLE_5_HEAD QTY ALT_CMN TABLE_ALT_ITEM TABLE_ALT_ITEM PCH INTERNAL PULL-UPS ARE TO VCCGPPD = 3.3V PART# 138S0719 C TABLE_ALT_ITEM TABLE_ALT_ITEM CHILISIN 740S00007 740S00019 ALT_CMN ALL BOURNS TABLE_ALT_ITEM 152S1872 152S00361 ALT_CMN ALL MURATA TABLE_ALT_ITEM 155S0659 155S0382 ALT_CMN ALL MURATA TABLE_ALT_ITEM 155S0694 155S0387 ALT_CMN ALL MURATA TABLE_ALT_ITEM 155S00155 155S0441 ALT_CMN TDK ALL TABLE_ALT_ITEM 155S0660 155S0513 ALT_CMN MURATA ALL TABLE_ALT_ITEM 155S00007 155S0667 ALT_CMN ALL TAIYO YUDEN TABLE_ALT_ITEM 155S00034 155S0706 ALT_CMN MURATA ALL TABLE_ALT_ITEM 155S00203 155S0894 ALT_CMN ALL TAIYO YUDEN TABLE_ALT_ITEM 155S00115 155S00114 ALT_CMN ALL MURATA DESIGN: X502/MLB_CATZ LAST CHANGE: Fri Aug 13:34:33 2016 A SYNC_MASTER=PAULM SYNC_DATE=06/15/2015 PAGE TITLE BOM Configuration DRAWING NUMBER Apple Inc 051-02265 REVISION R NOTICE OF PROPRIETARY PROPERTY: BOM_COST_GROUP=NO COST ITEMS THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED 1.0.0 BRANCH PAGE SHEET OF 500 OF 73 SIZE D A MOUNTING HOLES POGO PINS 998-03850 870-02068 870-01680 SH0430 SH0400 SH0431 SH0432 POGO-2.3OD-4.1H-SM POGO-2.3OD-4.1H-SM POGO-2.0OD-2.95H-SM-1 SM SM SM SM 1 SH0434 SH0401 SH0437 POGO-2.3OD-4.1H-SM 4.0R3.6-NSP D SH0435 SH0436 SH0433 POGO-2.3OD-4.1H-SM POGO-2.3OD-4.1H-SM POGO-2.3OD-4.1H-SM POGO-2.0OD-2.95H-SM-1 SM SM SM SM 4.0R3.6-NSP 1 D 1 TOP STANDOFFS FAN MOUNTING HOLE 860-00385 SH0450 998-03850 2.8OD1.2ID-1.44H-SM SH0410 TH-NSP SH0451 2.8OD1.2ID-1.44H-SM SH0452 SH0453 2.8OD1.2ID-1.44H-SM 2.8OD1.2ID-1.44H-SM 1 1 2 2 SL-2.6X2.0-4.7X4.1 C C SH0457 SH0455 2.8OD1.2ID-1.44H-SM 2.8OD1.2ID-1.44H-SM 1 2 BOTTOM STANDOFFS 860-00468 SH0460 2.8OD1.2ID-3.0H-SM PLATED HOLES SH0461 2.8OD1.2ID-3.0H-SM 1 2 SH0420 B TH-NSP B LARGER SLOT, NEAR ANTENNA SL-3.38X2.1-5.88X4.6 998-06494 SHIELD CANS SH0421 TH-NSP MEMORY CAN - TOP SL-3.36X2.1-5.86X4.6 998-03823 PART NUMBER QTY 806-07887 SH0425 1 DESCRIPTION SHIELD CAN FENCE,DRAM,MN,X520 REFERENCE DES SHLD4 CRITICAL CRITICAL BOM OPTION SHIELD_CAN_MEMORY_TOP MEMORY CAN - BOTTOM TH-NSP SL-3.36X2.1-5.86X4.6 PART NUMBER SH0426 QTY 806-08894 TH-NSP DESCRIPTION SHIELD FENCE,BOT DRAM,SUS,PRE-MN,X520 REFERENCE DES SHLD1 CRITICAL CRITICAL BOM OPTION SHIELD_CAN_MEMORY_BOT SL-3.36X2.1-5.86X4.6 998-03823 WIRELESS CAN PART NUMBER 806-07886 A QTY DESCRIPTION SHIELD CAN,EMI,WIFI,SYM,MN,TALL,X520 REFERENCE DES SHLD2 CRITICAL CRITICAL BOM OPTION SHIELD_CAN_WIFI DESIGN: X502/MLB_CATZ LAST CHANGE: Thu Aug 21:00:42 2016 SYNC_MASTER=PAULM SYNC_DATE=06/15/2015 PAGE TITLE PD Parts USB-C CAN PART NUMBER 806-07885 DRAWING NUMBER QTY DESCRIPTION SHIELD CAN,AR,USB-C,THRU,X520 REFERENCE DES SHLD3 CRITICAL CRITICAL BOM OPTION SHIELD_CAN_USBC BOM_COST_GROUP=MECHANICALS Apple Inc 051-02265 REVISION R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED 1.0.0 BRANCH PAGE SHEET OF 500 OF 73 SIZE D A D D CRITICAL OMIT_TABLE U0500 SKL-ULT-2+3E TBD BGA 69 10 C =PP0V95_S0_CPU_VCCIO OUT 28 OUT 28 OUT 28 OUT 28 OUT 28 OUT 28 OUT 28 OUT 28 OUT 28 OUT 28 OUT 28 OUT 28 OUT 28 OUT 28 OUT 17 IN 28 IN R0530 IN 70 24.9 1% 1/20W MF 201 28 72 66 OUT IN E55 F55 E58 F58 F53 G53 F56 G56 DDI1_TXN[0] DDI1_TXP[0] DDI1_TXN[1] DDI1_TXP[1] DDI1_TXN[2] DDI1_TXP[2] DDI1_TXN[3] DDI1_TXP[3] DP_DDI2_ML_C_N DP_DDI2_ML_C_P DP_DDI2_ML_C_N DP_DDI2_ML_C_P DP_DDI2_ML_C_N DP_DDI2_ML_C_P DP_DDI2_ML_C_N DP_DDI2_ML_C_P C50 D50 C52 D52 A50 B50 D51 C51 DDI2_TXN[0] DDI2_TXP[0] DDI2_TXN[1] DDI2_TXP[1] DDI2_TXN[2] DDI2_TXP[2] DDI2_TXN[3] DDI2_TXP[3] XDP_USB_EXTD_OC_L DP_DDPB_HPD B9 L9 DP_DDPC_HPD TP_PCH_GPP_E15 L7 L6 JTAG_ISP_TDO DP_INT_HPD N9 L10 EDP_COMP E52 SYM OF 20 C47 C46 D46 C45 A45 B45 A47 B47 EDP_ML_C_N EDP_ML_C_P EDP_ML_C_N EDP_ML_C_P EDP_ML_C_N EDP_ML_C_P EDP_ML_C_N EDP_ML_C_P EDP_AUXN E45 EDP_AUXP F45 EDP_AUXCH_C_N EDP_AUXCH_C_P EDP_TXN[0] EDP_TXP[0] EDP_TXN[1] EDP_TXP[1] EDP_TXN[2] EDP_TXP[2] EDP_TXN[3] EDP_TXP[3] EDP 28 DP_DDI1_ML_C_N DP_DDI1_ML_C_P DP_DDI1_ML_C_N DP_DDI1_ML_C_P DP_DDI1_ML_C_N DP_DDI1_ML_C_P DP_DDI1_ML_C_N DP_DDI1_ML_C_P DDI OUT 28 PLACE_NEAR=U0500.E52:15.24MM 28 EDP_DISP_UTIL B52 DDI1_AUXN DDI1_AUXP DDI2_AUXN DDI2_AUXP DISPLAY SIDEBANDS GPP_E12/USB2_OC3* GPP_E13/DDPB_HPD0 GPP_E7/CPU_GP1 GPP_E8/SATALED* GPP_E9/USB2_OC0* GPP_E10/USB2_OC1* GPP_E11/USB2_OC2* GPP_E14/DDPC_HPD1 GPP_E15/DDPD_HPD2 GPP_E16/DDPE_HPD3 GPP_E17/EDP_HPD G50 F50 E48 F48 66 72 OUT 66 72 OUT 66 72 OUT 66 72 OUT 66 72 OUT 66 72 OUT 66 72 OUT 66 72 BI 66 BI 66 BI 28 BI 28 BI 28 BI 28 NC DP_DDI1_AUXCH_C_N DP_DDI1_AUXCH_C_P DP_DDI2_AUXCH_C_N DP_DDI2_AUXCH_C_P A7 H1 A9 C9 D9 XDP_PCH_OBSDATA_A3 XDP_PCH_OBSDATA_B0 XDP_USB_EXTA_OC_L XDP_USB_EXTB_OC_L XDP_USB_EXTC_OC_L EDP_BKLTEN R12 EDP_BKLTCTL R11 EDP_VDDEN U13 EDP_RCOMP OUT EDP_BKLT_EN EDP_BKLT_PWM EDP_PANEL_PWR_EN OUT 17 OUT 17 IN 17 IN 17 IN 17 OUT 65 68 OUT 66 72 OUT 66 72 C OMIT_TABLE U0500 SKL-ULT-2+3E TBD BGA B FOR FUTURE PRODUCT PER PDG 12 12 =PP1V8_SUS_PCH_VCC1P8_U12 =PP1V8_SUS_PCH_VCC1P8_U11 NC NC NC NC NC NC NC =PP3V3_SUS_PCH_VCCPRIM R0550 R0551 R0552 R0553 100K 100K 100K 100K 1 1 AW69 AW68 AU56 AW48 C7 U12 U11 H11 G46 RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD SYM 20 OF 20 SPARE RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD F6 E3 C11 B11 A11 D12 C12 F52 F46 B NC NC NC NC NC NC NC NC NC 12 69 5% 5% 5% 5% A 1/20W MF 201 1/20W MF 201 1/20W MF 201 1/20W MF 201 XDP_USB_EXTA_OC_L XDP_USB_EXTB_OC_L XDP_USB_EXTC_OC_L XDP_USB_EXTD_OC_L 17 17 17 DESIGN: X502/MLB_CATZ LAST CHANGE: Thu Aug 21:00:42 2016 17 SYNC_MASTER=PAULM =PP3V3_S0_PCH R0554 10K PAGE TITLE 13 14 16 19 60 69 5% 1/20W SYNC_DATE=06/15/2015 MF 201 JTAG_ISP_TDO CPU GFX DRAWING NUMBER 28 Apple Inc 051-02265 REVISION R NOTICE OF PROPRIETARY PROPERTY: BOM_COST_GROUP=CPU & CHIPSET THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED 1.0.0 BRANCH PAGE SHEET OF 500 OF 73 SIZE D A 69 59 54 19 14 10 =PP1V_S3_CPU_VCCST PLACE_NEAR=U0500.C63:254MM 69 17 10 R0612 =PP1V_S0SW_CPU_VCCSTG 1K R06101 D 1K 5% 1/20W MF 201 68 54 40 39 BI CPU_PROCHOT_L OMIT_TABLE 5% 1/20W MF 201 PLACE_NEAR=R0611:1MM 39 19 68 40 R0611 499 1% 1/20W MF 201 U0500 CPU_CATERR_L CPU_PECI CPU_PROCHOT_R_L PM_THRMTRIP_L OUT BI 40 39 OUT NC PLACE_NEAR=U0500.C65:25.4MM 19 BI 19 BI 19 BI 19 BI 13 IN 17 OUT 13 OUT 13 OUT C D63 A54 C65 C63 A65 XDP_BPM_L XDP_BPM_L XDP_BPM_L XDP_BPM_L C55 D55 B54 C56 MLB_RAMCFG4 XDP_PCH_OBSDATA_D2 BT_PWRRST_L BT_TIMESTAMP V1 H3 BA5 AY5 PROC_POPIRCOMP PCH_OPIRCOMP OPCE_RCOMP OPC_RCOMP R06811 R06821 R06831 R06841 1% 1/20W MF 201 1% 1/20W MF 201 1% 1/20W MF 201 1% 1/20W MF 201 49.9 D SKL-ULT-2+3E 49.9 49.9 AT16 AU16 H66 H65 TBD BGA SYM OF 20 CATERR* PECI PROCHOT* THERMTRIP* SKTOCC* JTAG CPU MISC BPM[0]* BPM[1]* BPM[2]* BPM[3]* GPP_D21/SPI1_IO2 GPP_E1/SATAXPCIE1/SATAGP1 GPP_B3/CPU_GP2 GPP_B4/CPU_GP3 PROC_POPIRCOMP PCH_OPIRCOMP OPCE_RCOMP OPC_RCOMP PROC_TCK PROC_TDI PROC_TDO PROC_TMS PROC_TRST* B61 D60 A61 C60 B59 XDP_CPU_TCK XDP_CPU_TDI XDP_CPU_TDO XDP_CPU_TMS XDP_CPU_TRST_L PCH_JTAG_TCK PCH_JTAG_TDI PCH_JTAG_TDO PCH_JTAG_TMS PCH_TRST* JTAGX B56 D59 A56 C59 C61 A59 XDP_PCH_TCK XDP_PCH_TDI XDP_PCH_TDO XDP_PCH_TMS XDP_PCH_TRST_L PCH_JTAGX IN 17 72 IN 17 72 OUT 17 72 IN 17 72 IN 17 72 IN 17 72 IN 17 72 OUT 17 72 IN 17 72 IN 17 72 BI 17 49.9 C PLACE_NEAR=U0500.AT16:12.7MM PLACE_NEAR=U0500.H65:12.7MM PLACE_NEAR=U0500.AU16:12.7MM PLACE_NEAR=U0500.H66:12.7MM OMIT_TABLE U0500 SKL-ULT-2+3E TBD BGA 17 BI 17 BI 17 BI 72 17 BI 17 BI 17 BI 17 BI 17 BI 17 BI 17 BI 17 BI 17 BI 17 BI 17 BI 17 BI 17 BI 17 BI 17 BI 17 BI 17 BI B 72 17 R06801 OUT CPU_CFG CPU_CFG CPU_CFG CPU_CFG CPU_CFG CPU_CFG CPU_CFG CPU_CFG CPU_CFG CPU_CFG CPU_CFG CPU_CFG CPU_CFG CPU_CFG CPU_CFG CPU_CFG E68 B67 D65 D67 E70 C68 D68 C67 F71 G69 F70 G68 H70 G71 H69 G70 CFG[0] (IPU) SYM 19 OF 20 CFG[1] (IPU) RESERVED CFG[2] (IPU) CFG[3] (IPU) CFG[4] (IPU) CFG[5] (IPU) CFG[6] (IPU) CFG[7] (IPU) CFG[8] (IPU) CFG[9] (IPU) CFG[10] (IPU) CFG[11] (IPU) CFG[12] (IPU) CFG[13] (IPU) CFG[14] (IPU) CFG[15] (IPU) CPU_CFG CPU_CFG E63 F63 CFG[16] CFG[17] CPU_CFG CPU_CFG E66 F66 CFG[18] CFG[19] CPU_CFG_RCOMP E60 CFG_RCOMP E8 ITP_PMODE NC NC 49.9 1% 1/20W MF 201 NC NC NC NC NC NC NC NC NC NC 70 70 A CFG :eDP ENABLE/DISABLE = DISABLED = ENABLED NC NC 17 NC NC R0634 RSVD_TP AK13 RSVD_TP AK12 TP_CPU_RSVD_AK13 TP_CPU_RSVD_AK12 RSVD BB2 RSVD BA3 TP5 AU5 TP6 AT5 RSVD RSVD RSVD RSVD D5 D4 B2 C2 TP_CPU_AU5 TP_CPU_AT5 NC ITP_PMODE RSVD E1 RSVD E2 NC NC AY2 AY1 RSVD RSVD RSVD BA4 RSVD BB4 NC NC D1 D3 RSVD RSVD RSVD A4 RSVD C4 NC NC K46 K45 RSVD RSVD AL25 AL27 RSVD RSVD C71 B70 (IPU) (IPU) TP4 BB5 NC NC RSVD AY3 NC RSVD RSVD RSVD D71 RSVD C70 F60 NC NC RSVD A52 RSVD RSVD C54 RSVD D54 NC NC J71 J68 F61 E61 RSVD RSVD VSS VSS RSVD RSVD TP1 AY4 TP2 BB3 VSS AY71 ZVM* AR56 RSVD_TP AW71 RSVD_TP AW70 MSM* AP56 PROC_SELECT* C64 19 70 70 70 B TP_CPU_BB5 RSVD A69 RSVD B69 RSVD_TP RSVD_TP 70 NC NC NC NC RSVD AW1 (IPU) 70 NC NC NC NC F65 G65 CPU_CFG EDP_ENABLE TP_CPU_RSVD_BB68 TP_CPU_RSVD_BB69 RSVD B3 RSVD A3 BA70 BA68 TP_CPU_RSVD_BA70 TP_CPU_RSVD_BA68 (IPU) RSVD_TP BB68 RSVD_TP BB69 70 TP_CPU_AY4 TP_CPU_BB3 70 CPU_ZVM_L SYNC_MASTER=PAULM OUT TP_CPU_RSVD_AW71 TP_CPU_RSVD_AW70 CPU_MSM_L DESIGN: X502/MLB_CATZ LAST CHANGE: Thu Aug 21:00:42 2016 70 59 CONNECT TO OPC VRS 70 CPU MISC/JTAG/CFG/RSVD DRAWING NUMBER 70 OUT 59 Apple Inc CONNECT TO OPC VRS NC NOTICE OF PROPRIETARY PROPERTY: 5% 1/20W MF 201 BOM_COST_GROUP=CPU & CHIPSET 051-02265 REVISION R 1K PAGE TITLE SYNC_DATE=06/15/2015 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED 1.0.0 BRANCH PAGE SHEET OF 500 OF 73 SIZE D A D OMIT_TABLE 72 71 BI 72 71 BI BI 72 71 BI 72 71 BI 72 71 BI 72 71 BI 72 71 BI 72 71 BI 72 71 BI 72 71 BI 72 71 BI 72 71 BI 72 71 BI 72 71 BI 72 71 BI 72 71 BI 72 71 BI 72 71 BI 72 71 BI 72 71 BI 72 71 BI 72 71 BI 72 71 BI 72 71 BI 72 71 BI 72 71 BI 72 71 BI 72 71 BI 72 71 BI 72 71 BI 72 71 BI 72 71 BI 72 71 BI 72 71 BI 72 71 B BI 72 71 72 71 C BI BI 72 71 BI 72 71 BI 72 71 BI 72 71 BI 72 71 BI 72 71 BI 72 71 BI 72 71 BI 72 71 BI 72 71 BI 72 71 BI 72 71 BI 72 71 BI 72 71 BI 72 71 BI 72 71 BI 72 71 BI 72 71 BI 72 71 BI 72 71 BI 72 71 BI 72 71 BI 72 71 BI 72 71 BI 72 71 BI AL71 AL68 AN68 AN69 AL70 AL69 AN70 AN71 AR70 AR68 AU71 AU68 AR71 AR69 AU70 AU69 AF65 AF64 AK65 AK64 AF66 AF67 AK67 AK66 AF70 AF68 AH71 AH68 AF71 AF69 AH70 AH69 BB65 AW65 AW63 AY63 BA65 AY65 BA63 BB63 BA61 AW61 BB59 AW59 BB61 AY61 BA59 AY59 AT66 AU66 AP65 AN65 AN66 AP66 AT65 AU65 AT61 AU61 AP60 AN60 AN61 AP61 AT60 AU60 MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ DDR0_DQ[0] DDR0_DQ[1] DDR0_DQ[2] DDR0_DQ[3] DDR0_DQ[4] DDR0_DQ[5] DDR0_DQ[6] DDR0_DQ[7] DDR0_DQ[8] DDR0_DQ[9] DDR0_DQ[10] DDR0_DQ[11] DDR0_DQ[12] DDR0_DQ[13] DDR0_DQ[14] DDR0_DQ[15] DDR0_DQ[16] DDR0_DQ[17] DDR0_DQ[18] DDR0_DQ[19] DDR0_DQ[20] DDR0_DQ[21] DDR0_DQ[22] DDR0_DQ[23] DDR0_DQ[24] DDR0_DQ[25] DDR0_DQ[26] DDR0_DQ[27] DDR0_DQ[28] DDR0_DQ[29] DDR0_DQ[30] DDR0_DQ[31] DDR0_DQ[32] DDR0_DQ[33] DDR0_DQ[34] DDR0_DQ[35] DDR0_DQ[36] DDR0_DQ[37] DDR0_DQ[38] DDR0_DQ[39] DDR0_DQ[40] DDR0_DQ[41] DDR0_DQ[42] DDR0_DQ[43] DDR0_DQ[44] DDR0_DQ[45] DDR0_DQ[46] DDR0_DQ[47] DDR0_DQ[48] DDR0_DQ[49] DDR0_DQ[50] DDR0_DQ[51] DDR0_DQ[52] DDR0_DQ[53] DDR0_DQ[54] DDR0_DQ[55] DDR0_DQ[56] DDR0_DQ[57] DDR0_DQ[58] DDR0_DQ[59] DDR0_DQ[60] DDR0_DQ[61] DDR0_DQ[62] DDR0_DQ[63] U0500 SKL-ULT-2+3E TBD BGA SYM OF 20 D OMIT_TABLE DDR0_CKP[0] DDR0_CKN[0] DDR0_CKP[1] DDR0_CKN[1] AT53 AU53 AT55 AU55 MEM_A_CLK_P MEM_A_CLK_N MEM_A_CLK_P MEM_A_CLK_N DDR0_CKE[0] DDR0_CKE[1] DDR0_CKE[2] DDR0_CKE[3] BA56 BB56 AW56 AY56 MEM_A_CKE MEM_A_CKE MEM_A_CKE MEM_A_CKE DDR0_CS[0]* AU45 DDR0_CS[1]* AU43 MEM_A_CS_L MEM_A_CS_L DDR0_ODT[0] AT45 DDR0_ODT[1] AT43NC MEM_A_ODT DDR0_CAA[0] DDR0_CAA[1] DDR0_CAA[2] DDR0_CAA[3] DDR0_CAA[4] DDR0_CAA[5] DDR0_CAA[6] DDR0_CAA[7] DDR0_CAA[8] DDR0_CAA[9] BA51 BB54 BA52 AY52 AW52 AY55 AW54 BA54 BA55 AY54 MEM_A_CAA MEM_A_CAA MEM_A_CAA MEM_A_CAA MEM_A_CAA MEM_A_CAA MEM_A_CAA MEM_A_CAA MEM_A_CAA MEM_A_CAA DDR0_CAB[0] DDR0_CAB[1] DDR0_CAB[2] DDR0_CAB[3] DDR0_CAB[4] DDR0_CAB[5] DDR0_CAB[6] DDR0_CAB[7] DDR0_CAB[8] DDR0_CAB[9] AU46 AU48 AT46 AU50 AU52 AY51 AT48 AT50 BB50 AY50 MEM_A_CAB MEM_A_CAB MEM_A_CAB MEM_A_CAB MEM_A_CAB MEM_A_CAB MEM_A_CAB MEM_A_CAB MEM_A_CAB MEM_A_CAB DDR0_DQSN[0] DDR0_DQSN[1] DDR0_DQSN[2] DDR0_DQSN[3] DDR0_DQSN[4] DDR0_DQSN[5] DDR0_DQSN[6] DDR0_DQSN[7] AM70 AT69 AH66 AG69 BA64 AY60 AR66 AR61 MEM_A_DQS_N MEM_A_DQS_N MEM_A_DQS_N MEM_A_DQS_N MEM_A_DQS_N MEM_A_DQS_N MEM_A_DQS_N MEM_A_DQS_N DDR0_DQSP[0] DDR0_DQSP[1] DDR0_DQSP[2] DDR0_DQSP[3] DDR0_DQSP[4] DDR0_DQSP[5] DDR0_DQSP[6] DDR0_DQSP[7] AM69 AT70 AH65 AG70 AY64 BA60 AR65 AR60 MEM_A_DQS_P MEM_A_DQS_P MEM_A_DQS_P MEM_A_DQS_P MEM_A_DQS_P MEM_A_DQS_P MEM_A_DQS_P MEM_A_DQS_P OUT 21 25 72 72 71 OUT 21 25 72 72 71 OUT 22 25 72 72 71 BI OUT 22 25 72 72 71 BI 72 71 BI 21 25 72 72 71 BI OUT 21 25 72 72 71 BI OUT 22 25 72 72 71 BI OUT 22 25 72 72 71 BI 72 71 BI OUT 21 22 25 72 72 71 BI OUT 21 22 25 72 72 71 BI 72 71 BI OUT 21 22 25 72 72 71 BI 72 71 BI 72 71 BI OUT 21 25 72 72 71 BI OUT 21 25 72 72 71 BI OUT 21 25 72 72 71 BI OUT 21 25 72 72 71 BI OUT 21 25 72 72 71 BI OUT 21 25 72 72 71 BI OUT 21 25 72 72 71 BI OUT 21 25 72 72 71 BI OUT 21 25 72 72 71 BI OUT 21 25 72 72 71 BI 72 71 BI OUT 22 25 72 72 71 BI OUT 22 25 72 72 71 BI OUT 22 25 72 72 71 BI OUT 22 25 72 72 71 BI OUT 22 25 72 72 71 BI OUT 22 25 72 72 71 BI OUT 22 25 72 72 71 BI OUT 22 25 72 72 71 BI OUT 22 25 72 72 71 BI OUT 22 25 72 72 71 BI 72 71 BI 72 71 BI 72 71 BI 72 71 BI 72 71 BI 72 71 BI 72 71 BI 72 71 BI 72 71 BI BI 71 72 BI 71 72 BI 71 72 BI 71 72 BI 71 72 BI 71 72 BI 71 72 BI 71 72 BI 71 72 72 71 BI BI 71 72 72 71 BI BI 71 72 72 71 BI BI 71 72 72 71 BI BI 71 72 72 71 BI BI 71 72 72 71 BI BI 71 72 72 71 BI BI 71 72 72 71 BI 72 71 BI 72 71 BI 72 71 BI 72 71 BI 72 71 BI 72 71 BI 72 71 BI DDR0_MA[3] BA50NC DDR0_MA[4] BB52NC DDR0_VREF_DQ AY68 DDR1_VREF_DQ BA67 DDR_VTT_CNTL AW67 CPU_DIMM_VREFCA CPU_DIMMA_VREFDQ CPU_DIMMB_VREFDQ PM_MEMVTT_EN BI OUT DDR0_ALERT* AW50 DDR0_PAR AT52NC DDR_VREF_CA AY67 BI OUT 20 OUT 20 72 71 BI OUT 20 72 71 BI 72 71 BI OUT 62 MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ AY39 AW39 AY37 AW37 BB39 BA39 BA37 BB37 AY35 AW35 AY33 AW33 BB35 BA35 BA33 BB33 AU40 AT40 AT37 AU37 AR40 AP40 AP37 AR37 AT33 AU33 AU30 AT30 AR33 AP33 AR30 AP30 AY31 AW31 AY29 AW29 BB31 BA31 BA29 BB29 AY27 AW27 AY25 AW25 BB27 BA27 BA25 BB25 AU27 AT27 AT25 AU25 AP27 AN27 AN25 AP25 AT22 AU22 AU21 AT21 AN22 AP22 AP21 AN21 U0500 DDR1_DQ[0] DDR1_DQ[1] DDR1_DQ[2] DDR1_DQ[3] DDR1_DQ[4] DDR1_DQ[5] DDR1_DQ[6] DDR1_DQ[7] DDR1_DQ[8] DDR1_DQ[9] DDR1_DQ[10] DDR1_DQ[11] DDR1_DQ[12] DDR1_DQ[13] DDR1_DQ[14] DDR1_DQ[15] DDR1_DQ[16] DDR1_DQ[17] DDR1_DQ[18] DDR1_DQ[19] DDR1_DQ[20] DDR1_DQ[21] DDR1_DQ[22] DDR1_DQ[23] DDR1_DQ[24] DDR1_DQ[25] DDR1_DQ[26] DDR1_DQ[27] DDR1_DQ[28] DDR1_DQ[29] DDR1_DQ[30] DDR1_DQ[31] DDR1_DQ[32] DDR1_DQ[33] DDR1_DQ[34] DDR1_DQ[35] DDR1_DQ[36] DDR1_DQ[37] DDR1_DQ[38] DDR1_DQ[39] DDR1_DQ[40] DDR1_DQ[41] DDR1_DQ[42] DDR1_DQ[43] DDR1_DQ[44] DDR1_DQ[45] DDR1_DQ[46] DDR1_DQ[47] DDR1_DQ[48] DDR1_DQ[49] DDR1_DQ[50] DDR1_DQ[51] DDR1_DQ[52] DDR1_DQ[53] DDR1_DQ[54] DDR1_DQ[55] DDR1_DQ[56] DDR1_DQ[57] DDR1_DQ[58] DDR1_DQ[59] DDR1_DQ[60] DDR1_DQ[61] DDR1_DQ[62] DDR1_DQ[63] SKL-ULT-2+3E TBD BGA SYM OF 20 LPDDR3 NON-INTERLEAVED 72 71 BI LPDDR3 NON-INTERLEAVED0 72 71 DDR1_CKP[0] DDR1_CKN[0] DDR1_CKP[1] DDR1_CKN[1] AP45 AN45 AP46 AN46 MEM_B_CLK_P MEM_B_CLK_N MEM_B_CLK_P MEM_B_CLK_N DDR1_CKE[0] DDR1_CKE[1] DDR1_CKE[2] DDR1_CKE[3] AN56 AP55 AN55 AP53 MEM_B_CKE MEM_B_CKE MEM_B_CKE MEM_B_CKE DDR1_CS[0]* BB42 DDR1_CS[1]* AY42 MEM_B_CS_L MEM_B_CS_L DDR1_ODT[0] BA42 DDR1_ODT[1] AW42NC MEM_B_ODT DDR1_CAA[0] DDR1_CAA[1] DDR1_CAA[2] DDR1_CAA[3] DDR1_CAA[4] DDR1_CAA[5] DDR1_CAA[6] DDR1_CAA[7] DDR1_CAA[8] DDR1_CAA[9] AY48 AP50 BA48 BB48 AP48 AP52 AN50 AN48 AN53 AN52 MEM_B_CAA MEM_B_CAA MEM_B_CAA MEM_B_CAA MEM_B_CAA MEM_B_CAA MEM_B_CAA MEM_B_CAA MEM_B_CAA MEM_B_CAA DDR1_CAB[0] DDR1_CAB[1] DDR1_CAB[2] DDR1_CAB[3] DDR1_CAB[4] DDR1_CAB[5] DDR1_CAB[6] DDR1_CAB[7] DDR1_CAB[8] DDR1_CAB[9] BA43 AY43 AY44 AW44 BB44 AY47 BA44 AW46 AY46 BA46 MEM_B_CAB MEM_B_CAB MEM_B_CAB MEM_B_CAB MEM_B_CAB MEM_B_CAB MEM_B_CAB MEM_B_CAB MEM_B_CAB MEM_B_CAB DDR1_DQSN[0] DDR1_DQSN[1] DDR1_DQSN[2] DDR1_DQSN[3] DDR1_DQSN[4] DDR1_DQSN[5] DDR1_DQSN[6] DDR1_DQSN[7] BA38 AY34 AT38 AT32 BA30 AY26 AR25 AR22 MEM_B_DQS_N MEM_B_DQS_N MEM_B_DQS_N MEM_B_DQS_N MEM_B_DQS_N MEM_B_DQS_N MEM_B_DQS_N MEM_B_DQS_N DDR1_DQSP[0] DDR1_DQSP[1] DDR1_DQSP[2] DDR1_DQSP[3] DDR1_DQSP[4] DDR1_DQSP[5] DDR1_DQSP[6] DDR1_DQSP[7] AY38 BA34 AR38 AR32 AY30 BA26 AR27 AR21 MEM_B_DQS_P MEM_B_DQS_P MEM_B_DQS_P MEM_B_DQS_P MEM_B_DQS_P MEM_B_DQS_P MEM_B_DQS_P MEM_B_DQS_P OUT 23 25 72 OUT 23 25 72 OUT 24 25 72 OUT 24 25 72 OUT 23 25 72 OUT 23 25 72 OUT 24 25 72 OUT 24 25 72 OUT 23 24 25 72 OUT 23 24 25 72 OUT 23 24 25 72 OUT 23 25 72 OUT 23 25 72 OUT 23 25 72 OUT 23 25 72 OUT 23 25 72 OUT 23 25 72 OUT 23 25 72 OUT 23 25 72 OUT 23 25 72 OUT 23 25 72 OUT 24 25 72 OUT 24 25 72 OUT 24 25 72 OUT 24 25 72 OUT 24 25 72 OUT 24 25 72 OUT 24 25 72 OUT 24 25 72 OUT 24 25 72 OUT 24 25 72 BI 71 72 BI 71 72 BI 71 72 BI 71 72 BI 71 72 BI 71 72 BI 71 72 BI 71 72 BI 71 72 BI 71 72 BI 71 72 BI 71 72 BI 71 72 BI 71 72 BI 71 72 BI 71 72 C B DDR1_ALERT* AN43 DDR1_PAR AP43NC DDR1_MA[3] BB46NC DDR1_MA[4] BA47NC DRAM_RESET* AT13NC DDR_RCOMP[0] AR18 DDR_RCOMP[1] AT18 DDR_RCOMP[2] AU18 CPU_DDR_RCOMP CPU_DDR_RCOMP CPU_DDR_RCOMP R0700 162 1% 1/20W MF 201 R0701 80.6 1% 1/20W MF 201 PLACE_NEAR=U0500.AU18:6MM R0702 200 1% 1/20W MF 201 PLACE_NEAR=U0500.AR18:6MM PLACE_NEAR=U0500.AT18:6MM A SYNC_MASTER=PAULM PAGE TITLE SYNC_DATE=06/15/2015 CPU LPDDR3 Interface DRAWING NUMBER Apple Inc 051-02265 REVISION R NOTICE OF PROPRIETARY PROPERTY: BOM_COST_GROUP=CPU & CHIPSET THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED 1.0.0 BRANCH PAGE OF 500 SHEET OF 73 SIZE D A 69 11 =PPVCCGT_S0_CPU OMIT_TABLE U0500 SKL-ULT-2+3E 69 10 D U0500 69 10 69 10 69 59 54 19 14 10 69 17 10 =PP1V2_S3_CPU_VDDQ =PP1V2_S3_CPU_VDDQC AU23 AU28 AU35 AU42 BB23 BB32 BB41 BB47 BB51 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ AM40 VDDQC =PP1V_S3_CPU_VCCST A18 =PP1V_S0SW_CPU_VCCSTG A22 69 10 =PP1V2_S0SW_CPU_VCCPLLOC 69 10 =PP1V_S3_CPU_VCCPLL AL23 K20 K21 SYM 14 OF 20 CPU POWER VCCST VCCSTG VCCPLL_OC VCCPLL VCCPLL C VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO AK28 AK30 AL30 AL42 AM28 AM30 AM42 =PP0V95_S0_CPU_VCCIO VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA AK23 AK25 G23 G25 G27 G28 J22 J23 J27 K23 K25 K27 K28 K30 =PPVCCSA_S0_CPU VCCIO_SENSE AM23 VSSIO_SENSE AM22 VSSSA_SENSE H21 VCCSA_SENSE H20 10 69 54 69 11 =PPVCCGT_S0_CPU PLACE_NEAR=U0500.J70:50.8MM 100 CPU_VCCGTSENSE_P 54 69 11 =PPVCCGTX_S0_CPU PLACE_NEAR=U0500.AK62:50.8MM 100 CPU_VCCGTXSENSE_P 69 59 =PP1V_S0_CPU_VCCOPC_AB62 PLACE_NEAR=U0500.AC63:50.8MM 100 CPU_VCCOPCSENSE_P 59 59 =PP1V_S0_CPU_VCCEOPIO_AE62 PLACE_NEAR=U0500.AL63:50.8MM 100 CPU_VCCEOPIOSENSE_P 59 =PPVCC_S0_CPU PLACE_NEAR=U0500.E32:50.8MM 100 CPU_VCCSENSE_P 54 PLACE_NEAR=U0500.AM22:50.8MM 100 CPU_VCCIOSENSE_N 61 PLACE_NEAR=U0500.H21:50.8MM 100 CPU_VCCSASENSE_N 54 PLACE_NEAR=U0500.J69:50.8MM 100 CPU_VCCGTSENSE_N 54 72 PLACE_NEAR=U0500.AL61:50.8MM 100 CPU_VCCGTXSENSE_N 69 PLACE_NEAR=U0500.AE63:50.8MM 100 CPU_VCCOPCSENSE_N 59 PLACE_NEAR=U0500.AJ62:50.8MM 100 CPU_VCCEOPIOSENSE_N 59 CPU_VCCSENSE_N 54 R0804 5% 1/20W MF 201 R0811 5% 1/20W MF 201 R0813 5% 1/20W MF 201 R0821 5% 1/20W MF 201 R0823 5% 1/20W MF 201 R0825 5% 1/20W MF 201 A48 A53 A58 A62 A66 AA63 AA64 AA66 AA67 AA69 AA70 AA71 AC64 AC65 AC66 AC67 AC68 AC69 AC70 AC71 J43 J45 J46 J48 J50 J52 J53 J55 J56 J58 J60 K48 K50 K52 K53 K55 K56 K58 K60 L62 L63 L64 L65 L66 L67 L68 L69 L70 L71 M62 N63 N64 N66 N67 N69 10 69 R0802 5% 1/20W MF 201 R0803 5% 1/20W MF 201 R0812 5% 1/20W MF 201 R0814 5% 1/20W MF 201 R0822 CPU_VCCSASENSE_N CPU_VCCSASENSE_P 61 CPU_VCCSASENSE_P 69 10 CPU_VCCIOSENSE_P CPU_VCCIOSENSE_N CPU_VCCIOSENSE_P 5% 1/20W MF 201 =PPVCCSA_S0_CPU SKL-ULT-2+3E TBD BGA R0801 =PP0V95_S0_CPU_VCCIO TBD BGA PLACE_NEAR=U0500.H20:50.8MM 100 69 10 OMIT_TABLE PLACE_NEAR=U0500.AM23:50.8MM 100 OUT 61 OUT 61 OUT 54 OUT 54 5% 1/20W MF 201 R0824 5% 1/20W MF 201 PLACE_NEAR=U0500.E33:50.8MM 100 R0826 5% 1/20W MF 201 OMIT_TABLE U0500 SKL-ULT-2+3E TBD BGA 69 12 69 12 B 12 69 12 69 12 12 12 69 12 69 14 12 69 47 13 69 12 A 69 12 64 12 69 12 =PP1V_SUS_PCH_VCCPRIM =PPVCCPRIMECORE_SUS_PCH AB19 AB20 P18 VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0 AF18 AF19 V20 V21 VCCPRIM_CORE VCCPRIM_CORE VCCPRIM_CORE VCCPRIM_CORE SYM 15 OF 20 CPU POWER PP1V_S5_PCH_DCPDSW AL1 DCPDSW_1P0 =PP1V_SUS_PCH_VCCMPHYAON K17 L1 VCCMPHYAON_1P0 VCCMPHYAON_1P0 N15 N16 N17 P15 P16 VCCMPHYGT_1P0 VCCMPHYGT_1P0 VCCMPHYGT_1P0 VCCMPHYGT_1P0 VCCMPHYGT_1P0 =PP1V_SUSSW_PCH_VCCAMPHYPLL K15 L15 VCCAMPHYPLL_1P0 VCCAMPHYPLL_1P0 =PP1V_SUS_PCH_VCCAPLL_F V15 =PP1V_SUSSW_PCH_VCCMPHYGT =PP1V_SUS_PCH_VCCPRIM AB17 Y18 U0500 69 12 69 VCCPRIM_1P0 T1 =PP1V_SUS_PCH_VCCPRIM 12 69 12 14 15 69 DCPRTC BB10 PPDCPRTC_PCH 12 VCCCLK1 A14 =PP1V_SUS_PCH_VCCCLK1 69 VCCCLK2 K19 =PP1V_SUS_PCH_VCCCLK2 12 VCCAPLL_1P0 VCCCLK3 L21 =PP1V_SUS_PCH_VCCCLK3 69 VCCPRIM_1P0 VCCPRIM_1P0 VCCCLK4 N20 =PP1V_SUS_PCH_VCCCLK4 12 VCCCLK5 L19 =PP1V_SUS_PCH_VCCCLK5 12 VCCCLK6 A10 =PP1V_SUS_PCH_VCCCLK6 12 69 AJ16 VCCSPI AF20 AF21 T19 T20 VCCSRAM_1P0 VCCSRAM_1P0 VCCSRAM_1P0 VCCSRAM_1P0 AJ21 VCCPRIM_3P3 N18 OMIT_TABLE =PP3V_G3H_PCH_VCCRTC =PP3V3_SUS_PCH_VCCSPI =PP1V_SUSSW_PCH_VCCAPLLEBB 12 69 14 69 VCCRTC AK19 VCCRTC BB14 VCCHDA AK20 69 =PP3V3_SUS_PCH_VCCPRIM VCCRTCPRIM_3P3 AK17 GPP_B0/CORE_VID0 AN11 GPP_B1/CORE_VID1 AN13 VCCPRIM_CORE_VID0 VCCPRIM_CORE_VID1 OUT 70 OUT 70 SKL-ULT-2+3E TBD BGA A30 A34 A39 A44 AK33 AK35 AK37 AK38 AK40 AL33 AL37 AL40 AM32 AM33 AM35 AM37 AM38 G30 NC 59 AB62 P62 V62 VCCOPC VCCOPC VCCOPC 59 =PP1V8_SUS_CPU_VCCOPC_H63 H63 59 59 RSVD =PP1V_S0_CPU_VCCOPC_AB62 =PP1V_S0_CPU_VCCOPC_P62 =PP1V_S0_CPU_VCCOPC_V62 VCCPRIM_1P0 59 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC RSVD 59 VCCAPLLEBB_1P0 K32 SYM 12 OF 20 AK32 NC 59 OUT OUT 59 59 59 OUT 59 OUT 10 69 12 69 VCCPRIM_3P3 V19 VCCATS_1P8 AA1 =PPVCC_S0_CPU 12 19 69 12 69 AJ19 =PP1V_SUS_PCH_FUSE 13 14 15 16 69 =PP3V3_SUS_PCH_VCCRTCPRIM =PP1V8_S0_PCH_VCCHDA_F =PP3V3_SUS_PCH_VCCPRIM =PP3V3_SUS_PCH_VCCPGPPA =PP3V3_SUS_PCH_VCCPGPPB =PP3V3_SUS_PCH_VCCPGPPC =PP3V3_SUS_PCH_VCCPGPPD =PP3V3_SUS_PCH_VCCPGPPE =PP1V8_SUS_PCH_VCCPGPPF =PP3V3_SUS_PCH_VCCPGPPG 12 69 VCCDSW_3P3 VCCDSW_3P3 VCCDSW_3P3 =PP1V_SUSSW_PCH_VCCSRAM AK15 AG15 Y16 Y15 T16 AF16 AD15 =PP1V8_SUS_PCH_VCCATS AD17 AD18 AJ17 =PP3V3_S5_PCH_VCCDSW VCCPGPPA VCCPGPPB VCCPGPPC VCCPGPPD VCCPGPPE VCCPGPPF VCCPGPPG G61 VCC_OPC_1P8 CPU POWER VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC 54 OUT 72 54 OUT G32 G33 G35 G37 G38 G40 G42 J30 J33 J37 J40 K33 K35 K37 K38 K40 K42 K43 =PP1V_S3_CPU_VCCST R0827 56 VCC_SENSE E32 VSS_SENSE E33 CPU_VCCSENSE_P CPU_VCCSENSE_N VIDALERT* B63 VIDSCK A63 VIDSOUT D64 CPU_VIDALERT_R_L CPU_VIDSCLK_R CPU_VIDSOUT_R VCCSTG G20 1% 1/20W MF 201 OUT 54 OUT 54 =PP1V_S0SW_CPU_VCCSTG AC63 AE63 VCCOPC_SENSE VSSOPC_SENSE =PP1V_S0_CPU_VCCEOPIO_AE62 =PP1V_S0_CPU_VCCEOPIO_AG62 AE62 AG62 VCCEOPIO VCCEOPIO CPU_VCCEOPIOSENSE_P CPU_VCCEOPIOSENSE_N AL63 AJ62 J70 J69 VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX AK42 AK43 AK45 AK46 AK48 AK50 AK52 AK53 AK55 AK56 AK58 AK60 AK70 AL43 AL46 AL50 AL53 AL56 AL60 AM48 AM50 AM52 AM53 AM56 AM58 AU58 AU63 BB57 BB66 =PPVCCGTX_S0_CPU 11 69 C CPU_VCCGTXSENSE_P CPU_VCCGTXSENSE_N OUT 69 OUT 69 B R0828 R0829: R0830: R0831: 100 1% 1/20W MF 201 PLACE_NEAR=U0500.B63:12.7MM PLACE_NEAR=U0500.A63:12.7MM PLACE_NEAR=U0500.D64:12.7MM 220 CPU_VIDALERT_L IN 54 1% 1/20W MF 201 10 17 69 R0830 CPU_VIDSCLK SYNC_MASTER=PAULM OUT 54 SYNC_DATE=06/15/2015 PAGE TITLE CPU & PCH Power DRAWING NUMBER R0831 CPU_VIDSOUT Apple Inc BI 54 5% 1/20W MF 0201 D 10 14 19 54 59 69 5% 1/20W MF 0201 VCCEOPIO_SENSE VSSEOPIO_SENSE N70 N71 R63 R64 R65 R66 R67 R68 R69 R70 R71 T62 U65 U68 U71 W63 W64 W65 W66 W67 W68 W69 W70 W71 Y62 VCCGTX_SENSE AK62 VSSGTX_SENSE AL61 VCCGT_SENSE VSSGT_SENSE 051-02265 REVISION R NOTICE OF PROPRIETARY PROPERTY: BOM_COST_GROUP=CPU & CHIPSET VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT R0829 VCC_OPC_1P8 =PP1V8_SUS_CPU_VCCOPC_G61 CPU_VCCOPCSENSE_P CPU_VCCOPCSENSE_N CPU_VCCGTSENSE_P CPU_VCCGTSENSE_N SYM 13 OF 20 CPU POWER VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED 1.0.0 BRANCH PAGE OF 500 SHEET OF 73 SIZE D A OMIT_TABLE OMIT_TABLE OMIT_TABLE SKL-ULT-2+3E SKL-ULT-2+3E SKL-ULT-2+3E TBD BGA TBD BGA TBD BGA U0500 D C B 70 TP_CPU_NCTFVSS_A5 70 TP_CPU_NCTFVSS_A70 A5 A67 A70 AA2 AA4 AA65 AA68 AB15 AB16 AB18 AB21 AB8 AD13 AD16 AD19 AD20 AD21 AD62 AD8 AE64 AE65 AE66 AE67 AE68 AE69 AF1 AF10 AF15 AF17 AF2 AF4 AF63 AG16 AG17 AG18 AG19 AG20 AG21 AG71 AH13 AH6 AH63 AH64 AH67 AJ15 AJ18 AJ20 AJ4 AK11 AK16 AK18 AK21 AK22 AK27 AK63 AK68 AK69 AK8 AL2 AL28 AL32 AL35 AL38 AL4 AL45 AL48 AL52 AL55 AL58 AL64 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS SYM 16 OF 20 GND1 U0500 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS AL65 AL66 AM13 AM21 AM25 AM27 AM43 AM45 AM46 AM55 AM60 AM61 AM68 AM71 AM8 AN20 AN23 AN28 AN30 AN32 AN33 AN35 AN37 AN38 AN40 AN42 AN58 AN63 AP10 AP18 AP20 AP23 AP28 AP32 AP35 AP38 AP42 AP58 AP63 AP68 AP70 AR11 AR15 AR16 AR20 AR23 AR28 AR35 AR42 AR43 AR45 AR46 AR48 AR5 AR50 AR52 AR53 AR55 AR58 AR63 AR8 AT2 AT20 AT23 AT28 AT35 AT4 AT42 AT56 AT58 70 70 70 AT63 AT68 AT71 AU10 AU15 AU20 AU32 AU38 AV1 AV68 AV69 AV70 AV71 AW10 AW12 AW14 AW16 AW18 AW21 AW23 AW26 AW28 AW30 AW32 AW34 AW36 AW38 AW41 AW43 AW45 AW47 AW49 AW51 AW53 AW55 AW57 AW6 AW60 AW62 AW64 AW66 AW8 AY66 B10 B14 B18 B22 B30 B34 B39 B44 B48 B53 B58 B62 B66 B71 BA1 BA10 BA14 BA18 BA2 BA23 BA28 BA32 BA36 F68 BA45 TP_CPU_NCTFVSS_AV1 TP_CPU_NCTFVSS_B71 TP_CPU_NCTFVSS_BA1 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS SYM 17 OF 20 GND2 U0500 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS BA49 BA53 BA57 BA6 BA62 BA66 BA71 BB18 BB26 BB30 BB34 BB38 BB43 BB55 BB6 BB60 BB64 BB67 BB70 C1 C25 C5 D10 D11 D14 D18 D22 D25 D26 D30 D34 D39 D44 D45 D47 D48 D53 D58 D6 D62 D66 D69 E11 E15 E18 E21 E46 E50 E53 E56 E6 E65 E71 F1 F13 F2 F22 F23 F27 F28 F32 F33 F35 F37 F38 F4 F40 F42 BA41 TP_CPU_NCTFVSS_BA71 TP_CPU_NCTFVSS_BB70 TP_CPU_NCTFVSS_C1 F8 G10 G22 G43 G45 G48 G5 G52 G55 G58 G6 G60 G63 G66 H15 H18 H71 J11 J13 J25 J28 J32 J35 J38 J42 J8 K16 K18 K22 K61 K63 K64 K65 K66 K67 K68 K70 K71 L11 L16 L17 70 70 70 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS SYM 18 OF 20 GND VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS D L18 L2 L20 L4 L8 N10 N13 N19 N21 N6 N65 N68 P17 P19 P20 P21 R13 R6 T15 T17 T18 T2 T21 T4 U10 U63 U64 U66 U67 U69 U70 V16 V17 V18 W13 W6 W9 Y17 Y19 Y20 Y21 C B A SYNC_MASTER=PAULM SYNC_DATE=06/15/2015 PAGE TITLE CPU & PCH Grounds DRAWING NUMBER Apple Inc 051-02265 REVISION R NOTICE OF PROPRIETARY PROPERTY: BOM_COST_GROUP=CPU & CHIPSET THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED 1.0.0 BRANCH PAGE OF 500 SHEET OF 73 SIZE D A 69 =PPVCC_S0_CPU C1000 1UF 20% 6.3V X6S-CERM 0201 69 C1001 1UF 20% 6.3V X6S-CERM 0201 C1002 1UF 20% 6.3V X6S-CERM 0201 C1003 1UF C1004 1UF 20% 6.3V X6S-CERM 0201 20% 6.3V X6S-CERM 0201 C1005 1UF 20% 6.3V X6S-CERM 0201 C1006 1UF 20% 6.3V X6S-CERM 0201 C1007 1UF C1008 1UF 20% 6.3V X6S-CERM 0201 20% 6.3V X6S-CERM 0201 C1009 1UF 20% 6.3V X6S-CERM 0201 C100A 1UF 20% 6.3V X6S-CERM 0201 C100B 1UF 20% 6.3V X6S-CERM 0201 C100C 1UF 20% 6.3V X6S-CERM 0201 C100D 1UF 20% 6.3V X6S-CERM 0201 C100E 1UF 20% 6.3V X6S-CERM 0201 C100F 1UF 20% 6.3V X6S-CERM 0201 C100G 1UF 20% 6.3V X6S-CERM 0201 C100H =PP1V2_S3_CPU_VDDQ 1UF CRITICAL CRITICAL C1050 10UF 20% 6.3V X6S-CERM 0201 20% 4V X6S 0402 C1051 10UF C1052 1UF 20% 4V X6S 0402 20% 6.3V X6S-CERM 0201 C1053 1UF C1054 1UF 20% 6.3V X6S-CERM 0201 20% 6.3V X6S-CERM 0201 C1055 1UF 20% 6.3V X6S-CERM 0201 D D C100I 1UF 20% 6.3V X6S-CERM 0201 C100J 1UF 20% 6.3V X6S-CERM 0201 C100K 1UF 20% 6.3V X6S-CERM 0201 C100L 1UF C100M 1UF 20% 6.3V X6S-CERM 0201 20% 6.3V X6S-CERM 0201 C100N 1UF 20% 6.3V X6S-CERM 0201 C100O 1UF 20% 6.3V X6S-CERM 0201 C100P 1UF C100Q 1UF 20% 6.3V X6S-CERM 0201 20% 6.3V X6S-CERM 0201 C100R 1UF 20% 6.3V X6S-CERM 0201 C100S 1UF 20% 6.3V X6S-CERM 0201 C100T 1UF 20% 6.3V X6S-CERM 0201 C100U 1UF 20% 6.3V X6S-CERM 0201 C100V 1UF 20% 6.3V X6S-CERM 0201 C100W 1UF 20% 6.3V X6S-CERM 0201 C100X 1UF 20% 6.3V X6S-CERM 0201 C100Y 1UF CRITICAL CRITICAL CRITICAL CRITICAL C1060 10UF 20% 6.3V X6S-CERM 0201 20% 4V X6S 0402 C1061 10UF 20% 4V X6S 0402 C1062 20UF 20% 2.5V X6S-CERM 0402 C1063 20UF CRITICAL CRITICAL CRITICAL C1064 20UF 20% 2.5V X6S-CERM 0402 20% 2.5V X6S-CERM 0402 C1065 10UF C1066 20UF 20% 4V X6S 0402 20% 2.5V X6S-CERM 0402 CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF C1010 20UF 20% 2.5V X6S-CERM 0402 1 C1011 20UF 20% 2.5V X6S-CERM 0402 C1020 20UF 20% 2.5V X6S-CERM 0402 C1021 C101A 20% 20% 0402 1 C1022 0402 C101B 20UF 20% C101C 0402 CRITICAL C10G0 220UF 20% 2.5V X6S-CERM 0402 C1023 20UF 20% 20% C1024 2.5V X6S-CERM 0402 C1015 20UF 20% 2.5V X6S-CERM 0402 C1016 20UF 20% 2.5V X6S-CERM 0402 C1017 20UF 0402 C1025 20% 2.5V X6S-CERM 0402 20UF 20% C1026 20UF 20% 2.5V X6S-CERM 20% 2.5V X6S-CERM 0402 C1027 0402 C1028 20UF 20% 69 2.5V X6S-CERM C101D 20UF C101E 20UF 20% 20% 2.5V X6S-CERM 2.5V X6S-CERM 0402 0402 CRITICAL C10G1 C101F 20UF 20% 20% 2.5V X6S-CERM 0402 C10H1 20% 20% 2.5V X6S-CERM 0402 0402 CRITICAL C10G3 20% C1029 69 C101J 20UF 20% 2.5V X6S-CERM 0402 C101K 20UF 20% 2.5V X6S-CERM 0402 C101L CRITICAL C10D0 20% 2.5V X6S-CERM 10UF 1UF 20% 4V X6S 0402 C1080 10UF 0402 20% 4V X6S 0402 20% 6.3V X6S-CERM 0201 C10D2 1UF C10D3 1UF 20% 6.3V X6S-CERM 0201 20% 6.3V X6S-CERM 0201 C10D4 1UF 20% 6.3V X6S-CERM 0201 C10G4 ELEC SM-COMBO 1UF 20% 6.3V X6S-CERM 0201 C1090 10UF 20% 4V X6S 0402 C10D6 20% 6.3V X6S-CERM 0201 C10A0 C10B0 20UF C10E0 10UF 20% 4V X6S 0402 10UF C1082 1UF 20% 4V X6S 0402 20% 6.3V X6S-CERM 0201 C1091 10UF 20% 4V X6S 0402 C1092 10UF 20% 4V X6S 0402 C10A1 1UF 20% 6.3V X6S-CERM 0201 C10A2 1UF 20% 6.3V X6S-CERM 0201 C10C0 20% 2.5V X6S-CERM 0402 C10E1 10UF C10B1 20UF 20% 2.5V X6S-CERM 0402 C10B2 20UF 20% 2.5V X6S-CERM 0402 CRITICAL CRITICAL CRITICALNOSTUFF NOSTUFF 20UF CRITICAL CRITICAL C1081 CRITICAL NOSTUFF C1093 10UF C1083 1UF C1084 1UF 20% 6.3V X6S-CERM 0201 C1094 10UF 20% 4V X6S 0402 C10A3 1UF 20% 6.3V X6S-CERM 0201 CRITICAL CRITICAL CRITICAL CRITICAL NOSTUFF NOSTUFF NOSTUFF NOSTUFF 1UF =PP1V_S0_CPU_VCCEOPIO CRITICAL 20% 6.3V X6S-CERM 0201 C1085 1UF 20% 6.3V X6S-CERM 0201 20% 4V X6S 0402 CRITICAL NOSTUFF C1095 10UF 20% 4V X6S 0402 =PPVCCSA_S0_CPU 20% 2.5V X6S-CERM 0402 59 CRITICAL CRITICAL CRITICAL CRITICAL NOSTUFF NOSTUFF 20% C10D5 C CRITICAL 20% 6.3V X6S-CERM 0201 C10D1 0201 =PP0V95_S0_CPU_VCCIO 1UF 20% 6.3V X6S-CERM CRITICAL 20UF =PP1V_S0_CPU_VCCOPC 1UF 0402 B C1071 20% 69 59 2.5V X6S-CERM 2V ELEC SM-COMBO C1070 20% 4V X6S 0402 220UF 2V ELEC SM-COMBO C101I CRITICAL 10UF 20UF 20UF 220UF 2V ELEC SM-COMBO 20UF 2.5V X6S-CERM 0402 CRITICAL NOSTUFF C101H 20% 2.5V X6S-CERM 0402 20UF 220UF 20% C101G =PP1V2_S3_CPU_VDDQC 0402 20UF 2.5V X6S-CERM 0402 C1019 CRITICAL CRITICAL 20% 2.5V X6S-CERM 1 20UF 20% 2.5V X6S-CERM 0402 C1018 20UF CRITICAL CRITICAL CRITICAL CRITICALNOSTUFF NOSTUFF 20% 2.5V X6S-CERM 2V ELEC SM-COMBO 20UF 220UF 2V C1014 20UF 20% 2.5V X6S-CERM 0402 20UF 2.5V X6S-CERM 0402 CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL 20% 2.5V X6S-CERM C1013 20UF 20UF 2.5V X6S-CERM 0402 CRITICAL CRITICALNOSTUFF 20% 2.5V X6S-CERM 20UF 2.5V X6S-CERM 20UF 20UF CRITICAL CRITICAL NOSTUFF NOSTUFF C C1012 20% 2.5V X6S-CERM 0402 CRITICAL CRITICALNOSTUFF 1 C10C1 20UF 20% 2.5V X6S-CERM 0402 C10C2 20UF 20% 2.5V X6S-CERM 0402 C10B3 20UF 20% 2.5V X6S-CERM 0402 1 C10A4 1UF 20% 6.3V X6S-CERM 0201 C10B4 20UF 20% 2.5V X6S-CERM 0402 20UF 20% 2.5V X6S-CERM 0402 C10A5 1UF 20% 6.3V X6S-CERM 0201 C10A6 1UF 20% 6.3V X6S-CERM 0201 B CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICALNOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF CRITICAL CRITICALNOSTUFF C10C3 C10C4 20UF 20% 2.5V X6S-CERM 0402 C10B5 20UF 20% 2.5V X6S-CERM 0402 1 C10B6 20UF C10B7 20UF 20% 2.5V X6S-CERM 0402 20% 2.5V X6S-CERM 0402 C10B8 20UF 20% 2.5V X6S-CERM 0402 C10B9 C10BA 20UF 20% 2.5V X6S-CERM 0402 20UF 20% 2.5V X6S-CERM 0402 CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICALNOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF C10C5 20UF 20% 2.5V X6S-CERM 0402 C10C6 20UF C10C7 20UF 20% 2.5V X6S-CERM 0402 20% 2.5V X6S-CERM 0402 C10C8 20UF 20% 2.5V X6S-CERM 0402 C10C9 C10CA 20UF 20% 2.5V X6S-CERM 0402 20UF 20% 2.5V X6S-CERM 0402 20% 4V X6S 0402 CRITICAL C10H0 220UF 20% 2V ELEC SM-COMBO 69 A =PP1V_S3_CPU_VCCPLL C10F0 1UF 20% 6.3V X6S-CERM 0201 69 =PP1V2_S0SW_CPU_VCCPLLOC C10F1 1UF 20% 6.3V X6S-CERM 0201 59 54 19 14 69 =PP1V_S3_CPU_VCCST C10F2 1UF 20% 6.3V X6S-CERM 0201 69 17 =PP1V_S0SW_CPU_VCCSTG C10F3 1UF SYNC_MASTER=PAULM 20% PAGE TITLE 6.3V X6S-CERM 0201 SYNC_DATE=06/15/2015 CPU Core Decoupling DRAWING NUMBER Apple Inc 051-02265 REVISION R NOTICE OF PROPRIETARY PROPERTY: BOM_COST_GROUP=CPU & CHIPSET THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED SIZE 1.0.0 BRANCH PAGE 10 OF 500 SHEET 10 OF 73 D A 1V S0 REGULATOR FOR EDRAM (ON-PACKAGE CACHE) PPBUS_G3H_CPU 63 62 61 57 56 55 54 43 1 EDRAM_RAIL:ENABLE PP5V_S0_P1VOPC 5% 1/16W MF-LF 402 PM_SLP_S3_L IN 2.2UF 5% 1/20W MF 0201 R7730 2.2 BYPASS=U7700.2::6MM 20% 25V X6S-CERM 0402 MIN_LINE_WIDTH=0.2500 MIN_NECK_WIDTH=0.2000 DIDT=TRUE VLDOIN 12 V5IN Scrub S3 & S5 pins connections! P1VOPC_ENS3 P1VOPC_EN 5% 1/20W MF 0201 C7715 1 CRITICAL R7711 0.1UF 0.1% 0.05W MF 0201 BYPASS=U7700.6::6MM TPS51916 QFN VREF P1VOPC_REFIN MIN_LINE_WIDTH=0.1160 MIN_NECK_WIDTH=0.0600 30.9K 10% 16V X7R-CERM 0402 CRITICAL REFIN P1VOPC_MODE P1VOPC_TRIP 19 MODE 18 TRIP 1% 1/20W MF 201 1 R7710 R7713 1K CRITICAL R7712 1% 1/20W MF 201 C7716 1% 1/20W MF 201 R7714 PLACE_NEAR=U7700.8:5MM 1 Q3D VIN P1VOPC_DRVH VOUT = 1.01V DIDT=TRUE 5% GATE_NODE=TRUE 1/20W MF 201 TG P1VOPC_SW MIN_LINE_WIDTH=0.1160 MIN_NECK_WIDTH=0.0600 SWITCH_NODE=TRUE DIDT=TRUE TGR VSW MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.2000 SWITCH_NODE=TRUE DIDT=TRUE 5% 1/16W MF-LF 402 IN P1VOPC_DRVL BG DIDT=TRUE GATE_NODE=TRUE MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.2000 PP3V3_S0 NOSTUFF C7751 10UF 10% 25V X7R 0201 CRITICAL C7761 10UF 20% 4V X6S 0402 20% 4V X6S 0402 C PLACE_NEAR=L7730.2:6MM P1VOPC_LL_SNUB DIDT=TRUE NOSTUFF C7732 0.001UF 10% 50V CERM 402 CRITICAL C7748 220UF 20% 2V ELEC SM-COMBO CRITICAL C7749 220UF CRITICAL C7752 270UF 20% 2V ELEC SM-COMBO CRITICAL C7753 270UF 20% 2V TANT CASE-B 20% 2V TANT CASE-B CRITICAL C7754 270UF 20% 2V TANT CASE-B PLACE_NEAR=Q7750.5:1MM 2 P1VOPC_SNS 100K VCC 74AUP1G07GF PM_PGOOD_EDRAM_R PM_OPC_ZVM_L NC 5% 1/20W MF 201 72 P1VOPC_SNS_R MIN_LINE_WIDTH=0.1160 MIN_NECK_WIDTH=0.0600 R7745 5% 1/20W MF 201 Y EDRAM_RAIL:ENABLE 14 26 39 59 60 66 72 100K 5% 1/20W MF 201 U7790 10 MIN_LINE_WIDTH=0.1000 MIN_NECK_WIDTH=0.0600 38 42 45 46 49 54 60 63 64 69 IN R7741 R7791 (OD) NC CRITICAL 0.22UF R7790 NC C7723 1000PF 5% 1/16W MF-LF 402 XW7700 SM PM_SLP_S3_L A 10K 5% 1/10W MF-LF 603 10% 16V CERM 402 =PP1V_S3_CPU_VCCST CPU_ZVM_L R7751 XW7710 SM SOT891 59 72 C7740 BYPASS=U7700.8::4MM LEVEL SHIFT B PP1V_OPC_S0 2.2 PLACE_NEAR=U7700.21:1MM 10% 10V X5R-CERM 0201 L7730 R7732 P1VOPC_PGND 0.1UF F = 500 KHZ CRITICAL R7733 5.2A MAX OUTPUT 1UH-20%-11A-0.0127OHM P1VOPC_VSW IHLP2020BD-PIHA052D-COMBO NOSTUFF PLACE_NEAR=Q7730.9:1MM 1% 1/20W MF 201 MIN_LINE_WIDTH=0.1160 MIN_NECK_WIDTH=0.0600 C7790 TANT CASE-B1S Q7730 P1VOPC_AGND 69 54 19 14 10 20% 16V CSD58873Q3D R7731 P1VOPC_VTTREF 35.7K 10% 10V X7R-CERM 0201 0.1% 1/20W MF 0201 33UF 20% 16V TANT CASE-B1S CRITICAL MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.2000 XW7730 SM PLACE_NEAR=U7700.18:3MM PLACE_NEAR=U7700.19:3MM 0.01UF 48.7K 33K 10 3.09K C7721 0402 21 R7715 VTT THRM GND PAD PGND GND MIN_LINE_WIDTH=0.1160 MIN_NECK_WIDTH=0.0600 GATE_NODE=TRUE DIDT=TRUE MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.2000 GATE_NODE=TRUE DIDT=TRUE VTTREF P1VOPC_REFIN_R P1VOPC_DRVH_R 11 20 P1VOPC_VTT DRVL PGOOD VDDQSNS VTT VTTSNS PLACE_NEAR=U7700.8:5MM 72 72 P1VOPC_DRVL_R C P1VOPC_VREF VBST 15 DRVH 14 SW 13 U7700 17 S3 16 S5 MIN_LINE_WIDTH=0.1160 MIN_NECK_WIDTH=0.0600 33UF 20% 25V X6S-CERM 0402 D CRITICAL 10% P1VOPC_VBST EDRAM_RAIL:DISABLE C7719 16V X7R-CERM 5% 1/20W MF 201 BYPASS=U7700.12::6MM R7719 CRITICAL 0.1UF 20% 4V X6S 0402 C7700 1 C7730 10UF CRITICAL R7718 72 66 60 59 39 26 14 C7701 C7724 PLACE_NEAR=Q7730.8:2.7MM MIN_LINE_WIDTH=0.1160 MIN_NECK_WIDTH=0.0600 DIDT=TRUE PGND PP5V_S0 CRITICAL 2.2UF 20% 25V X6S-CERM 0402 P1VOPC_BOOT_RC CRITICAL 72 69 64 59 57 56 55 54 72 2.2UF 10% 25V X7R 0201 R7700 2.2 C7722 1000PF PP1V_OPC_S0 72 59 CRITICAL C7720 D THE FOLLOWING SHORTCUTS ARE USED FOR POC: - OPC (EDRAM) IS POWERED FROM ONE VR - LOAD SWITCHES ARE USED TO MEET THE TURN-ON TIMING.( 5MS 10% 10V X5R-CERM 0201 OUT 5% 1/20W MF 201 5% 1/20W MF 201 PP3V3_S5 72 69 68 64 63 61 60 58 44 SLP_S0# Isolation C C7852 SLP_S0# IS DRIVEN HIGH OUTSIDE OF S0 SOME DEVICES CARE ABOUT THIS USE BANJO AS BUFFER AND PULL-UP TO SLP_S3# TO CREATE VERSION THAT IS HIGH ONLY IN S0 0.1UF 10% 10V X5R-CERM 0201 U7852 74AUP1T97GM 72 66 60 59 39 26 14 PM_SLP_S0S3_L OUT IN 19 60 68 72 64 60 IN PM_SLP_S3_L R7853 PM_EN_P3V3S0 59K 1% 1/20W MF 201 SOT886 PM_EN_P1V8S0 PM_EN_P1V8S0_RC C7853 0.1UF 60 64 R7852 100K 5% 1/20W MF 201 DELAY > 1.5MS 10% 10V X5R-CERM 0201 OUT C7896 0.1UF 10% 10V X5R-CERM 0201 CRITICAL 68 62 60 72 66 60 59 39 26 14 IN PM_PGOOD_PVDDQ IN PM_SLP_S3_L 62 61 60 U7896 (PGVR4) 64 OUT 60 60 OUT PM_EN_P3V3S0_RC 1% 1/20W MF 201 =PP3V3_S0_PCH 69 19 16 14 13 SOT886 36.5K2 58 60 68 60 62 68 74AUP1T97GM R7851 70 5% 1/20W MF 0201 58 60 PM_SLP_S3_L 10% 0201 OUT 72 66 60 59 39 26 14 64 C7886 10V X7R-CERM U7850 60 0.01UF 14 19 60 R7887 ENLVA 62 64 PP3V3_S5 0.1UF 100K SOT891 (ENVR3) PM_EN_PVCCIO 08 CRITICAL OUT 61 R7896 NC 100K 5% 1/20W MF 201 39 NC 70 AGND_PMIC CKPLUS_WAIVE=PWRTERM2GND 74LVC1G08 (TO SMC) S5_PWRGD TP_PGOOD_PVCCIO TP_PGOOD_P1V00 MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE U7894 C7850 R7882 PM_EN_P1V2S0G 72 60 17 72 69 68 64 63 61 60 58 44 PM_EN_P1V00 PM_EN_P1V8 PM_EN_PVDDQ PM_EN_PVCCPCH PM_EN_P1VS5GTD PM_EN_P5VS0 0201 XDP_PWR:YES R7893 64 60 0 0201 72 66 60 59 39 26 14 (ENVR1) (ENVR2) (ENVR4) (ENVR5) MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE XDP_PWR:NO OUT 5% 1/20W MF 0201 WIRE-ORED WITH PMIC PCHPWROK OUTPUT PM_PGOOD_P3V3S5 PM_PGOOD_P5VS4 PM_PGOOD_PVDDQ PM_EN_S0_SW (PGVR5) PM_SLP_S0S3_L PM_PGOOD_P3V3S5 PM_PGOOD_PVCCIO PM_PGOOD_P1V00 1 1 PM_EN_P1VS3 XDP_PWR:YES 10% 10V X5R-CERM 0201 PM_SLP_S0_OD_L 72 69 68 64 63 61 60 58 44 OUT 58 (INV) RC DELAY TPAD REQUIRES 10US MINIMUM OFF TIME < 0.5V 6.04K E7 K9 K8 E6 F4 E8 J10 F5 PMIC_ENLVA 0201 R7890 PMIC_EN_P3V3S5 (1 OF 10) C7 58 10% 10V X5R-CERM 0201 5% 1/20W MF 0201 BGA PMIC_SHUTDOWN_L OUT 2.4UA CURRENT SOURCE AT VR CRITICAL SN650839ZAJ 201 PM_SLP_S4_L 5% 1/20W MF 201 U7800 PP3V3_LDO3V R7828 72 60 39 14 VDDPG 2.2UF 60 40 39 PM_EN_P3V3S5 47K C7805 60 NC 1% 1/20W MF 201 72 68 60 39 14 PM_EN_P5VS5 PP3V3_S5 72 69 68 64 63 61 60 58 44 174K 0.1% 1/20W MF 0201 MAKE_BASE=TRUE NC IN PM_EN_PVXS5 R7868 XDP_PRESENT_L 0.1UF SOT886 SOT891 IN C7894 (S4# OR XDP) 74AUP1T97GM NOSTUFF SSD_PWR_REQ IN U7892 =PP3V3_SUS_XDP XDP_PWR:YES NOSTUFF L8 D 60 19 5% 1/20W MF 0201 72 60 17 PMIC_VSF 74LVC1G32 69 60 17 XDP_PWR:YES VDDLV 60 D1 PP1V8_S0 67 64 63 51 50 48 72 69 U7890 PMIC_EN_P3V3S5 KEEP THESE RAILS ON WHEN USING XDP 10% 10V X5R-CERM 0201 OPTIONAL: DIVIDE 1.8V FOR 1.5V INPUT 1 0.1UF 0.1UF 10% 10V X5R-CERM 0201 69 68 53 52 51 47 42 41 28 19 72 ECVCC L1 U7800 70 B SN650839ZAJ BGA (8 OF 10) 60 40 39 PP3V3_LDO3V FOR REPROGRAMMING OTP CONTENTS R7830 C7824 PP5VR7V_VPROGOTP 2.2UF 20% E1 M13 0402 AGND_PMIC 0V => 0X30/31 60 VDDIO0 VDDIO1 62 61 60 I2C BUS ADDRESS PP3V3_LDO3V 3.3V => 0X32/33 NOSTUFF NOSTUFF R78391 FLOAT => 0X34/35 R7838 3.3K 3.3K 5% 1/20W MF 201 5% 1/20W MF 201 NOSTUFF R7832 5% 1/20W MF 0201 PP5V_LDO5V 60 61 62 5% 1/20W MF 0201 CAP AT D1 25V X6S-CERM D3 CRITICAL CRITICAL PPBUS_G3H SN650839ZAJ 42 IN =SMBUS_SMC_PMIC_SCL A 62 61 60 68 60 58 IN PM_PGOOD_P5VS4 60 63 60 58 53 50 43 72 69 68 R7833 R7834 AGND_PMIC PPBUS_G3H 0201 SMB_PMIC_SDA 0201 SMB_PMIC_SCL J1 SCLK PMIC_SLVADDR L3 SLAVEADDR PMIC_EN3V3SW K3 EN3V3SW 100K 4.7K 201 PMIC_EN5VSW PP5V_S4 58 54 72 69 64 63 PPBUS_PMIC R7835 201 N5 M8 0201 CRITICAL C7843 2.2UF GND M5 CRITICAL C7844 2.2UF 20% 25V X6S-CERM 0402 20% 25V X6S-CERM 0402 N6 SDA EN5VSW AGND_PMIC TEMP_ALERT* L2 VOUT3V3SW M7 LDO3V N8 PP3V3_LDO3V VREF1V25 B1 PP1V25_VREF LDO5V N7 PP5V_LDO5V PMIC_SYSPWROK 0201 60 PPBUS_PMIC VINPP SYS_PWROK F1 G1 BAT1 BAT2 PCH_PWROK E11 PMIC_PCH_PWROK 0201 ALL_SYS_PWRGD G11 PMIC_ALLSYSPGD 0201 RSMRST_L_PWRGD J11 PMIC_RSMRST_L 0201 PMIC_INT* D12 PMIC_INT_L 0201 PMIC_VDCSNS E2 ACIN G3 VDCSNS H9 R7813 150K 0V = HIGH FSW (2 CELL) 3.3V = LOW FSW (3 CELL) EC_RST* J3 EC_ONOFF* K4 PCH_PWRBTN* K2 NVDC* C7837 2.2UF VINLDO3 60 61 62 NC K12 ACSWON* J2 BAT1SWON* BAT2SWON* F2 G2 20% 25V X6S-CERM 0402 CRITICAL C7838 0.47UF 10% 10V X7R 0402 CRITICAL C7839 2.2UF 20% 25V X6S-CERM 0402 PM_PCH_SYS_PWROK OUT 14 39 59 60 PM_PCH_PWROK OUT 14 19 60 ALL_SYS_PWRGD OUT 39 60 72 PM_RSMRST_L OUT 14 17 39 60 68 SMC_PMIC_INT_L OUT 39 40 AGND_PMIC MAKE_BASE=TRUE (PULL-UP AT SMC) PMIC_VCCST_PGD PP3V3_S5G CPU_VCCST_PWRGD 5% 1/20W MF 0201 60 61 62 64 63 60 59 54 49 46 45 42 38 69 CRITICAL C7840 60 59 39 14 2.2UF 60 19 14 20% 25V X6S-CERM 0402 AGND_PMIC OUT (PU AT PCH) 14 DESIGN: X502/MLB_CATZ LAST CHANGE: Thu Aug 21:00:42 2016 SYNC_MASTER=PAULM 60 61 62 72 60 39 68 60 39 17 14 PM_PCH_SYS_PWROK PM_PCH_PWROK ALL_SYS_PWRGD PM_RSMRST_L R7841 R7842 R7846 R7847 1 1 2 2 PP3V3_S0 100K 100K 10K 4.7K SYNC_DATE=06/15/2015 PAGE TITLE PMIC IC & Power Control 5% 201 5% 201 5% 201 5% 201 60 61 62 BOM_COST_GROUP=PLATFORM POWER 54 DRAWING NUMBER Apple Inc 051-02265 REVISION R NOTICE OF PROPRIETARY PROPERTY: MAKE_BASE=TRUE OUT R7803 VCCST_PWRGD E4 60 R7804 R7805 R7806 R7807 R7808 (SMC DRIVES DPWROK TO PCH) 72 69 64 60 CRITICAL VIN5VSW VIN K11 PM_EN_CPUVCC NC H11 AGND_PMIC 62 61 60 AGND1 AGND2 AGND3 AGND4 OUT =SMBUS_SMC_PMIC_SDA 1HZ PWRBTNIN DPWROK BGA H1 K13 E5 U7800 DS3_VREN H2 1% 1/20W MF 201 C1 K1 L13 D13 42 1M 1% 1/20W MF 201 (7 OF 10) R7836 R7837 ACOK PP3V3_LDO3V R7812 72 69 68 63 60 58 53 50 43 D11 60 NOSTUFF VDD5_VPROGOTP 60 SMC_PM_G2_EN IN THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED SIZE 1.0.0 BRANCH PAGE 78 OF 500 SHEET 60 OF 73 D A V12 (VCCPCH (1V / 0.7V PRIM_CORE)) (BANJO VR5) PPBUS_G3H_CPU 63 62 61 59 57 56 55 54 43 PP3V1_RTC 69 CRITICAL C7900 CRITICAL C7901 2.2UF 33UF C7902 1UF 2.2UF 20% 25V X6S-CERM 0402 20% 16V TANT CASE-B1S CRITICAL 20% 25V X6S-CERM 0402 V3P3A_RTC C13 C7922 20% 10V X6S-CERM 0201 C7903 1000PF 10% 25V X7R 0201 U7800 B13 VBATTBKUP D BGA J4 VCOMP 0.1UF NC0 NC1 NC2 NC3 (10 OF 10) 20% 16V X6S-CERM 0201 M3 72 VBSTVR5 BANJO_VBSTVR5 AGND_PMIC BANJO_ILIMVR5LS 62 61 60 1% 1/20W MF 201 60 OUT PM_PGOOD_PVCCPCH K5 ILIMVR5HS L5 ILIMVR5LS BANJO_ENVR5 IN PM_EN_PVCCPCH N3 R7903 AGND TG DIDT=TRUE GATE_NODE=TRUE TGR VSW BANJO_SWVR5 NOSTUFF 5% 1/16W MF-LF 402 FBVR5+ G4 FBVR5- L4 IHLP2020BD-PIHA052D-COMBO 1 R7915 BANJO_DRVLVR5 BG DIDT=TRUE GATE_NODE=TRUE C7915 0.001UF C7909 63 69 72 C7908 10UF 1000PF 20% 4V X6S 0402 10 BANJO_FBVR5P 5% 1/20W MF 201 CRITICAL C7910 220UF 20% 2V ELEC SM-COMBO XW7910 SM R7910 BANJO_FBVR5_N 10% 50V CERM 402 1 PPVCCPCH_S5G CRITICAL 60 61 62 10% 25V X7R 0201 BANJO_SWVR5_SNUB DIDT=TRUE SWITCH_NODE=TRUE NOSTUFF XW7901 BANJO_FBVR5_P C7906 20% 4V X6S 0402 5% 1/10W MF-LF 603 SHORT-12L-1.25MM-SM CRITICAL 10UF 2.2 BANJO_PGNDVR5 5% 1/20W MF 0201 C BANJO_DRVHVR5 AGND_PMIC L7900 SWITCH_NODE=TRUE DIDT=TRUE 1UH-20%-11A-0.0127OHM R7909 DIDT=TRUE GATE_NODE=TRUE M2 ENVR5 5% 1/16W MF-LF 402 BANJO_DRVHVR5_R BANJO_SWVR5R BANJO_DRVLVR5_R M4 PGVR5 (VR5) 60 DRVHVR5 M1 SWVR5 N2 DRVLVR5 N4 DIDT=TRUE GATE_NODE=TRUE 7.68K2 VIN R7908 L7 VINVR5 CRITICAL Q3D DIDT=TRUE (6 OF 10) A1 A13 N1 N13 F6 F7 F8 G5 G6 G7 G8 H5 H6 H7 H8 J5 J6 J7 J8 K6 K7 5% 1/20W MF SWITCH_NODE=TRUE 201 SN650839ZAJ PGNDVR5 AGND_PMIC CSD58889Q3D R7902 62 61 60 Q7900 R7907 BGA HIGHSIDE OCP DISABLED IN OTP CRITICAL DIDT=TRUE SWITCH_NODE=TRUE U7800 PPBUS_G3H_CPU 63 62 61 59 57 56 55 54 43 BANJO_VBSTVR5_R PGND 72 CRITICAL D TRIP* H10 SN650839ZAJ SWITCH_NODE=TRUEDIDT=TRUE CRITICAL C7907 CRITICAL CRITICAL C7911 220UF 20% 2V ELEC SM-COMBO C XW7911 SM NO_XNET_CONNECTION=1 V8 (1.8V) (Banjo VR2) 72 69 68 64 63 60 58 44 PP3V3_S5 CRITICAL C7932 CRITICAL C7934 PPBUS_G3H_CPU 20% 25V X6S-CERM 0402 AGND_PMIC 62 61 60 10% 25V X7R 0201 20% 16V TANT CASE-B1S B C7962 1000PF 33UF 0402 U7800 2.2UF C7960 20% 6.3V CERM-X6S CRITICAL V4 (0.95V VCCIO) (BANJO VR3) C7933 PP5V_LDO5V 62 60 CRITICAL 10UF 20% 6.3V CERM-X6S 0402 20% 6.3V TANT-POLY CASE-B1S-1 CRITICAL C7930 10UF 150UF 63 62 61 59 57 56 55 54 43 CRITICAL SN650839ZAJ BGA CRITICAL (3 OF 10) F12 VINVR2_0 F13 VINVR2_1 SWVR2_0 H12 SWVR2_1 H13 L7930 0.47UH-20%-4.0A-28MOHM 72 BANJO_SWVR2 DIDT=TRUE SWITCH_NODE=TRUE E13 VREGVR2 1 PP1V8_S5G PIFE25201B-SM 0.1UF 2.2UF 20% 25V X6S-CERM 0402 20% 25V X6S-CERM 0402 (VR2) 20% 16V X6S-CERM 0201 72 R7932 BANJO_VBSTVR3_R SWITCH_NODE=TRUE DIDT=TRUE 60 U7800 SN650839ZAJ BGA R7962 62 61 60 AGND_PMIC 6.04K2 AGND_PMIC BANJO_ILIMVR3LS 62 61 60 G9 VINVR3 B11 72 VBSTVR3 DRVHVR3 A12 A11 72 SWVR3 DRVLVR3 A9 1% 1/20W MF 201 60 OUT BANJO_ENVR3 B9 PGVR3 E9 ENVR3 A R7963 IN PM_EN_PVCCIO 5% 1/20W MF 0201 A10 60 BANJO_VBSTVR3 5% 1/16W MF-LF 402 BANJO_SWVR2_SNUB DIDT=TRUE SWITCH_NODE=TRUENOSTUFF 10% 50V CERM 402 R7931 BANJO_DRVHVR3_R BANJO_SWVR3R BANJO_DRVLVR3_R 5% 1/16W MF-LF 402 BANJO_DRVHVR3 L7960 TG DIDT=TRUE GATE_NODE=TRUE TGR VSW DIDT=TRUE BANJO_SWVR3 NOSTUFF 5% 1/16W MF-LF 402 BANJO_DRVLVR3 BG DIDT=TRUE GATE_NODE=TRUE XW7961 5% 1/20W MF 201 PPVCCIO_S0G IHLP2020BD-PIHA052D-COMBO R7975 4V X6S 0402 XW7935 SM CRITICAL C7969 10UF 20% 4V X6S 0402 C7970 1000PF 10% 25V X7R 0201 10 BANJO_FBVR2_P 5% 1/20W MF 201 63 69 72 100 2BANJO_FBVR2_N 2 20% 2.5V X6S-CERM 0402 CRITICAL C7935 100UF IN C7937 100UF 20% 6.3V TANT-POLY CASE-A3-LLP 72 C7931 0.01UF 10% 10V X7R-CERM 0201 C7975 1 CRITICAL C7965 220UF 20% 2V ELEC SM-COMBO CRITICAL SYNC_MASTER=PAULM SYNC_DATE=06/15/2015 PAGE TITLE C7966 PMIC VCCPCH VCCIO 1.8V 220UF 20% 2V ELEC SM-COMBO DRAWING NUMBER Apple Inc 051-02265 REVISION R CRITICAL DESIGN: X502/MLB_CATZ LAST CHANGE: Thu Aug 21:00:42 2016 IN C7939 20UF 20% 6.3V TANT-POLY CASE-A3-LLP BANJO_FBVR2_RC XW7936 SM 1 CRITICAL 1% 1/20W MF 201 NOTICE OF PROPRIETARY PROPERTY: BOM_COST_GROUP=PLATFORM POWER 1% 1/20W MF 201 R7936 BANJO_SWVR3_SNUB DIDT=TRUE GATE_NODE=TRUE NOSTUFF 10% 50V CERM 402 CPU_VCCIOSENSE_P CPU_VCCIOSENSE_N C7968 20% 5% 1/10W MF-LF 603 72 CRITICAL 10UF 0.001UF R7970 10 2.2 SHORT-12L-1.25MM-SM 1 R7969 BANJO_FBVR3RP BANJO_PGNDVR3 100 SWITCH_NODE=TRUE DIDT=TRUE 1UH-20%-11A-0.0127OHM 20% 2.5V X6S-CERM 0402 0.001UF R7935 C7938 20UF C7945 CRITICAL CRITICAL 72 VIN R7968 PGNDVR3 (VR3) FBVR3+ C10 FBVR3- D7 2.2 BANJO_FBVR2R_P BANJO_FBVR2R_N Q3D DIDT=TRUE GATE_NODE=TRUE PM_PGOOD_PVCCIO 5% 1/20W MF 0201 CSD58889Q3D DIDT=TRUE GATE_NODE=TRUE D10 ILIMVR3HS C9 ILIMVR3LS FBVR2+ G10 FBVR2- E10 10% 25V X7R 0201 Q7960 SWITCH_NODE=TRUE DIDT=TRUE (4 OF 10) HIGHSIDE OCP DISABLED IN OTP CRITICAL 5% 1/20W MF 201 PGND 63 62 61 59 57 56 55 54 43 PM_EN_P1V8 R7967 CRITICAL PPBUS_G3H_CPU IN PGNDVR2_0 C7964 BANJO_ENVR2 E12 PGVR2 F11 ENVR2 G13 2.2UF PM_PGOOD_P1V8 PGNDVR2_1 C7967 OUT G12 C7963 60 CRITICAL CRITICAL B 1000PF R7945 CRITICAL C7936 NOSTUFF 59 64 67 69 72 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED SIZE 1.0.0 BRANCH PAGE 79 OF 500 SHEET 61 OF 73 D A CRITICAL C8060 CRITICAL C8061 2.2UF 33UF CRITICAL C8062 2.2UF 20% 25V X6S-CERM 0402 20% 16V TANT CASE-B1S 20% 25V X6S-CERM 0402 C8063 1000PF 10% 25V X7R 0201 D C8067 CRITICAL DIDT=TRUE SWITCH_NODE=TRUE 20% 16V X6S-CERM 0201 72 CRITICAL BANJO_VBSTVR1_R R8067 20% 25V X6S-CERM 0402 SN650839ZAJ BGA M11 72 VBSTVR1 R8066 6.04K2 BANJO_ILIMVR1 DRVHVR1 N12 SWVR1 N11 DRVLVR1 N9 L9 ILIMVR1 1% 1/20W MF 201 OUT M9 PGVR1 M12 ENVR1 BANJO_ENVR1 (VR1) 64 60 IN PM_EN_P1V00 N10 R8068 2 5% 1/16W MF-LF 402 DIDT=TRUE GATE_NODE=TRUE BANJO_DRVHVR1_R BANJO_SWVR1R BANJO_DRVLVR1_R BANJO_DRVHVR1 DIDT=TRUE BANJO_SWVR1 NOSTUFF TG GATE_NODE=TRUE TGR VSW 5% 1/16W MF-LF 402 BANJO_DRVLVR1 DIDT=TRUE BG GATE_NODE=TRUE XW8061 R8069 NO_XNET_CONNECTION=1 2.2 CRITICAL C8070 220UF 19 63 64 69 72 CRITICAL C8071 220UF 20% 2V ELEC SM-COMBO 5% 1/10W MF-LF 603 20% 2V ELEC SM-COMBO BANJO_SWVR1_SNUB DIDT=TRUE SWITCH_NODE=TRUE NOSTUFF C8069 0.001UF 10% 50V CERM 402 CRITICAL C8075 10UF 10 BANJO_FBVR1P 5% 1/20W MF 201 CRITICAL C8076 C8077 10UF 20% 4V X6S 0402 XW8070 SM R8070 5% 1/20W MF 0201 20% 4V X6S 0402 1000PF 10% 25V X7R 0201 XW8071 SM BANJO_FBVR1_N C 44 PP1V_S5G BANJO_FBVR1_P BANJO_PGNDVR1 PP1V_S5G_REG IHLP2020BD-PIHA052D-COMBO SHORT-12L-1.25MM-SM OUT 1% 1W CYN 0612-SHORT-1 R8063 FBVR1+ K10 FBVR1- J9 PGNDVR1 60 BANJO_VBSTVR1 DIDT=TRUE GATE_NODE=TRUE PM_PGOOD_P1V00 44 0.003 L8060 SWITCH_NODE=TRUE DIDT=TRUE 1UH-20%-11A-0.0127OHM VIN R8062 DIDT=TRUE SWITCH_NODE=TRUE (2 OF 10) M10 VREGVR1 AGND_PMIC 5% 1/20W MF 201 OUT R8060 CRITICAL Q3D U7800 AGND_PMIC 62 61 60 Q8060 CSD58889Q3D 2.2UF OMIT CRITICAL PGND C8065 CRITICAL CRITICAL DIDT=TRUE SWITCH_NODE=TRUE ISNS_1VS5G_P ISNS_1VS5G_N SHORT RSENSE PP5V_LDO5V D V11 (1V) (Banjo VR1) 0.1UF 62 61 60 PPBUS_G3H_CPU 63 62 61 59 57 56 55 54 43 62 61 60 C NO_XNET_CONNECTION=1 V13 (0.6V) (Banjo LDO1) PP1V2_S3 CRITICAL CRITICAL C8090 10UF CRITICAL C8091 U7800 10UF 20% 4V X6S 0402 20% 4V X6S 0402 SN650839ZAJ BGA (9 OF 10) A6 B6 XW8090 PP1V2_S3 BANJO_VINLDO1S F9 VINLDO1S PPBUS_G3H_CPU CRITICAL C8030 33UF C8031 C8036 1000PF 33UF 20% 16V TANT CASE-B1S B CRITICAL A7 10% 20% 16V TANT CASE-B1S 25V X7R FBLDO1 D8 10 CRITICAL C8035 AGND_PMIC 1% 1/20W MF 201 IN BANJO_ILIMVR4 PM_MEMVTT_EN R8034 OUT 62 61 60 AGND_PMIC D4 DDRID E3 DDR_VTT_CTRL PMIC_VTT_CTRL B5 PGVR4 C2 ENVR4 R8033 IN PM_EN_PVDDQ 5% 1/20W MF 0201 BANJO_ENVR4 R80322 VIN R8036 5% 1/16W MF-LF 402 BANJO_DRVHVR4 DIDT=TRUE TG TGR GATE_NODE=TRUE VSW R8039 5% 1/16W MF-LF 402 BANJO_DRVLVR4 DIDT=TRUE BG GATE_NODE=TRUE XW8031 SHORT-12L-1.25MM-SM 20% 2V X6S 0402 15UF 20% 2V X6S 0402 CRITICAL BANJO_SWVR4 NOSTUFF PP1V2_S3_REG PILA062D-SM-COMBO R8038 BANJO_FBVR4_P 2.2 5% 1/10W MF-LF 603 BANJO_SWVR4_SNUB DIDT=TRUE SWITCH_NODE=TRUE NOSTUFF C8040 270UF 44 OUT 44 20% 2V TANT CASE-B 20% ELEC SM-COMBO C8041 20% 2V TANT CASE-B C8043 2V CRITICAL 270UF 220UF 10% 50V CERM 402 10 CRITICAL CRITICAL 0.001UF 1 1 BANJO_FBVR4P 20% 2V X6S 0402 CRITICAL NOSTUFF C8042 270UF 20% 2V TANT CASE-B CRITICAL C8044 220UF 20% 2V ELEC SM-COMBO CRITICAL C8045 10UF 20% 4V X6S 0402 PP1V2_S3 15UF 20% 2V X6S 0402 CRITICAL C8099 B 15UF 20% 2V X6S 0402 1 1000PF 10% 25V X7R 0201 CRITICAL C8046 10UF 20% 4V X6S 0402 SYNC_MASTER=PAULM PAGE TITLE SYNC_DATE=06/15/2015 PMIC 1.2V 1.0V 0.6V DRAWING NUMBER Apple Inc 051-02265 REVISION R NOTICE OF PROPRIETARY PROPERTY: BOM_COST_GROUP=PLATFORM POWER DESIGN: X502/MLB_CATZ LAST CHANGE: Thu Aug 21:00:42 2016 NO_XNET_CONNECTION=1 62 63 64 69 C8047 XW8041 SM BANJO_FBVR4_N 15UF XW8040 SM 5% 1/20W MF 201 AGND_PMIC NO_XNET_CONNECTION=1 C8038 OUT 1% 1W CYN 0612-SHORT-1 R8040 5% 1/20W MF 201 C8098 C8094 0.003 L8030 SWITCH_NODE=TRUE DIDT=TRUE 0.56UH-20%-19A-0.0065OHM BANJO_PGNDVR4 100K 62 61 60 C8097 15UF R8030 CRITICAL Q3D BANJO_DRVHVR4_R BANJO_SWVR4R BANJO_DRVLVR4_R FBVR4+ C3 FBVR4- D5 A4 60 Q8030 DIDT=TRUE GATE_NODE=TRUE (VR4) A DRVHVR4 A2 SWVR4 A3 DRVLVR4 A5 (1V INPUT, 3.3V TOLERANT) PM_PGOOD_PVDDQ BANJO_VBSTVR4 DIDT=TRUE GATE_NODE=TRUE D2 ILIMVR4 0V = 1.2V LPDDR3 5% 1/20W MF 0201 68 60 B3 72 VBSTVR4 OMIT CRITICAL CSD58873Q3D DIDT=TRUE SWITCH_NODE=TRUE ISNS_1V2S3_P ISNS_1V2S3_N SHORT RSENSE CRITICAL 5% 1/20W MF 201 BGA B4 VREGVR4 SWITCH_NODE=TRUE DIDT=TRUE SN650839ZAJ BANJO_FBLDO1_R 1 C8096 20% 16V X6S-CERM 0201 R8037 U7800 69 72 CRITICAL 0.1UF PGNDVR4 62 61 60 11K C8037 BANJO_VBSTVR4_R (5 OF 10) R8031 72 DIDT=TRUE SWITCH_NODE=TRUE CRITICAL 20% 25V X6S-CERM 0402 AGND_PMIC 20% 25V X6S-CERM 0402 CRITICAL 2.2UF 62 61 60 C8034 2.2UF 20% 25V X6S-CERM 0402 PP5V_LDO5V 62 61 60 CRITICAL 5% 1/20W MF 201 PGND 2.2UF XW8095 SM R8095 C8033 CRITICAL CRITICAL 0201 CRITICAL 20% 2V X6S 0402 BANJO_FBLDO1 1 C8095 15UF PGNDLDO1_0 V10 (1.2V VDDQ) (Banjo VR4) 63 62 61 59 57 56 55 54 43 CRITICAL SHORT-12L-0.1MM-SM PGNDLDO1_1 69 64 63 62 PPVTT_S0 A8 B8 VOUTLDO1_0 VOUTLDO1_1 VINLDO1_0 VINLDO1_1 B7 69 64 63 62 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED SIZE 1.0.0 BRANCH PAGE 80 OF 500 SHEET 62 OF 73 D A 69 64 63 62 PP1V2_S3 69 64 63 62 CRITICAL C8100 12PF 5% 25V CERM 0201 72 69 68 64 63 61 60 58 44 C8110 5% 25V CERM 0201 63 62 61 59 57 56 55 54 43 C8120 3PF +/-0.1PF 25V C0G 0201 C8130 3PF +/-0.1PF 25V C0G 0201 NOSTUFF C8140 5% 25V CERM 0201 NOSTUFF C8150 5% 25V CERM 0201 C8160 12PF 5% 25V CERM 0201 72 69 55 45 C8131 3PF 3PF +/-0.1PF 25V C0G 0201 +/-0.1PF 25V C0G 0201 C8141 C8170 C8161 3PF +/-0.1PF 25V C0G 0201 C8171 +/-0.1PF 25V C0G 0201 72 69 67 64 63 45 44 43 41 C8181 72 69 64 63 60 58 54 C8191 PP1V8_S0 5% 25V CERM 0201 72 69 67 64 63 60 51 50 48 CRITICAL C81A0 2.9PF +/-0.05PF 25V C0G-CERM 0201 C8192 CRITICAL C81A1 C8144 C8163 C8164 +/-0.1PF 25V C0G 0201 72 69 61 C8165 3PF C8166 5% 25V CERM 0201 C8176 12PF 5% 25V CERM 0201 C8185 3PF +/-0.1PF 25V C0G 0201 C8193 PP5V_S4 3PF C8194 12PF +/-0.1PF 25V C0G 0201 5% 25V CERM 0201 72 69 67 64 63 45 44 43 41 1 +/-0.1PF 25V C0G 0201 C81A5 C8168 5% 25V CERM 0201 C8177 PP3V3_S4 NOSTUFF C8138 C8178 5% 25V CERM 0201 27 C8187 C8188 12PF 5% 25V CERM 0201 0201 C8149 +/-0.1PF 25V C0G 0201 C PP5V_S5 69 64 63 C8159 69 64 63 3PF PP5V_S5 C8154 3PF +/-0.1PF 25V C0G 0201 C8156 3PF +/-0.1PF 25V C0G 0201 +/-0.1PF 25V C0G 0201 C8169 3PF +/-0.1PF 25V C0G 0201 PP3V3_S5_SSD_SNS C8179 3PF +/-0.25PF 25V C0G 0201 B PP3V3_S5 72 69 68 64 63 61 60 58 44 C8174 3.5PF +/-0.1PF 25V C0G 0201 C8189 3PF C8180 3PF +/-0.1PF 25V C0G 0201 +/-0.1PF 25V C0G 0201 72 69 64 63 60 58 54 C8199 PP5V_S4 3PF C8196 12PF +/-0.1PF 25V C0G 0201 5% 25V CERM 0201 C8198 3PF +/-0.1PF 25V C0G 0201 PP3V3_S0 NOSTUFF C81A8 3PF +/-0.1PF 25V C0G 0201 +/-0.1PF 25V C0G 3PF C81A7 C8139 3PF +/-0.1PF 25V C0G 0201 PP5V_S5 C8197 69 64 60 59 54 49 46 45 42 38 3PF PP0V9_TBT_X_SVR 69 64 63 NOSTUFF C8136 69 12PF +/-0.1PF 25V C0G 0201 PP3V3_S4 67 64 63 45 44 43 41 72 69 PP3V3_S5 3PF +/-0.25PF 25V C0G 0201 0201 12PF 3PF +/-0.1PF 25V C0G PP3V3_TBT_X_S0 72 69 68 64 63 61 60 58 44 PP3V3_S4_WLS 3.5PF +/-0.05PF 25V C0G-CERM 0201 C8158 +/-0.1PF 25V C0G 0201 72 69 44 3PF PPBUS_G3H_CPU 3PF +/-0.1PF 25V C0G 0201 C81A3 C8148 3PF +/-0.1PF 25V C0G 0201 3PF C8129 PPBUS_G3H_CPU C8167 PP5V_S4 C8195 PP3V3_S4 C8157 +/-0.1PF 25V C0G 0201 72 69 64 63 60 58 54 72 69 67 64 63 45 44 43 41 5% 25V CERM 0201 3PF +/-0.1PF 25V C0G 0201 0201 12PF 3PF +/-0.1PF 25V C0G PP1V_S5G 63 62 61 59 57 56 55 54 43 PPBUS_G3H D 3PF +/-0.1PF 25V C0G 0201 +/-0.1PF 25V C0G 0201 C8119 3PF 3PF 1 C8147 PP3V3_UPC_XB_LDO 72 69 68 60 58 53 50 43 5% 25V CERM 0201 28 12PF +/-0.1PF 25V C0G 0201 C8183 C8128 C8137 PP3V3_S4 0201 12PF +/-0.1PF 25V C0G 0201 PPBUS_SSD_FLT C8175 PP1V2_S3 3PF +/-0.25PF 25V C0G PPVBAT_G3H_CONN +/-0.25PF 25V C0G 0201 3PF +/-0.1PF 25V C0G 0201 C8127 3.5PF 3PF C8118 +/-0.1PF 25V C0G 0201 63 53 52 C8109 3.5PF 3PF +/-0.1PF 25V C0G 0201 69 30 28 2.9PF +/-0.05PF 25V C0G-CERM 0201 PPVCCIO_S0G C8173 PP1V8_S0 5% 25V CERM 0201 +/-0.1PF 25V C0G 0201 3PF C8146 12PF 72 69 67 64 63 45 44 43 41 3PF +/-0.1PF 25V C0G 0201 NOSTUFF +/-0.1PF 25V C0G 0201 3PF 1 C8155 PP3V3_S4 63 62 61 59 57 56 55 54 43 3PF 72 69 67 64 63 45 44 43 41 C8117 PP1V2_S3 PPBUS_G3H_CPU +/-0.1PF 25V C0G 0201 3PF +/-0.1PF 25V C0G 0201 3PF C8108 3PF 67 C8153 1 C8145 PP1V8_S3 +/-0.1PF 25V C0G 0201 PP3V3_S4 3PF 72 69 64 63 62 19 3.0PF 3PF PP1V_S5G C8135 +/-0.1PF 25V C0G 0201 +/-0.1PF 25V C0G 0201 2.9PF NOSTUFF 3PF +/-0.1PF 25V C0G 0201 69 64 63 62 5% 25V CERM 0201 72 69 64 63 60 58 54 12PF +/-0.1PF 25V C0G 0201 C8126 +/-0.1PF 25V NP0-C0G 0201 12PF +/-0.1PF 25V C0G 0201 PP5V_S4 3PF 72 69 67 64 63 60 51 50 48 C8182 +/-0.1PF 25V C0G 0201 PPBUS_G3H_CPU 3PF C8116 63 62 61 59 57 56 55 54 43 3PF 72 69 64 63 62 19 C8107 PPVBAT_G3H_CHGR_R 3PF PP1V2_S3 69 64 63 62 3PF +/-0.1PF 25V C0G 0201 5% 25V CERM 0201 C8143 PP3V3_S4 3PF 63 62 61 59 57 56 55 54 43 C8172 3PF +/-0.1PF 25V C0G 0201 PPVCCGT_S0G 3PF C8162 5% 25V CERM 0201 72 69 63 57 45 PPVCCGT_S0G C8152 12PF +/-0.1PF 25V C0G 0201 12PF +/-0.1PF 25V C0G 0201 C8125 PP5V_S4 5% 25V CERM 0201 +/-0.1PF 25V C0G 0201 C8134 C8106 12PF 63 53 CRITICAL 72 69 67 64 63 45 44 43 41 3.5PF PP1V8_S3 +/-0.1PF 25V C0G 0201 C8115 FREQUENCY SPECIFIC PP1V8_S0 3PF PP3V3_TBT_X_LC 3PF C8133 69 64 63 60 +/-0.1PF 25V C0G 0201 63 28 27 C8142 3PF +/-0.1PF 25V C0G 0201 C8124 +/-0.1PF 25V C0G 0201 72 69 67 64 63 60 51 50 48 3PF +/-0.25PF 25V C0G 0201 3PF +/-0.1PF 25V C0G 0201 PP1V2_S3 3PF NOSTUFF 5% 25V CERM 0201 C8151 3PF 3PF PPVBAT_G3H_CHGR_R 69 64 63 62 12PF +/-0.1PF 25V C0G 0201 C8123 PP1V2_S3 3PF C8132 C8114 72 69 64 63 60 58 54 +/-0.25PF 25V C0G 0201 63 53 C8105 +/-0.1PF 25V C0G 0201 3.5PF +/-0.25PF 25V C0G 0201 PP5V_S4 3.5PF C8104 +/-0.1PF 25V C0G 0201 C8113 PPVCCCPU_S0G PPVCCPCH_S5G 72 69 63 57 45 5% 25V CERM 0201 PP3V3_TBT_X_LC B 12PF +/-0.25PF 25V C0G 0201 C8122 69 64 63 60 3PF +/-0.1PF 25V C0G 0201 PP1V2_S3 3PF PPDCIN_G3H 69 64 63 62 12PF 72 69 61 C8121 3.5PF C8112 5% 25V CERM 0201 72 69 68 53 C8103 72 69 64 63 60 58 54 12PF +/-0.1PF 25V C0G 0201 PP5V_S4 PP1V8_S3 63 28 27 C8111 3PF C8102 +/-0.1PF 25V C0G 0201 69 64 63 62 12PF 69 64 63 60 +/-0.1PF 25V C0G 0201 69 64 63 62 3PF PP1V2_S3 C 3PF PP1V2_S3 PPVBAT_G3H_CONN 69 64 63 62 C8101 PPBUS_G3H_CPU 63 53 52 CRITICAL 72 69 64 63 60 58 54 12PF D PP3V3_S5 +/-0.1PF 25V C0G 0201 NOSTUFF C81A9 3PF +/-0.1PF 25V C0G 0201 DESIGN: X502/MLB_CATZ LAST CHANGE: Thu Aug 21:00:42 2016 A SYNC_MASTER=PAULM SYNC_DATE=06/15/2015 PAGE TITLE RAIL DESENSE CAPS DRAWING NUMBER Apple Inc 051-02265 REVISION R NOTICE OF PROPRIETARY PROPERTY: BOM_COST_GROUP=PLATFORM POWER THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED SIZE 1.0.0 BRANCH PAGE 81 OF 500 SHEET 63 OF 73 D A PP1V8_S0 U8200 K VIN1 PM_EN_P1V8S0 ON1 12 CT1 P1V8S3SW_CT1 PP5V_S5 69 64 63 D (IBIAS 540US TPS22968 Type LOAD SWITCH - DUAL R(on) @ 5V VBIAS 25 MOHM TYP 38 MOHM MAX Current 4A MAX 1MS MAX S R8260 5% 1/20W MF 0201 @ 1.8V PP5V_S5 69 64 63 (IBIAS 1700US LOAD SWITCH - DUAL R(on) @ 5V VBIAS 18 MOHM TYP 27 MOHM MAX Current 6A MAX TON-TOTAL Current 2.5A MAX TON-TOTAL 39US MAX @ 1V 12 C8230 0.1UF 10% 10V X5R-CERM 0201 D S C CRITICAL C8233 Part SLG5AP1635V Type Load Switch R(on) @ 25C 10UF 20 MOHM TYP 28 MOHM MAX 20% 4V X6S Current 2.5A MAX TON-TOTAL 39US MAX @ 1V 0402 PP1V_S3 64 69 EDP: 0.24A 1V S0G CPU SWITCH (VCCSTG) 69 64 63 Type 20 MOHM TYP 28 MOHM MAX U8230 PP1V_S5G GND 100PF U8210 TPS22966 @ 25C MAKE_BASE=TRUE EDP: TBD STDFN C8232 54 55 56 57 59 69 72 Part Load Switch NOSTUFF U8250 CT2 1000PF 10% 25V X7R 0201 PP5V_S0 Type FAST TURN ON: < 64US GND VOUT2 11 C8210 PM_EN_P1VS3 41 43 44 45 63 67 69 72 SLG5AP1635V R(on) SLG5AP1635V IN Part PP1V_S5G_FUSE 69 64 PP5V_S5 PP1V_S3 C8250 0.1UF PP5V_S5 69 64 63 72 69 64 63 62 19 5% 25V C0G 0201 THRM PAD P3V3S4SW_CT1 S U8230 CRITICAL 15 IN PM_EN_P3V3S4 U8230 C8280 GND 4A MAX PP3V3_S4 D D 69 5% 1/20W MF 0201 VDD 60 VOUT1 13 65US MAX @ 1V EDP: 2.1A 0201 U8210 60 P1VS3CPUSW_RAMP DPU-THICKSTNCL CRITICAL PP5V_S5 69 64 63 TPS22966 VIN1 ON 25 MOHM TYP 38 MOHM MAX 1.4MS MAX PP1V_S5GTD 1V S3 SWITCH (VCCST, VCCPLL) LOAD SWITCH - DUAL TON-TOTAL TPS22968 Part Current PP3V3_S5 CAP 5% 25V C0G 0201 U8205 RISE TIME: 3.3V, 1000PF ==> 930US STDFN 100PF R(on) @ 5V VBIAS 72 69 68 64 63 61 60 58 44 PM_EN_P1V00 IN C8282 VOUT2 TON-TOTAL 5% 1/20W MF 0201 SLG5AP1635V CRITICAL VBIAS VIN2 5% 1/20W MF 0201 10% U8280 60 69 72 CT1 6A MAX 10V X5R-CERM 12 P3V3S5GSW_CT1 Current ON1 PP3V3_S5G 7.4 MOHM TYP 10.6 MOHM MAX VOUT1 13 THRM PAD IN PM_EN_P3V3S5G DPU-THICKSTNCL @ 25C @ 70C R8262 0.1UF VDD 15 60 VIN1 Load Switch PP1V_S5G 72 69 64 63 62 19 PP5V_S5 69 64 63 U8205 Type 1V S5G FUSE (FOR FAST TURN OFF) TPS22968 PP3V3_S5 SLG5AP1643V R8261 MIN_LINE_WIDTH=0.1200 MIN_NECK_WIDTH=0.1500 72 69 68 64 63 61 60 58 44 VOLTAGE=1V GND Part TON-TOTAL VMPHY:SWITCHED ON CRITICAL S 10% 25V X7R D D Part R(on) R(on) VMPHY:EQUAL_SUS VMPHY:EQUAL_SUS VMPHY:EQUAL_SUS U8260 TDFN 60 C8263 10UF PP5V_S5 VMPHY:SWITCHED PMEG3010EB/S500 PP1V8_S3 VOUT2 A U8260 CRITICAL 62 63 64 69 ENSURE 1.8V RAIL IS ALWAYS ABOVE 1.2V MINUS 0.2V D8230 SOD523 VBIAS 1000PF 10% PMEG3010EB/S500 K GND VOUT1 13 CRITICAL 11 C8200 DPU-THICKSTNCL PP1V_S5G IN THRM PAD 60 PP1V8_S5G 15 72 69 67 61 59 1V S5GTD SWITCH (VCCMPHYGT,VCCSRAM,VCCAPLLEBB) 48 50 51 60 63 67 69 72 PP1V2_S3 A 72 69 64 63 62 19 D8231 SOD523 TPS22968 10% VDD 10V X5R-CERM U8250 0201 CRITICAL C8253 10UF 1.7MS MAX @ 3,3V 2.4MS MAX @ 5V 60 IN PM_EN_P1VS0G CAP ON STDFN CRITICAL C8252 D S PP1V_S0G MIN_LINE_WIDTH=0.5000 MIN_NECK_WIDTH=0.1500 GND Type Load Switch R(on) @ 25C 0402 B 20 MOHM TYP 28 MOHM MAX Current 2.5A MAX TON-TOTAL 39US MAX @ 1V 69 EDP: 0.04A 100PF SLG5AP1635V 20% 4V X6S SLG5AP1635V P1VS0GCPUSW_RAMP Part 5% 25V C0G 0201 SHORT RSENSE OMIT 1V2 S0G SWITCH (VCCPLL_OC) R8220 PP3V3_S5 TP_ISNS_3V3S0P TP_ISNS_3V3S0N 60 A IN U8220 VCCPLLOC:S3 TPS22920 PP3V3_S5_S0R A2 B2 C2 CSP VOUT VIN A1 B1 C1 PP3V3_S0 R8240 38 42 45 46 49 54 59 60 63 69 CRITICAL PM_EN_P3V3S0 U8220 GND C8220 1.0UF 20% 6.3V X5R 0201-1 SEE 5% 1/20W MF 0201 D2 ON D1 72 69 68 64 63 61 60 58 44 1% 1/3W MF 0306-SHORT Part 69 64 63 62 PP1V2_S3 TPS22904 TPS22920 Type A1 VIN Load Switch 5.3 MOHM TYP 9.8 MOHM MAX R(on) @ 3.6V Current 4A MAX TON-TOTAL 1.3MS MAX @ 3.6V PP1V2_S0G U8240 60 IN PM_EN_P1V2S0G VCCPLLOC:S0G C8240 1.0UF CSP DESIGN: X502/MLB_CATZ LAST CHANGE: Mon Aug 12:54:34 2016 69 EDP: 0.24A VOUT A2 CRITICAL VCCPLLOC:S0G B1 ON SYNC_MASTER=PAULM U8240 GND Part TPS22904 B2 0.005 Type Load Switch R(on) @ 1.2V 135 MOHM TYP 185 MOHM MAX Current 0.5A MAX TON-TOTAL 20US MAX @ 1.2V 20% 6.3V X5R 0201-1 PAGE TITLE Power FETs DRAWING NUMBER Apple Inc 051-02265 REVISION R NOTICE OF PROPRIETARY PROPERTY: BOM_COST_GROUP=PLATFORM POWER SYNC_DATE=06/15/2015 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED SIZE 1.0.0 BRANCH PAGE 82 OF 500 SHEET 64 OF 73 D A Page Notes PPVOUT_S0_LCDBKLT Power aliases required by this page: - =PPVIN_S0SW_LCDBKLTFET (9-12.6V LCD BACKLIGHT INPUT) - =PP5V_S0_BKLT (5V BACKLIGHT DRIVER INPUT) 65 66 72 PLACE_NEAR=D8410.K:5MM PLACE_NEAR=D8410.K:5MM PLACE_NEAR=D8410.K:5MM PLACE_NEAR=D8410.K:5MM PLACE_NEAR=D8410.K:5MM CRITICAL C8460 2.2UF 10% 100V X5R 1206 CRITICAL 0.025 F8400 3AMP-32V 65 PPVIN_S0SW_LCDBKLT_F 0603 107S00034 FDC638APZ_SBMS001 SSOT6-HF C8400 10% 1% 1/16W MF-LF 402 R8401 1000PF 43 43 OUT OUT PPVIN_S0SW_LCDBKLT_R ISNS_LCDBKLT_P 80.6K 16V X7R-1 0201 65 MIN_LINE_WIDTH=2.0000 MIN_NECK_WIDTH=0.2000 VOLTAGE=12.9V MAKE_BASE=TRUE NOSTUFF C8401 R8445 0 5% 1/16W MF-LF 402 C8440 VDDD 11 10 BKLT_SD 19 BKLT_SENSE_OUT PLATFORM_RESET NO LONGER GATES THE BKLT_EN AS BOTH COME FROM PCH NOW R8442 BKLT_EN_R NO STUFF C8442 LP8548B1SQ_-04 SD VSENSE_N VSENSE_P SW SW FB 65 GD SENSE_OUT 17 12 EN PWM_KEYB 15 16 SCL SDA D8410 C8411 C8412 0.1UF 10% 25V X6S-CERM 0603 10% 25V X5R 402 65 A 5% 10% 100V X5R 1206 C8462 2.2UF 10% 100V X5R 1206 CRITICAL C8463 2.2UF 10% 100V X5R 1206 CRITICAL C8464 2.2UF 10% 100V X5R D 1206 21 C8466 2.2UF 10% 100V X5R 1206 CRITICAL C8467 2.2UF 10% 100V X5R 1206 NC NC SW2 FB2 NC NC CRITICAL C8468 2.2UF 10% 100V X5R 1206 CRITICAL C8469 2.2UF 10% 100V X5R 1206 PLACE_NEAR=D8410.K:5MM PLACE_NEAR=D8410.K:5MM PLACE_NEAR=D8410.K:6.1MM PLACE_NEAR=D8410.K:5MM PLACE_NEAR=D8410.K:5MM PLACE_NEAR=D8410.K:6.1MM XW8410 SM PLACE_NEAR=D8410::2MM SI7812DN PWRPK-1212-8 GATE_NODE=TRUE DIDT=TRUE PLACE_NEAR=U8400.1:3MM CRITICAL C8470 2.2UF 10% 100V X5R 1206 R8431 CRITICAL C8471 2.2UF 10% 100V X5R 1206 CRITICAL C8472 2.2UF 10% 100V X5R 1206 CRITICAL C8473 2.2UF 10% 100V X5R 1206 C8477 C8478 C8479 +/-0.1PF 100V C0G 0201 5% 100V C0G 0201 +/-0.1PF 100V C0G 0201 5% 100V C0G 0201 12PF 3PF C8474 12PF 5% 100V CERM 0402 C8476 3PF 1 C8475 12PF 5% 100V CERM 0402 12PF C 18.2K 1% 1/16W MF-LF 402 Vout = 46V Typ, 55V Max Iout = 0.12A Typ, 0.15A Max Fs = 625kHz Typ (+/- 7%) LCDBKLT_FB LCDBKLT_FET_DRV KEYB1 13 KEYB2 14 (IPU) CRITICAL LCDBKLT_SW NC (IPU) PMEG10020ELR-DFLS2100 Q8401 LCDBKLT_FET_DRV_R C8465 10% 100V X5R 1206 K CRITICAL 10 CRITICAL 2.2UF SOD123-COMBO DIDT=TRUE SWITCH_NODE=TRUE VOLTAGE=55V MIN_NECK_WIDTH=0.2000 MIN_LINE_WIDTH=2.0000 ISET_KEYB 20 33PF 25V NP0-C0G GATE_NODE=TRUE DIDT=TRUE R8432 150K 1% 1/16W MF-LF 402 NOSTUFF C8432 100PF 5% 100V C0G-CERM 0603 CRITICAL 0201 GND_SW GND_SW GND_SW2 GNDD GNDA GND_BKLT_SGND THRM PAD 24 23 22 65 152S00253 4.7UF 5% 1/16W MF-LF 402 LLP PIME062D-SM CRITICAL U8400 5% 1/20W MF 201 5% 1/20W MF 0201 R8410 1M L8410 PLACE_NEAR=L8410.1:5MM PLACE_NEAR=L8410.1:5MM PLACE_NEAR=L8410.1:5MM 10% 10V X5R 402-1 R8440 CRITICAL C8441 PLACE_NEAR=U8400.18:5MM EDP_BKLT_EN CRITICAL 1UF 10% 10V X5R 402-1 2.2UF CRITICAL PLACE_NEAR=D8410.K:5MM PLACE_NEAR=D8410.K:5MM PLACE_NEAR=D8410.K:5.1MM PLACE_NEAR=D8410.K:5MM PLACE_NEAR=D8410.K:5.1MM PLACE_NEAR=L8410.2:3MM 371S0704 PLACE_NEAR=Q8401.5:3MM SANDWICH C8410 AND C8411 PP5V_S0_BKLT_A PP5V_S0_BKLT_D PLACE_NEAR=U8400.5:5MM 1UF IN +/-0.1PF 25V C0G 0201 PLACEMENT_NOTE: 5% 1/16W MF-LF 402 65 68 C8410 10% 25V X6S-CERM 0603 R8444 GND_BKLT_SGND CRITICAL 4.7UF 65 3PF 1 1% 1/16W MF-LF 402 C C8414 15UH-20%-1.9A-0.24OHM =PP5V_S0_BKLT 69 65 63.4K 65 5% 25V CERM 0201 LCDBKLT_EN_L R8402 C8413 12PF 10% 50V CERM 402 C8461 PPVIN_S0SW_LCDBKLT 0.001UF ISNS_LCDBKLT_N CRITICAL BKLT_PWM_KEYB 353S4160 25 =PPVIN_S0SW_LCDBKLTFET 1% 1W MF 0612-1 LCDBKLT_TB_XWR CRITICAL 69 Q8400 R8400 PPVIN_SW_LCDBKLT_SW 740S0159 VDDA 18 D 1 R8447 10K 5% 1/20W MF 201 B B XW8400 SM GND_BKLT_SGND 65 GND_BKLT_SGND 69 65 MIN_LINE_WIDTH=0.4000 MIN_NECK_WIDTH=0.2000 =PP5V_S0_BKLT 65 VOLTAGE=0V R8452 1.8K 5% 1/20W MF 201 R8453 1.8K 5% 1/20W MF 201 PLACE_NEAR=U8400.15:10MM R8450 70 IN =I2C_BKLT_SCL R8451 70 BI =I2C_BKLT_SDA 2 5% 1/20W MF 0201 BKLT_SCL BKLT_SDA 5% 1/20W MF 0201 I2C ID DEDICATED.ONLY CONNECTS TO JERRY PLACE_NEAR=U8400.16:10MM LINE WIDTHS A PP5V_S0_BKLT_A MIN_LINE_WIDTH=2.0000 MIN_NECK_WIDTH=0.2000 PBUS LINE WIDTHS LCD BKLT LINE WIDTHS PPVIN_S0SW_LCDBKLT_F 65 65 MIN_LINE_WIDTH=2.0000 MIN_NECK_WIDTH=0.2000 VOLTAGE=5V VOLTAGE=12.9V PPVIN_S0SW_LCDBKLT_R PP5V_S0_BKLT_D MIN_LINE_WIDTH=2.0000 MIN_NECK_WIDTH=0.2000 65 MIN_LINE_WIDTH=2.0000 MIN_NECK_WIDTH=0.2000 LCDBKLT_FET_DRV MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.2000 VOLTAGE=5V GATE_NODE=TRUE DIDT=TRUE 65 MIN_LINE_WIDTH=0.5000 MIN_NECK_WIDTH=0.2000 PPVIN_S0SW_LCDBKLT MIN_LINE_WIDTH=2.0000 MIN_NECK_WIDTH=0.2000 VOLTAGE=5V MIN_LINE_WIDTH=2.0000 MIN_NECK_WIDTH=0.2000 VOLTAGE=55V DIDT=TRUE SWITCH_NODE=TRUE PPVOUT_S0_LCDBKLT VOLTAGE=12.9V 65 PPVIN_SW_LCDBKLT_SW 65 SYNC_MASTER=X362 PAGE TITLE LCD Backlight Driver DRAWING NUMBER 65 66 72 Apple Inc VOLTAGE=55V 65 NOTICE OF PROPRIETARY PROPERTY: BOM_COST_GROUP=DISPLAY 051-02265 REVISION R VOLTAGE=12.9V SYNC_DATE=06/25/2015 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED SIZE 1.0.0 BRANCH PAGE 84 OF 500 SHEET 65 OF 73 D A LCD Panel HPD & AUX strapping LCD PANEL INTERFACE (eDP) + Camera (MIPI) 69 =PP3V3_S0_LCD 69 72 66 =PP5V_S0_LCD DP_INT_HPD 72 66 NO_XNET_CONNECTION=1 EDP_INT_AUX_P R85031 NO_XNET_CONNECTION=1 1M U8500 D SLG5AP1443V D8517 SC2 R8517 PANEL_P5V_EN_D 1% 1/20W MF 201 A PANEL_P5V_EN K CAP ON DSF01S30SCAP D S 150K PP5V_S0SW_LCD 66 72 1% 1/20W MF 201 C8515 0.1UF C8511 0.1UF C8509 10% 10V X5R-CERM 0201 2200PF 10% 10V X5R-CERM 0201 10% 10V X7R-CERM 0201 CRITICAL C8512 5% 25V CERM 0201 =PP3V3_S5_LCD 69 10UF 20% 10V X5R-CERM 0402-7 CRITICAL LCD_PWR_SLEW_3V3 66 330 0.47UF PANEL_P3V3_EN_D 1% 1/20W MF 201 K +/-0.1PF SHORT RSENSE 25V C0G ON C8513 R8554 PP3V3_S0SW_LCD_R D S 1% 1/3W MF 0306-SHORT VOLTAGE=3.3V PP3V3_S0SW_LCD_R1 5% 1/16W MF-LF 402 PP3V3_S0SW_LCD C8562 12PF 5% 25V CERM 0201 C8510 20% 6.3V X5R 0201-1 44 ISNS_LCDPANEL_P 44 ISNS_LCDPANEL_N C8563 3PF +/-0.1PF 0201 5% 1/20W PANEL_P3V3_EN_DLY 5% R8591 1/20W BUF_EDP_PANEL_PWR_EN MF 0201 VDD 66 66 IN EDP_PANEL_PWR_EN EDP_PANEL_PWR_EN 72 60 59 39 26 14 IN PM_SLP_S3_L PM_SLP_S3_L IN SMC_RESET_L 5% 68 66 53 47 R8592 1/20W BUF_SMC_RESET_L MF 0201 IN SMC_RESET_L 39 41 66 OUT 72 66 SLG4AP4998 72 NOSTUFF 66 53 47 68 72 66 CRITICAL NOSTUFF PANEL_FET_EN_DLY PANEL_PWR_EN_CONN 12 SMC_RESET_INPUT_L SMC_RESET_OUTPUT_L X604_DISP_PWR_EN R85101 X604_DISP_SMC_RST_L 5% 1/20W MF 201 72 66 BUF_EDP_PANEL_PWR_EN STQFN 100K U8510 NC0 NC1 BUF_SMC_RESET_L 66 72 66 72 66 OUT 10 11 72 66 72 66 NC 72 66 NC NC 72 66 R8556 B BI I2C_ALS_SDA 33 1/20W 201 I2C_ALS_SDA_CONN 5% MF 72 37 OUT 72 37 OUT 72 37 OUT 72 37 OUT BI I2C_ALS_SCL 33 1/20W 201 36 BI I2C_CAM_SDA 1/20W 201 I2C_ALS_SCL_CONN 36 BI I2C_CAM_SCL 1/20W 201 I2C_CAM_SDA_CONN 66 72 72 IN EDP_ML_C_P 72 IN EDP_ML_C_N I2C_CAM_SCL_CONN 72 IN EDP_ML_C_P R8572 42 BI =I2C_TCON_SDA 33 5% MF I2C_TCON_SDA_CONN 1/20W 201 72 66 72 PLACE_NEAR=J8500:5MM 72 R8568 42 BI =I2C_TCON_SCL 33 5% MF I2C_TCON_SCL_CONN 1/20W 201 72 C8550 12PF 5% 25V CERM 0201 C8551 12PF 5% 25V CERM 0201 C8552 12PF 5% 25V CERM 0201 C8553 12PF 5% 25V CERM 0201 C8554 12PF 5% 25V CERM 0201 C8555 72 72 0201 A BUF_EDP_PANEL_PWR_EN LCD_IRQ_L TCON_BKLT_PWM I2C_BKLT_SDA C8570 12PF 5% 25V CERM 0201 IN EDP_ML_C_P IN EDP_ML_C_N IN EDP_ML_C_P IN EDP_ML_C_N BI EDP_AUXCH_C_P 5% 25V CERM C8571 12PF 5% 25V CERM 0201 C8572 12PF 5% 25V CERM 0201 BI C8522 C8523 0.1UF C8524 0.1UF C8525 0.1UF C8526 0.1UF 12PF EDP_ML_C_N PLACE_NEAR=J8500:5MM C8521 0.1UF IN 66 72 0.1UF 66 72 PLACE_NEAR=J8500:5MM C8520 0.1UF PLACE_NEAR=J8500:5MM 5% MF EDP_INT_ML_N EDP_INT_ML_P EDP_INT_ML_N EDP_INT_ML_P EDP_INT_ML_N EDP_INT_ML_P EDP_INT_ML_N EDP_INT_ML_P MIPI_CLK_CONN_N MIPI_CLK_CONN_P PP5V_S0SW_LCD 45 66 72 R8562 33 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 PLACE_NEAR=J8500:5MM 5% MF C8527 0.1UF C8528 0.1UF EDP_AUXCH_C_N C8529 0.1UF 10% 16V X5R-CERM 0201 10% 16V X5R-CERM 0201 10% 16V X5R-CERM 0201 10% 16V X5R-CERM 0201 10% 16V X5R-CERM 0201 10% 16V X5R-CERM 0201 10% 16V X5R-CERM 0201 10% 16V X5R-CERM 0201 10% 16V X5R-CERM 0201 10% 16V X5R-CERM 0201 EDP_INT_ML_P 66 72 EDP_INT_ML_N 66 72 EDP_INT_ML_P 66 72 EDP_INT_ML_N 66 72 EDP_INT_ML_P 66 72 EDP_INT_ML_N 66 72 47 49 51 53 55 57 59 61 63 65 67 10% 100V X7R-CERM 0603 1000PF PP3V3_S0SW_LCD 44 PWR SIGNAL 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 BUF_EDP_PANEL_PWR_EN DP_INT_HPD 66 LCD_IRQ_L TCON_BKLT_PWM EDP_BKLT_PWM OUT 66 72 OUT 16 66 72 41 66 72 OUT 72 IN I2C_BKLT_SDA I2C_BKLT_SCL I2C_TCON_SDA_CONN I2C_TCON_SCL_CONN BI 66 70 72 BI 70 72 66 72 66 72 I2C_ALS_SDA_CONN I2C_ALS_SCL_CONN I2C_CAM_SCL_CONN I2C_CAM_SDA_CONN PWR 66 72 66 72 66 72 66 72 GND PP5V_S0_ALSCAM_F 46 48 50 52 54 56 58 60 62 64 66 68 37 72 B C8564 12PF 5% 25V CERM 0201 COWLING BOSES 860-00469 SH8501 2.7X1.8R-1.4ID-0.91H-SM SH8502 516S00228 2.7X1.8R-1.4ID-0.91H-SM EDP_INT_ML_P 66 72 EDP_INT_ML_N 66 72 EDP_INT_AUX_P 66 72 SYNC_MASTER=X362 EDP_INT_AUX_N 66 72 PAGE TITLE 66 SYNC_DATE=06/23/2015 eDP Display Connector DRAWING NUMBER 16 66 72 Apple Inc 41 66 72 66 70 72 C8573 12PF 5% 25V CERM 0201 051-02265 REVISION R NOTICE OF PROPRIETARY PROPERTY: C 66 72 BOM_COST_GROUP=DISPLAY 5% 100V C0G 0201 66 72 R8560 33 EDP_INT_AUX_N EDP_INT_AUX_P MIPI_DATA_CONN_N MIPI_DATA_CONN_P 72 66 5% MF 43 PLACE_NEAR=J8500:5MM R8558 42 PPVOUT_S0_LCDBKLT 39 41 66 NC GND 42 +/-0.1PF 100V C0G 0201 F-ST-SM 72 66 MF 0201 C8500 12PF PLACE_NEAR=J8500:5MM PLACE_NEAR=J8500:5MM PLACE_NEAR=J8500:5MM CRITICAL =PP3V3_G3H_SMC NOSTUFF 66 C8501 J8500 U8510 BYPASS R8590 C8502 20759-042E-02 69 PPVOUT_S0_LCDBKLT 72 66 65 25V C0G DSF01S30SCAP C 5% 100V C0G 0201 12PF 66 72 3PF 72 66 65 +/-0.1PF 100V C0G 0201 VOLTAGE=3.3V PANEL_P3V3_EN_DLY PANEL_P3V3_EN C8503 MIN_NECK_WIDTH=0.2000 MIN_LINE_WIDTH=0.5000 1.0UF 10% 10V X7R-CERM 0201 A C8504 3PF OMIT 0201 VOLTAGE=3.3V 2200PF 10% 6.3V CERM-X5R 0201 D8518 SC2 3PF GND C8516 PPVOUT_S0_LCDBKLT 72 66 65 0.005 TDFN CAP R8518 PANEL_P3V3_EN 1% 1/20W MF 201 C8561 VDD 1 R8520 U8501 R8516 C8560 12PF SLG5AP1443V 200K D EDP_INT_AUX_N VOLTAGE=5V GND R8515 1M 5% 1/20W MF 201 72 66 330 TDFN LCD_PWR_SLEW 5% 1/20W MF 201 R8502 5% 1/20W MF 201 VDD 1M R8501 CRITICAL THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED SIZE 1.0.0 BRANCH PAGE 85 OF 500 SHEET 66 OF 73 D A NOSTUFF R8641 VENDOR FERRITE DATA: 20A - 20MS, 2% DUTY CYCLE 10A - 100MS, 10% DUTY CYCLE 9A - 5MIN 5% 1/20W MF 0201 PP1V8_S5G CRITICAL C8640 R8645 5% 1/20W MF 201 D 13 14 IN IN SOT1116 SSD_PWR_EN_L A1 1OE* A2 SSD_BOOT_L R8640 100K NOSTUFF R8642 C8602 1 SSD_PWR_EN_CONN_L 67 Y2 ACT SSD_BOOT_CONN_L 67 72 LIKE OPEN DRAIN 20% 6.3V X5R-CERM-1 603 10% 10V X5R-CERM 0201 0.1UF C8606 3.5PF +/-0.25PF 25V C0G 0201 43 PPBUS_G3H_SSD J8600 63 0603 C8604 1 C8603 67 0201 67 72 67 67 19 16 67 39 67 39 470K C 67 19 16 IN 67 39 IN 67 39 OUT 67 14 IN 67 19 OUT 67 19 OUT SSD_PWR_EN_CONN_L SSD_BOOT_CONN_L (BFH#) SSD_RESET_L (STORAGE_RST_L) SMC_OOB1_R2D_L SMC_OOB1_D2R_L SSD_SR_EN_L (LPSR#) STORAGE_LATCH SSD_CLKREQ_L SSD_EN (STORAGE_EN) R86211 100K 5% 1/16W MF-LF 402 67 67 14 R86371 100K 5% 1/16W MF-LF 402 5% 1/16W MF-LF 402 R86111 67 19 100K 67 19 5% 1/16W MF-LF 402 67 C8673 12PF 5% 25V CERM 0201 C8674 3PF +/-0.1PF 25V C0G 0201 67 72 72 15 72 15 72 15 72 15 B 72 15 72 15 72 15 IN PCIE_SSD_R2D_C_N IN PCIE_SSD_R2D_C_P 72 67 72 67 (3.3V) (OC) (4.7K PULLUP AT CLOCK CHIP) C8675 12PF C8676 C8677 2.9PF 5% 25V CERM 0201 2.9PF +/-0.05PF 25V C0G-CERM 0201 +/-0.05PF 25V C0G-CERM 0201 C8670 R8610 1 12PF 100K 3.5PF 5% 25V CERM 0201 5% 1/16W MF-LF 402 C8671 C8672 +/-0.25PF 25V C0G 0201 IN IN IN C8610 PCIE_SSD_R2D_C_P 0201 PCIE_SSD_R2D_C_N IN PCIE_SSD_R2D_C_P IN PCIE_SSD_R2D_C_N IN PCIE_SSD_R2D_C_P 0201 X5R 0201 X5R C8615 C8616 72 67 3.5PF +/-0.25PF 25V C0G 0201 72 67 20% 1 2 X5R 20% 6.3V 20% 6.3V 0.22UF 0.22UF 67 72 PCIE_SSD_R2D_N 72 15 OUT 72 15 OUT 72 15 OUT PCIE_SSD_D2R_N PCIE_SSD_D2R_P 72 15 OUT 72 15 OUT 72 15 OUT 72 15 OUT 67 67 67 72 PCIE_SSD_R2D_P 67 72 PCIE_SSD_R2D_N 67 72 PCIE_SSD_R2D_P 67 72 GND_VOID=TRUE GND_VOID=TRUE (RX) 67 72 PCIE_SSD_R2D_N GND_VOID=TRUE GND_VOID=TRUE PCIE_SSD_D2R_N PCIE_SSD_D2R_P PCIE_SSD_D2R_N PCIE_SSD_D2R_P 67 72 PCIE_SSD_R2D_P GND_VOID=TRUE GND_VOID=TRUE 28 BI 28 IN GND_VOID=TRUE GND_VOID=TRUE PCIE_SSD_D2R_N PCIE_SSD_D2R_P GND_VOID=TRUE GND_VOID=TRUE PCIE_CLK100M_SSD_C_N PCIE_CLK100M_SSD_C_P SSD_JTAG_TMS SSD_JTAG_TCK 6.3V 0.22UF 20% PCIE_SSD_R2D_P OUT 6.3V 0.22UF 20% 67 72 6.3V 0.22UF 20% PCIE_SSD_R2D_N 72 15 GND_VOID=TRUE GND_VOID=TRUE PCIE_SSD_R2D_N PCIE_SSD_R2D_P 72 67 6.3V 0.22UF PCIE_SSD_R2D_N PCIE_SSD_R2D_P 72 67 6.3V 0.22UF 20% X5R C8617 0201 X5R C8614 0201 X5R C8613 0.22UF 20% X5R C8612 0201 X5R C8611 0201 GND_VOID=TRUE GND_VOID=TRUE 10 11 12 13 14 15 16 17 18 19 20 21 22 57 58 59 60 61 62 63 64 NC 6.3V AC CAPS FOR PCIE GEN Per PCIe spec, only TX side should have AC cap CRITICAL C 65 (TX) 67 GND_VOID=TRUE GND_VOID=TRUE PCIE_SSD_R2D_N PCIE_SSD_R2D_P 72 67 0201 PCIE_SSD_R2D_C_N PCIE_SSD_R2D_N PCIE_SSD_R2D_P 72 67 (3.3V TOLERANT INPUT) FREQUENCY SPECIFIC 72 15 AC_SHIELD_SSD SSD_PWR_EN_CONN_L SSD_BOOT_CONN_L SSD_RESET_L SMC_OOB1_D2R_L SMC_OOB1_R2D_L SSD_SR_EN_L STORAGE_LATCH SSD_CLKREQ_L SSD_EN NC CRITICAL MIN_LINE_WIDTH=0.4000 MIN_NECK_WIDTH=0.1000 10% 25V X5R PP3V3_S5_SSD PP3V3_S4 PP1V8_S0 R86201 F-RT-SM PPBUS_SSD_FLT 0.1UF 10% 35V X5R-CERM 0603 NOSTUFF 0201 SSD-MIDMOUNT-J130 CRITICAL NOSTUFF +/-0.25PF 25V C0G CRITICAL 4.7UF 72 69 64 63 60 51 50 48 3.5PF L8602 69 67 44 C8607 FERR-10-OHM-8A (WORST CASE ??A) 72 69 64 63 45 44 43 41 CRITICAL 5% 1/20W MF 201 5% 1/20W MF 0201 C8601 MIN_LINE_WIDTH=0.4000 MIN_NECK_WIDTH=0.1000 D Y1 PUSH-PULL 2OE* GND 0603 22UF 74LVC2G125GN PP3V3_SSD_FLT CRITICAL 100K U8640 L8600 FERR-10-OHM-8A PP3V3_S5_SSD 10% 10V X5R-CERM 0201 VCC 59 61 64 69 72 69 67 44 0.1UF (WORST CASE ??A) CRITICAL 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 66 67 68 69 70 71 72 B 73 74 75 76 77 514S00081 L8630 90-OHM-0.1A EXCX4CE SYM_VER-1 A 15 IN PCIE_CLK100M_SSD_N PCIE_CLK100M_SSD_C_N 67 15 IN PCIE_CLK100M_SSD_P PCIE_CLK100M_SSD_C_P 67 AC_SHIELD_SSD 67 SSD STANDOFFS NOTES: POWER-ON TO PERST_L DE-ASSERTION = 10MS MINIMUM PP3V3_EN: PROVIDE 10MS EARLY WARNING TO SSD THAT POWER WILL BE OFF (PIN 47, PP3V3_EN, IS NOT USED BY SAMSUNG UAX AND SANDISK SSD.) PCIE CLK100M ARE 2.5V SIGNALS R8661 860-00380 SH8600 4.0OD1.6ID-0.85H-TH OOB SIGNALS: UART 3.3V, 115.2 KBAUD, 8B, NO PARITY, STOP BIT SH8601 4.0OD1.6ID-0.85H-TH SYNC_MASTER=PAULM C8660 0.1UF 10% 25V X5R 0201 SSD MODULE DRAWING NUMBER Apple Inc AC_SHIELD_SSD_RC C8661 051-02265 REVISION R 0.1UF NOTICE OF PROPRIETARY PROPERTY: 10% 25V X5R 0201 BOM_COST_GROUP=SSD SYNC_DATE=06/15/2015 PAGE TITLE 10 5% 1/20W MF 201 DESIGN: X502/MLB_CATZ LAST CHANGE: Thu Aug 21:00:42 2016 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED SIZE 1.0.0 BRANCH PAGE 86 OF 500 SHEET 67 OF 73 D A VF = 2V IF = 1MA DEV_LEDS DZ9927 GDZ-0201 72 69 63 60 58 53 50 43 IN ON-BOARD POWER BUTTON PPBUS_G3H K DIV_PPBUS_G3H DEV_LEDS A R9928 GDZT2R8.2 470K DEV_POWER_BUTTON SW9988 SOX-152HNT SILK_PART=PWR_BTN R9988 R9920 SMC_ONOFF_L OUT 38 39 40 72 SM DIV_PPDCIN DEV_LEDS R9921 DEV_LEDS 66 53 47 SW9930 DIAG_LED_EN_R_L 20 DIAG_LED_ENABLE_L 5% 1/20W MF 201 NOSTUFF SW9998 DEV_RST_BUTTONS:YES SOX-152HNT SMC_RST_BTN_R_L NOSTUFF SMC_RST_BTN_L OUT 41 5% 1/20W MF 0201 C9998 1000PF 39 14 20% 6.3V X6S-CERM 0201 PM_DSW_PWRGD IN STUFF TO ALWAYS ENABLE LEDS 60 39 17 14 PM_RSMRST_L IN PM_PGOOD_P5VS4 IN DEV_RST_BUTTONS:YES R9999 SYSRST_R_L NOSTUFF G S C9999 1000PF 62 60 PM_SYSRST_L OUT PM_PGOOD_PVDDQ IN 14 17 39 5% 1/20W MF 0201 G G PM_SLP_S0S3_L IN G R9922 35 19 14 IN PLT_RST_L 10K PLTRST_LED_L 5% 1/20W MF 201 G S IN EDP_BKLT_EN B S PM_SLP_S4_L 72 60 39 14 R9923 G 470K (1V SIGNALS) 5% 1/20W MF 201 S CATERR_LED DEV_LEDS R9925 39 19 IN CPU_CATERR_L 100K CATERR_LED_L DEV_LEDS Q9922 K S K A A LED_S5_R LED_S4_R R9906 LED_S3_R DEV_LEDS R9907 LED_S0I_R SML-P11-SM DEV_LEDS LED_PLTRST K A R9908 LED_PLTRST_R SML-P11-SM DEV_LEDS LED_BKLT K A R9909 LED_BKLT_R SML-P11-SM DEV_LEDS LED_CATERR SOT563 K A R9910 LED_CATERR_R LED_PROCHOT SML-P11-SM DEV_LEDS K A 1.3K 5% 1/20W MF 201 RED-621NM-2.5MCD-1MA DEV_LEDS LED9911 VER B DEV_LEDS LED9910 VER 1.3K 5% 1/20W MF 201 GREEN-569NM-2.1MCD-1MA SOT563 DEV_LEDS LED9909 VER 1.3K 5% 1/20W MF 201 GREEN-569NM-2.1MCD-1MA SOT563 DEV_LEDS LED9908 VER 1.3K 5% 1/20W MF 201 GREEN-569NM-2.1MCD-1MA SOT563 DEV_LEDS LED9907 A 1.3K 5% 1/20W MF 201 SML-P11-SM K C DEV_LEDS GREEN-569NM-2.1MCD-1MA LED_S0I 1.3K 5% 1/20W MF 201 LED9906 VER R9905 DEV_LEDS K 1.3K DEV_LEDS SML-P11-SM LED_S3 5% 1/20W MF 201 YELLOW-586NM-7.6MCD-1MA A 1.3K R9904 DEV_LEDS K 44 58 60 61 63 64 68 69 72 DEV_LEDS LED9905 LED_S4 PP3V3_S5 5% 1/20W MF 201 SML-P11-SM SOT563 PP3V3_S5 GREEN-569NM-2.1MCD-1MA VER D3 LED_DS5_R LED9904 LED_S5 R9903 DEV_LEDS SOT963 A 1.3K DEV_LEDS SML-P11-SM SOT563 D6 GREEN-569NM-2.1MCD-1MA DEV_LEDS Q9910 DMN5L06VK-7 G DST3904DJ 5% 1/20W MF 201 72 69 68 64 63 61 60 58 44 LED_DS5 5% 1/20W MF 201 DEV_LEDS VER D3 LED_G3H_R SML-P11-SM SOT563 D6 A 1.3K R9902 GREEN-569NM-2.1MCD-1MA VER D3 DEV_LEDS LED9903 DEV_LEDS Q9910 DMN5L06VK-7 DEV_LEDS K D 5% 1/20W MF 201 DEV_LEDS SOT563 D6 LED_DCIN_R SML-P11-SM VER D3 A R9901 YELLOW-586NM-7.6MCD-1MA LED_G3H DEV_LEDS Q9908 DMN5L06VK-7 G K 1.3K DEV_LEDS LED9902 DEV_LEDS Q9908 DMN5L06VK-7 65 LED_DCIN SOT563 D6 5% 1/20W MF 201 DEV_LEDS VER D3 LED_PBUS_R SML-P11-SM SOT563 D6 R9900 LED9901 DEV_LEDS Q9906 DMN5L06VK-7 S DEV_LEDS D3 A 19 28 41 42 47 51 52 53 60 69 72 DEV_LEDS YELLOW-586NM-7.6MCD-1MA VER DEV_LEDS Q9906 DMN5L06VK-7 G K SOT563 DEV_LEDS Q9904 DMN5L06VK-7 72 68 60 19 LED_PBUS DEV_LEDS Q9904 DMN5L06VK-7 S 10% 25V X7R 0201 D6 DEV_LEDS Q9902 DMN5L06VK-7 G DEV_LEDS LED9900 VER DEV_LEDS Q9902 DMN5L06VK-7 SM S S DEV_RST_BUTTONS:YES SILK_PART=SMC_RST G PP3V3_G3H SOT563 DEV_LEDS Q9900 DMN5L06VK-7 SYSTEM RESET BUTTON SOX-152HNT S S 60 58 SW9999 G 10% 25V X7R 0201 C DEV_LEDS Q9900 DMN5L06VK-7 S 5% 1/20W MF 0201 R9998 SM C9933 1UF R9930 DEV_RST_BUTTONS:YES 1 PLACE ON SAME SIDE AS DIAG LEDS SMC_RESET BUTTON R9933 SM SMC_RESET_L IN DEV_LEDS SOX-152HNT SILK_PART=DIAG_LED 470K 5% 1/20W MF 201 PRESS TO ENABLE DIAG LEDS PPDCIN_G3H DIAG LED BUTTON PLACE_SIDE=BOTTOM SILK_PART=SMC_RST IN 5% 1/20W MF 201 5% 1/20W MF 201 10% 25V X7R 0201 SW9989 72 69 63 53 470K 5% 1/20W MF 0201 1000PF SOX-152HNT 2 C9988 DEV_POWER_BUTTON SILK_PART=PWR_BTN DEV_LEDS SMC_ONOFF_R_L NOSTUFF PLACE_SIDE=TOP D DEV_POWER_BUTTON SM R9911 LED_PROCHOT_R 1.3K 5% 1/20W MF 201 RED-621NM-2.5MCD-1MA SML-P11-SM C9911 0.1UF 10% 10V X5R-CERM 0201 DEV_LEDS CRITICAL U9911 72 68 60 19 IN PM_SLP_S0S3_L 74LVC1G08 SOT891 PM_SLP_S0S3_BUFFLED_L DEV_LEDS 08 NC A R9924 470K NC R9926 54 40 39 IN CPU_PROCHOT_L PROCHOT_LED_L 5% 1/20W MF 201 DEV_LEDS Q9922 051-02265 REVISION R DST3904DJ NOTICE OF PROPRIETARY PROPERTY: SOT963 BOM_COST_GROUP=DEBUG DEVELOPMENT ONLY Apple Inc PROCHOT IS ONLY VALID IN FULL S0, NOT S0I OR LOWER SYNC_DATE=06/15/2015 DRAWING NUMBER PROCHOT_LED DEV_LEDS 100K SYNC_MASTER=PAULM PAGE TITLE 5% 1/20W MF 201 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED SIZE 1.0.0 BRANCH PAGE 99 OF 500 SHEET 68 OF 73 D A CPU RAILS 10 10 11 11 69 10 10 10 D 59 54 19 14 10 40 17 10 10 10 =PPVCC_S0_CPU =PPVCCSA_S0_CPU =PPVCCGT_S0_CPU =PPVCCGTX_S0_CPU =PP1V2_S3_CPU_VDDQ =PP1V2_S3_CPU_VDDQC =PP0V95_S0_CPU_VCCIO =PP1V_S3_CPU_VCCST =PP1V_S0_SMC_VCCST MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE =PP1V_S0SW_CPU_VCCSTG =PP1V_S3_CPU_VCCPLL =PP1V2_S0SW_CPU_VCCPLLOC MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE PPVCCCPU_S0G PPVCCSA_S0G PPVCCGT_S0G PPVCCGT_S0G PP1V2_S3 =PP1V2_S3_CPU_VDDQ PPVCCIO_S0G PP1V_S3 PP1V_S0G PP1V_S3 PP1V2_S0G 45 55 63 72 56 72 45 57 63 69 72 45 57 63 69 72 62 63 64 69 8 10 69 64 36 =PP3V3_S0_CAMERA 37 =PP5V_S0_ALSCAM 52 32 31 =PPBUS_G3H PPBUS_G3H MAKE_BASE=TRUE 14 =PP3V3_S5_PCH_VCCDSW MAKE_BASE=TRUE 43 50 53 58 60 63 68 69 72 MAKE_BASE=TRUE 43 PPDCIN_G3H MAKE_BASE=TRUE 53 63 68 69 72 16 15 14 13 19 12 12 8 12 8 58 66 40 39 C 40 40 =PP5V_S5_LDO =PP3V3_G3H_SMC =PP3V3_S5_SMC =PP3V3_S4_SMC =PP3V3_S0_SMC PP5V_S5 MAKE_BASE=TRUE 63 64 12 47 13 PP3V3_G3H PP3V3_G3H PP3V3_S4 PP3V3_S0 MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE 19 69 19 69 12 28 41 42 47 51 52 53 60 68 72 28 41 42 47 51 52 53 60 68 72 69 12 41 43 44 45 63 64 67 69 72 12 =PPVIN_S5_SMCVREF PP3V3_G3H MAKE_BASE=TRUE 12 19 28 41 42 47 51 52 53 60 68 69 72 12 12 12 15 12 14 24 23 22 21 24 23 22 21 24 23 22 21 24 23 22 21 20 25 25 20 69 20 20 69 20 =PP1V8_S3_MEM =PP1V2_S3_MEM_VDD2 =PP1V2_S3_MEM_VDDCA =PP1V2_S3_MEM_VDDQ =PPDDR_S3_MEMVREF =PP0V6_S0_MEM_VTT_A =PP0V6_S0_MEM_VTT_B PPVREF_S3_MEM_VREFDQ_A PPVREF_S3_MEM_VREFCA PPVREF_S3_MEM_VREFDQ_B PPVREF_S3_MEM_VREFCA PP1V8_S3 PP1V2_S3 PP1V2_S3 PP1V2_S3 PP1V2_S3 MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE 12 60 63 64 MAKE_BASE=TRUE MAKE_BASE=TRUE PP0V6_S3_MEM_VREFDQ_A MAKE_BASE=TRUE PP0V6_S3_MEM_VREFCA_A MAKE_BASE=TRUE PP0V6_S3_MEM_VREFDQ_B MAKE_BASE=TRUE PP0V6_S3_MEM_VREFCA_B MAKE_BASE=TRUE =PP3V3_SUS_PCH_VCCPGPPG =PP3V3_SUS_PCH_VCCPRIM =PP3V3_SUS_PCH_VCCSPI MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE =PP3V3_SUS_PCH_VCCRTCPRIM MAKE_BASE=TRUE =PP1V_SUS_PCH_VCCPRIM =PP1V_SUS_PCH_VCCMPHYAON MAKE_BASE=TRUE MAKE_BASE=TRUE 12 =PP1V_SUS_PCH_VCCCLK1 =PP1V_SUS_PCH_VCCCLK2_SRC =PP1V_SUS_PCH_VCCCLK3 =PP1V_SUS_PCH_VCCCLK4_SRC =PP1V_SUS_PCH_VCCCLK5_SRC =PP1V_SUS_PCH_VCCCLK6 =PP1V_SUS_PCH_VCCAPLL MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE =PP1V8_SUS_PCH_VCCPGPPF =PP1V8_SUS_PCH_VCCATS =PP1V8_SUS_PCH_VCC1P8_SRC MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE 62 63 64 69 62 63 64 69 12 =PPVCCPRIMECORE_SUS_PCH MAKE_BASE=TRUE 62 63 64 69 62 63 64 69 12 12 PPVTT_S0 PPVTT_S0 MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE 38 42 45 46 49 54 59 60 63 64 69 40 =PP3V3_SUS_PCH_VCCPGPPA =PP3V3_SUS_PCH_VCCPGPPB =PP3V3_SUS_PCH_VCCPGPPC =PP3V3_SUS_PCH_VCCPGPPD =PP3V3_SUS_PCH_VCCPGPPE 44 58 60 61 63 64 68 69 72 35 12 62 69 72 12 =PP1V_SUSSW_PCH_VCCAMPHYPLL_SRC =PP1V_SUSSW_PCH_VCCMPHYGT =PP1V_SUSSW_PCH_VCCSRAM =PP1V_SUSSW_PCH_VCCAPLLEBB 62 69 72 12 21 22 18 21 22 60 19 16 14 13 23 24 14 =PP1V8_S0_PCH_VCCHDA =PP1V8R1V5_S0_PCH_VCCHDA =PP3V3_S0_PCH =PP3V3_S4_PCH MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE 23 24 PP3V3_S5G PP3V3_S5G PP3V3_S5G PP3V3_S5G PP3V3_S5G PP3V3_S5G PP3V3_S5G PP3V3_S5G PP3V3_S5G 60 64 69 72 38 60 64 69 72 38 60 64 69 72 38 PP1V8_S5G PP1V8_S5G PP1V8_S5G PPVCCPCH_S5G PP1V_S5GTD PP1V_S5GTD PP1V_S5GTD PP1V_S5GTD 54 55 56 57 59 64 69 72 PP3V3_S0 PP3V3_S5 PP5V_S0 MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE =PP3V3_S0_BT_UART =PP3V3_S4_BT_UART PP3V3_S0 PP3V3_S4 MAKE_BASE=TRUE MAKE_BASE=TRUE =PP3V3_G3H_KBD =PP3V3_S4_KBD =PP5V_S0_KBD PP3V3_G3H PP3V3_S4 PP5V_S0 MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE 38 42 45 46 49 54 59 60 63 64 69 44 58 60 61 63 64 68 69 72 54 55 56 57 59 64 69 72 38 42 45 46 49 54 59 60 63 64 69 41 43 44 45 63 64 67 69 72 19 28 41 42 47 51 52 53 60 68 69 72 41 43 44 45 63 64 67 69 72 54 55 56 57 59 64 69 72 60 64 69 72 34 19 60 64 69 72 18 =PP3V3_S4_WLAN =PP3V3_S5_WIRELESS PP3V3_S4_WLS PP3V3_S5 MAKE_BASE=TRUE MAKE_BASE=TRUE 60 64 69 72 44 63 72 44 58 60 61 63 64 68 69 72 60 64 69 72 60 64 69 72 38 19 62 63 64 69 72 38 19 62 63 64 69 72 38 PP1V_S5G PP1V_S5G PP1V_S5G PP1V_S5G PP1V_S5G PP1V_S5G PP1V_S5G =PP3V3_S0_LCD =PP3V3_S5_LCD =PP5V_S0_LCD 60 64 69 72 38 PP1V_S5G PP1V_S5G PP5V_S0 MAKE_BASE=TRUE 61 35 =PPDCIN_G3H_SNS D 38 42 45 46 49 54 59 60 63 64 69 64 66 PP3V3_S5 PP3V3_S0 MAKE_BASE=TRUE 64 69 66 PP3V1_RTC PU_VSNS_CPU_VCCGTX_TP PD_VSNS_CPU_VCCGTX_TN 64 69 66 =PP3V_G3H_PCH_VCCRTC MAKE_BASE=TRUE MAKE_BASE=TRUE 61 63 72 PCH RAILS 15 14 12 CPU_VCCGTXSENSE_P CPU_VCCGTXSENSE_N =PP3V3_S0_TPAD =PP3V3_S4_TPAD =PP5V_S4_TPAD =PPBUS_S4_TPAD PP3V3_S0 PP3V3_S4 PP5V_S4 PPBUS_G3H_TPAD MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE 38 42 45 46 49 54 59 60 63 64 69 41 43 44 45 63 64 67 69 72 54 58 60 63 64 69 72 C 43 19 62 63 64 69 72 19 62 63 64 69 72 17 19 62 63 64 69 72 60 17 =PP1V_SUS_PCH_VCCPRIM PP3V3_S5G =PP1V_SUS_XDP =PP3V3_SUS_XDP MAKE_BASE=TRUE 19 62 63 64 69 72 12 69 60 64 69 72 19 62 63 64 69 72 19 62 63 64 69 72 19 62 63 64 69 72 59 61 64 67 69 72 65 59 61 64 67 69 72 65 =PP5V_S0_BKLT =PPVIN_S0SW_LCDBKLTFET 38 =PP5V_S0_FAN PP5V_S0 PPBUS_G3H MAKE_BASE=TRUE MAKE_BASE=TRUE 59 61 64 67 69 72 PP5V_S0 MAKE_BASE=TRUE 61 63 72 54 55 56 57 59 64 69 72 43 50 53 58 60 63 68 69 72 54 55 56 57 59 64 69 72 64 69 64 69 64 69 64 69 PP1V8_S0 48 50 51 60 63 64 67 72 PP3V3_S0 PP3V3_S4 38 42 45 46 49 54 59 60 63 64 69 41 43 44 45 63 64 67 69 72 Digital Ground B B GND VOLTAGE=0V MIN_NECK_WIDTH=0.0850 MIN_LINE_WIDTH=0.3000 40 =PP3V3R1V8_S0_PCH_VCCPGPPB MAKE_BASE=TRUE PP3V3_S0 38 42 45 46 49 54 59 60 63 64 69 USB-C GLOBAL POWER ALIASES 30 =PP3V3_UPC_XA_AUX =PP3V3_UPC_XB_AUX 33 =PP3V3_S5_TBT_X 29 SSD RAILS 29 30 28 67 44 PP3V3_S5_SSD MAKE_BASE=TRUE PP3V3_S5_SSD_SNS 63 30 29 =PP5V_XA_USBC =PP5V_XB_USBC =PP5V_USBC =PPHV_EXT_G3H PP3V3_UPC_XA_LDO PP3V3_UPC_XB_LDO MAKE_BASE=TRUE MAKE_BASE=TRUE PP3V3_S5 MAKE_BASE=TRUE PP5V_S4 MAKE_BASE=TRUE PPDCIN_G3H MAKE_BASE=TRUE 28 29 28 30 63 44 58 60 61 63 64 68 69 72 54 58 60 63 64 69 72 53 63 68 69 72 DESIGN: X502/MLB_CATZ LAST CHANGE: Mon Aug 19:33:56 2016 A SYNC_MASTER=X502-EXP SYNC_DATE=12/03/2015 PAGE TITLE 45 =PP3V3_S0_TBT_X_SNS =PP3V3_TBT_X_S0 Power Aliases 27 28 DRAWING NUMBER Apple Inc 051-02265 REVISION R NOTICE OF PROPRIETARY PROPERTY: BOM_COST_GROUP=NO COST ITEMS THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED SIZE D 1.0.0 BRANCH PAGE 100 OF 500 SHEET 69 OF 73 A UNUSED GPIOS, HSIO D IN IN 16 C IN 16 IN 13 IN 13 IN IN 16 IN 16 IN 15 15 15 IN IN OUT 15 OUT 15 IN 15 IN 15 OUT 15 OUT 15 15 15 13 IN IN BI USB_CAMERA_DFR_N USB_CAMERA_DFR_P IN DEBUGUART_SEL_SOC BI 15 BI 15 BI 15 BI 15 BI 26 BI 26 BI 26 BI 26 BI 15 15 A NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE NO_TEST=1 NO_TEST=1 NO_TEST=1 MAKE_BASE=TRUE NC_I2C_UPC_SDA NC_I2C_UPC_SCL NC_PCH_BSSB_CLK NC_PCH_BSSB_DATA NC_TBT_X_DPMUX_SEL NC_TBT_T_CIO_PWR_EN NC_TBT_T_USB_PWR_EN NC_TBT_T_PCI_RESET_L NC_TBT_T_DPMUX_SEL NC_TBT_T_CLKREQ_L NC_PCIE_CLK100M_TBT_TN NC_PCIE_CLK100M_TBT_TP NC_PCIE_TBT_T_D2RN0 NC_PCIE_TBT_T_D2RP0 NC_PCIE_TBT_T_R2D_CN0 NC_PCIE_TBT_T_R2D_CP0 NC_PCIE_TBT_T_D2RN1 NC_PCIE_TBT_T_D2RP1 NC_PCIE_TBT_T_R2D_CN1 NC_PCIE_TBT_T_R2D_CP1 NC_USB2_03N NC_USB2_03P NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NC_USB3_EXTB_D2RN NC_USB3_EXTB_D2RP NC_USB3_EXTB_R2DCN NC_USB3_EXTB_R2DCP =DP_X_SRC_ML_P =DP_X_SRC_ML_N MAKE_BASE=TRUE MAKE_BASE=TRUE NO_TEST=1 NO_TEST=1 NC_DP_X_SRC_ML_CP NC_DP_X_SRC_ML_CN =DP_X_SRC_AUX_P =DP_X_SRC_AUX_N MAKE_BASE=TRUE MAKE_BASE=TRUE NO_TEST=1 NO_TEST=1 NC_DP_X_SRC_AUXCHP NC_DP_X_SRC_AUXCHN USB_EXTA_N USB_EXTA_P 15 BI 15 BI BI BI 15 BI 15 BI NC_USB2_05N NC_USB2_05P NC_USB2_06N NC_USB2_06P NC_USB2_07N NC_USB2_07P MAKE_BASE=TRUE MAKE_BASE=TRUE NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 30 BI TP_BT_I2S_CLK TP_BT_I2S_D2R TP_BT_I2S_R2D TP_BT_I2S_SYNC TP_CAM_GPIO3 TP_CPU_AT5 TP_CPU_AU5 TP_CPU_AY4 TP_CPU_BB3 TP_CPU_BB5 TP_CPU_MSM_L TP_CPU_NCTFVSS_A5 TP_CPU_NCTFVSS_A70 TP_CPU_NCTFVSS_AV1 TP_CPU_NCTFVSS_B71 TP_CPU_NCTFVSS_BA1 TP_CPU_NCTFVSS_BA71 TP_CPU_NCTFVSS_BB70 TP_CPU_NCTFVSS_C1 MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NC_BT_I2S_CLK NC_BT_I2S_D2R NC_BT_I2S_R2D NC_BT_I2S_SYNC NC_CAM_GPIO3 NC_CPU_AT5 NC_CPU_AU5 NC_CPU_AY4 NC_CPU_BB3 NC_CPU_BB5 NC_CPU_MSM_L NC_CPU_NCTFVSS_A5 NC_CPU_NCTFVSS_A70 NC_CPU_NCTFVSS_AV1 NC_CPU_NCTFVSS_B71 NC_CPU_NCTFVSS_BA1 NC_CPU_NCTFVSS_BA71 NC_CPU_NCTFVSS_BB70 NC_CPU_NCTFVSS_C1 TP_PCH_CLKOUT_LPC1 TP_PCH_GPD7 MAKE_BASE=TRUE MAKE_BASE=TRUE NO_TEST=1 NO_TEST=1 NC_PCH_CLKOUT_LPC1 NC_PCH_GPD7 TP_PCH_GPP_D0 TP_PCH_GPP_D1 TP_PCH_GPP_D3 TP_PCH_GPP_D4 TP_PCH_GPP_E15 TP_PCH_GPP_F8 TP_PCH_GPP_F9 TP_PCH_GPP_F10 PCH_BT_ROM_BOOT PCH_SOC_DFU_STATUS SOC_PANIC_L SOC_S2R_ACK_L SOC_SLEEP_L TP_PCH_LANPHYPC TP_PCH_PME_L MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NC_PCH_GPP_D0 NC_PCH_GPP_D1 NC_PCH_GPP_D3 NC_PCH_GPP_D4 NC_PCH_GPP_E15 NC_PCH_GPP_F8 NC_PCH_GPP_F9 NC_PCH_GPP_F10 NC_PCH_GPP_F11 NC_PCH_GPP_F18 NC_PCH_GPP_F19 NC_PCH_GPP_F20 NC_PCH_GPP_F21 NC_PCH_LANPHYPC NC_PCH_PME_L TP_PCH_SLP_WLAN_L TP_PCH_STRP_ESPI TP_PCH_STRP_TLSCONF TP_PMIC_PGC TP_SPI_CS1_L TP_SPI_CS2_L TP_SYSCLK_CLK24M_SSD MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NC_PCH_SLP_WLAN_L NC_PCH_STRP_ESPI NC_PCH_STRP_TLSCONF NC_PMIC_PGC NC_SPI_CS1_L NC_SPI_CS2_L NC_SYSCLK_CLK24M_SSD TP_USB3_03_D2RN TP_USB3_03_D2RP TP_USB3_03_R2DN TP_USB3_03_R2DP TP_USB3_04_D2RN TP_USB3_04_D2RP TP_USB3_04_R2DN TP_USB3_04_R2DP MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NC_USB3_03_D2RN NC_USB3_03_D2RP NC_USB3_03_R2DN NC_USB3_03_R2DP NC_USB3_04_D2RN NC_USB3_04_D2RP NC_USB3_04_R2DN NC_USB3_04_R2DP OUT PCH_SOC_FORCE_DFU PCH_SOC_WDOG MAKE_BASE=TRUE MAKE_BASE=TRUE NO_TEST=1 NO_TEST=1 NC_PCH_SOC_FORCE_DFU NC_PCH_SOC_WDOG 14 OUT UPC_I2C_INT_L MAKE_BASE=TRUE NO_TEST=1 NC_UPC_I2C_INT_L 30 IN TP_UPC_XB_SWD_DATA MAKE_BASE=TRUE NO_TEST=1 NC_UPC_XB_SWD_DATA 29 IN 29 IN TP_UPC_XA_SWD_DATA TP_UPC_XA_SWD_CLK MAKE_BASE=TRUE MAKE_BASE=TRUE NO_TEST=1 NO_TEST=1 NC_UPC_XA_SWD_DATA NC_UPC_XA_SWD_CLK 15 IN 15 IN 15 IN 15 IN 15 IN 55 IN IN IN IN IN IN IN IN 19 IN 60 IN 60 IN 19 IN 19 IN 19 IN 19 IN 19 IN TP_PCIE_CLK100M5P TP_PCIE_CLK100M5N TP_PCH_CLKREQ5_L TP_ITPXDP_CLK100MP TP_ITPXDP_CLK100MN TP_CPUVR_GH1 TP_CPU_RSVD_BB69 TP_CPU_RSVD_BB68 TP_CPU_RSVD_BA70 TP_CPU_RSVD_BA68 TP_CPU_RSVD_AW71 TP_CPU_RSVD_AW70 TP_CPU_RSVD_AK12 TP_SPKR_ID0 TP_PGOOD_PVCCIO TP_PGOOD_P1V00 TP_PCH_CLK32K_RTCX2 TP_PCH_CLK24M_XTALOUT TP_XDP_BPM_L TP_XDP_BPM_L TP_XDP_BPM_L MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NC_PCIE_CLK100M5P NC_PCIE_CLK100M5N NC_PCH_CLKREQ5_L NC_ITPXDP_CLK100MP NC_ITPXDP_CLK100MN NC_CPUVR_GH1 NC_CPU_RSVD_BB69 NC_CPU_RSVD_BB68 NC_CPU_RSVD_BA70 NC_CPU_RSVD_BA68 NC_CPU_RSVD_AW71 NC_CPU_RSVD_AW70 NC_CPU_RSVD_AK12 NC_SPKR_ID0 NC_PGOOD_PVCCIO NC_PGOOD_P1V00 NC_PCH_CLK32K_RTCX2 NC_PCH_CLK24M_XTALOUT NC_XDP_BPM_L NC_XDP_BPM_L NC_XDP_BPM_L 16 IN 16 IN 16 IN 16 IN 36 IN IN IN IN IN IN 59 IN IN IN IN IN IN IN IN IN 13 IN 14 IN 14 IN 16 IN 16 IN 16 IN IN 14 IN 14 IN 14 IN 14 IN 13 IN 13 IN 13 IN 13 IN 14 IN 14 IN 14 IN 13 IN 13 IN 60 IN 13 IN 13 IN 19 IN 15 IN 15 IN 15 IN 15 IN 15 IN 15 IN 15 IN 15 IN 14 IN 13 D C NC_DEBUGUART_SEL_SOC MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE BI 15 NO_TEST=1 NC_VCCPRIM_CORE_VID0 NC_VCCPRIM_CORE_VID1 NC_MLB_DEV_L USB3_EXTB_D2R_N USB3_EXTB_D2R_P USB3_EXTB_R2D_C_N USB3_EXTB_R2D_C_P BI 15 NO_TEST=1 NO_TEST=1 MAKE_BASE=TRUE TBT_T_CIO_PWR_EN TBT_T_USB_PWR_EN TBT_T_PCI_RESET_L TBT_T_DPMUX_SEL =TBT_T_CLKREQ_L PCIE_CLK100M_TBT_T_N PCIE_CLK100M_TBT_T_P PCIE_TBT_T_D2R_N PCIE_TBT_T_D2R_P PCIE_TBT_T_R2D_C_N PCIE_TBT_T_R2D_C_P PCIE_TBT_T_D2R_N PCIE_TBT_T_D2R_P PCIE_TBT_T_R2D_C_N PCIE_TBT_T_R2D_C_P OUT NO_TEST=1 NO_TEST=1 MAKE_BASE=TRUE MAKE_BASE=TRUE TBT_X_DPMUX_SEL IN NO_TEST=1 NO_TEST=1 NO_TEST=1 MAKE_BASE=TRUE MAKE_BASE=TRUE PCH_BSSB_CLK PCH_BSSB_DATA 15 15 MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE I2C_UPC_SDA I2C_UPC_SCL IN 16 16 B IN 16 16 VCCPRIM_CORE_VID0 VCCPRIM_CORE_VID1 MLB_DEV_L NC_USB2_01N NC_USB2_01P NC_UPC_XB_I2C_ADDR NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 GND B DESIGN: X502/MLB_CATZ LAST CHANGE: Mon Aug 12:54:34 2016 SYNC_MASTER=PAULM SYNC_DATE=06/15/2015 PAGE TITLE NC_ AND NO_TEST SIGNALS MIN_LINE_WIDTH=0.3000 MIN_NECK_WIDTH=0.0850 DRAWING NUMBER VOLTAGE=0V 15 BI 15 BI 15 BI 15 BI NC_USB2_09N NC_USB2_09P NO_TEST=1 NO_TEST=1 NC_USB2_10N NC_USB2_10P NO_TEST=1 NO_TEST=1 65 65 Digital Ground BI BI MAKE_BASE TRUE TRUE =I2C_BKLT_SCL =I2C_BKLT_SDA Apple Inc I2C_BKLT_SCL I2C_BKLT_SDA REVISION R BI 66 72 BI 66 72 NOTICE OF PROPRIETARY PROPERTY: BOM_COST_GROUP=NO COST ITEMS 051-02265 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED SIZE D 1.0.0 BRANCH PAGE 102 OF 500 SHEET 70 OF 73 A Memory Bit/Byte Swizzle CPU D C B 72 BI 72 BI 72 BI 72 BI 72 BI 72 BI 72 BI 72 BI 72 BI 72 BI 72 BI 72 BI 72 BI 72 BI 72 BI 72 BI 72 BI 72 BI 72 BI 72 BI 72 BI 72 BI 72 BI 72 BI 72 BI 72 BI 72 BI 72 BI 72 BI 72 BI 72 BI 72 BI 72 BI 72 BI 72 BI 72 BI 72 BI 72 BI 72 BI 72 BI 72 BI 72 BI 72 BI 72 BI 72 BI 72 BI 72 BI 72 BI 72 BI 72 BI 72 BI 72 BI 72 BI 72 BI 72 BI 72 BI 72 BI 72 BI 72 BI 72 BI 72 BI 72 BI 72 BI 72 BI 72 BI 72 BI 72 BI 72 BI 72 BI 72 BI 72 BI 72 BI 72 BI 72 BI 72 BI 72 BI 72 BI 72 BI 72 BI 72 BI MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N DRAM MAKE_BASE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE =MEM_A_DQ =MEM_A_DQ =MEM_A_DQ =MEM_A_DQ =MEM_A_DQ =MEM_A_DQ =MEM_A_DQ =MEM_A_DQ =MEM_A_DQ =MEM_A_DQ =MEM_A_DQ =MEM_A_DQ =MEM_A_DQ =MEM_A_DQ =MEM_A_DQ =MEM_A_DQ =MEM_A_DQ =MEM_A_DQ =MEM_A_DQ =MEM_A_DQ =MEM_A_DQ =MEM_A_DQ =MEM_A_DQ =MEM_A_DQ =MEM_A_DQ =MEM_A_DQ =MEM_A_DQ =MEM_A_DQ =MEM_A_DQ =MEM_A_DQ =MEM_A_DQ =MEM_A_DQ =MEM_A_DQ =MEM_A_DQ =MEM_A_DQ =MEM_A_DQ =MEM_A_DQ =MEM_A_DQ =MEM_A_DQ =MEM_A_DQ =MEM_A_DQ =MEM_A_DQ =MEM_A_DQ =MEM_A_DQ =MEM_A_DQ =MEM_A_DQ =MEM_A_DQ =MEM_A_DQ =MEM_A_DQ =MEM_A_DQ =MEM_A_DQ =MEM_A_DQ =MEM_A_DQ =MEM_A_DQ =MEM_A_DQ =MEM_A_DQ =MEM_A_DQ =MEM_A_DQ =MEM_A_DQ =MEM_A_DQ =MEM_A_DQ =MEM_A_DQ =MEM_A_DQ =MEM_A_DQ =MEM_A_DQS_P =MEM_A_DQS_N =MEM_A_DQS_P =MEM_A_DQS_N =MEM_A_DQS_P =MEM_A_DQS_N =MEM_A_DQS_P =MEM_A_DQS_N =MEM_A_DQS_P =MEM_A_DQS_N =MEM_A_DQS_P =MEM_A_DQS_N =MEM_A_DQS_P =MEM_A_DQS_N =MEM_A_DQS_P =MEM_A_DQS_N CPU BI 21 72 BI BI 21 72 BI BI 21 72 BI BI 21 72 BI BI 21 72 BI BI 21 72 BI BI 21 72 BI BI 21 72 BI BI 21 72 BI BI 21 72 BI BI 21 72 BI BI 21 72 BI BI 21 72 BI BI 21 72 BI BI 21 72 BI BI 21 72 BI BI 22 72 BI BI 22 72 BI BI 22 72 BI BI 22 72 BI BI 22 72 BI BI 22 72 BI BI 22 72 BI BI 22 72 BI BI 22 72 BI BI 22 72 BI BI 22 72 BI BI 22 72 BI BI 22 72 BI BI 22 72 BI BI 22 72 BI BI 22 72 BI BI 21 72 BI BI 21 72 BI BI 21 72 BI BI 21 72 BI BI 21 72 BI BI 21 72 BI BI 21 72 BI BI 21 72 BI BI 21 72 BI BI 21 72 BI BI 21 72 BI BI 21 72 BI BI 21 72 BI BI 21 72 BI BI 21 72 BI BI 21 72 BI BI 22 72 BI BI 22 72 BI BI 22 72 BI BI 22 72 BI BI 22 72 BI BI 22 72 BI BI 22 72 BI BI 22 72 BI BI 22 72 BI BI 22 72 BI BI 22 72 BI BI 22 72 BI BI 22 72 BI BI 22 72 BI BI 22 72 BI BI 22 72 BI BI 21 72 BI BI 21 72 BI BI 21 72 BI BI 21 72 BI BI 22 72 BI BI 22 72 BI BI 22 72 BI BI 22 72 BI BI 21 72 BI BI 21 72 BI BI 21 72 BI BI 21 72 BI BI 22 72 BI BI 22 72 BI BI 22 72 BI BI 22 72 BI MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N DRAM MAKE_BASE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE =MEM_B_DQ =MEM_B_DQ =MEM_B_DQ =MEM_B_DQ =MEM_B_DQ =MEM_B_DQ =MEM_B_DQ =MEM_B_DQ =MEM_B_DQ =MEM_B_DQ =MEM_B_DQ =MEM_B_DQ =MEM_B_DQ =MEM_B_DQ =MEM_B_DQ =MEM_B_DQ =MEM_B_DQ =MEM_B_DQ =MEM_B_DQ =MEM_B_DQ =MEM_B_DQ =MEM_B_DQ =MEM_B_DQ =MEM_B_DQ =MEM_B_DQ =MEM_B_DQ =MEM_B_DQ =MEM_B_DQ =MEM_B_DQ =MEM_B_DQ =MEM_B_DQ =MEM_B_DQ =MEM_B_DQ =MEM_B_DQ =MEM_B_DQ =MEM_B_DQ =MEM_B_DQ =MEM_B_DQ =MEM_B_DQ =MEM_B_DQ =MEM_B_DQ =MEM_B_DQ =MEM_B_DQ =MEM_B_DQ =MEM_B_DQ =MEM_B_DQ =MEM_B_DQ =MEM_B_DQ =MEM_B_DQ =MEM_B_DQ =MEM_B_DQ =MEM_B_DQ =MEM_B_DQ =MEM_B_DQ =MEM_B_DQ =MEM_B_DQ =MEM_B_DQ =MEM_B_DQ =MEM_B_DQ =MEM_B_DQ =MEM_B_DQ =MEM_B_DQ =MEM_B_DQ =MEM_B_DQ =MEM_B_DQS_P =MEM_B_DQS_N =MEM_B_DQS_P =MEM_B_DQS_N =MEM_B_DQS_P =MEM_B_DQS_N =MEM_B_DQS_P =MEM_B_DQS_N =MEM_B_DQS_P =MEM_B_DQS_N =MEM_B_DQS_P =MEM_B_DQS_N =MEM_B_DQS_P =MEM_B_DQS_N =MEM_B_DQS_P =MEM_B_DQS_N BI 23 BI 23 BI 23 BI 23 BI 23 BI 23 BI 23 BI 23 BI 23 BI 23 BI 23 BI 23 BI 23 BI 23 BI 23 BI 23 BI 24 BI 24 BI 24 BI 24 BI 24 BI 24 BI 24 BI 24 BI 24 BI 24 BI 24 BI 24 BI 24 BI 24 BI 24 BI 24 BI 23 BI 23 BI 23 BI 23 BI 23 BI 23 BI 23 BI 23 BI 23 BI 23 BI 23 BI 23 BI 23 BI 23 BI 23 BI 23 BI 24 BI 24 BI 24 BI 24 BI 24 BI 24 BI 24 BI 24 BI 24 BI 24 BI 24 BI 24 BI 24 BI 24 BI 24 BI 24 BI 23 BI 23 BI 23 BI 23 BI 24 BI 24 BI 24 BI 24 BI 23 BI 23 BI 23 BI 23 BI 24 BI 24 BI 24 BI 24 D C B DESIGN: X502/MLB_CATZ LAST CHANGE: Thu Aug 21:00:42 2016 A SYNC_MASTER=X502-EXP SYNC_DATE=12/03/2015 PAGE TITLE Memory Signal Swaps DRAWING NUMBER Apple Inc 051-02265 REVISION R NOTICE OF PROPRIETARY PROPERTY: BOM_COST_GROUP=NO COST ITEMS THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED SIZE D 1.0.0 BRANCH PAGE 103 OF 500 SHEET 71 OF 73 A XDP 17 BI 17 BI 17 15 BI 17 15 BI 17 BI 17 D BI 17 BI 17 BI 17 BI 17 BI 17 BI 17 BI 17 BI 17 BI 17 BI 17 BI 17 BI 17 BI 60 17 BI 69 64 63 62 19 BI FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE CPU_CFG ITP_PMODE XDP_CPU_PRDY_L XDP_CPU_PREQ_L XDP_CPU_PWRBTN_L XDP_CPU_TCK XDP_CPU_TDI XDP_CPU_TDO XDP_CPU_TMS XDP_CPU_TRST_L XDP_DBRESET_L XDP_PCH_TCK XDP_PCH_TDI XDP_PCH_TDO XDP_PCH_TMS XDP_PCH_TRST_L XDP_PM_RSMRST_L XDP_PRESENT_CPU XDP_PRESENT_L FUNC_TEST=TRUE FUNC_TEST=TRUE PP1V_S5G GND 15 15 69 64 63 60 58 54 51 BI 51 BI 51 C BI 51 BI 51 BI 51 BI 51 BI 51 BI 51 48 BI 51 48 BI 51 41 69 67 64 63 60 51 50 48 53 52 51 47 42 41 28 19 72 69 68 60 BI BI BI AUD_CONN_HP_LEFT AUD_CONN_HP_RIGHT AUD_CONN_HP_SENSE_L AUD_CONN_HP_SENSE_R AUD_CONN_RING2 AUD_CONN_RING2_XW AUD_CONN_SLEEVE AUD_CONN_SLEEVE_XW AUD_CONN_TIP_SENSE DMIC1_CLK DMIC1_DATA HALL_SENSOR_RIGHT BI MAKE_BASE=TRUE MAKE_BASE=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE PP5V_S4 GND USB_TESTER_P DA410 69 68 63 60 58 53 50 43 BI 69 68 63 53 BI 53 52 BI 72 66 65 BI PPBUS_G3H PPDCIN_G3H PPDCIN_G3H_CHGR PPVOUT_S0_LCDBKLT BI 60 39 14 BI 66 60 59 39 26 14 BI 68 60 39 14 BI 60 39 BI BI BI BI PM_SLP_S0S3_L PM_SLP_S0_L PM_SLP_S3_L PM_SLP_S4_L PM_SLP_S5_L PM_SLP_SUS_L PM_PWRBTN_L ALL_SYS_PWRGD 40 39 28 BI BI SMC_DEBUGPRT_TX_L SMC_DEBUGPRT_RX_L FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE 28 26 BI 28 26 BI 28 26 BI 26 BI 31 28 32 28 51 50 BI 51 50 BI 51 50 51 50 BI BI 8409_SPKR_ID0 SPKRCONN_FL_OUT_N SPKRCONN_FL_OUT_P SPKRCONN_RL_OUT_N SPKRCONN_RL_OUT_P 14 FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE BI 36 36 36 RIGHT SPEAKERS B BI 51 50 BI 51 50 BI 51 50 BI 51 50 BI 36 36 FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE 36 36 FUNC_TEST=TRUE 66 66 66 BATTERY 52 BI 72 42 BI 72 42 BI SYS_DETECT_L SMBUS_SMC_5_G3H_SCL SMBUS_SMC_5_G3H_SCL BI BI BI BI BI BI BI BI CAM_TEST_MODE TP_CAM_LV_JTAG_TCK TP_CAM_LV_JTAG_TDI TP_CAM_LV_JTAG_TDO TP_CAM_LV_JTAG_TMS TP_CAM_LV_JTAG_TRSTN TP_CAM_TEST_MODE0 TP_CAM_TEST_MODE1 TP_CAM_TEST_MODE2 BI BI 69 64 60 69 63 55 45 FUNC_TEST=TRUE FUNC_TEST=TRUE 69 63 57 45 BI 40 39 BI 47 40 39 28 BI 41 BI FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE A BI 47 BI 47 BI 47 BI 47 BI 47 BI 47 47 BI BI SPIROM_USE_MLB SPI_MLBROM_CS_L SPI_MLB_CLK SPI_MLB_CS_L SPI_MLB_IO SPI_MLB_IO SPI_MLB_MISO SPI_MLB_MOSI 35 34 BI 35 15 BI FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE JTAG_TBT_TCK JTAG_TBT_TDI JTAG_TBT_X_TMS TBT_X_TEST_EN PP20V_USBC_XA_VBUS PP20V_USBC_XB_VBUS BI 35 15 BI 35 15 BI 35 34 BI 35 34 BI BI 67 15 BI 67 15 BI 67 15 BI 67 BI 67 BI 30 BI BI BI BI FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE PP1V8_S5G PP1V_OPC_S0 PP3V3_S4_WLS PP3V3_S5 PP3V3_S5G PPVCCCPU_S0G PPVCCGT_S0G PPVCCIO_S0G PPVCCOPC_S0G PPVCCPCH_S5G PPVCCSA_S0G PPVTT_S0 BI BI 31 26 BI 31 26 BI 31 26 BI 31 26 BI 31 BI 31 WIRELESS 34 BI 34 BI 34 BI 34 BI 34 BI 34 BI FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE JTAG_WLAN_SEL TP_JTAG_WLAN_TCK JTAG_WLAN_TDI TP_JTAG_WLAN_TDO TP_JTAG_WLAN_TMS TP_JTAG_WLAN_TRST BI 29 28 BI 29 28 BI 29 28 BI 29 28 BI 32 26 BI BI BI BI DP_INT_HPD EDP_BKLT_PWM EDP_INT_AUX_N EDP_INT_AUX_P FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE BI 32 26 BI 32 26 BI 32 26 BI 32 BI 32 BI 32 30 BI 32 30 BI 32 30 BI 32 30 BI 55 39 38 38 38 38 66 FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE 66 66 BI BI 70 66 BI 70 66 BI 66 BI 66 66 FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE BI 66 BI BI BI 66 16 BI 66 37 BI 66 37 BI 66 37 BI 66 37 BI 66 41 BI 66 BI 66 BI 66 37 BI 72 66 65 BI EDP_PANEL_PWR_EN I2C_ALS_SCL_CONN I2C_ALS_SDA_CONN I2C_BKLT_SCL I2C_BKLT_SDA I2C_CAM_SCL_CONN I2C_CAM_SDA_CONN I2C_TCON_SCL_CONN I2C_TCON_SDA_CONN LCD_IRQ_L MIPI_CLK_CONN_N MIPI_CLK_CONN_P MIPI_DATA_CONN_N MIPI_DATA_CONN_P TCON_BKLT_PWM PP3V3_S0SW_LCD PP5V_S0SW_LCD PP5V_S0_ALSCAM_F PPVOUT_S0_LCDBKLT FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE 38 38 38 BI BI BI BI BI BI BI BI BI BI 38 16 BI 38 16 BI 38 BI 38 16 38 16 38 16 BI BI BI 38 BI 41 38 BI 68 40 39 38 BI 41 40 39 BI 68 60 53 52 51 47 42 41 28 19 72 69 69 67 64 63 45 44 43 41 BI BI 69 64 59 57 56 55 54 BI 38 BI 38 BI FUNC_TEST=TRUE GND BI BI FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE ACT_THERM_TRIP_L FAN_LT_PWM FAN_LT_TACH KBD_BLC_GSLAT KBD_BLC_GSSCK KBD_BLC_GSSIN KBD_BLC_GSSOUT KBD_BLC_XBLANK KBD_I2C_SCL KBD_I2C_SDA KBD_INT_L 62 FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE TPAD_VIBE_L SMC_LSOC_RST SMC_ONOFF_L SMC_PME_S4_WAKE_L PP3V3_G3H PP3V3_S4 PP5V_S0 PP5V_S4_TPAD_CONN PPVIN_S4_TPAD_FUSE FUNC_TEST=TRUE GND BI 61 BI 55 BI 55 BI 55 BI 55 BI 59 BI 59 BI 55 BI 55 BI 56 FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE TPAD_SPI_MOSI TPAD_SPI_INT_L TPAD_SPI_CS_CONN_L TPAD_SPI_MISO TPAD_SPI_IF_EN TPAD_SPI_CLK BI BI TRACKPAD AND KEYBOARD FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE BOOTROM 47 16 BI BI 38 SMC 40 39 BI 59 38 SMC_TCK SMC_TDI SMC_TDO SMC_TMS SMC_DEV_SUPPLY_L BI BI 38 BI BI 69 63 61 38 47 40 39 28 BI DISPLAY 66 GND BI BI 35 34 67 15 CAMERA FUNC_TEST=TRUE 8409_SPKR_ID1 SPKRCONN_FR_OUT_N SPKRCONN_FR_OUT_P SPKRCONN_RR_OUT_N SPKRCONN_RR_OUT_P BI 59 69 62 36 51 48 BI 69 67 64 61 59 69 56 36 GND BI 66 EDP_ML_C_N EDP_ML_C_P EDP_INT_ML_N EDP_INT_ML_P PCIE_AP_D2R_C_N PCIE_AP_D2R_C_P PCIE_AP_D2R_N PCIE_AP_D2R_P PCIE_AP_R2D_C_N PCIE_AP_R2D_C_P PCIE_AP_R2D_N PCIE_AP_R2D_P PCIE_SSD_D2R_N PCIE_SSD_D2R_P PCIE_SSD_R2D_C_N PCIE_SSD_R2D_C_P PCIE_SSD_R2D_N PCIE_SSD_R2D_P USB_UPC_XB_F_N USB_UPC_XB_F_P NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 25 22 BI 25 22 21 BI 25 22 21 BI 25 22 21 BI 25 22 21 BI 71 BI 71 BI 71 BI 25 22 21 BI 25 23 BI 25 24 BI 25 24 23 BI 25 24 23 BI 25 24 23 BI 25 24 23 BI 71 BI 71 BI 71 BI 25 24 23 BI 37 36 BI 37 36 BI 37 36 BI 37 36 BI 37 36 BI 37 36 BI 34 BI 34 BI 34 BI 34 BI 34 BI 34 BI 34 BI 34 BI 34 BI 34 BI 34 BI 34 BI 55 BI 61 BI 61 BI 61 BI 61 BI 61 BI 61 BI 62 BI 61 BI 62 BI 61 BI 55 BI 55 BI 55 45 BI 55 45 BI 55 BI 55 BI BI 54 BI 14 BI 57 BI 57 45 BI 57 BI 57 BI 57 BI 57 BI 57 BI 59 BI 59 BI 59 BI 59 BI 58 BI 58 BI 56 BI 56 BI 59 BI 56 BI 59 BI BI 72 55 BI 27 BI 12 BI 56 BI 72 55 12 BI BI 55 BI 53 BI 60 BI NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 AGND_U7320 BANJO_VBSTVR1 BANJO_VBSTVR3 BANJO_VBSTVR4 BANJO_VBSTVR5 CPUVR_BP2 CPUVR_PHASE2 CPUVR_SNB1 CPUVR_SNB2 PD_VSNS_CPU_VCCEOPIO_TN PD_VSNS_CPU_VCCOPC_TN PPVCCCPU_S0G_PH1 PPVCCCPU_S0G_PH2 PPVCCSA_S0G_R PU_VSNS_CPU_VCCEOPIO_TP PU_VSNS_CPU_VCCOPC_TP NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 VR0V9_IND_TBT_X PP1V_SUS_PCH_VCCAPLL_F PP1V8_S0_PCH_VCCHDA_F NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 MEM_A_CAA MEM_A_CAB MEM_A_CKE MEM_A_CLK_N MEM_A_CLK_P MEM_A_CS_L MEM_A_DQ MEM_A_DQS_N MEM_A_DQS_P MEM_A_ODT NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 MEM_B_CAA MEM_B_CAB MEM_B_CKE MEM_B_CLK_N MEM_B_CLK_P MEM_B_CS_L MEM_B_DQ MEM_B_DQS_N MEM_B_DQS_P MEM_B_ODT NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 MEM_CAM_A MEM_CAM_BA MEM_CAM_DM MEM_CAM_DQ MEM_CAM_DQS_N MEM_CAM_DQS_P RF_0_ANT RF_0_ANT_MATCH_T RF_1_ANT RF_1_ANT_MATCH_T RF_A_0_DIPLEXER RF_A_0_MATCH RF_A_1_DIPLEXER RF_A_1_MATCH RF_G_0_DIPLEXER RF_G_0_MATCH RF_G_1_DIPLEXER RF_G_1_MATCH AGND_U7310 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 BANJO_FBVR2_N BANJO_FBVR2_RC NO_TEST=1 NO_TEST=1 BANJO_SWVR2 BANJO_SWVR2_SNUB BANJO_SWVR3R BANJO_SWVR3_SNUB BANJO_VBSTVR1_R BANJO_VBSTVR3_R BANJO_VBSTVR4_R BANJO_VBSTVR5_R CPUVR_BOOT1 CPUVR_BP1 CPUVR_ISNS2_N CPUVR_ISNS2_P CPUVR_PHASE1 CPUVR_SW1 CPU_PROCHOT_R_L CPU_VCCGTSENSE_N CPU_VCCST_PWRGD_R GTVR_BP1 GTVR_ISNS2_P GTVR_SNB1 GTVR_SNB2 GTVR_SNB3 GTVR_SW1 GTVR_SW2 P1VOPC_BOOT_RC P1VOPC_DRVH_R P1VOPC_REFIN_R P1VOPC_SNS_R P3V3S5_DRVH_R P5VS4_DRVH_R SAVR_BP SAVR_SNB1 SAVR_SW VCINP_P5V_U7310 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 AGND_U7470 VCINP_P5V_U7310 VCINP_P5V_U7320 TBA_PHASE1 PMIC_ENH NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 FOR DC/DC 53 BI 53 BI FOR DEBUG 29 BI 29 BI 30 BI 30 BI TP_UPC_XA_DBG_UART_TX TP_UPC_XA_DBG_UART_RX TP_UPC_XB_DBG_UART_TX TP_UPC_XB_DBG_UART_RX FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE C B SYNC_DATE=06/15/2015 FCT, ICT PROPERTIES FUNC_TEST=TRUE FUNC_TEST=TRUE TBA_HPWR_EN_L PD_TBA_MPM_DET D NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 NO_TEST=1 SYNC_MASTER=PAULM PAGE TITLE BOM_COST_GROUP=NO COST ITEMS BI NO_TEST=1 NO_TEST=1 USBC_XA_D2R_N USBC_XA_D2R_P USBC_XA_R2D_C_N USBC_XA_R2D_C_P USBC_XA_R2D_N USBC_XA_R2D_P USBC_XA_USB_BOT_N USBC_XA_USB_BOT_P USBC_XA_USB_TOP_N USBC_XA_USB_TOP_P USBC_XB_D2R_N USBC_XB_D2R_P USBC_XB_R2D_C_N USBC_XB_R2D_C_P USBC_XB_R2D_N USBC_XB_R2D_P USBC_XB_USB_BOT_N USBC_XB_USB_BOT_P USBC_XB_USB_TOP_N USBC_XB_USB_TOP_P 25 21 POWER MISC BI BI 30 LEFT SPEAKERS BI 0201-THICKSTNCL USBC/TBT 69 68 64 63 61 60 58 44 SSD_BOOT_CONN_L TP_PCH_SLP_A_L BI 66 35 15 69 63 44 67 66 66 ESD112-B1-02ELS MOJO PORT 40 39 28 TPA410 TP-P6 TP TPA411 TP-P6 DA411 SYSTEM STATE 68 60 19 TP FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE 69 63 61 51 48 2 CRITICAL CRITICAL CAP POWER DISCHARGE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE PP1V8_S0 PP3V3_G3H GND BI TP_USB_TESTERN TP_USB_TESTERP FUNC_TEST=TRUE USB_TESTER_N FUNC_TEST=TRUE 0201-THICKSTNCL 41 39 17 FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE BI FUNC_TEST=TRUE FUNC_TEST=TRUE ESD112-B1-02ELS 60 14 AUDIO FLEX BI USB2 FIXTURE PORT 60 39 14 51 DRAWING NUMBER Apple Inc 051-02265 REVISION R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED SIZE D 1.0.0 BRANCH PAGE 104 OF 500 SHEET 72 OF 73 A D D LAST SCHEMATIC PAGE FORCES CROSS REFERENCE PAGES TO COME AFTER THIS SKIPS ANY TEMPORARY PAGES I MIGHT MAKE C C B B DESIGN: X502/MLB_CATZ LAST CHANGE: Thu Aug 21:00:42 2016 A SYNC_MASTER=MICHKLEE PAGE TITLE SYNC_DATE=06/23/2015 =LAST SCHEMATIC PAGE= DRAWING NUMBER Apple Inc 051-02265 REVISION R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED SIZE D 1.0.0 BRANCH PAGE 500 OF 500 SHEET 73 OF 73 A ... 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