99208 apple macbook pro a1386 (MBP 15MLB) schematics

8 CK APPD ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5% ALL CAPACITANCE VALUES ARE IN MICROFARADS ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ REV SCHEM,CORNHOLE,K19 ZONE ECN ENG APPD DESCRIPTION OF CHANGE DATE ? ? ? ? DATE ? PVT 04/24/2009 (.csa) D Page TABLE_TABLEOFCONTENTS_HEAD TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM C TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM B TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM 1 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 10 11 12 13 14 15 16 17 18 19 20 21 22 24 25 26 28 29 31 32 33 34 35 37 38 39 41 42 43 45 46 48 49 50 51 52 Date Contents Sync Table of Contents System Block Diagram Power Block Diagram Power Block Diagram BOM Configuration JTAG Scan Chain Functional / ICT Test Power Aliases Signal Aliases CPU FSB CPU Power & Ground CPU Decoupling & VID eXtended Debug Port(MiniXDP) MCP CPU Interface MCP Memory Interface MCP Memory Misc MCP PCIe Interfaces MCP Ethernet & Graphics MCP PCI & LPC MCP SATA & USB MCP HDA & MISC MCP Power & Ground MCP79 A01 Silicon Support MCP Standard Decoupling MCP Graphics Support SB Misc FSB/DDR3/FRAMEBUF Vref Margining DDR3 SO-DIMM Connector A DDR3 SO-DIMM Connector B DDR3 Support Right Clutch Connector SECUREDIGITAL CARD READER Ethernet PHY (RTL8211CL) Ethernet & AirPort Support Ethernet Connector FireWire LLC/PHY (FW643) FireWire Port Power FireWire Ports SATA Connectors External USB Connectors Front Flex Support SMC SMC Support LPC+SPI Debug Connector K19 SMBUS CONNECTIONS 12/05/2008 (.csa) Page TABLE_TABLEOFCONTENTS_HEAD DDR 12/12/2007 TABLE_TABLEOFCONTENTS_ITEM T18_MLB 12/12/2007 TABLE_TABLEOFCONTENTS_ITEM T18_MLB N/A TABLE_TABLEOFCONTENTS_ITEM N/A 12/18/2008 TABLE_TABLEOFCONTENTS_ITEM DDR 07/22/2008 TABLE_TABLEOFCONTENTS_ITEM DDR N/A TABLE_TABLEOFCONTENTS_ITEM N/A (MASTER) TABLE_TABLEOFCONTENTS_ITEM (MASTER) (MASTER) TABLE_TABLEOFCONTENTS_ITEM (MASTER) 11/12/2008 TABLE_TABLEOFCONTENTS_ITEM M98_MLB 11/12/2008 TABLE_TABLEOFCONTENTS_ITEM M98_MLB 10/17/2007 TABLE_TABLEOFCONTENTS_ITEM M87_MLB 11/12/2008 TABLE_TABLEOFCONTENTS_ITEM M98_MLB 12/12/2008 TABLE_TABLEOFCONTENTS_ITEM T18_MLB 12/12/2008 TABLE_TABLEOFCONTENTS_ITEM T18_MLB 12/12/2008 TABLE_TABLEOFCONTENTS_ITEM T18_MLB 04/04/2008 TABLE_TABLEOFCONTENTS_ITEM T18_MLB 12/12/2008 TABLE_TABLEOFCONTENTS_ITEM T18_MLB 12/12/2008 TABLE_TABLEOFCONTENTS_ITEM T18_MLB 12/12/2008 TABLE_TABLEOFCONTENTS_ITEM T18_MLB 12/12/2008 TABLE_TABLEOFCONTENTS_ITEM T18_MLB 12/12/2008 TABLE_TABLEOFCONTENTS_ITEM T18_MLB 03/31/2008 TABLE_TABLEOFCONTENTS_ITEM T18_MLB 06/18/2008 TABLE_TABLEOFCONTENTS_ITEM T18_MLB 06/18/2008 AMASON_M98_MLB 12/15/2008 DDR 12/05/2008 DDR 07/22/2008 DDR 07/22/2008 DDR 12/12/2008 T18_MLB 12/08/2008 MUXGFX 01/30/2009 VEMURI 07/01/2008 SUMA_M98_MLB 07/01/2008 SUMA_M98_MLB 12/16/2008 AMASON_M98_MLB 08/14/2008 SENSOR 12/22/2008 YUN_K19_MLB 08/14/2008 SENSOR 12/04/2008 PWRSQNC 11/14/2008 M98_MLB 12/04/2008 PWRSQNC 12/12/2008 T18_MLB 12/19/2008 DDR 05/09/2008 CHANGZHANG 12/19/2008 DDR TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 53 54 55 56 57 58 59 60 61 62 63 65 66 67 68 69 70 71 72 73 75 76 77 78 79 80 81 82 84 85 86 87 88 89 90 93 94 95 96 97 98 99 100 101 102 Date Contents Current & Voltage Sensing Current Sensing Thermal Sensors Fan Connectors WELLSPRING WELLSPRING Sudden Motion Sensor (SMS) DEBUG SENSORS AND ADC SPI ROM AUDIO: CODEC/REGULATOR AUDIO: LINE INPUT FILTER AUDIO: HEADPHONE FILTER AUDIO: SPEAKER AMP AUDIO: JACKS AUDIO: JACK TRANSLATORS DC-In & Battery Connectors PBus Supply & Battery Charger IMVP6 CPU VCore Regulator 5V / 3.3V Power Supply 1.5V DDR3 Supply MCP CORE REGULATOR CPU VTT / 1V05 S0 Power Supply Misc Power Supplies Power Control Power FETs NV G96 PCI-E NV G96 Core/FB Power NV G96 Frame Buffer I/F GDDR3 Frame Buffer A (Top) GDDR3 Frame Buffer B (Top) NV G96 GPIO/MIO/Misc G96 GPIOs & Straps NV G96 Video Interfaces GPU (G96) CORE SUPPLY LVDS Display Connector Muxed Graphics Support DisplayPort Connector 1.1V / 1V8 FB Power Supply Graphics MUX (GMUX) LCD BACKLIGHT DRIVER LCD Backlight Support Misc Power Supplies CPU/FSB Constraints Memory Constraints MCP Constraints Page 08/14/2008 TABLE_TABLEOFCONTENTS_HEAD SENSOR 12/10/2008 YUN_K19_MLB 12/22/2008 YUN_K19_MLB 10/17/2007 M87_MLB 06/18/2008 AMASON_M98_MLB 01/05/2009 PWRSQNC 08/14/2008 SENSOR 12/19/2008 DDR 07/01/2008 CHANG_M98_MLB 03/16/2009 AUDIO 03/16/2009 AUDIO 03/16/2009 AUDIO 03/16/2009 AUDIO 03/16/2009 AUDIO 03/16/2009 AUDIO 12/16/2008 YUN_K19_MLB 12/10/2007 M99_MLB 10/17/2007 M87_MLB 12/17/2008 PWRSQNC 12/05/2008 DDR 11/14/2008 M98_MLB 12/14/2007 M99_MLB 12/14/2007 M99_MLB 12/17/2008 PWRSQNC 12/05/2008 DDR 07/10/2008 MUXGFX 07/10/2008 MUXGFX 07/10/2008 MUXGFX 07/10/2008 MUXGFX 07/10/2008 MUXGFX 07/10/2008 MUXGFX 07/09/2008 MUXGFX 07/10/2008 MUXGFX 10/17/2007 M87_MLB 12/19/2008 DDR 12/05/2008 AMASON_M98_MLB 07/10/2008 MUXGFX 07/10/2008 MUXGFX 07/10/2008 MUXGFX 12/12/2008 DDR 07/02/2008 YITE_M98_MLB 02/01/2008 MUXGFX 02/18/2008 MUXGFX 02/18/2008 MUXGFX 02/18/2008 MUXGFX TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM 91 92 93 94 95 96 97 103 104 105 106 107 108 109 Contents MCP Constraints Ethernet Constraints FireWire Constraints SMC Constraints GPU (G96) CONSTRAINTS Project Specific Constraints PCB Rule Definitions D Date Sync 02/18/2008 MUXGFX 02/18/2008 MUXGFX 02/18/2008 MUXGFX 02/18/2008 MUXGFX 02/18/2008 MUXGFX 02/21/2008 MUXGFX 01/22/2008 M99_MLB TABLE_TABLEOFCONTENTS_ITEM C B TABLE_TABLEOFCONTENTS_ITEM ALIASES RESOLVED A (.csa) Sync Schematic / PCB #’s PART NUMBER DIMENSIONS ARE IN MILLIMETERS APPLE INC METRIC XX X.XX DRAFTER THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING ENG APPD MFG APPD QA APPD DESIGNER RELEASE SCALE I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART ANGLES QTY DESCRIPTION REFERENCE DES CRITICAL 051-7892 SCHEM,CORNHOLE,K19 SCH CRITICAL 820-2523 PCBF,CORNHOLE,K19 PCB CRITICAL A NOTICE OF PROPRIETARY PROPERTY DESIGN CK X.XXX BOM OPTION TITLE DO NOT SCALE DRAWING DRAWING SIZE ABBREV=DRAWING TITLE=MLB LAST_MODIFIED=Fri Apr 24 15:23:24 2009 THIRD ANGLE PROJECTION SCHEM,MBP 15MLB NONE MATERIAL/FINISH NOTED AS APPLICABLE D DRAWING NUMBER REV 051-7892 SHT 1 A.0.0 OF 97 U1000 U1300 INTEL CPU XDP CONN 2.X OR 3.X GHZ PG 12 PENRYN PG FSB D D J6950 64-Bit 800/1067/1333 MHz DC/BATT POWER SUPPLY PG 13 PG 60 J2900 UDIMMs MAIN FSB INTERFACE GPIOs DDR2-800MHZ DDR3-1067/1333MHZ MEMORY DIMM PG 14 U4900 PG 25,26 TEMP SENSOR PG 41 Misc CLK PG 24 U6100 SYNTH POWER SENSE PG 45 SPI Boot ROM J4510 J5650,5600,5610,5611,5660,5720,5730,5750 FAN CONN AND CONTROL SPI SATA PG 52 Conn 1.05V/3GHZ PG 48,49 PG 20 PG 38 HD NVIDIA J4520 J4900 B,0 SATA Conn PG 38 C ADC BSB Fan Ser J5100 MCP79 SATA 1.05V/3GHZ Prt SMC LPC Conn LPC PG 19 ODD Port80,serial PG 41 C PG 43 PG 18 U1400 J9000 PWR LVDS CONN CTRL LVDS OUT PG 71 RGB OUT J4720 DP OUT IR J3900,4635,4655 CAMERA HDMI OUT EXTERNAL USB Connectors PG 40 PG 40 PG 40 PG 40 USB PG 16 PCI-E UP TO 20 LANES3 B PG 17 PG 19 TMDS OUT PG 39 DVI OUT PG 71 J4710 J4710 TRACKPAD/ KEYBOARD DISPLAY PORT CONN J4700 Bluetooth (UP TO 12 DEVICES) J9400 B SMB SMB PG 20 CONN RGMII HDA PCI PG 44 DIMM’s (UP TO FOUR PORTS) PG 17 PG 18 PG 20 U6200 Audio Codec PG 53 U6301 U6400 U6500 System Block Diagram U6600,6605,6610,6620 U3700 A GB Line In Line Out Speaker E-NET Amp Amp Amp Amps PG 54 PG 55 PG 56 PG 57 HEADPHONE SYNC_MASTER=T18_MLB SYNC_DATE=12/12/2007 NOTICE OF PROPRIETARY PROPERTY 88E1116 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING PG 31 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE J3400 II NOT TO REPRODUCE OR COPY IT U3900 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART Mini PCI-E J6800,6801,6802,6803 E-NET AirPort Conn PG 28 Audio SIZE Conns D PG 33 PG 59 APPLE INC DRAWING NUMBER SCALE SHT NONE REV 051-7892 A.0.0 OF 97 A M98 POWER SYSTEM ARCHITECTURE SMC PWRGD RN5VD30A-F U5000 (PAGE 43) D6905 V PP3V42_G3H_REG LT3470 U6990 (PAGE 59) Q5315 VIN CPUVTTS0_EN PPBUS_G3H CHGR_EN (S5) 6A FUSE DCIN(16.5V) A ENABLES PM_GPUVCORE_EN VIN LIO_DCIN_ISENSE VIN ISL6263B U8900 EN_PSV A (PAGE 60) PBUS SUPPLY/ BATTERY CHARGER VOUT PGOOD CPUVTTS0_PGOOD GPUVCORE_PGOOD MCP79 CK_PWRGD U2830 VR_PWRGD_CLKEN U5400 V MCP_PS_PWRGD U1400 (PAGE 14~22) U2850 VR_PWRGD_CLKEN_L VR_PWRGOOD_DELAY PGOOD Q7920 (PAGE 61) C PP5V_S0_FET CPU PPBUS_G3H EN1 PP1V1_S0GPU_REG VIN PWRGOOD U1000 (PAGE 10,11) P5VS0_SS P1V1GPU_EN P3V3S3_EN CPU_PWRGD PWROK CPUPWRGD(GPIO49) PPVCORE_CPU_S0 VR_ON PPVBAT_G3H_CHGR_R CHGR_BGATE PLT_RST_L RSMRST* SMC_CPU_VSENSE A CPUVCORE_IOUT VOUT U7100 IMVP_VR_ON_R Q7055 MCP79 PWRBTN# VRMPWRGD PLTRST* VIN ISL9504B C (18A MAX CURRENT) U5715 A SMC_BATT_ISENSE J6950 BATT_POS_F TPS51117 U7600 (PAG 66) (PAGE 78) CPU VCORE (9 TO 12.6V) D 1.05V PPVCORE_GPU_REG GPUVCORE_IOUT PGOOD ISL6258A U7000 3S2P VOUT VOUT (6A MAX CURRENT) V U5498 PPCPUVTT_S0_REG EN_PSV SMC_GPU_VSENSE GPU VCORE AC ADAPTER IN SMC_RESET_L 3.425V G3HOT PBUSB_VSENSE 8A FUSE PPVBAT_G3H_CHGR_REG U5705 ENABLE PPVIN_G3H_P3V42G3H D6905 D RESET* Q7900 VOUT1 PP5V_S3_FET 1.103V(L/H) SLP_S5#(H17) P5VS3_EN LIO_S3_EN SLP_S3#(G17) P1V8FB_EN U4900 P60 (PAGE 14~22) EN2 1.8V(R/H) SMC U1400 (PAGE 42) PP1V8_GPU_REG VOUT2 P5VS3_SS TPS51124 U9500 (PAGE 82) U7859 SMC_PM_G2_EN VIN 5V VOUT1 (S5) 3.3V VOUT2 (R/H) P3V3S5_EN VIN P5V_RT_EN U7400 PP5V_RT_REG VOUT EN/PSV SC417 (PAGE 64) P5V_RT_PGOOD ENL PGOOD PP5V_S5_REG PP5V_S3 (8A MAX CURRENT) (L/H) PP3V3_S5_REG PP3V3_S5 ISL8009 V4 Q7910 TPS51125 U7201 (PAGE 62) PGOOD1,2 VREG3 PP3V3_S3_FET EN0 U7750 (PAGE 66) P3V3S3_SS P5V3V3_S5_PGOOD Q7930 Q3805 B PP1V05_S5_MCP (5.5A MAX CURRENT) SMC PP3V3_S0GPU_FET PM_RSMRST_L RSMRST_OUT(P15) PM_WLAN_EN_L ALL_SYS_PWRGD WOW_EN PWRGD(P12) VIN P3V3S0_SS GOSHAWK6P Q3801 BKLT_EN PM_ENET_EN RSMRST_PWRGD PPVOUT_S0_LCDBKLT PP3V3_S0_FET ENA VOUT (PAGE 84) PLT_RST* SMC_ONOFF_L PWR_BUTTON(P90) P17(BTN_OUT) P1V05S0_PGOOD P5VRIGHT_PGOOD P3V3GPU_SS VIN LTC3407 P1V2ENET_EN RUN2 ENETAVDD_EN Q3810 PP1V9_ENET_REG VOUT1 P3V3_ENET_FET U3850 (PAGE 33) RUN1 VOUT2 PM_ENET_EN_L MCPCORES0_PGOOD CPUVTTS0_PGOOD PP1V2_ENET_REG RST* PM_SLP_S5_L PM_PWRBTN_L SMC_RESET_L SLP_S5_L(P95) PM_SLP_S4_L SLP_S4_L(P94) P1V8S0_PGOOD P3V3ENET_EN_L PM_SLP_S3_L SLP_S3_L(P93) P1V5S0_PGOOD Q3800 IMVP_VR_ON RSMRST_IN(P13) Q7970 U9701 B 99ms DLY IMVP_VR_ON(P16) PPVIN_S0_DDRREG_LDO U4900 (PAGE 42) S0PGOOD_PWROK WOL_EN PM_ENET_EN_L SMC_ADAPTER_EN RC DELAY A P5VRIGHT_EN RC DELAY P1V8S0_EN MCPDDR_EN RC DELAY CPUVTTS0_EN RC DELAY MCPCORES0_EN VLDOIN 1.8V VOUT1 PPDDR_S3_REG S3 0.9V VOUT2 RST* PPVTT_S0_DDR_LDO TPS51116 U7300 (PAGE 63) P5VS0_EN RC DELAY S5 (12A MAX CURRENT) DDRVTT_EN PM_SLP_S3_L RC DELAY VIN DDRREG_EN (S0) P3V3S0_EN (S0) PBUSVSENS_EN (S0) PP5V_S0 V1 PP3V3_S0 V2 V3 PP1V5_S0_REG MCP_CORE MCPCORES0_EN P1V05S0_EN VIN SYNC_DATE=12/12/2007 NOTICE OF PROPRIETARY PROPERTY U7870 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING (PAGE 68) (25A MAX CURRENT) I TO MAINTAIN THE DOCUMENT IN CONFIDENCE PP5V_RT_REG VOUT1 II NOT TO REPRODUCE OR COPY IT (5A MAX CURRENT) III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE ISL6236 U7500 DRAWING NUMBER D (PAGE 65) (S0) LTC2900 VOUT2 1.1V EN1 PM_SLP_S3_DELAY_L MCPCPCORE_S0_REG EN2 V4 Power Block Diagram SYNC_MASTER=T18_MLB APPLE INC SCALE SHT NONE REV 051-7892 A.0.0 OF 97 A D D C C B B Power Block Diagram A SYNC_MASTER=N/A SYNC_DATE=N/A NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC SCALE SHT NONE REV 051-7892 A.0.0 OF 97 A BOM Variants TABLE_ALT_HEAD TABLE_BOMGROUP_HEAD BOM NUMBER BOM NAME BOM OPTIONS PART NUMBER ALTERNATE FOR PART NUMBER 138S0603 BOM OPTION REF DES COMMENTS: 138S0602 ALL Murata alt to Samsung 353S1681 353S1294 ALL LMV2011,OPAMP GBW 152S0276 152S0683 ALL Maglayers alt to Dale/Vishay 341S2367 341S2366 ALL Macronix alt to SST 152S1034 152S0867 ALL Toko alt to Delta 157S0058 157S0055 ALL Delta alt to TDK Magnetics 152S0915 152S0796 ALL Maglayers alt to Cyntec IND 128S0220 128S0262 ALL KEMET ALT TO SANYO 127S0062 127S0108 ALL ROHM ALT TO KEMET 152S0968 152S0966 ALL Maglayer alt to Delta 311S0447 311S0406 ALL NXP alt to TI 338S0714 338S0554 ALL Low Leakage G96 GPU 107S0138 107S0074 ALL CYNTEC alt to YDS 107S0139 107S0075 ALL CYNTEC alt to YDS TABLE_BOMGROUP_ITEM 630-9965 PCBA,2.66GHZ,256SAM_VRAM,HB_AUDIO,K19 TABLE_ALT_ITEM K19_COMMON,DEVEL_BOM,EEE_6XN,CPU_2_66GHZ,FB_256_SAMSUNG TABLE_BOMGROUP_ITEM 630-9966 PCBA,2.66GHZ,256HYN_VRAM,HB_AUDIO,K19 TABLE_ALT_ITEM K19_COMMON,DEVEL_BOM,EEE_6XP,CPU_2_66GHZ,FB_256_HYNIX TABLE_BOMGROUP_ITEM 630-9967 PCBA,2.80GHZ,512SAM_VRAM,HB_AUDIO,K19 TABLE_ALT_ITEM K19_COMMON,DEVEL_BOM,EEE_6XQ,CPU_2_80GHZ,FB_512_SAMSUNG TABLE_BOMGROUP_ITEM 630-9968 PCBA,2.80GHZ,512HYN_VRAM,HB_AUDIO,K19 TABLE_ALT_ITEM K19_COMMON,DEVEL_BOM,EEE_6XR,CPU_2_80GHZ,FB_512_HYNIX TABLE_BOMGROUP_ITEM 630-9969 PCBA,3.06GHZ,512SAM_VRAM,HB_AUDIO,K19 TABLE_ALT_ITEM K19_COMMON,DEVEL_BOM,EEE_6XS,CPU_3_06GHZ,FB_512_SAMSUNG TABLE_BOMGROUP_ITEM 630-9970 D PCBA,3.06GHZ,512HYN_VRAM,HB_AUDIO,K19 TABLE_ALT_ITEM K19_COMMON,DEVEL_BOM,EEE_6XT,CPU_3_06GHZ,FB_512_HYNIX TABLE_BOMGROUP_ITEM 085-0736 K19 MLB DEVELOPMENT D TABLE_ALT_ITEM K19_DEVEL_PVT TABLE_ALT_ITEM K19 BOM Groups TABLE_ALT_ITEM TABLE_BOMGROUP_HEAD BOM GROUP BOM OPTIONS K19_COMMON ALTERNATE,COMMON,K19,K19_COMMON1,K19_COMMON2,K19_PROGPARTS K19_COMMON1 BOOT_MODE_USER,DPMUX_EN_S0,DP_CA_DET_EG_PLD,DP_ESD,EG_PWRSEQ_HW,EXTRACT_BUFF K19_COMMON2 GMUX_1V8,GPUVID_1P00V,GPU_SS_INT,ISL6258A,MCP_B03,MCPSEQ_SMC,MIKEY,MUXGFX,SMC_DEBUG_YES,XDP K19_DEVEL_ENG BMON_ENG,DEBUG_ADC,GMUX_JTAG,LPCPLUS,VREFMRGN,XDP_CONN K19_DEVEL_PVT BMON_PROD,LPCPLUS,NO_VREFMRGN,XDP_CONN K19_PROD BMON_PROD,LPCPLUS_NOT,NO_VREFMRGN K19_PROGPARTS GMUX_PROG,BOOTROM_PROG,SMC_PROG,TPAD_PROG BOM GROUP BOM OPTIONS FB_256_SAMSUNG VRAM4,VRAM_256_SAMSUNG FB_256_HYNIX VRAM4,VRAM_256_HYNIX FB_512_SAMSUNG VRAM4,VRAM_512_SAMSUNG FB_512_HYNIX VRAM4,VRAM_512_HYNIX TABLE_ALT_ITEM TABLE_BOMGROUP_ITEM TABLE_ALT_ITEM TABLE_BOMGROUP_ITEM TABLE_ALT_ITEM TABLE_BOMGROUP_ITEM TABLE_ALT_ITEM TABLE_BOMGROUP_ITEM TABLE_ALT_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_HEAD TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM C C Bar Code Labels / EEE #’s PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION 826-4393 LBL,P/N LABEL,PCB,28MM X MM [EEE:6XN] CRITICAL EEE_6XN 826-4393 LBL,P/N LABEL,PCB,28MM X MM [EEE:6XP] CRITICAL EEE_6XP 826-4393 LBL,P/N LABEL,PCB,28MM X MM [EEE:6XQ] CRITICAL EEE_6XQ 826-4393 LBL,P/N LABEL,PCB,28MM X MM [EEE:6XR] CRITICAL EEE_6XR 826-4393 LBL,P/N LABEL,PCB,28MM X MM [EEE:6XS] CRITICAL EEE_6XS 826-4393 LBL,P/N LABEL,PCB,28MM X MM [EEE:6XT] CRITICAL EEE_6XT DESCRIPTION REFERENCE DES Module Parts PART NUMBER B QTY CRITICAL BOM OPTION 337S3761 IC,PDC,SLGLA,PRQ,2.66G,25W,1066,R0,3M,BGA U1000 CRITICAL CPU_2_66GHZ 337S3682 IC,PDC,SLGEM,PRQ,2.80G,35W,1066,E0,6M,BGA U1000 CRITICAL CPU_2_80GHZ 337S3744 IC,PDC,SLGKH,QS,3.06G,35W,1066,E0,6M,BGA U1000 CRITICAL CPU_3_06GHZ 338S0710 IC,MCP79MXT-B3,35X35MM,BGA1437 U1400 CRITICAL MCP_B03 338S0694 IC,RTL8251CA-VB-GR,GIGE TRANSCEIVER,48P LQFP U3700 CRITICAL 338S0654 IC,FW643-E,1394B PHY/OHCI LINK/PCI-E,12 U4100 CRITICAL 341S2384 IR,ENCORE II, CY7C63803-LQXC U4800 CRITICAL 338S0563 IC,SMC,HS8/2117,9MMX9MM,TLP U4900 CRITICAL 341S2462 IC,SMC,DEVELOPMENT,K19 U4900 CRITICAL SMC_PROG 341S2503 IC,PSOC +W/USB,56PIN,MLF,K19 U5701 CRITICAL TPAD_PROG 335S0384 IC,32MBIT 8-PIN SPI SERIAL FLASH,SOIC8 U6100 CRITICAL BOOTROM_BLANK 341S2456 IC,EFI ROM,DEVELOPMENT,K19 U6100 CRITICAL BOOTROM_PROG 338S0554 IC,GPU,55nm,NV G96-GS,BGA969,LF U8000 CRITICAL 333S0507 IC,SGRAM,GDDR3,16Mx32,1000MHZ,136 FBGA U8400,U8450,U8500,U8550 CRITICAL 333S0483 IC,SGRAM,GDDR3,16Mx32,900MHZ,136 FBGA U8400,U8450,U8500,U8550 CRITICAL VRAM_256_HYNIX 333S0511 IC,SGRAM,GDDR3,32Mx32,800MHZ,136 FBGA U8400,U8450,U8500,U8550 CRITICAL VRAM_512_SAMSUNG 333S0506 IC,SGRAM,GDDR3,32Mx32,900MHZ,136 FBGA U8400,U8450,U8500,U8550 CRITICAL VRAM_512_HYNIX B SMC_BLANK VRAM_256_SAMSUNG Development BOM PART NUMBER 085-0736 QTY DESCRIPTION REFERENCE DES K19 MLB DEVELOPMENT DEVEL CRITICAL CRITICAL BOM OPTION DEVEL_BOM BOM Configuration A SYNC_MASTER=DDR SYNC_DATE=12/18/2008 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC SCALE SHT NONE REV 051-7892 A.0.0 OF 97 A 1.05V TO 3.3V LEVEL TRANSLATOR (M98: ON ICT FIXTURE) D 82 81 80 77 70 69 68 63 60 59 PP3V3_S0 28 25 24 22 21 19 18 13 55 51 49 48 47 45 43 39 37 29 96 85 84 U1000 CPU From XDP connector JTAG_ALLDEV JTAG_ALLDEV C0601 C0602 0.1UF 0.1UF 20% 10V CERM 402 20% 10V CERM 402 88 13 10 IN 88 13 10 IN 88 13 10 IN 88 13 10 IN XDP_TCK XDP_TDI XDP_TMS XDP_TRST_L D To XDP connector and/or level translator PPCPUVTT_S0 20 18 17 14 13 12 11 10 67 63 25 24 22 XDP R0603 88 10 XDP_TDO PLACEMENT_NOTE=Place near pin U1000.AB3 XDP_TDO_CONN 5% 1/16W MF-LF 402 13 OUT XDP connector JTAG_ALLDEV R0601 11 10K 5% 1/16W MF-LF 402 From XDP connector or via level translator VCCA VCCB U0600 U1400 MCP NLSV4T244 XDP_TCK 88 13 10 NOSTUFF R0602 5% 1/16W MF-LF 402 XDP_TMS XDP_TRST_L 88 13 10 88 13 10 A1 A2 A3 A4 UQFN JTAG_ALLDEV B1 B2 B3 B4 10 MAKE_BASE=TRUE MAKE_BASE=TRUE JTAG_LVL_TRANS_EN_L 12 OE* 13 21 76 XDP 13 21 R0604 13 21 21 13 21 76 JTAG_MCP_TDO 2 PLACEMENT_NOTE=Place near pin U1400.F19 JTAG_MCP_TDO_CONN 5% 1/16W MF-LF 402 R0606 10K GND C JTAG_MCP_TCK JTAG_MCP_TDI JTAG_MCP_TMS JTAG_MCP_TRST_L 5% 1/16W MF-LF 402 13 OUT XDP connector C R0607 5% 1/16W MF-LF 402 NOSTUFF U8000 GPU VCC U0601 JTAG_MCP_TCK GPU_JTAG_TDI GPU_JTAG_TMS JTAG_MCP_TRST_L 74LVC1G07 GMUX CPLD Programming Port NC A NC SOT886 Y NC R0605 81 79 77 76 70 69 PP3V3_S0GPU 10K PLACEMENT_NOTE=Place close to U8000 GPU_JTAG_TMS 76 5% 1/16W MF-LF 402 13 21 76 76 76 13 21 76 76 TP_GPU_JTAG_TDO TP_GPU_JTAG_TDO NC 76 MAKE_BASE=TRUE GND GMUX_JTAG CRITICAL PLACEMENT_NOTE=Place close to U0600 J0600 1909782 M-RT-SM PP3V3_S0 TDO TDI TMS 59 60 63 68 69 70 77 80 81 82 13 18 19 21 22 24 25 28 29 37 39 43 45 47 48 49 51 55 84 85 96 U9200 GMUX B TCK JTAG_GMUX_TCK JTAG_GMUX_TDI JTAG_GMUX_TMS B 84 19 84 19 84 84 17 JTAG_GMUX_TDO JTAG Scan Chain A SYNC_MASTER=DDR SYNC_DATE=07/22/2008 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC SCALE SHT NONE REV 051-7892 A.0.0 OF 97 A Fan Connectors D C PP5V_S0 TRUE TRUE TRUE TRUE FAN_LT_PWM FAN_LT_TACH FAN_RT_PWM FAN_RT_TACH TRUE GND 66 67 70 39 44 49 51 63 83 85 TPs 49 SATA ODD Connectors 49 FUNC_TEST 49 TPs TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE LVDS_DDC_CLK LVDS_DDC_DATA LVDS_CONN_A_DATA_N LVDS_CONN_A_DATA_P LVDS_CONN_A_DATA_N LVDS_CONN_A_DATA_P LVDS_CONN_A_DATA_N LVDS_CONN_A_DATA_P LVDS_CONN_A_CLK_F_N LVDS_CONN_A_CLK_F_P LVDS_CONN_B_DATA_N LVDS_CONN_B_DATA_P LVDS_CONN_B_DATA_N LVDS_CONN_B_DATA_P LVDS_CONN_B_DATA_N LVDS_CONN_B_DATA_P LVDS_CONN_B_CLK_F_N LVDS_CONN_B_CLK_F_P LED_RETURN_1 LED_RETURN_2 LED_RETURN_3 LED_RETURN_4 LED_RETURN_5 LED_RETURN_6 BKL_ISEN1 BKL_ISEN2 BKL_ISEN3 BKL_ISEN4 BKL_ISEN5 BKL_ISEN6 TRUE 59 60 63 68 69 70 77 80 81 82 13 18 19 21 22 24 25 28 29 37 39 43 45 47 48 49 51 55 84 85 96 80 TRUE TRUE GND 80 81 80 81 95 80 81 95 80 81 95 80 81 95 80 81 95 80 95 80 95 80 81 95 80 81 95 80 81 95 80 81 95 80 81 95 80 81 95 80 95 80 95 80 85 80 85 80 85 80 85 80 85 80 85 85 85 85 85 85 85 TPs 55 61 55 20 GND TRUE 39 90 TPs 51 51 50 51 50 51 50 51 50 51 50 51 51 50 51 50 51 50 51 50 51 50 51 50 51 50 51 31 42 45 51 94 31 42 45 51 94 50 51 50 51 TPs 18 Battery Connector 39 90 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE 21 27 31 32 45 50 52 70 TRUE GND 50 50 FUNC_TEST 50 PP3V42_G3H SMBUS_SMC_BSA_SCL SMBUS_SMC_BSA_SDA SMC_BIL_BUTTON_L SMC_LID_R GND TRUE TRUE TRUE TRUE TRUE TRUE 50 50 50 50 50 TRUE GND 19 61 TPs 15 16 16 16 45 46 50 61 62 64 69 44 43 40 42 21 22 26 16 TPs 42 45 61 62 94 16 42 43 61 16 61 16 TPs 16 Power Nets 50 50 50 16 16 21 FUNC_TEST 50 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE 50 50 50 50 50 50 50 50 50 50 50 50 50 51 TPs 17 31 90 17 31 90 31 90 96 31 90 96 31 96 31 96 31 PPVCORE_S0_CPU PPVCORE_S0_MCP_REG PP0V9R0V75_S0_DDRVTT PPCPUVTT_S0 PP1V8R1V5_S0_FET PP1V8_S0 PP3V3_S0 PP1V8R1V5_S3 PP3V3_S3 PP1V2R1V05_S5 PP3V3_S5 PP3V42_G3H PPBUS_G3H PP3V3_ENET_PHY PP1V2R1V05_ENET PP5V_S3 PP3V3_S5_AVREF_SMC PP18V5_S3 PP3V3_S3_LDO PPVOUT_S0_LCDBKLT PP4V5_AUDIO_ANALOG SMC_PM_G2_EN PM_SLP_S4_L PM_SLP_S3_L PP1V05_S0_MCP_PLL_UF PP5V_SW_ODD PP5V_S0_HDD_FLT BKL_VLDO 50 11 12 46 63 TRUE GND MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE TRUE TRUE TRUE TRUE TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE 32 TPs 10 11 12 13 14 17 18 20 22 24 25 63 67 11 12 16 24 28 29 39 68 69 70 18 25 55 69 70 84 87 59 60 63 68 69 70 77 80 81 82 13 18 19 21 22 24 25 28 29 37 39 43 45 47 48 49 51 55 84 85 96 28 29 30 65 70 21 27 31 32 45 50 52 70 19 22 24 34 68 19 18 20 22 24 26 30 34 37 38 44 54 64 68 69 70 82 87 96 21 22 26 40 42 43 44 45 46 50 61 62 64 69 19 37 46 61 62 64 65 66 67 79 83 86 18 24 33 34 19 18 24 33 34 37 19 31 39 40 41 43 51 53 55 64 65 70 79 42 43 19 7 51 19 7 51 19 7 53 80 85 19 55 17 42 64 69 17 21 40 42 43 69 70 17 21 34 37 42 69 82 84 17 24 68 17 7 39 53 17 7 39 17 85 17 19 19 19 19 19 19 50 TPs 31 20 31 20 31 20 7 31 42 45 51 94 20 7 31 42 45 51 94 20 31 96 21 D 20 18 18 PP5V_S0_HDD_FLT PP5V_S3_IR_R NC_PCI_C_BE_L NC_PCI_CLK0 NC_PCI_CLK1 NC_PCI_DEVSEL_L NC_PCI_FRAME_L NC_PCI_GNT0_L NC_PCI_GNT1_L NC_PCI_INTW_L NC_PCI_INTX_L NC_PCI_INTZ_L NC_PCI_IRDY_L NC_PCI_PERR_L NC_PCI_RESET1_L NC_PCI_SERR_L NC_PCI_STOP_L NC_PCI_TRDY_L NC_PCIE_CLK100M_PE4N NC_PCIE_CLK100M_PE4P NC_PCIE_CLK100M_PE5N NC_PCIE_CLK100M_PE5P NC_PCIE_CLK100M_PE6P NC_PCIE_PE4_D2RN NC_PCIE_PE4_R2D_CN NC_PE4_PRSNT_L NC_PSOC_P1_3 NC_PSOC_SDA NC_SATA_C_D2RP NC_SATA_C_R2D_CN NC_SATA_C_R2D_CP NC_SATA_D_D2RN NC_SATA_D_D2RP NC_SB_A20GATE NC_PCI_CLK0 NC_PCI_CLK1 NC_PCI_DEVSEL_L NC_PCI_FRAME_L NC_PCI_GNT0_L NC_PCI_GNT1_L NC_PCI_INTW_L NC_PCI_INTX_L NC_PCI_INTZ_L NC_PCI_IRDY_L NC_PCI_PERR_L NC_PCI_RESET1_L NC_PCI_SERR_L NC_PCI_STOP_L NC_PCI_TRDY_L NC_PCIE_CLK100M_PE4N NC_PCIE_CLK100M_PE4P NC_PCIE_CLK100M_PE5N NC_PCIE_CLK100M_PE5P NC_PCIE_CLK100M_PE6P NC_PCIE_PE4_D2RN NC_PCIE_PE4_R2D_CN NC_PE4_PRSNT_L NC_PSOC_P1_3 NC_PSOC_SDA NC_SATA_C_D2RP NC_SATA_C_R2D_CN NC_SATA_C_R2D_CP NC_SATA_D_D2RN NC_SATA_D_D2RP NC_SB_A20GATE 39 TPs TRUE TRUE TRUE FSB_A_L FSB_ADS_L FSB_ADSTB_L 10 14 88 TRUE FSB_D_L 10 14 88 TRUE FSB_DINV_L 10 14 88 TRUE TRUE TRUE TRUE TRUE FSB_DSTB_L_N FSB_DSTB_L_P FSB_HIT_L FSB_HITM_L FSB_LOCK_L TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE USB_BT_N USB_BT_P USB_CAMERA_N USB_CAMERA_P SATA_ODD_D2R_UF_N SATA_ODD_D2R_UF_P DP_ML_C_P TRUE GND 10 14 88 10 14 88 16 16 16 16 16 16 16 16 16 16 16 21 50 19 C 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 17 17 17 17 17 17 17 17 50 B 50 20 20 20 20 20 21 Note NO_TEST properties are also on page9,26,43,50 39 90 39 90 39 90 10 14 88 10 14 88 10 14 88 10 14 88 10 14 88 39 90 Functional / ICT Test 39 41 39 TPs 20 31 91 SYNC_MASTER=N/A SYNC_DATE=N/A 20 31 91 NOTICE OF PROPRIETARY PROPERTY 20 31 91 20 31 91 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING 39 96 39 96 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE 82 95 II NOT TO REPRODUCE OR COPY IT TRUE TRUE KBDLED_ANODE SMC_KDBLED_PRESENT_L TRUE GND 51 TPs III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART 51 SIZE 58 59 96 58 59 96 15 39 FUNC_TEST 58 59 96 TP_PCI_C_BE_L 16 NO_TEST 10 TPs SATA_HDD_R2D_P SATA_HDD_R2D_N SATA_HDD_D2R_C_P SATA_HDD_D2R_C_N IR_RX_OUT SYS_LED_ANODE_R 58 59 96 NC_MEM_B_CKE NC_MEM_B_CLK3P NC_MEM_B_CLK4N NC_MEM_B_CLK4P NC_MEM_B_CLK5N NC_MEM_B_ODT NC_MLB_RAM_SIZE NC_P7_7 NC_PCI_AD 19 31 96 KBD Backlight Conn 58 59 96 DRAWING NUMBER D TPs 7 20 31 96 59 60 58 59 96 NC_MEM_B_CKE NC_MEM_B_CLK3P NC_MEM_B_CLK4N NC_MEM_B_CLK4P NC_MEM_B_CLK5N NC_MEM_B_ODT NC_MLB_RAM_SIZE NC_P7_7 TP_PCI_AD 31 96 59 60 59 60 NC_MEM_A_CKE NC_MEM_A_CLK2N NC_MEM_A_CLK3N NC_MEM_A_CLK3P NC_MEM_A_CLK4P NC_MEM_A_CS_L NC_MEM_A_ODT APPLE INC REV 051-7892 SCALE SHT NONE 55 28 29 65 70 50 GND 32 NC_LPC_DRQ0_L 22 24 46 66 17 31 31 NC_LPC_DRQ0_L TP_MEM_A_CKE NC_MEM_A_CLK2N NC_MEM_A_CLK3N NC_MEM_A_CLK3P NC_MEM_A_CLK4P NC_MEM_A_CS_L TP_MEM_A_ODT 42 45 61 62 94 50 32 93 FUNC_TEST BI_MIC_LO BI_MIC_SHIELD BI_MIC_HI SPKRCONN_L_OUT_P SPKRCONN_L_OUT_N SPKRCONN_R_OUT_P SPKRCONN_R_OUT_N SPKRCONN_S_OUT_P SPKRCONN_S_OUT_N 55 42 45 61 62 94 32 93 Speaker Connectors TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NC_AUD_LO1_N_L NC_AUD_LO1_P_L NC_USB_10N NC_USB_10P NC_ENET_INTR_L NC_ENET_PWRDWN_L TPs 42 45 61 62 94 Batt Signal Connector GND TRUE TRUE 32 93 61 62 21 22 26 40 42 43 44 45 46 50 61 62 64 69 50 FUNC_TEST PCIE_MINI_D2R_P TRUE PCIE_MINI_D2R_N TRUE PCIE_MINI_R2D_P TRUE PCIE_MINI_R2D_N TRUE PCIE_CLK100M_MINI_CONN_P TRUE PCIE_CLK100M_MINI_CONN_N TRUE MINI_CLKREQ_Q_L TRUE PCIE_WAKE_L TRUE MINI_RESET_CONN_L TRUE PP5V_WLAN TRUE PP3V3_S3_BT_F TRUE PP5V_S3_BTCAMERA_F TRUE SMBUS_SMC_A_S3_SDA TRUE SMBUS_SMC_A_S3_SCL TRUE USB_CAMERA_CONN_P TRUE USB_CAMERA_CONN_N TRUE CONN_USB2_BT_P TRUE CONN_USB2_BT_N TRUE TRUE PPVBAT_G3H_CONN SMBUS_SMC_BSA_SCL SMBUS_SMC_BSA_SDA SYS_DETECT_L GND TRUE TRUE TRUE TRUE TRUE FUNC_TEST SD_D SD_CMD SD_CLK SD_CD_L SD_WP 18 NC_AUD_LO1_N_L NC_AUD_LO1_P_L NC_USB_10N NC_USB_10P NC_ENET_INTR_L NC_ENET_PWRDWN_L TPs SATA HDD Connector FUNC_TEST TRUE TRUE TRUE TRUE TRUE 20 39 90 PP3V3_S3 PP3V42_G3H WS_KBD1 WS_KBD2 WS_KBD3 WS_KBD4 WS_KBD5 WS_KBD6 WS_KBD7 WS_KBD8 WS_KBD9 WS_KBD10 WS_KBD11 WS_KBD12 WS_KBD13 WS_KBD14 WS_KBD15_CAP WS_KBD16_NUM WS_KBD17 WS_KBD18 WS_KBD19 WS_KBD20 WS_KBD21 WS_KBD22 WS_KBD23 WS_KBD_ONOFF_L WS_LEFT_SHIFT_KBD WS_LEFT_OPTION_KBD WS_CONTROL_KBD KBDLED_ANODE TRUE GND TPs 39 90 Airport/BT/Camera Conn PP3V3_S3_LDO PP18V5_S3 Z2_CS_L Z2_DEBUG3 Z2_MOSI Z2_MISO Z2_SCLK Z2_BOOST_EN Z2_HOST_INTN Z2_CLKIN Z2_KEY_ACT_L Z2_RESET PSOC_MISO PSOC_MOSI PSOC_SCLK SMBUS_SMC_A_S3_SDA SMBUS_SMC_A_S3_SCL PSOC_F_CS_L PICKB_L 61 39 42 FUNC_TEST 80 81 95 GND NO_TEST PP18V5_DCIN_FUSE ADAPTER_SENSE TRUE TRUE FUNC_TEST SD Card Connector A SMC_ODD_DETECT SATA_ODD_R2D_P SATA_ODD_R2D_N SATA_ODD_D2R_C_N SATA_ODD_D2R_C_P TPs Keyboard Connector 80 81 FUNC_TEST B TRUE TRUE TRUE TRUE TRUE 39 53 53 80 85 IPD Flex Connector TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE FUNC_TEST PP5V_SW_ODD TRUE FUNC_TEST PP3V3_S0 PP3V3_SW_LCD PPVOUT_S0_LCDBKLT ICT Test Points DC Power Connector 49 LVDS Connector TRUE TRUE TRUE Functional Test Points FUNC_TEST TRUE A.0.0 OF 97 A 86 66 65 64 37 62 61 46 83 79 67 PPBUS_G3H "G3Hot" (Always-Present) Rails PPBUS_G3H PP3V3_S5 MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.6V MAKE_BASE=TRUE PPBUS_G3H 37 46 61 62 64 65 66 67 79 83 86 37 46 61 62 64 65 66 67 79 83 86 37 46 61 62 64 65 66 67 79 83 86 PPBUS_G3H PPBUS_G3H PPBUS_G3H PPBUS_G3H PPBUS_G3H PPBUS_G3H PPBUS_CPU_IMVP_ISNS 37 46 61 62 64 65 66 67 79 83 86 37 46 61 62 64 65 66 67 79 83 86 37 46 61 62 64 65 66 67 79 83 86 37 46 61 62 64 65 66 67 79 83 86 37 46 61 62 64 65 66 67 79 83 86 37 46 61 62 64 65 66 67 79 83 86 PPBUS_CPU_IMVP_ISNS MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.6V MAKE_BASE=TRUE PPBUS_CPU_IMVP_ISNS 46 63 PPDCIN_G3H PPDCIN_G3H MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=16.5V MAKE_BASE=TRUE PPDCIN_G3H 61 44 26 22 21 42 46 64 69 50 43 40 45 62 MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.42V MAKE_BASE=TRUE PP3V42_G3H PP3V42_G3H C PP1V8R1V5_S0_FET 18 20 22 24 26 30 34 37 38 44 54 64 68 69 70 82 87 96 130 mA 18 20 22 24 26 30 34 37 38 44 54 64 68 69 70 82 87 96 500 mA 4771 mA 21 27 31 32 45 50 52 70 PP1V0_FW 21 27 31 32 24 17 45 50 52 70 21 27 31 32 45 50 52 70 28 29 30 65 70 PP3V3_FW_FWPHY 28 38 37 36 29 30 65 70 PP3V3_FW_FWPHY PP3V3_FW_FWPHY PP3V3_FW_FWPHY 21 22 26 40 42 43 44 45 46 50 61 62 64 69 21 22 26 40 42 43 44 45 46 50 61 62 64 69 31 39 40 41 43 51 53 55 64 65 70 79 31 39 40 41 43 51 53 55 64 65 70 79 31 39 40 41 43 51 53 55 64 65 70 79 64 65 64 65 31 70 31 70 39 40 41 43 51 53 55 79 39 40 41 43 51 53 55 79 31 39 40 41 43 51 53 55 64 65 70 79 64 65 64 65 31 70 31 70 39 40 41 43 51 53 55 79 39 40 41 43 51 53 55 79 31 39 40 41 43 51 53 55 64 65 70 79 31 39 40 41 43 51 53 55 64 65 70 79 31 39 40 41 43 51 53 55 64 65 70 79 31 39 40 41 43 51 53 55 64 65 70 79 31 39 40 41 43 51 53 55 64 65 70 79 31 39 40 41 43 51 53 55 64 65 70 79 31 39 40 41 43 51 53 55 64 65 70 79 31 39 40 41 43 51 53 55 64 65 70 79 31 39 40 41 43 51 53 55 64 65 70 79 39 44 49 51 63 66 67 70 83 85 39 44 49 51 63 66 67 70 83 85 39 44 49 51 63 66 67 70 83 85 39 44 49 51 63 66 67 70 83 85 39 44 49 51 63 66 67 70 83 85 39 44 49 51 63 66 67 70 83 85 39 44 49 51 63 66 67 70 83 85 39 44 49 51 63 66 67 70 83 85 39 44 49 51 63 66 67 70 83 85 39 44 49 51 63 66 67 70 83 85 39 44 49 51 63 66 67 70 83 85 39 44 49 51 63 66 67 70 83 85 Chipset "VCore" Rails PPVCORE_S0_CPU MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=1.25V MAKE_BASE=TRUE PPVCORE_S0_CPU 36 37 38 11 12 16 24 28 29 39 68 69 70 11 12 16 24 28 29 39 68 69 70 11 12 16 24 28 29 39 68 69 70 PP1V05_S0_MCP_PLL_UF PP1V05_S0_MCP_PLL_UF 11 12 16 24 28 29 39 68 69 70 11 12 16 24 28 29 39 68 69 70 81 79 77 76 70 69 "GPU" Rails PP3V3_S0GPU PP3V3_S0GPU 69 70 76 77 79 81 MIN_LINE_WIDTH=0.30MM MIN_NECK_WIDTH=0.20MM VOLTAGE=3.3V MAKE_BASE=TRUE 10 11 12 13 14 17 18 20 22 24 25 63 67 PP3V3_S0GPU PP3V3_S0GPU 10 11 12 13 14 17 18 20 22 24 25 63 67 PP1V05_S0_MCP_PEX_AVDD PP1V05_S0_MCP_PEX_AVDD 24 68 MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.2mm VOLTAGE=1.05V MAKE_BASE=TRUE 11 12 16 24 28 29 39 68 69 70 17 24 69 70 76 77 79 81 69 70 76 77 79 81 PP3V3_S0GPU 69 70 76 77 79 81 17 24 21 27 31 32 45 50 52 70 PPCPUVTT_S0 21 27 31 32 45 50 52 70 PPCPUVTT_S0 PP3V3_S0GPU PP3V3_S0GPU 10 11 12 13 14 17 18 20 22 24 25 63 67 21 27 31 32 45 50 52 70 PP1V05_S0_MCP_SATA_AVDD PP3V3_S0 PP1V05_S0_MCP_SATA_AVDD 69 70 76 77 79 81 69 70 76 77 79 81 C 20 24 59 60 63 68 69 70 77 80 81 82 13 18 19 21 22 24 25 28 29 37 39 43 45 47 48 49 51 55 84 85 96 18 17 14 13 12 11 10 67 63 25 24 22 20 PPCPUVTT_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 59 60 29 37 84 85 82 84 51 55 85 96 59 60 25 28 19 21 63 13 39 96 85 59 13 29 63 29 22 13 68 69 70 77 80 81 82 18 19 21 22 24 25 28 43 45 47 48 49 51 55 59 60 29 37 84 85 77 80 43 45 29 37 68 69 59 60 29 37 63 13 39 96 81 47 13 39 70 63 39 13 68 69 70 77 80 81 82 18 19 21 22 24 25 28 43 45 47 48 49 51 55 PP3V3_S0 59 60 29 37 84 85 59 60 29 37 84 85 63 13 39 96 63 13 39 96 70 77 47 48 21 22 68 34 59 60 29 37 84 85 59 60 29 37 59 60 29 37 84 85 80 49 24 13 24 63 13 39 96 63 39 13 63 13 39 96 96 60 18 37 68 37 24 18 63 19 39 69 39 68 21 43 70 43 PPVCORE_S0_MCP_REG 69 22 45 77 45 70 24 47 80 47 6600 MA 77 25 48 81 48 51 82 PP1V1_S0GPU_REG PPCPUVTT_S0 80 28 49 81 49 55 84 4500 mA PPCPUVTT_S0 1182 mA PPCPUVTT_S0 1034 mA 241 mA max load 84 85 96 68 69 70 77 80 81 82 43 45 47 48 49 51 55 18 19 21 22 24 25 28 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 10 11 12 13 14 17 18 20 22 24 25 63 67 22 24 22 24 10 11 12 13 14 17 18 20 25 63 67 10 11 12 13 14 17 18 20 25 63 67 10 11 12 13 14 17 18 20 22 24 25 63 67 78 70 81 51 25 18 22 68 18 43 84 68 43 18 68 18 43 82 55 28 19 69 19 45 85 69 45 19 69 19 45 59 60 29 37 84 85 59 60 29 37 84 85 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 63 13 39 96 63 13 39 96 PP1V2R1V05_S5 70 21 47 96 70 47 21 70 21 47 PP1V2R1V05_S5 71 73 76 78 83 71 73 76 78 83 71 73 76 78 83 71 73 76 78 83 71 73 76 78 83 PP1V8_GPUIFPX 70 78 70 78 77 48 22 77 22 48 80 49 24 80 24 49 81 51 25 81 25 51 82 55 28 82 28 55 22 24 34 68 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V MAKE_BASE=TRUE 77 80 81 82 22 24 25 28 48 49 51 55 105 mA/241 mA 139 mA/ mA 75 74 73 72 47 PP1V2R1V05_S5 PP1V2R1V05_S5 PP1V8_S0GPU_ISNS PP1V8_S0GPU_ISNS PP1V8_S0GPU_ISNS PP1V8_S0GPU_ISNS PP1V8_S0GPU_ISNS 27 65 PP0V9R0V75_S0_DDRVTT MIN_LINE_WIDTH=2 mm MIN_NECK_WIDTH=0.17 mm VOLTAGE=0.9V MAKE_BASE=TRUE PP0V9R0V75_S0_DDRVTT PP0V9R0V75_S0_DDRVTT PP0V9R0V75_S0_DDRVTT 79 72 46 PPVCORE_GPU 47 72 73 74 75 47 72 73 74 75 47 72 73 74 75 PPVCORE_GPU 46 72 79 PPVCORE_GPU 46 72 79 PP1V8_S0GPU_ISNS_R 47 83 28 29 65 70 28 29 65 70 28 29 65 70 83 47 PP1V8_S0GPU_ISNS_R MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.8V MAKE_BASE=TRUE ENET Rails PP1V8_S0GPU_ISNS_R PP1V2R1V05_ENET 47 83 18 24 33 34 37 MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V MAKE_BASE=TRUE 80 81 82 84 85 96 37 39 43 45 47 48 49 51 55 13 18 19 21 22 24 25 28 29 59 60 63 68 69 70 77 84 685 96 59 760 63 68 69 70 77 80 81 82 29 37 39 43 45 47 48 49 51 55 13 18 19 21 22 24 25 28 59 60 63 68 69 70 77 80 81 82 13 18 19 21 22 24 25 28 29 37 39 43 45 47 48 49 51 55 84 85 96 47 72 73 74 75 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.0V MAKE_BASE=TRUE 28 29 65 70 OR 0.75V 68 69 70 77 80 81 82 18 19 21 22 24 25 28 43 45 47 48 49 51 55 47 72 73 74 75 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.8V MAKE_BASE=TRUE 22 24 34 68 MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0.75V MAKE_BASE=TRUE 68 69 70 77 80 81 82 18 19 21 22 24 25 28 43 45 47 48 49 51 55 B PP1V8_S0GPU_ISNS 22 24 34 68 PPVTTDDR_S3 PP1V2R1V05_ENET PP1V2R1V05_ENET 18 24 33 34 37 PP1V2R1V05_ENET PP1V2R1V05_ENET PP1V2R1V05_ENET PP1V2R1V05_ENET Power Aliases 18 24 33 34 37 SYNC_MASTER=(MASTER) 18 24 33 34 37 SYNC_DATE=(MASTER) NOTICE OF PROPRIETARY PROPERTY 18 24 33 34 37 18 24 33 34 37 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING 11 12 46 63 PP3V3_ENET_PHY 22 24 46 66 87 84 PP1V2_S0 PP1V2_S0 84 87 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.2V MAKE_BASE=TRUE 22 24 46 66 PP1V2_S0 PP3V3_ENET_PHY 18 24 33 34 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V MAKE_BASE=TRUE I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART PP3V3_ENET_PHY 18 24 33 34 PP3V3_ENET_PHY 18 24 33 34 SIZE DRAWING NUMBER D 84 87 APPLE INC REV 051-7892 SCALE SHT NONE 71 73 76 78 83 PP1V8_GPUIFPX 85 96 47 48 49 51 55 59 13 18 19 21 22 24 25 28 29 37 39 43 45 60 63 68 69 70 77 80 81 82 84 11 12 46 63 71 73 76 78 83 84 85 96 59 60 63 68 69 29 37 39 43 45 PP0V9R0V75_S0_DDRVTT PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 71 73 76 78 83 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.15 mm VOLTAGE=1.8V MAKE_BASE=TRUE 68 69 70 77 80 81 82 18 19 21 22 24 25 28 43 45 47 48 49 51 55 PPVTTDDR_S3 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP1V8_GPUIFPX 68 69 70 77 80 81 82 18 19 21 22 24 25 28 43 45 47 48 49 51 55 80 81 82 84 85 96 47 48 49 51 55 59 60 63 68 69 13 18 19 21 22 24 25 28 29 37 39 43 45 70 77 65 27 59 60 63 68 69 70 77 80 81 82 13 18 19 21 22 24 25 28 29 37 39 43 45 47 48 49 51 55 84 85 96 68 69 70 77 80 81 84 39 43 45 47 48 49 51 55 59 60 13 18 19 21 22 24 25 28 29 85 96 85 96 80 81 82 84 37 37 39 43 45 47 48 49 51 55 63 13 18 19 21 22 24 25 28 29 82 59 60 63 68 69 70 77 84 685 96 59 760 63 68 69 70 77 80 81 82 29 37 39 43 45 47 48 49 51 55 13 18 19 21 22 24 25 28 59 60 63 68 69 70 77 80 81 82 13 18 19 21 22 24 25 28 29 37 39 43 45 47 48 49 51 55 84 85 96 PP3V3_S0 PP1V1_S0GPU_REG PP1V1_S0GPU_REG PP1V1_S0GPU_REG PP1V1_S0GPU_REG PP1V1_S0GPU_REG PP1V1_S0GPU_REG PP1V1_S0GPU_REG PP1V1_S0GPU_REG 10 11 12 13 14 17 18 20 22 24 25 63 67 PPCPUVTT_S0 PPCPUVTT_S0 PPCPUVTT_S0 PPCPUVTT_S0 71 73 76 78 83 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.1V MAKE_BASE=TRUE 10 11 12 13 14 17 18 20 22 24 25 63 67 59 60 63 68 69 70 77 80 81 82 13 18 19 21 22 24 25 28 29 37 39 43 45 47 48 49 51 55 84 85 96 PP3V3_S0 PP3V3_S0 PP1V1_S0GPU_REG 83 78 76 73 71 10 11 12 13 14 17 18 20 22 24 25 63 67 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V MAKE_BASE=TRUE 82 84 85 96 48 49 51 55 59 60 63 18 19 21 22 24 25 28 34 33 24 18 PPVCORE_S0_MCP_REG MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V MAKE_BASE=TRUE 8 36 37 38 11 12 16 24 28 29 39 68 69 70 PPCPUVTT_S0 MAKE_BASE=TRUE 36 37 38 MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.2mm VOLTAGE=3.3V MAKE_BASE=TRUE 11 12 16 24 28 29 39 68 69 70 PPCPUVTT_S0 PP1V05_S0_MCP_PEX_AVDD 36 37 28 29 30 65 70 PP1V8R1V5_S0_FET PP1V8R1V5_S0_FET PP1V8R1V5_S0_FET PP1V8R1V5_S0_FET PP1V8R1V5_S0_FET PP1V8R1V5_S0_FET PPCPUVTT_S0 D PP1V0_FW 28 29 30 65 70 PP1V8R1V5_S0_FET 21 27 31 32 45 50 52 70 36 37 MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.2mm VOLTAGE=1.05V MAKE_BASE=TRUE 21 27 31 32 45 50 52 70 50 52 70 21 27 31 32 18 17 14 13 12 11 10 45 67 63 25 24 22 20 37 38 PP1V0_FW 28 29 30 65 70 21 27 31 32 45 50 52 70 MIN_LINE_WIDTH=0.30MM MIN_NECK_WIDTH=0.10MM VOLTAGE=3.3V MAKE_BASE=TRUE 21 22 26 40 42 43 44 45 46 50 61 62 64 69 21 22 26 40 42 43 44 45 46 50 61 62 64 69 MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=5V MAKE_BASE=TRUE PPVCORE_S0_MCP_REG 28 29 30 65 70 37 36 8 37 38 MAKE_BASE=TRUE 21 22 26 40 42 43 44 45 46 50 61 62 64 69 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 22 66 46 24 PPVP_FW PPVP_FW 18 25 55 69 70 84 87 MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.17mm VOLTAGE=1.5V MAKE_BASE=TRUE 18 20 22 24 26 30 34 37 38 44 54 64 68 69 70 82 87 96 37 38 MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=12.6V MAKE_BASE=TRUE 18 25 55 69 70 84 87 PP1V8R1V5_S0_FET 18 20 22 24 26 30 34 37 38 44 54 64 68 69 70 82 87 96 18 20 22 24 26 30 34 37 38 44 54 64 68 69 70 82 87 96 24 20 PP3V3_S0 PP5V_S0 PPVCORE_S0_CPU 18 20 22 24 26 30 34 37 38 44 54 64 68 69 70 82 87 96 82 87 96 30 34 37 38 44 54 64 68 69 70 18 20 22 24 68 39 29 28 24 16 12 11 26 70 69 PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3 21 22 26 40 42 43 44 45 46 50 61 62 64 69 PP5V_S3 PP5V_S3 PP5V_S3 PP5V_S3 PP5V_S3 PP5V_S3 11 63 46 12 18 20 22 24 26 30 34 37 38 44 54 64 68 69 70 82 87 96 18 20 22 24 26 30 34 37 38 44 54 64 68 69 70 82 87 96 PPVP_FW PPVP_FW 18 25 55 69 70 84 87 PP1V8R1V5_S3 PP1V8R1V5_S3 PP1V8R1V5_S3 PP1V8R1V5_S3 PP1V8R1V5_S3 18 20 22 24 26 30 34 37 38 44 54 64 68 69 70 82 87 96 PP3V3_S3 18 25 55 69 70 84 87 38 37 PP1V8R1V5_S3 18 20 22 24 26 30 34 37 38 44 54 64 68 69 70 82 87 96 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP1V8_S0 PP1V8_S0 PP1V8_S0 PP1V8_S0 MIN_LINE_WIDTH=0.8 mm MIN_NECK_WIDTH=0.1 mm VOLTAGE=1.5V MAKE_BASE=TRUE 18 20 22 24 26 30 34 37 38 44 54 64 68 69 70 82 87 96 21 22 26 40 42 43 44 45 46 50 61 62 64 69 21 22 26 40 42 43 44 45 46 50 61 62 64 69 PP5V_S3 A PP1V8R1V5_S3 PP3V3_S3 PP3V3_S3 21 22 26 40 42 43 44 45 46 50 61 62 64 69 PP5V_S3 PP5V_S0 96 18 20 22 24 26 30 34 37 38 44 54 64 68 69 70 82 87 82 887 96 30 34 37 38 44 54 64 68 69 70 18 20 22 24 70 65 30 29 28 26 18 20 22 24 26 30 34 37 38 44 54 64 68 69 70 82 87 96 PP3V3_S5 "FW" (FireWire) Rails 21 22 26 40 42 43 44 45 46 50 61 62 64 69 PP5V_S3 PP5V_S3 PP5V_S3 PP5V_S3 PP5V_S3 PP5V_S3 PP5V_S3 PP5V_S3 PP5V_S3 85 83 70 51 49 44 39 67 66 63 500 mA max supply 18 25 55 69 70 84 87 MIN_LINE_WIDTH=0.10MM MIN_NECK_WIDTH=0.10MM VOLTAGE=1.8V MAKE_BASE=TRUE 18 20 22 24 26 30 34 37 38 44 54 64 68 69 70 82 87 96 PP3V3_S3 21 22 26 40 42 43 44 45 46 50 61 62 64 69 21 22 26 40 42 43 44 45 46 50 61 62 64 69 MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.17MM VOLTAGE=5.0V MAKE_BASE=TRUE B 61 62 21 22 26 40 42 43 44 45 46 50 61 62 64 69 5V Rails PP5V_S3 1.8V/DDR 1.5V Rails PP1V8_S0 190 mA PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 MIN_LINE_WIDTH=0.40MM MIN_NECK_WIDTH=0.20MM VOLTAGE=3.3V MAKE_BASE=TRUE 21 22 26 40 42 43 44 45 46 50 61 62 64 69 PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H 79 70 53 51 43 31 41 40 39 65 64 55 PP3V3_S3 61 62 PP3V42_G3H PP3V42_G3H PP1V8_S0 69 70 82 87 96 18 20 22 24 26 30 34 37 38 44 54 64 68 46 63 70 52 50 45 32 31 27 21 62 61 3.3V-2.5V Rails PP3V3_S5 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V MAKE_BASE=TRUE 37 46 61 62 64 65 66 67 79 83 86 PPBUS_G3H PPBUS_G3H D 37 46 61 62 64 65 66 67 79 83 86 37 46 61 62 64 65 66 67 79 83 86 PPBUS_G3H PPBUS_G3H 63 46 A.0.0 OF 97 A CPU signals Thermal Module Holes ZT0981 63 STDOFF-4.5OD.98H-1.1-3.48-TH STDOFF-4.5OD.98H-1.1-3.48-TH 88 11 2.0DIA-TALL-EMI-MLB-M97-M98 STDOFF-4.5OD.98H-1.1-3.48-TH ZT0982 ZT0985 SH0900 SM 88 10 2.0DIA-TALL-EMI-MLB-M97-M98 70 65 26 STDOFF-4.5OD.98H-1.1-3.48-TH 1 SM Left CPU TM Hole ZT0930 SH0916 STDOFF-4.5OD.98H-1.1-3.48-TH 2.0DIA-TALL-EMI-MLB-M97-M98 SM 10 90 71 PEG_R2D_C_N 10 GPU_FB_B_VREF_DIV MAKE_BASE=TRUE GPU_FB_B_VREF_DIV LCD_BKLT_EN 86 84 R09701 R09901 5% 1/16W MF-LF 402 5% 1/16W MF-LF 402 1% 1/16W MF-LF 402 200 R0960 62 5% 1/16W MF-LF 402 3R2P5 OUT 88 14 10 OUT 29 DP_IG_ML_P DP_IG_ML_N DP_IG_ML_P 150 DP_IG_ML_N DP_IG_DDC_CLK TP_MEM_B_A NC_USB_EXTCP 90 18 NC_LVDS_IG_B_CLKN STDOFF-4.0OD3.0H-TH 18 MAKE_BASE=TRUE NO_TEST=TRUE NC_LVDS_IG_BKL_PWM NO_TEST=TRUE MAKE_BASE=TRUE 150 1% 1/16W MF-LF 402 DP_IG_DDC_DATA DP_IG_HPD MAKE_BASE=TRUE 29 NC_USB_EXTCP 20 91 NC_USB_EXTCN 20 91 TP_CPU_PECI_MCP 14 MAKE_BASE=TRUE 37 19 FW_PLUG_DET_L 37 36 FW643_WAKE_L PM_ALL_GPU_PGOOD EG_RESET_L 84 19 JTAG_GMUX_TDI 84 19 JTAG_GMUX_TMS 84 17 JTAG_GMUX_TDO GND_CHASSIS_AUDIO_JACK 17 90 90 17 TP_PCIE_EXCARD_D2R_N TP_PCIE_EXCARD_D2R_N 90 17 TP_PCIE_EXCARD_R2D_C_P TP_PCIE_EXCARD_R2D_C_P 17 90 17 90 MAKE_BASE=TRUE 90 17 TP_PCIE_EXCARD_R2D_C_N TP_PCIE_EXCARD_R2D_C_N 17 TP_PCIE_EXCARD_PRSNT_L TP_PCIE_EXCARD_PRSNT_L 17 90 MAKE_BASE=TRUE 18 77 81 17 MAKE_BASE=TRUE 18 81 TP_EXCARD_CLKREQ_L TP_EXCARD_CLKREQ_L 90 17 TP_PCIE_CLK100M_EXCARD_P TP_PCIE_CLK100M_EXCARD_P 90 17 TP_PCIE_CLK100M_EXCARD_N TP_PCIE_CLK100M_EXCARD_N 17 9 69 83 84 17 MAKE_BASE=TRUE 17 90 MAKE_BASE=TRUE 84 17 90 MAKE_BASE=TRUE 71 84 JTAG_GMUX_TDI 19 84 JTAG_GMUX_TMS 19 84 MAKE_BASE=TRUE MAKE_BASE=TRUE AUDIO ALIASES SM JTAG_GMUX_TDO 17 84 55 53 51 43 41 40 39 31 79 70 65 64 MAKE_BASE=TRUE LVDS_IG_BKL_ON LVDS_IG_BKL_ON PP5V_S3 PP5V_S3_AUDIO_AMP ETHERNET ALIASES LVDS_IG_PANEL_PWR LVDS_IG_PANEL_PWR 58 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=5V XW0901 18 84 MAKE_BASE=TRUE 84 18 C TP_PCIE_EXCARD_D2R_P TP_PCIE_EXCARD_D2R_P MAKE_BASE=TRUE MAKE_BASE=TRUE EG_RESET_L 36 37 18 77 81 TP_LVDS_MUX_SEL_EG MAKE_BASE=TRUE 19 37 FW643_WAKE_L MAKE_BASE=TRUE PM_ALL_GPU_PGOOD TP_LVDS_MUX_SEL_EG FW_PLUG_DET_L MAKE_BASE=TRUE MAKE_BASE=TRUE R0980 18 DP_IG_HPD 84 71 9 18 84 MAKE_BASE=TRUE 34 21 34 21 PM_SLP_RMGT_L PM_SLP_RMGT_L 21 34 MAKE_BASE=TRUE TP_PP3V3_ENET_PHY_VDDREG TP_PP3V3_ENET_PHY_VDDREG 33 MAKE_BASE=TRUE NC_LVDS_IG_B_CLKP 18 90 NC_LVDS_IG_B_CLKN 18 90 MCP79 PCIe PRSNT# Straps These need work NC_LVDS_IG_BKL_PWM NC_RTL8211_REGOUT NC_RTL8211_REGOUT MAKE_BASE=TRUE 33 NO_TEST=TRUE GND Add other PRSNT# straps if needed 18 NO STUFF 90 18 ZT0935 NC_LVDS_IG_A_DATAP MAKE_BASE=TRUE STDOFF-4.0OD3.0H-TH 90 18 90 18 90 18 NO_TEST=TRUE NC_LVDS_IG_A_DATAN MAKE_BASE=TRUE NO_TEST=TRUE NC_LVDS_IG_B_DATAN NO_TEST=TRUE MAKE_BASE=TRUE 18 90 NC_LVDS_IG_A_DATAN 18 90 NC_LVDS_IG_B_DATAP 18 90 NC_LVDS_IG_B_DATAN 18 90 NO_TEST=TRUE NC_LVDS_IG_B_DATAP MAKE_BASE=TRUE NC_LVDS_IG_A_DATAP ZT0951 4.0OD1.85H-M1.6X0.35 R0925 Bosses ZT0952 GND PCIE_FW_PRSNT_L 1 5% 1/16W MF-LF 402 NO STUFF ZT0988 ZT0954 4.0OD1.85H-M1.6X0.35 18 MCP_MII_PD OUT GND 17 MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.09MM VOLTAGE=0V R0926 EG_CLKREQ_OUT_L IN 84 5% 1/16W MF-LF 402 MCP_MII_PD 18 MCP_MII_PD 18 MAKE_BASE=TRUE ZT0989 GND Digital Ground PEG_PRSNT_L MAKE_BASE=TRUE 1 17 37 R0927 4.0OD1.5H-M1.6X0.35 ZT0953 STDOFF-4.5OD.98H-1.1-3.48-TH OUT MAKE_BASE=TRUE 5% 1/16W MF-LF 402 4.0OD1.5H-M1.6X0.35 Signal Aliases SYNC_MASTER=(MASTER) STDOFF-4.5OD.98H-1.1-3.48-TH R0930 MCP_MII_PD 18 5% 1/16W MF-LF 402 ZT0991 STDOFF-4.5OD.98H-1.1-3.48-TH SYNC_DATE=(MASTER) NOTICE OF PROPRIETARY PROPERTY 47K THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC REV 051-7892 SCALE SHT NONE B PM_SLP_RMGT_L 59 A NO_TEST=TRUE TP_CPU_PECI_MCP 33 ZT0934 28 TP_MEM_B_A UNUSED EXPRESS CARD LANE =MCP_HDMI_TXD_N DP_IG_DDC_CLK DP_IG_DDC_DATA 84 NO STUFF NO_TEST=TRUE 42 TP_MEM_A_A NO_TEST=TRUE NC_USB_EXTCN MAKE_BASE=TRUE SM MAKE_BASE=TRUE SMC_MCP_SAFE_MODE TP_MEM_A_A SH0914 NC_LVDS_IG_B_CLKP MAKE_BASE=TRUE 90 17 18 MAKE_BASE=TRUE 1.4DIA-SHORT-EMI-MLB-M97-M98 SM 18 =MCP_HDMI_TXD_P MAKE_BASE=TRUE 84 83 69 SH0917 18 =MCP_HDMI_TXC_N 1.4DIA-SHORT-EMI-MLB-M97-M98 90 18 MAKE_BASE=TRUE MAKE_BASE=TRUE 81 18 84 18 B 18 84 R0903 MCP_SPKR MAKE_BASE=TRUE 81 77 18 =MCP_HDMI_TXC_P MAKE_BASE=TRUE 81 77 18 CPU_DPRSTP_L FSB_BREQ0_L FSB_CPURST_L CPU_INTR CPU_NMI GND GMUX_INT MAKE_BASE=TRUE MAKE_BASE=TRUE 84 86 MAKE_BASE=TRUE 90 81 R09501 ZT0990 28 LCD_BKLT_EN MAKE_BASE=TRUE 90 81 NO STUFF GMUX_INT 5% 1/16W MF-LF 402 GMUX ALIASES 90 81 NO STUFF D 1.4DIA-SHORT-EMI-MLB-M97-M98 SH0901 NO STUFF OUT 21 SH0913 27 75 1.4DIA-SHORT-EMI-MLB-M97-M98 220 88 14 10 MAKE_BASE=TRUE 14 SM 88 14 13 10 RTL8211_CLK125 SM NO STUFF OUT RTL8211_CLK125 27 75 PPCPUVTT_S0 88 14 10 MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE Exist in MRB but not Intel designs Here for CYA If found to be necessary, will move to page14.csa GND 20 91 91 20 Extra FSB Pull-ups OUT NC_USB_EXCARDN MAKE_BASE=TRUE NO_TEST=TRUE 91 20 90 81 88 63 14 10 17 20 91 NC_USB_EXCARDN MAKE_BASE=TRUE SH0911 3R2P5 =PEG_R2D_C_N MAKE_BASE=TRUE 20 32 96 91 20 402 SM ZT0960 17 20 32 96 USB_CARDREADER_N NC_USB_EXCARDP SM GND GND SL-3.1X2.7-6CIR-NSP =PEG_R2D_C_P USB_CARDREADER_P NC_USB_EXCARDP 3R2P5 17 14 13 12 11 10 67 63 25 24 22 20 18 USB_CARDREADER_N 91 20 5% 1/16W MF-LF SH0912 17 20 91 22 1.4DIA-SHORT-EMI-MLB-M97-M98 ZT0950 TH USB_CARDREADER_P 20 91 MAKE_BASE=TRUE R0931 27 74 20 91 NC_USB_MINIP NC_USB_MININ MAKE_BASE=TRUE 96 32 20 1.4DIA-SHORT-EMI-MLB-M97-M98 GPU_FB_A_VREF_DIV 20 91 NC_USB_EXTDN NO_TEST=TRUE MAKE_BASE=TRUE 1 27 74 ZT0940 C 17 MAKE_BASE=TRUE SM MAKE_BASE=TRUE 1% 1/16W MF-LF 402 PEG_R2D_C_P NC_USB_EXTDP NC_USB_MINIP MAKE_BASE=TRUE NC_USB_MININNO_TEST=TRUE 84 18 R0901 90 71 =PEG_D2R_N 1.4DIA-SHORT-EMI-MLB-M97-M98 GPU_FB_A_VREF_DIV GND PEG_D2R_N 33 1% 1/16W MF-LF 402 Frame Holes 90 71 NO_TEST=TRUE MAKE_BASE=TRUE 96 32 20 =PEG_D2R_P MAKE_BASE=TRUE SH0910 R0900 3R2P5 PEG_D2R_P SM ZT0915 26 65 70 91 20 90 71 SH0904 75 74 73 72 47 91 20 MEM_VTT_EN 2.0DIA-TALL-EMI-MLB-M97-M98 STDOFF-4.5OD.98H-1.1-3.48-TH MEM_VTT_EN NO_TEST=TRUE NC_USB_EXTDN 14 GPU signals SM TOP MCP LEFT TM Hole PP1V8_S0GPU_ISNS =MCP_BSEL MAKE_BASE=TRUE ZT0986 STDOFF-4.5OD.98H-1.1-3.48-TH ZT0987 91 20 CPU_BSEL NC_USB_EXTDP MAKE_BASE=TRUE 63 88 MAKE_BASE=TRUE STDOFF-4.5OD.98H-1.1-3.48-TH SH0903 2.0DIA-TALL-EMI-MLB-M97-M98 ZT0980 Right CPU TM Hole IMVP6_VID STDOFF-4.5OD.98H-1.1-3.48-TH D 63 91 20 CPU_VID MAKE_BASE=TRUE Top GPU Right TM Hole ZT0983 TP_IMVP6_CLKEN_L MAKE_BASE=TRUE SH0902 ZT0984 TP_IMVP6_CLKEN_L A.0.0 OF 97 A OMIT 88 14 BI 88 14 BI 88 14 BI 88 14 BI 88 14 BI 88 14 BI 88 14 BI 88 14 BI 88 14 BI 88 14 BI 88 14 BI 88 14 BI 88 14 BI 88 14 BI 88 14 BI 88 14 BI 88 14 C BI 88 14 BI 88 14 BI 88 14 BI 88 14 BI 88 14 BI 88 14 BI 88 14 BI 88 14 BI 88 14 BI 88 14 BI 88 14 BI 88 14 BI 88 14 BI 88 14 BI 88 14 BI 88 14 BI 88 14 BI 88 14 IN 88 14 OUT 88 14 IN 88 14 IN 88 14 IN 88 14 88 14 IN IN FSB_REQ_L FSB_REQ_L FSB_REQ_L FSB_REQ_L FSB_REQ_L K3 H2 K2 J3 L1 REQ0* REQ1* REQ2* REQ3* REQ4* FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_ADSTB_L Y2 U5 R3 W6 U4 Y5 U1 R4 T5 T3 W2 W5 Y4 U2 V4 W3 AA4 AB2 AA3 V1 CPU_A20M_L CPU_FERR_L CPU_IGNNE_L BR0* D5 C6 B4 A3 M4 N5 T2 V3 B2 F6 D2 D22 D3 FSB_DEFER_L FSB_DRDY_L FSB_DBSY_L BI 14 88 F1 FSB_BREQ0_L BI 14 88 CPU_IERR_L CPU_INIT_L IN BI 14 88 BI 14 88 BI 14 88 BI 14 88 PPCPUVTT_S0 IERR* INIT* D20 B3 LOCK* H4 FSB_LOCK_L RESET* RS0* RS1* RS2* TRDY* C1 F3 F4 G3 G2 FSB_CPURST_L FSB_RS_L FSB_RS_L FSB_RS_L FSB_TRDY_L HIT* HITM* G6 E4 FSB_HIT_L FSB_HITM_L BPM0* BPM1* BPM2* BPM3* PRDY* PREQ* TCK TDI TDO TMS TRST* DBR* AD4 AD3 AD1 AC4 AC2 AC1 AC5 AA6 AB3 AB5 AB6 C20 XDP_BPM_L XDP_BPM_L XDP_BPM_L XDP_BPM_L XDP_BPM_L XDP_BPM_L XDP_TCK XDP_TDI XDP_TDO XDP_TMS XDP_TRST_L XDP_DBRESET_L 88 14 88 BI 10 11 12 13 14 17 18 20 22 24 25 63 67 R1002 PLACE TESTPOINT ON FSB_IERR_L WITH A GND 0.1" AWAY 54.9 1% 1/16W MF-LF 402 D 14 88 14 88 IN 13 14 88 IN 14 88 IN 14 88 IN 14 88 IN 14 88 OMIT A17* A18* A19* A20* A21* A22* A23* A24* A25* A26* A27* A28* A29* A30* A31* A32* A33* A34* A35* ADSTB1* STPCLK* LINT0 LINT1 SMI* BI 14 88 BI 14 88 BI 13 88 BI 13 88 BI 13 88 BI 13 88 BI 13 88 PPCPUVTT_S0 10 11 12 13 14 17 18 20 22 24 25 63 67 88 14 BI 88 14 BI R10031 88 14 BI 88 14 BI 1% 1/16W MF-LF 402 88 14 BI 88 14 BI 88 14 BI 88 14 BI 54.9 BI 13 88 IN 10 13 88 88 14 BI IN 10 13 88 88 14 BI 10 88 88 14 BI IN 10 13 88 88 14 BI IN 10 13 88 88 14 BI 88 14 BI 88 14 BI 88 14 BI 88 14 BI 88 14 BI 88 14 BI 88 14 BI 88 14 BI 88 14 BI 88 14 BI 88 14 BI 88 14 BI OUT OUT 13 26 R1004 68 5% 1/16W MF-LF 402 THERMAL PROCHOT* THERMDA THERMDC A6 A20M* A5 FERR* C4 IGNNE* CPU_STPCLK_L CPU_INTR CPU_NMI CPU_SMI_L TP_CPU_RSVD0 TP_CPU_RSVD1 TP_CPU_RSVD2 TP_CPU_RSVD3 TP_CPU_RSVD4 TP_CPU_RSVD5 TP_CPU_RSVD6 TP_CPU_RSVD7 TP_CPU_RSVD8 DEFER* DRDY* DBSY* H5 F21 E1 BI THERMTRIP* RSVD0 RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 RSVD6 RSVD7 RSVD8 D21 A24 B25 CPU_PROCHOT_L CPU_THERMD_P CPU_THERMD_N C7 PM_THRMTRIP_L OUT OUT 48 96 OUT 48 96 OUT 14 43 88 H CLK BCLK0 BCLK1 A22 A21 FSB_CLK_CPU_P FSB_CLK_CPU_N 14 43 63 88 PM_THRMTRIP# SHOULD CONNECT TO ICH AND GMCH WITHOUT T (NO STUB) IN 14 88 88 14 BI IN 14 88 88 14 BI 88 14 BI 88 14 BI 88 14 BI 88 14 BI 88 14 BI 88 14 BI 88 14 BI 88 14 BI 88 14 BI 18 17 14 13 12 11 10 67 63 25 24 22 20 PPCPUVTT_S0 R1005 1K 1% 1/16W MF-LF 402 B R10061 R1020 XDP_TMS 88 13 10 XDP_TDI 88 10 54.9 1% 1/16W MF-LF 402 XDP_TDO 2.0K PPCPUVTT_S0 10 11 12 13 14 17 18 20 22 24 25 63 67 1% 1/16W MF-LF 402 1% 1/16W MF-LF 402 R1021 54.9 NOSTUFF C1000 0.1uF 10% 16V X5R 402 R1024 PLACE C1000 CLOSE TO CPU_TEST4 PIN MAKE SURE CPU_TEST4 IS REFERENCED TO GND 54.9 PLACEMENT_NOTE=Place R1024 near ITP connector (if present) 1% 1/16W MF-LF 402 BI 88 14 BI E22 F24 E26 G22 F23 G25 E25 E23 K24 G24 J24 J23 H22 F26 K22 H23 J26 H26 H25 D0* D1* D2* D3* D4* D5* D6* D7* D8* D9* D10* D11* D12* D13* D14* D15* DSTBN0* DSTBP0* DINV0* FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_DSTB_L_N FSB_DSTB_L_P FSB_DINV_L N22 K25 P26 R23 L23 M24 L22 M23 P25 P23 P22 T24 R24 L25 T25 N25 L26 M26 N24 D16* D17* D18* D19* D20* D21* D22* D23* D24* D25* D26* D27* D28* D29* D30* D31* DSTBN1* DSTBP1* DINV1* 88 OUT 88 OUT 88 OUT CPU_GTLREF CPU_TEST1 CPU_TEST2 TP_CPU_TEST3 CPU_TEST4 TP_CPU_TEST5 TP_CPU_TEST6 TP_CPU_TEST7 CPU_BSEL CPU_BSEL CPU_BSEL AD26 C23 D25 C24 AF26 AF1 A26 C3 B22 B23 C21 R1023 88 13 10 XDP_TRST_L 649 FCBGA OF D32* D33* D34* D35* D36* D37* D38* D39* D40* D41* D42* D43* D44* D45* D46* D47* DSTBN2* DSTBP2* DINV2* Y22 AB24 V24 V26 V23 T22 U25 U23 Y25 W22 Y23 W24 W25 AA23 AA24 AB25 Y26 AA26 U22 FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_DSTB_L_N FSB_DSTB_L_P FSB_DINV_L D48* D49* D50* D51* D52* D53* D54* D55* D56* D57* D58* D59* D60* D61* D62* D63* DSTBN3* DSTBP3* DINV3* AE24 AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21 AC22 AD23 AF22 AC23 AE25 AF24 AC20 FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_DSTB_L_N FSB_DSTB_L_P FSB_DINV_L BI 14 88 BI 14 88 BI 14 88 BI 14 88 BI 14 88 BI 14 88 BI 14 88 BI 14 88 BI 14 88 BI 14 88 BI 14 88 BI 14 88 BI 14 88 BI 14 88 BI 14 88 BI 14 88 BI 14 88 BI 14 88 BI 14 88 BI 14 88 BI 14 88 BI 14 88 BI 14 88 BI 14 88 BI 14 88 BI 14 88 BI 14 88 BI 14 88 BI 14 88 BI 14 88 BI 14 88 BI 14 88 BI 14 88 BI 14 88 BI 14 88 BI 14 88 BI 14 88 BI 14 88 C LAYOUT NOTE: COMP0,2 CONNECT WITH ZO=27.4OHM, MAKE TRACE LENGTH SHORTER THAN 0.5" COMP1,3 CONNECT WITH ZO=55OHM, MAKE TRACE LENGTH SHORTER THAN 0.5" R1016 GTLREF TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 TEST7 BSEL0 BSEL1 BSEL2 MISC COMP0 COMP1 COMP2 COMP3 R26 U26 AA1 Y1 DPRSTP* DPSLP* DPWR* PWRGOOD SLP* PSI* E5 B5 D24 D6 D7 AE6 88 88 88 88 54.9 1% 1/16W MF-LF 402 CPU_COMP CPU_COMP CPU_COMP CPU_COMP CPU_DPRSTP_L CPU_DPSLP_L FSB_DPWR_L CPU_PWRGD FSB_CPUSLP_L CPU_PSI_L 1% 1/16W MF-LF 402 R1017 R1019 54.9 14 63 88 IN 14 88 IN 14 88 IN 13 14 88 IN 14 88 OUT B R1018 IN 27.4 27.4 1% 1/16W MF-LF 402 1% 1/16W MF-LF 402 63 R1030 54.9 XDP_TCK PENRYN NOSTUFF R1022 88 13 10 U1000 0.5" MAX LENGTH FOR CPU_GTLREF 88 27 88 13 10 88 14 FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_DSTB_L_N FSB_DSTB_L_P FSB_DINV_L DATA GRP BI FSB_ADS_L FSB_BNR_L FSB_BPRI_L DATA GRP BI 88 14 H1 E2 G5 DATA GRP 88 14 FCBGA OF ADS* BNR* BPRI* DATA GRP BI PENRYN CONTROL 88 14 U1000 XDP/ITP SIGNALS BI A3* A4* A5* A6* A7* A8* A9* A10* A11* A12* A13* A14* A15* A16* ADSTB0* ADDR GROUP0 88 14 FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_ADSTB_L ADDR GROUP1 BI ICH BI 88 14 RESERVED D 88 14 J4 L5 L4 K5 M3 N2 J1 N3 P5 P2 L2 P4 P1 R1 M1 NOSTUFF R1012 1% 1/16W MF-LF 402 1K 5% 1/16W MF-LF 402 2 1% 1/16W MF-LF 402 5% 1/16W MF-LF 402 NOSTUFF R1007 1K 5% 1/16W MF-LF 402 CPU FSB A SYNC_MASTER=M98_MLB SYNC_DATE=11/12/2008 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC SCALE SHT NONE REV 051-7892 A.0.0 OF 10 97 A D D PPBUS_G3H CRITICAL C9540 1 C9545 CRITICAL 1UF 22UF 10% 25V X5R 603-1 20% 25V POLY-TANT CASE-D2-SM C9590 Q9510 CRITICAL SI7904BDN PWRPK-1212-8 4.7 5% 1/16W MF-LF 402 D G P1V1GPU_DRVH MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM S GATE_NODE=TRUE DIDT=TRUE 10% 25V X5R 805 Q9510 CRITICAL 39 44 49 51 63 66 67 70 85 C9501 1UF 10% 10V X5R 402-1 (Internal 10-ohm path from PVCC to VCC) CRITICAL PP5V_S0GPU_P1V1P1V8_VCC PWRPK-1212-8 PP5V_S0 C9500 10UF SI7904BDN 1UF 10% 25V X5R 603-1 20% 25V POLY-TANT CASE-D2-SM PVIN_S0GPU_P1V1 C9595 22UF R9500 67 66 65 64 62 61 46 37 86 79 Q9560 MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=5V D FDMS9600S P1V1GPU_DRVL GATE_NODE=TRUE DIDT=TRUE PP1V1_S0GPU_REG f = 400 kHz 1 10% 50V X7R 603-1 L9510 3.3UH-3.5A (Q9510 limit) CRITICAL C9510 330UF P1V1GPU_VBST MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM P1V1GPU_LL MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM PCMB053T SWITCH_NODE=TRUE 20% 2.0V POLY-TANT B2-SM DIDT=TRUE P1V1GPU_VFB P1V1GPU_TRIP C9515 10UF 17 15 16 18 10 14 11 12 29 20 PLACEMENT_NOTE=Place XW9515 next to C7615 20% 6.3V X5R 603 U9500 R9520 5.76K B 1% 1/16W MF-LF 402 R9521 C9520 21 P1V1S0_VSNS NO STUFF 33 THRM_PAD GND 24 26 25 23 30 27 Q1 10 SW C9560 Q2 C9580 GATE_NODE=TRUE C9565 10UF 20% 6.3V X5R 603 DIDT=TRUE 10% 50V X7R 603-1 GPU_P1V8_REFIN P1V8FB_TRIP P1V8FB_LL PP2V_S0GPU_P1V8_REF MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM VOLTAGE=2V P1V8_GPU_VSNS PLACEMENT_NOTE=Place next to C7665 14.0K R95851 XW9565 SM SWITCH_NODE=TRUE DIDT=TRUE R95631 PGND 20% 2.5V POLY-TANT CASE-B2-SM2 MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM 1 13 28 f = 300 kHz 220UF (=PP1V8FB_S0_REG) C (Q9560 limit) CRITICAL P1V8FB_VBST P1V8FB_DRVL 47 10.5A max output MMD06CZ-SM MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM 1% 1/16W MF-LF 402 130K 1% 1/16W MF-LF 402 1 R9535 5% 50V CERM 402 L9560 2.2UH-14A 0.1UF 32 31 PP1V8_S0GPU_ISNS_R Vout = 1.8V CRITICAL DIDT=TRUE (SGND) 100PF GATE_NODE=TRUE NC 22 6A max output XW9515 SM 0.1UF CRITICAL LDO LDOREFIN VIN BOOT1 OMIT BOOT2 UGATE1 UGATE2 PHASE1 PHASE2 ISL6236 LGATE1 LGATE2 QFN OUT1 OUT2 EN1 EN2 BYP FB1 REFIN2 ILIM1 ILIM2 SKIP* EN_LDO REF SECFB POK1 TON POK2 MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM 10% 10V X5R 402-1 10% 10V X5R 402-1 P1V8FB_DRVH 1UF 1UF PVCC VCC VREF3 C9530 Vout = 1.103V C9503 C9504 MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM 73 71 78 76 G S 19 C MLP PP5V_S0GPU_VREF XW9500 SM 280K 1% 1/16W MF-LF 402 GND_P1V1P1V8_SGND 0.1UF R9562 78.7K R9564 20% 10V CERM 402 MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM VOLTAGE=0V Vout = 0.7V * (1 + Ra / Rb) (Rb should be between 10K and 100K) C9585 127K 1% 1/16W MF-LF 402 C9561 1% 1/16W MF-LF B 0.0022UF 402 10% GPUFB_VID_L 50V CERM 402 Q9565 D 10K SSM3K15FV SOD-VESM-HF 1% 1/16W MF-LF 402 S 84 69 IN 69 OUT 84 69 OUT 84 70 69 IN P1V1_GPU_EN P1V1GPU_PGOOD PM_ALL_GPU_PGOOD P1V8_S0GPU_EN PART NUMBER 353S2312 QTY DESCRIPTION REFERENCE DES CRITICAL IC,ISL6236,DUAL PWM CTRL,QFN32 U9500 CRITICAL G GPIO7_FBVDD_ALTVO 76 77 BOM OPTION 1.1V / 1V8 FB Power Supply A SYNC_MASTER=MUXGFX SYNC_DATE=07/10/2008 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC SCALE SHT NONE REV 051-7892 A.0.0 OF 83 97 A 80 77 70 55 51 49 37 29 28 18 13 24 22 21 47 45 43 68 63 60 85 84 82 96 69 48 25 19 39 59 81 LVDS Receiver Termination GMUX CPLD PP3V3_S0 C9610 0.1UF C9621 C9622 0.1UF 20% 10V CERM 402 0.1UF 20% 10V CERM 402 C9623 0.1UF 20% 10V CERM 402 C9624 0.1UF 20% 10V CERM 402 C9625 0.1UF 20% 10V CERM 402 20% 10V CERM 402 C9626 0.1UF C9628 0.1UF 20% 10V CERM 402 C9629 0.1UF 20% 10V CERM 402 20% 10V CERM 402 59 60 63 68 69 70 77 80 81 82 13 18 19 21 22 24 25 28 29 37 39 43 45 47 48 49 51 55 84 85 96 90 84 18 C9630 0.1UF 90 84 18 20% 10V CERM 402 90 84 18 90 84 18 L9631 90 84 18 FERR-220-OHM PP3V3_S0_ULC_F PP1V8_S0 D C9611 1 0.1UF C9612 0.1UF 20% 10V CERM 402 C9613 0.1UF 20% 10V CERM 402 C9614 0.1UF 20% 10V CERM 402 20% 10V CERM 402 C9615 0.1UF C9616 0.1UF 20% 10V CERM 402 0.1UF 0.1UF 20% 10V CERM 402 90 84 18 MIN_LINE_WIDTH=0.2 mm 0402 MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V C9631 C9617 90 84 18 95 84 78 20% 10V CERM 402 20% 10V CERM 402 L9627 95 84 78 FERR-220-OHM PP3V3_S0_LRC_F 95 84 78 95 84 78 MIN_LINE_WIDTH=0.2 mm0402 MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V 87 95 84 78 95 84 78 PP1V2_S0 C9627 95 84 78 PLACEMENT_NOTE=Place at U9200 LVDS_IG_A_CLK_P LVDS_IG_A_DATA_P LVDS_IG_A_DATA_P LVDS_IG_A_DATA_P LVDS_IG_B_DATA_P LVDS_IG_B_DATA_P LVDS_IG_B_DATA_P LVDS_EG_A_CLK_P LVDS_EG_A_DATA_P LVDS_EG_A_DATA_P LVDS_EG_A_DATA_P LVDS_EG_B_DATA_P LVDS_EG_B_DATA_P LVDS_EG_B_DATA_P R9650 R9651 R9652 R9653 R9654 R9655 R9656 100 100 100 100 1 1 100 100 100 1 R9660 R9661 R9662 R9663 R9664 R9665 R9666 100 100 100 100 1 1 100 100 100 1 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 0.1UF C9600 4.7UF 20% 4V X5R 402 C9604 0.1UF C9605 0.1UF 20% 10V CERM 402 C9606 0.1UF 20% 10V CERM 402 C9607 0.1UF 20% 10V CERM 402 20% 10V CERM 402 C9608 0.1UF 20% 10V CERM 402 C9609 0.1UF 20% 10V CERM 402 84 GMUX_CFG0 1% 1/16W MF-LF 402 OUT 84 81 OUT 84 71 OUT 84 OUT 84 OUT 84 OUT 84 OUT 84 OUT 77 OUT 80 OUT 91 44 42 19 BI BI BI BI 91 44 42 19 BI 91 26 19 IN 26 84 18 B R9647 10K 1% 1/16W MF-LF 402 90 84 18 IN 90 84 18 IN 90 84 18 IN 90 84 18 IN 90 84 18 IN 90 84 18 IN 90 84 18 IN 90 84 18 IN 90 84 18 IN 90 84 18 IN 90 84 18 IN 90 84 18 IN 90 84 18 IN 90 84 18 IN OUT IN IN IN 84 IN PL2A PL2B PL10A PL10B PL11A PL11B PL12A PL12B PL13A PL13B PL14A PL14B PL15A PL15B PL16A PL16B PL18A PL18B PL19A PL19B PL32A PL32B (Tie/strap low if EGPU doesn’t provide CLKREQ_L output, provide pullup to GPU rail if using CLKREQ_L output from EGPU) GND J1 PM_SLP_S3_L Isolation 82 81 80 77 70 69 68 63 60 59 28 25 24 22 21 19 18 13 55 51 49 48 47 45 43 39 37 29 96 85 84 PP3V3_S0 Q9670 PM_SLP_S3_L K12 A4 P11 ULC_VCCPLL LRC_VCCPLL VCCIO7 VCCIO6 VCCIO5 VCCIO4 VCCIO3 1/16W 1/16W 1/16W 1/16W MF-LF MF-LF MF-LF MF-LF 402 402 402 402 1/16W MF-LF 402 1/16W MF-LF 402 1/16W MF-LF 402 LVDS_IG_B_DATA_N LVDS_IG_B_DATA_N LVDS_IG_B_DATA_N LVDS_EG_A_CLK_N LVDS_EG_A_DATA_N LVDS_EG_A_DATA_N LVDS_EG_A_DATA_N LVDS_EG_B_DATA_N LVDS_EG_B_DATA_N LVDS_EG_B_DATA_N R9680 1K JTAG_GMUX_TCK R9690 4.7K EG_CLKREQ_OUT_L NO STUFF R9695 10K 10K A2 A3 A1 B3 C5 A5 B6 C7 A6 A7 C8 C9 A8 B9 A9 C10 B10 A10 A11 B12 B13 A13 LVDS_B_DATA_P LVDS_B_DATA_N LVDS_B_DATA_P LVDS_B_DATA_N LVDS_B_DATA_P LVDS_B_DATA_N GMUX_PM_SLP_S3_L GMUX_DEBUG_RESET_L LVDS_A_CLK_P LVDS_A_CLK_N LVDS_B_CLK_P LVDS_B_CLK_N LVDS_A_DATA_P LVDS_A_DATA_N LVDS_A_DATA_P LVDS_A_DATA_N LVDS_A_DATA_P LVDS_A_DATA_N TP_GMUX_PT20A TP_GMUX_PT20B TP_GMUX_PT32A TP_GMUX_PT32B PR2A PR2B PR10A PR10B PR11A PR11B PR12A PR12B PR13A PR13B PR14A PR14B PR15A PR15B PR16A PR16B PR18A PR18B PR30A PR30B A14 B14 D12 D13 D14 E14 E12 F12 F14 G14 G12 G13 H13 H12 H14 J12 L14 M13 N14 N13 DP_CA_DET DP_HOTPLUG_DET LVDS_EG_A_DATA_P LVDS_EG_A_DATA_N LVDS_EG_A_DATA_P LVDS_EG_A_DATA_N LVDS_EG_A_DATA_P LVDS_EG_A_DATA_N LVDS_EG_B_DATA_P LVDS_EG_B_DATA_N LVDS_EG_B_DATA_P LVDS_EG_B_DATA_N LVDS_EG_B_DATA_P LVDS_EG_B_DATA_N LVDS_EG_A_CLK_P LVDS_EG_A_CLK_N LVDS_IG_PANEL_PWR EG_LCD_PWR_EN LVDS_IG_BKL_ON EG_BKLT_EN OUT 81 95 OUT 81 95 OUT 81 95 OUT 81 95 OUT 81 95 OUT 84 81 84 81 84 81 81 95 IN 84 IN 84 18 84 90 18 84 90 18 84 90 18 84 90 18 84 90 D 18 84 90 78 84 95 78 84 95 78 84 95 78 84 95 78 84 95 78 84 95 78 84 95 PP3V3_S0 5% 1/16W MF-LF 402 5% 1/16W MF-LF 402 5% 1/16W MF-LF 402 1% 1/16W MF-LF 402 PLACEMENT_NOTE=Place on top side at U9200 DP_MUX_SEL_EG R9681 10K C LVDS_DDC_SEL_IG R9682 10K LVDS_DDC_SEL_EG R9683 10K 5% 1/16W MF-LF 402 5% 1/16W MF-LF 402 5% 1/16W MF-LF 402 (Use open-drain PGOOD output to hold off the start of the GPU PWRSEQ until the first GPU rail’s source is valid) OUT 81 95 OUT 81 95 OUT 81 95 OUT 81 95 OUT 81 95 OUT 81 95 OUT 81 95 OUT 81 95 OUT 81 95 OUT 81 95 84 71 84 18 85 84 84 NO STUFF EG_RESET_L R9691 100K GMUX_INT R9692 20K LCD_BKLT_PWM R9693 100K EG_CLKREQ_IN_L R9694 R9630 100K EG_PWRSEQ_HW 5% IN 18 77 81 82 IN 81 82 IN 78 84 95 IN 78 84 95 IN 78 84 95 IN 78 84 95 IN 78 84 95 IN 78 84 95 IN 78 84 95 IN 78 84 95 IN 78 84 95 IN 78 84 95 IN 78 84 95 IN 78 84 95 IN 78 84 95 IN 78 84 95 EG_RAIL1_EN EG_PWRSEQ_GMUX R9631 EG_RAIL2_EN EG_PWRSEQ_GMUX R9632 84 EG_RAIL3_EN EG_PWRSEQ_GMUX R9633 84 EG_RAIL4_EN R9634 84 5% 5% 5% 5% 1/16W MF-LF 402 5% 1/16W MF-LF 402 5% 1/16W MF-LF 402 5% 1/16W MF-LF 402 EXTGPU_PWR_EN OUT 1/16W MF-LF 402 P1V1_GPU_EN OUT 69 83 P3V3GPU_EN OUT 69 70 GPUVCORE_ENOUT 69 79 1/16W MF-LF 402 1/16W MF-LF 402 1/16W MF-LF 402 EG_PWRSEQ_GMUX 5% 69 B P1V8_S0GPU_EN 69 OUT 1/16W MF-LF 402 70 83 The MAKE BASE properties for these signals are on the POWER CONTROL page IN 18 IN 76 77 IN 18 IN 76 77 NO STUFF NO STUFF C9691 0.1UF C9693 0.1UF 20% 10V CERM 402 20% 10V CERM 402 NO STUFF C9692 NO STUFF 0.1UF C9694 0.1UF 20% 10V CERM 402 20% 10V CERM 402 Graphics MUX (GMUX) GMUX_JTAG_TCK Inversion JTAG_GMUX_TCK SYNC_MASTER=MUXGFX G GMUX_PM_SLP_S3_L SYNC_DATE=07/10/2008 1% 1/16W MF-LF 402 GMUX_PM_SLP_S3_L MAKE_BASE=TRUE NOTICE OF PROPRIETARY PROPERTY 84 D TABLE_5_HEAD PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION IC,XP2-5,HF,CPLD,BLANK U9600 CRITICAL GMUX_5K_BLANK 341S2479 IC,CPLD,LATTICE,132CSBGA,K19 U9600 CRITICAL GMUX_PROG Q9670 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING SSM6N15FEAPE TABLE_5_ITEM 336S0025 SOT563 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE TABLE_5_ITEM 84 II NOT TO REPRODUCE OR COPY IT S G III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART GMUX_JTAG_TCK_L IN SIZE 17 DRAWING NUMBER D APPLE INC REV 051-7892 SCALE SHT NONE 18 84 90 1 S IN D 42 37 34 21 82 69 1/16W MF-LF 402 1/16W MF-LF 402 1/16W MF-LF 402 LVDS_IG_A_CLK_N LVDS_IG_A_DATA_N LVDS_IG_A_DATA_N LVDS_IG_A_DATA_N 96 85 84 82 81 80 77 70 69 68 63 60 59 55 51 49 48 47 45 43 39 37 29 28 25 24 22 21 19 18 13 GMUX_DEBUG_RESET_L SILK_PART=GMUX_RST PT2A PT2B PT3A PT3B PT4A PT4B PT14A PT14B PT15A PT15B PT16A PT16B PT17A PT17B PT18A PT18B PT19A PT19B PT20A PT20B PT32A PT32B 84 SSM6N15FEAPE R9670 10K SOT563 B5 B7 A12 C14 F13 M12 M9 M3 N5 M1 C3 F2 BANK6 26 84 83 69 B1 B2 C2 D3 D1 E1 D2 E3 F1 G1 F3 G2 H2 G3 H1 H3 L1 L3 K3 L2 N1 P1 402 402 402 402 R96791 84 LVDS_IG_B_DATA_P LVDS_IG_B_DATA_N TP_GMUX_PL10A TP_GMUX_PL10B LVDS_IG_A_DATA_P LVDS_IG_A_DATA_N LVDS_IG_A_DATA_P LVDS_IG_A_DATA_N LVDS_IG_A_DATA_P LVDS_IG_A_DATA_N LVDS_IG_B_DATA_P LVDS_IG_B_DATA_N LVDS_IG_B_DATA_P LVDS_IG_B_DATA_N LVDS_IG_A_CLK_P LVDS_IG_A_CLK_N TP_LVDS_MUX_SEL_EG TP_GMUX_PL18B_VSYNC GMUX_PCIE_RESET_L GMUX_PM_SLP_S3_L PM_ALL_GPU_PGOOD EG_CLKREQ_IN_L BANK7 NO STUFF IN OUT BANK4 91 44 42 19 91 44 42 19 91 44 42 19 MF-LF MF-LF MF-LF MF-LF Required Pulldowns BANK0 10K OUT 81 CSBGA-HF BANK5 10K 1% 1/16W MF-LF 402 R9646 OUT 84 81 U9600 PB2A PB2B PB14A PB14B PB15A (OD) PB15B PB16A PB16B PB17A PB17B PB18A PB18B (OD) PB19A PB19B PB20A PB20B PB30A PB30B PB31A PB31B PB32A PB32B BANK1 R9641 NO STUFF OUT 84 81 CFG0 84 XP28 P2 N2 P4 N4 N3 M4 P5 M5 P6 M6 P7 M7 N7 N8 P9 N9 P10 M10 P12 P13 N12 P14 BANK2 85 84 K1 LCD_BKLT_EN LCD_BKLT_PWM LVDS_DDC_SEL_EG LVDS_DDC_SEL_IG DP_MUX_EN DP_MUX_SEL_EG EG_RESET_L EG_RAIL1_EN EG_RAIL2_EN EG_RAIL3_EN EG_RAIL4_EN EG_CLKREQ_OUT_L DP_CA_DET_EG LCD_PWR_EN LPC_AD LPC_AD LPC_AD LPC_AD LPC_FRAME_L LPC_RESET_L LPC_CLK33M_GMUX GMUX_INT BANK3 NO STUFF OUT ULC_GNDPLL LRC_GNDPLL 86 B4 M11 C VCCJ OMIT CRITICAL GNDIO7 IN VCCIO2 19 TCK TDI TDO TMS TOE GNDIO6 OUT K14 L13 K13 L12 K2 VCCIO1 17 JTAG_GMUX_TCK JTAG_GMUX_TDI JTAG_GMUX_TDO JTAG_GMUX_TMS GMUX_TOE GNDIO5 IN GNDIO3 GNDIO4 19 GNDIO2 1% 1/16W MF-LF 402 GNDIO1 84 10K GNDIO0 R9645 VCCAUX B8 C6 C12 C13 E13 M14 N10 N6 P3 M2 C1 E2 10K 1% 1/16W MF-LF 402 VCCIO0 C11 J2 J14 M8 B11 C4 J3 J13 N11 P8 R9640 (All 14 resistors) Required Pullups 20% 10V CERM 402 VCC 1/16W 1/16W 1/16W 1/16W SIGNAL_MODEL=EMPTY 84 A PP3V3_S0 55 25 18 87 70 69 A.0.0 OF 84 97 A *L9701, D9701, C9796, C9797, C9799, C9712 AND C9713 SHOULD ALL BE PLACED NEAR EACHOTHER *PPVOUT_S0_LCDBKLT_SW SHOULD BE KEPT AS SHORT AS POSSIBLE * LVDS_IG_BKL_PWM SHOULD BE AWAY FROM BOOST CIRCUIT BKL_VLDO_EN_L CRITICAL Q9701 NTZD3155C SOT-563-HF P-CHN D D D R9735 G 100K S 1% 1/16W MF-LF 402 PP5V_S0 39 44 49 51 63 66 67 70 83 BKLT_EN 85 MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM D R9701 BKLT_EN_R G S 5% 1/16W MF-LF 402 N-CHN MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=5V R9702 5% 1/16W MF-LF 402 CRITICAL PPBUS_S0_LCDBKLT_PWR 1 XW9722 SM 1 C9712 0.1UF 10UF NO STUFF 10% 25V X5R 402 10% 25V X5R 805 BKL_VLDO PP3V3_S0 100K 5% 1/16W MF-LF 402 C9714 0.01UF 10% 16V CERM 402 PPVOUT_S0_LCDBKLT C9710 1UF 10% 25V X5R 603-1 C9711 0.1UF 10% 16V X5R 402 VDDIO 53 80 MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.375 MM VOLTAGE=50V C9796 220PF 10% 50V X7R-CERM 402 5% 1/16W MF-LF 402 ISNS_LCDBKLT_N R97161 SWITCH_NODE=TRUE RB160M-60G ISNS_LCDBKLT_P 81 80 77 70 69 68 63 60 59 28 25 24 22 21 19 18 13 55 51 49 48 47 45 43 39 37 29 96 84 82 MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.375 MM VOLTAGE=50V R9703 23 OUT XW9721 SM C9713 22 OUT 96 53 PPBUS_S0_LCDBKLT_PWR_SW C9799 2.2UF 10% 100V X7R 1210 C C9797 2.2UF 10% 100V X7R 1210 PPVIN_BKL_R 96 53 MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.375 MM VOLTAGE=6V IHLP2525CZ-SM PPVIN_BKL CRITICAL C D9701 SOD-123 22UH-2.5A 86 85 CRITICAL L9701 XW9720 SM VLDO VIN CRITICAL U9701 R9714 IF_SEL=1 FOR SMBUS NC 100K 5% 1/16W MF-LF 402 20 ADR 5% R9757 SMBUS_MCP_1_DATA 1/16W MF-LF 402 OUT2 13 BKL_ISEN2 OUT3 14 BKL_ISEN3 OUT4 16 BKL_ISEN4 PWM OUT5 17 BKL_ISEN5 TP_BKL_FAULT FAULT OUT6 18 BKL_ISEN6 BKLT_EN EN OUT7 19 IF_SEL 5% PPBUS_S0_LCDBKLT_PWR 85 BKL_SDA 11 SDA OMIT NO STUFF C9723 0.1UF 10% 25V X5R 402 BKL_ISEN1 R9715 100K 1% 1/16W MF-LF 402 10.2 LED_RETURN_1 OUT 80 OUT MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm 80 OUT MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm 80 OUT MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm 80 OUT MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm 80 OUT 80 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm 0.1% 1/16W TF 402 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm R9718 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm 10.2 LED_RETURN_2 0.1% 1/16W TF 402 B R9719 NC MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm GND_SW 1% 1/16W MF-LF 402 301K 1 10 SCLK 1/16W MF-LF 402 R9731 86 85 BKL_SCL LVDS_BKL_PWM_RC 15 GND_L R9717 FB 21 THRM PAD 10.2 LED_RETURN_3 0.1% 1/16W TF 402 R9720 25 SW 24 OUT1 12 GND_S B 91 60 45 21 R9753 SMBUS_MCP_1_CLK ALSO ALSI BKL_IF_SEL 91 60 45 21 LP8543SQX LLP NO STUFF 1 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm 10.2 LED_RETURN_4 0.1% 1/16W TF 402 R9721 R9704 84 IN LCD_BKLT_PWM 1 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm 5% 1/16W MF-LF 402 XW9710 SM C9704 33PF 5% 50V CERM 402 BKL_SGND LED_RETURN_5 0.1% 1/16W TF 402 NO STUFF R9704 SHOULD BE 47K IF RC FILTER IS USED 10.2 R9722 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm PLACE XW9700 CLOSE TO C9712 AND C9713 10.2 LED_RETURN_6 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm 0.1% 1/16W TF 402 LCD BACKLIGHT DRIVER TABLE_5_HEAD A PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL U9701 CRITICAL SYNC_MASTER=DDR BOM OPTION SYNC_DATE=12/12/2008 TABLE_5_ITEM 353S2670 IC,LP8543,WHT LED BKLT,PROD NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC SCALE SHT NONE REV 051-7892 A.0.0 OF 85 97 A CRITICAL Q9806 FDC638APZ_SBMS001 CRITICAL F9800 IN 0402-HF PPBUS_S0_LCDBKLT_FUSED MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.251 mm VOLTAGE=12.6V R9808 301K C9802 0.1UF 1% 1/16W MF-LF 402 MOSFET FDC638APZ CHANNEL P-TYPE RDS(ON) LOADING 10% 16V X5R 402 D 43 mOhm @4.5V 0.4 A (EDP) D PPBUS_G3H 2AMP-32V 67 66 65 64 62 61 46 37 83 79 PPBUS S0 LCDBkLT FET SSOT6-HF PPBUS_S0_LCDBKLT_EN_DIV R9809 147K 1% 1/16W MF-LF 402 PPBUS_S0_LCDBKLT_EN_L Q9807 D SSM6N15FEAPE SOT563 86 84 IN G LCD_BKLT_EN S PPBUS_S0_LCDBKLT_PWR OUT MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.6V BKLT_EN_L Q9807 85 D SSM6N15FEAPE SOT563 C 26 IN G BKLT_PLT_RST_L C S B B LCD_BKLT_EN 84 86 R9840 4.7K 5% 1/16W MF-LF 402 LCD Backlight Support A SYNC_MASTER=YITE_M98_MLB SYNC_DATE=07/02/2008 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC SCALE SHT NONE REV 051-7892 A.0.0 OF 86 97 A 1.8V/1.2V S0 SWITCHER D D 37 34 30 26 24 22 20 18 96 82 70 69 68 64 54 44 38 PP3V3_S5 CRITICAL C9900 L9980 10UF 2.2UH-1.2A 20% 6.3V X5R 603 PP1V2_S0 PCAA031B-SM P1V2S0_SW MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm SWITCH_NODE=TRUE DIDT=TRUE C9982 10PF 5% 50V CERM 402 C R9982 (Switcher limit) 1% 1/16W MF-LF 402 69 IN P1V2R1V8S0_EN MODE R9983 SW2 VFB1 20% 6.3V X5R 603 280K DFN RUN2 CRITICAL SW1 C9985 10UF U9900 C f = 2.25 MHz 1% 1/16W MF-LF 402 LTC3419 RUN1 0.6A max output 280K P1V2S0_VFB VIN 84 Vout = 1.2V VFB2 CRITICAL L9900 P1V8S0_SW MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm SWITCH_NODE=TRUE DIDT=TRUE 2.2UH-1.2A PP1V8_S0 PCAA031B-SM Vout = 1.8V C9901 10PF THRM PAD 5% 50V CERM 402 P2V5S0_VFB 0.6A max output R9900 475K (Switcher limit) 1% 1/16W MF-LF 402 f = 2.25 MHz R9901 237K 18 25 55 69 70 84 C9905 10UF 20% 6.3V 603 X5R 1% 1/16W MF-LF 402 Vout = 0.6V * (1 + Ra/Rb) B B Misc Power Supplies A SYNC_MASTER=MUXGFX SYNC_DATE=02/01/2008 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC SCALE SHT NONE REV 051-7892 A.0.0 OF 87 97 A FSB (Front-Side Bus) Constraints CPU / FSB Net Properties TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP FSB_50S * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD NET_TYPE ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =1:1_DIFFPAIR =1:1_DIFFPAIR TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM FSB_DATA * =2x_DIELECTRIC ? FSB_DSTB * =3x_DIELECTRIC ? TABLE_SPACING_RULE_ITEM FSB_DATA TOP,BOTTOM =4x_DIELECTRIC ? FSB_DSTB TOP,BOTTOM =5x_DIELECTRIC ? TABLE_SPACING_RULE_ITEM D TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM FSB_ADDR * =STANDARD TABLE_SPACING_RULE_ITEM ? FSB_ADDR TOP,BOTTOM =3x_DIELECTRIC ? TABLE_SPACING_RULE_ITEM FSB_ADSTB * =2x_DIELECTRIC TABLE_SPACING_RULE_ITEM ? FSB_ADSTB TOP,BOTTOM =4x_DIELECTRIC ? TABLE_SPACING_RULE_ITEM FSB_1X * =STANDARD FSB 4X Signal Groups FSB_DSTB_50S TABLE_SPACING_RULE_ITEM ? FSB_1X TOP,BOTTOM =3x_DIELECTRIC ? All 4x/2x/1x FSB signals with impedance requirements are 50-ohm single-ended FSB 2X Signals FSB 4X signals / groups shown in signal table on right Signals within each 4x group should be matched within ps of strobe DSTB# complementary pairs should be matched within ps of each other, all DSTB#s matched to +/- 300 ps Spacing is 2x dielectric between DATA#, DINV# signals, with 3x dielectric spacing to the DSTB#s DSTB# complementary pairs are spaced normally and are NOT routed as differential pairs FSB 2X signals / groups shown in signal table on right Signals within each 2x group should be matched within 20 ps ADTSB#s should be matched +/- 300 ps Spacing is 1x dielectric between ADDR#, REQ# signals, with 2x dielectric spacing to ADSTB# FSB 1X signals shown in signal table on right Signals within each 1x group should be matched to CPU clock, +0/-1000 mils FSB 1X Signals Design Guide recommends each strobe/signal group is routed on the same layer Intel Design Guide recommends FSB signals be routed only on internal layers NOTE: Intel Design Guide allows closer spacing if signal lengths can be shortened SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2 SOURCE: Santa Rosa Platform DG, Rev 1.5 (#22294), Sections 4.2 & 4.3 CPU Signal Constraints TABLE_PHYSICAL_RULE_HEAD C PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP CPU_50S * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM CPU_27P4S * =27P4_OHM_SE =27P4_OHM_SE =27P4_OHM_SE =27P4_OHM_SE MIL MIL NOTE: mil gap is for VCCSense pair, which Intel says to route with mil spacing without specifying a target impedance TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LINE-TO-LINE SPACING WEIGHT CPU_AGTL LAYER * =STANDARD ? CPU_8MIL * MIL ? TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT =2x_DIELECTRIC ? TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM CPU_AGTL TOP,BOTTOM TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM CPU_COMP * 25 MIL ? CPU_GTLREF * 25 MIL ? TABLE_SPACING_RULE_ITEM SR DG recommends at least 25 mils, >50 mils preferred TABLE_SPACING_RULE_ITEM CPU_ITP * =2:1_SPACING ? CPU_VCCSENSE * 25 MIL ? TABLE_SPACING_RULE_ITEM Most CPU signals with impedance requirements are 55-ohm single-ended Some signals require 27.4-ohm single-ended impedance SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2 SOURCE: Santa Rosa Platform DG, Rev 0.9 (#20517), Sections 4.4 & 5.8.2.4 MCP FSB COMP Signal Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MCP_50S * =50_OHM_SE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD TABLE_PHYSICAL_RULE_ITEM B TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM MCP_FSB_COMP * MIL ? SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2.4 FSB Clock Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM CLK_FSB * =3x_DIELECTRIC TABLE_SPACING_RULE_ITEM ? CLK_FSB TOP,BOTTOM =4x_DIELECTRIC FSB_50S FSB_50S FSB_DSTB_50S FSB_DSTB_50S FSB_DATA FSB_DATA FSB_DSTB FSB_DSTB FSB_D_L FSB_DINV_L FSB_DSTB_L_P FSB_DSTB_L_N FSB_DATA_GROUP1 FSB_DATA_GROUP1 FSB_DSTB1 FSB_DSTB1 FSB_50S FSB_50S FSB_DSTB_50S FSB_DSTB_50S FSB_DATA FSB_DATA FSB_DSTB FSB_DSTB FSB_D_L FSB_DINV_L FSB_DSTB_L_P FSB_DSTB_L_N FSB_DATA_GROUP2 FSB_DATA_GROUP2 FSB_DSTB2 FSB_DSTB2 FSB_50S FSB_50S FSB_DSTB_50S FSB_DSTB_50S FSB_DATA FSB_DATA FSB_DSTB FSB_DSTB FSB_D_L FSB_DINV_L FSB_DSTB_L_P FSB_DSTB_L_N FSB_DATA_GROUP3 FSB_DATA_GROUP3 FSB_DSTB3 FSB_DSTB3 FSB_50S FSB_50S FSB_DSTB_50S FSB_DSTB_50S FSB_DATA FSB_DATA FSB_DSTB FSB_DSTB FSB_D_L FSB_DINV_L FSB_DSTB_L_P FSB_DSTB_L_N FSB_ADDR_GROUP0 FSB_ADDR_GROUP0 FSB_ADSTB0 FSB_50S FSB_50S FSB_50S FSB_ADDR FSB_ADDR FSB_ADSTB FSB_A_L FSB_REQ_L FSB_ADSTB_L FSB_ADDR_GROUP1 FSB_ADSTB1 FSB_50S FSB_50S FSB_ADDR FSB_ADSTB FSB_A_L FSB_ADSTB_L FSB_1X FSB_BREQ0_L FSB_BREQ1_L FSB_1X FSB_1X FSB_1X FSB_1X FSB_1X FSB_1X FSB_1X FSB_1X FSB_CPURST_L FSB_1X FSB_1X FSB_50S FSB_50S FSB_50S FSB_50S FSB_50S FSB_50S FSB_50S FSB_50S FSB_50S FSB_50S FSB_50S FSB_50S FSB_50S FSB_50S FSB_1X FSB_1X FSB_1X FSB_1X FSB_1X FSB_1X FSB_1X FSB_1X FSB_1X FSB_1X FSB_1X FSB_1X FSB_1X FSB_1X FSB_ADS_L FSB_BREQ0_L FSB_BREQ1_L FSB_BNR_L FSB_BPRI_L FSB_DBSY_L FSB_DEFER_L FSB_DRDY_L FSB_HIT_L FSB_HITM_L FSB_LOCK_L FSB_CPURST_L FSB_RS_L FSB_TRDY_L CPU_ASYNC CPU_BSEL CPU_FERR_L CPU_ASYNC CPU_INIT_L CPU_ASYNC_R CPU_ASYNC_R CPU_PROCHOT_L CPU_PWRGD CPU_ASYNC CPU_ASYNC PM_THRMTRIP_L FSB_CPUSLP_L CPU_FROM_SB CPU_DPRSTP_L CPU_ASYNC MCP_CPU_COMP MCP_CPU_COMP MCP_CPU_COMP MCP_CPU_COMP CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S MCP_50S MCP_50S MCP_50S MCP_50S CPU_AGTL CPU_AGTL CPU_8MIL CPU_AGTL CPU_AGTL CPU_AGTL CPU_AGTL CPU_AGTL CPU_AGTL CPU_AGTL CPU_AGTL CPU_8MIL CPU_AGTL CPU_AGTL CPU_AGTL CPU_AGTL MCP_FSB_COMP MCP_FSB_COMP MCP_FSB_COMP MCP_FSB_COMP CPU_A20M_L CPU_BSEL CPU_FERR_L CPU_IGNNE_L CPU_INIT_L CPU_INTR CPU_NMI CPU_PROCHOT_L CPU_PWRGD CPU_SMI_L CPU_STPCLK_L PM_THRMTRIP_L FSB_CPUSLP_L CPU_DPSLP_L CPU_DPRSTP_L FSB_DPWR_L MCP_BCLK_VML_COMP_VDD MCP_BCLK_VML_COMP_GND MCP_CPU_COMP_VCC MCP_CPU_COMP_GND FSB_CLK_CPU FSB_CLK_CPU FSB_CLK_ITP FSB_CLK_ITP FSB_CLK_MCP FSB_CLK_MCP CLK_FSB_100D CLK_FSB_100D CLK_FSB_100D CLK_FSB_100D CLK_FSB_100D CLK_FSB_100D CLK_FSB CLK_FSB CLK_FSB CLK_FSB CLK_FSB CLK_FSB FSB_CLK_CPU_P FSB_CLK_CPU_N FSB_CLK_ITP_P FSB_CLK_ITP_N FSB_CLK_MCP_P FSB_CLK_MCP_N CPU_IERR_L CPU_50S PM_DPRSLPVR (See above) CPU_50S CPU_50S CPU_AGTL CPU_AGTL PM_DPRSLPVR IMVP_DPRSLPVR CPU_GTLREF CPU_COMP CPU_COMP CPU_COMP CPU_COMP CPU_50S CPU_50S CPU_27P4S CPU_50S CPU_27P4S CPU_GTLREF CPU_COMP CPU_COMP CPU_COMP CPU_COMP CPU_GTLREF CPU_COMP CPU_COMP CPU_COMP CPU_COMP XDP_TDI XDP_TDO XDP_TMS XDP_TCK XDP_TRST_L XDP_BPM_L XDP_BPM_L5 (FSB_CPURST_L) CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_ITP CPU_ITP CPU_ITP CPU_ITP CPU_ITP CPU_ITP CPU_ITP CPU_ITP XDP_TDI XDP_TDO XDP_TMS XDP_TCK XDP_TRST_L XDP_BPM_L XDP_BPM_L XDP_CPURST_L CPU_VCCSENSE CPU_VCCSENSE (CPU_VCCSENSE) (CPU_VCCSENSE) CPU_50S CPU_50S CPU_27P4S CPU_27P4S CPU_27P4S CPU_27P4S CPU_8MIL CPU_8MIL CPU_VCCSENSE CPU_VCCSENSE CPU_VCCSENSE CPU_VCCSENSE CPU_VID IMVP6_VID CPU_VCCSENSE_P CPU_VCCSENSE_N IMVP6_VSEN_P IMVP6_VSEN_N CPU_IERR_L 10 14 10 14 10 14 10 14 10 14 10 14 10 14 D 10 14 10 14 10 14 10 14 10 14 10 14 10 14 10 14 10 14 10 14 10 14 10 14 10 14 10 14 10 14 10 14 14 10 14 10 14 10 14 10 14 10 14 10 14 10 14 C 10 14 10 13 14 10 14 10 14 10 14 10 10 14 10 14 10 14 10 14 10 14 10 14 43 63 10 13 14 10 14 10 14 10 14 43 10 14 10 14 10 14 63 10 14 14 14 14 14 10 14 10 14 B 13 14 13 14 14 14 10 21 63 63 DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM CLK_FSB_100D FSB_DATA_GROUP0 FSB_DATA_GROUP0 FSB_DSTB0 FSB_DSTB0 10 27 10 10 10 10 ? SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2.5 A 10 13 10 10 13 10 13 10 13 10 13 10 13 13 11 CPU/FSB Constraints 63 11 63 SYNC_MASTER=MUXGFX SYNC_DATE=02/18/2008 11 63 NOTICE OF PROPRIETARY PROPERTY 63 63 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC SCALE SHT NONE REV 051-7892 A.0.0 OF 88 97 A Memory Bus Constraints Memory Net Properties TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP MEM_40S * =40_OHM_SE =40_OHM_SE =40_OHM_SE =40_OHM_SE =STANDARD =STANDARD NET_TYPE ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM MEM_40S_VDD * =40_OHM_SE =40_OHM_SE =40_OHM_SE =40_OHM_SE =STANDARD =STANDARD MEM_A_CLK MEM_A_CLK MEM_70D_VDD MEM_70D_VDD MEM_CLK MEM_CLK MEM_A_CLK_P MEM_A_CLK_N MEM_A_CNTL MEM_A_CNTL MEM_A_CNTL MEM_40S_VDD MEM_40S_VDD MEM_40S_VDD MEM_CTRL MEM_CTRL MEM_CTRL MEM_A_CKE MEM_A_CS_L MEM_A_ODT MEM_A_CMD MEM_A_CMD MEM_A_CMD MEM_A_CMD MEM_A_CMD MEM_40S_VDD MEM_40S_VDD MEM_40S_VDD MEM_40S_VDD MEM_40S_VDD MEM_CMD MEM_CMD MEM_CMD MEM_CMD MEM_CMD MEM_A_A MEM_A_BA MEM_A_RAS_L MEM_A_CAS_L MEM_A_WE_L MEM_A_DQ_BYTE0 MEM_A_DQ_BYTE1 MEM_A_DQ_BYTE2 MEM_A_DQ_BYTE3 MEM_A_DQ_BYTE4 MEM_A_DQ_BYTE5 MEM_A_DQ_BYTE6 MEM_A_DQ_BYTE7 MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ_BYTE0 MEM_A_DQ_BYTE1 MEM_A_DQ_BYTE2 MEM_A_DQ_BYTE3 MEM_A_DQ_BYTE4 MEM_A_DQ_BYTE5 MEM_A_DQ_BYTE6 MEM_A_DQ_BYTE7 MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_A_DM MEM_A_DM MEM_A_DM MEM_A_DM MEM_A_DM MEM_A_DM MEM_A_DM MEM_A_DM MEM_A_DQS0 MEM_A_DQS0 MEM_A_DQS1 MEM_A_DQS1 MEM_A_DQS2 MEM_A_DQS2 MEM_A_DQS3 MEM_A_DQS3 MEM_A_DQS4 MEM_A_DQS4 MEM_A_DQS5 MEM_A_DQS5 MEM_A_DQS6 MEM_A_DQS6 MEM_A_DQS7 MEM_A_DQS7 MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_B_CLK MEM_B_CLK MEM_70D_VDD MEM_70D_VDD MEM_CLK MEM_CLK MEM_B_CLK_P MEM_B_CLK_N MEM_B_CNTL MEM_B_CNTL MEM_B_CNTL MEM_40S_VDD MEM_40S_VDD MEM_40S_VDD MEM_CTRL MEM_CTRL MEM_CTRL MEM_B_CKE MEM_B_CS_L MEM_B_ODT MEM_B_CMD MEM_B_CMD MEM_B_CMD MEM_B_CMD MEM_B_CMD MEM_40S_VDD MEM_40S_VDD MEM_40S_VDD MEM_40S_VDD MEM_40S_VDD MEM_CMD MEM_CMD MEM_CMD MEM_CMD MEM_CMD MEM_B_A MEM_B_BA MEM_B_RAS_L MEM_B_CAS_L MEM_B_WE_L MEM_B_DQ_BYTE0 MEM_B_DQ_BYTE1 MEM_B_DQ_BYTE2 MEM_B_DQ_BYTE3 MEM_B_DQ_BYTE4 MEM_B_DQ_BYTE5 MEM_B_DQ_BYTE6 MEM_B_DQ_BYTE7 MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ_BYTE0 MEM_B_DQ_BYTE1 MEM_B_DQ_BYTE2 MEM_B_DQ_BYTE3 MEM_B_DQ_BYTE4 MEM_B_DQ_BYTE5 MEM_B_DQ_BYTE6 MEM_B_DQ_BYTE7 MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_B_DM MEM_B_DM MEM_B_DM MEM_B_DM MEM_B_DM MEM_B_DM MEM_B_DM MEM_B_DM MEM_B_DQS0 MEM_B_DQS0 MEM_B_DQS1 MEM_B_DQS1 MEM_B_DQS2 MEM_B_DQS2 MEM_B_DQS3 MEM_B_DQS3 MEM_B_DQS4 MEM_B_DQS4 MEM_B_DQS5 MEM_B_DQS5 MEM_B_DQS6 MEM_B_DQS6 MEM_B_DQS7 MEM_B_DQS7 MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N 15 28 15 28 TABLE_PHYSICAL_RULE_ITEM MEM_70D * =70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF MEM_70D_VDD * =70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF SPACING_RULE_SET LAYER TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_HEAD D LINE-TO-LINE SPACING WEIGHT =4:1_SPACING ? TABLE_SPACING_RULE_ITEM MEM_CLK2MEM * TABLE_SPACING_RULE_ITEM MEM_CTRL2CTRL * =2:1_SPACING ? 15 28 15 28 15 28 15 28 15 28 D 15 28 15 28 15 28 TABLE_SPACING_RULE_ITEM MEM_CTRL2MEM * =2.5:1_SPACING ? MEM_CMD2CMD * =1.5:1_SPACING ? TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM MEM_CMD2MEM * =3:1_SPACING ? TABLE_SPACING_RULE_ITEM MEM_DATA2DATA * =1.5:1_SPACING ? TABLE_SPACING_RULE_ITEM MEM_DATA2MEM * =3:1_SPACING ? MEM_DQS2MEM * =3:1_SPACING ? TABLE_SPACING_RULE_ITEM 15 28 15 28 15 28 15 28 15 28 15 28 15 28 15 28 TABLE_SPACING_RULE_ITEM MEM_2OTHER * 25 MIL ? Memory Bus Spacing Group Assignments TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET TABLE_SPACING_ASSIGNMENT_ITEM MEM_CLK MEM_CLK * MEM_CLK2MEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CMD MEM_CLK * MEM_CMD2MEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CLK MEM_CTRL * MEM_CLK2MEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CMD MEM_CTRL * MEM_CMD2MEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CLK MEM_CMD * MEM_CLK2MEM MEM_CLK MEM_DATA * MEM_CLK2MEM MEM_CLK MEM_DQS * MEM_CLK2MEM MEM_CMD MEM_CMD * MEM_CMD2CMD MEM_CMD MEM_DATA * MEM_CMD2MEM MEM_CMD MEM_DQS * MEM_CMD2MEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_HEAD C NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET MEM_CTRL MEM_CLK * MEM_CTRL2MEM TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET MEM_DATA MEM_CLK * MEM_DATA2MEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CTRL MEM_CTRL * MEM_CTRL2CTRL MEM_CTRL MEM_CMD * MEM_CTRL2MEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_DATA MEM_CTRL * MEM_DATA2MEM MEM_DATA MEM_CMD * MEM_DATA2MEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CTRL MEM_DATA * MEM_CTRL2MEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_DATA MEM_DATA * MEM_DATA2DATA TABLE_SPACING_ASSIGNMENT_ITEM MEM_CTRL MEM_DQS * MEM_CTRL2MEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_DATA MEM_DQS * MEM_DATA2MEM TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET MEM_DQS MEM_CLK * MEM_DQS2MEM MEM_DQS MEM_CTRL * MEM_DQS2MEM TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET MEM_CLK * * MEM_2OTHER MEM_CTRL * * MEM_2OTHER TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CMD * MEM_DQS2MEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CMD * * MEM_2OTHER TABLE_SPACING_ASSIGNMENT_ITEM MEM_DQS MEM_DATA * MEM_DQS2MEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_DATA * * MEM_DQS * MEM_DQS2MEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_DQS * * MEM_2OTHER Need to support MEM_*-style wildcards! DDR2: B DQ signals should be matched within 20 ps of associated DQS pair DQS intra-pair matching should be within ps, no inter-pair matching requirement All DQS pairs should be matched within 100 ps of clocks CLK intra-pair matching should be within ps, inter-pair matching should be within 140 ps A/BA/cmd signals should be matched within 75 ps, no CLK matching requirement All memory signals maximum length is 1.005 ps CLK minimum length is 594 ps (lengths include substrate) DQ/A/BA/cmd signal spacing is 3x dielectric, DQS/CLK is 4x dielectric DDR3: DQ signals should be matched within ps of associated DQS pair DQS intra-pair matching should be within ps, inter-pair matching shoulw be within 180 ps No DQS to clock matching requirement CLK intra-pair matching should be within ps, inter-pair matching should be within ps A/BA/cmd signals should be matched within ps of CLK pairs All memory signals maximum length is 1.005 ps CLK minimum length is 594 ps (lengths include substrate) DQ/A/BA/cmd signal spacing is 3x dielectric, DQS/CLK is 4x dielectric SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.3 SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Section 6.2 MCP MEM COMP Signal Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM MCP_MEM_COMP * Y MIL MIL =STANDARD =STANDARD =STANDARD TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM MCP_MEM_COMP * MIL 15 28 15 28 15 28 15 28 15 28 15 28 15 28 15 28 15 28 15 28 15 28 C 15 28 15 28 15 28 15 28 15 28 15 28 15 28 15 28 15 28 15 28 15 29 15 29 15 29 15 29 15 29 MEM_2OTHER TABLE_SPACING_ASSIGNMENT_ITEM MEM_DQS 15 28 TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_DQS 15 28 TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM NET_SPACING_TYPE1 15 28 ? SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.3.4 A MCP_MEM_COMP MCP_MEM_COMP MCP_MEM_COMP MCP_MEM_COMP MCP_MEM_COMP MCP_MEM_COMP MCP_MEM_COMP_VDD MCP_MEM_COMP_GND 15 29 15 29 15 29 15 29 15 29 15 29 15 29 15 29 15 29 B 15 29 15 29 15 29 15 29 15 29 15 29 15 29 15 29 15 29 15 29 15 29 15 29 15 29 15 29 15 29 15 29 15 29 15 29 15 29 15 29 15 29 15 29 15 29 Memory Constraints 15 29 15 29 SYNC_MASTER=MUXGFX SYNC_DATE=02/18/2008 15 29 NOTICE OF PROPRIETARY PROPERTY 15 29 15 29 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING 16 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE 16 II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC SCALE SHT NONE REV 051-7892 A.0.0 OF 89 97 A PCI-Express TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP PCIE_90D * =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF 13.1 MM =90_OHM_DIFF =90_OHM_DIFF NET_TYPE ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM CLK_PCIE_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF PEG_R2D TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING TABLE_SPACING_RULE_HEAD WEIGHT SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM PCIE * =3X_DIELECTRIC PEG_D2R TABLE_SPACING_RULE_ITEM ? PCIE TOP,BOTTOM =4X_DIELECTRIC ? TABLE_SPACING_RULE_ITEM CLK_PCIE D * 20 MIL ? PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PEG_R2D_P PEG_R2D_N PEG_R2D_C_P PEG_R2D_C_N PEG_D2R_P PEG_D2R_N PEG_D2R_C_P PEG_D2R_C_N PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE PCIE PCIE PCIE PCIE PCIE PCIE_MINI_R2D_P PCIE_MINI_R2D_N PCIE_MINI_R2D_C_P PCIE_MINI_R2D_C_N PCIE_MINI_D2R_P PCIE_MINI_D2R_N PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE_FW_R2D_P PCIE_FW_R2D_N PCIE_FW_R2D_C_P PCIE_FW_R2D_C_N PCIE_FW_D2R_P PCIE_FW_D2R_N PCIE_FW_D2R_C_P PCIE_FW_D2R_C_N PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE PCIE PCIE PCIE PCIE PCIE PCIE_EXCARD_R2D_P PCIE_EXCARD_R2D_N TP_PCIE_EXCARD_R2D_C_P TP_PCIE_EXCARD_R2D_C_N TP_PCIE_EXCARD_D2R_P TP_PCIE_EXCARD_D2R_N CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE MCP_PEX_COMP PEG_CLK100M_P PEG_CLK100M_N PCIE_CLK100M_MINI_P PCIE_CLK100M_MINI_N PCIE_CLK100M_FW_P PCIE_CLK100M_FW_N TP_PCIE_CLK100M_EXCARD_P TP_PCIE_CLK100M_EXCARD_N MCP_PEX_CLK_COMP CRT CRT CRT CRT_SYNC CRT_SYNC MCP_DAC_COMP MCP_DAC_COMP NC_CRT_IG_R_C_PR NC_CRT_IG_G_Y_Y NC_CRT_IG_B_COMP_PB NC_CRT_IG_HSYNC NC_CRT_IG_VSYNC NC_MCP_TV_DAC_RSET NC_MCP_TV_DAC_VREF 71 71 71 71 71 71 71 71 D TABLE_SPACING_RULE_ITEM MCP_PEX_COMP * MIL ? SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.4 PCIE_MINI_R2D Analog Video Signal Constraints PCIE_MINI_D2R TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP CRT_50S * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD 31 96 31 96 17 31 17 31 17 31 17 31 TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING TABLE_SPACING_ASSIGNMENT_HEAD WEIGHT NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE CRT * =4:1_SPACING PCIE_FW_R2D SPACING_RULE_SET TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM ? CRT CRT * CRT_2CRT PCIE_FW_D2R TABLE_SPACING_RULE_ITEM CRT_2CRT * =STANDARD ? TABLE_SPACING_RULE_ITEM CRT_2CLK * 50 MIL ? 36 36 17 36 17 36 17 36 17 36 36 36 TABLE_SPACING_RULE_ITEM CRT_2SWITCHER * 250 MIL ? TABLE_SPACING_RULE_ITEM CRT_SYNC * 16 MIL ? MCP_DAC_COMP * =2:1_SPACING ? PCIE_EXCARD_R2D TABLE_SPACING_RULE_ITEM C CRT signal single-ended impedence varies by location: - 37.5-ohm from MCP to first termination resistor - 50-ohm from first to second termination resistor - 75-ohm from output of three-pole filter to connector (if possible) R/G/B signals should be matched as close as possible and < 10 inches SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Sections 2.5.1 & 2.5.2 PCIE_EXCARD_D2R Digital Video Signal Constraints MCP_PE2_REFCLK MCP_PE0_REFCLK MCP_PE1_REFCLK TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP MCP_PE3_REFCLK DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM DP_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF LVDS_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF MCP_DV_COMP * Y 20 MIL 20 MIL =STANDARD =STANDARD =STANDARD MCP_PEX_CLK_COMP 96 96 17 17 17 17 17 71 17 71 17 31 17 31 C 17 36 17 36 17 17 17 TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING TABLE_SPACING_RULE_HEAD WEIGHT SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM DISPLAYPORT * =3x_DIELECTRIC TABLE_SPACING_RULE_ITEM ? DISPLAYPORT TOP,BOTTOM =4x_DIELECTRIC ? TABLE_SPACING_RULE_ITEM LVDS * =3x_DIELECTRIC TABLE_SPACING_RULE_ITEM ? LVDS TOP,BOTTOM =4x_DIELECTRIC SATA Interface Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP SATA_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LINE-TO-LINE SPACING WEIGHT SATA LAYER * =4x_DIELECTRIC ? SATA_TERMP * MIL ? TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT =3x_DIELECTRIC ? TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM SATA TOP,BOTTOM CRT_50S CRT_50S CRT_50S CRT_50S CRT_50S TMDS_IG_TXC TMDS_IG_TXC TMDS_IG_TXD TMDS_IG_TXD DP_100D DP_100D DP_100D DP_100D DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT TMDS_IG_TXC_P TMDS_IG_TXC_N TMDS_IG_TXD_P TMDS_IG_TXD_N DP_ML DP_ML DP_AUX_CH DP_AUX_CH DP_100D DP_100D DP_100D DP_100D DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DP_IG_ML_P DP_IG_ML_N DP_IG_AUX_CH_P DP_IG_AUX_CH_N MCP_HDMI_RSET MCP_HDMI_VPROBE MCP_DV_COMP MCP_DV_COMP LVDS_IG_A_CLK LVDS_IG_A_CLK LVDS_IG_A_DATA LVDS_IG_A_DATA LVDS_IG_A_DATA3 LVDS_IG_A_DATA3 LVDS_IG_B_CLK LVDS_IG_B_CLK LVDS_IG_B_DATA LVDS_IG_B_DATA LVDS_IG_B_DATA3 LVDS_IG_B_DATA3 LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D MCP_IFPAB_RSET MCP_IFPAB_VPROBE MCP_DV_COMP SATA_HDD_R2D SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D 18 25 18 25 18 25 18 25 18 25 18 25 18 25 ? LVDS intra-pair matching should be mils Pairs should be within 100 mils of clock length DisplayPort/TMDS intra-pair matching should be ps Inter-pair matching should be within 150 ps DIsplayPort AUX CH intra-pair matching should be ps No relationship to other signals Max length of LVDS/DisplayPort/TMDS traces: 12 inches SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Sections 2.5.3 & 2.5.4 B CRT_RED CRT_GREEN CRT_BLUE CRT_SYNC CRT_SYNC MCP_DAC_RSET MCP_DAC_VREF TABLE_SPACING_RULE_ITEM SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.7.1 SATA_HDD_D2R SATA_ODD_R2D SATA_ODD_D2R A MCP_SATA_TERMP MCP_HDMI_RSET MCP_HDMI_VPROBE LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS_IG_A_CLK_P LVDS_IG_A_CLK_N LVDS_IG_A_DATA_P LVDS_IG_A_DATA_N NC_LVDS_IG_A_DATAP NC_LVDS_IG_A_DATAN NC_LVDS_IG_B_CLKP NC_LVDS_IG_B_CLKN LVDS_IG_B_DATA_P LVDS_IG_B_DATA_N NC_LVDS_IG_B_DATAP NC_LVDS_IG_B_DATAN MCP_IFPAB_RSET MCP_IFPAB_VPROBE SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA_TERMP SATA_HDD_R2D_C_P SATA_HDD_R2D_C_N SATA_HDD_R2D_P SATA_HDD_R2D_N SATA_HDD_D2R_P SATA_HDD_D2R_N SATA_HDD_D2R_C_P SATA_HDD_D2R_C_N SATA_ODD_R2D_C_P SATA_ODD_R2D_C_N SATA_ODD_R2D_P SATA_ODD_R2D_N SATA_ODD_D2R_P SATA_ODD_D2R_N SATA_ODD_D2R_C_P SATA_ODD_D2R_C_N MCP_SATA_TERMP 81 81 18 81 18 81 18 25 18 25 18 84 18 84 B 18 84 18 84 18 18 18 18 18 84 18 84 18 18 18 25 18 25 20 39 20 39 39 39 20 39 20 39 39 39 20 39 20 39 39 MCP Constraints 39 20 39 SYNC_MASTER=MUXGFX SYNC_DATE=02/18/2008 20 39 NOTICE OF PROPRIETARY PROPERTY 39 39 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING 20 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC SCALE SHT NONE REV 051-7892 A.0.0 OF 90 97 A PCI Bus Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP PCI_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD NET_TYPE ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM CLK_PCI_55S * SPACING_RULE_SET LAYER =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD TABLE_SPACING_RULE_HEAD LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM PCI * =STANDARD ? CLK_PCI * MIL ? TABLE_SPACING_RULE_ITEM D SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.8 LPC Bus Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP LPC_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD CLK_LPC_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LINE-TO-LINE SPACING WEIGHT LPC LAYER * MIL ? CLK_LPC * MIL ? TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM MCP_DEBUG PCI_AD PCI_AD24 PCI_AD PCI_AD PCI_C_BE_L PCI_CNTL PCI_CNTL PCI_CNTL PCI_CNTL PCI_CNTL PCI_CNTL PCI_CNTL PCI_REQ0_L PCI_GNT0_L PCI_REQ1_L PCI_GNT1_L PCI_INTW_L PCI_INTX_L PCI_INTY_L PCI_INTZ_L PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI MCP_DEBUG PCI_AD PCI_AD PCI_AD PCI_PAR PCI_C_BE_L PCI_IRDY_L PCI_DEVSEL_L PCI_PERR_L PCI_SERR_L PCI_STOP_L PCI_TRDY_L PCI_FRAME_L PCI_REQ0_L PCI_GNT0_L PCI_REQ1_L PCI_GNT1_L PCI_INTW_L PCI_INTX_L PCI_INTY_L PCI_INTZ_L MCP_PCI_CLK2 CLK_PCI_55S CLK_PCI_55S CLK_PCI CLK_PCI PCI_CLK33M_MCP_R PCI_CLK33M_MCP LPC_AD LPC_FRAME_L LPC_RESET_L LPC_55S LPC_55S LPC_55S LPC LPC LPC LPC_AD LPC_FRAME_L LPC_RESET_L MCP_LPC_CLK0 CLK_LPC_55S CLK_LPC_55S CLK_LPC_55S CLK_LPC CLK_LPC CLK_LPC LPC_CLK33M_SMC_R LPC_CLK33M_SMC LPC_CLK33M_LPCPLUS USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB_EXTA_P USB_EXTA_N USB_EXTA_MUXED_P USB_EXTA_MUXED_N NC_USB_MINIP NC_USB_MININ NC_USB_EXTDP NC_USB_EXTDN USB_CAMERA_P USB_CAMERA_N USB_BT_P USB_BT_N USB_TPAD_P USB_TPAD_N USB_IR_P USB_IR_N USB_EXTB_P USB_EXTB_N NC_USB_EXCARDP NC_USB_EXCARDN NC_USB_EXTCP NC_USB_EXTCN SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.9.1 USB 2.0 Interface Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 13 19 D 19 19 19 19 19 42 44 84 19 42 44 84 19 26 84 TABLE_PHYSICAL_RULE_ITEM MCP_USB_RBIAS * =STANDARD MIL MIL =STANDARD =STANDARD =STANDARD USB_90D * =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF SPACING_RULE_SET LAYER TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_HEAD LINE-TO-LINE SPACING WEIGHT =2x_DIELECTRIC ? LAYER LINE-TO-LINE SPACING WEIGHT =4x_DIELECTRIC ? TABLE_SPACING_RULE_ITEM USB C * USB_EXTA TABLE_SPACING_RULE_HEAD SPACING_RULE_SET TABLE_SPACING_RULE_ITEM USB TOP,BOTTOM SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.10.1 USB_MINI SMBus Interface Constraints USB_EXTD TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP SMB_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD USB_CAMERA TABLE_PHYSICAL_RULE_ITEM USB_BT TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT USB_TPAD TABLE_SPACING_RULE_ITEM SMB * =2x_DIELECTRIC ? USB_IR SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.11.1 USB_EXTB HD Audio Interface Constraints USB_EXCARD TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH =55_OHM_SE =55_OHM_SE MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM HDA_55S * =55_OHM_SE =55_OHM_SE =STANDARD USB_EXTC =STANDARD 19 26 26 42 26 44 20 40 20 40 C 20 20 20 20 20 31 20 31 20 31 20 31 20 50 20 50 20 41 20 41 20 40 20 40 20 20 20 20 TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT MCP_USB_RBIAS_GND MCP_USB_RBIAS MCP_USB_RBIAS SMBUS_MCP_0_CLK SMBUS_MCP_0_DATA SMBUS_MCP_1_CLK SMBUS_MCP_1_DATA SMB_55S SMB_55S SMB_55S SMB_55S SMB SMB SMB SMB SMBUS_MCP_0_CLK SMBUS_MCP_0_DATA SMBUS_MCP_1_CLK SMBUS_MCP_1_DATA HDA_BIT_CLK HDA_55S HDA_55S HDA_55S HDA_55S HDA_55S HDA_55S HDA_55S HDA_55S HDA_55S HDA_55S HDA HDA HDA HDA HDA HDA HDA HDA HDA HDA HDA_BIT_CLK HDA_BIT_CLK_R HDA_SYNC HDA_SYNC_R HDA_RST_R_L HDA_RST_L HDA_SDIN0 HDA_SDIN_CODEC HDA_SDOUT HDA_SDOUT_R MCP_HDA_COMP MCP_HDA_PULLDN_COMP 21 CLK_SLOW_55S CLK_SLOW_55S CLK_SLOW CLK_SLOW PM_CLK32K_SUSCLK_R PM_CLK32K_SUSCLK 26 42 SPI_55S SPI_55S SPI_55S SPI_55S SPI_55S SPI_55S SPI_55S SPI_55S SPI SPI SPI SPI SPI SPI SPI SPI SPI_CLK_R SPI_CLK SPI_MOSI_R SPI_MOSI SPI_MISO SPI_MISO_R SPI_CS0_R_L SPI_CS0_L 20 TABLE_SPACING_RULE_ITEM HDA * =2x_DIELECTRIC ? MCP_HDA_COMP * MIL ? TABLE_SPACING_RULE_ITEM SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.12.1 B SIO Signal Constraints HDA_SYNC TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM CLK_SLOW_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD HDA_RST_L =STANDARD HDA_SDIN0 TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT MIL ? TABLE_SPACING_RULE_ITEM CLK_SLOW * HDA_SDOUT SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.13 MCP_HDA_PULLDN_COMP SPI Interface Constraints MCP_SUS_CLK TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP SPI_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD SPI_CLK TABLE_PHYSICAL_RULE_ITEM SPI_MOSI TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT MIL ? SPI_MISO TABLE_SPACING_RULE_ITEM SPI * SPI_CS0 SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.14 13 21 28 29 45 13 21 28 29 45 21 45 60 85 21 45 60 85 21 55 B 21 21 55 21 21 21 55 21 55 21 55 21 21 26 21 44 54 21 44 54 21 44 54 21 44 MCP Constraints A SYNC_MASTER=MUXGFX SYNC_DATE=02/18/2008 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC SCALE SHT NONE REV 051-7892 A.0.0 OF 91 97 A MCP RGMII (Ethernet) Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP MCP_MII_COMP * =STANDARD 7.5 MIL 7.5 MIL =STANDARD =STANDARD =STANDARD NET_TYPE ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM ENET_MII_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD MCP_MII_COMP MCP_MII_COMP MCP_CLK25M_BUF0 ENET_MII_55S ENET_MII_55S MCP_BUF0_CLK MCP_BUF0_CLK MCP_CLK25M_BUF0_R RTL8211_CLK25M_CKXTAL1 ENET_INTR_L ENET_MDIO ENET_MDC ENET_PWRDWN_L ENET_MII_55S ENET_MII_55S ENET_MII_55S ENET_MII_55S ENET_MII ENET_MII ENET_MII ENET_MII ENET_INTR_L ENET_MDIO ENET_MDC ENET_PWRDWN_L ENET_RXD ENET_RXD_STRAP ENET_RXD ENET_MII_55S ENET_MII_55S ENET_MII_55S ENET_MII_55S ENET_MII_55S ENET_MII_55S ENET_MII ENET_MII ENET_MII ENET_MII ENET_MII ENET_MII ENET_CLK125M_RXCLK_R ENET_CLK125M_RXCLK ENET_RXD_R ENET_RXD ENET_RXD ENET_RX_CTRL ENET_TXCLK ENET_TXD0 ENET_TXD ENET_TXD ENET_MII_55S ENET_MII_55S ENET_MII_55S ENET_MII_55S ENET_MII ENET_MII ENET_MII ENET_MII ENET_CLK125M_TXCLK ENET_TXD ENET_TXD ENET_TX_CTRL ENET_MII_55S ENET_MII ENET_RESET_L TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING MCP_MII_COMP_VDD MCP_MII_COMP_GND MCP_MII_COMP MCP_MII_COMP WEIGHT 18 18 18 34 33 34 TABLE_SPACING_RULE_ITEM MCP_BUF0_CLK * =3:1_SPACING ? ENET_MII * 12 MIL ? TABLE_SPACING_RULE_ITEM D SOURCE: MCP73 Interface DG (DG-02974-001_v01), Sections 2.7.2 & 2.7.4 88E1116R (Ethernet PHY) Constraints ENET_RXCLK TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP ENET_MDI_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF TABLE_PHYSICAL_RULE_ITEM 18 33 18 33 D 33 18 33 33 18 33 18 33 18 33 TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT 25 MIL ? TABLE_SPACING_RULE_ITEM ENET_MDI * SOURCE: MCP73 Interface DG (DG-02974-001_v01), Section 2.7.4 ENET_MDI ENET_MDI_100D ENET_MDI ENET_MDI_100D ENET_MDI ENET_MDI_P ENET_MDI_N 18 33 18 33 18 33 18 33 18 33 33 35 33 35 C C B B Ethernet Constraints A SYNC_MASTER=MUXGFX SYNC_DATE=02/18/2008 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC SCALE SHT NONE REV 051-7892 A.0.0 OF 92 97 A FireWire Interface Constraints FireWire Net Properties TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP FW_110D * =110_OHM_DIFF =110_OHM_DIFF =110_OHM_DIFF =110_OHM_DIFF =110_OHM_DIFF =110_OHM_DIFF NET_TYPE ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING TABLE_PHYSICAL_RULE_ITEM FW_P0_TPA FW_P0_TPA FW_P0_TPB FW_P0_TPB FW_P1_TPA FW_P1_TPA FW_P1_TPB FW_P1_TPB TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM FW_TP * =3:1_SPACING ? FW_110D FW_110D FW_110D FW_110D FW_110D FW_110D FW_110D FW_110D FW_TP FW_TP FW_TP FW_TP FW_TP FW_TP FW_TP FW_TP NC_FW0_TPAP NC_FW0_TPAN NC_FW0_TPBP NC_FW0_TPBN FW_PORT1_TPA_P FW_PORT1_TPA_N FW_PORT1_TPB_P FW_PORT1_TPB_N 36 38 36 38 36 38 36 38 36 38 36 38 36 38 36 38 D D Port Not Used SD CARD NET PROPERTIES NET_TYPE ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING SD CARD INTERFACE CONSTRAINTS TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP I32 SD_DATA SD_55S SD_INTERFACE I31 SD_DATA SD_55S SD_INTERFACE I30 SD_DATA SD_55S SD_INTERFACE I29 SD_DATA SD_55S SD_INTERFACE I28 SD_DATA SD_55S SD_INTERFACE I27 SD_DATA SD_55S SD_INTERFACE I26 SD_DATA SD_55S SD_INTERFACE I25 SD_DATA SD_55S SD_INTERFACE I23 SD_CLK SD_55S SD_INTERFACE I24 SD_CMD SD_55S SD_INTERFACE TABLE_PHYSICAL_RULE_ITEM SD_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM SD_INTERFACE * =3X_DIELECTRIC ? SD_D SD_D SD_D SD_D SD_D SD_D SD_D SD_D 32 32 32 32 32 32 32 32 SD_CLK SD_CMD 32 32 C C B B FireWire Constraints A SYNC_MASTER=MUXGFX SYNC_DATE=02/18/2008 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC SCALE SHT NONE REV 051-7892 A.0.0 OF 93 97 A SMC SMBus Net Properties TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 1TO1_DIFFPAIR * =STANDARD =STANDARD =STANDARD =STANDARD 0.1 MM 0.1 MM NET_TYPE ELECTRICAL_CONSTRAINT_SET SPACING PHYSICAL TABLE_PHYSICAL_RULE_ITEM SMBUS_SMC_A_S3_SCL SMBUS_SMC_A_S3_SDA SMBUS_SMC_B_S0_SCL SMBUS_SMC_B_S0_SDA SMBUS_SMC_0_S0_SCL SMBUS_SMC_0_S0_SDA SMBUS_SMC_BSA_SCL SMBUS_SMC_BSA_SDA SMBUS_SMC_MGMT_SCL SMBUS_SMC_MGMT_SDA D SMB_55S SMB_55S SMB_55S SMB_55S SMB_55S SMB_55S SMB_55S SMB_55S SMB_55S SMB_55S SMB SMB SMB SMB SMB SMB SMB SMB SMB SMB SMBUS_SMC_A_S3_SCL SMBUS_SMC_A_S3_SDA SMBUS_SMC_B_S0_SCL SMBUS_SMC_B_S0_SDA SMBUS_SMC_0_S0_SCL SMBUS_SMC_0_S0_SDA SMBUS_SMC_BSA_SCL SMBUS_SMC_BSA_SDA SMBUS_SMC_MGMT_SCL SMBUS_SMC_MGMT_SDA 31 42 45 51 31 42 45 51 42 45 48 42 45 48 42 45 48 53 78 42 45 48 53 78 42 45 61 62 42 45 61 62 D 27 39 42 45 27 39 42 45 SMBus Charger Net Properties NET_TYPE ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING CHGR_CSI 1TO1_DIFFPAIR 1TO1_DIFFPAIR CHGR_CSI_P CHGR_CSI_N CHGR_CSO 1TO1_DIFFPAIR 1TO1_DIFFPAIR CHGR_CSO_P CHGR_CSO_N 62 62 62 62 C C B B SMC Constraints A SYNC_MASTER=MUXGFX SYNC_DATE=02/18/2008 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC SCALE SHT NONE REV 051-7892 A.0.0 OF 94 97 A GDDR3 Frame Buffer Signal Constraints GDDR3 FB A/B Net Properties GDDR3 FB C/D Net Properties TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET ALLOW ROUTE ON LAYER? LAYER MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM GDDR3_40R55SE * =55_OHM_SE =40_OHM_SE 0.095 MM 12.7 MM =STANDARD =STANDARD GDDR3_40SE * =40_OHM_SE =40_OHM_SE 0.095 MM =40_OHM_SE =STANDARD =STANDARD NET_TYPE ELECTRICAL_CONSTRAINT_SET GDDR3_CLK GDDR3_CLK GDDR3_CLK GDDR3_CLK FB_A_CLK_P FB_A_CLK_N FB_A_CLK_P FB_A_CLK_N FB_AB_CMD FB_AB_CMD FB_AB_CMD FB_AB_CMD FB_AB_CMD FB_AB_CMD FB_AB_CMD_PD FB_AB_CMD_PD FB_AB_CS0 FB_AB_CMD_PD GDDR3_40R55SE GDDR3_40R55SE GDDR3_40R55SE GDDR3_40R55SE GDDR3_40R55SE GDDR3_40R55SE GDDR3_40R55SE GDDR3_40R55SE GDDR3_40R55SE GDDR3_40R55SE GDDR3_CMD GDDR3_CMD GDDR3_CMD GDDR3_CMD GDDR3_CMD GDDR3_CMD GDDR3_CMD GDDR3_CMD GDDR3_CMD GDDR3_CMD FB_A_MA FB_A_MA FB_A_BA FB_A_RAS_L FB_A_CAS_L FB_A_WE_L FB_A_UCKE FB_A_LCKE FB_A_LCS0_L FB_A_DRAM_RST FB_A_CMD FB_B_CMD GDDR3_40SE GDDR3_40SE GDDR3_CMD GDDR3_CMD FB_A_LMA FB_A_UMA FB_A_WDQS0 FB_A_WDQS1 FB_A_WDQS2 FB_A_WDQS3 GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_DQS GDDR3_DQS GDDR3_DQS GDDR3_DQS FB_A_WDQS FB_A_WDQS FB_A_WDQS FB_A_WDQS FB_A_RDQS0 FB_A_RDQS1 FB_A_RDQS2 FB_A_RDQS3 GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_DQS GDDR3_DQS GDDR3_DQS GDDR3_DQS FB_A_RDQS FB_A_RDQS FB_A_RDQS FB_A_RDQS FB_A_DQ_BYTE0 FB_A_DQ_BYTE1 FB_A_DQ_BYTE2 FB_A_DQ_BYTE3 GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_DATA GDDR3_DATA GDDR3_DATA GDDR3_DATA FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQM0 FB_A_DQM1 FB_A_DQM2 FB_A_DQM3 GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_DATA GDDR3_DATA GDDR3_DATA GDDR3_DATA FB_A_DQM_L FB_A_DQM_L FB_A_DQM_L FB_A_DQM_L FB_B_WDQS0 FB_B_WDQS1 FB_B_WDQS2 FB_B_WDQS3 GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_DQS GDDR3_DQS GDDR3_DQS GDDR3_DQS FB_A_WDQS FB_A_WDQS FB_A_WDQS FB_A_WDQS FB_B_RDQS0 FB_B_RDQS1 FB_B_RDQS2 FB_B_RDQS3 GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_DQS GDDR3_DQS GDDR3_DQS GDDR3_DQS FB_A_RDQS FB_A_RDQS FB_A_RDQS FB_A_RDQS FB_B_DQ_BYTE0 FB_B_DQ_BYTE1 FB_B_DQ_BYTE2 FB_B_DQ_BYTE3 GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_DATA GDDR3_DATA GDDR3_DATA GDDR3_DATA FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_B_DQM0 FB_B_DQM1 FB_B_DQM2 FB_B_DQM3 GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_DATA GDDR3_DATA GDDR3_DATA GDDR3_DATA FB_A_DQM_L FB_A_DQM_L FB_A_DQM_L FB_A_DQM_L TABLE_PHYSICAL_RULE_ITEM GDDR3_80D * =80_OHM_DIFF =80_OHM_DIFF 0.095 MM =80_OHM_DIFF =80_OHM_DIFF FB_B_CLK_P =80_OHM_DIFF TABLE_SPACING_RULE_HEAD SPACING_RULE_SET D LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM GDDR3_CLK * =2.5:1_SPACING ? TABLE_SPACING_RULE_ITEM GDDR3_CMD * =2.5:1_SPACING ? GDDR3_DATA * =2.5:1_SPACING ? GDDR3_DQS * =2.5:1_SPACING ? TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM I205 From T18 MXM: Digital Video Signal Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET ALLOW ROUTE ON LAYER? LAYER MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM C DP_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF LVDS_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF NET_TYPE ELECTRICAL_CONSTRAINT_SET SPACING GDDR3_80D GDDR3_80D GDDR3_80D GDDR3_80D FB_A_CLK_P TABLE_PHYSICAL_RULE_ITEM PHYSICAL GDDR3_CLK GDDR3_CLK GDDR3_CLK GDDR3_CLK FB_B_CLK_P FB_B_CLK_N FB_B_CLK_P FB_B_CLK_N FB_CD_CMD FB_CD_CMD FB_CD_CMD FB_CD_CMD FB_CD_CMD FB_CD_CMD FB_CD_CMD_PD FB_CD_CMD_PD FB_CD_CS0 FB_CD_CMD_PD GDDR3_40R55SE GDDR3_40R55SE GDDR3_40R55SE GDDR3_40R55SE GDDR3_40R55SE GDDR3_40R55SE GDDR3_40R55SE GDDR3_40R55SE GDDR3_40R55SE GDDR3_40R55SE GDDR3_CMD GDDR3_CMD GDDR3_CMD GDDR3_CMD GDDR3_CMD GDDR3_CMD GDDR3_CMD GDDR3_CMD GDDR3_CMD GDDR3_CMD FB_B_MA FB_B_MA FB_B_BA FB_B_RAS_L FB_B_CAS_L FB_B_WE_L FB_B_UCKE FB_B_LCKE FB_B_LCS0_L FB_B_DRAM_RST FB_C_CMD FB_D_CMD GDDR3_40SE GDDR3_40SE GDDR3_CMD GDDR3_CMD FB_B_LMA FB_B_UMA FB_C_WDQS0 FB_C_WDQS1 FB_C_WDQS2 FB_C_WDQS3 GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_DQS GDDR3_DQS GDDR3_DQS GDDR3_DQS FB_B_WDQS FB_B_WDQS FB_B_WDQS FB_B_WDQS FB_C_RDQS0 FB_C_RDQS1 FB_C_RDQS2 FB_C_RDQS3 GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_DQS GDDR3_DQS GDDR3_DQS GDDR3_DQS FB_B_RDQS FB_B_RDQS FB_B_RDQS FB_B_RDQS FB_C_DQ_BYTE0 FB_C_DQ_BYTE1 FB_C_DQ_BYTE2 FB_C_DQ_BYTE3 GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_DATA GDDR3_DATA GDDR3_DATA GDDR3_DATA FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_C_DQM0 FB_C_DQM1 FB_C_DQM2 FB_C_DQM3 GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_DATA GDDR3_DATA GDDR3_DATA GDDR3_DATA FB_B_DQM_L FB_B_DQM_L FB_B_DQM_L FB_B_DQM_L FB_D_WDQS0 FB_D_WDQS1 FB_D_WDQS2 FB_D_WDQS3 GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_DQS GDDR3_DQS GDDR3_DQS GDDR3_DQS FB_B_WDQS FB_B_WDQS FB_B_WDQS FB_B_WDQS FB_D_RDQS0 FB_D_RDQS1 FB_D_RDQS2 FB_D_RDQS3 GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_DQS GDDR3_DQS GDDR3_DQS GDDR3_DQS FB_B_RDQS FB_B_RDQS FB_B_RDQS FB_B_RDQS FB_D_DQ_BYTE0 FB_D_DQ_BYTE1 FB_D_DQ_BYTE2 FB_D_DQ_BYTE3 GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_DATA GDDR3_DATA GDDR3_DATA GDDR3_DATA FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_D_DQM0 FB_D_DQM1 FB_D_DQM2 FB_D_DQM3 GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_DATA GDDR3_DATA GDDR3_DATA GDDR3_DATA FB_B_DQM_L FB_B_DQM_L FB_B_DQM_L FB_B_DQM_L 73 74 FB_D_CLK_P 73 74 73 74 73 74 73 74 73 74 73 74 73 74 73 74 I204 73 74 73 74 73 74 73 74 73 74 73 74 73 74 73 74 73 74 73 74 73 74 73 74 73 74 73 74 73 74 73 74 73 74 73 74 73 74 SPACING GDDR3_80D GDDR3_80D GDDR3_80D GDDR3_80D FB_C_CLK_P 73 74 PHYSICAL 73 75 73 75 73 75 73 75 73 75 73 75 73 75 D 73 75 73 75 73 75 73 75 73 75 73 75 73 75 73 75 73 75 73 75 73 75 73 75 73 75 73 75 73 75 73 75 73 75 73 75 73 75 73 75 73 75 C 73 75 TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING TABLE_SPACING_RULE_HEAD WEIGHT SPACING_RULE_SET LAYER LINE-TO-LINE SPACING * =3x_DIELECTRIC ? LVDS * =3x_DIELECTRIC ? 73 74 73 74 73 74 73 75 73 75 73 75 73 75 WEIGHT TABLE_SPACING_RULE_ITEM DISPLAYPORT 73 74 TABLE_SPACING_RULE_ITEM DISPLAYPORT TOP,BOTTOM =4x_DIELECTRIC ? LVDS TOP,BOTTOM =4x_DIELECTRIC ? TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM LVDS intra-pair matching should be mils Pairs should be within 100 mils of clock length DisplayPort/TMDS intra-pair matching should be ps Inter-pair matching should be within 150 ps DIsplayPort AUX CH intra-pair matching should be ps No relationship to other signals Max length of LVDS/DisplayPort/TMDS traces: 12 inches SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Sections 2.5.3 & 2.5.4 MUXGFX Net Properties 73 74 73 74 73 74 73 74 73 74 73 74 73 74 73 74 73 74 73 74 73 74 73 74 73 75 73 75 73 75 73 75 73 75 73 75 73 75 73 75 73 75 73 75 73 75 73 75 G96 Net Properties NET_TYPE ELECTRICAL_CONSTRAINT_SET I148 I149 B I199 I198 I152 I153 I201 I200 LVDS_A_CLK LVDS_A_CLK LVDS_A_DATA LVDS_A_DATA NET_TYPE PHYSICAL SPACING LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS LVDS LVDS LVDS ELECTRICAL_CONSTRAINT_SET LVDS_A_CLK_P LVDS_A_CLK_N 81 84 LVDS_B_CLK LVDS_B_CLK LVDS_100D LVDS_100D LVDS LVDS LVDS_B_CLK_P LVDS_B_CLK_N LVDS_B_DATA LVDS_B_DATA LVDS_100D LVDS_100D LVDS LVDS LVDS_B_DATA_P LVDS_B_DATA_N 81 84 81 84 81 84 81 84 I142 81 84 I144 LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D I183 I182 I184 I185 I190 I191 I192 I193 I194 I195 I196 I197 LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS CK505_CLK27MSS LVDS_EG_A_CLK LVDS_EG_A_CLK LVDS_EG_A_DATA LVDS_EG_A_DATA CLK_SLOW CLK_SLOW LVDS LVDS LVDS LVDS GPU_CLK27M GPU_CLK27M_SS LVDS_EG_A_CLK_P LVDS_EG_A_CLK_N LVDS_EG_A_DATA_P LVDS_EG_A_DATA_N LVDS_EG_B_DATA LVDS_EG_B_DATA LVDS_100D LVDS_100D LVDS LVDS LVDS_EG_B_DATA_P LVDS_EG_B_DATA_N DP_ML DP_ML DP_AUX_CH DP_AUX_CH DP_100D DP_100D DP_100D DP_100D DP_100D DP_100D 81 84 81 84 LVDS_CONN_A_CLK_F_P 80 LVDS_CONN_A_CLK_F_N 80 LVDS_CONN_B_CLK_F_P 80 LVDS_CONN_B_CLK_F_N 80 LVDS_CONN_A_CLK_P 80 81 LVDS_CONN_A_CLK_N 80 81 LVDS_CONN_A_DATA_P 80 LVDS_CONN_A_DATA_N 80 LVDS_CONN_B_CLK_P 80 81 LVDS_CONN_B_CLK_N 80 81 LVDS_CONN_B_DATA_P 80 LVDS_CONN_B_DATA_N 80 I145 I143 SPACING CLK_SLOW_55S CLK_SLOW_55S LVDS_100D LVDS_100D LVDS_100D LVDS_100D (CK505_DOT96) LVDS_A_DATA_P LVDS_A_DATA_N PHYSICAL I139 I138 DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DP_EG_ML_P DP_EG_ML_N DP_EG_AUX_CH_P DP_EG_AUX_CH_N DP_EG_AUX_CH_C_P DP_EG_AUX_CH_C_N 76 77 76 77 78 84 B 78 84 78 84 78 84 78 84 78 84 78 81 78 81 78 81 78 81 81 81 81 81 81 81 GPU (G96) CONSTRAINTS A I161 DP_ML I160 I155 DP_ML I157 I202 DP_ML I203 DP_100D DP_100D DP_100D DP_100D DP_100D DP_100D DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DP_ML_C_P DP_ML_C_N DP_ML_P DP_ML_P DP_ML_N DP_ML_N DP_ML_CONN_P DP_ML_CONN_N SYNC_MASTER=MUXGFX 82 82 SYNC_DATE=02/18/2008 NOTICE OF PROPRIETARY PROPERTY 81 82 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING 81 82 82 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE 82 II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART I159 I158 DP_AUX_CH DP_AUX_CH DP_100D DP_100D DISPLAYPORT DISPLAYPORT DP_AUX_CH_C_P DP_AUX_CH_C_N SIZE 81 82 DRAWING NUMBER D 81 82 APPLE INC SCALE SHT NONE REV 051-7892 A.0.0 OF 95 97 A TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET ALLOW ROUTE ON LAYER? LAYER MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP K19 Specific Net Properties K19 Specific Net Properties NET_TYPE NET_TYPE TABLE_PHYSICAL_RULE_ITEM SENSE_1TO1_55S * =55_OHM_SE =1:1_DIFFPAIR =55_OHM_SE =55_OHM_SE =1:1_DIFFPAIR ELECTRICAL_CONSTRAINT_SET =1:1_DIFFPAIR THERM_1TO1_55S * =55_OHM_SE =1:1_DIFFPAIR =55_OHM_SE =55_OHM_SE =1:1_DIFFPAIR =1:1_DIFFPAIR TABLE_PHYSICAL_RULE_ITEM DIFFPAIR * =1:1_DIFFPAIR =1:1_DIFFPAIR =1:1_DIFFPAIR =1:1_DIFFPAIR I146 I145 I144 I142 TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT I143 TABLE_SPACING_RULE_ITEM I140 D SENSE * =2:1_SPACING ? THERM * =2:1_SPACING ? I141 TABLE_SPACING_RULE_ITEM I139 SENSE_DIFFPAIR TABLE_SPACING_RULE_ITEM AUDIO * ? =2:1_SPACING TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING I124 WEIGHT I125 TABLE_SPACING_RULE_ITEM ENETCONN * 25 MILS CPUTHMSNS_D2_DP ? I127 CPU_THERMD_DP I126 TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING I128 WEIGHT I130 TABLE_SPACING_RULE_ITEM GND * =STANDARD ? PP1V8_MEM * =STANDARD ? GPUTHMSNS_D_DP I129 GPU_THERMD_DP TABLE_SPACING_RULE_ITEM I138 SPACING_RULE_SET LAYER LINE-TO-LINE SPACING MCPTHMSNS_D_DP I137 TABLE_SPACING_RULE_HEAD WEIGHT I135 MCP_THERMD_DP TABLE_SPACING_RULE_ITEM I136 GND_P2MM * 0.20 MM 1000 PWR_P2MM * 0.20 MM 1000 I156 TABLE_SPACING_RULE_ITEM SENSE_DIFFPAIR I157 ELECTRICAL_CONSTRAINT_SET SPACING PHYSICAL ENET_MDI_100D ENET_MDI_100D SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D SENSE_1TO1_55S SENSE_1TO1_55S TABLE_PHYSICAL_RULE_ITEM ENETCONN ENETCONN SATA SATA SATA SATA SATA SATA SATA SATA SENSE SENSE ENETCONN_P ENETCONN_N SATA_ODD_R2D_UF_P SATA_ODD_R2D_UF_N SATA_ODD_D2R_UF_P SATA_ODD_D2R_UF_N SATA_HDD_D2R_UF_P SATA_HDD_D2R_UF_N SATA_HDD_R2D_UF_P SATA_HDD_R2D_UF_N GFXIMVP6_VSEN_P GFXIMVP6_VSEN_N THERM_1TO1_55S THERM_1TO1_55S THERM_1TO1_55S THERM_1TO1_55S THERM_1TO1_55S THERM_1TO1_55S THERM_1TO1_55S THERM_1TO1_55S THERM_1TO1_55S THERM_1TO1_55S THERM_1TO1_55S THERM_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S THERM THERM THERM THERM THERM THERM THERM THERM THERM THERM THERM THERM SENSE SENSE CPUTHMSNS_D2_P CPUTHMSNS_D2_N CPU_THERMD_P CPU_THERMD_N GPUTHMSNS_D_P GPUTHMSNS_D_N GPU_TDIODE_P GPU_TDIODE_N MCPTHMSNS_D_P MCPTHMSNS_D_N MCP_THMDIODE_P MCP_THMDIODE_N CPUVTTISNS_R_P CPUVTTISNS_R_N SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE SENSE SENSE SENSE GPUISENS_P GPUISENS_N CPUVTT_ISNS_P CPUVTT_ISNS_N SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE SENSE SENSE SENSE SB_POWER SB_POWER 35 I164 (PCIE_EXCARD) I162 (PCIE_EXCARD) 35 39 I163 39 I161 39 (PCIE_MINI) (PCIE_MINI) I160 39 I159 39 I168 39 I166 39 I167 39 I165 79 I182 (USB_EXTA) I181 (USB_EXTA) I179 (USB_EXTA) I180 (USB_EXTA) I177 (USB_EXTD) I178 (USB_EXTD) I176 (USB_CAMERA) I175 (USB_CAMERA) 79 48 48 10 48 10 48 48 I174 48 I172 48 76 77 I173 48 76 77 I171 48 I169 USB_CARDREADER 48 I170 21 48 I183 21 48 I184 PHYSICAL SPACING PCIE_90D PCIE PCIE_90D PCIE PCIE_90D PCIE PCIE_90D PCIE CLK_PCIE_100D CLK_PCIE CLK_PCIE_100D CLK_PCIE 1TO1_DIFFPAIR 1TO1_DIFFPAIR 1TO1_DIFFPAIR 1TO1_DIFFPAIR USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB DP_100D DISPLAYPORT DP_100D DISPLAYPORT PCIE_EXCARD_R2D_P PCIE_EXCARD_R2D_N PCIE_MINI_R2D_P PCIE_MINI_R2D_N PCIE_CLK100M_MINI_CONN_P PCIE_CLK100M_MINI_CONN_N CHGR_CSI_R_P 62 CHGR_CSI_R_N 62 CHGR_CSO_R_P 46 CHGR_CSO_R_N 46 USB2_EXTA_MUXED_P USB2_EXTA_MUXED_N USB2_LT1_P USB2_LT1_N USB_TPAD_R_P USB_TPAD_R_N USB_CAMERA_CONN_P USB_CAMERA_CONN_N CONN_USB2_BT_P CONN_USB2_BT_N USB_LT2_P USB_LT2_N USB_CARDREADER_P USB_CARDREADER_N DP_IG_AUX_CH_C_P DP_IG_AUX_CH_C_N 90 90 31 90 31 90 31 31 D 62 62 40 40 40 40 50 50 31 31 31 31 40 40 20 32 20 32 81 81 47 47 TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET MEM_CLK GND * GND_P2MM I153 TABLE_SPACING_ASSIGNMENT_ITEM I151 MEM_CMD GND * SENSE_DIFFPAIR GND_P2MM I150 TABLE_SPACING_ASSIGNMENT_ITEM C SENSE_DIFFPAIR I152 TABLE_SPACING_ASSIGNMENT_ITEM MEM_CTRL GND * GND_P2MM MEM_DATA GND * GND_P2MM 47 47 47 67 47 67 C TABLE_SPACING_ASSIGNMENT_ITEM I158 TABLE_SPACING_ASSIGNMENT_ITEM MEM_DQS GND * GND_P2MM NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET SENSE_DIFFPAIR I147 I186 TABLE_SPACING_ASSIGNMENT_HEAD SENSE_DIFFPAIR I185 TABLE_SPACING_ASSIGNMENT_ITEM CLK_PCIE GND * TABLE_SPACING_ASSIGNMENT_HEAD GND_P2MM NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET CLK_FSB GND * GND_P2MM P1V8GPU_P P1V8GPU_N ISNS_CPU_P ISNS_CPU_N PP3V3_S5 PP3V3_S0 47 I198 47 I197 46 I201 46 82 87 37 38 44 54 64 68 69 70 18 20 22 24 26 30 34 48 49 51 55 59 60 63 68 13 18 19 21 22 24 25 28 29 37 39 43 45 47 69 70 77 80 81 82 84 85 TABLE_SPACING_ASSIGNMENT_ITEM PCIE GND TABLE_SPACING_ASSIGNMENT_ITEM GND_P2MM * GND * SPK_OUT I200 I199 SPK_OUT I202 I206 TABLE_SPACING_ASSIGNMENT_ITEM SATA SPK_OUT TABLE_SPACING_ASSIGNMENT_ITEM GND_P2MM I207 CPU_COMP GND * GND_P2MM CPU_GTLREF GND * GND_P2MM TABLE_SPACING_ASSIGNMENT_ITEM USB GND * TABLE_SPACING_ASSIGNMENT_ITEM GND_P2MM I134 SENSE_DIFFPAIR SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S TABLE_SPACING_ASSIGNMENT_ITEM CLK_PCIE SB_POWER * I133 TABLE_SPACING_ASSIGNMENT_ITEM PWR_P2MM CPU_VCCSENSE GND * GND_P2MM FSB_DSTB FSB_DSTB * GND_P2MM I214 TABLE_SPACING_ASSIGNMENT_ITEM SENSE_DIFFPAIR TABLE_SPACING_ASSIGNMENT_ITEM SATA SB_POWER * PWR_P2MM USB SB_POWER * PWR_P2MM NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET I209 TABLE_SPACING_ASSIGNMENT_ITEM I215 I216 TABLE_SPACING_ASSIGNMENT_HEAD TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SENSE_DIFFPAIR SPACING_RULE_SET I218 SENSE_DIFFPAIR TABLE_SPACING_ASSIGNMENT_ITEM I217 TABLE_SPACING_ASSIGNMENT_ITEM LVDS GND * ENET_MDI GND * GND_P2MM GND_P2MM I210 SENSE_DIFFPAIR I211 Memory Constraint Relaxations I212 SENSE_DIFFPAIR I213 I219 Allow 0.127 mm necks for >0.127 mm lines for GMCH fanout TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER MEM_70D BOTTOM ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH 0.127 MM 6.35 MM DIFFPAIR PRIMARY GAP SENSE_DIFFPAIR I220 P1V8GPUISNS_R_P P1V8GPUISNS_R_N ISNS_AIRPORT_P ISNS_AIRPORT_N ISNS_AIRPORT_R_P ISNS_AIRPORT_R_N ISNS_1V5_S3_R_P ISNS_1V5_S3_R_N ISNS_1V5_S3_P ISNS_1V5_S3_N ISNS_LCDBKLT_P ISNS_LCDBKLT_N ISNS_LCDBKLT_R_P ISNS_LCDBKLT_R_N SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE I204 47 I205 47 I208 31 53 I203 31 53 I223 SENSE_DIFFPAIR 53 I224 53 I226 SENSE_DIFFPAIR 53 I225 53 I221 SENSE_DIFFPAIR 53 65 I222 53 65 I227 SENSE_DIFFPAIR 53 85 I228 DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S AUDIO AUDIO AUDIO AUDIO AUDIO AUDIO AUDIO AUDIO AUDIO AUDIO AUDIO AUDIO SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SPKRCONN_L_OUT_P SPKRCONN_L_OUT_N SPKRCONN_S_OUT_P SPKRCONN_S_OUT_N SPKRCONN_R_OUT_P SPKRCONN_R_OUT_N SPKRAMP_L_OUT_P SPKRAMP_L_OUT_N SPKRAMP_R_OUT_P SPKRAMP_R_OUT_N SPKRAMP_S_OUT_P SPKRAMP_S_OUT_N ISNS_ODD_P 39 ISNS_ODD_N 39 ISNS_ODD_R_P 53 ISNS_ODD_R_N 53 ISNS_HDD_P 39 ISNS_HDD_N 39 ISNS_HDD_R_P 53 ISNS_HDD_R_N 53 58 59 58 59 58 59 58 59 58 59 58 59 58 58 58 58 58 58 53 53 53 53 53 85 GND GND DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM B B TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET Graphics ,SATA Constraint Relaxations ALLOW ROUTE ON LAYER? LAYER MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM MEM_40S * OVERRIDE OVERRIDE MEM_40S_VDD * OVERRIDE OVERRIDE OVERRIDE OVERRIDE 0.09 MM 5.8 MM OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE TABLE_PHYSICAL_RULE_ITEM Alternate diffpair width/gap through BGA fanout areas (95-ohm diff) TABLE_PHYSICAL_ASSIGNMENT_HEAD NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET LVDS_100D BGA 100_DIFF_BGA DP_100D BGA 100_DIFF_BGA 0.09 MM 5.8 MM OVERRIDE OVERRIDE OVERRIDE OVERRIDE 0.09 MM 5.8 MM OVERRIDE OVERRIDE OVERRIDE OVERRIDE 0.09 MM 100 MIL OVERRIDE OVERRIDE OVERRIDE OVERRIDE 0.09 MM 100 MIL OVERRIDE OVERRIDE OVERRIDE OVERRIDE 0.09 MM 500 MIL OVERRIDE OVERRIDE OVERRIDE OVERRIDE 0.1 MM 500 MIL OVERRIDE OVERRIDE OVERRIDE OVERRIDE 0.1 MM 500 MIL OVERRIDE OVERRIDE OVERRIDE OVERRIDE 0.1 MM 500 MIL OVERRIDE OVERRIDE OVERRIDE OVERRIDE 0.1 MM 500 MIL OVERRIDE OVERRIDE OVERRIDE OVERRIDE 0.25 MM 250 MIL OVERRIDE OVERRIDE OVERRIDE OVERRIDE 0.23 MM 100 MIL OVERRIDE OVERRIDE OVERRIDE OVERRIDE TABLE_PHYSICAL_RULE_ITEM MEM_70D * OVERRIDE OVERRIDE TABLE_PHYSICAL_ASSIGNMENT_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_ASSIGNMENT_ITEM MEM_70D_VDD * OVERRIDE OVERRIDE TABLE_PHYSICAL_ASSIGNMENT_ITEM SATA_100D BGA TABLE_PHYSICAL_RULE_ITEM 100_DIFF_BGA PCIE_90D * OVERRIDE OVERRIDE TABLE_PHYSICAL_RULE_ITEM PGA CONSTRAINT RELAXATIONS USB_90D * OVERRIDE OVERRIDE TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET ALLOW ROUTE ON LAYER? LAYER MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM PGA_50SE * Y =50_OHM_SE 0.073 MM =50_OHM_SE =1:1_DIFFPAIR TABLE_PHYSICAL_ASSIGNMENT_HEAD NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET FSB_50S PGA PGA_50SE FSB_DSTB_50S PGA PGA_50SE CPU_50S PGA PGA_50SE TABLE_PHYSICAL_RULE_ITEM MCP_DV_COMP TOP OVERRIDE OVERRIDE TABLE_PHYSICAL_RULE_ITEM 0.073 MM MCP_MEM_COMP TOP OVERRIDE OVERRIDE TABLE_PHYSICAL_RULE_ITEM MCP_MII_COMP TOP OVERRIDE OVERRIDE TABLE_PHYSICAL_ASSIGNMENT_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_ASSIGNMENT_ITEM MCP_USB_RBIAS TOP OVERRIDE OVERRIDE TABLE_PHYSICAL_ASSIGNMENT_ITEM TABLE_PHYSICAL_RULE_ITEM MCP_DV_COMP * OVERRIDE OVERRIDE TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 A NET_SPACING_TYPE2 AREA_TYPE TABLE_SPACING_ASSIGNMENT_ITEM FSB_DATA * PGA CPU_27P4S BOTTOM OVERRIDE OVERRIDE * PGA SYNC_MASTER=MUXGFX PHYSICAL_RULE_SET PGA_CPU FSB_ADDR * PGA PGA_CPU FSB_ADSTB * PGA PGA_CPU NOTICE OF PROPRIETARY PROPERTY TABLE_PHYSICAL_RULE_HEAD LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_SPACING_ASSIGNMENT_ITEM THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_40S ISL4,ISL9 OVERRIDE OVERRIDE OVERRIDE MEM_40S_VDD ISL3,ISL10 N OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE I TO MAINTAIN THE DOCUMENT IN CONFIDENCE TABLE_PHYSICAL_RULE_ITEM II NOT TO REPRODUCE OR COPY IT TABLE_SPACING_ASSIGNMENT_ITEM FSB_1X * PGA PGA_CPU III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM CPU_AGTL * PGA PGA_CPU CPU_8MIL * PGA PGA_CPU MEM_70D ISL4,ISL9 OVERRIDE OVERRIDE OVERRIDE MEM_70D_VDD ISL3,ISL10 N OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE TABLE_SPACING_ASSIGNMENT_ITEM SIZE DRAWING NUMBER REV TABLE_PHYSICAL_RULE_ITEM D APPLE INC Ground-referenced memory signals (DQ,DQM,DQS) MAY route on ISL9 (VDD-referenced plane)but not next to VDD island Forces power-referenced memory signals (CLK,ADDR,CTRL) to not route on ISL3, ISL4 & ISL10(GND-referenced planes) SYNC_DATE=02/21/2008 PGA_CPU TABLE_SPACING_ASSIGNMENT_ITEM FSB_DSTB Project Specific Constraints TABLE_PHYSICAL_RULE_ITEM SPACING_RULE_SET 051-7892 SCALE SHT NONE A.0.0 OF 96 97 A K19 Board-Specific Spacing & Physical Constraints TABLE_BOARD_INFO BOARD LAYERS BOARD AREAS BOARD UNITS (MIL or MM) ALLEGRO VERSION TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM NO_TYPE,BGA,PGA MM 15.5.1 TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_PHYSICAL_RULE_ITEM DEFAULT * Y =50_OHM_SE =50_OHM_SE 33.6 MM MM MM * DEFAULT 0.1 MM * Y =DEFAULT =DEFAULT 10 MM =DEFAULT =DEFAULT NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET * * BGA BGA_P1MM MEM_CLK * BGA BGA_P2MM CLK_FSB * BGA BGA_P2MM CLK_PCIE * BGA BGA_P2MM CLK_SLOW * BGA BGA_P2MM FSB_DSTB FSB_DSTB BGA BGA_P3MM TABLE_SPACING_ASSIGNMENT_ITEM ? TABLE_PHYSICAL_RULE_ITEM STANDARD TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM STANDARD * =DEFAULT ? BGA_P1MM * =DEFAULT ? TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_PHYSICAL_RULE_HEAD D PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH 55_OHM_SE TOP,BOTTOM Y 0.090 MM 0.090 MM MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_SPACING_RULE_ITEM BGA_P2MM * =DEFAULT D TABLE_SPACING_ASSIGNMENT_ITEM ? TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_ITEM BGA_P3MM * =DEFAULT ? PGA_CPU * 0.073 MM ? LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_ASSIGNMENT_ITEM TABLE_PHYSICAL_RULE_ITEM 55_OHM_SE * Y 0.076 MM 0.076 MM =STANDARD =STANDARD TABLE_SPACING_RULE_ITEM =STANDARD TABLE_SPACING_ASSIGNMENT_ITEM NOTE:From T18 MLB, changed to reflect M99 stackup TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER TABLE_SPACING_RULE_HEAD TABLE_PHYSICAL_RULE_ITEM 50_OHM_SE TOP,BOTTOM Y 0.110 MM 0.095 MM TABLE_SPACING_RULE_ITEM 1.5:1_SPACING * 0.15 MM SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT * 0.140 MM ? 3X_DIELECTRIC * 0.210 MM ? 4X_DIELECTRIC * 0.280 MM ? 5X_DIELECTRIC * 0.350 MM ? ? TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM 50_OHM_SE * Y 0.090 MM 0.090 MM =STANDARD =STANDARD =STANDARD 1.8:1_SPACING * 0.18 MM ? 2:1_SPACING * 0.2 MM ? TABLE_SPACING_RULE_ITEM 2X_DIELECTRIC TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM 2.5:1_SPACING * 0.25 MM ? TABLE_SPACING_RULE_ITEM 3:1_SPACING * 0.3 MM ? 4:1_SPACING * 0.4 MM ? TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH 40_OHM_SE TOP,BOTTOM Y 0.165 MM 0.095 MM 40_OHM_SE * Y 0.135 MM 0.135 MM =STANDARD =STANDARD =STANDARD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 27P4_OHM_SE TOP,BOTTOM Y 0.310 MM 0.095 MM 27P4_OHM_SE * Y 0.250 MM 0.250 MM =STANDARD =STANDARD =STANDARD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 70_OHM_DIFF * N =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM C C TABLE_PHYSICAL_RULE_HEAD TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 1:1_DIFFPAIR * Y =STANDARD =STANDARD =STANDARD 0.1 MM 0.1 MM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM 70_OHM_DIFF ISL3,ISL4 Y 0.160 MM 0.160 MM 0.175 MM 0.175 MM 70_OHM_DIFF ISL9,ISL10 Y 0.160 MM 0.160 MM 0.175 MM 0.175 MM 70_OHM_DIFF ISL2,ISL11 Y 0.170 MM 0.170 MM 0.150 MM 0.150 MM 70_OHM_DIFF TOP,BOTTOM Y 0.170 MM 0.095 MM 0.150 MM 0.150 MM PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 80_OHM_DIFF * N =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD 80_OHM_DIFF ISL3,ISL4 Y 0.125 MM 0.125 MM 0.180 MM 0.180 MM 80_OHM_DIFF ISL9,ISL10 Y 0.125 MM 0.125 MM 0.180 MM 0.180 MM 80_OHM_DIFF ISL2,ISL11 Y 0.140 MM 0.140 MM 0.190 MM 0.190 MM 80_OHM_DIFF TOP,BOTTOM Y 0.140 MM 0.095 MM 0.190 MM 0.190 MM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM B B TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 90_OHM_DIFF * N =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD 90_OHM_DIFF ISL3,ISL4 Y 0.102 MM 0.102 MM 0.220 MM 0.220 MM 90_OHM_DIFF ISL9,ISL10 Y 0.102 MM 0.102 MM 0.220 MM 0.220 MM 90_OHM_DIFF ISL2,ISL11 Y 0.115 MM 0.115 MM 0.230 MM 0.230 MM 90_OHM_DIFF TOP,BOTTOM Y 0.115 MM 0.095 MM 0.230 MM 0.230 MM PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD MAXIMUM NECK LENGTH TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 100_DIFF_BGA * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF 100_DIFF_BGA ISL3,ISL4 Y 0.075 MM 0.075 MM 0.125 MM 0.125 MM 100_DIFF_BGA ISL9,ISL10 Y 0.075 MM 0.075 MM 0.125 MM 0.125 MM TABLE_PHYSICAL_RULE_ITEM 100_OHM_DIFF * N =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM 100_OHM_DIFF ISL3,ISL4 Y 0.080 MM 0.080 MM 0.200 MM 0.200 MM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM 100_OHM_DIFF A ISL9,ISL10 Y 0.080 MM 0.080 MM 0.200 MM 0.200 MM PCB Rule Definitions TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM 100_OHM_DIFF ISL2,ISL11 Y 0.089 MM 0.089 MM 0.220 MM SYNC_MASTER=M99_MLB NOTICE OF PROPRIETARY PROPERTY TABLE_PHYSICAL_RULE_ITEM 100_OHM_DIFF TOP,BOTTOM Y 0.089 MM 0.089 MM 0.220 MM SYNC_DATE=01/22/2008 NOTE: 100_DIFF_BGA is 100-ohms differential impedance on outer layers and 95-ohms on inner layers 0.220 MM 0.220 MM THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 110_OHM_DIFF * N =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD I TO MAINTAIN THE DOCUMENT IN CONFIDENCE TABLE_PHYSICAL_RULE_ITEM II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART TABLE_PHYSICAL_RULE_ITEM 110_OHM_DIFF ISL3,ISL4 Y 0.077 MM 0.077 MM 0.330 MM 0.330 MM 110_OHM_DIFF ISL9,ISL10 Y 0.077 MM 0.077 MM 0.330 MM 0.330 MM 110_OHM_DIFF ISL2,ISL11 Y 0.077 MM 0.077 MM 0.330 MM 0.330 MM SIZE TABLE_PHYSICAL_RULE_ITEM APPLE INC TABLE_PHYSICAL_RULE_ITEM 110_OHM_DIFF TOP,BOTTOM Y 0.077 MM 0.077 MM 0.330 MM DRAWING NUMBER D TABLE_PHYSICAL_RULE_ITEM SCALE SHT 0.330 MM NONE REV 051-7892 A.0.0 OF 97 97 A ... BMON_ENG,DEBUG_ADC,GMUX_JTAG,LPCPLUS,VREFMRGN,XDP_CONN K19_DEVEL_PVT BMON_PROD,LPCPLUS,NO_VREFMRGN,XDP_CONN K19_PROD BMON_PROD,LPCPLUS_NOT,NO_VREFMRGN K19_PROGPARTS GMUX_PROG,BOOTROM_PROG,SMC_PROG,TPAD_PROG BOM GROUP BOM OPTIONS FB_256_SAMSUNG... MCPCORES0_EN P1V05S0_EN VIN SYNC_DATE=12/12/2007 NOTICE OF PROPRIETARY PROPERTY U7870 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING... SYNC_MASTER=T18_MLB SYNC_DATE=12/12/2007 NOTICE OF PROPRIETARY PROPERTY 88E1116 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING