8 CK APPD ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5% ALL CAPACITANCE VALUES ARE IN MICROFARADS ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ REV SCHEM,MBP 15" MLB ZONE ECN ENG APPD DESCRIPTION OF CHANGE DATE ? ? ? ? DATE ? 12/07/2007 (.csa) Page D TABLE_TABLEOFCONTENTS_HEAD TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM C TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM B TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 37 38 39 40 41 42 43 44 46 47 49 Contents Table of Contents System Block Diagram Power Block Diagram Power Block Diagram BOM Configuration Revision History Functional / ICT Test Power Aliases Signal Aliases CPU FSB CPU Power & Ground CPU Decoupling & VID eXtended Debug Port (XDP) NB CPU Interface NB PEG / Video Interfaces NB Misc Interfaces NB DDR2 Interfaces NB Power NB Power NB Grounds NB Standard Decoupling NB Graphics Decoupling SB Enet, Disk, FSB, LPC SB PCI, PCIe, DMI, USB SB Pwr Mgt, GPIO, Clink SB Power & Ground SB Decoupling SB Misc Clock (CK505) Clock Termination DDR2 SO-DIMM Connector A DDR2 SO-DIMM Connector B Memory Active Termination Left I/O Board Connector Ethernet (Yukon) Yukon Power Control Ethernet Connector FireWire Link (TSB83AA22) FireWire PHY (TSB83AA22) FireWire Port Power FireWire Ports PATA Connector External USB Connector Left Clutch Barrel Interconnect SMC Date Sync N/A (.csa) Page TABLE_TABLEOFCONTENTS_HEAD N/A 08/23/2006 TABLE_TABLEOFCONTENTS_ITEM (T9_MLB) 08/23/2006 TABLE_TABLEOFCONTENTS_ITEM (T9_MLB) N/A TABLE_TABLEOFCONTENTS_ITEM N/A N/A TABLE_TABLEOFCONTENTS_ITEM N/A N/A TABLE_TABLEOFCONTENTS_ITEM N/A (MASTER) TABLE_TABLEOFCONTENTS_ITEM (MASTER) (MASTER) TABLE_TABLEOFCONTENTS_ITEM (MASTER) 08/23/2006 TABLE_TABLEOFCONTENTS_ITEM (T9_MLB) 03/16/2007 TABLE_TABLEOFCONTENTS_ITEM T9_NOME 03/16/2007 TABLE_TABLEOFCONTENTS_ITEM T9_NOME 03/19/2007 TABLE_TABLEOFCONTENTS_ITEM M76_MLB 12/12/2006 TABLE_TABLEOFCONTENTS_ITEM T9_NOME 03/16/2007 TABLE_TABLEOFCONTENTS_ITEM T9_NOME 03/16/2007 TABLE_TABLEOFCONTENTS_ITEM T9_NOME 03/16/2007 TABLE_TABLEOFCONTENTS_ITEM T9_NOME 03/16/2007 TABLE_TABLEOFCONTENTS_ITEM T9_NOME 03/16/2007 TABLE_TABLEOFCONTENTS_ITEM T9_NOME 03/16/2007 TABLE_TABLEOFCONTENTS_ITEM T9_NOME 03/16/2007 TABLE_TABLEOFCONTENTS_ITEM T9_NOME 01/17/2007 TABLE_TABLEOFCONTENTS_ITEM T9_NOME 03/12/2007 TABLE_TABLEOFCONTENTS_ITEM M76_MLB 03/16/2007 TABLE_TABLEOFCONTENTS_ITEM T9_NOME 03/16/2007 TABLE_TABLEOFCONTENTS_ITEM T9_NOME 03/16/2007 TABLE_TABLEOFCONTENTS_ITEM T9_NOME 03/16/2007 TABLE_TABLEOFCONTENTS_ITEM T9_NOME 01/17/2007 TABLE_TABLEOFCONTENTS_ITEM T9_NOME 08/24/2006 TABLE_TABLEOFCONTENTS_ITEM (T9_MLB) 03/16/2007 TABLE_TABLEOFCONTENTS_ITEM T9_NOME 08/23/2006 TABLE_TABLEOFCONTENTS_ITEM (MASTER) 08/24/2006 TABLE_TABLEOFCONTENTS_ITEM (M59_SYNC) 08/24/2006 TABLE_TABLEOFCONTENTS_ITEM (M59_SYNC) 11/14/2006 TABLE_TABLEOFCONTENTS_ITEM (T9_NOME) 08/24/2006 TABLE_TABLEOFCONTENTS_ITEM (M59_SYNC) 03/16/2007 TABLE_TABLEOFCONTENTS_ITEM T9_NOME 03/16/2007 TABLE_TABLEOFCONTENTS_ITEM T9_NOME 03/19/2007 TABLE_TABLEOFCONTENTS_ITEM M76_MLB 03/19/2007 TABLE_TABLEOFCONTENTS_ITEM M76_MLB 03/19/2007 TABLE_TABLEOFCONTENTS_ITEM M76_MLB 03/19/2007 TABLE_TABLEOFCONTENTS_ITEM M76_MLB 03/19/2007 TABLE_TABLEOFCONTENTS_ITEM M76_MLB (MASTER) TABLE_TABLEOFCONTENTS_ITEM (MASTER) 08/02/2007 TABLE_TABLEOFCONTENTS_ITEM M88 07/16/2007 TABLE_TABLEOFCONTENTS_ITEM M87 01/17/2007 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 50 51 52 53 54 55 56 58 59 61 69 70 71 73 74 75 76 77 78 80 81 82 84 85 86 87 88 89 90 91 92 93 94 96 100 101 102 103 104 105 106 107 108 109 Date Contents D Sync SMC Support LPC+ Debug Connector SMBus Connections Current & Voltage Sensing Current Sensing Thermal Sensors Fan Connectors ALS Support Sudden Motion Sensor (SMS) SPI BootROM PBus-In & Battery Connectors Power FETs IMVP6 CPU VCore Regulator 5V / 3.3V Power Supply 1.25V / 1.05V Power Supply 1.8V DDR2 Supply 1.5V Power Supply FW PHY Power Supplies 3.425V G3Hot Supply & Power Control NV G84M PCI-E NV G84M Core/FB Power NV G84M Frame Buffer I/F GDDR3 Frame Buffer A (Top) GDDR3 Frame Buffer B (Top) NV G84M GPIO/MIO/Misc GPU Straps NV G84M Video Interfaces GPU (G84M) Core Supply LVDS Display Connector GDDR3 Frame Buffer A (Bot) GDDR3 Frame Buffer B (Bot) 1.8V FB Power Supply DVI Display Connector Project Specific Connectors CPU/FSB Constraints NB Constraints Memory Constraints SB Constraints (1 of 2) SB Constraints (2 of 2) Clock & SMC Constraints FireWire Constraints GPU (G84M) Constraints Project Specific Constraints PCB Rule Definitions (MASTER) (MASTER) 03/19/2007 M76_MLB (MASTER) (MASTER) 05/22/2007 M87_MLB 05/22/2007 M87_MLB (MASTER) (MASTER) 03/19/2007 M76_MLB 03/19/2007 M76_MLB 03/19/2007 M76_MLB 03/16/2007 T9_NOME 09/09/2006 (M59_SYNC) 03/19/2007 M76_MLB 01/23/2007 M76_MLB 03/19/2007 M76_MLB 03/12/2007 M76_MLB 03/19/2007 M76_MLB 03/12/2007 C M76_MLB 03/19/2007 M76_MLB 08/02/2007 M88 (MASTER) (MASTER) (MASTER) (MASTER) (MASTER) (MASTER) (MASTER) (MASTER) (MASTER) (MASTER) (MASTER) (MASTER) 08/02/2007 M88 (MASTER) (MASTER) 08/02/2007 M88 (MASTER) (MASTER) 06/19/2007 M88_MLB_VRAM_BOT 06/19/2007 M88_MLB_VRAM_BOT (MASTER) (MASTER) (MASTER) (MASTER) 08/24/2006 (M59_SYNC) 01/17/2007 T9_NOME 01/17/2007 T9_NOME 01/17/2007 T9_NOME 01/17/2007 T9_NOME 01/17/2007 T9_NOME 01/17/2007 T9_NOME 01/17/2007 T9_NOME (MASTER) (MASTER) (MASTER) (MASTER) (MASTER) (MASTER) B TABLE_TABLEOFCONTENTS_ITEM T9_NOME TABLE_TABLEOFCONTENTS_ITEM DIMENSIONS ARE IN MILLIMETERS A APPLE INC METRIC XX X.XX DRAFTER Schematic / PCB #’s PART NUMBER THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING ENG APPD MFG APPD QA APPD DESIGNER RELEASE SCALE I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART ANGLES QTY DESCRIPTION REFERENCE DES CRITICAL 051-7413 SCHEM,TAUPO,M87 SCH CRITICAL 820-2249 PCBF,TAUPO,M87 PCB CRITICAL A NOTICE OF PROPRIETARY PROPERTY DESIGN CK X.XXX BOM OPTION TITLE DO NOT SCALE DRAWING SCHEM,TAUPO,M87 NONE DRAWING SIZE TITLE=MLB ABBREV=DRAWING LAST_MODIFIED=Wed Dec 12 10:44:22 2007 THIRD ANGLE PROJECTION MATERIAL/FINISH NOTED AS APPLICABLE D DRAWING NUMBER REV 051-7413 16.0.0 SHT 1 OF 89 CPU U2900 CK 505 2.? GHz Core ~1.2V Pg 10 Clocks Pg 28 J1300/JD000 TERMS Pg 29 UC500 ReGen ITP/XDP CONN Pg Clocks Pg 98 Pg 12/103 Pg 17,18,19 Pg 14 U9120 Power Supply Pg 66 Pg 68-76 Pg 15/16 DIMM DDR2 - Dual Channel 1.8V - 64 Bits 533/667/800? MHz J5810/20/90 Parallel Term ALS SENS Temp Sense CPU GPU Right Side Charger Pg 32 Pg30,31 Misc LVDS MUX DC/Batt Conn J3100 J3200 Main Memory Pg 77 Core 1.05 - 1.25V TV RGB Out PEG Connector PCI-E DVI-I NB-GMCH Pg 14 Pg Pg Pg Pg 51 52 52 ?? CLnk Pg 15 Pg 15 U5920 Sudden Motion Detect Pg 56 Pg 79,81 J9000/10 U9250/60 Int Disp Conn Pg 78 GPIO Pg 80 SPI Boot ROM MUX x4 DMI A B,0 BSA BSB ADC Fan Ser Prt SMC Pg 92 Pg 93/4/5 LPC Pg 48 Prt 80, Comm 1, SMC, FWH Pg 124-130 Pg 24 GPIOs J4710 J4720 J4700 Camera/IR Bluetooth Geyser Pg 45 Pg 45 Trackpad/Keyboard Pg 45 USB Pg 23 B Core Pg 25 Pg 24 MUX Pg 23 PCI-E Conns PCI-E PCI-E LPC Conn Pg 57 J4600 USB Connectors Pg 44 UATA UB100 TPM Linda Fnc Core 1.05V Ln1 Ln2 Ln3 Ln4 Ln5 Ln6 - x1 2.5 GHz JB200 JB300 JB400 J4630 SB-ICH8 Pg 22 Pg 42 3.3 V 100 MHz Pg 23 SMB J4400 SPI Pg 24 SATA SATA-1 SATA-2 Pg 43 CLnk Pg 46 J5100 U2300 Pg 22 SATA Conn DMI Pg 23 U6000 Pg 22 SATA-0 1.2 V / 1.5 GHz J4510/20/30 C Pg 58 2.5 GHz J9200 U4900 UATA Conn Pg 51, 115-120 J5600/10/50/60, J5720/30/50 Fan Conn Pg 53, 54 U6100/50 J9200 Source is the LVDS from the PEG based GPU B U5572 U5500 U5550 U??? Pg 55 Pg 15 DMI Power Sense C D J6900/50 Pg 13 U1400 x16 PCI-E SDVO GPIO J9400 TERMS Pg 98 FSB 64-Bit 800/1066? MHz J8000 Approximate System Block Diagram U1000 D E-NET CLnk PCI AZALIA Pg 22 Pg 24 Pg 23 Pg 22 DIMM’s J3100 J3200 Clk Gen U2900 UC500 33 MHz 32-Bit U6200 U4000 U???? MDC TSB82AA2 Audio Codec FW-Link Pg 59 Pg ?? Pg 38 100 MHz 8-Bit U3700 A U6300/1 U4100 NINEVEH TSB81BA3 Line In Amp E-NET FW-PHY Pg 60 Pg 35 Pg 39 U6400 U6500 System Block Diagram U6600/10/20 Line Out Amp Line Out Amp Speaker Amps Pg 61 Pg 62 Pg 63 SYNC_MASTER=(T9_MLB) SYNC_DATE=08/23/2006 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT J3400 JB500 J4320 J4630 J4330 JB000 J6800/1/2/3 Mini PCI-E AirPort PCI-E Conn E-NET Conn FireWire Conn PCI Conn Audio Conns Pg 33 Pg 96 Pg 37 Pg 41 Pg 91 Pg 65 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC SCALE SHT NONE REV 051-7413 15.0.0 OF 89 A M87 POWER SYSTEM ARCHITECTURE SHDN* CRITICAL 87438-0832 Energy Star LDO V U7950 PBUS_LDO_ENSHDN* VOUT (PAGE 17, LIO) 03 U5705 VOUT Q6950 LIO_DCIN_ISENSE INRUSH LIMITER (PAGE 15, LIO) J6950 CHGR_EN SMC_ADAPTER_EN VOUT Q7970 VIN BATTERY CHARGE A FETS PPVBATT_G3H_FET VR_ON LIO_BATT_ISENSE VIN SMC_PM_G2_ENU7858 EN1 PP3V42_G3H C 3.3V EN2 U7859 P5VS3_SS VOUT2 EN5 NBCORE_IOUT (18A MAX CURRENT) P1V8S3_PGOOD V A PPVCORE_SO_CPU CPUVCORE_IOUT PM_SLP_S3_L P1V8S3_EN S5 0.9V VR_ON CLKEN# 1.8V U2300 VR_PWRGOOD_DELAY PM_SB_PWROK 10 C PP5V_S3 15 Q7030 PGOOD Q7851 Q7851 CPU PP3V3_S0 Q7020 07 P5VS3_SS 14 PWRGOOD PP5V_S0 RESET* PP5V_S5 17 Q7070 U1000 PP3V3_S0GPU P5VS0_SS Q3810 P3V3GPU_SS U5440 MCH PP3V3_ENET Q7010 A PP1V8_S3_ISNS P1V8_S3_IOUT PP1V9_ENET IN EN P3V3ENET_SS 11 PP3V3_S3 P3V3S3_SS 1V8S3_PGOOD PM_GPUVCORE_EN PWROK 08 Q7610 U7880 SMC P1V8P1V5P1V05S0_PGOOD P15 ALL_SYS_PWRGD 10a VIN EN1 5V VOUT1 PM_SLP_S3_LS5V PP3V3_S0_LIO PP5V_S3_LIO 3.3V 4.5V VOUT2 TPS51120 U7600 PGOOD1 NC_LIO_P3V3S3_PGOOD (PAGE 16, LIO) (UNUSED) EN5 VOUT RST* 09 PM_SLP_S5_L WOL_EN PM_P3V3GPU_EN SIGNAL DELAY TIME P3V3GPU_SS (6A MAX CURRENT) A PP1V25_ENET PM_SLP_S3_DELAY_L PWR/RST STATUS G3H POWER ON S5 POWER ON S3 POWER ON S0 SYSTEM POWER ON S0 CPU POWER ON PLATFORM,CPU RESET Q7095 16 PP1V25_S0 TP1V25ENET_PGOOD (UNUSED) PM_SLP_S3_L P94 U4900 (PAGE 45) STEP 01-04 01,05-09 10-13 14-18 17,19-24 25-27 STEP 06 (S5 POWER STATUS)TRUTH TABLE P1V25S0_SS 19 VIN Q7002 P5VS0_SS PM_P1V8_S0GPU_EN VOUT EN (10A MAX CURRENT) PP1V8_S0GPU_ISNS_R ISL6269 U9300 (PAGE 77) Q7012 Q4260 Q7096 P1V25S0_SS NO AC/BATTERY BATTERY ONLY ACIN WITH/WITHOUT BATTERY BATTERY ONLY,PRESS PWR BUTTON U5410 A PGOOD PP1V8_S0GPU_ISNS P1V8_S0GPU_IOUT P3V3S0_SS TP_P1V8_S0GPU_PGOOD (UNUSED) PPVP_FW 1.5A FUSE L(S5 L(S5 H(S5 H(S5 Power Block Diagram OFF) OFF) ON) ON) SYNC_MASTER=(T9_MLB) SYNC_DATE=08/23/2006 NOTICE OF PROPRIETARY PROPERTY PP3V3_FW VIN SHDN* THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING VOUT LT3470 U7700 (PAGE 63) PPBUS_FW_FWPWRSW_F PPVIN_FW_3V3FW (0.2A MAX CURRENT) I TO MAINTAIN THE DOCUMENT IN CONFIDENCE PP1V95_FW VIN EN II NOT TO REPRODUCE OR COPY IT VOUT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART TPS799195 U7720 SIZE FWPWR_EN_L_DIV DRAWING NUMBER D (PAGE 63) APPLE INC SMC_PM_G2_EN P60 P93 POWER ON SEQUENCE LIST U7860 MAX6838 (PAGE 64) P1V25_S0_IOUT PGOOD PP3V3_S5 PP1V25_S0_ISNS P95 IMVP_VR_ON 99ms S0PWRGD_OK 200ms VR_PWRGOOD_DELAY 7ms VCC RSTIN RST* U5430 PM_ENET_EN U7850 B RES* PM_S4_STATE_L SMC_ADAPTER_EN VOUT PM_PWRBTN_L PP3V3_S0_LIO PM_SLP_S3_LS5V TPS51117 U7400 (PAGE 60) LRESET* P17 Q3800 EN_PSV IMVP_VR_ON P90 LTC2900 V3(1.8V) U7870 (PAGE 64) Q7072 P3V3ENET_SS PM_RSMRST_L P13 SMC_ONOFF_L FWPWR_EN_L_DIV VIN 99ms DLY P16 RSMRST_PWRGD PGOOD2 NC_LIO_P5VS3_PGOOD (UNUSED) PM_ENET_EN P12 S0PGOOD_PWROK V4(1.25V) Q7611 EN3 Q4261 PP4V5_AUDIO_ANALOG TPS79501 U6201 (PAGE 10, LIO) PP3V3_S3_LIO EN2 V1(5V) V2(3.3V) VIN EN_PSV 11a Q7850 PM_P1V8_S0GPU_EN FSB_CPURST_L U1400 U3850 TPS79501 (PAGE 36) PM_SLP_S3_L LIO_S3_EN H_CPURST* VOUT PP5V_S0_AUDIO PM_SLP_S3_LS5V GPUVCORE_PGOOD CPU_PWRGD PWROK CPUPWRGD(GPIO49) CLPWROK Q7000 06 PP1V8_S3 (12A MAX CURRENT) VOUT2 S4_STATE* Q7096 RSMRST* 12 TPS511160 U7500 (PAGE 61) LIO_S3_EN PLT_RST_L PLTRST* U2840 PGOOD VOUT1 PM_S4_STATE_L A U2300 VR_PWRGD_CLKEN_L P3V3S0_SS S3 Q3801 VRMPWRGD (PAGE 58) (10mA MAX CURRENT) PP0V9_S0 VIN SLP_S3* ICH8M PWRBTN* U2830 VR_PWRGD_CLKEN (44A MAX CURRENT) GPUVCORE_IOUT RSMRST_PWRGD PGOOD2 13 ICH8M CPUVCORE PPVCORE_S0_NB_R A PP3V3_S5 (5.5A MAX) CURRENT) P3V3S3_SS P1V8S3_EN VOUT ISL9504 U7100 GPUVCORE_PGOOD PM_GPUVCORE_EN PP3V3_S5 TPS51120 EN3 U7300 PGOOD1 (PAGE 59) Q7012 PPVCORE_GPU18 PP5V_S5 (8A MAX CURRENT) VOUT1 5V VIN IMVP_VR_ON 05 04 V A PGOOD PPVBAT_G3H_CHGR_OUT Q7002 U8995 U5400 VOUT ISL6263B U8900 (PAGE 73) (PAGE 17) 518S0457 U5420 SMC_CPU_VSENSE SMC_GPU_VSENSE 8A FUSE PPVBATT_G3H_FET_F PP1V05_S0(10A MAX CURRENT) 1.05VVOUT TPS51117 U7450 (PAGE 60)PGOOD ENABLE U5715 BATT_POS VIN D EN_PSV U7900 (PAGE 17, LIO) SMC_BC_ACOK CRITICAL 87438-1043 (4.5A MAX CURRENT) PP1V5_S0 PM_SLP_S3_DELAY_L VOUT TPS51117 U7600 (PAGE 62) PGOOD VIN ISL6257 RN5VD30A-F U5000 (PAGE 46) 1.5V EN_PSV SMC_RESET_L VOUT Q5315 VIN PM_SLP_S3_DELAY_L PBUS SUPPLY / BATTERY CHARGER A PP18V5_G3H_CHGR VIN B 02 SMC RESET "BUTTON" PPBUS_G3H VIN 518S0456 LT3470 U7800 (PAGE 64) SMC_PBUS_VSENSE MAX8719 D Q7850 PP3V42_G3H VOUT 3.425V"G3HOT" 6A FUSE 01 (0.2A MAX CURRENT) VIN PPDCIN_G3H PP18V5_DCIN J6990 SCALE SHT NONE REV 051-7413 15.0.0 OF 89 A D D C C B B Power Block Diagram SYNC_MASTER=N/A A SYNC_DATE=N/A NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC SCALE SHT NONE REV 051-7413 15.0.0 OF 89 A BOM Variants TABLE_BOMGROUP_HEAD BOM NUMBER BOM NAME BOM OPTIONS 630-9089 PCBA,2.5GHZ,512SAM_VRAM,M87 M87_COMMON,EEE_Z3G,CPU_2_5GHZ,FB_512_SAMSUNG 630-9091 PCBA,2.6GHZ,512SAM_VRAM,M87 M87_COMMON,EEE_Z3J,CPU_2_6GHZ,FB_512_SAMSUNG 630-9088 PCBA,2.5GHZ,512HY_VRAM,M87 M87_COMMON,EEE_Z3F,CPU_2_5GHZ,FB_512_HYNIX 630-9090 PCBA,2.6GHZ,512HY_VRAM,M87 M87_COMMON,EEE_Z3H,CPU_2_6GHZ,FB_512_HYNIX 630-9213 PCBA,2.4GHZ,256SAM_VRAM,M87 M87_COMMON,EEE_ZUP,CPU_2_4GHZ,FB_256_SAMSUNG 630-9238 PCBA,2.4GHZ,256HY_VRAM,M87 M87_COMMON,EEE_043,CPU_2_4GHZ,FB_256_HYNIX 630-9286 PCBA,2.4GHZFUSED,256SAM_VRAM,M87 M87_COMMON,EEE_0U2,CPU_2_4GHZFUSED,FB_256_SAMSUNG 630-9287 PCBA,2.4GHZFUSED,256HY_VRAM,M87 M87_COMMON,EEE_0U3,CPU_2_4GHZFUSED,FB_256_HYNIX TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM D D TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM M87 BOM Groups TABLE_BOMGROUP_HEAD BOM GROUP BOM OPTIONS M87_COMMON ALTERNATE,COMMON,M87_COMMON1,M87_COMMON2,M87_PROGPARTS M87_COMMON1 ISL9504B,ONEWIRE_PU,LPCPLUS,SMC_DEBUG_NO M87_COMMON2 GPUVID_1P13V,P1V8S3_1V8,SMS_MOT_DIS,YUKON_ULTRA,VGA_TERM_CONN M87_DEBUG SMC_DEBUG_YES,XDP,XDP_CONN M87_PROGPARTS BOOTROM_PROG,SMC_PROG BOM GROUP BOM OPTIONS FB_512_SAMSUNG VRAM8,VRAM_16M,VRAM_SAMSUNG,VRAM_512_SAMSUNG FB_512_HYNIX VRAM8,VRAM_16M,VRAM_HYNIX,VRAM_512_HYNIX FB_256_SAMSUNG VRAM4,VRAM_16M,VRAM_SAMSUNG,VRAM_256_SAMSUNG FB_256_HYNIX VRAM4,VRAM_16M,VRAM_HYNIX,VRAM_256_HYNIX TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_HEAD TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM C Bar Code Labels / EEE #’s C PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION 826-4393 LBL,P/N LABEL,PCB,28MM X MM [EEE:Z3F] CRITICAL EEE_Z3F 826-4393 LBL,P/N LABEL,PCB,28MM X MM [EEE:Z3G] CRITICAL EEE_Z3G 826-4393 LBL,P/N LABEL,PCB,28MM X MM [EEE:Z3H] CRITICAL EEE_Z3H 826-4393 LBL,P/N LABEL,PCB,28MM X MM [EEE:Z3J] CRITICAL EEE_Z3J 826-4393 LBL,P/N LABEL,PCB,28MM X MM [EEE:ZUP] CRITICAL EEE_ZUP 826-4393 LBL,P/N LABEL,PCB,28MM X MM [EEE:043] CRITICAL EEE_043 826-4393 LBL,P/N LABEL,PCB,28MM X MM [EEE:ZUP] CRITICAL EEE_0U2 826-4393 LBL,P/N LABEL,PCB,28MM X MM [EEE:043] CRITICAL EEE_0U3 Module Parts B PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL 337S3560 IC,PDC,SR,QS,C0,2.5G,35W,800FSB,6M,BGA U1000 CRITICAL BOM OPTION CPU_2_5GHZ 337S3559 IC,PDC,SR,QS,C0,2.6G,35W,800FSB,6M,BGA U1000 CRITICAL CPU_2_6GHZ 338S0509 IC,GPU,NV G84M,BGA,LOW LEAK U8000 CRITICAL 338S0432 IC,NB,CRESTLINE,GM,C0,PRQ,965PM U1400 CRITICAL 338S0434 IC,SB,ICH8M,B1,PRQ,BGA U2300 CRITICAL 353S1651 IC,ISL9504B,2PH IMVP6 REG,PMON,QFN48 U7100 CRITICAL 359S0130 IC,SLG2AP101,LW PWR CLCK GEN,CK505,QFN68 U2900 CRITICAL 338S0386 IC,88E8058,GIGABIT ENET XCVR,64P QFN U3700 CRITICAL 338S0274 IC,SMC,HS8/2116 U4900 CRITICAL 341S2193 IC,SMC,DEVELOPMENT,M75 U4900 CRITICAL SMC_PROG 335S0384 IC,16MBIT 8-PIN SPI SERIAL FLASH,SOIC8 U6100 CRITICAL BOOTROM_BLANK 341S2192 IC,EFI ROM,DEVELOPMENT,M75 U6100 CRITICAL BOOTROM_PROG 337S3561 IC,PDC,SR,ES2,L0,2.4G,35W,800FSB,3M,BGA U1000 CRITICAL CPU_2_4GHZ 337S3576 IC,PDC,SR,QS,C0,2.4G,35W,800FSB,3M,BGA U1000 CRITICAL CPU_2_4GHZFUSED 333S0423 IC,SGRAM,GDDR3,16Mx32,800MHZ,136 FBGA U8400,U8450,U8500,U8550,U9100,U9150,U9200,U9250 CRITICAL VRAM_512_SAMSUNG 333S0424 IC,SGRAM,GDDR3,16Mx32,900MHZ,136 FBGA U8400,U8450,U8500,U8550,U9100,U9150,U9200,U9250 CRITICAL VRAM_512_HYNIX 333S0423 IC,SGRAM,GDDR3,16Mx32,800MHZ,136 FBGA U8400,U8450,U8500,U8550 CRITICAL VRAM_256_SAMSUNG 333S0424 IC,SGRAM,GDDR3,16Mx32,900MHZ,136 FBGA U8400,U8450,U8500,U8550 CRITICAL VRAM_256_HYNIX B ISL9504B SMC_BLANK TABLE_ALT_HEAD PART NUMBER ALTERNATE FOR PART NUMBER 157S0011 157S0030 BOM OPTION REF DES COMMENTS: ALL E&E alt to TDK/BI-Tech magnetics BOM Configuration TABLE_ALT_ITEM A SYNC_MASTER=N/A SYNC_DATE=N/A TABLE_ALT_ITEM 152S0476 152S0276 ALL Inductor alternate NOTICE OF PROPRIETARY PROPERTY TABLE_ALT_ITEM 353S1681 353S1294 ALL TI alt to National THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING TABLE_ALT_ITEM 138S0603 138S0602 ALL Murata alt to Samsung 353S1681 353S1294 ALL LMV2011,OPAMP GBW 152S0684 152S0368 ALL Maglayers alt to Dale/Vishay 152S0683 152S0276 ALL Maglayers alt to Dale/Vishay 104S0023 104S0018 ALL Cyntec alt to sense resistor 104S0024 104S0017 ALL Panasonic alt to FW resistor I TO MAINTAIN THE DOCUMENT IN CONFIDENCE TABLE_ALT_ITEM II NOT TO REPRODUCE OR COPY IT TABLE_ALT_ITEM III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART TABLE_ALT_ITEM SIZE DRAWING NUMBER D TABLE_ALT_ITEM APPLE INC TABLE_ALT_ITEM SCALE SHT NONE REV 051-7413 15.0.0 OF 89 A PROTO D C B 0.1.0: 04/26/07 04/26/07 04/26/07 04/26/07 04/26/07 04/26/07 04/26/07 04/30/07 05/01/07 0.1.2: 05/08/07 05/08/07 0.2.0: 05/10/07 05/10/07 0.3.0: 05/14/07 05/14/07 0.4.0: 05/22/07 05/22/07 05/22/07 0.5.0: 06/06/07 06/06/07 06/06/07 06/06/07 0.6.0: 06/07/07 06/18/07 06/18/07 06/18/07 06/19/07 06/20/07 0.7.0: 06/25/07 06/25/07 06/25/07 06/25/07 06/25/07 06/25/07 0.8.0: 06/27/07 0.9.0: 06/27/07 06/27/07 0.10.0: 06/27/07 0.11.0: 06/27/07 06/27/07 0.12.0: 07/02/07 07/02/07 07/02/07 0.13.0: 07/05/07 07/05/07 1.2.0: 08/02/07 08/02/07 Design branched from 051-7225-A Clock Termination: Removed support for SLG8LP537 device (GPU_CLK_27M/27MSS muxes, etc) Clock Termination: Added S0-powered AND gate between GPU_PGOOD and SLG2AP101 enable pin to eliminate leakage path (rdar://5086613) SB Misc: Removed EXTGPU_RST_L support for reseting the GPU (hardware control only) Power Control: Removed U7858 and R7860 Tied SMC_PM_G2_EN/PM_G2_EN directly to S5 regulators SB Decoupling: Replaced L2700 with 155S0333 for AVL updates FW Port Power: Replaced D4260 with proper symbol (instead of table) FW Port Power: Updated U4210 to 353S1744 for AVL updates Current Sensors: Changed R5425/35/45 to RES_SENSE symbol which implements kelvin sensing without the need for XW shorts D SB Decoupling: Changed C2703 to 138S0578 per Intel recommendations (rdar://5185100) GPU Straps: Stuffed R8728 to put GPU PEG I/F into mobile mode (rdar://5188253) Thermal Sensors: Added SIGNAL_MODEL=EMPTY properties to thermal sense diff pairs (rdar://5192397) Current Sensors: Added SIGNAL_MODEL=EMPTY properties to current sense diff pairs (rdar://5192397) Power Control: Added U7858,U7859 to properly enable/disable S5 regulators (rdar://TBD) 5V/3.3V Regulators: Added C7307,C7308 to allow soft-start control of S5 regulators (rdar://TBD) Power Control: Added C7858 to decouple U7858/59 GPU Vcore: Removed Power Control circuitry GPU Straps: Added R8734 to get PCIDEVID3 pullup - GPU FB: Reassigned CS1/BA2 for future memory expansion GPU FB: Changed 22uF, 0805 caps to 10uF, 0603 for future memory expansion GPU FB: Reworked/added FB device Vrefs (with smaller FETs) for future memory expansion Left Clutch I/C: Removed SIM I/F connector - GPU Straps: U8700 changed to TS3V340 only GPU FB: Added support for 1Gb density ICs (added MA and CS1) Left Clutch I/C: Added alternate camera connections (CCP2 I/F) DFM: Added NC nets to allow copper on BGA corner balls (CPU and GPU) GPU FB: Added more 16Mx32 VRAM devices Muxed Gfx: Began removing support for this feature - GPU VCORE: U8900 Changed to IMVP6 FB REGULATOR: Added U9300 Muxed Gfx: Removed LVDS/BKLT muxes and support Power Fet: Removed 1V8 and 1V25 Fets Current Sense: Removed U5410 NBGfx Sense Regulators: Changed Q7320,Q7360,Q7410,Q7460,Q7620 to SI7110N C Power Fet: Removed 1v8 S0 Fet, cleaned up aliasing Current Sense: Added 1v8 FB current sense GPU VCORE: Added additional High side Input Cap MUX Gfx: Delete GPU PGOOD Monitor Aliasing:Cleanup BOM: Changed BOM option table for M87 Power CTL:Added 1.25 PGOOD/3V3 GPU EN,Moved 1V8_S3 to pgood chain LCC: Added Camera/MIC pins DVI: Removed SB Hotplug Detect support(muxed gfx) Aliasing: Moved pages back in sync with T9, aliasing now on separate page Regulators: Changed L7100,L7101 to 4mm 152S0433 USB: Change to active enable USB ports Regulators: Changed U8900 to use VID instead of Feedback resistors B EVT 4.1.0: 08/09/07 Current Sense: Change Q5322 TO FDN337 to accommodate TH1H 08/09/07 Ethernet: Change T3900,T3901 to 157S0053 5.1.0: 08/13/07 Regulators: Change GPUVCORE VID pullup/pulldowns to 2.2K DVT 10.0.0: 09/21/07 BOM OPTION: Add 2.4Ghz 256MB VRAM Config, change 2.5Ghz Conifgs to 512MB VRAM Revision History SYNC_MASTER=N/A A SYNC_DATE=N/A NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC SCALE SHT NONE REV 051-7413 15.0.0 OF 89 A Functional Test Points Fan Connectors TRUE TRUE TRUE D TRUE TRUE TRUE TRUE TRUE TRUE 52 FAN_LT_PWM FAN_LT_TACH 52 52 FAN_RT_PWM FAN_RT_TACH SMC_BS_ALRT_L =SMBUS_BATT_SCL =SMBUS_BATT_SDA GND_BATT TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE 45 46 56 48 56 48 56 56 52 52 LPC+ Debug Connector Left I/O Power Connector FUNC_TEST C CPU FSB NO_TESTs FUNC_TEST TRUE TRUE =PP3V3_S5_LPCPLUS =PP5V_S0_LPCPLUS TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE LPC_AD LPC_AD LPC_FRAME_L PM_CLKRUN_L BOOT_LPC_SPI_L SMC_TMS DEBUG_RESET_L SMC_TRST_L SMC_TDO SMC_MD1 SMC_TX_L FWH_INIT_L PCI_CLK33M_LPCPLUS LPC_AD LPC_AD INT_SERIRQ PM_SUS_STAT_L SMC_TDI SMC_TCK SMC_RESET_L SMC_NMI SMC_RX_L LINDACARD_GPIO TRUE TRUE 47 47 =PPBUS_G3H_LIO_CONN GND 56 23 45 47 23 45 47 23 45 47 25 45 47 NB NO_TESTs NO_TEST FUNC_TEST =PP5V_S0_FAN_LT ICT Test Points Battery Digital Connector FUNC_TEST NO_TEST FSB_A_L FSB_ADS_L FSB_ADSTB_L FSB_BNR_L FSB_BREQ0_L FSB_D_L FSB_DBSY_L FSB_DINV_L FSB_DRDY_L FSB_DSTB_L_N FSB_DSTB_L_P FSB_HIT_L FSB_HITM_L FSB_LOCK_L FSB_REQ_L 10 14 80 TRUE TP_NB_NC NC_NB_NC 16 10 14 80 10 14 80 10 14 80 D 10 14 80 10 14 80 10 14 80 10 14 80 10 14 80 10 14 80 10 14 80 10 14 80 10 14 80 10 14 80 10 14 80 Request for at least 10 GND test points GPU NO_TESTs NOTE: 10 additional GND test points are called out separately in these notes 24 47 RTC Battery Connector 45 46 47 28 47 FUNC_TEST 45 47 TRUE TRUE 45 46 47 45 47 PPVBATT_G3_RTC GND 28 43 45 46 47 47 Current Sense Calibration 30 47 85 FUNC_TEST 23 45 47 23 45 47 25 45 47 TRUE TRUE ISENSE_CAL_EN =PP5V_S0_ISENSECAL TRUE TRUE =PPVCORE_S0_CPU_REG =PPVCORE_GPU_REG 45 49 49 25 45 46 47 45 46 47 45 46 47 49 58 49 73 C TPs per 45 46 47 GND TRUE TPs, with each of above TP pairs 45 47 43 45 46 47 25 47 Left Clutch Barrel Connector Left ALS Connector FUNC_TEST FUNC_TEST TRUE TRUE TRUE TRUE =PP3V3_S3_LTALS ALS_GAIN LTALS_OUT GND 79 45 53 79 TRUE TRUE TRUE TRUE B 44 24 44 83 24 44 83 Other Func Test Points FUNC_TEST I554 =PP5V_S3_CAMERA USB_CAMERA_N USB_CAMERA_P =PP5V_S3_WWAN 53 79 Thermal Diode Connectors I553 TRUE TRUE TRUE TRUE FUNC_TEST HSTHMSNS_D_P HSTHMSNS_D_N RSFSTHMSNS_D_P RSFSTHMSNS_D_N CPUTHMSNS_D2_P CPUTHMSNS_D2_N 51 88 51 88 TRUE TRUE PM_SYSRST_L SMC_ONOFF_L 25 28 45 45 46 79 51 88 51 88 51 88 51 88 CPUTHMSNS can not be supported due to layout constraints B System Validation TPs FUNC_TEST TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE FUNC_TEST CPU_PWRGD CPU_DPSLP_L PM_DPRSLPVR CPU_DPSLP_L PM_LAN_ENABLE PCI_RST_L PM_RSMRST_L PM_SB_PWROK SB_RTC_RST_L PM_STPCPU_L PM_STPPCI_L VR_PWRGD_CLKEN VR_PWRGOOD_DELAY FSB_CPURST_L FSB_CPUSLP_L FSB_DPWR_L NB_SB_SYNC_L 10 13 23 80 10 23 80 16 25 58 80 10 23 80 25 45 24 28 25 45 25 28 23 28 25 29 30 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE IMVP_VR_ON IMVP_DPRSLPVR PM_SLP_S3_L PM_S4_STATE_L PM_SLP_S5_L PM_ENET_EN P1V8P1V5P1V05S0_PGOOD CPU_DPRSTP_L IMVP6_VID TRUE TRUE TRUE PLT_RST_L NB_RESET_L GPU_RESET_L SMC_LRESET_L TRUE TRUE TRUE TRUE TRUE TRUE CPU_STPCLK_L FSB_CLK_NB_P FSB_CLK_NB_N NB_CLKREQ_L NB_CLK100M_PCIE_P NB_CLK100M_PCIE_N 25 29 30 25 28 16 28 58 45 58 58 80 25 36 40 45 64 25 45 64 25 45 46 36 64 64 10 16 23 58 80 12 58 80 24 28 16 28 28 65 28 45 10 13 14 80 10 14 80 10 14 80 16 25 10 23 80 14 30 85 14 30 85 16 29 16 30 85 Functional / ICT Test 16 30 85 SYNC_MASTER=(MASTER) A SYNC_DATE=(MASTER) NOTICE OF PROPRIETARY PROPERTY TRUE CPU_THERMTRIP_R THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING 23 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC SCALE SHT NONE REV 051-7413 15.0.0 OF 89 A "G3Hot" (Always-Present) Rails 56 =PPBUS_G3H_LIO_CONN 3.3V-2.5V Rails PPBUS_G3H =PPBUS_S5_FWPWRSW 34 =PPDCIN_G3H_LIO_CONN =PP3V42_G3H_REG 57 58 58 59 59 59 60 61 62 77 60 73 PPDCIN_G3H 57 =PP3V3_S3_FET PP3V42_G3H 28 34 43 48 =PP3V3_S3_P1V8ISNS =PP3V3_S3_LTALS =PP3V3_S3_TOPCASE =PP3V3_S3_REMTHMSNS =PP3V3_S3_PWRCTL 47 46 64 57 =PP3V3_S0_FET PP5V_S5 =PP5V_S5_SB =PP5V_S5_P1V8FB 27 77 =PP5V_S5_P1V25S0FET =PP5V_S5_P1V25ENET =PP5V_S5_P1V05S0 =PP5V_S5_P1V8DDRREG 57 60 60 61 =PP5V_S5_PWRCTL =PP5V_S5_GPUVCORE =PP5V_S3_RTUSB =PP5V_S3_P5VS3FET =PP5V_S0_P5VS0FET =PP5V_S3_FET 64 73 43 57 57 PP5V_S3 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5V MAKE_BASE=TRUE =PP5V_S3_SYSLED =PP5V_S3_CAMERA =PP5V_S3_WWAN =PP5V_S3_IR =PP5V_S3_TOPCASE =PP5V_S0_KBDLED =PP5V_S0_ISENSECAL =PP5V_S5_P1V5S0 B 57 =PP5V_S0_FET 24 25 27 25 46 44 79 79 53 49 =PP3V3_S0_NBCOREISNS =PP3V3_S0_ALLSYSPG =PP3V3_S0_DDC_LCD 64 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5V MAKE_BASE=TRUE =PP5V_S0_SB =PP5V_S0_ODD =PP5V_S0_LPCPLUS =PP5V_S0_FAN_LT =PP5V_S0_FAN_RT =PP5V_S0_CPU_IMVP 27 =PP3V3R5V_GPU_GPUISENS =PP3V3_S0_XDP =PP3V3_S0M_CK505 42 47 50 =PP1V8_S3_ISNS =PPSPD_S0M_MEM_A =PPSPD_S0M_MEM_B =PP3V3_S0MWOL_SB_CLINK0 =PP3V3_S0MWOL_SB_VCCCL3_3 =PP3V3_S0MWOL_SB_VCCLAN3_3 =PP3V3_S0_PWRCTL =PP3V3_S0_CCP2 =PP3V3_S0_P1V25ISNS 58 =PP5V_S0_DVI_DDC 78 =PP5V_S0_HDD =PP5V_S0_ODDPWREN =PP5V_S0_PCIREQFIX =PP5V_S0_MIC 79 42 42 A =PPVCORE_S0_CPU_REG 48 74 62 =PP1V5_S0_REG MAX I = ?.??A 57 64 38 38 48 50 =PP1V25_S0_ISNS PP1V25_S0_ISNS 79 79 51 64 16 19 21 19 21 21 23 25 24 26 27 60 =PP1V05_S0_REG 11 12 22 63 27 =PP1V95_FW_LDO PP1V95_FW MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.95V MAKE_BASE=TRUE 26 27 26 27 =PP1V95_FW_PHY =PP1V8_FW_PHYOSC 26 26 27 26 26 27 28 28 29 30 42 46 47 48 =PP3V3_S0GPU_FET PP3V3_S0GPU MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V MAKE_BASE=TRUE =PP3V3_GPU_VDD33 =PP3V3_GPU_MIO =PP3V3_GPU_DAC =PP3V3_GPU_DVI 21 21 21 50 =PPVCORE_S0_NB_R 21 26 27 51 =PP0V9_S3_VTTR_BUF 70 70 74 67 71 =PP3V3_S0GPU_TMDS_FET 13 61 =PP0V9_S0_VTT_LDO 72 18 21 10 11 12 13 50 =PP1V8_S0GPU_ISNS PP1V8_S0GPU_ISNS 64 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.8V MAKE_BASE=TRUE 21 21 =PP1V8_GPU_FB_VDD =PP1V8_GPU_FB_VDDQ =PP1V8_GPU_FBVDDQ =PP1V8_GPU_FBIO =PP1V8_GPU_IFPX 23 26 27 46 14 30 19 21 50 68 69 75 76 68 69 75 76 66 67 72 21 26 27 73 49 =PPVCORE_GPU_REG PPVCORE_GPU MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.2V MAKE_BASE=TRUE B 66 =PP1V8_S0GPU_REG PP1V8_S0GPU_ISNS_R MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.25V MAKE_BASE=TRUE =PP1V8_S0GPU_ISNS_R 50 16 16 31 32 PP0V9_S0 MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0.9V MAKE_BASE=TRUE 29 30 31 =PP0V9_S0M_MEM_TERM 33 32 25 "ENET" Rails 26 27 26 27 64 36 =PP3V3_ENET_FET PP3V3_ENET MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V MAKE_BASE=TRUE 50 PP1V25_S0 60 =PPVOUT_ENET_AVDDLDO Power Aliases 35 36 SYNC_MASTER=(MASTER) PP1V9_ENET MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.9V MAKE_BASE=TRUE =PP1V25_ENET_REG THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING 35 PP1V25_ENET I TO MAINTAIN THE DOCUMENT IN CONFIDENCE MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.25V MAKE_BASE=TRUE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART =PP1V2_ENET_PHY =PP1V25_S0_P1V25S0FET 50 SYNC_DATE=(MASTER) NOTICE OF PROPRIETARY PROPERTY 35 SIZE 57 APPLE INC 35 DRAWING NUMBER D REV 051-7413 SCALE SHT NONE 78 50 =PP1V8R2V5_ENET_PHY 73 71 PP3V3_S0GPU_TMDS Yukon EC will not be supported 64 MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V MAKE_BASE=TRUE PP0V9_S3_MEM_VREF =YUKON_EC_PP2V5_ENET 48 18 21 =PP0V9_S3M_MEM_NBVREFA =PP0V9_S3M_MEM_NBVREFB =PP0V9_S3M_MEM_DIMMVREFA =PP0V9_S3M_MEM_DIMMVREFB 64 71 70 MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0.9V MAKE_BASE=TRUE 50 71 =PP3V3_GPU_PWRCTL =PP3V3_GPU_VCORELOGIC =PP3V3_GPU_HDCP 65 77 61 C 78 =PPVCORE_GPU =PPVCORE_S0_NB 58 78 =PP3V3_GPU_SMBUS_SMC_0_S0 65 52 52 72 65 MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0.9V MAKE_BASE=TRUE 51 70 71 =PP3V3_GPU_VGASYNC =PP3V3_GPU_TMDS =PP3V3_GPU_VIDEOMUX 21 PPVCORE_S0_NB_R 50 70 19 21 48 50 39 "GPU" Rails 34 =PP3V3_GPU_TMDSBIAS =PP3V3_GPU_IFPCD_IOVDD =PP1V05_S0M_NB_VCCAXM =PP1V05_S0_CPU =PP1V05_S0_NB_FOLLOW =PP1V05_S0_NB_PCIE =PP1V05_S0_SB_CPU_IO =PP1V05_S0_SMC_LS =PP1V25R1V05_S0_FSB_NB =PP1V25R1V05_S0_NB_VTT =PPVCORE_S0_NBCOREISNS =PPVCORE_S0_NB_FOLLOW =PPVCORE_S0_SB 27 39 26 27 PP1V05_S0 26 D =PP3V3_FW_PHY 39 41 =PP3V3_FW_LATEVG_ACTIVE 40 =PP3V3_FW_LATEVG 41 =PPVIN_FW_P1V95FW 63 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V MAKE_BASE=TRUE 26 27 41 PP3V3_FW 26 27 26 27 41 =PPVP_FW_PORT1 MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V MAKE_BASE=TRUE 64 =PP1V25_S0M_NB_PLL =PP1V25_S0M_NB_VCC =PP1V25_S0M_NB_VCCA =PP1V25_S0_NB_VCCDMI =PP1V25_S0_NB_PLL =PP1V25_S0_NB_VCC =PP1V25_S0_SB_DMI =PP1V2_GPU_PEX_IOVDDQ =PP1V2_GPU_PEX_IOVDD =PP1V2_GPU_PEX_PLLXVDD =PP1V2_GPU_PLLVDD =PP1V2_GPU_H_PLLVDD =PP1V2_GPU_VID_PLLVDD =PP1V2_GPU_FBPLLAVDD 11 12 49 =PP1V25_S0_ISNS_R =PP3V3_FW_REG 88 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.25V MAKE_BASE=TRUE 50 36 18 PPVP_FW_PORTB_UF MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.5V MAKE_BASE=TRUE 57 54 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.25V MAKE_BASE=TRUE =PPVCORE_S0_NB_GFX 63 16 18 21 53 48 63 =PPVP_FW_PORT0 MAKE_BASE=TRUE =PP1V5_S0_CPU =PP1V5_S0_NB_TVDAC =PP1V5_S0_SB =PP1V5_S0_SB_VCC1_5_A_ARX =PP1V5_S0_SB_VCC1_5_A_ATX =PP1V5_S0_SB_VCC1_5_A =PP1V5_S0_SB_VCCUSBPLL =PP1V5_S0_SB_VCC1_5_A_USB_CORE =PP1V5_S0_LIO 36 39 21 PP1V5_S0 57 40 MAKE_BASE=TRUE 40 57 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.3 mm VOLTAGE=1.25V MAKE_BASE=TRUE =PP1V25_S0_FET PPVP_FW_PORTA_UF 64 PPVCORE_S0_CPU 57 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.3 mm VOLTAGE=33V MAKE_BASE=TRUE =PPVP_FW_SUMNODE =PPVP_FW_CPS =PPVP_FW_P3V3FW 40 =PP1V8_S3M_NB_VCC =PP1V8_S3M_MEM_NB 55 63 PPVP_FW 50 =PP3V3_ENET_PHY =PP3V3_ENET_AVDDLDO =PPVCORE_S0_CPU =PPBU_S0_P3V3FW =PPBUS_S5_FW_FET 32 88 PP1V8_S3_ISNS 46 Chipset "VCore" Rails 58 49 PPBUS_FW_FWPWRSW_F MAKE_BASE=TRUE 31 88 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.8V MAKE_BASE=TRUE 26 27 52 52 40 26 27 26 27 62 PP5V_S0 40 38 25 64 88 =PP3V3_S0_NB_VCCHV =PP3V3_S0_NB_VCCA_PEG_BG =PP3V3_S0_NB_FOLLOW =PP3V3_S0_SB_GPIO =PP3V3_S0_SB_PCI =PP3V3_S0_SB_VCC3_3_IDE =PP3V3_S0_SB_VCC3_3_PCI =PP3V3R1V5_S0_SB_VCCHDA =PP3V3_S0_SB_VCC3_3_DMI =PP3V3_S0_SB_VCC3_3_VCCPCORE =PP3V3_S0_SB_VCCGLAN3_3 =PP3V3_S0_SB_VCC3_3_SATA =PP3V3_S0_SB =PP3V3_S0_SB_PM =PP3V3_S0_RSTBUF =PP3V3_S0_CK505 =PP3V3_S0_IDE =PP3V3_S0_SMC =PP3V3_S0_LPCPLUS =PP3V3_S0_SMBUS_SB =PP3V3_S0_SMBUS_SMC_B_S0 =PP3V3_S0_CPUCOREISNS =PP3V3_S0_GPU1V8ISNS =PP3V3_S0_CPUTHMSNS =PP3V3_S0_GPUTHMSNS =PP3V3_S0_FAN_LT =PP3V3_S0_FAN_RT =PP3V3_S0_IMVP MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5V MAKE_BASE=TRUE "FW" (FireWire) Rails =PP1V8_S3_FW =PP1V8_S3M_MEM_A =PP1V8_S3M_MEM_B =PP1V8_S3_ISNS_R 28 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V MAKE_BASE=TRUE 5V Rails 57 PP3V3_S0 PP1V8_S3 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.8V MAKE_BASE=TRUE 79 45 46 C =PP5V_S5_REG =PP1V8_S3_REG PP3V3_S3 =PP3V3_S3_P3V3ENETFET =PP3V3_S3_FW =PP3V3_S3_PCI =PP3V3_S3_SMBUS_SMC_A_S3 =PP3V3_S3_RTALS =PP3V3_S3_SMS =PP3V3_S3_SMBUS_SMC_MGMT MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.42V MAKE_BASE=TRUE 59 61 88 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V MAKE_BASE=TRUE 64 =PP3V42_G3H_SB_RTC =PP3V42_G3H_LIO =PP3V42_G3H_SMCUSBMUX =PP3V42_G3H_SMBUS_SMC_BSA =PP3V42_G3H_LIDSWITCH =PP3V3_S5_SMC =PP3V3_S5_LPCPLUS =PPVIN_S5_SMCVREF =PP3V42_G3H_PWRCTL 1.8V-0.9V Rails PP3V3_S5 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V MAKE_BASE=TRUE =PP3V3_S5_SB_PM =PP3V3_S5_SB_USB =PP3V3_S5_SB =PP3V3_S5_SB_CLINK1 =PP3V3_S5_SB_GPIO =PP3V3_S5_SB_3V3_VCCSUSHDA =PP3V3_S5_SB_VCCSUS3_3 =PP3V3_S5_SB_VCCSUS3_3_USB =PP3V3_S5_S5PWRGD =PP3V3_S5_SMBUS_SB_ME =PP3V3_S5_ROM =PP3V3_S5_P1V5P1V05PG =PP3V3_S3_P3V3S3FET =PP3V3_S0_LCD =PP3V3_S0_P3V3S0FET =PP3V3_GPU_P3V3GPUFET =PP3V3_S5_PWRCTL MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=18.5V MAKE_BASE=TRUE =PPVIN_G3H_P3V42G3H 64 =PP3V3_S5_REG 40 =PPBUS_S5_P1V25S0FET =PPVIN_S5_CPU_IMVP_VIN =PPVIN_S5_CPU_IMVP =PPVIN_S5_P5VP3V3 =PPVIN_S5_P5VS5 =PPVIN_S5_P3V3S5 =PPVIN_ENET_P1V25ENET =PPVIN_S3_P1V8S3 =PPVIN_S0_P1V5S0 =PPVIN_S0_P1V8FB =PPVIN_S0_P1V05S0 =PPVIN_GPU_GPUVCORE D 59 49 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=12.6V MAKE_BASE=TRUE 15.0.0 OF 89 A 23 Thermal Module Holes EXTGPU_PWR_EN TP_EXTGPU_PWR_EN MAKE_BASE=TRUE TP_USB_EXTDP USB_EXTD_P 24 83 USB_EXTD_N 24 83 MAKE_BASE=TRUE TP_USB_EXTDN Top CPU TM Notch MAKE_BASE=TRUE ZT0985 5P75R2P7 Add buried vias to GND 28 25 Top GPU Right TM Hole ZT0970 ZT0975 ZT0980 5P75R2P7 5P75R2P7 D PM_SB_PWROK =SB_CLINK_MPWROK 25 =NB_CLINK_MPWROK 16 =SMC_SMS_INT 45 PEG_CLK100M_P 85 PEG_CLK100M_N 85 MAKE_BASE=TRUE VR_PWRGOOD_DELAY MAKE_BASE=TRUE 5P75R2P7 Left CPU TM Hole 58 28 16 Right CPU TM Hole 54 Bottom Left GPU TM Hole 65 30 SMC_SMS_INT MAKE_BASE=TRUE PEG_CLK100M_GPU_P D MAKE_BASE=TRUE 65 30 PEG_CLK100M_GPU_N MAKE_BASE=TRUE RAM Door (Torx) Holes ZT0930 3P7R3P2 GND_CHASSIS_RAMDOOR_HOLE_0 TP_MEM_A_A TP_MEM_B_A 3P7R3P2 31 MEM_B_A 32 USB_EXTC_P 24 83 USB_EXTC_N 24 83 MAKE_BASE=TRUE GND_CHASSIS_RAMDOOR_HOLE_1 MEM_A_A MAKE_BASE=TRUE ZT0935 TP_USB_EXTCP MAKE_BASE=TRUE TP_USB_EXTCN MAKE_BASE=TRUE Frame Holes ZT0920 84 24 INT_PIRQE_L IPHS_SW_INT 34 MAKE_BASE=TRUE 3P2R2P7 25 GND_CHASSIS_LVDS_HOLE SB_SLOAD IPHS_SW_BIAS_EN_L 34 MAKE_BASE=TRUE ZT0940 3P7R3P2 GND_CHASSIS_RIGHT_FAN_HOLE C Board Edge Notches (Can’t be PTH) C ZT0945 HOLE-VIA-P5RP25 GND_CHASSIS_RIGHT_FAN_NOTCH ZT0950 HOLE-VIA-P5RP25 GND_CHASSIS_DIMM_NOTCH ZT0955 3P2R2P7 GND_CHASSIS_LIOFLEX_HOLE ZT0965 3P2R2P7 GND_CHASSIS_LINDACARD_HOLE ZT0960 Tooling Holes (Can’t be PTH) B HOLE-VIA-P5RP25 GND_CHASSIS_BATTCONN_HOLE ZT0990 HOLE-VIA-P5RP25 GND_CHASSIS_DVI_HOLE B Digital Ground GND MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM VOLTAGE=0V Signal Aliases SYNC_MASTER=(T9_MLB) A SYNC_DATE=08/23/2006 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING SH0925 OG-503040 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE SHLD-SM-LF II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC SCALE SHT NONE REV 051-7413 15.0.0 OF 89 A OMIT 80 14 BI 80 14 BI 80 14 BI 80 14 BI 80 14 BI 80 14 BI 80 14 BI 80 14 BI 80 14 BI 80 14 BI 80 14 BI 80 14 BI 80 14 BI 80 14 BI 80 14 BI 80 14 BI 80 14 C BI 80 14 BI 80 14 BI 80 14 BI 80 14 BI 80 14 BI 80 14 BI 80 14 BI 80 14 BI 80 14 BI 80 14 BI 80 14 BI 80 14 BI 80 14 BI 80 14 BI 80 14 BI 80 14 BI 80 14 BI 80 23 IN 80 23 OUT 80 23 IN 80 23 IN 80 23 IN 80 23 80 23 IN IN FSB_REQ_L FSB_REQ_L FSB_REQ_L FSB_REQ_L FSB_REQ_L K3 H2 K2 J3 L1 REQ0* REQ1* REQ2* REQ3* REQ4* FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_ADSTB_L Y2 U5 R3 W6 U4 Y5 U1 R4 T5 T3 W2 W5 Y4 U2 V4 W3 AA4 AB2 AA3 V1 A6 A20M* A5 FERR* C4 IGNNE* CPU_STPCLK_L CPU_INTR CPU_NMI CPU_SMI_L D5 C6 B4 A3 M4 N5 T2 V3 B2 F6 D2 D22 D3 BR0* FSB_DEFER_L FSB_DRDY_L FSB_DBSY_L F1 FSB_BREQ0_L CPU_IERR_L CPU_INIT_L IN BI 14 80 BI 14 80 =PP1V05_S0_CPU IERR* INIT* D20 B3 LOCK* H4 FSB_LOCK_L RESET* RS0* RS1* RS2* TRDY* C1 F3 F4 G3 G2 FSB_CPURST_L FSB_RS_L FSB_RS_L FSB_RS_L FSB_TRDY_L HIT* HITM* G6 E4 FSB_HIT_L FSB_HITM_L BPM0* BPM1* BPM2* BPM3* PRDY* PREQ* TCK TDI TDO TMS TRST* DBR* AD4 AD3 AD1 AC4 AC2 AC1 AC5 AA6 AB3 AB5 AB6 C20 80 14 80 BI BI 14 80 BI 14 80 BI 14 80 BI 14 80 10 11 12 13 R1002 54.9 1% 1/16W MF-LF 402 PLACE TESTPOINT ON FSB_IERR_L WITH A GND 0.1" AWAY D 23 47 80 14 80 IN 13 14 80 IN 14 80 IN 14 80 IN 14 80 IN 14 80 OMIT A17* A18* A19* A20* A21* A22* A23* A24* A25* A26* A27* A28* A29* A30* A31* A32* A33* A34* A35* ADSTB1* CPU_A20M_L CPU_FERR_L CPU_IGNNE_L TP_CPU_RSVD0 TP_CPU_RSVD1 TP_CPU_RSVD2 TP_CPU_RSVD3 TP_CPU_RSVD4 TP_CPU_RSVD5 TP_CPU_RSVD6 TP_CPU_RSVD7 TP_CPU_RSVD8 DEFER* DRDY* DBSY* H5 F21 E1 BI STPCLK* LINT0 LINT1 SMI* XDP_BPM_L XDP_BPM_L XDP_BPM_L XDP_BPM_L XDP_BPM_L XDP_BPM_L XDP_TCK XDP_TDI XDP_TDO XDP_TMS XDP_TRST_L XDP_DBRESET_L BI 14 80 BI 14 80 BI 13 80 BI 13 80 BI 13 80 BI 13 80 BI 13 80 =PP1V05_S0_CPU R10031 80 14 BI 80 14 BI 1% 1/16W MF-LF 402 80 14 BI 80 14 BI 80 14 BI 80 14 BI 54.9 13 80 10 13 80 80 14 BI IN 10 13 80 80 14 BI OUT 10 13 80 80 14 BI IN 10 13 80 80 14 BI IN 10 13 80 80 14 BI 80 14 BI 80 14 BI 80 14 BI 80 14 BI 80 14 BI 80 14 BI OUT 13 28 R1004 5% 1/16W MF-LF 402 THERMAL THERMTRIP* RSVD0 RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 RSVD6 RSVD7 RSVD8 D21 A24 B25 CPU_PROCHOT_L CPU_THERMD_P CPU_THERMD_N C7 PM_THRMTRIP_L OUT OUT 51 88 OUT 51 88 OUT 16 23 46 80 BCLK0 BCLK1 A22 A21 FSB_CLK_CPU_P FSB_CLK_CPU_N IN 30 85 IN 30 85 46 58 80 PM_THRMTRIP# SHOULD CONNECT TO ICH AND GMCH WITHOUT T (NO STUB) H CLK 13 12 11 10 =PP1V05_S0_CPU R1005 1K 1% 1/16W MF-LF 402 R1020 80 13 10 XDP_TDI D16* D17* D18* D19* D20* D21* D22* D23* D24* D25* D26* D27* D28* D29* D30* D31* DSTBN1* DSTBP1* DINV1* BI R10061 XDP_TMS N22 FSB_D_L K25 FSB_D_L P26 FSB_D_L 80 14 BI R23 FSB_D_L 80 14 BI L23 FSB_D_L 80 14 BI M24 FSB_D_L 80 14 BI L22 FSB_D_L 80 14 BI M23 FSB_D_L 80 14 BI P25 FSB_D_L 80 14 BI P23 FSB_D_L 80 14 BI P22 FSB_D_L 80 14 BI T24 FSB_D_L 80 14 BI R24 FSB_D_L 80 14 BI L25 FSB_D_L 80 14 BI T25 FSB_D_L 80 14 BI N25 FSB_D_L 80 14 BI FSB_DSTB_L_N L26 80 14 BI FSB_DSTB_L_P M26 80 14 BI N24 FSB_DINV_L 80 14 BI 0.5" MAX LENGTH FOR CPU_GTLREF AD26 80 CPU_GTLREF C23 CPU_TEST1 D25 CPU_TEST2 C24 TP_CPU_TEST3 AF26 CPU_TEST4 AF1 TP_CPU_TEST5 NOSTUFF A26 TP_CPU_TEST6 C1000 0.1uF C3 TP_CPU_TEST7 10% 16V B22 CPU_BSEL 80 30 OUT X5R 402 B23 CPU_BSEL 80 30 OUT C21 CPU_BSEL 80 30 OUT BI IN B 80 13 10 D0* D1* D2* D3* D4* D5* D6* D7* D8* D9* D10* D11* D12* D13* D14* D15* DSTBN0* DSTBP0* DINV0* 80 14 BI 54.9 R1021 54.9 2.0K =PP1V05_S0_CPU 10 11 12 13 1% 1/16W MF-LF 402 1% 1/16W MF-LF 402 1% 1/16W MF-LF 402 PLACE C1000 CLOSE TO CPU_TEST4 PIN MAKE SURE CPU_TEST4 IS REFERENCED TO GND R1024 54.9 XDP_TDO 80 13 10 1% PLACEMENT_NOTE=Place R1024 near ITP connector (if present) 1/16W FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_DSTB_L_N FSB_DSTB_L_P FSB_DINV_L E22 F24 E26 G22 F23 G25 E25 E23 K24 G24 J24 J23 H22 F26 K22 H23 J26 H26 H25 80 14 68 PROCHOT* THERMDA THERMDC 10 11 12 13 80 14 BI 80 14 BI 80 13 10 XDP_TRST_L 649 OF MISC Y22 AB24 V24 V26 V23 T22 U25 U23 Y25 W22 Y23 W24 W25 AA23 AA24 AB25 Y26 AA26 U22 FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_DSTB_L_N FSB_DSTB_L_P FSB_DINV_L D48* D49* D50* D51* D52* D53* D54* D55* D56* D57* D58* D59* D60* D61* D62* D63* DSTBN3* DSTBP3* DINV3* AE24 AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21 AC22 AD23 AF22 AC23 AE25 FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_DSTB_L_N FSB_DSTB_L_P FSB_DINV_L AF24 AC20 COMP0 COMP1 COMP2 COMP3 R26 U26 AA1 Y1 DPRSTP* DPSLP* DPWR* PWRGOOD SLP* PSI* E5 B5 D24 D6 D7 AE6 80 80 80 80 BI 14 80 BI 14 80 BI 14 80 BI 14 80 BI 14 80 BI 14 80 BI 14 80 BI 14 80 BI 14 80 BI 14 80 BI 14 80 BI 14 80 BI 14 80 BI 14 80 BI 14 80 BI 14 80 BI 14 80 BI 14 80 BI 14 80 BI 14 80 BI 14 80 BI 14 80 BI 14 80 BI 14 80 BI 14 80 BI 14 80 BI 14 80 BI 14 80 BI 14 80 BI 14 80 BI 14 80 BI 14 80 BI 14 80 BI 14 80 BI 14 80 BI 14 80 BI 14 80 BI 14 80 C LAYOUT NOTE: COMP0,2 CONNECT WITH ZO=27.4OHM, MAKE TRACE LENGTH SHORTER THAN 0.5" COMP1,3 CONNECT WITH ZO=55OHM, MAKE TRACE LENGTH SHORTER THAN 0.5" R1016 27.4 1% 1/16W MF-LF 402 1% 1/16W MF-LF 402 R1018 R1019 1% 1/16W MF-LF 402 54.9 CPU_COMP CPU_COMP CPU_COMP CPU_COMP CPU_DPRSTP_L CPU_DPSLP_L FSB_DPWR_L CPU_PWRGD FSB_CPUSLP_L CPU_PSI_L R1017 54.9 IN 16 23 58 80 IN 23 80 IN 14 80 IN 13 23 80 IN 14 80 OUT B 27.4 1% 1/16W MF-LF 402 28 54.9 R1023 FCBGA D32* D33* D34* D35* D36* D37* D38* D39* D40* D41* D42* D43* D44* D45* D46* D47* DSTBN2* DSTBP2* DINV2* R1030 R1022 XDP_TCK PENRYN NOSTUFF MF-LF 402 80 13 10 GTLREF TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 TEST7 BSEL0 BSEL1 BSEL2 U1000 DATA GRP BI FSB_ADS_L FSB_BNR_L FSB_BPRI_L DATA GRP BI 80 14 H1 E2 G5 DATA GRP 80 14 ADS* BNR* BPRI* DATA GRP BI CONTROL 80 14 XDP/ITP SIGNALS BI A3* A4* PENRYN FCBGA A5* OF A6* A7* A8* A9* A10* A11* A12* A13* A14* A15* A16* ADSTB0* ADDR GROUP0 80 14 U1000 FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_ADSTB_L ADDR GROUP1 BI ICH BI 80 14 RESERVED D 80 14 J4 L5 L4 K5 M3 N2 J1 N3 P5 P2 L2 P4 P1 R1 M1 NOSTUFF R10121 1% 1/16W MF-LF 402 1K 5% 1/16W MF-LF 402 1% 1/16W MF-LF 402 5% 1/16W MF-LF 402 NOSTUFF R1007 1K 5% 1/16W MF-LF 402 CPU FSB SYNC_MASTER=T9_NOME A SYNC_DATE=03/16/2007 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC SCALE SHT NONE REV 051-7413 15.0.0 OF 10 89 A ... TABLE_BOMGROUP_ITEM M87 BOM Groups TABLE_BOMGROUP_HEAD BOM GROUP BOM OPTIONS M87_ COMMON ALTERNATE,COMMON ,M87_ COMMON1 ,M87_ COMMON2 ,M87_ PROGPARTS M87_ COMMON1 ISL9504B,ONEWIRE_PU,LPCPLUS,SMC_DEBUG_NO M87_ COMMON2... PCBA,2.6GHZ,512HY_VRAM ,M87 M87_COMMON,EEE_Z3H,CPU_2_6GHZ,FB_512_HYNIX 630-9213 PCBA,2.4GHZ,256SAM_VRAM ,M87 M87_COMMON,EEE_ZUP,CPU_2_4GHZ,FB_256_SAMSUNG 630-9238 PCBA,2.4GHZ,256HY_VRAM ,M87 M87_COMMON,EEE_043,CPU_2_4GHZ,FB_256_HYNIX... PCBA,2.5GHZ,512SAM_VRAM ,M87 M87_COMMON,EEE_Z3G,CPU_2_5GHZ,FB_512_SAMSUNG 630-9091 PCBA,2.6GHZ,512SAM_VRAM ,M87 M87_COMMON,EEE_Z3J,CPU_2_6GHZ,FB_512_SAMSUNG 630-9088 PCBA,2.5GHZ,512HY_VRAM ,M87 M87_COMMON,EEE_Z3F,CPU_2_5GHZ,FB_512_HYNIX