8 CK APPD OROYA ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5% ALL CAPACITANCE VALUES ARE IN MICROFARADS ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ REV ZONE ECN ENG APPD DESCRIPTION OF CHANGE DATE ? ? ? ? DATE ? 03/20/2007 - DVT (.csa) Page D TABLE_TABLEOFCONTENTS_HEAD TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM C TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM B TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 37 38 39 40 41 42 43 44 46 47 Contents Table of Contents System Block Diagram Power Block Diagram Power Block Diagram BOM Configuration Revision History Functional / ICT Test Power Aliases Signal Aliases CPU FSB CPU Power & Ground CPU Decoupling & VID eXtended Debug Port (XDP) NB CPU Interface NB PEG / Video Interfaces NB Misc Interfaces NB DDR2 Interfaces NB Power NB Power NB Grounds NB Standard Decoupling NB Graphics Decoupling SB Enet, Disk, FSB, LPC SB PCI, PCIe, DMI, USB SB Pwr Mgt, GPIO, Clink SB Power & Ground SB Decoupling SB Misc Clock (CK505) Clock Termination DDR2 SO-DIMM Connector A DDR2 SO-DIMM Connector B Memory Active Termination Left I/O Board Connector Ethernet (Yukon) Yukon Power Control Ethernet Connector FireWire Link (TSB83AA22) FireWire PHY (TSB83AA22) FireWire Port Power FireWire Ports PATA Connector External USB Connector Left Clutch Barrel Interconnect Date Sync N/A (.csa) Page TABLE_TABLEOFCONTENTS_HEAD N/A 08/23/2006 TABLE_TABLEOFCONTENTS_ITEM (T9_MLB) 08/23/2006 TABLE_TABLEOFCONTENTS_ITEM (T9_MLB) N/A TABLE_TABLEOFCONTENTS_ITEM N/A N/A TABLE_TABLEOFCONTENTS_ITEM N/A N/A TABLE_TABLEOFCONTENTS_ITEM N/A (MASTER) TABLE_TABLEOFCONTENTS_ITEM (MASTER) (MASTER) TABLE_TABLEOFCONTENTS_ITEM (MASTER) 08/23/2006 TABLE_TABLEOFCONTENTS_ITEM (T9_MLB) 03/16/2007 TABLE_TABLEOFCONTENTS_ITEM T9_NOME 03/16/2007 TABLE_TABLEOFCONTENTS_ITEM T9_NOME 03/19/2007 TABLE_TABLEOFCONTENTS_ITEM M76_MLB 12/12/2006 TABLE_TABLEOFCONTENTS_ITEM T9_NOME 03/16/2007 TABLE_TABLEOFCONTENTS_ITEM T9_NOME 03/16/2007 TABLE_TABLEOFCONTENTS_ITEM T9_NOME 03/16/2007 TABLE_TABLEOFCONTENTS_ITEM T9_NOME 03/16/2007 TABLE_TABLEOFCONTENTS_ITEM T9_NOME 03/16/2007 TABLE_TABLEOFCONTENTS_ITEM T9_NOME 03/16/2007 TABLE_TABLEOFCONTENTS_ITEM T9_NOME 03/16/2007 TABLE_TABLEOFCONTENTS_ITEM T9_NOME 01/17/2007 TABLE_TABLEOFCONTENTS_ITEM T9_NOME 03/12/2007 TABLE_TABLEOFCONTENTS_ITEM M76_MLB 03/16/2007 TABLE_TABLEOFCONTENTS_ITEM T9_NOME 03/16/2007 TABLE_TABLEOFCONTENTS_ITEM T9_NOME 03/16/2007 TABLE_TABLEOFCONTENTS_ITEM T9_NOME 03/16/2007 TABLE_TABLEOFCONTENTS_ITEM T9_NOME 01/17/2007 TABLE_TABLEOFCONTENTS_ITEM T9_NOME 08/24/2006 TABLE_TABLEOFCONTENTS_ITEM (T9_MLB) 03/16/2007 TABLE_TABLEOFCONTENTS_ITEM T9_NOME 08/23/2006 TABLE_TABLEOFCONTENTS_ITEM (MASTER) 08/24/2006 TABLE_TABLEOFCONTENTS_ITEM (M59_SYNC) 08/24/2006 TABLE_TABLEOFCONTENTS_ITEM (M59_SYNC) 11/14/2006 TABLE_TABLEOFCONTENTS_ITEM (T9_NOME) 08/24/2006 TABLE_TABLEOFCONTENTS_ITEM (M59_SYNC) 03/16/2007 TABLE_TABLEOFCONTENTS_ITEM T9_NOME 03/16/2007 TABLE_TABLEOFCONTENTS_ITEM T9_NOME 03/19/2007 TABLE_TABLEOFCONTENTS_ITEM M76_MLB 03/19/2007 TABLE_TABLEOFCONTENTS_ITEM M76_MLB 03/19/2007 TABLE_TABLEOFCONTENTS_ITEM M76_MLB 03/19/2007 TABLE_TABLEOFCONTENTS_ITEM M76_MLB 03/19/2007 TABLE_TABLEOFCONTENTS_ITEM M76_MLB (MASTER) TABLE_TABLEOFCONTENTS_ITEM (MASTER) 03/19/2007 TABLE_TABLEOFCONTENTS_ITEM M76_MLB 03/19/2007 TABLE_TABLEOFCONTENTS_ITEM M76_MLB TABLE_TABLEOFCONTENTS_ITEM 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 49 50 51 52 53 54 55 56 58 59 61 69 70 71 72 73 74 75 76 77 78 80 81 82 84 85 86 87 88 89 90 94 95 96 100 101 102 103 104 105 106 107 108 109 Schematic / PCB #’s PART NUMBER D Sync SMC SMC Support LPC+ Debug Connector SMBus Connections Current & Voltage Sensing Current Sensing Thermal Sensors Fan Connectors ALS Support Sudden Motion Sensor (SMS) SPI BootROM PBus-In & Battery Connectors Power FETs IMVP6 CPU VCore Regulator IMVP6 NB Gfx Core Regulator 5V / 3.3V Power Supply 1.25V / 1.05V Power Supply 1.8V DDR2 Supply 1.5V Power Supply FW PHY Power Supplies 3.425V G3Hot Supply & Power Control NV G84M PCI-E NV G84M Core/FB Power NV G84M Frame Buffer I/F GDDR3 Frame Buffer A GDDR3 Frame Buffer B NV G84M GPIO/MIO/Misc GPU Straps NV G84M Video Interfaces GPU (G84M) Core Supply LVDS Display Connector DVI Display Connector LVDS Interface Mux M75 Specific Connectors CPU/FSB Constraints NB Constraints Memory Constraints SB Constraints (1 of 2) SB Constraints (2 of 2) Clock & SMC Constraints FireWire Constraints GPU (G84M) Constraints M75 Specific Constraints M75 Rule Definitions 01/17/2007 T9_NOME (MASTER) (MASTER) 03/19/2007 M76_MLB (MASTER) (MASTER) (MASTER) (MASTER) (MASTER) (MASTER) (MASTER) (MASTER) 03/19/2007 M76_MLB 03/19/2007 M76_MLB 03/19/2007 M76_MLB 03/16/2007 T9_NOME 09/09/2006 (M59_SYNC) 03/19/2007 M76_MLB 01/23/2007 M76_MLB 03/19/2007 M76_MLB 03/19/2007 M76_MLB 03/12/2007 C M76_MLB 03/19/2007 M76_MLB 03/12/2007 M76_MLB 03/19/2007 M76_MLB (MASTER) (MASTER) (MASTER) (MASTER) (MASTER) (MASTER) (MASTER) (MASTER) (MASTER) (MASTER) (MASTER) (MASTER) (MASTER) (MASTER) (MASTER) (MASTER) (MASTER) (MASTER) (MASTER) (MASTER) (MASTER) (MASTER) (MASTER) (MASTER) (MASTER) (MASTER) 08/24/2006 (M59_SYNC) B 01/17/2007 T9_NOME 01/17/2007 T9_NOME 01/17/2007 T9_NOME 01/17/2007 T9_NOME 01/17/2007 T9_NOME 01/17/2007 T9_NOME 01/17/2007 T9_NOME (MASTER) (MASTER) (MASTER) (MASTER) (MASTER) (MASTER) TABLE_TABLEOFCONTENTS_ITEM ALIASES RESOLVED A Date Contents DIMENSIONS ARE IN MILLIMETERS Apple Computer Inc METRIC XX X.XX DRAFTER THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING ENG APPD MFG APPD QA APPD DESIGNER RELEASE SCALE I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART ANGLES QTY DESCRIPTION REFERENCE DES CRITICAL 051-7225 SCHEM,MLB,M75 SCH CRITICAL 820-2101 PCBF,MLB,M75 PCB CRITICAL A NOTICE OF PROPRIETARY PROPERTY DESIGN CK X.XXX BOM OPTION TITLE DO NOT SCALE DRAWING SCHEM,OROYA,M75 NONE DRAWING SIZE TITLE=MLB ABBREV=DRAWING LAST_MODIFIED=Tue Mar 20 20:28:27 2007 THIRD ANGLE PROJECTION MATERIAL/FINISH NOTED AS APPLICABLE D DRAWING NUMBER REV 051-7225 14.0.0 SHT 1 OF 88 CPU U2900 CK 505 2.? GHz Core ~1.2V Pg 10 Clocks Pg 28 J1300/JD000 TERMS Pg 29 UC500 ReGen ITP/XDP CONN Pg Clocks Pg 98 Pg 12/103 Pg 17,18,19 Pg 14 U9120 Power Supply Pg 66 Pg 68-76 Pg 15/16 DIMM DDR2 - Dual Channel 1.8V - 64 Bits 533/667/800? MHz J5810/20/90 Parallel Term ALS SENS Temp Sense CPU GPU Right Side Charger Pg 32 Pg30,31 Misc LVDS MUX DC/Batt Conn J3100 J3200 Main Memory Pg 77 PEG Connector Core 1.05 - 1.25V TV RGB Out GPIO DVI-I NB-GMCH Pg 14 Pg Pg Pg Pg 51 52 52 ?? CLnk Pg 15 Pg 15 U5920 Sudden Motion Detect Pg 56 Pg 79,81 J9000/10 U9250/60 Int Disp Conn Pg 78 GPIO Pg 80 SPI Boot ROM MUX x4 DMI A B,0 BSA BSB ADC Fan Ser Prt SMC Pg 92 Pg 93/4/5 LPC Pg 48 Prt 80, Comm 1, SMC, FWH Pg 124-130 Pg 24 GPIOs J4710 J4720 J4700 Camera/IR Bluetooth Geyser Pg 45 Pg 45 Trackpad/Keyboard Pg 45 USB Pg 23 B Core Pg 25 Pg 24 MUX Pg 23 PCI-E Conns PCI-E PCI-E LPC Conn Pg 57 J4600 USB Connectors Pg 44 UATA UB100 TPM Core 1.05V Ln1 Ln2 Ln3 Ln4 Ln5 Ln6 - x1 2.5 GHz JB200 JB300 JB400 J4630 SB-ICH8 Pg 22 Pg 42 3.3 V 100 MHz Pg 23 SMB J4400 SPI Pg 24 SATA SATA-1 SATA-2 Pg 43 CLnk Pg 46 Linda Fnc U2300 Pg 22 SATA Conn DMI Pg 23 J5100 U6000 Pg 22 SATA-0 1.2 V / 1.5 GHz J4510/20/30 C Pg 58 2.5 GHz J9200 U4900 UATA Conn Pg 51, 115-120 J5600/10/50/60, J5720/30/50 Fan Conn Pg 53, 54 U6100/50 J9200 Source is the LVDS from the PEG based GPU B U5572 U5500 U5550 U??? Pg 55 Pg 15 DMI Power Sense C D J6900/50 Pg 13 U1400 x16 PCI-E SDVO PCI-E J9400 TERMS Pg 98 FSB 64-Bit 800/1066? MHz J8000 T9 Diagram Needs to be updated to M75 U1000 D E-NET CLnk PCI AZALIA Pg 22 Pg 24 Pg 23 Pg 22 DIMM’s J3100 J3200 Clk Gen U2900 UC500 33 MHz 32-Bit U6200 U4000 U???? MDC TSB82AA2 Audio Codec FW-Link Pg 59 Pg ?? Pg 38 100 MHz 8-Bit U3700 A U6300/1 U4100 NINEVEH TSB81BA3 Line In Amp E-NET FW-PHY Pg 60 Pg 35 Pg 39 U6400 U6500 System Block Diagram U6600/10/20 Line Out Amp Line Out Amp Speaker Amps Pg 61 Pg 62 Pg 63 SYNC_MASTER=(T9_MLB) SYNC_DATE=08/23/2006 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT J3400 JB500 J4320 J4630 J4330 JB000 J6800/1/2/3 Mini PCI-E AirPort PCI-E Conn E-NET Conn FireWire Conn PCI Conn Audio Conns Pg 33 Pg 96 Pg 37 Pg 41 Pg 91 Pg 65 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE APPLE COMPUTER INC DRAWING NUMBER D SCALE SHT NONE REV 051-7225 14.0.0 OF 88 A D D C C B B Power Block Diagram SYNC_MASTER=(T9_MLB) A SYNC_DATE=08/23/2006 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE APPLE COMPUTER INC DRAWING NUMBER D SCALE SHT NONE REV 051-7225 14.0.0 OF 88 A D D C C B B Power Block Diagram SYNC_MASTER=N/A A SYNC_DATE=N/A NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE APPLE COMPUTER INC DRAWING NUMBER D SCALE SHT NONE REV 051-7225 14.0.0 OF 88 A BOM Variants TABLE_BOMGROUP_HEAD BOM NUMBER BOM NAME BOM OPTIONS 630-7931 PCBA,OROYA1,M75 M75_COMMON,EEE_X5D,CPU_2_2GHZ,FB_128_SAMSUNG 630-7932 PCBA,OROYA2,M75 M75_COMMON,EEE_X5E,CPU_2_4GHZ,FB_256_SAMSUNG 630-8659 PCBA,OROYA1,VRAM-HY,M75 M75_COMMON,EEE_XXS,CPU_2_2GHZ,FB_128_HYNIX 630-8662 PCBA,OROYA2,VRAM-HY,M75 M75_COMMON,EEE_XXT,CPU_2_4GHZ,FB_256_HYNIX TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM M75 BOM Groups D D TABLE_BOMGROUP_HEAD BOM GROUP BOM OPTIONS M75_COMMON ALTERNATE,COMMON,M75_COMMON1,M75_COMMON2,M75_DEBUG,M75_PROGPARTS M75_COMMON1 EXTGPU_RST_HW,GPU_TMP401,ISL9504B,LVDS_SEL_RESUME,ONEWIRE_PU M75_COMMON2 P1V8S3_1V825,SLG2AP101,SMS_MOT_DIS,YUKON_ULTRA,VGA_TERM_CONN M75_DEBUG SMC_DEBUG_YES,XDP,XDP_CONN,LPCPLUS M75_PROGPARTS BOOTROM_PROG,SMC_PROG BOM GROUP BOM OPTIONS FB_128_SAMSUNG VRAM_128,VRAM_SAMSUNG,VRAM_128_SAMSUNG FB_128_HYNIX VRAM_128,VRAM_HYNIX,VRAM_128_HYNIX FB_256_SAMSUNG VRAM_256,VRAM_SAMSUNG,VRAM_256_SAMSUNG FB_256_HYNIX VRAM_256,VRAM_HYNIX,VRAM_256_HYNIX TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_HEAD TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM Bar Code Labels / EEE #’s C PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL 826-4393 LBL,P/N LABEL,PCB,28MM X MM [EEE:X5D] CRITICAL BOM OPTION EEE_X5D 826-4393 LBL,P/N LABEL,PCB,28MM X MM [EEE:X5E] CRITICAL EEE_X5E 826-4393 LBL,P/N LABEL,PCB,28MM X MM [EEE:XXS] CRITICAL EEE_XXS 826-4393 LBL,P/N LABEL,PCB,28MM X MM [EEE:XXT] CRITICAL EEE_XXT C Module Parts B PART NUMBER QTY REFERENCE DES CRITICAL 337S3457 IC,MDC,SR,E1,QS,2.2G,35W,800FSB,4M,BGA DESCRIPTION U1000 CRITICAL BOM OPTION CPU_2_2GHZ 337S3458 IC,MDC,SR,E1,QS,2.4G,35W,800FSB,4M,BGA U1000 CRITICAL CPU_2_4GHZ 338S0388 IC,GPU,NV G84M,BGA U8000 CRITICAL 338S0426 IC,NB,CRESTLINE,GM,C0,QS,965PM U1400 CRITICAL 338S0427 IC,SB,ICH8M,B1,QS,BGA U2300 CRITICAL 353S1461 IC,ISL9504,SYNC REG CTRL,2PHAS,QFN48,LF U7100 CRITICAL 353S1651 IC,ISL9504B,2PH IMVP6 REG,PMON,QFN48 U7100 CRITICAL ISL9504B 359S0127 IC,68 PIN,CK505,LOW POWER CLOCK GENER U2900 CRITICAL SLG8LP537 359S0130 IC,SLG2AP101,LW PWR CLCK GEN,CK505,QFN68 U2900 CRITICAL SLG2AP101 338S0386 IC,88E8058,GIGABIT ENET XCVR,64P QFN U3700 CRITICAL 338S0274 IC,SMC,HS8/2116 U4900 CRITICAL 341S2004 IC,SMC,DEVELOPMENT,M75 U4900 CRITICAL SMC_PROG 335S0384 IC,16MBIT 8-PIN SPI SERIAL FLASH,SOIC8 U6100 CRITICAL BOOTROM_BLANK 341S2002 IC,EFI ROM,DEVELOPMENT,M75 U6100 CRITICAL BOOTROM_PROG 333S0404 IC,SGRAM,GDDR3,8Mx32,700MHZ,136 FBGA U8400,U8450,U8500,U8550 CRITICAL VRAM_128_SAMSUNG 333S0409 IC,SGRAM,GDDR3,8Mx32,700MHZ,136 FBGA U8400,U8450,U8500,U8550 CRITICAL VRAM_128_HYNIX 333S0382 IC,SGRAM,GDDR3,16Mx32,700MHZ,136 FBGA U8400,U8450,U8500,U8550 CRITICAL VRAM_256_SAMSUNG 333S0401 IC,SGRAM,GDDR3,16Mx32,700MHZ,136 FBGA U8400,U8450,U8500,U8550 CRITICAL VRAM_256_HYNIX PART NUMBER IS ALTERNATE FOR PART NUMBER REF DES COMMENTS: 157S0011 157S0030 ALL E&E alt to TDK/BI-Tech magnetics 152S0476 152S0276 ALL Inductor alternate 353S1681 353S1294 ALL TI alt to National 138S0603 138S0602 ALL Murata alt to Samsung ISL9504A SMC_BLANK B TABLE_ALT_HEAD BOM OPTION TABLE_ALT_ITEM TABLE_ALT_ITEM TABLE_ALT_ITEM TABLE_ALT_ITEM BOM Configuration SYNC_MASTER=N/A A SYNC_DATE=N/A NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE APPLE COMPUTER INC DRAWING NUMBER D SCALE SHT NONE REV 051-7225 14.0.0 OF 88 A 12.8.0: 03/08/07 13.0.0: 03/12/07 13.1.0: 03/13/07 03/14/07 03/14/07 13.2.0: 03/16/07 03/16/07 03/16/07 13.3.0: 03/16/07 13.4.0: 03/19/07 03/19/07 03/19/07 03/19/07 13.5.0: 03/19/07 14.0.0: 03/20/07 03/20/07 See Perforce change notes for updates before Proto Release 12/22/06 Released for Proto (Schem Rev 08, PCB Rev 01) EVT D C DVT (cont’d) PROTO 8.1.0: 01/05/07 01/05/07 8.2.0: 01/08/07 9.0.0: 01/09/07 01/12/07 01/12/07 9.1.0: 01/17/07 01/17/07 01/17/07 01/17/07 01/17/07 01/17/07 01/17/07 01/17/07 9.2.0: 01/17/07 01/18/07 01/18/07 01/18/07 01/18/07 9.3.0: 01/19/07 01/19/07 01/19/07 01/19/07 01/19/07 9.4.0: 01/19/07 01/19/07 9.5.0: 01/22/07 01/22/07 01/22/07 01/22/07 01/22/07 10.0.0: 01/23/07 01/23/07 01/23/07 Clock Termination: Removed NO STUFF property from R3067 GPU FB: Corrected FB CLK termination (added cap and removed connection to VDDQ) GPU FB: Added VREF support for unterminated memory mode (added FETs and pulldown Rs) Temp Sensors: NO STUFFed C5520 (circuit should have only cap) Power Aliases: Moved Ethernet to PP3V3_S3 from S5 (layout improvements) Power Supplies: Minor power supply feedback connection changes from M76 - Power Aliases: Moved LCD panel FET to PP3V3_S5 from S0 SMBus: Changed R5260 & R5261 from 4.7K to 3.3K Sync with T9 noME (6.1.4) to pull in WOL_EN and Wake-on-Wireless support Power FETs: Corrected BOM values for 5V/3.3V S3/S0 FETs Power Sequencing: Added RC delay on PP1V8_S3 switcher enable Testpoints: Removed FUNC_TEST from NB_RESET_L and FSB_DPWR_L per PCB request BOM: Consolidated caps on page 59 from 132S0120 to 132S0131 BOM: Added Hynix BOM configurations Power Aliases: Deleted alias that accidentally eliminated filtering on PP1V5_S0_SB_VCC1_5_B Clock Termination: Changed series termination on all single ended clocks to 33 ohms IMVP: Updated BOMOPTIONs and values for ISL9504B Testpoints: Added NO_TEST property to LVDS_L_DATA_N, _N, _P due to lack of layout space for TP ODD Conn: Reconnected ODD power FET gate control circuitry to properly implement soft start (added one cap) SB Decoupling: Removed filtering for PP1V5_S0_SB_VCCGLANPLL to enable PP1V5_S0 corrections at SB Ethernet Conn: Changed resistor short reference designators from R392x to RX392x Clock Termination: Changed R3050 and R3055 to bypass discrete muxes for pending change to SLG2AP101 Power Sequencing: Added C7859 to create RC delay for 1.5 and 1.05V S0 rails Power Sequencing: Changed power rail for U7850 to PP3V3_S5 to eliminate a leakage path Thermal Sensors: Added R5515/R5516 in case low pass filter is needed for EMC1033 Power Control: Corrected alias connections for 5V/3V3 S5 enable signals BOM Options: Removed HDCP BOM option from stuffing list (feature removed) Constraints: Constrained WWAN_SIM signals to 50 ohms Thermal Sensors/Aliases: Changed mounting pads of Th2H sensor connector to left clutch chassis gnd Thermal Sensors: Replaced EMC1033 with second EMC1043 for improved noise filtering NB GFX: LVDS_VREFL/VREFH changed to single pin nets to prevent LVDS glitches per Intel Yukon Power Control: Crystal caps changed to 18pF (rdar://4946795 and rdar://4945362) D Thermal Sensors: Moved remote sensor U5500 to SMC SMBus "A" and S3 power rail to clear I2C addr clash - Thermal Sensors: Updated U5500 power alias to indicate device should be on S3 rail Power Control: Added U7858 to level shift PM_G2_EN from 3.42V to 5V Power Supplies: For 1.8, 3.3 and 5V, removed VBST 0-ohm series R (rdar://5070179) Power Supplies: For 1.8, 3.3 and 5V, increased cap size to 0603/0805 on VBST caps (rdar://5070179) Power Control: Tied all 5V/3.3V enables (EN1, EN2, EN3, EN5) together as part of PM_G2_EN GPU Vcore: Updated setpoints for GPU Vcore based upon Nvidia Vmin (i.e 1.05V,1.05V,1.05V,1.125V) FB: Changed FB VREF caps to 2x0.0047uF as required in Nvidia PUN 02736-001-v07 (which requests 1x0.01uF) C GPU GPIOs: Added TPs on GPIOs to make G-state externally visible SB GPIOs: Changed SB_GPIO42 to WOW_EN and changed pullup to pulldown (T9_noME change 40787) LIO Conn: Removed unnecessary aliases as T9 reference design now matches M75 (T9_noME change 40998) Clocks: Changed U2900 to SLG2AP101 as primary clock chip (T9_noME change 40975) Clock Termination: Added R3051 for Silego 537/101 compatibility BOM: Added BOMOPTIONs for SLG2AP101 (primary) and SLG8LP537 (backup) BOM: Selected P1V8S3_1V825 BOMOPTION to lift voltage at FB memories BOM: Changed C3860/61 to 22pF from 27 pF based on -R characterization (T9_noME change 41248) BOM: Changed FB memories to new Samsung and Hynix APNs (also added new BOMOPTIONs to GPU straps) Released for EVT (Schem Rev 10, PCB Rev 02) EVT_SE B 10.1.0: 01/24/07 01/24/07 01/24/07 10.2.0: 01/25/07 01/25/07 11.0.0: 01/25/07 01/25/07 01/25/07 12.0.0: 02/19/07 02/19/07 02/19/07 02/19/07 02/19/07 PATA Conn: Added pass FET Q4430 to allow PCIREQ3 (ODD reset GPIO) to pullup to S0 PATA Conn: Changed =PP5V_S0_ODDPWREN to =PP3V3_S0_ODDPWREN for minor power savings Power Aliases: Updated PP3V3_S0 aliases to support above changes PATA Conn: Replaced PCIREQ pass FET with OD buffer to correct a corner case during PLTRST Power Aliases: Updated PP5V_S0 aliases to support above changes BOM: Updated gain of PP1V25_ENET current sense amplifier to 165 (R5432 to 165K) BOM: Updated all Intel APNs to use QS parts Released for EVT (Schem Rev 11, PCB Rev 03) B GPU Reset: Changed C2885 to 0.047uF to reduce reset delay on powerup GPU PGOOD: Changed C9595 to 330pF to reduce PGOOD delay on powerup Power Sequencing: NO STUFFed U7885 to remove GPU PGOOD from PWROK chain Power Sequencing Rework: Short pins and of U7885 to complete PWROK chain Released post-EVT to document what was built (Schem Rev 12) - GPU FB: Changed cal resistors per Nvidia PUN (R8290 to 45.3 ohm and R8291 to 24.9 ohm) GPU FB: Changed unterminated-mode reference voltage to 40% (R8297 -> 1.02K, R8432/82, R8532/82 -> 2.21K) FireWire: Changed to Rev C of TI FireWire MCM (APN: 338S0435) Power Sequencing: Removed U7885/C7885 to take GFX_PGOOD out of PWR_OK chain (rdar://4974927) GPU Vcore: NO STUFFed all PWRCTL related components (feature not to be supported) GPU Vcore: Updated voltage setpoints to 1.000/1.070/1.125V (rdar://5021453) SB GPIOs: Sync’d page25.csa to T9_MLB to get pullup updates Thermal Sensors: Updated topology of EMC1033 filter caps (added C5515 next to IC, moved other caps to connectors - rdar://5025773) DVT A 12.1.0: 02/20/07 02/20/07 02/21/07 02/21/07 02/26/07 02/26/07 02/26/07 02/26/07 12.2.0: 02/27/07 02/28/07 12.3.0: 02/28/07 02/28/07 02/28/07 03/01/07 03/01/07 12.4.0: 03/01/07 03/01/07 12.5.0: 03/02/07 12.6.0: 03/06/07 03/06/07 12.7.0: 03/06/07 03/06/07 03/06/07 03/06/07 ODD Conn: Changed ODD power FET to FDC606P (from FDC638P) for reduced Rds(on) (rdar://4993378) Power Aliases: Moving PP1V8_GPU FET source to PP1V8_S3 rather than PP1V8_S3_ISNS to improve power delivery to GPU (rdar://5021462) Left Clutch IC: Updated both I-PEX connectors to new APN (part update for shell plating) NB GFX Core: Changed Vcore controller to ISL6263B (part consolidation effort between Apple/Intersil - rdar://5009109) Power Supplies: Replaced APN 152S0511 with 152S0368 (duplicate APNs for same part - rdar://5009109) Thermal Sensors: Updated topology of EMC1033 sensors (removed shorts, changed connector caps to 18pF) NB GFX Decoupling/Power Aliases: Connected VCCD_CRT of NB to GND per CRT disable guidelines Revision History SYNC_MASTER=N/A LVDS Connector: Changed pin of connector from NC to PP3V3_SW_LCD (in case we add extra cable for power - rdar://5024882) NB GFX Decoupling: Added R2260 (0.3 ohm, 0603) to bring ESR of regulator output cap in spec (rdar://5000272) SYNC_DATE=N/A NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING Power/Signal Aliases: Added XW0900 to PP5V_S5 to enable layout improvements I TO MAINTAIN THE DOCUMENT IN CONFIDENCE Power FETs: Changed Q7080 to RJK0301 which provides much lower Rds(on) FireWire Ports: Changed D4260 to PDS340 for lower height II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART - FireWire Ports: Changed D4260 to PDS540 for higher current capacity Ethernet Connector: Removed RX shorts on Ethernet MDI lines per EMC request SB GPIOs: Changed R2514 from pulldown to pullup to correct auto power-on issue (Linda card detect GPIO) DDR2 Regulator: Changed FB resistors to 0.1% to raise guaranteed lowest output voltage SIZE APPLE COMPUTER INC DRAWING NUMBER D SCALE SHT NONE REV 051-7225 14.0.0 OF 88 A Functional Test Points Fan Connectors TRUE TRUE TRUE D TRUE TRUE TRUE TRUE TRUE TRUE 27 42 47 52 57 58 59 65 76 78 FAN_LT_PWM FAN_LT_TACH 52 52 FAN_RT_PWM FAN_RT_TACH SMC_BS_ALRT_L SMBUS_SMC_BSA_SCL SMBUS_SMC_BSA_SDA GND_BATT TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE 45 46 56 45 48 56 84 45 48 56 84 56 52 52 LPC+ Debug Connector Left I/O Power Connector FUNC_TEST C CPU FSB NO_TESTs FUNC_TEST TRUE TRUE PP3V42_G3H PP5V_S0 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE LPC_AD LPC_AD LPC_FRAME_L PM_CLKRUN_L PCI_FW_GNT_L SMC_TMS DEBUG_RESET_L SMC_TRST_L SMC_TDO SMC_MD1 SMC_TX_L FWH_INIT_L PCI_CLK33M_LPCPLUS LPC_AD LPC_AD INT_SERIRQ PM_SUS_STAT_L SMC_TDI SMC_TCK SMC_RESET_L SMC_NMI SMC_RX_L LINDACARD_GPIO TRUE TRUE 28 34 43 45 46 47 48 65 78 27 42 47 52 57 58 59 65 76 78 PPBUS_G3H GND 40 49 56 57 58 59 60 61 62 63 74 23 45 47 23 45 47 23 45 47 25 45 47 NB NO_TESTs NO_TEST FUNC_TEST PP5V_S0 ICT Test Points Battery Digital Connector FUNC_TEST NO_TEST FSB_A_L FSB_ADS_L FSB_ADSTB_L FSB_BNR_L FSB_BREQ0_L FSB_D_L FSB_DBSY_L FSB_DINV_L FSB_DRDY_L FSB_DSTB_L_N FSB_DSTB_L_P FSB_HIT_L FSB_HITM_L FSB_LOCK_L FSB_REQ_L 10 14 79 TRUE NC_NB_NC TP_NB_NC 16 10 14 79 10 14 79 10 14 79 D 10 14 79 10 14 79 10 14 79 10 14 79 10 14 79 10 14 79 10 14 79 10 14 79 10 14 79 10 14 79 10 14 79 Request for at least 10 GND test points GPU NO_TESTs NOTE: 10 additional GND test points are called out separately in these notes NO_TEST 24 38 47 83 RTC Battery Connector 45 46 47 I550 28 47 FUNC_TEST I551 45 47 TRUE TRUE 45 46 47 45 47 PPVBATT_G3_RTC GND I552 TRUE TRUE TRUE LVDS_L_DATA_N LVDS_L_DATA_N LVDS_L_DATA_P 73 77 86 73 77 86 73 77 86 28 43 45 46 47 47 Current Sense Calibration 30 47 84 FUNC_TEST 23 45 47 23 45 47 TRUE TRUE TRUE TRUE TRUE 25 45 47 25 45 46 47 45 46 47 45 46 47 ISENSE_CAL_EN PP5V_S3 PPVCORE_S0_NB_GFX PPVCORE_S0_CPU PPVCORE_GPU 45 49 44 46 49 53 57 78 18 22 59 11 12 49 58 49 67 74 C TPs per 45 46 47 GND TRUE TPs, with each of above TP pairs 45 47 43 45 46 47 25 47 Left Clutch Barrel Connector Left ALS Connector FUNC_TEST FUNC_TEST TRUE TRUE TRUE TRUE PP3V3_S3 ALS_GAIN LTALS_OUT GND 36 38 48 50 51 53 54 57 78 45 53 78 53 78 Thermal Diode Connectors TRUE TRUE TRUE TRUE I554 B PP5V_S3 USB_CAMERA_N USB_CAMERA_P PP5V_S3 USB_WWAN_N USB_WWAN_P 44 46 49 53 57 78 24 44 82 24 44 82 44 46 49 53 57 78 24 44 82 24 44 82 Other Func Test Points FUNC_TEST I553 TRUE TRUE TRUE TRUE TRUE TRUE FUNC_TEST HSTHMSNS_D_P HSTHMSNS_D_N RSFSTHMSNS_D_P RSFSTHMSNS_D_N CPUTHMSNS_D2_P CPUTHMSNS_D2_N 51 87 51 TRUE TRUE PM_SYSRST_L SMC_ONOFF_L 25 28 45 45 46 78 51 87 51 51 87 51 CPUTHMSNS can not be supported due to layout constraints B System Validation TPs FUNC_TEST TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE FUNC_TEST CPU_PWRGD CPU_DPSLP_L PM_DPRSLPVR CPU_DPSLP_L PM_LAN_ENABLE PCI_RST_L PM_RSMRST_L PM_SB_PWROK SB_RTC_RST_L PM_STPCPU_L PM_STPPCI_L VR_PWRGD_CLKEN VR_PWRGOOD_DELAY FSB_CPURST_L FSB_CPUSLP_L FSB_DPWR_L NB_SB_SYNC_L 10 13 23 79 10 23 79 16 25 58 79 10 23 79 25 45 24 28 25 45 25 28 23 28 25 29 30 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE IMVP_VR_ON IMVP_DPRSLPVR PM_SLP_S3_L PM_S4_STATE_L PM_SLP_S5_L PM_ENET_EN P1V5P1V05S0_PGOOD CPU_DPRSTP_L IMVP6_VID TRUE TRUE TRUE PLT_RST_L NB_RESET_L GPU_RESET_L SMC_LRESET_L TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE CPU_STPCLK_L FSB_CLK_NB_P FSB_CLK_NB_N NB_CLKREQ_L NB_CLK100M_PCIE_P NB_CLK100M_PCIE_N NB_CLK96M_DOT_P NB_CLK96M_DOT_N NB_CLK100M_DPLLSS_P NB_CLK100M_DPLLSS_N CPU_THERMTRIP_R 25 29 30 25 28 16 28 58 45 58 58 79 25 35 36 40 45 49 57 62 65 25 34 43 45 57 65 25 45 46 36 61 65 61 63 65 10 16 23 58 79 12 58 79 24 28 77 16 28 28 66 28 45 10 13 14 79 10 14 79 10 14 79 16 25 A 10 23 79 14 29 30 84 14 29 30 84 16 29 16 29 30 84 Functional / ICT Test 16 29 30 84 84 SYNC_MASTER=(MASTER) 84 16 22 29 30 84 SYNC_DATE=(MASTER) NOTICE OF PROPRIETARY PROPERTY 16 22 29 30 84 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING 23 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE APPLE COMPUTER INC DRAWING NUMBER D SCALE SHT NONE REV 051-7225 14.0.0 OF 88 A 74 60 59 58 40 57 56 49 63 62 61 "G3Hot" (Always-Present) Rails PPBUS_G3H PPBUS_G3H D PPDCIN_G3H 40 49 56 57 58 59 60 61 62 63 74 40 49 56 57 58 59 60 61 62 63 74 40 49 56 57 58 59 60 61 62 63 74 40 49 56 57 58 59 60 61 62 63 74 40 49 56 57 58 59 60 61 62 63 74 40 49 56 57 58 59 60 61 62 63 74 40 49 56 57 58 59 60 61 62 63 74 40 49 56 57 58 59 60 61 62 63 74 40 49 56 57 58 59 60 61 62 63 74 40 49 56 57 58 59 60 61 62 63 74 40 49 56 57 58 59 60 61 62 63 74 40 49 56 57 58 59 60 61 62 63 74 PPDCIN_G3H MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=18.5V MAKE_BASE=TRUE PP3V42_G3H 34 65 57 54 53 51 50 48 38 36 78 34 65 PP3V42_G3H PP3V3_S3 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 28 34 43 45 46 47 48 65 78 PP1V8_S3_ISNS 28 34 43 45 46 47 48 65 78 28 34 43 45 46 47 48 65 78 28 34 43 45 46 47 48 65 78 28 34 43 45 46 47 48 65 78 28 34 43 45 46 47 48 65 78 28 34 43 45 46 47 48 65 78 28 34 43 45 46 47 48 65 78 28 34 43 45 46 47 48 65 78 28 34 43 45 46 47 48 65 78 PP1V8_S0 MAX I = 0.36A MAX I = ?.??A 36 38 48 50 51 53 54 57 78 PP5V_S5 PP5V_S5 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5V MAKE_BASE=TRUE PP5V_S5 PP5V_S5 PP5V_S5 PP5V_S5 PP5V_S5 PP5V_S5 PP5V_S5 PP5V_S5 PP5V_S5 PP5V_S5 PP5V_S5 PP5V_S5 PP5V_S5 PP5V_S5 78 57 44 53 49 46 PP5V_S3 27 43 57 60 61 62 63 65 74 27 43 57 60 61 62 63 65 74 27 43 57 60 61 62 63 65 74 27 43 57 60 61 62 63 65 74 27 43 57 60 61 62 63 65 74 27 43 57 60 61 62 63 65 74 27 43 57 60 61 62 63 65 74 27 43 57 60 61 62 63 65 74 27 43 57 60 61 62 63 65 74 27 43 57 60 61 62 63 65 74 27 43 57 60 61 62 63 65 74 27 43 57 60 61 62 63 65 74 27 43 57 60 61 62 63 65 74 27 43 57 60 61 62 63 65 74 PP5V_S3 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5V MAKE_BASE=TRUE PP5V_S3 PP5V_S3 PP5V_S3 PP5V_S3 PP5V_S3 PP5V_S3 PP5V_S3 B 59 58 57 27 52 47 42 78 76 65 PP5V_S0 27 43 57 60 61 62 63 65 74 44 46 49 53 57 78 44 46 49 53 57 78 44 46 49 53 57 78 44 46 49 53 57 78 44 46 49 53 57 78 44 46 49 53 57 78 44 46 49 53 57 78 44 46 49 53 57 78 PP5V_S0 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5V MAKE_BASE=TRUE PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 27 42 47 52 57 58 59 65 76 78 27 42 47 52 57 58 59 65 76 78 27 42 47 52 57 58 59 65 76 78 27 42 47 52 57 58 59 65 76 78 27 42 47 52 57 58 59 65 76 78 27 42 47 52 57 58 59 65 76 78 27 42 47 52 57 58 59 65 76 78 27 42 47 52 57 58 59 65 76 78 27 42 47 52 57 58 59 65 76 78 27 42 47 52 57 58 59 65 76 78 27 42 47 52 57 58 59 65 76 78 27 42 47 52 57 58 59 65 76 78 27 42 47 52 57 58 59 65 76 78 36 38 48 50 51 53 54 57 78 36 38 48 50 51 53 54 57 78 36 38 48 50 51 53 54 57 78 36 38 48 50 51 53 54 57 78 36 38 48 50 51 53 54 57 78 36 38 48 50 51 53 54 57 78 36 38 48 50 51 53 54 57 78 A PPVCORE_S0_CPU 18 59 22 PPVCORE_S0_NB_GFX PPVCORE_S0_NB_GFX PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=1.25V MAKE_BASE=TRUE PPVCORE_S0_NB_GFX PPVCORE_S0_NB_GFX 13 16 19 21 23 24 25 26 27 28 29 30 31 32 42 46 47 48 50 51 65 74 75 77 87 51 52 57 58 59 32 42 46 47 48 13 16 19 21 31 87 23 24 25 26 27 28 29 30 50 51 52 57 58 59 65 74 75 77 21 23 24 25 26 27 28 29 30 31 32 42 46 47 48 50 16 75 77 87 13 28 29 30 31 32 42 46 47 48 19 13 16 19 21 23 24 25 26 27 50 51 52 57 58 59 65 74 75 77 87 46 47 48 50 51 52 57 58 59 65 13 16 19 21 23 24 25 26 27 28 65 74 75 77 8729 30 31 32 42 74 46 47 48 50 51 52 57 58 59 21 23 24 25 26 27 28 29 30 31 32 42 16 58 59 65 74 75 77 87 13 28 29 30 31 32 42 46 47 48 19 13 16 19 21 23 24 25 26 27 50 51 52 57 58 59 65 74 75 77 87 30 31 32 42 46 47 48 50 51 52 13 16 19 21 23 24 25 26 27 28 29 57 52 57 58 59 65 74 75 77 87 PP1V05_S0 19 22 57 65 11 12 22 26 27 34 63 87 PP3V3_GPU PP1V25_ENET_ISNS PP1V25_ENET_ISNS PP1V25_ENET_ISNS 61 50 35 50 57 11 12 22 26 27 34 63 87 19 21 26 27 57 65 19 21 26 27 57 65 19 21 26 27 57 65 19 21 26 27 57 65 76 73 72 PP3V3_GPU_TMDS C 71 72 73 71 72 73 72 73 76 PP3V3_GPU_TMDS PP3V3_GPU_TMDS 10 11 12 13 14 18 19 21 23 26 27 30 46 50 61 10 11 12 13 14 18 19 21 23 26 27 30 46 50 61 70 69 68 67 57 77 73 PP1V8_GPU 10 11 12 13 14 27 30 46 50 61 10 11 12 13 14 27 30 46 50 61 10 11 12 13 14 27 30 46 50 61 10 11 12 13 14 27 30 46 50 61 10 11 12 13 14 27 30 46 50 61 72 73 76 72 73 76 PP1V8_GPU 57 67 68 69 70 73 77 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.8V MAKE_BASE=TRUE 10 11 12 13 14 18 19 21 23 26 27 30 46 50 61 10 11 12 13 14 18 19 21 23 26 27 30 46 50 61 10 11 12 13 14 18 19 21 23 26 27 30 46 50 61 PP1V8_GPU PP1V8_GPU PP1V8_GPU PP1V8_GPU PP1V8_GPU 18 19 21 23 26 18 19 21 23 26 18 19 21 23 26 18 19 21 23 26 57 67 68 69 70 73 77 57 77 57 77 57 77 57 77 67 68 69 70 73 67 68 69 70 73 67 68 69 70 73 67 68 69 70 73 18 19 21 23 26 B 16 18 21 22 50 77 74 71 68 66 57 PPVCORE_S0_NB_R 16 18 21 22 50 PP0V9_S3_MEM_VREF 16 31 32 62 PP1V25_GPU PP1V25_GPU 57 66 68 71 74 77 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.25V MAKE_BASE=TRUE PP1V25_GPU PP1V25_GPU PP1V25_GPU PP1V25_GPU PP1V25_GPU PP1V25_GPU PP1V25_GPU PP1V25_GPU 16 31 32 62 16 31 32 62 16 31 32 62 16 31 32 62 57 66 68 71 74 77 57 66 68 71 74 77 57 66 68 71 74 77 57 66 68 71 74 77 57 66 68 71 74 77 57 66 68 71 74 77 57 66 68 71 74 77 57 66 68 71 74 77 33 62 74 67 49 PPVCORE_GPU PPVCORE_GPU 49 67 74 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.2V MAKE_BASE=TRUE 33 62 PPVCORE_GPU PP3V3_ENET 49 67 74 35 36 MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V MAKE_BASE=TRUE Power Aliases 35 36 35 36 SYNC_MASTER=(MASTER) PP1V9_ENET SYNC_DATE=(MASTER) 35 36 MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.9V MAKE_BASE=TRUE NOTICE OF PROPRIETARY PROPERTY PP1V9_ENET 35 36 PP1V25_ENET 35 50 61 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.25V MAKE_BASE=TRUE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART PP1V25_ENET PP1V25_ENET 71 72 73 48 57 65 71 72 73 74 76 77 PP3V3_GPU_TMDS 35 50 61 SIZE 35 50 61 APPLE COMPUTER INC DRAWING NUMBER D REV 051-7225 SHT NONE 71 72 73 48 57 65 71 72 73 74 76 77 48 57 65 71 72 73 74 76 77 48 57 65 71 72 73 74 76 77 MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V MAKE_BASE=TRUE 10 11 12 13 14 18 19 21 23 26 27 30 46 50 61 Yukon EC will not be supported 71 72 73 19 21 26 27 57 65 SCALE 48 57 65 74 76 77 48 57 65 74 76 77 48 57 65 74 76 77 48 57 65 74 76 77 48 57 65 74 76 77 19 21 26 27 57 65 GND 8 48 57 65 71 72 73 74 76 77 48 57 65 71 72 73 74 76 77 48 57 65 71 72 73 74 76 77 PP3V3_GPU PP3V3_GPU PP3V3_GPU "ENET" Rails 50 57 48 57 65 71 72 73 74 76 77 PP3V3_GPU 19 21 26 27 57 65 19 21 26 27 57 65 PP0V9_S0 50 57 48 57 65 71 72 73 74 76 77 PP3V3_GPU PP3V3_GPU PP3V3_GPU PP3V3_GPU PP3V3_GPU PP3V3_GPU PP3V3_GPU PP3V3_GPU PP3V3_GPU 11 12 22 26 27 34 63 87 PP0V9_S0 PP1V25_ENET 39 64 PP3V3_GPU 11 12 22 26 27 34 63 87 MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0.9V MAKE_BASE=TRUE PP1V9_ENET 39 64 MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V MAKE_BASE=TRUE 11 12 22 26 27 34 63 87 PP0V9_S3_MEM_VREF PP0V9_S3_MEM_VREF PP0V9_S3_MEM_VREF PP0V9_S3_MEM_VREF PP3V3_ENET 39 64 "GPU" Rails 11 12 22 26 27 34 63 87 MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0.9V MAKE_BASE=TRUE 42 46 47 48 50 13 16 19 21 23 24 25 26 27 28 29 30 31 32 51 52 57 58 59 65 74 75 77 87 39 40 41 64 PP1V95_FW PP1V95_FW 11 12 22 26 27 34 63 87 PPVCORE_S0_NB_R PP0V9_S0 39 40 41 64 11 12 22 26 27 34 63 87 MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0.9V MAKE_BASE=TRUE PP0V9_S3_MEM_VREF 39 40 41 64 MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.95V MAKE_BASE=TRUE 11 12 22 26 27 34 63 87 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PPVCORE_S0_NB_R 39 40 41 64 PP1V95_FW PP1V95_FW 11 12 22 26 27 34 63 87 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.5V MAKE_BASE=TRUE MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V MAKE_BASE=TRUE 58 59 65 74 75 77 87 30 31 32 42 46 47 48 50 51 52 13 16 19 21 23 24 25 26 27 28 29 57 52 57 58 59 65 74 75 77 87 13 16 19 21 23 24 25 26 27 28 29 30 31 32 42 46 47 48 50 51 77 87 51 52 57 58 59 65 74 75 24 25 26 27 28 29 30 31 32 42 46 47 48 50 23 21 75 77 87 16 58 59 65 74 48 50 51 52 13 28 29 30 31 19 13 16 19 21 23 24 25 26 27 32 42 46 47 58 59 65 74 75 77 87 57 30 31 32 42 46 47 48 50 51 52 13 16 19 21 23 24 25 26 27 28 29 57 52 57 58 59 65 74 75 77 87 13 16 19 21 23 24 25 26 27 28 29 30 31 32 42 46 47 48 50 51 65 74 75 77 87 47 48 50 51 52 57 58 59 30 31 32 42 46 26 27 28 29 21 23 24 25 16 74 75 77 87 13 28 29 30 31 32 42 46 47 48 19 13 16 19 21 23 24 25 26 27 50 51 52 57 58 59 65 74 75 77 87 42 46 47 48 50 51 52 57 58 59 13 16 19 21 23 24 25 26 27 28 32 59 65 74 75 77 8729 30 31 65 42 46 47 48 50 51 52 57 58 21 23 24 25 26 27 28 29 30 31 32 16 57 58 59 65 74 75 77 87 13 28 29 30 31 32 42 46 47 48 19 13 16 19 21 23 24 25 26 27 50 51 52 57 58 59 65 74 75 77 87 24 25 26 27 28 29 30 31 32 42 46 47 48 50 51 52 23 21 87 16 65 74 75 77 51 52 57 58 13 28 29 30 31 19 13 16 19 21 23 24 25 26 27 32 42 46 47 48 50 65 74 75 77 87 59 32 42 46 47 48 50 51 52 57 58 13 16 19 21 23 24 25 26 27 28 31 58 59 65 74 75 77 8729 30 32 42 46 47 48 50 51 52 5759 21 23 24 25 26 27 28 29 30 31 16 52 57 58 59 65 74 75 77 87 13 28 29 30 31 32 42 46 47 48 19 13 16 19 21 23 24 25 26 27 50 51 52 57 58 59 65 74 75 77 87 29 30 31 32 42 46 47 48 50 51 13 16 19 21 23 24 25 26 27 28 D 19 22 57 65 PP1V05_S0 13 16 19 21 23 24 25 26 27 28 29 30 31 32 42 46 47 48 50 51 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.25V MAKE_BASE=TRUE 18 22 59 PP3V3_FW PP3V3_FW PP3V3_FW PP3V3_FW 19 22 57 65 PP1V25_S0 PP1V25_S0 PP1V25_S0 PP1V25_S0 PP1V25_S0 PP1V25_S0 PP1V25_S0 11 12 49 58 18 22 59 MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V MAKE_BASE=TRUE MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.8V MAKE_BASE=TRUE MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.25V MAKE_BASE=TRUE 58 59 65 74 75 77 87 30 31 32 42 46 47 48 50 51 52 13 16 19 21 23 24 25 26 27 28 29 57 52 57 58 59 65 74 75 77 87 13 16 19 21 23 24 25 26 27 28 29 30 31 32 42 46 47 48 50 51 58 59 65 74 75 77 87 28 29 30 31 32 42 46 47 48 13 16 19 21 23 24 25 26 27 50 51 52 57 58 59 65 74 75 77 87 30 31 32 42 46 47 48 50 51 52 13 16 19 21 23 24 25 26 27 28 29 57 52 57 58 59 65 74 75 77 87 36 35 PP1V25_ENET_ISNS PP3V3_FW 16 18 21 50 57 PP1V25_S0 65 57 27 26 21 19 52 57 58 59 65 74 75 77 87 13 16 19 21 23 24 25 26 27 28 29 30 31 32 42 46 47 48 50 51 11 12 49 58 18 22 59 39 40 41 64 16 18 21 50 57 36 38 48 50 51 53 54 57 78 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.3 mm VOLTAGE=1.25V MAKE_BASE=TRUE PPVCORE_S0_CPU PP3V3_FW 39 40 64 MAKE_BASE=TRUE PP3V3_ENET PP3V3_ENET PPVCORE_S0_CPU 40 41 PPVP_FW_PORTB_UF 36 38 48 50 51 53 54 57 78 Chipset "VCore" Rails 11 58 49 12 40 41 PPVP_FW_PORTB_UF PPVP_FW_PORTA_UF 39 40 64 16 18 21 50 57 PP1V5_S0 PP1V5_S0 PP1V5_S0 PP1V5_S0 PP1V5_S0 PP1V5_S0 PP1V5_S0 PP1V5_S0 PP1V5_S0 36 38 48 50 51 53 54 57 78 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V MAKE_BASE=TRUE 5V Rails 63 62 61 27 60 57 43 74 65 PPVP_FW_PORTA_UF 64 39 PP1V25_S0 PP3V3_S0 16 18 21 50 57 41 40 8 39 40 64 MAKE_BASE=TRUE PP1V5_S0 36 38 48 50 51 53 54 57 78 39 40 64 PPVP_FW PPVP_FW PPVP_FW 41 40 PP1V8_S0 PP1V8_S0 PP1V5_S0 40 64 31 32 38 50 57 62 87 36 38 48 50 51 53 54 57 78 87 63 34 27 26 22 12 11 PPBUS_FW_FWPWRSW_F PPVP_FW MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.3 mm VOLTAGE=33V MAKE_BASE=TRUE 31 32 38 50 57 62 87 PP1V8_S0 24 25 26 27 28 46 48 55 57 60 65 75 87 24 25 26 27 28 46 48 55 57 60 65 75 87 24 25 26 27 28 46 48 55 57 60 65 75 87 PPVP_FW 31 32 38 50 57 62 87 PP1V8_S3_ISNS PP1V8_S3_ISNS PP1V8_S3_ISNS 24 25 26 27 28 46 48 55 57 60 65 75 87 60 65 75 87 24 25 26 27 28 46 48 55 57 PPBUS_FW_FWPWRSW_F MAKE_BASE=TRUE 31 32 38 50 57 62 87 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.8V MAKE_BASE=TRUE 24 25 26 27 28 46 48 55 57 60 65 75 87 24 25 26 27 28 46 48 55 57 60 65 75 87 24 25 26 27 28 46 48 55 57 60 65 75 87 C 87 77 75 74 65 59 58 57 52 51 27 26 25 24 23 21 19 16 13 50 48 47 46 42 32 31 30 29 28 31 32 38 50 57 62 87 PP1V8_S3_ISNS 57 50 21 18 16 8 24 25 26 27 28 46 48 55 57 60 65 75 87 24 25 26 27 28 46 48 55 57 60 65 75 87 PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3 64 40 PP1V8_S3 PP1V8_S3 PP1V8_S3 PP1V8_S3 PP1V8_S3 24 25 26 27 28 46 48 55 57 60 65 75 87 24 25 26 27 28 46 48 55 57 60 65 75 87 24 25 26 27 28 46 48 55 57 60 65 75 87 PP3V3_S3 31 32 38 50 57 62 87 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.8V MAKE_BASE=TRUE 24 25 26 27 28 46 48 55 57 60 65 75 87 24 25 26 27 28 46 48 55 57 60 65 75 87 "FW" (FireWire) Rails PP1V8_S3 24 25 26 27 28 46 48 55 57 60 65 75 87 24 25 26 27 28 46 48 55 57 60 65 75 87 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V MAKE_BASE=TRUE MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.42V MAKE_BASE=TRUE PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H 1.8V-0.9V Rails PP1V8_S3 PP3V3_S5 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V MAKE_BASE=TRUE 40 49 56 57 58 59 60 61 62 63 74 PPDCIN_G3H 48 47 46 28 45 43 34 78 65 3.3V-2.5V Rails 40 49 56 57 58 59 60 61 62 63 74 PP3V3_S5 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=12.6V MAKE_BASE=TRUE PPBUS_G3H PPBUS_G3H PPBUS_G3H PPBUS_G3H PPBUS_G3H PPBUS_G3H PPBUS_G3H PPBUS_G3H PPBUS_G3H PPBUS_G3H PPBUS_G3H PPBUS_G3H PPBUS_G3H 65 34 14.0.0 OF 88 A Thermal Module Holes Top CPU TM Notch ZT0985 5P75R2P7 Add buried vias to GND 28 25 Top GPU Right TM Hole ZT0970 ZT0975 ZT0980 5P75R2P7 5P75R2P7 D PM_SB_PWROK PM_SB_PWROK 25 28 VR_PWRGOOD_DELAY 16 28 58 SMC_SMS_INT 45 54 PEG_CLK100M_GPU_P 29 30 66 84 PEG_CLK100M_GPU_N 29 30 66 84 PM_ALL_NBGFX_PGOOD 59 77 GFX_VR_EN 16 59 GFX_VID 16 TP_MEM_A_A 31 TP_MEM_B_A 32 TP_USB_EXTCP 24 82 TP_USB_EXTCN 24 82 PP5V_S5_P1V25S0FET 57 MAKE_BASE=TRUE VR_PWRGOOD_DELAY MAKE_BASE=TRUE 5P75R2P7 Left CPU TM Hole 58 28 16 Right CPU TM Hole 54 45 Bottom Left GPU TM Hole SMC_SMS_INT MAKE_BASE=TRUE PEG_CLK100M_GPU_P 84 66 30 29 D MAKE_BASE=TRUE PEG_CLK100M_GPU_N 84 66 30 29 MAKE_BASE=TRUE RAM Door (Torx) Holes 77 59 ZT0930 59 16 3P7R3P2 59 GND 31 ZT0935 32 3P7R3P2 PM_ALL_NBGFX_PGOOD MAKE_BASE=TRUE GFX_VR_EN MAKE_BASE=TRUE GFXIMVP6_VID MAKE_BASE=TRUE TP_MEM_A_A MAKE_BASE=TRUE TP_MEM_B_A MAKE_BASE=TRUE GND TP_USB_EXTCP 82 24 MAKE_BASE=TRUE 82 24 Frame Holes XW0900 SM ZT0920 74 65 63 62 61 60 57 43 27 3P2R2P7 PP5V_S5 257 PP5V_S5_P1V25S0FET MIN_LINE_WIDTH=0.1 mm MIN_NECK_WIDTH=0.1 mm VOLTAGE=5V MAKE_BASE=TRUE GND TP_USB_EXTCN MAKE_BASE=TRUE NO_TEST=TRUE ZT0940 3P7R3P2 GND C C ZT0945 Board Edge Notches HOLE-VIA-P5RP25 GND (Can’t be PTH) HOLE-VIA-P5RP25 GND ZT0950 ZT0955 3P2R2P7 GND ZT0965 3P2R2P7 GND ZT0960 HOLE-VIA-P5RP25 GND Tooling Holes ZT0990 (Can’t be PTH) HOLE-VIA-P5RP25 176 GND_CHASSIS_DVI_TOP B B Chassis GNDs GND_CHASSIS_DVI_TOP 76 GND_CHASSIS_DVI_TOP 76 GND_CHASSIS_DVI_BOT 76 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=0V MAKE_BASE=TRUE 76 GND_CHASSIS_DVI_BOT MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=0V MAKE_BASE=TRUE OMIT R09101 SHORT NONE NONE NONE 4022 Digital Ground GND_CHASSIS_ENET MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=0V MAKE_BASE=TRUE GND_CHASSIS_ENET GND_CHASSIS_ENET GND_CHASSIS_ENET GND MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM VOLTAGE=0V 37 41 37 41 37 41 GND_CHASSIS_RTUSB 43 41 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=0V MAKE_BASE=TRUE GND_CHASSIS_RTUSB GND_CHASSIS_RTUSB 41 43 41 43 Signal Aliases SYNC_MASTER=(T9_MLB) A SYNC_DATE=08/23/2006 NOTICE OF PROPRIETARY PROPERTY SH0925 OG-503040 SHLD-SM-LF 51 44 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING GND_CHASSIS_LEFTCLUTCH MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=0V MAKE_BASE=TRUE GND_CHASSIS_LEFTCLUTCH 44 51 GND_CHASSIS_LEFTCLUTCH 44 51 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE APPLE COMPUTER INC DRAWING NUMBER D SCALE SHT NONE REV 051-7225 14.0.0 OF 88 A OMIT 79 14 BI 79 14 BI 79 14 BI 79 14 BI 79 14 BI 79 14 BI 79 14 BI 79 14 BI 79 14 BI 79 14 BI 79 14 BI 79 14 BI 79 14 BI 79 14 BI 79 14 BI 79 14 BI 79 14 BI 79 14 BI 79 14 BI 79 14 BI 79 14 BI 79 14 BI 79 14 BI 79 14 BI 79 14 BI 79 14 BI 79 14 BI 79 14 BI 79 14 BI 79 14 BI 79 14 BI 79 14 BI 79 14 BI 79 14 BI 79 23 IN 79 23 OUT 79 23 IN 79 23 IN 79 23 IN 79 23 79 23 IN IN FSB_REQ_L FSB_REQ_L FSB_REQ_L FSB_REQ_L FSB_REQ_L K3 H2 K2 J3 L1 REQ0* REQ1* REQ2* REQ3* REQ4* FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_ADSTB_L A17* A18* A19* A20* A21* A22* A23* A24* A25* A26* A27* A28* A29* A30* A31* A32* A33* A34* A35* ADSTB1* CPU_A20M_L CPU_FERR_L CPU_IGNNE_L A6 A5 C4 A20M* FERR* IGNNE* CPU_STPCLK_L CPU_INTR CPU_NMI CPU_SMI_L D5 C6 B4 A3 STPCLK* LINT0 LINT1 SMI* TP_CPU_RSVD0 TP_CPU_RSVD1 TP_CPU_RSVD2 TP_CPU_RSVD3 TP_CPU_RSVD4 TP_CPU_RSVD5 TP_CPU_RSVD6 TP_CPU_RSVD7 TP_CPU_RSVD8 TP_CPU_RSVD9 B Y2 U5 R3 W6 U4 Y5 U1 R4 T5 T3 W2 W5 Y4 U2 V4 W3 AA4 AB2 AA3 V1 M4 N5 T2 V3 B2 C3 D2 D22 D3 F6 DEFER* DRDY* DBSY* BR0* FSB_ADS_L FSB_BNR_L FSB_BPRI_L H5 F21 E1 FSB_DEFER_L FSB_DRDY_L FSB_DBSY_L F1 FSB_BREQ0_L CPU_IERR_L CPU_INIT_L IN BI D20 B3 LOCK* H4 FSB_LOCK_L RESET* RS0* RS1* RS2* TRDY* C1 F3 F4 G3 G2 FSB_CPURST_L FSB_RS_L FSB_RS_L FSB_RS_L FSB_TRDY_L HIT* HITM* G6 E4 FSB_HIT_L FSB_HITM_L BPM0* BPM1* BPM2* BPM3* PRDY* PREQ* TCK TDI TDO TMS TRST* DBR* AD4 AD3 AD1 AC4 AC2 AC1 AC5 AA6 AB3 AB5 AB6 C20 14 79 BI 14 79 BI 14 79 PP1V05_S0 IERR* INIT* 79 BI BI 14 79 BI 14 79 BI 14 79 BI 14 79 10 11 12 13 14 18 19 21 23 26 27 30 46 50 61 R1002 PLACE TESTPOINT ON FSB_IERR_L WITH A GND 0.1" AWAY 54.9 1% 1/16W MF-LF 402 D 23 47 79 14 79 IN 13 14 79 IN 14 79 IN 14 79 IN 14 79 IN 14 79 OMIT XDP_BPM_L XDP_BPM_L XDP_BPM_L XDP_BPM_L XDP_BPM_L XDP_BPM_L XDP_TCK XDP_TDI XDP_TDO XDP_TMS XDP_TRST_L XDP_DBRESET_L BI 14 79 BI 14 79 BI 13 79 BI 13 79 BI 13 79 BI 13 79 BI 13 79 PP1V05_S0 10 11 12 13 14 18 19 21 23 26 27 30 46 50 61 79 13 10 XDP_TDI FSB_D_L N22 FSB_D_L K25 FSB_D_L P26 79 14 BI FSB_D_L R23 79 14 BI FSB_D_L L23 79 14 BI FSB_D_L M24 79 14 BI FSB_D_L L22 79 14 BI FSB_D_L M23 79 14 BI FSB_D_L P25 79 14 BI FSB_D_L P23 79 14 BI FSB_D_L P22 79 14 BI FSB_D_L T24 79 14 BI FSB_D_L R24 79 14 BI FSB_D_L L25 79 14 BI FSB_D_L T25 79 14 BI FSB_D_L N25 79 14 BI FSB_DSTB_L_N L26 79 14 BI FSB_DSTB_L_P M26 79 14 BI FSB_DINV_L N24 79 14 BI 0.5" MAX LENGTH FOR CPU_GTLREF 79 CPU_GTLREF AD26 CPU_TEST1 C23 CPU_TEST2 D25 TP_CPU_TEST3 C24 CPU_TEST4 AF26 TP_CPU_TEST5 AF1 NOSTUFF TP_CPU_TEST6 A26 C1000 0.1uF 10% 16V CPU_BSEL B22 79 30 OUT X5R 402 CPU_BSEL B23 79 30 OUT CPU_BSEL C21 79 30 OUT D16* D17* D18* D19* D20* D21* D22* D23* D24* D25* D26* D27* D28* D29* D30* D31* DSTBN1* DATBP1* DINV1* 79 14 BI R10031 79 14 BI 79 14 BI 1% 1/16W MF-LF 402 79 14 BI 79 14 BI 79 14 BI 79 14 BI 54.9 BI 13 79 IN 10 13 79 79 14 BI IN 10 13 79 79 14 BI OUT 10 13 79 79 14 BI IN 10 13 79 79 14 BI IN 10 13 79 79 14 BI 79 14 BI 79 14 BI 79 14 BI 79 14 BI 79 14 BI 79 14 BI OUT 13 28 R1004 68 5% 1/16W MF-LF 402 THERMAL PROCHOT* THERMDA THERMDC THERMTRIP* RSVD0 RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 RSVD6 RSVD7 RSVD8 RSVD9 D21 A24 B25 CPU_PROCHOT_L CPU_THERMD_P CPU_THERMD_N C7 PM_THRMTRIP_L OUT OUT 51 87 OUT 51 OUT 16 23 46 79 H CLK BCLK0 BCLK1 A22 A21 FSB_CLK_CPU_P FSB_CLK_CPU_N IN 29 30 84 IN 29 30 84 23 21 19 18 14 13 12 11 10 61 50 46 30 27 26 46 58 79 PM_THRMTRIP# SHOULD CONNECT TO ICH AND GMCH WITHOUT T (NO STUB) PP1V05_S0 R1005 1K NC B1 R1020 XDP_TMS D0* D1* D2* D3* D4* D5* D6* D7* D8* D9* D10* D11* D12* D13* D14* D15* DSTBN0* DSTBP0* DINV0* BI 1% 1/16W MF-LF 402 NC R10061 79 13 10 FSB_D_L E22 FSB_D_L F24 FSB_D_L E26 FSB_D_L G22 FSB_D_L F23 FSB_D_L G25 FSB_D_L E25 FSB_D_L E23 FSB_D_L K24 FSB_D_L G24 FSB_D_L J24 FSB_D_L J23 FSB_D_L H22 FSB_D_L F26 FSB_D_L K22 FSB_D_L H23 FSB_DSTB_L_N J26 FSB_DSTB_L_P H26 FSB_DINV_L H25 79 14 54.9 R1021 54.9 2.0K PP1V05_S0 10 11 12 13 14 18 19 21 23 26 27 30 46 50 61 1% 1/16W MF-LF 402 1% 1/16W MF-LF 402 1% 1/16W MF-LF 402 PLACE C1000 CLOSE TO CPU_TEST4 PIN MAKE SURE CPU_TEST4 IS REFERENCED TO GND R1024 54.9 XDP_TDO 79 13 10 1% PLACEMENT_NOTE=Place R1024 near ITP connector (if present) 1/16W 79 14 BI 79 14 BI 79 13 10 XDP_TRST_L 649 OF MISC BSEL0 BSEL1 BSEL2 Y22 AB24 V24 V26 V23 T22 U25 U23 Y25 W22 Y23 W24 W25 AA23 AA24 AB25 Y26 AA26 U22 FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_DSTB_L_N FSB_DSTB_L_P FSB_DINV_L D48* D49* D50* D51* D52* D53* D54* D55* D56* D57* D58* D59* D60* D61* D62* D63* DSTBN3* DSTBP3* DINV3* AE24 AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21 AC22 AD23 AF22 AC23 AE25 AF24 AC20 FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_DSTB_L_N FSB_DSTB_L_P FSB_DINV_L COMP0 COMP1 COMP2 COMP3 R26 U26 AA1 Y1 DPRSTP* DPSLP* DPWR* PWRGOOD SLP* PSI* E5 B5 D24 D6 D7 AE6 79 79 79 79 BI 14 79 BI 14 79 BI 14 79 BI 14 79 BI 14 79 BI 14 79 BI 14 79 BI 14 79 BI 14 79 BI 14 79 BI 14 79 BI 14 79 BI 14 79 BI 14 79 BI 14 79 BI 14 79 BI 14 79 BI 14 79 BI 14 79 BI 14 79 BI 14 79 BI 14 79 BI 14 79 BI 14 79 BI 14 79 BI 14 79 BI 14 79 BI 14 79 BI 14 79 BI 14 79 BI 14 79 BI 14 79 BI 14 79 BI 14 79 BI 14 79 BI 14 79 BI 14 79 BI 14 79 C LAYOUT NOTE: COMP0,2 CONNECT WITH ZO=27.4OHM, MAKE TRACE LENGTH SHORTER THAN 0.5" COMP1,3 CONNECT WITH ZO=55OHM, MAKE TRACE LENGTH SHORTER THAN 0.5" R1016 27.4 1% 1/16W MF-LF 402 1% 1/16W MF-LF 402 R1018 R1019 1% 1/16W MF-LF 402 54.9 CPU_COMP CPU_COMP CPU_COMP CPU_COMP CPU_DPRSTP_L CPU_DPSLP_L FSB_DPWR_L CPU_PWRGD FSB_CPUSLP_L CPU_PSI_L R1017 54.9 IN 16 23 58 79 IN 23 79 IN 14 79 IN 13 23 79 IN 14 79 OUT B 27.4 1% 1/16W MF-LF 402 28 58 54.9 R1023 FCBGA D32* D33* D34* D35* D36* D37* D38* D39* D40* D41* D42* D43* D44* D45* D46* D47* DSTBN2* DSTBP2* DINV2* R1030 R1022 XDP_TCK MEROM NOSTUFF MF-LF 402 79 13 10 GTLREF TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 U1000 DATA GRP BI H1 E2 G5 DATA GRP BI 79 14 ADS* BNR* BPRI* DATA GRP 79 14 FCBGA OF DATA GRP BI MEROM CONTROL 79 14 U1000 XDP/ITP SIGNALS BI A3* A4* A5* A6* A7* A8* A9* A10* A11* A12* A13* A14* A15* A16* ADSTB0* ADDR GROUP0 BI 79 14 J4 L5 L4 K5 M3 N2 J1 N3 P5 P2 L2 P4 P1 R1 M1 ADDR GROUP1 79 14 FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_ADSTB_L ICH C BI RESERVED D 79 14 NOSTUFF R10121 1% 1/16W MF-LF 402 1K 5% 1/16W MF-LF 402 1% 1/16W MF-LF 402 5% 1/16W MF-LF 402 NOSTUFF R1007 1K 5% 1/16W MF-LF 402 CPU FSB SYNC_MASTER=T9_NOME A SYNC_DATE=03/16/2007 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE APPLE COMPUTER INC DRAWING NUMBER D SCALE SHT NONE REV 051-7225 14.0.0 OF 10 88 A GPU VCore Current Sense GPUISENS_NTC D 87 77 75 65 59 58 57 52 51 27 26 25 24 23 21 19 16 13 50 48 47 46 42 32 31 30 29 28 PP3V3_S0 65 63 62 61 60 57 43 27 1% 1/16W MF-LF 402 GPU VCore Regulator PP5V_S5 C8931 1% 1/16W MF-LF 402 C8930 2.2UF 10% 16V X5R 603 OUT 10% 16V X5R 603 U8900 TPS51117RGY_QFN14 SYM (2 OF 2) QFN EN_PSV PGOOD VBST 14 (=PPVCORE_GPU_REG) VOUT DRVH 13 GPUVCORE_VFB VFB LL 12 GPUVCORE_LL SWITCH_NODE=TRUE GATE_NODE=TRUE PGND 15 THRM_PAD GPUVCORE_DRVH GATE_NODE=TRUE C8991 0.22UF R8919 200K 1% 1/16W MF-LF 402 0.1UF Q8920 MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.2 mm MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm CRITICAL L8920 CRITICAL Q8922 close close close close close RJK0301DPB LFPAK RJK0301DPB MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.20 mm VOLTAGE=1.25V R89211 470pF L8920 L8920 L8920 L8920 L8920 10% 50V CERM 402 PPVCORE_GPU 330UF 10% 2.0V TANT D2T C8920 C CRITICAL C8940 10UF C8943 330UF 20% 6.3V X5R 603 5% 50V CERM 402 49 67 Vout = 1.25V - 0.96V 18A max output (L8920 limit) C8942 1 100PF 1% 1/16W MF-LF 402 2 C8992 CRITICAL NO STUFF 2.87K C8921 1 to to to to to PPVCORE_GPU_XW Q8921 NO STUFF 10% 2.0V TANT D2T 1000pF 10% 25V X7R 402 XW8900 SM (GPUVCORE_VFB) NO STUFF NO STUFF R89221 (GND) R8923 7.15K Vout = 0.75V * (1 + Ra / Req) Vout(min) = 0.75V * (1 + Ra / Rb) Req = Rb || Rc || Rd || Re 74 R8997 R8994 C8990 C8991 R8990 XW8920 SM LFPAK PLACEMENT_NOTE=Place PLACEMENT_NOTE=Place PLACEMENT_NOTE=Place PLACEMENT_NOTE=Place PLACEMENT_NOTE=Place Place near C8940 49 CRITICAL 10.5K OUT 1% 1/16W MF-LF 402 1% 1/16W MF-LF 402 XW8901 SM 1.0UH-20A 1M GPUISENS_POS R8905 GPUVCORE_IOUT V- CRITICAL - IHLP4040DZ11-SM SC70-5 R8992 20.0K2 1 1% 1/16W MF-LF 402 1uF HPA00141AIDCKR V+ PVCORE_GPU_NTC C8995 10% 6.3V CERM 402 U8995 + R8991 R8990 1 10% 6.3V CERM-X5R 402 RJK0305DPB LFPAK GPUISENS_NEG 1% 1/16W MF-LF 402 GPUISENS_RC 649 1% 1/16W MF-LF 402 10% 6.3V CERM-X5R 402 CRITICAL 20% 10V CERM 402 20.0K2 0.47UF 1% 1/16W MF-LF 402 R8993 C8990 10% 25V X5R 603 20% 25V POLY CASE-D2-LF GPUVCORE_VBST GPUVCORE_DRVL DRVL GND 5% 1/16W MF-LF 402 GPUVCORE_TON TON 11 TRIP R89151 C8915 1UF MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm C8900 1uF PM_GPUP1V8FET_EN GPUVCORE_TRIP C V5DRV CRITICAL PM_GPUVCORE_EN IN 65 57 V5FILT 72 65 10 C8901 GPUVCORE_BOOT_R C8932 22UF 20% 25V POLY CASE-D2-LF (GPUVCORE_TON) 1M 1 10% 50V CERM 402 R8998 2 1% 1/16W MF-LF 402 CRITICAL 22UF MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5V 1K CRITICAL 200 PP5V_S5_GPUVCORE_V5FILT 0603-LF PPBUS_G3H R89011 10KOHM-5% NO STUFF R8994 61 60 59 58 57 56 49 40 63 62 470pF R8997 1K D C8998 CRITICAL R89961 61.9K 1% 1/16W MF-LF 402 1% 1/16W MF-LF 402 GND_GPUVCORE_SGND MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=0V R8924 30.1K 1% 1/16W MF-LF 402 NO STUFF NO STUFF R8925 R8926 28K R8927 53.6K 1% 1/16W MF-LF 402 53.6K 1% 1/16W MF-LF 402 1% 1/16W MF-LF 402 GPUVCORE_VFB_PC1 GPUVCORE_VFB_PC0 74 74 (GPUVCORE_VFB) (=PPVCORE_GPU_REG) 77 71 68 66 57 PP1V25_GPU 77 76 73 72 71 65 57 48 PP3V3_GPU GPUVCORE_VFB_C NO STUFF B GPU VCore Setpoints R8962 NO STUFF NO STUFF IN GPU_VCORE_PWRCTL0 4.99K2 1% 1/16W MF-LF 402 5% 1/16W MF-LF 402 C8961 R8960 72 71 0.01UF PC0_DIV NO STUFF R89611 1K GPUVCORE_VFB_PC0 1K NO STUFF R8964 PC0_BIAS NO STUFF 10% 16V CERM 402 PC0_BIAS_B R8963 1.5K 100K 5% 1/16W MF-LF 402 NO STUFF Q8927 MMDT3904XF SOT-363-LF 5% 1/16W MF-LF 402 5% 1/16W MF-LF 402 10K R89701 R89711 R89721 74 72 71 IN 100K 5% 1/16W MF-LF 402 100K 7.5K GPU_VCORE_VID0 5% 1/16W MF-LF 402 GND_GPUVCORE_SGND 74 Q8923 D R8973 5% 1/16W MF-LF 402 VID2 VID1 VID0 5% 1/16W MF-LF 402 2N7002DW-X-F GPU_VCORE_VID0_RC G SOT-363 S C8973 0.1UF 20% 10V CERM 402 74 0 0 1 1 C D E State Y Y Y 1.050V 1.050V 1.050V 1.125V Y Y Y B (rsvd state) (max batt) (balanced) (max perf) All other states not defined GND_GPUVCORE_SGND GPUVCORE_VFB_D R8967 72 71 IN GPU_VCORE_VID1 1.5K C8966 R8965 72 71 IN GPU_VCORE_PWRCTL1 4.99K2 1% 1/16W MF-LF 402 A 5% 1/16W MF-LF 402 NO STUFF NO STUFF PC1_DIV NO STUFF R89661 1K 10% 16V CERM 402 5% 1/16W MF-LF 402 PC1_BIAS NO STUFF R8968 1K 10K 5% 1/16W MF-LF 402 74 PC1_BIAS_B Q8927 2N7002DW-X-F GPU_VCORE_VID1_RC G SOT-363 S C8974 0.1UF 20% 10V CERM 402 NO STUFF R8969 0.01UF GPUVCORE_VFB_PC1 NO STUFF 7.5K Q8923 D R8974 NO STUFF 74 GND_GPUVCORE_SGND MMDT3904XF GPU (G84M) Core Supply GPUVCORE_VFB_E SOT-363-LF 5% 1/16W MF-LF 402 GND_GPUVCORE_SGND 5% 1/16W MF-LF 402 SYNC_MASTER=(MASTER) 74 Q8925 D R8975 72 71 IN 7.5K GPU_VCORE_VID2 5% 1/16W MF-LF 402 2N7002DW-X-F GPU_VCORE_VID2_RC G SOT-363 S THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING C8975 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT 0.1UF 20% 10V CERM 402 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART 74 SIZE GND_GPUVCORE_SGND APPLE COMPUTER INC DRAWING NUMBER D SHT NONE REV 051-7225 SCALE SYNC_DATE=(MASTER) NOTICE OF PROPRIETARY PROPERTY 14.0.0 OF 74 88 A D D LCD (LVDS) INTERFACE 57 55 48 46 28 27 26 25 24 87 65 60 PP3V3_S5 C9000 0.0022uF R90001 100K 5% 1/16W MF-LF 402 CRITICAL 10% 50V CERM 402 R9001 100K L9000 LCD_PWREN_L_RC G 5% 1/16W MF-LF 402 LCD_PWREN_L FERR-250-OHM PP3V3_SW_LCD_UF S MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=3.3V SM C9001 0.001uF TSOP-LF D 20% 50V CERM 402 SI3443DV Q9000 Q9001 D CRITICAL 2N7002 77 IN LVDS_PANEL_EN J9000 SOT23-LF S R90941 C G 87 77 74 65 59 58 57 52 51 27 26 25 24 23 21 19 16 13 50 48 47 46 42 32 31 30 29 28 MSC-RB30-5-FA F-RT-SM 34 PP3V3_S0 100K 5% 1/16W MF-LF 402 R9010 100K pull-ups are for 100K no-panel case (development) 5% 1/16W Panel has 2K pull-ups MF-LF 402 77 15 77 15 R9011 PP3V3_SW_LCD 100K MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=3.3V 5% 1/16W MF-LF 402 87 77 LVDS_L_DATA_CONN_N LVDS_L_DATA_CONN_P 87 77 87 77 CRITICAL LVDS_L_DATA_CONN_N LVDS_L_DATA_CONN_P 87 77 1210-4SM1 SYM_VER-1 87 77 LVDS_L_DATA_CONN_N LVDS_L_DATA_CONN_P 12 14 15 16 87 11 13 L9010 90-OHM-100MA LVDS_L_CLK_CONN_P 10 20% 50V CERM 402 87 77 C9010 1 0.001uF LVDS_L_CLK_CONN_N LVDS_CONN_DDC_CLK LVDS_CONN_DDC_DATA 87 77 87 77 C 1 87 LVDS_L_CLK_CONN_F_N LVDS_L_CLK_CONN_F_P 17 18 19 PLACEMENT_NOTE=Place close to connector 87 77 87 77 LVDS_U_DATA_CONN_N LVDS_U_DATA_CONN_P 20 21 22 87 77 87 77 CRITICAL 87 77 1210-4SM1 SYM_VER-1 87 77 87 77 LVDS_U_CLK_CONN_N 87 77 LVDS_U_CLK_CONN_P 23 24 25 L9011 90-OHM-100MA B LVDS_U_DATA_CONN_N LVDS_U_DATA_CONN_P LVDS_U_DATA_CONN_N LVDS_U_DATA_CONN_P B 26 27 28 LVDS_U_CLK_CONN_F_N LVDS_U_CLK_CONN_F_P PLACEMENT_NOTE=Place close to connector 29 30 33 518S0289 LVDS Display Connector SYNC_MASTER=(MASTER) A SYNC_DATE=(MASTER) NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE APPLE COMPUTER INC DRAWING NUMBER D SCALE SHT NONE REV 051-7225 14.0.0 OF 75 88 A TMDS Filtering (Place close to GPU) 86 73 76 73 72 IN CRITICAL R94621 90-OHM-100MA C9462 PP3V3_GPU_TMDS NO STUFF 0.01UF 10% 16V CERM 402 D 1210-4SM1 SYM_VER-1 1% 1/16W MF-LF 402 SIGNAL_MODEL=EMPTY 86 73 IN TMDS_DATA_P 86 73 IN TMDS_DATA_N 1% C9466 86 73 IN IN 1% TMDS_DATA_F_P 77 76 74 73 72 71 65 57 48 76 87 86 73 C R9471 TMDS_DATA_F_N 76 87 TMDS_DATA_F_P 76 87 NO STUFF 76 73 72 R9474 49.9 C9474 10% 16V CERM 402 87 TMDS_CLK_R_N SM-LF SM SYM_VER-1 76 TMDS_CLK_F_N 86 73 IN TMDS_CLK_F_P R94781 49.9 NO STUFF 0.01UF 10% 16V CERM 402 1% 1/16W MF-LF 402 SIGNAL_MODEL=EMPTY PP3V3_GPU_TMDS NO STUFF R9479 86 73 IN TMDS_DATA_P 86 73 IN TMDS_DATA_N 1% R9482 49.9 NO STUFF 0.01UF 10% 16V CERM 402 87 76 87 TMDS_CLK_R_P 87 76 1% 1/16W MF-LF 402 SIGNAL_MODEL=EMPTY PP3V3_GPU_TMDS NO STUFF R9483 TMDS_DATA_F_N 17 TMDS_DATA_F_P 18 87 76 TMDS_DATA_F_N 20 87 76 TMDS_DATA_F_P 21 CRITICAL L9476 90-OHM-100MA 1210-4SM1 SYM_VER-1 TMDS_DATA_F_N TMDS_DATA_F_P 22 76 87 87 76 TMDS_CLK_F_P 23 87 76 TMDS_CLK_F_N 24 76 87 PLACEMENT_NOTE=Place close to connector 87 76 VGA_B 87 76 VGA_HSYNC C3 C5B C4 R9445 L9480 90-OHM-100MA 86 73 A 76 73 72 IN TMDS_DATA_P IN TMDS_DATA_N 1% TMDS_DATA_F_N 76 87 TMDS_DATA_F_P 76 87 1% 1/16W MF-LF 402 C9486 0.01UF 10% 16V CERM 402 IN CRITICAL R94861 90-OHM-100MA PP3V3_GPU_TMDS NO STUFF R9487 TMDS_DATA_P 1% CX9400 L9484 NONE NONE NONE 402 SHORT TMDS_DATA_F_N 76 87 TMDS_DATA_F_P 76 87 76 76 87 NONE NONE NONE 402 GPU_DVI_DDC_CLK D DVI_DDC_DATA S GPU_DVI_DDC_DATA 5% 50V CERM 402 S G D R9414 S 71 72 R9422 G Q9414 270K D 2N7002DW-X-F SOT-363 5% 1/16W MF-LF 402 DVI_HPD GPU_HPD 5% 1/16W MF-LF 402 PP5V_S0 27 42 47 52 57 58 59 65 76 78 1 150 20% 50V CERM 603 1% 1/16W MF-LF 402 OMIT R9423 VGA_TERM_CONN CX9492 C9414 100pF 5% 50V CERM 402 Q9415 270K 2N7002DW-X-F 5% 1/16W MF-LF 402 G SOT-363 D S DVI_HOTPLUG_DET OUT 24 OMIT SHORT NONE NONE NONE 402 R9415 CX9493 20K 5% 1/16W MF-LF 402 SHORT NONE NONE 402 NONE OMIT CX9401 SHORT NONE NONE NONE 402 OMIT CX9402 SHORT NONE NONE NONE 402 OMIT SYNC_MASTER=(MASTER) CX9403 SHORT SYNC_DATE=(MASTER) NOTICE OF PROPRIETARY PROPERTY NONE NONE NONE 402 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING GND_CHASSIS_DVI_BOT I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT PLACEMENT_NOTE=Place close to connector III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART 49.9 SIZE 1/16W MF-LF 402 APPLE COMPUTER INC DRAWING NUMBER D REV 051-7225 SHT NONE OUT B SCALE 28 77 GPU_IOENABLE_RC C9413 100 IN GPU_HPD_BILAT 100pF 76 87 72 73 5% 1/16W MF-LF 402 G 76 87 76 87 OUT 10K SOT-363 R9413 76 87 72 73 R9421 Q9411 100 OUT 76 87 OMIT SHORT S 2N7002DW-X-F 76 87 1% 1/16W MF-LF 402 CX9491 D DVI_DDC_CLK 5% 1/16W MF-LF 402 R9443 R9444 C9410 0.01uF DVI Display Connector 1210-4SM1 SYM_VER-1 C9411 5% 50V CERM 402 76 87 5% 1/16W MF-LF 402 G SOT-363 GND_CHASSIS_DVI_TOP 1 100 10K 2N7002DW-X-F 100pF 76 87 VGA_G 514-0278 CX9490 76 87 76 87 OMIT NO STUFF 1% 1/16W MF-LF 402 SIGNAL_MODEL=EMPTY VGA_VSYNC DVI_HPD_R 32 NONE NONE NONE 402 86 73 VGA_R SHORT 49.9 NO STUFF C1 C5A C2 TMDS_DATA_F_N TMDS_DATA_F_N TMDS_DATA_F_P TMDS_DATA_F_P DVI_DDC_CLK_R (PP5V_S0_DDC) DVI_DDC_DATA_R 150 PLACEMENT_NOTE=Place close to connector Q9411 5% 1/16W MF-LF 402 OMIT 1/16W MF-LF 402 PP3V3_GPU_TMDS TMDS_DATA_F_N TMDS_DATA_F_N TMDS_DATA_F_P TMDS_DATA_F_P 150 1210-4SM1 SYM_VER-1 R9420 5% 1/16W MF-LF 402 VGA_TERM_CONN 34 4.7K R9411 10 11 12 13 14 15 16 PP3V3_GPU R9412 5% 1/16W MF-LF 402 VGA_TERM_CONN CRITICAL 77 76 74 73 72 71 65 57 48 4.7K 31 19 GPU Isolation / Level-Shift PP5V_S0_DDC_PULLUPS MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=5V R94101 33 49.9 86 73 C F-RT-TH-DVI 1/16W MF-LF 402 PP3V3_GPU_TMDS C9482 B0530WXF QH11121-RIG02-4F 49.9 NO STUFF 76 73 72 MIN_LINE_WIDTH=0.38 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=5V SM-1 GND_CHASSIS_DVI_BOT 76 87 TMDS_DATA_N C9478 PP5V_S0_DDC CRITICAL R9473 PP3V3_GPU_TMDS 3.3pF D9410 SOD-123 J9400 NO STUFF 76 73 72 MIN_LINE_WIDTH=0.38 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=5V PP5V_S0_DDC_F 76 87 5% 1/16W MF-LF 402 B L9472 370-OHM 1 C9442 0.25% 50V CERM 402 Isolation required for DVI->ADC Adapter L9410 400-OHM-EMI 0.5AMP-13.2V PLACEMENT_NOTE=Place close to connector 1% 1/16W MF-LF 402 150 R9475 TMDS_CLK_P VGA_R 76 87 (DACB TV C) 1% 1/16W MF-LF 402 CRITICAL F9410 PP5V_S0 CRITICAL NO STUFF 49.9 IN PP3V3_GPU_TMDS 0.01UF 86 73 1% 1/16W MF-LF 402 SIGNAL_MODEL=EMPTY NO STUFF 3.3pF MEA2010P-SM (55mA requirement per DVI spec) 5% 1/16W MF-LF 402 PP3V3_GPU_TMDS C9441 0.25% 50V CERM 402 210MHZ R94421 76 87 5% 1/16W MF-LF 402 CRITICAL 1 DVI INTERFACE 1/16W MF-LF 402 TMDS_CLK_N VGA_G 76 87 (DACB TV Y) DVI DDC Current Limit R9472 IN U9451 PLACEMENT_NOTE=Place close to connector 65 59 58 57 52 47 42 27 78 76 86 73 1210-4SM1 SYM_VER-1 PP3V3_GPU_TMDS NO STUFF 1% 20% 10V CERM 402 L9468 90-OHM-100MA 1% 1/16W MF-LF 402 SIGNAL_MODEL=EMPTY TMDS_DATA_P GPU_TV_C_VGA_R VGA_TERM_FILTER IN 0.1uF CRITICAL 49.9 IN GPU_VGA_HSYNC C9451 49.9 10% 16V CERM 402 86 73 IN 86 72 R9451 49.9 R9470 0.01UF PLACEMENT_NOTE=Place close to connector MC74VHC1G08 SC70 33 87 VGA_HSYNC_R VGA_HSYNC 76 87 1/16W MF-LF 402 PP3V3_GPU_TMDS 1% 1/16W MF-LF 402 PP3V3_GPU PLACEMENT_NOTE=Place close to connector 0.25% 50V CERM 402 R94411 TMDS_DATA_F_N FL9440 150 D C9440 3.3pF GPU_TV_Y_VGA_G IN CRITICAL 150 1% 1/16W MF-LF 402 VGA_TERM_FILTER TMDS_DATA_N R94401 L9464 R9467 TMDS_DATA_P C9470 VGA_TERM_FILTER 1210-4SM1 SYM_VER-1 VGA_B 76 87 (DACB TV COMP) GPU_TV_COMP_VGA_B IN 90-OHM-100MA PP3V3_GPU_TMDS NO STUFF NO STUFF 86 72 CRITICAL NO STUFF 76 73 72 C9450 76 87 5% 1/16W MF-LF 402 86 72 86 73 R9450 U9450 20% 10V CERM 402 1% 1/16W MF-LF 402 SIGNAL_MODEL=EMPTY IN 76 87 GPU_VGA_VSYNC 0.1uF 49.9 10% 16V CERM 402 TMDS_DATA_F_P 86 73 PLACEMENT_NOTE=Place close to connector R94661 0.01UF PLACEMENT_NOTE=Place close to connector MC74VHC1G08 SC70 33 87 VGA_VSYNC_R VGA_VSYNC 76 87 1/16W MF-LF 402 PP3V3_GPU_TMDS NO STUFF TMDS_DATA_F_N 49.9 NO STUFF 76 73 72 R9463 PP3V3_GPU L9460 49.9 NO STUFF 77 76 74 73 72 71 65 57 48 NO STUFF ANALOG FILTERING PLACE CLOSE TO CONNECTOR VGA SYNC Buffers (Place close to connector) TMDS_DATA_N PP3V3_GPU_TMDS 14.0.0 OF 76 88 A LVDS I/F Mux PGOOD Monitor for GPU Rails 77 PP2V5_S0_LVDS_MUX Alias to 3.3V if not used-> 77 76 74 73 72 71 65 57 48 73 70 69 68 67 57 74 71 68 66 57 PP3V3_GPU PP3V3_GPU PP1V8_GPU PP1V25_GPU C9591 C9590 C9592 0.1UF 0.1UF R9593 10 20% 10V CERM 402 124K 1% 1/16W MF-LF 402 V1 GPU_PGOOD_P1V2_DIV R9594 V3 V4 R9590 28K 1% 1/16W MF-LF 402 U9590 VREF VPG CRT GND NB LVDS I/F PM_ALL_GPU_PGOOD OUT 28 30 77 GPU_PGOOD_CRT THRM_PAD Fast wake condition is worst case ICHx can create an S3 duration of RTC clock (32 us) If mux select is on core well and AND-gate is implemented, glitch filter or 50 mils preferred TABLE_SPACING_RULE_ITEM CPU_ITP * =2:1_SPACING ? TABLE_SPACING_RULE_ITEM CPU_VCCSENSE * 25 MIL ? Most CPU signals with impedance requirements are 55-ohm single-ended Some signals require 27.4-ohm single-ended impedance (See above) SOURCE: Santa Rosa Platform DG, Rev 0.9 (#20517), Sections 4.4 & 5.8.2.4 CPU_BSEL0 (See above) CPU_BSEL1 (See above) CPU_BSEL2 (See above) B (FSB_CPURST_L) CPU_VCCSENSE CPU_VCCSENSE CPU_2TO1 CPU_2TO1 CPU_2TO1 CPU_2TO1 CPU_2TO1 CPU_2TO1 CPU_2TO1 CPU_2TO1 CPU_2TO1 CPU_IERR_L CPU_FERR_L CPU_PROCHOT_L CPU_PWRGD CPU_INTR CPU_NMI CPU_A20M_L CPU_DPSLP_L CPU_IGNNE_L CPU_INIT_L CPU_SMI_L CPU_STPCLK_L PM_THRMTRIP_L FSB_CPUSLP_L PM_DPRSLPVR IMVP_DPRSLPVR CPU_BSEL NB_BSEL CPU_BSEL NB_BSEL CPU_BSEL NB_BSEL CPU_DPRSTP_L CPU_55S CPU_55S CPU_27P4S CPU_55S CPU_27P4S CPU_GTLREF CPU_COMP CPU_COMP CPU_COMP CPU_COMP CPU_GTLREF CPU_COMP CPU_COMP CPU_COMP CPU_COMP CPU_55S CPU_55S CPU_55S CPU_55S CPU_55S CPU_55S CPU_55S CLK_FSB_100D CLK_FSB_100D CPU_55S CPU_ITP CPU_ITP CPU_ITP CPU_ITP CPU_ITP CPU_ITP CPU_ITP CLK_FSB CLK_FSB CPU_ITP XDP_TDI XDP_TDO XDP_TMS XDP_TCK XDP_TRST_L XDP_BPM_L XDP_BPM_L XDP_CLK_P XDP_CLK_N XDP_CPURST_L CPU_55S CPU_55S CPU_27P4S CPU_27P4S CPU_27P4S CPU_27P4S CPU_2TO1 CPU_2TO1 CPU_VCCSENSE CPU_VCCSENSE CPU_VCCSENSE CPU_VCCSENSE CPU_VID IMVP6_VID CPU_VCCSENSE_P CPU_VCCSENSE_N IMVP6_VSEN_P IMVP6_VSEN_N CPU_2TO1 CPU_2TO1 10 10 23 10 46 58 10 13 23 10 23 10 23 10 23 10 23 10 23 10 23 47 10 23 10 23 10 16 23 46 10 14 16 25 58 58 10 30 13 16 30 10 30 13 16 30 10 30 13 16 30 B 10 16 23 58 10 10 10 10 10 10 13 10 13 10 13 10 13 10 13 10 13 10 13 13 29 30 84 13 29 30 84 13 11 12 12 58 11 58 11 58 58 58 CPU/FSB Constraints SYNC_MASTER=T9_NOME A SYNC_DATE=01/17/2007 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE APPLE COMPUTER INC DRAWING NUMBER D SCALE SHT NONE REV 051-7225 14.0.0 OF 79 88 A PCI-Express / DMI Bus Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP PCIE_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF DMI_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF ELECTRICAL_CONSTRAINT_SET NET_TYPE PHYSICAL SPACING TABLE_PHYSICAL_RULE_ITEM PEG_R2D TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT PEG_D2R TABLE_SPACING_RULE_ITEM PCIE * ? 20 MIL TABLE_SPACING_RULE_ITEM DMI D * ? 20 MIL SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Sections 7.2, 9.2 & 10.5 DMI_N2S Video Signal Constraints DMI_S2N TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP LVDS_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF CRT_50S * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD LVDS_A_CLK LVDS_A_CLK LVDS_A_DATA LVDS_A_DATA LVDS_A_DATA3 LVDS_A_DATA3 LVDS_B_CLK LVDS_B_CLK LVDS_B_DATA LVDS_B_DATA LVDS_B_DATA3 LVDS_B_DATA3 LVDS_IBG TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM CRT_55S * =55_OHM_SE SPACING_RULE_SET LAYER =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD TABLE_SPACING_RULE_HEAD LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM LVDS * 20 MIL ? CRT * 25 MIL ? TABLE_SPACING_RULE_ITEM DG Says 40 mil spacing minimum TABLE_SPACING_RULE_ITEM CRT_2CRT * 20 MIL ? CRT_SYNC * 25 MIL ? CRT_SYNC2SYNC * 20 MIL ? TVDAC * 25 MIL ? TVDAC_2TVDAC * 20 MIL ? TABLE_SPACING_RULE_ITEM DG Says 30 mil spacing minimum PCIE_100D PCIE_100D PCIE_100D PCIE_100D PCIE_100D PCIE_100D PCIE_100D PCIE_100D PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PEG_R2D_P PEG_R2D_N PEG_R2D_C_P PEG_R2D_C_N PEG_D2R_P PEG_D2R_N PEG_D2R_C_P PEG_D2R_C_N DMI_100D DMI_100D DMI_100D DMI_100D DMI DMI DMI DMI DMI_N2S_P DMI_N2S_N DMI_S2N_P DMI_S2N_N LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS_A_CLK_P LVDS_A_CLK_N LVDS_A_DATA_P LVDS_A_DATA_N LVDS_A_DATA_P LVDS_A_DATA_N LVDS_B_CLK_P LVDS_B_CLK_N LVDS_B_DATA_P LVDS_B_DATA_N LVDS_B_DATA_P LVDS_B_DATA_N LVDS_IBG CRT CRT CRT CRT CRT_SYNC CRT_SYNC TVDAC TVDAC TVDAC CRT_TVO_IREF CRT_RED CRT_GREEN CRT_BLUE CRT_HSYNC_R CRT_VSYNC_R TV_A_DAC TV_B_DAC TV_C_DAC 66 66 15 66 15 66 15 66 15 66 66 66 D 16 24 16 24 16 24 16 24 15 77 15 77 15 77 15 77 15 77 15 77 15 77 15 77 15 22 TABLE_SPACING_RULE_ITEM CRT_TVO_IREF CRT_RED CRT_GREEN CRT_BLUE CRT_SYNC CRT_SYNC TV_A_DAC TV_B_DAC TV_C_DAC TABLE_SPACING_RULE_ITEM DG Says 40 mil spacing minimum TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET TABLE_SPACING_ASSIGNMENT_ITEM C CRT CRT * CRT_2CRT CRT_SYNC CRT_SYNC * CRT_SYNC2SYNC TVDAC TVDAC * TVDAC_2TVDAC TABLE_SPACING_ASSIGNMENT_ITEM CRT_50S CRT_50S CRT_50S CRT_55S CRT_55S CRT_50S CRT_50S CRT_50S C TABLE_SPACING_ASSIGNMENT_ITEM LVDS signals are 100-ohm +/- 20% differential impedence CRT & TVDAC signal single-ended impedence varies by location: - 37.5-ohm +/- 15% from GMCH to first termination resistor - 50-ohm +/- 15% from first to second termination resistor - 55-ohm +/- 15% from second termination resistor to connector CRT_HSYNC/CRT_VSYNC signals are 55-ohm +/- 15% single-ended impedence SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Sections 8.1 - 8.3 B B NB Constraints SYNC_MASTER=T9_NOME A SYNC_DATE=01/17/2007 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE APPLE COMPUTER INC DRAWING NUMBER D SCALE SHT NONE REV 051-7225 14.0.0 OF 80 88 A DDR2 Memory Bus Constraints Memory Net Properties TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP MEM_45S * =45_OHM_SE =45_OHM_SE =45_OHM_SE =45_OHM_SE =STANDARD =STANDARD MEM_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD ELECTRICAL_CONSTRAINT_SET NET_TYPE PHYSICAL SPACING TABLE_PHYSICAL_RULE_ITEM MEM_A_CLK MEM_70D MEM_70D MEM_CLK MEM_CLK MEM_CLK_P MEM_CLK_N MEM_A_CNTL MEM_A_CNTL MEM_A_CNTL MEM_45S MEM_45S MEM_45S MEM_CTRL MEM_CTRL MEM_CTRL MEM_CKE MEM_CS_L MEM_ODT MEM_A_CMD MEM_A_CMD MEM_A_CMD MEM_A_CMD MEM_A_CMD MEM_55S MEM_55S MEM_55S MEM_55S MEM_55S MEM_CMD MEM_CMD MEM_CMD MEM_CMD MEM_CMD MEM_A_A MEM_A_BS MEM_A_RAS_L MEM_A_CAS_L MEM_A_WE_L MEM_A_DQ_BYTE0 MEM_A_DQ_BYTE1 MEM_A_DQ_BYTE2 MEM_A_DQ_BYTE3 MEM_A_DQ_BYTE4 MEM_A_DQ_BYTE5 MEM_A_DQ_BYTE6 MEM_A_DQ_BYTE7 MEM_55S MEM_55S MEM_55S MEM_55S MEM_55S MEM_55S MEM_55S MEM_55S MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DM0 MEM_A_DM1 MEM_A_DM2 MEM_A_DM3 MEM_A_DM4 MEM_A_DM5 MEM_A_DM6 MEM_A_DM7 MEM_55S MEM_55S MEM_55S MEM_55S MEM_55S MEM_55S MEM_55S MEM_55S MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_A_DM MEM_A_DM MEM_A_DM MEM_A_DM MEM_A_DM MEM_A_DM MEM_A_DM MEM_A_DM MEM_A_DQS0 MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_B_CLK MEM_70D MEM_70D MEM_CLK MEM_CLK MEM_CLK_P MEM_CLK_N MEM_B_CNTL MEM_B_CNTL MEM_B_CNTL MEM_45S MEM_45S MEM_45S MEM_CTRL MEM_CTRL MEM_CTRL MEM_CKE MEM_CS_L MEM_ODT MEM_B_CMD MEM_B_CMD MEM_B_CMD MEM_B_CMD MEM_B_CMD MEM_55S MEM_55S MEM_55S MEM_55S MEM_55S MEM_CMD MEM_CMD MEM_CMD MEM_CMD MEM_CMD MEM_B_A MEM_B_BS MEM_B_RAS_L MEM_B_CAS_L MEM_B_WE_L MEM_B_DQ_BYTE0 MEM_B_DQ_BYTE1 MEM_B_DQ_BYTE2 MEM_B_DQ_BYTE3 MEM_B_DQ_BYTE4 MEM_B_DQ_BYTE5 MEM_B_DQ_BYTE6 MEM_B_DQ_BYTE7 MEM_55S MEM_55S MEM_55S MEM_55S MEM_55S MEM_55S MEM_55S MEM_55S MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DM0 MEM_B_DM1 MEM_B_DM2 MEM_B_DM3 MEM_B_DM4 MEM_B_DM5 MEM_B_DM6 MEM_B_DM7 MEM_55S MEM_55S MEM_55S MEM_55S MEM_55S MEM_55S MEM_55S MEM_55S MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_B_DM MEM_B_DM MEM_B_DM MEM_B_DM MEM_B_DM MEM_B_DM MEM_B_DM MEM_B_DM MEM_B_DQS0 MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N TABLE_PHYSICAL_RULE_ITEM 16 31 16 31 TABLE_PHYSICAL_RULE_ITEM MEM_70D * =70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF MEM_85D * =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF SPACING_RULE_SET LAYER TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_HEAD D LINE-TO-LINE SPACING WEIGHT =4:1_SPACING ? TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET MEM_CLK MEM_CLK * MEM_CLK2MEM TABLE_SPACING_RULE_ITEM MEM_CLK2MEM * TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_RULE_ITEM MEM_CTRL2CTRL * TABLE_SPACING_ASSIGNMENT_ITEM ? =2:1_SPACING MEM_CLK MEM_CTRL * MEM_CLK2MEM TABLE_SPACING_RULE_ITEM MEM_CTRL2MEM * MEM_CLK MEM_CMD * MEM_CLK2MEM MEM_CLK MEM_DATA * MEM_CLK2MEM TABLE_SPACING_RULE_ITEM MEM_CMD2CMD * =1.5:1_SPACING TABLE_SPACING_ASSIGNMENT_ITEM ? TABLE_SPACING_RULE_ITEM MEM_CMD2MEM * TABLE_SPACING_ASSIGNMENT_ITEM ? =3:1_SPACING MEM_CLK MEM_DQS * MEM_CLK2MEM TABLE_SPACING_RULE_ITEM MEM_DATA2DATA * =1.5:1_SPACING ? TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 TABLE_SPACING_RULE_ITEM MEM_DATA2MEM * =3:1_SPACING ? NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET TABLE_SPACING_ASSIGNMENT_ITEM MEM_CMD TABLE_SPACING_RULE_ITEM MEM_DQS2MEM * =3:1_SPACING 16 31 33 16 31 33 16 17 31 33 17 31 33 D 17 31 33 17 31 33 17 31 33 TABLE_SPACING_ASSIGNMENT_ITEM ? =3:1_SPACING 16 31 33 ? MEM_CLK * MEM_CMD2MEM 17 31 17 31 17 31 17 31 17 31 17 31 17 31 17 31 TABLE_SPACING_ASSIGNMENT_ITEM MEM_CMD TABLE_SPACING_RULE_ITEM MEM_2OTHER * 25 MIL ? MEM_CTRL * MEM_CMD2MEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CMD MEM_CMD * MEM_CMD2CMD TABLE_SPACING_ASSIGNMENT_ITEM MEM_CMD MEM_DATA * MEM_CMD2MEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CMD MEM_DQS * MEM_CMD2MEM TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET MEM_CTRL MEM_CLK * MEM_CTRL2MEM 17 31 17 31 17 31 17 31 17 31 17 31 17 31 17 31 TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CTRL MEM_CTRL * MEM_CTRL2CTRL MEM_A_DQS1 TABLE_SPACING_ASSIGNMENT_ITEM MEM_CTRL MEM_CMD * MEM_CTRL2MEM MEM_CTRL MEM_DATA * MEM_CTRL2MEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_A_DQS2 TABLE_SPACING_ASSIGNMENT_ITEM C MEM_CTRL MEM_DQS * MEM_CTRL2MEM NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET MEM_DATA MEM_CLK * MEM_DATA2MEM MEM_DATA MEM_CTRL * MEM_DATA2MEM MEM_A_DQS3 TABLE_SPACING_ASSIGNMENT_HEAD MEM_A_DQS4 TABLE_SPACING_ASSIGNMENT_ITEM MEM_A_DQS5 TABLE_SPACING_ASSIGNMENT_ITEM MEM_A_DQS6 TABLE_SPACING_ASSIGNMENT_ITEM MEM_DATA MEM_CMD * MEM_DATA2MEM MEM_DATA MEM_DATA * MEM_DATA2DATA TABLE_SPACING_ASSIGNMENT_ITEM MEM_A_DQS7 TABLE_SPACING_ASSIGNMENT_ITEM MEM_DATA MEM_DQS * MEM_DATA2MEM TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE MEM_CLK * * MEM_2OTHER * * MEM_2OTHER TABLE_SPACING_ASSIGNMENT_ITEM MEM_DQS MEM_CLK * MEM_DQS2MEM MEM_DQS MEM_CTRL * MEM_DQS2MEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CMD * * MEM_2OTHER MEM_DATA * * MEM_2OTHER MEM_DQS * * MEM_2OTHER 17 31 17 31 17 31 17 31 17 31 C 17 31 17 31 17 31 17 31 17 31 17 31 17 31 17 31 17 31 17 31 16 32 16 32 SPACING_RULE_SET TABLE_SPACING_ASSIGNMENT_ITEM MEM_CTRL 17 31 16 32 33 16 32 33 16 32 33 TABLE_SPACING_ASSIGNMENT_ITEM MEM_DQS MEM_CMD * MEM_DQS2MEM MEM_DQS MEM_DATA * MEM_DQS2MEM MEM_DQS MEM_DQS * MEM_DQS2MEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM Need to support MEM_*-style wildcards! SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Section 6.2 B MEM_B_DQS1 MEM_B_DQS2 MEM_B_DQS3 MEM_B_DQS4 MEM_B_DQS5 MEM_B_DQS6 A MEM_B_DQS7 16 17 32 33 17 32 33 17 32 33 17 32 33 17 32 33 17 32 17 32 17 32 17 32 B 17 32 17 32 17 32 17 32 17 32 17 32 17 32 17 32 17 32 17 32 17 32 17 32 17 32 17 32 17 32 17 32 17 32 17 32 17 32 17 32 17 32 17 32 17 32 Memory Constraints 17 32 17 32 SYNC_MASTER=T9_NOME SYNC_DATE=01/17/2007 17 32 NOTICE OF PROPRIETARY PROPERTY 17 32 17 32 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE APPLE COMPUTER INC DRAWING NUMBER D SCALE SHT NONE REV 051-7225 14.0.0 OF 81 88 A Disk Interface Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP IDE_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD SATA_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD ELECTRICAL_CONSTRAINT_SET NET_TYPE PHYSICAL SPACING TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM SATA_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM D IDE * =1.8:1_SPACING ? SATA * 20 MIL ? TABLE_SPACING_RULE_ITEM SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Sections 10.7 & 10.9 HD Audio Interface Constraints IDE_PDD IDE_PDA IDE_PDCS IDE_PDCS IDE_CNTL IDE_PDIOR_L IDE_CNTL IDE_CNTL IDE_PDIORDY IDE_IRQ14 IDE_RST_L IDE_55S IDE_55S IDE_55S IDE_55S IDE_55S IDE_55S IDE_55S IDE_55S IDE_55S IDE_55S IDE_55S IDE IDE IDE IDE IDE IDE IDE IDE IDE IDE IDE IDE_PDD IDE_PDA IDE_PDCS1_L IDE_PDCS3_L IDE_PDIOW_L IDE_PDIOR_L IDE_PDDACK_L IDE_PDDREQ IDE_PDIORDY IDE_IRQ14 ODD_RST_5VTOL_L SATA_A_R2D SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D SATA_55S SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA_A_R2D_C_P SATA_A_R2D_C_N SATA_A_R2D_P SATA_A_R2D_N SATA_A_D2R_P SATA_A_D2R_N SATA_A_D2R_C_P SATA_A_D2R_C_N TP_SATA_B_R2DP TP_SATA_B_R2DN SATA_B_R2D_P SATA_B_R2D_N TP_SATA_B_D2RP TP_SATA_B_D2RN SATA_B_D2R_C_P SATA_B_D2R_C_N TP_SATA_C_R2DP TP_SATA_C_R2DN SATA_C_R2D_P SATA_C_R2D_N TP_SATA_C_D2RP TP_SATA_C_D2RN SATA_C_D2R_C_P SATA_C_D2R_C_N SATA_RBIAS HDA_55S HDA_55S HDA_55S HDA_55S HDA_55S HDA_55S HDA_55S HDA_55S HDA_55S HDA_55S HDA HDA HDA HDA HDA HDA HDA HDA HDA HDA HDA_BIT_CLK HDA_BIT_CLK_R HDA_SYNC HDA_SYNC_R HDA_RST_L HDA_RST_L_R HDA_SDIN0 HDA_SDIN_CODEC HDA_SDOUT HDA_SDOUT_R USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB_RBIAS USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_60S USB_EXTA_P USB_EXTA_N USB_EXTA_MUXED_P USB_EXTA_MUXED_N USB_MINI_P USB_MINI_N USB_WWAN_P USB_WWAN_N USB_CAMERA_P USB_CAMERA_N USB_BT_P USB_BT_N USB_TPAD_P USB_TPAD_N USB_IR_P USB_IR_N USB_EXTB_P USB_EXTB_N USB_EXCARD_P USB_EXCARD_N TP_USB_EXTCP TP_USB_EXTCN USB_RBIAS SMB_SB_SCL SMB_SB_SDA SMB_SB_ME_SCL SMB_SB_ME_SDA SMB_55S SMB_55S SMB_55S SMB_55S SMB SMB SMB SMB SMBUS_SB_SCL SMBUS_SB_SDA SMBUS_SB_ME_SCL SMBUS_SB_ME_SDA SPI_SCLK SPI_55S SPI_55S SPI_55S SPI_55S SPI_55S SPI_55S SPI_55S SPI_55S SPI_55S SPI_55S SPI_55S SPI_55S SPI_55S SPI_55S SPI_55S SPI_55S SPI SPI SPI SPI SPI SPI SPI SPI SPI SPI SPI SPI SPI SPI SPI SPI SPI_SCLK_R SPI_SCLK SPI_A_SCLK_R SPI_B_SCLK_R SPI_SI_R SPI_SI SPI_A_SI_R SPI_B_SI_R SPI_SO SPI_A_SO_R SPI_B_SO SPI_B_SO_R SPI_CE_R_L SPI_CE_L SPI_CE_R_L SPI_CE_L TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM HDA_55S * SPACING_RULE_SET LAYER =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD SATA_A_D2R TABLE_SPACING_RULE_HEAD LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM HDA * =1.8:1_SPACING ? SATA_B_R2D SOURCE: Napa Platform DG, Rev 0.9 (#17978), Section 10.9.1 USB 2.0 Interface Constraints SATA_B_D2R TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM USB_60S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD USB_90D * =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF SATA_C_R2D TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT 20 MIL ? SATA_C_D2R TABLE_SPACING_RULE_ITEM USB * TABLE_SPACING_RULE_ITEM C USB_2CLK * DG says minimum spacing 50 mils to clocks ? 25 MIL SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Section 10.13.2 SATA_RBIAS HDA_BIT_CLK Internal Interface Constraints HDA_SYNC TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM SMB_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD HDA_RST_L TABLE_PHYSICAL_RULE_ITEM SPI_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD HDA_SDIN0 TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT =3:1_SPACING ? HDA_SDOUT TABLE_SPACING_RULE_ITEM SMB * USB_EXTA TABLE_SPACING_RULE_ITEM SPI * =1.8:1_SPACING ? SOURCE: Santa Platform DG, Rev 1.0 (#21112), Section 10.17 USB_MINI USB_EXTD USB_CAMERA USB_BT USB_TPAD B USB_IR USB_EXTB USB_EXCARD USB_EXTC SPI_SI SPI_SO A SPI_CE_L0 SPI_CE_L1 23 42 23 42 23 42 23 42 23 42 23 42 23 42 23 42 D 23 42 23 42 24 42 23 78 23 78 78 78 23 78 23 78 78 78 23 42 23 42 23 42 23 42 23 42 23 42 23 42 23 42 C 23 42 23 34 23 23 34 23 23 34 23 23 34 23 34 23 24 43 24 43 24 34 24 34 24 44 24 44 24 44 24 44 24 78 24 78 24 78 B 24 78 24 78 24 78 24 34 24 34 24 34 24 34 24 24 24 25 29 31 32 34 48 25 29 31 32 34 48 25 48 25 48 24 55 55 24 55 55 24 55 SB Constraints (1 of 2) 55 SYNC_MASTER=T9_NOME SYNC_DATE=01/17/2007 NOTICE OF PROPRIETARY PROPERTY 24 55 55 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE APPLE COMPUTER INC DRAWING NUMBER D SCALE SHT NONE REV 051-7225 14.0.0 OF 82 88 A PCI Bus Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP PCI_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD ELECTRICAL_CONSTRAINT_SET NET_TYPE PHYSICAL SPACING TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM PCI * ? =2:1_SPACING SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Sections 10.18.1 & 10.19 D Controller Link (AMT) Constraints PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH TABLE_PHYSICAL_RULE_HEAD MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM CLINK_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD CLINK_12MIL * =STANDARD 12 MILS MILS 300 MILS =STANDARD =STANDARD SPACING_RULE_SET LAYER TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_HEAD LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM CLINK * =1.8:1_SPACING ? CLINK_VREF * 12 MILS ? TABLE_SPACING_RULE_ITEM SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Sections 10.27.1.5-7, 10.29 & 10.30 Ethernet (Yukon) Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM ENET_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT 25 MILS ? PCI_AD PCI_AD19 PCI_AD20 PCI_AD PCI_AD PCI_C_BE_L PCI_CNTL PCI_CNTL PCI_CNTL PCI_LOCK_L PCI_CNTL PCI_CNTL PCI_CNTL PCI_CNTL PCI_FW_REQ_L PCI_FW_GNT_L PCI_REQ1_L PCI_GNT1_L PCI_REQ2_L PCI_GNT2_L INT_PIRQA_L INT_PIRQB_L INT_PIRQC_L INT_PIRQD_L INT_PIRQE_L INT_PIRQF_L PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI_AD PCI_AD PCI_AD PCI_AD PCI_PAR PCI_C_BE_L PCI_IRDY_L PCI_DEVSEL_L PCI_PERR_L PCI_LOCK_L PCI_SERR_L PCI_STOP_L PCI_TRDY_L PCI_FRAME_L PCI_FW_REQ_L PCI_FW_GNT_L PCI_REQ1_L PCI_GNT1_L PCI_REQ2_L PCI_GNT2_L INT_PIRQA_L INT_PIRQB_L INT_PIRQC_L INT_PIRQD_L INT_PIRQE_L INT_PIRQF_L PCIE_A_R2D PCIE_100D PCIE_100D PCIE_100D PCIE_100D PCIE_100D PCIE_100D PCIE_100D PCIE_100D PCIE_100D PCIE_100D PCIE_100D PCIE_100D PCIE_100D PCIE_100D PCIE_100D PCIE_100D PCIE_100D PCIE_100D PCIE_100D PCIE_100D PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE_A_R2D_C_P PCIE_A_R2D_C_N PCIE_A_D2R_P PCIE_A_D2R_N PCIE_B_R2D_C_P PCIE_B_R2D_C_N PCIE_B_D2R_P PCIE_B_D2R_N PCIE_EXCARD_R2D_C_P PCIE_EXCARD_R2D_C_N PCIE_EXCARD_D2R_P PCIE_EXCARD_D2R_N PCIE_FW_R2D_C_P PCIE_FW_R2D_C_N PCIE_FW_D2R_P PCIE_FW_D2R_N PCIE_MINI_R2D_C_P PCIE_MINI_R2D_C_N PCIE_MINI_D2R_P PCIE_MINI_D2R_N TABLE_SPACING_RULE_ITEM ENET_MDI * PCIE_A_D2R SOURCE: Based on Santa Rosa Platform DG, Rev 1.0 (#21112), Sections 10.27.1.5-7, 10.29 & 10.30 PCIE_B_R2D PCIE_B_D2R C PCIE_EXCARD_R2D PCIE_EXCARD_D2R PCIE_FW_R2D PCIE_FW_D2R PCIE_MINI_R2D PCIE_MINI_D2R GLAN_COMP GLAN_COMP CLINK_NB CLINK_NB CLINK_NB_RESET_L CLINK_WLAN CLINK_WLAN CLINK_WLAN_RESET_L NB_CLINK_VREF SB_CLINK_VREF0 SB_CLINK_VREF1 CLINK_55S CLINK_55S CLINK_55S CLINK_55S CLINK_55S CLINK_55S CLINK_12MIL CLINK_12MIL CLINK_12MIL CLINK CLINK CLINK CLINK CLINK CLINK CLINK_VREF CLINK_VREF CLINK_VREF CLINK_NB_CLK CLINK_NB_DATA CLINK_NB_RESET_L CLINK_WLAN_CLK CLINK_WLAN_DATA CLINK_WLAN_RESET_L NB_CLINK_VREF SB_CLINK_VREF0 SB_CLINK_VREF1 PCIE_ENET_R2D PCIE_100D PCIE_100D PCIE_100D PCIE_100D PCIE_100D PCIE_100D PCIE_100D PCIE_100D PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE_ENET_R2D_C_P PCIE_ENET_R2D_C_N PCIE_ENET_R2D_P PCIE_ENET_R2D_N PCIE_ENET_D2R_P PCIE_ENET_D2R_N PCIE_ENET_D2R_C_P PCIE_ENET_D2R_C_N ENET_100D ENET_100D ENET_100D ENET_100D ENET_100D ENET_100D ENET_100D ENET_100D ENET_MDI ENET_MDI ENET_MDI ENET_MDI ENET_MDI ENET_MDI ENET_MDI ENET_MDI ENET_MDI_P ENET_MDI_N ENET_MDI_P ENET_MDI_N ENET_MDI_P ENET_MDI_N ENET_MDI_P ENET_MDI_N B PCIE_ENET_D2R ENET_MDI ENET_MDI ENET_MDI ENET_MDI 24 38 24 38 24 38 24 38 24 38 24 38 24 38 24 38 D 24 38 24 24 38 24 38 24 38 24 38 24 38 24 38 47 24 24 24 24 24 24 38 24 24 C 24 34 24 34 24 34 24 34 24 34 24 34 24 34 24 34 23 16 25 16 25 16 25 16 25 25 24 35 24 35 35 B 35 24 35 24 35 35 35 35 37 35 37 35 37 35 37 35 37 35 37 35 37 35 37 SB Constraints (2 of 2) SYNC_MASTER=T9_NOME A SYNC_DATE=01/17/2007 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE APPLE COMPUTER INC DRAWING NUMBER D SCALE SHT NONE REV 051-7225 14.0.0 OF 83 88 A Clock Signal Constraints Clock Net Properties TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP CLK_FSB_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF CLK_PCIE_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF ELECTRICAL_CONSTRAINT_SET NET_TYPE PHYSICAL SPACING TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM CLK_MED_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD CLK_SLOW_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD TABLE_PHYSICAL_RULE_ITEM CK505_CPU CK505_CPU CK505_NB CK505_NB CK505_ITP CK505_ITP CLK_FSB_100D CLK_FSB_100D CLK_FSB_100D CLK_FSB_100D CLK_FSB_100D CLK_FSB_100D CLK_FSB CLK_FSB CLK_FSB CLK_FSB CLK_FSB CLK_FSB FSB_CLK_CPU_P FSB_CLK_CPU_N FSB_CLK_NB_P FSB_CLK_NB_N XDP_CLK_P XDP_CLK_N CK505_PCIF0 CK505_PCIF1 CK505_PCI1 CK505_PCI2 CK505_PCI3 CK505_PCI4 CK505_PCI5 CLK_MED_55S CLK_MED_55S CLK_MED_55S CLK_MED_55S CLK_MED_55S CLK_MED_55S CLK_MED_55S CLK_MED CLK_MED CLK_MED CLK_MED CLK_MED CLK_MED CLK_MED CK505_PCIF0_CLK_ITPEN CK505_PCIF1_CLK CK505_PCI1_CLK TP_CK505_PCI2_CLK CK505_PCI3_CLK TP_CK505_PCI4_CLK CK505_PCI5_CLK_FCTSEL (CPU_BSEL0) (CPU_BSEL2) CLK_MED_55S CLK_MED_55S CLK_MED CLK_MED CK505_48M_FSA CK505_REF0_FSC CK505_DOT96 CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CK505_CLK27M CK505_CLK27M_SS NB_CLK100M_DPLLSS_P NB_CLK100M_DPLLSS_N PEG_CLK100M_GPU_P PEG_CLK100M_GPU_N SB_CLK100M_DMI_P SB_CLK100M_DMI_N PCIE_CLK100M_EXCARD_P PCIE_CLK100M_EXCARD_N SB_CLK100M_SATA_P SB_CLK100M_SATA_N NB_CLK100M_PCIE_P NB_CLK100M_PCIE_N PCIE_CLK100M_MINI_P PCIE_CLK100M_MINI_N TP_PCIE_CLK100M_SRC7P TP_PCIE_CLK100M_SRC7N PCIE_CLK100M_ENET_P PCIE_CLK100M_ENET_N (CK505_CPU) (CK505_CPU) (CK505_NB) (CK505_NB) (CK505_ITP) (CK505_ITP) CLK_FSB_100D CLK_FSB_100D CLK_FSB_100D CLK_FSB_100D CLK_FSB_100D CLK_FSB_100D CLK_FSB CLK_FSB CLK_FSB CLK_FSB CLK_FSB CLK_FSB FSB_CLK_CPU_P FSB_CLK_CPU_N FSB_CLK_NB_P FSB_CLK_NB_N XDP_CLK_P XDP_CLK_N (CK505_PCIF0) (CK505_PCIF1) (CK505_PCI1) (CK505_PCI2) (CK505_PCI3) CLK_MED_55S CLK_MED_55S CLK_MED_55S CLK_MED_55S CLK_MED_55S CLK_MED CLK_MED CLK_MED CLK_MED CLK_MED PCI_CLK33M_LPCPLUS 30 47 PCI_CLK33M_SB 24 30 PCI_CLK33M_FW 30 38 PCI_CLK33M_TPM PCI_CLK33M_SMC 30 45 CK505 PCI4 is project-specific CK505 PCI5 is project-specific (CPU_BSEL0) (CPU_BSEL2) CLK_MED_55S CLK_MED_55S CLK_MED CLK_MED SB_CLK48M_USBCTLR SB_CLK14P3M_TIMER (CPU_BSEL0) (CPU_BSEL2) CLK_MED_55S CLK_MED_55S CLK_MED CLK_MED CK505_FSA CK505_FSC (CK505_DOT96) (CK505_DOT96) (CK505_LVDS) (CK505_LVDS) (CK505_SRC1) (CK505_SRC1) (CK505_SRC2) (CK505_SRC2) (CK505_SRC3) (CK505_SRC3) (CK505_SRC4) (CK505_SRC4) (CK505_SRC5) (CK505_SRC5) (CK505_SRC6) (CK505_SRC6) CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE NB_CLK96M_DOT_P NB_CLK96M_DOT_N NB_CLK100M_DPLLSS_P NB_CLK100M_DPLLSS_N PEG_CLK100M_GPU_P PEG_CLK100M_GPU_N SB_CLK100M_DMI_P SB_CLK100M_DMI_N PCIE_CLK100M_EXCARD_P PCIE_CLK100M_EXCARD_N SB_CLK100M_SATA_P SB_CLK100M_SATA_N NB_CLK100M_PCIE_P NB_CLK100M_PCIE_N PCIE_CLK100M_MINI_P PCIE_CLK100M_MINI_N 10 29 30 84 10 29 30 84 14 29 30 84 14 29 30 84 13 29 30 79 84 13 29 30 79 84 TABLE_SPACING_RULE_HEAD SPACING_RULE_SET D LAYER LINE-TO-LINE SPACING WEIGHT 25 MIL ? TABLE_SPACING_RULE_ITEM CLK_FSB * TABLE_SPACING_RULE_ITEM CLK_PCIE * 20 MIL ? CLK_MED * 20 MIL ? TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM CLK_SLOW * 10 MIL ? SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Sections 14.1 - 14.6 CK505_LVDS CK505_SRC1 CK505_SRC2 CK505_SRC3 CK505_SRC4 CK505_SRC5 CK505_SRC6 CK505_SRC7 C CK505_SRC8 B 29 30 D 29 30 29 30 29 30 29 30 29 30 29 30 29 30 29 30 29 30 29 30 16 22 29 30 84 16 22 29 30 84 29 30 66 84 29 30 66 84 24 29 30 84 24 29 30 84 29 30 34 84 29 30 34 84 23 29 30 84 23 29 30 84 16 29 30 84 16 29 30 84 29 30 34 84 29 30 34 84 29 30 29 30 C 29 30 35 84 29 30 35 84 10 29 30 84 10 29 30 84 14 29 30 84 14 29 30 84 13 29 30 79 84 13 29 30 79 84 25 30 25 30 30 30 7 16 22 29 30 84 16 22 29 30 84 B 29 30 66 84 29 30 66 84 24 29 30 84 24 29 30 84 29 30 34 84 29 30 34 84 23 29 30 84 23 29 30 84 16 29 30 84 16 29 30 84 29 30 34 84 29 30 34 84 CK505 SRC7 is project-specific (CK505_SRC8) (CK505_SRC8) CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE CLK_PCIE PCIE_CLK100M_ENET_P PCIE_CLK100M_ENET_N 29 30 35 84 29 30 35 84 SMC SMBus Net Properties ELECTRICAL_CONSTRAINT_SET SMBUS_SMC_A_S3_SCL SMBUS_SMC_A_S3_SDA SMBUS_SMC_B_S0_SCL SMBUS_SMC_B_S0_SDA SMBUS_SMC_0_S0_SCL SMBUS_SMC_0_S0_SDA SMBUS_SMC_BSA_SCL SMBUS_SMC_BSA_SDA SMBUS_SMC_MGMT_SCL SMBUS_SMC_MGMT_SDA A NET_TYPE PHYSICAL SPACING SMB_55S SMB_55S SMB_55S SMB_55S SMB_55S SMB_55S SMB_55S SMB_55S SMB_55S SMB_55S SMB SMB SMB SMB SMB SMB SMB SMB SMB SMB SMBUS_SMC_A_S3_SCL SMBUS_SMC_A_S3_SDA SMBUS_SMC_B_S0_SCL SMBUS_SMC_B_S0_SDA SMBUS_SMC_0_S0_SCL SMBUS_SMC_0_S0_SDA SMBUS_SMC_BSA_SCL SMBUS_SMC_BSA_SDA SMBUS_SMC_MGMT_SCL SMBUS_SMC_MGMT_SDA 45 48 51 78 45 48 51 78 34 45 48 51 34 45 48 51 45 48 51 73 Clock & SMC Constraints SYNC_MASTER=T9_NOME SYNC_DATE=01/17/2007 45 48 51 73 NOTICE OF PROPRIETARY PROPERTY 45 48 56 45 48 56 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING 45 48 54 45 48 54 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE APPLE COMPUTER INC DRAWING NUMBER D SCALE SHT NONE REV 051-7225 14.0.0 OF 84 88 A FireWire Interface Constraints FireWire Net Properties TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP FW_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD FW_110D * =110_OHM_DIFF =110_OHM_DIFF =110_OHM_DIFF =110_OHM_DIFF =110_OHM_DIFF =110_OHM_DIFF SPACING_RULE_SET LAYER ELECTRICAL_CONSTRAINT_SET NET_TYPE SPACING PHYSICAL TABLE_PHYSICAL_RULE_ITEM FW_55S FW_55S CLK_MED_55S CLK_MED_55S CLK_MED_55S CLK_MED_55S FW_55S FW_55S FW_55S FW_55S FW_55S FW FW CLK_MED CLK_MED CLK_MED CLK_MED FW FW FW FW FW FW_LINK FW_CTL CLKFW_LINK_LCLK CLKFW_PHY_LCLK CLKFW_LINK_PCLK CLKFW_PHY_PCLK FW_LKON FW_LKON_R FW_LPS FW_LREQ FW_PINT FWPHY_CLK98P304M_XI CLK_MED_55S CLK_MED_55S CLK_MED CLK_MED CLK98P304M_FW_XI_R CLK98P304M_FW_XI FW_0_TPA FW_0_TPA FW_0_TPB FW_0_TPB FW_1_TPA FW_1_TPA FW_1_TPB FW_1_TPB FW_110D FW_110D FW_110D FW_110D FW_110D FW_110D FW_110D FW_110D FW_TP FW_TP FW_TP FW_TP FW_TP FW_TP FW_TP FW_TP FW_PORT0_TPA_P FW_PORT0_TPA_N FW_PORT0_TPB_P FW_PORT0_TPB_N FW_PORT1_TPA_P FW_PORT1_TPA_N FW_PORT1_TPB_P FW_PORT1_TPB_N FW_D_CTL FW_D_CTL FW_LCLK TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_HEAD LINE-TO-LINE SPACING WEIGHT FW_PCLK TABLE_SPACING_RULE_ITEM FW * =2:1_SPACING ? FW_LKON TABLE_SPACING_RULE_ITEM FW_TP * =3:1_SPACING ? D FW_LPS FW_LREQ FW_PINT 38 39 38 39 D 38 39 38 39 38 39 39 41 39 41 39 41 39 41 39 41 39 41 39 41 39 41 Port Not Used C C B B FireWire Constraints SYNC_MASTER=T9_NOME A SYNC_DATE=01/17/2007 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE APPLE COMPUTER INC DRAWING NUMBER D SCALE SHT NONE REV 051-7225 14.0.0 OF 85 88 A TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP GDDR3 FB A/B Net Properties DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM GDDR3_40R50SE * =50_OHM_SE =40_OHM_SE =50_OHM_SE 12.7 MM =STANDARD =STANDARD GDDR3_50SE * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD TABLE_PHYSICAL_RULE_ITEM ELECTRICAL_CONSTRAINT_SET GDDR3_80D * =80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF ELECTRICAL_CONSTRAINT_SET GDDR3_CLK GDDR3_CLK GDDR3_CLK GDDR3_CLK FB_A_CLK_P FB_A_CLK_N FB_A_CLK_P FB_A_CLK_N FB_AB_CMD FB_AB_CMD FB_AB_CMD FB_AB_CMD FB_AB_CMD FB_AB_CMD FB_AB_CMD_PD FB_AB_CMD FB_AB_CMD_PD GDDR3_40R50SE GDDR3_40R50SE GDDR3_40R50SE GDDR3_40R50SE GDDR3_40R50SE GDDR3_40R50SE GDDR3_40R50SE GDDR3_40R50SE GDDR3_40R50SE GDDR3_CMD GDDR3_CMD GDDR3_CMD GDDR3_CMD GDDR3_CMD GDDR3_CMD GDDR3_CMD GDDR3_CMD GDDR3_CMD FB_A_MA FB_A_MA FB_A_BA FB_A_RAS_L FB_A_CAS_L FB_A_WE_L FB_A_CKE FB_A_CS0_L FB_A_DRAM_RST FB_A_CMD FB_B_CMD GDDR3_50SE GDDR3_50SE GDDR3_CMD GDDR3_CMD FB_A_LMA FB_A_UMA FB_A_WDQS0 FB_A_WDQS1 FB_A_WDQS2 FB_A_WDQS3 GDDR3_50SE GDDR3_50SE GDDR3_50SE GDDR3_50SE GDDR3_DQS GDDR3_DQS GDDR3_DQS GDDR3_DQS FB_A_WDQS FB_A_WDQS FB_A_WDQS FB_A_WDQS FB_A_RDQS0 FB_A_RDQS1 FB_A_RDQS2 FB_A_RDQS3 GDDR3_50SE GDDR3_50SE GDDR3_50SE GDDR3_50SE GDDR3_DQS GDDR3_DQS GDDR3_DQS GDDR3_DQS FB_A_RDQS FB_A_RDQS FB_A_RDQS FB_A_RDQS FB_A_DQ_BYTE0 FB_A_DQ_BYTE1 FB_A_DQ_BYTE2 FB_A_DQ_BYTE3 GDDR3_50SE GDDR3_50SE GDDR3_50SE GDDR3_50SE GDDR3_DATA GDDR3_DATA GDDR3_DATA GDDR3_DATA FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQM0 FB_A_DQM1 FB_A_DQM2 FB_A_DQM3 GDDR3_50SE GDDR3_50SE GDDR3_50SE GDDR3_50SE GDDR3_DATA GDDR3_DATA GDDR3_DATA GDDR3_DATA FB_A_DQM_L FB_A_DQM_L FB_A_DQM_L FB_A_DQM_L FB_B_WDQS0 FB_B_WDQS1 FB_B_WDQS2 FB_B_WDQS3 GDDR3_50SE GDDR3_50SE GDDR3_50SE GDDR3_50SE GDDR3_DQS GDDR3_DQS GDDR3_DQS GDDR3_DQS FB_A_WDQS FB_A_WDQS FB_A_WDQS FB_A_WDQS FB_B_RDQS0 FB_B_RDQS1 FB_B_RDQS2 FB_B_RDQS3 GDDR3_50SE GDDR3_50SE GDDR3_50SE GDDR3_50SE GDDR3_DQS GDDR3_DQS GDDR3_DQS GDDR3_DQS FB_A_RDQS FB_A_RDQS FB_A_RDQS FB_A_RDQS FB_B_DQ_BYTE0 FB_B_DQ_BYTE1 FB_B_DQ_BYTE2 FB_B_DQ_BYTE3 GDDR3_50SE GDDR3_50SE GDDR3_50SE GDDR3_50SE GDDR3_DATA GDDR3_DATA GDDR3_DATA GDDR3_DATA FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_B_DQM0 FB_B_DQM1 FB_B_DQM2 FB_B_DQM3 GDDR3_50SE GDDR3_50SE GDDR3_50SE GDDR3_50SE GDDR3_DATA GDDR3_DATA GDDR3_DATA GDDR3_DATA FB_A_DQM_L FB_A_DQM_L FB_A_DQM_L FB_A_DQM_L FB_B_CLK_P GDDR3 FB C/D Net Properties NET_TYPE PHYSICAL SPACING GDDR3_80D GDDR3_80D GDDR3_80D GDDR3_80D FB_A_CLK_P TABLE_PHYSICAL_RULE_ITEM GDDR3 Frame Buffer Signal Constraints GDDR3_80D GDDR3_80D GDDR3_80D GDDR3_80D GDDR3_CLK GDDR3_CLK GDDR3_CLK GDDR3_CLK FB_B_CLK_P FB_B_CLK_N FB_B_CLK_P FB_B_CLK_N FB_CD_CMD FB_CD_CMD FB_CD_CMD FB_CD_CMD FB_CD_CMD FB_CD_CMD FB_CD_CMD_PD FB_CD_CMD FB_CD_CMD_PD GDDR3_40R50SE GDDR3_40R50SE GDDR3_40R50SE GDDR3_40R50SE GDDR3_40R50SE GDDR3_40R50SE GDDR3_40R50SE GDDR3_40R50SE GDDR3_40R50SE GDDR3_CMD GDDR3_CMD GDDR3_CMD GDDR3_CMD GDDR3_CMD GDDR3_CMD GDDR3_CMD GDDR3_CMD GDDR3_CMD FB_B_MA FB_B_MA FB_B_BA FB_B_RAS_L FB_B_CAS_L FB_B_WE_L FB_B_CKE FB_B_CS0_L FB_B_DRAM_RST FB_C_CMD FB_D_CMD GDDR3_50SE GDDR3_50SE GDDR3_CMD GDDR3_CMD FB_B_LMA FB_B_UMA FB_C_WDQS0 FB_C_WDQS1 FB_C_WDQS2 FB_C_WDQS3 GDDR3_50SE GDDR3_50SE GDDR3_50SE GDDR3_50SE GDDR3_DQS GDDR3_DQS GDDR3_DQS GDDR3_DQS FB_B_WDQS FB_B_WDQS FB_B_WDQS FB_B_WDQS FB_C_RDQS0 FB_C_RDQS1 FB_C_RDQS2 FB_C_RDQS3 GDDR3_50SE GDDR3_50SE GDDR3_50SE GDDR3_50SE GDDR3_DQS GDDR3_DQS GDDR3_DQS GDDR3_DQS FB_B_RDQS FB_B_RDQS FB_B_RDQS FB_B_RDQS FB_C_DQ_BYTE0 FB_C_DQ_BYTE1 FB_C_DQ_BYTE2 FB_C_DQ_BYTE3 GDDR3_50SE GDDR3_50SE GDDR3_50SE GDDR3_50SE GDDR3_DATA GDDR3_DATA GDDR3_DATA GDDR3_DATA FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_C_DQM0 FB_C_DQM1 FB_C_DQM2 FB_C_DQM3 GDDR3_50SE GDDR3_50SE GDDR3_50SE GDDR3_50SE GDDR3_DATA GDDR3_DATA GDDR3_DATA GDDR3_DATA FB_B_DQM_L FB_B_DQM_L FB_B_DQM_L FB_B_DQM_L FB_D_WDQS0 FB_D_WDQS1 FB_D_WDQS2 FB_D_WDQS3 GDDR3_50SE GDDR3_50SE GDDR3_50SE GDDR3_50SE GDDR3_DQS GDDR3_DQS GDDR3_DQS GDDR3_DQS FB_B_WDQS FB_B_WDQS FB_B_WDQS FB_B_WDQS FB_D_RDQS0 FB_D_RDQS1 FB_D_RDQS2 FB_D_RDQS3 GDDR3_50SE GDDR3_50SE GDDR3_50SE GDDR3_50SE GDDR3_DQS GDDR3_DQS GDDR3_DQS GDDR3_DQS FB_B_RDQS FB_B_RDQS FB_B_RDQS FB_B_RDQS FB_D_DQ_BYTE0 FB_D_DQ_BYTE1 FB_D_DQ_BYTE2 FB_D_DQ_BYTE3 GDDR3_50SE GDDR3_50SE GDDR3_50SE GDDR3_50SE GDDR3_DATA GDDR3_DATA GDDR3_DATA GDDR3_DATA FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_D_DQM0 FB_D_DQM1 FB_D_DQM2 FB_D_DQM3 GDDR3_50SE GDDR3_50SE GDDR3_50SE GDDR3_50SE GDDR3_DATA GDDR3_DATA GDDR3_DATA GDDR3_DATA FB_B_DQM_L FB_B_DQM_L FB_B_DQM_L FB_B_DQM_L FB_C_CLK_P 68 69 68 69 FB_D_CLK_P 68 69 NET_TYPE PHYSICAL SPACING 68 69 68 70 68 70 68 70 68 70 TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT =2.5:1_SPACING ? TABLE_SPACING_RULE_ITEM GDDR3_CLK * TABLE_SPACING_RULE_ITEM D GDDR3_CMD * =2.5:1_SPACING ? TABLE_SPACING_RULE_ITEM GDDR3_DATA * =2.5:1_SPACING ? TABLE_SPACING_RULE_ITEM GDDR3_DQS * =2.5:1_SPACING ? Video Signal Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 68 69 68 69 68 69 68 69 68 69 68 69 68 69 68 69 68 69 68 69 68 69 68 70 68 70 68 70 D 68 70 68 70 68 70 68 70 68 70 68 70 68 70 68 70 TABLE_PHYSICAL_RULE_ITEM TMDS_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF TABLE_PHYSICAL_RULE_ITEM VGA_50S * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD TABLE_PHYSICAL_RULE_ITEM VGA_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM TMDS * 20 MIL ? TABLE_SPACING_RULE_ITEM VGA * 20 MIL ? VGA_SYNC * 20 MIL ? TABLE_SPACING_RULE_ITEM C =STANDARD 68 69 68 69 68 69 68 69 68 69 68 69 68 69 68 69 68 69 68 69 68 69 68 69 68 69 68 69 68 69 68 69 68 69 68 69 68 69 68 69 68 69 68 69 68 69 68 69 68 69 68 69 68 69 68 69 68 69 68 69 68 69 68 69 68 70 68 70 68 70 68 70 68 70 68 70 68 70 68 70 68 70 68 70 68 70 68 70 68 70 68 70 68 70 68 70 C 68 70 68 70 68 70 68 70 68 70 68 70 68 70 68 70 68 70 68 70 68 70 68 70 68 70 68 70 68 70 68 70 G84M Net Properties ELECTRICAL_CONSTRAINT_SET B A NET_TYPE PHYSICAL SPACING (CK505_DOT96) CLK_SLOW_55S CLK_SLOW_55S CLK_SLOW CLK_SLOW GPU_CLK27M GPU_CLK27M_GATED CK505_CLK27MSS CLK_SLOW_55S CLK_SLOW_55S CLK_SLOW CLK_SLOW GPU_CLK27M_SS GPU_CLK27M_SS_GATED LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS_L_CLK_P LVDS_L_CLK_N LVDS_L_DATA_P LVDS_L_DATA_N LVDS_U_CLK_P LVDS_U_CLK_N LVDS_U_DATA_P LVDS_U_DATA_N TMDS_CLK TMDS_CLK TMDS_DATA TMDS_DATA TMDS_100D TMDS_100D TMDS_100D TMDS_100D TMDS TMDS TMDS TMDS TMDS_CLK_P TMDS_CLK_N TMDS_DATA_P TMDS_DATA_N VGA_R_TV_C VGA_G_TV_Y VGA_B_TV_COMP VGA_50S VGA_50S VGA_50S VGA VGA VGA GPU_TV_C_VGA_R GPU_TV_Y_VGA_G GPU_TV_COMP_VGA_B VGA_50S VGA_50S VGA_50S VGA VGA VGA GPU_VGA_R GPU_VGA_G GPU_VGA_B VGA_50S VGA_50S VGA_50S VGA VGA VGA GPU_TV_C GPU_TV_Y GPU_TV_COMP VGA_55S VGA_55S VGA_SYNC VGA_SYNC GPU_VGA_HSYNC GPU_VGA_VSYNC VGA_SYNC VGA_SYNC 30 30 71 72 30 B 30 71 72 73 77 73 77 73 77 73 77 73 77 73 77 73 77 73 77 73 76 73 76 73 76 73 76 72 76 72 76 72 76 72 73 72 73 72 73 72 73 72 73 GPU (G84M) Constraints 72 73 SYNC_MASTER=(MASTER) 73 76 73 76 SYNC_DATE=(MASTER) NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE APPLE COMPUTER INC DRAWING NUMBER D SCALE SHT NONE REV 051-7225 14.0.0 OF 86 88 A ALLOW ROUTE ON LAYER? LAYER MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP ELECTRICAL_CONSTRAINT_SET TABLE_PHYSICAL_RULE_ITEM SENSE_1TO1_55S * =1:1_DIFFPAIR =55_OHM_SE =55_OHM_SE =55_OHM_SE =1:1_DIFFPAIR =1:1_DIFFPAIR THERM_1TO1_55S * =1:1_DIFFPAIR =55_OHM_SE =55_OHM_SE =55_OHM_SE =1:1_DIFFPAIR =1:1_DIFFPAIR SPACING_RULE_SET LAYER TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_HEAD LINE-TO-LINE SPACING WEIGHT =2:1_SPACING ? M75 Specific Net Properties TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET NET_TYPE PHYSICAL SPACING (PCIE_EXCARD) (PCIE_EXCARD) PCIE_100D PCIE_100D PCIE PCIE PCIE_EXCARD_R2D_P PCIE_EXCARD_R2D_N (PCIE_MINI) (PCIE_MINI) PCIE_100D PCIE_100D PCIE PCIE PCIE_MINI_R2D_P PCIE_MINI_R2D_N ENET_100D ENET_100D ENET_100D ENET_100D ENET_MDI ENET_MDI ENETCONN ENETCONN ENET_MDI_R_P ENET_MDI_R_N ENETCONN_P ENETCONN_N FW_110D FW_110D FW_110D FW_110D FW_TP FW_TP FW_TP FW_TP FW_PORT0_TPA_FL_P FW_PORT0_TPA_FL_N FW_PORT0_TPB_FL_P FW_PORT0_TPB_FL_N (SATA_A_R2D) (SATA_A_R2D) SATA_100D SATA_100D SATA SATA SATA_A_R2D_UF_P SATA_A_R2D_UF_N (SATA_A_D2R) (SATA_A_D2R) SATA_100D SATA_100D SATA SATA SATA_A_D2R_UF_P SATA_A_D2R_UF_N (USB_EXTA) (USB_EXTA) (USB_EXTA) (USB_EXTA) (USB_EXTD) (USB_EXTD) (USB_CAMERA) (USB_CAMERA) USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB USB USB USB USB USB USB USB USB2_EXTA_MUXED_P USB2_EXTA_MUXED_N USB2_RT_P USB2_RT_N USB_WWAN_F_P USB_WWAN_F_N USB_CAMERA_F_P USB_CAMERA_F_N SENSE_DIFFPAIR SENSE_DIFFPAIR SENSE_DIFFPAIR SENSE_DIFFPAIR SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE SENSE SENSE SENSE GFXIMVP6_VSEN_P NBCOREISNS_P P1V8ISNS_P P1V25ISNS_P THERM_DIFFPAIR THERM_DIFFPAIR THERM_DIFFPAIR THERM_DIFFPAIR THERM_DIFFPAIR THERM_DIFFPAIR THERM_DIFFPAIR THERM_1TO1_55S THERM_1TO1_55S THERM_1TO1_55S THERM_1TO1_55S THERM_1TO1_55S THERM_1TO1_55S THERM_1TO1_55S THERM THERM THERM THERM THERM THERM THERM CPUTHMSNS_D2_P CPU_THERMD_P GPUTHMSNS_D_P GPU_TDIODE_P HSTHMSNS_D_P REMTHMSNS_DX_P RSFSTHMSNS_D_P LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS_L_CLK_CONN_F_P LVDS_L_CLK_CONN_F_N LVDS_L_CLK_CONN_P LVDS_L_CLK_CONN_N LVDS_L_DATA_CONN_P LVDS_L_DATA_CONN_N LVDS_U_CLK_CONN_P LVDS_U_CLK_CONN_N LVDS_U_DATA_CONN_P LVDS_U_DATA_CONN_N TMDS_100D TMDS_100D TMDS_100D TMDS_100D TMDS_100D TMDS_100D TMDS TMDS TMDS TMDS TMDS TMDS TMDS_CLK_R_P TMDS_CLK_R_N TMDS_CLK_F_P TMDS_CLK_F_N TMDS_DATA_F_P TMDS_DATA_F_N (VGA_R_TV_Y) (VGA_G_TV_C) (VGA_B_TV_COMP) VGA_50S VGA_50S VGA_50S VGA VGA VGA VGA_R VGA_G VGA_B (VGA_SYNC) (VGA_SYNC) (VGA_SYNC) (VGA_SYNC) VGA_55S VGA_55S VGA_55S VGA_55S VGA_SYNC VGA_SYNC VGA_SYNC VGA_SYNC VGA_HSYNC_R VGA_VSYNC_R VGA_HSYNC VGA_VSYNC PP1V8_MEM PP1V8_MEM GND PP1V8_S3 PP1V8_S3 GND SB_POWER SB_POWER SB_POWER PP3V3_S5 PP3V3_S0 PP1V5_S0 WWAN_SIM WWAN_SIM WWAN_SIM_CLOCK WWAN_SIM_DATA 34 34 34 34 TABLE_SPACING_RULE_ITEM SENSE * TABLE_SPACING_RULE_ITEM THERM D =2:1_SPACING ? LINE-TO-LINE SPACING WEIGHT 25 MILS ? * TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER TABLE_SPACING_RULE_ITEM ENETCONN * TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT 37 D 37 41 41 41 41 TABLE_SPACING_RULE_ITEM GND * =STANDARD ? PP1V8_MEM * =STANDARD ? TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM GND_P2MM * 0.20 MM 1000 PWR_P2MM * 0.20 MM 1000 TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET MEM_CLK GND * GND_P2MM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CMD GND * GND_P2MM MEM_CTRL GND * GND_P2MM MEM_DATA GND * GND_P2MM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_DQS GND * GND_P2MM MEM_CLK PP1V8_MEM * PWR_P2MM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM C MEM_CMD PP1V8_MEM * PWR_P2MM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CTRL PP1V8_MEM PWR_P2MM * TABLE_SPACING_ASSIGNMENT_ITEM MEM_DATA PP1V8_MEM * PWR_P2MM MEM_DQS PP1V8_MEM * PWR_P2MM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET CLINK_VREF GND * GND_P2MM TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET CLK_FSB GND * GND_P2MM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM CLK_MED GND * GND_P2MM CLK_PCIE GND * GND_P2MM TABLE_SPACING_ASSIGNMENT_ITEM CPU_COMP GND * GND_P2MM CPU_GTLREF GND * GND_P2MM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM DMI GND * GND_P2MM PCIE GND * GND_P2MM TABLE_SPACING_ASSIGNMENT_ITEM CPU_VCCSENSE GND * GND_P2MM FSB_DSTB GND * GND_P2MM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM 78 78 78 78 43 43 43 43 44 44 44 44 59 50 50 50 51 10 51 C 51 51 71 72 51 51 75 75 75 77 75 77 75 77 75 77 75 77 75 77 75 77 75 77 TABLE_SPACING_ASSIGNMENT_ITEM SATA GND * GND_P2MM USB GND * GND_P2MM TABLE_SPACING_ASSIGNMENT_HEAD TABLE_SPACING_ASSIGNMENT_ITEM NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET ENET_MDI GND * GND_P2MM ENET_MDI ENET_POWER * PWR_P2MM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM CLK_PCIE SB_POWER * PWR_P2MM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM DMI SB_POWER * PWR_P2MM SATA SB_POWER * PWR_P2MM 76 76 76 76 76 76 TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET CLK_MED FW_POWER * GND_P2MM TABLE_SPACING_ASSIGNMENT_ITEM USB SB_POWER * PWR_P2MM TABLE_SPACING_ASSIGNMENT_ITEM 76 76 76 TABLE_SPACING_ASSIGNMENT_HEAD B NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET LVDS GND * GND_P2MM TABLE_SPACING_ASSIGNMENT_ITEM Memory Constraint Relaxations Allow 0.127 mm necks for >0.127 mm lines for GMCH fanout TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 76 B 76 76 76 31 32 38 50 57 62 87 31 32 38 50 57 62 87 TABLE_PHYSICAL_RULE_ITEM MEM_70D BOTTOM 0.127 MM 6.35 MM Allow 0.1 mm necks for >0.1 mm lines between thru-hole SO-DIMM pins 24 25 26 27 28 46 48 55 57 60 65 75 52 57 58 59 65 74 75 77 13 16 19 21 23 24 25 26 27 28 29 30 31 32 42 46 47 48 50 51 11 12 22 26 27 34 63 TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER MEM_45S * OVERRIDE OVERRIDE ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH 0.100 MM 2.54 MM OVERRIDE OVERRIDE DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP OVERRIDE OVERRIDE TABLE_PHYSICAL_RULE_ITEM OVERRIDE OVERRIDE MEM_70D ISL10 0.100 MM WWAN_SIM WWAN_SIM I119 I118 TABLE_PHYSICAL_RULE_ITEM 44 44 2.54 MM TABLE_PHYSICAL_RULE_ITEM MEM_85D ISL4,ISL10 0.100 MM 2.54 MM Graphics Constraint Relaxations Alternate diffpair width/gap through BGA fanout areas (95-ohm diff) M75 Specific Constraints TABLE_PHYSICAL_ASSIGNMENT_HEAD NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET LVDS_100D BGA 100_DIFF_BGA TMDS_100D BGA 100_DIFF_BGA TABLE_PHYSICAL_ASSIGNMENT_ITEM A SYNC_MASTER=(MASTER) SYNC_DATE=(MASTER) TABLE_PHYSICAL_ASSIGNMENT_ITEM NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING SIM Card Constraints I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH =50_OHM_SE =50_OHM_SE MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART TABLE_PHYSICAL_RULE_ITEM WWAN_SIM * SPACING_RULE_SET LAYER =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE SIZE DRAWING NUMBER REV TABLE_SPACING_RULE_HEAD LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM WWAN_SIM * =2:1_SPACING APPLE COMPUTER INC ? D 051-7225 SCALE SHT NONE 14.0.0 OF 87 88 A M75 Board-Specific Spacing & Physical Constraints TABLE_BOARD_INFO BOARD LAYERS BOARD AREAS BOARD UNITS (MIL or MM) ALLEGRO VERSION TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM NO_TYPE,BGA MM 15.5.1 TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_PHYSICAL_RULE_ITEM DEFAULT * Y =55_OHM_SE =55_OHM_SE 30 MM MM MM DEFAULT * * Y =DEFAULT =DEFAULT 12.7 MM =DEFAULT =DEFAULT NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET * * BGA BGA_P1MM MEM_CLK * BGA BGA_P2MM CLK_FSB * BGA BGA_P2MM CLK_PCIE * BGA BGA_P2MM CLK_MED * BGA BGA_P2MM CLK_SLOW * BGA BGA_P2MM FSB_DSTB FSB_DSTB BGA BGA_P3MM TABLE_SPACING_ASSIGNMENT_ITEM ? 0.1 MM TABLE_PHYSICAL_RULE_ITEM STANDARD TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM STANDARD * =DEFAULT ? BGA_P1MM * =DEFAULT ? TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_PHYSICAL_RULE_HEAD D PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH 55_OHM_SE TOP,BOTTOM Y 0.100 MM 0.100 MM MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_SPACING_RULE_ITEM BGA_P2MM * D TABLE_SPACING_ASSIGNMENT_ITEM ? =DEFAULT TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_ITEM * BGA_P3MM =DEFAULT ? LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_ASSIGNMENT_ITEM TABLE_PHYSICAL_RULE_ITEM 55_OHM_SE ISL2,ISL11 Y 0.250 MM 0.076 MM 55_OHM_SE * Y 0.076 MM 0.076 MM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_PHYSICAL_RULE_ITEM =STANDARD =STANDARD =STANDARD TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_RULE_ITEM 1.5:1_SPACING * 0.15 MM ? 1.8:1_SPACING * 0.18 MM ? 2:1_SPACING * 0.2 MM ? 2.5:1_SPACING * 0.25 MM ? 3:1_SPACING * 0.3 MM ? 4:1_SPACING * 0.4 MM ? TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH 50_OHM_SE TOP,BOTTOM Y 0.125 MM 0.125 MM 50_OHM_SE * Y 0.090 MM 0.090 MM MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM =STANDARD =STANDARD =STANDARD TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM 45_OHM_SE TOP,BOTTOM Y 0.150 MM 0.150 MM 45_OHM_SE * Y 0.105 MM 0.105 MM =STANDARD =STANDARD =STANDARD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 40_OHM_SE TOP,BOTTOM Y 0.185 MM 0.185 MM 40_OHM_SE * Y 0.131 MM 0.131 MM =STANDARD =STANDARD =STANDARD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 27P4_OHM_SE TOP,BOTTOM Y 0.335 MM 0.335 MM 27P4_OHM_SE * Y 0.240 MM 0.240 MM =STANDARD =STANDARD =STANDARD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM C C TABLE_PHYSICAL_RULE_HEAD TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 1:1_DIFFPAIR * Y =STANDARD =STANDARD =STANDARD 0.1 MM 0.1 MM TABLE_PHYSICAL_RULE_ITEM 70_OHM_DIFF * N =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM 70_OHM_DIFF ISL3,ISL4 Y 0.149 MM 0.149 MM 0.125 MM 0.125 MM 70_OHM_DIFF ISL9,ISL10 Y 0.149 MM 0.149 MM 0.125 MM 0.125 MM 70_OHM_DIFF ISL2,ISL11 Y 0.185 MM 0.185 MM 0.125 MM 0.125 MM 70_OHM_DIFF TOP,BOTTOM Y 0.185 MM 0.185 MM 0.125 MM 0.125 MM PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 80_OHM_DIFF * N =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD 80_OHM_DIFF ISL3,ISL4 Y 0.115 MM 0.115 MM 0.125 MM 0.125 MM 80_OHM_DIFF ISL9,ISL10 Y 0.115 MM 0.115 MM 0.125 MM 0.125 MM 80_OHM_DIFF ISL2,ISL11 Y 0.140 MM 0.140 MM 0.125 MM 0.125 MM 80_OHM_DIFF TOP,BOTTOM Y 0.140 MM 0.140 MM 0.125 MM 0.125 MM PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 85_OHM_DIFF * N =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD 85_OHM_DIFF ISL3,ISL4 Y 0.101 MM 0.101 MM 0.125 MM 0.125 MM 85_OHM_DIFF ISL9,ISL10 Y 0.101 MM 0.101 MM 0.125 MM 0.125 MM 85_OHM_DIFF ISL2,ISL11 Y 0.125 MM 0.125 MM 0.125 MM 0.125 MM 85_OHM_DIFF TOP,BOTTOM Y 0.125 MM 0.125 MM 0.125 MM 0.125 MM PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 90_OHM_DIFF * N =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD 90_OHM_DIFF ISL3,ISL4 Y 0.102 MM 0.102 MM 0.220 MM 0.220 MM 90_OHM_DIFF ISL9,ISL10 Y 0.102 MM 0.102 MM 0.220 MM 0.220 MM 90_OHM_DIFF ISL2,ISL11 Y 0.130 MM 0.130 MM 0.220 MM 0.220 MM 90_OHM_DIFF TOP,BOTTOM Y 0.130 MM 0.130 MM 0.220 MM 0.220 MM PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD TABLE_PHYSICAL_RULE_ITEM B B TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD MAXIMUM NECK LENGTH TABLE_PHYSICAL_RULE_HEAD LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 100_DIFF_BGA * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF 100_DIFF_BGA ISL3,ISL4 Y 0.075 MM 0.075 MM 0.125 MM 0.125 MM 100_DIFF_BGA ISL9,ISL10 Y 0.075 MM 0.075 MM 0.125 MM 0.125 MM PHYSICAL_RULE_SET TABLE_PHYSICAL_RULE_ITEM 100_OHM_DIFF * N =STANDARD =STANDARD 100_OHM_DIFF ISL3,ISL4 Y 0.080 MM 0.080 MM =STANDARD =STANDARD =STANDARD 0.200 MM 0.200 MM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM 100_OHM_DIFF ISL9,ISL10 Y 0.080 MM 0.200 MM 0.080 MM 0.200 MM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM 100_OHM_DIFF ISL2,ISL11 Y 0.099 MM 0.099 MM 0.200 MM 0.200 MM 100_OHM_DIFF TOP,BOTTOM Y 0.099 MM 0.099 MM 0.200 MM 0.200 MM LAYER ALLOW ROUTE ON LAYER? M75 Rule Definitions NOTE: 100_DIFF_BGA is 100-ohms differential impedance on outer layers and 95-ohms on inner layers TABLE_PHYSICAL_RULE_ITEM A SYNC_MASTER=(MASTER) PHYSICAL_RULE_SET MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING TABLE_PHYSICAL_RULE_ITEM 110_OHM_DIFF * N =STANDARD =STANDARD =STANDARD =STANDARD 110_OHM_DIFF ISL3,ISL4 Y 0.077 MM 0.077 MM 0.330 MM 0.330 MM 110_OHM_DIFF ISL9,ISL10 Y 0.077 MM 0.077 MM 0.330 MM 0.330 MM =STANDARD SYNC_DATE=(MASTER) NOTICE OF PROPRIETARY PROPERTY TABLE_PHYSICAL_RULE_HEAD TABLE_PHYSICAL_RULE_ITEM I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT TABLE_PHYSICAL_RULE_ITEM III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART TABLE_PHYSICAL_RULE_ITEM 110_OHM_DIFF ISL2,ISL11 Y 0.089 MM 0.089 MM 0.330 MM 0.330 MM 110_OHM_DIFF TOP,BOTTOM Y 0.089 MM 0.089 MM 0.330 MM 0.330 MM SIZE DRAWING NUMBER REV TABLE_PHYSICAL_RULE_ITEM APPLE COMPUTER INC D 051-7225 SCALE SHT NONE 14.0.0 OF 88 88 A ... 63 SYNC_MASTER=(T9_MLB) SYNC_DATE=08/23/2006 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING... Configuration SYNC_MASTER=N/A A SYNC_DATE=N/A NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING... cap in spec (rdar://5000272) SYNC_DATE=N/A NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING