Apple macbook pro a1278 820 3115 b (MLB j30) 051 9058

8 ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5% ALL CAPACITANCE VALUES ARE IN MICROFARADS ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ REV ECN DESCRIPTION OF REVISION 0001395489 CK APPD DATE SCHEM,MLB,J30 ENGINEERING RELEASED 2012-03-13 03/12/12 D (.csa) Date Page TABLE_TABLEOFCONTENTS_HEAD TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM C TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM B TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 Contents Sync Table of Contents (.csa) 02/15/2011 TABLE_TABLEOFCONTENTS_HEAD 02/15/2011 TABLE_TABLEOFCONTENTS_ITEM 03/26/2009 TABLE_TABLEOFCONTENTS_ITEM 02/15/2011 TABLE_TABLEOFCONTENTS_ITEM 02/15/2011 TABLE_TABLEOFCONTENTS_ITEM 02/15/2011 TABLE_TABLEOFCONTENTS_ITEM 02/15/2011 TABLE_TABLEOFCONTENTS_ITEM 02/15/2011 TABLE_TABLEOFCONTENTS_ITEM 02/15/2011 TABLE_TABLEOFCONTENTS_ITEM 02/15/2011 TABLE_TABLEOFCONTENTS_ITEM 02/15/2011 TABLE_TABLEOFCONTENTS_ITEM K90I_MLB System Block Diagram MASTER Revision History K20A_MLB Revision History K90I_MLB BOM Configuration K90I_MLB FUNC TEST K90I_MLB Power Aliases K90I_MLB Signal Aliases K90I_MLB 10 CPU DMI/PEG/FDI/RSVD MASTER 11 CPU CLOCK/MISC/JTAG MASTER CPU DDR3 INTERFACES MASTER 12 13 CPU POWER 02/15/2011 TABLE_TABLEOFCONTENTS_ITEM 02/15/2011 TABLE_TABLEOFCONTENTS_ITEM 09/27/2011 TABLE_TABLEOFCONTENTS_ITEM 02/15/2011 TABLE_TABLEOFCONTENTS_ITEM 06/13/2011 TABLE_TABLEOFCONTENTS_ITEM 06/13/2011 TABLE_TABLEOFCONTENTS_ITEM 06/13/2011 TABLE_TABLEOFCONTENTS_ITEM MASTER 14 CPU GROUNDS MASTER 16 CPU DECOUPLING-I JACK_J30 17 CPU DECOUPLING-II MASTER 18 PCH SATA/PCIe/CLK/LPC/SPI J31_MLB 19 PCH DMI/FDI/PM/Graphics J31_MLB PCH PCI/USB/TP/RSVD J31_MLB PCH GPIO/MISC/NCTF J31_MLB 20 21 22 PCH POWER 06/13/2011 TABLE_TABLEOFCONTENTS_ITEM 06/13/2011 TABLE_TABLEOFCONTENTS_ITEM 06/13/2011 TABLE_TABLEOFCONTENTS_ITEM 02/15/2011 TABLE_TABLEOFCONTENTS_ITEM 06/13/2011 TABLE_TABLEOFCONTENTS_ITEM 02/15/2011 TABLE_TABLEOFCONTENTS_ITEM 09/19/2011 TABLE_TABLEOFCONTENTS_ITEM J31_MLB 23 PCH GROUNDS J31_MLB 24 PCH DECOUPLING K90I_MLB 25 CPU & PCH XDP J31_MLB 26 Chipset Support K90I_MLB USB HUB & MUX LINDA_J30 27 28 CPU Memory S3 Support 02/15/2011 TABLE_TABLEOFCONTENTS_ITEM 02/15/2011 TABLE_TABLEOFCONTENTS_ITEM 11/03/2011 TABLE_TABLEOFCONTENTS_ITEM 06/13/2011 TABLE_TABLEOFCONTENTS_ITEM 02/15/2011 TABLE_TABLEOFCONTENTS_ITEM K90I_MLB 33 SD Card Connector TABLE_TABLEOFCONTENTS_ITEM K90I_MLB 31 DDR3 SO-DIMM Connector B 02/15/2011 K90I_MLB 30 DDR3 Byte/Bit Swaps TABLE_TABLEOFCONTENTS_ITEM K90I_MLB 29 DDR3 SO-DIMM Connector A 02/15/2011 YONAS_J30 34 DDR3/FRAMEBUF VREF MARGINING J31_MLB X19/ALS/CAMERA CONNECTOR K90I_MLB 35 36 T29 Host (1 of 2) 02/15/2011 TABLE_TABLEOFCONTENTS_ITEM 02/15/2011 TABLE_TABLEOFCONTENTS_ITEM 02/15/2011 TABLE_TABLEOFCONTENTS_ITEM 06/15/2011 TABLE_TABLEOFCONTENTS_ITEM 02/15/2011 TABLE_TABLEOFCONTENTS_ITEM K90I_MLB 37 T29 Host (2 of 2) K90I_MLB 38 T29 Power Support K90I_MLB 39 ETHERNET PHY (CAESAR IV) J31_MLB Ethernet Connector K90I_MLB 40 41 FireWire LLC/PHY (FW643E) 06/23/2011 TABLE_TABLEOFCONTENTS_ITEM 02/15/2011 TABLE_TABLEOFCONTENTS_ITEM 11/08/2011 TABLE_TABLEOFCONTENTS_ITEM 07/08/2011 TABLE_TABLEOFCONTENTS_ITEM K90I_MLB 43 FireWire Connector TABLE_TABLEOFCONTENTS_ITEM K90I_MLB 42 FireWire Port & PHY Power 02/15/2011 K90I_MLB 45 SATA/IR/SIL Connectors YONAS_J30 46 External A USB3 Connector 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 D Date Page Contents Sync 50 01/02/2012 SMC Support YONAS_J30 LPC+SPI Debug Connector J31_MLB SMBus Connections K90I_MLB Power Sensors: Load Side LINDA_J30 Power Sensors: High Side YONAS_J30 Thermal Sensors YONAS_J30 Fan K90I_MLB WELLSPRING J31_MLB WELLSPRING JACK_J30 Digital Accelerometer K90I_MLB SPI ROM K90I_MLB AUDIO: CODEC/REGULATOR KAVITHA_J30 AUDIO: DETECT/MIC BIAS DIRK_J30 AUDIO: HEADPHONE FILTER KAVITHA_J30 AUDI0: SPEAKER AMP KAVITHA_J30 AUDIO: JACK DIRK_J30 51 06/15/2011 52 02/15/2011 53 09/28/2011 54 11/03/2011 55 08/01/2011 56 02/15/2011 57 07/01/2011 58 09/28/2011 59 02/15/2011 61 02/15/2011 62 07/25/2011 64 02/16/2012 65 07/25/2011 66 07/25/2011 67 11/10/2011 68 C 02/20/2012 AUDIO:Jack Translators DIRK_J30 DC-In & Battery Connectors JACK_J30 PBus Supply & Battery Charger JACK_J30 System Agent Supply JACK_J30 5V/3.3V SUPPLY JACK_J30 1.5V DDR3 Supply JACK_J30 CPU IMVP7 & AXG VCore Regulator JACK_J30 69 07/29/2011 70 09/27/2011 71 09/28/2011 72 08/22/2011 73 07/28/2011 74 08/03/2011 75 07/28/2011 CPU IMVP7 & AXG VCore Output JACK_J30 CPUVCCIO (1.05V) Power Supply JACK_J30 Misc Power Supplies JACK_J30 Power FETs K90I_MLB Power Control 1/ENABLE K90I_MLB LVDS CONNECTOR K90I_MLB DisplayPort/T29 A MUXing K90I_MLB 76 09/28/2011 77 07/28/2011 78 02/15/2011 79 02/15/2011 90 02/15/2011 93 02/15/2011 94 02/15/2011 Thunderbolt Connector A K90I_MLB LCD Backlight Driver J31_MLB CPU Constraints K90I_MLB Memory Constraints K90I_MLB PCH Constraints K90I_MLB PCH Constraints K90I_MLB Ethernet/FW Constraints K90I_MLB T29 Constraints K90I_MLB SMC Constraints K90I_MLB Project Specific Constraints K90I_MLB PCB Rule Definitions K90I_MLB 97 07/08/2011 100 02/15/2011 101 02/15/2011 102 B 02/15/2011 103 02/15/2011 104 02/15/2011 105 02/15/2011 106 02/15/2011 108 02/15/2011 109 02/15/2011 J31_MLB 47 07/08/2011 External B USB3 Connector J31_MLB Front Flex Support K90I_MLB SMC YONAS_J30 48 02/15/2011 49 12/21/2011 TABLE_TABLEOFCONTENTS_ITEM A A DRAWING TITLE SCHEM,MLB,J30 DRAWING NUMBER Schematic / PCB #’s PART NUMBER QTY Apple Inc DESCRIPTION REFERENCE DES CRITICAL 051-9058 SCHEM,MLB,J30 SCH CRITICAL 820-3115 PCBF,MLB,J30 PCB CRITICAL BOM OPTION R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED DRAWING TITLE=MLB ABBREV=DRAWING LAST_MODIFIED=Tue Mar 13 14:00:17 2012 051-9058 REVISION 6.0.0 BRANCH PAGE OF 109 SHEET OF 86 SIZE D U1000 J2500 XDP CONN INTEL CPU PG 23 2.X GHz IVY BRIDGE 2C-35W J3100 PG 29 J2900 DIMMs DDR3-1333/1600MHZ PG 9-13 PG 27 DIMM J6900, J6950 D D POWER SUPPLY DC/BATT PG 63 GPIO FDI DMI RTC PG 19 PG 17 PG 17 PG 16 PG 63-73 U5511 TEMP SENSOR PG 51 U5920 Sudden Motion Sensor U2600 MISC CLK SYSTEM CLOCK PG 55 PG 19 U5400,U5410,U5340,U5360,U5370,Q5480,Q5490 BUFFER SPI SATA CONN HDD 1.05V/6GHZ PG 41 DP/TMDS U4900 Fan Ser Prt ADC SMC J5100 LPC+SPI Conn Port80,serial SPI PG 45 1.05V/1.5GHZ C PG 47 PG 16 U1800 PG 41 U5701 J3501 MUX LANEs PG 16-21 HDMI OUT CTRL CIO PG 33,34 DP DP OUT DVI OUT TMDS OUT USB PG 17 LVDS OUT PG 17 PCI J9000 J5800, J5713 TRACKPAD/ KEYBOARD TP/KB PSOC PG 32 PG 53 PG 54, 53 J3502 PG 17 RGB OUT T29 Host X19 Bluetooth PWR PCIe x4 PG 76 PG 18 PG 75 eDP OUT 10 11 12 13 U3600 CONN I2C SMS LPC PG 16 (UP TO 14 DEVICES) Display Port / T29 U9390 PG 52 INTEL PANTHER POINT-MPCH J9400 FAN CONN AND CONTROL SATA J4500 SATA CONN ODD J5601 PG 56 PG 16 J4501 PG 49, 50 SPI Boot ROM PG 16 C POWER SENSE U6100 PG 24 CAMERA U4800 PG 32 U2700 J4501 IR Controller IR PG 44 PG 41 USB HUB PG 25 J4700 U2760 EHCI XHCI USB MUX PG 25 EXTERNAL B USB PG 18 B PG 18 PG 16 PCI-E PG 74 PG 43 USB LVDS CONN J4600 EXTERNAL A USB SMBUS JTAG B PG 42 PG 16 PG 16 PCI-E PEG J2550 PG 16 PG 16 DIMM’s HDA (UP TO LINES) PG 16 From PCH PCH XDP CONN PG 23 U6201 AUDIO Codec PG 57 EXTMIC LINEIN HPOUT SPDIF MICIN U6610, U6620, U6630 U6400 U4100 E-NET FW643E A J3300 U3900 LINEOUT MIC BIAS BCM57765 SD Card CONN PG 36 PG 30 SPEAKER AMPs PG58 PG 60 PG 38 SYNC_MASTER=MASTER SYNC_DATE=02/15/2011 PAGE TITLE System Block Diagram DRAWING NUMBER J4310 J3501 Apple Inc J4000 X19 AirPort FW800 CONN E-NET CONN PG 32 PG 40 PG 37 J6700 J6701 NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED PG 61 R J6702 J6703 AUDIO CONNs 051-9058 REVISION 6.0.0 BRANCH PAGE OF 109 SHEET OF 86 SIZE D A D6990 J30 POWER SYSTEM ARCHITECTURE PPDCIN_G3H ENABLE 3.425V G3HOT PPDCIN_S5_P3V42G3H R6990 PP3V42_G3H_REG PM6640 U6990 R6905 SMC PWRGD SMC_RESET_L SN0903048 U5010 (PAGE 44) (PAGE 63) Q5300 D J6900 Q5310 F6905 6A FUSE AC V F7040 PPBUS_G3H V DCIN(16.5V) A U7000 CPUVCCIOS0_EN ISL95870 U7600 EN 21 (PAGE 70) ISL6259HRTZ SMC_DCIN_ISENSE PBUS SUPPLY/ BATTERY CHARGER SMC_CPU_FSB_ISENSE PGOOD 22-1 CPUVCCIOS0_PGOOD R7050 V A 24 VR_ON (9 TO 12.6V) R5330 SMC_GFX_VSENSE (PAGE 68) CPUIMVP_PGOOD PGOOD CPUIMVP_AXG_PGOOD PGOODG CHGR_BGATE VIN S5 C DDRVTT_EN 16 PPDDR_S3_REG 0.75V TPS51916 U7300 www.qdzbwx.com PP5V_S0_FET (PAGE 44) PM_SLP_S5_L COUGAR-POINT (PCH) R7917 CPU_VCCSA_VID SLP_SUS EN1 PG73 DELAY PG73 15 DELAY U1800 P3V3S3_EN PM_SLP_S4_L PG73 13-2 13 PG 17 SLP_S4#(H4) Q9706 F9700 VOUT2 15 SMC 25 PP5V_SW_ODD RSMRST_PWRGD ODD_PWR_EN_L 14-1 EN PP3V3_S0_VMON PP5V_S0_VMON PM_SLP_S3_L&&WOL_EN||SMC_ADAPTER_EN//WOL_EN ISL88042IRTEZ P17(BTN_OUT) VMON_Q3 PP1V05_S0_VMON U9701 PP3V3_S4_FET PPVOUT_SW_LCDBKLT VOUT Q7800 12 CPUIMVP_VR_ON PM_PWRBTN_L SLP_S5_L(P95) SMC_RESET_L PM_SLP_S4_L (PAGE 73) 26 PM_SYSRST_L PM_SLP_S5_L VMON_Q4 RES* 6-1 SLP_S4_L(P94) PM_SLP_S3_L (PAGE 76) R7978 IMVP_VR_ON(P16) U7960 VMON_Q2 PP1V5_S3RS0_VMON B PM_RSMRST_L 99ms DLY PWR_BUTTON(P90) SYSRST(PA2) R7803 10 12 RSMRST_IN(P13) SMC_ONOFF_L U3900 CAESAR IV (PAGE 36) 10-2 PM_DSW_PWRGD PWRGD(P12) RSMRST_OUT(P15) PP1V2_ENET_PHY BCM57765 PP3V3_ENET Q7922 P5V_3V3_SUS_EN EN RESET* ALL_SYS_PWRGD P5V3V3_PGOOD Q7840 PPBUS_SW_LCDBKLT_PWR (PAGE 9~13) PVCCSA_PGOOD Q4590 LCD_BKLT_EN VIN LP8550 UNCOREPWRGOOD P5VS0_EN TPS51125 U7200 (PAGE 66) PGOOD && BKLT_PLT_RST_L (PAGE 16~21) CPUVCCIOS0_PGOOD PP5V_S0_FET PP3V3_S5 PP5V_SUS_FET 14 PM_SLP_S3_L PG 17 SLP_S3#(F4) PP3V3_S5_REG U1000 P5V3V3_PGOOD Q7860 PP5V_S3_REG (R/H) PP5V_S5_LDO B DDRREG_EN VOUT1 EN2 13-1 CPU P1V8S0_PGOOD 3.3V P3V3S5_EN_L VREG5 RC 30 SM_DRAMPWROK CPUIMVP_AXG_PGOOD 23-1 (L/H) P5VS3_EN PVCCSA_PGOOD PGOOD 14 VIN 5V P5VS3_EN_L 13 PG73 RC (PAGE 65) 28 PM_MEM_PWRGD PPBUS_S5_HS_OTHER_ISNS A 11 10-1 P5V_3V3_SUS_EN VID1 R5410 PG 17 SLP_S5#(E4) CPU_PWRGD DRAMPWROK 23 VOUT VID0 C 29 PROCPWRGD (PAGE 16~21) ISL95870A U7100 R7916 11 PLT_RERST_L PLTRST# Q7801 PPVCCSA_S0_REG EN CPU_VCCSA_VID PG73 PM_DSW_PWRGD U2850 DDRREG_PGOOD PGOOD VCC PVCCSA_EN 22 P3V3S4_EN PM_RSMRST_L PP1V5_S3RS0_FET DELAY SMC_PM_G2_EN PM_SYSRST_L RSMRST# U1800 PP1V5S0FET_GATE SYS_RERST# PM_PCH_PWRGD (PAGE 67) P3V3S5_EN 27 PM_PWRBTN_L PPVTT_S0_DDR_LDO VOUT2 SMC COUGAR-POINT (PCH) PWRBTN# 26-1 VOUT1 S3 26 25-1 VLDOIN 1.5V DDRREG_EN FW_PWR_EN PPVCORE_S0_AXG_REG VOUT PPVBAT_G3H_CHGR_R RC PP1V0_FW_FWPHY EN V U7400 Q7055 U4202 CPU VCORE MAX15119GTM (PAGE 63) P60 TPS22924 (PAGE 39) CPUIMVP_VR_ON PPVBATT_G3H_CONN 25 PPVCORE_S0_CPU_REG VOUT SMC_BATT_ISENSE J6950 R5320 SMC_CPU_VSENSE VIN SMC_RESET_L U4900 D 22 VOUT IN 3S2P PPCPUVCCIO_S0_REG A 1.05VVOUT VCC PPVBAT_G3H VIN R7640 PP5V_S0_CPUVCCIOS0 A R7020 ADAPTER 15 R5400 SLP_S3_L(P93) P3V3S4_EN PG73 PP3V3_S3 Q4260 F4260 14 U4900 (PAGE 43) 16 PP3V3_S0 Q7810 PPBUS_FW_FET PM_SLP_S3_L_R P3V3S3_EN MAX15053EWL P1V8_S0_EN EN FWP5ORT_PWR_EN 1V05_S0_LDO_EN A RC CPUVCCIOS0_EN DELAY RC PVCCSA_EN 21 21 22 P1V5S0_EN 19 DELAY RC P1V8S0_EN DELAY 10-3 17 U7760 PP1V8_S0_REG 18 (PAGE 71) TPS720105 P1V05_S0_LDO_EN EN P5V_3V3_SUS_EN P5VS0_EN 14-1 U7740 T29_A_HV_EN PP1V05_SUS_LDO EN U7770 PP1V5_S0_REG SYNC_MASTER=K20A_MLB SYNC_DATE=03/26/2009 Revision History 20 DRAWING NUMBER (PAGE8 71) Apple Inc Q7830 U3890 PM_SLP_S3_L_R TPS22924 PP3V3_FW_P3V3FWFET 14 EN U4201 051-9058 REVISION R 6.0.0 PP3V3_FW_FE5T NOTICE OF PROPRIETARY PROPERTY: (PAGE 39) VOUT PP15V_T29_REG (PAGE 35) TPS62201 P1V5S0_EN 19 (PAGE 71) VIN LT3957 14-1 PP1V05_S0_LDO PAGE TITLE PBUSVSENS_EN 17 U7780 (PAGE 71) 14-1 TPS720105 P3V3S0_EN 19 Q7820 Q3880 DELAY RC PP3V3_SUS_FET THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED BRANCH PAGE OF 109 SHEET OF 86 SIZE D A PROTO: D D C C B B A SYNC_MASTER=K90I_MLB SYNC_DATE=02/15/2011 PAGE TITLE Revision History DRAWING NUMBER Apple Inc 051-9058 REVISION R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED 6.0.0 BRANCH PAGE OF 109 SHEET OF 86 SIZE D A BOM Variants Bar Code Labels / EEEE #’s TABLE_BOMGROUP_HEAD BOM NUMBER BOM NAME BOM OPTIONS 607-8895 CMN PTS,PCBA,MLB,J30 J30_COMMON,FET_PAIR 085-3092 J30 MLB DEVELOPMENT BOM J30_DEVEL:ENG 607-8721 POWER FETS PAIR,FAIRCHILD,DDR,J30 DDR_POWER_FET:FAIR 607-8722 POWER FETS PAIR,FAIRCHILD,5V_S3,J30 5V_S3_POWER_FET:FAIR 607-8723 POWER FETS PAIR,FAIRCHILD,PBUS_CHARGER,J30 CHARGER_POWER_FET:FAIR 607-9309 POWER FETS PAIR,RENESAS,DDR,J30 DDR_POWER_FET:REN PART NUMBER DESCRIPTION REFERENCE DES 826-4393 QTY LBL,P/N LABEL,PCB,28MM X MM [EEEE:F1YG] CRITICAL CRITICAL BOM OPTION EEEE_F1YG 826-4393 LBL,P/N LABEL,PCB,28MM X MM [EEEE:F1YH] CRITICAL EEEE_F1YH 826-4393 LBL,P/N LABEL,PCB,28MM X MM [EEEE:F1YJ] CRITICAL EEEE_F1YJ 826-4393 LBL,P/N LABEL,PCB,28MM X MM [EEEE:F1YK] CRITICAL EEEE_F1YK 826-4393 LBL,P/N LABEL,PCB,28MM X MM [EEEE:F1YL] CRITICAL EEEE_F1YL 826-4393 LBL,P/N LABEL,PCB,28MM X MM [EEEE:F1YM] CRITICAL EEEE_F1YM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM D D TABLE_BOMGROUP_ITEM 607-9310 POWER FETS PAIR,RENESAS,5V_S3,J30 5V_S3_POWER_FET:REN TABLE_BOMGROUP_ITEM 607-9311 POWER FETS PAIR,RENESAS,PBUS_CHARGER,J30 CHARGER_POWER_FET:REN 639-3752 PCBA,MLB,MOL,2.9G,J30 J30_CMNPTS,CPU_2_9GHZ,SODIMM:MOLEX,EEEE_F1YK 639-3756 PCBA,MLB,HYB,2.9G,J30 J30_CMNPTS,CPU_2_9GHZ,SODIMM:HYBRID,EEEE_F1YH 639-3753 PCBA,MLB,FOX,2.5G,J30 J30_CMNPTS,CPU_2_5GHZ,SODIMM:FOXCONN,EEEE_F1YL 639-3755 PCBA,MLB,HYB,2.5G,J30 J30_CMNPTS,CPU_2_5GHZ,SODIMM:HYBRID,EEEE_F1YJ 639-3751 PCBA,MLB,MOL,2.5G,J30 J30_CMNPTS,CPU_2_5GHZ,SODIMM:MOLEX,EEEE_F1YM 639-3754 PCBA,MLB,FOX,2.9G,J30 J30_CMNPTS,CPU_2_9GHZ,SODIMM:FOXCONN,EEEE_F1YG TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM Programmable Parts PART NUMBER C J30 BOM GROUPS REFERENCE DES CRITICAL 335S0862 QTY IC,FLASH,SERIAL,SPI,!MBIT,2V7,REV F DESCRIPTION U3990 CRITICAL BOM OPTION 341S3096 IC ENET,1!MBITFLAH,CIV REV01,K9x U3990 CRITICAL ENET_PROG 335S0550 IC,EEPROM,SERIAL,SPI,4Kx8,1.8V,MLP8,LF U3690 CRITICAL T29ROM:BLANK 341S3430 IC,T29 EEPROM,LR,J30/J31 U3690 CRITICAL T29ROM:PROG 337S3997 IC,MCU,32B,LPC1112A,16KB/2KB,HVQFN25 U9330 CRITICAL T29MCU:BLANK 341S3365 IC,PROGRMD,T29,PORT MCU,K90IA,K91A,K92A U9330 CRITICAL T29MCU:PROG 338S1098 IC,SMC12-A3,40MHZ/50DMIPS MCU,9x9,157BGA U4900 CRITICAL SMC_BLANK 341S3300 IC,SMC,EXTERNAL,FSB,A3,J30 U4900 CRITICAL SMC_PROG 335S0807 IC,SPI SRL 50MHZ FLASH,64MBT,8SOP,FUSE=1 U6100 CRITICAL BOOTROM_BLANK 335S0812 64 MBIT SPI SRL DUAL I/O FLSH,SOIC8 U6100 CRITICAL BOOTROM_BLANK 341S3558 IC,EFI,V00C7,J30/J31 U6100 CRITICAL BOOTROM_PROG 341S2384 IR,ENCORE II, CY7C63803-LQXC U4800 CRITICAL 341S3522 IC,PSOC,TP/KB,J30/J31 U5701 CRITICAL ENET_BLANK C TABLE_BOMGROUP_HEAD BOM GROUP BOM OPTIONS J30_COMMON ALTERNATE,COMMON,J30_COMMON1,J30_COMMON2,J30_DEBUG:ENG,J30_PROGPARTS,T29BST:Y,TBTHV:P15V J30_COMMON1 BATT_3S,CPUMEM_S0,USBHUB2513B,HUB_3NONREM,T29:YES,SDRV_PD,SDRVI2C:MCU,AXG_PHASE1,BTPWR:S4,UV_GLUE_J30 J30_COMMON2 MIKEY,TPAD:Z2,RAMCFG_SLOT TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM J30_PROGPARTS BOOTROM_PROG,SMC_PROG,TPAD_PROG,ENET_PROG,T29ROM:PROG,T29MCU:PROG J30_DEVEL:ENG BKLT:ENG,XDP_CONN,XDP_CPU:BPM,XDP_PCH,LPCPLUS_CONN:YES,LOADISNS:YES,DDRVREF_DAC,S0PGOOD_ISL TPAD_PROG TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM J30_DEVEL:PVT LPCPLUS_CONN:YES,XDP_CONN J30_DEBUG:ENG DEVEL_BOM,MOJO:YES,XDP,LPCPLUS_R:YES,VREFDQ:M1_M3,VREFCA:LDO_DAC Alternate Parts TABLE_BOMGROUP_ITEM TABLE_ALT_HEAD TABLE_BOMGROUP_ITEM J30_DEBUG:PVT DEVEL_BOM,BKLT:PROD,MOJO:YES,XDP,LPCPLUS_R:YES,VREFDQ:M1_M3,VREFCA:LDO,USBHUB2514B J30_DEBUG:PROD BKLT:PROD,MOJO:YES,XDP,LPCPLUS_R:YES,LOADISNS:NO,VREFDQ:M1_M3,VREFCA:LDO,USBHUB2513B PART NUMBER ALTERNATE FOR PART NUMBER 138S0603 138S0602 BOM OPTION REF DES COMMENTS: ALL Murata alt to Samsung TABLE_ALT_HEAD PART NUMBER ALTERNATE FOR PART NUMBER 152S1499 BOM OPTION REF DES COMMENTS: 152S0864 ALL Coilcraft alt to Murata 152S1493 152S1300 ALL Coilcraft alt to Murata 138S0652 138S0648 ALL Samsung/Murata alt to Taiyo 138S0684 138S0660 ALL Murata alt to Taiyo 152S1512 152S1295 ALL Cyntec alt to NEC 152S1019 152S1271 ALL Cyntec alt to TOKO 376S1023 376S0960 ALL Siliconix alt to Renesas 353S3312 353S3055 ALL NXP alt to Pericom 353S3238 353S1428 ALL Intersil alt to TI 353S3519 353S2179 ALL Intersil alt to TI 155S0578 155S0367 ALL Taiyo alt to Murata 138S0681 138S0638 ALL Taiyo alt to Samsung 138S0671 138S0673 ALL Taiyo alt to Murata 376S0903 376S0796 ALL Fairchidl alt to Vishay 377S0124 377S0057 ALL Amotech alt to Tdk 341S3492 341S3096 ALL Numonix alt to Atmel (ENET ROM) 376S1053 376S0604 ALL Diodes alt to fairchild 376S1076 376S0634 ALL Diodes alt to onsemi TABLE_ALT_ITEM TABLE_ALT_ITEM TABLE_BOMGROUP_ITEM TABLE_ALT_ITEM 157S0058 157S0084 ALL Delta alt to TDK Magnetics TABLE_ALT_ITEM TABLE_ALT_ITEM 128S0303 Module Parts 128S0353 ALL Panasonic alt to Sanyo TABLE_ALT_ITEM TABLE_ALT_ITEM 138S0676 138S0691 ALL Murata alt to Samsung TABLE_ALT_ITEM TABLE_ALT_ITEM PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL 152S0778 BOM OPTION 152S0693 ALL Cyntec alt to Vishay TABLE_ALT_ITEM TABLE_ALT_ITEM 337S4113 U1000 IC,IVB,2C,35W,1023BGA CRITICAL 376S0855 376S1032 ALL Diodes alt to Toshiba 376S0977 376S0859 ALL Diodes alt to Toshiba TABLE_ALT_ITEM CPU_IVB_2C TABLE_ALT_ITEM B 337S4264 U1000 IVB,S R0N0,PRQ,L1,2.5,35W,2+2,1.1,3M,BGA CRITICAL TABLE_ALT_ITEM CPU_2_5GHZ TABLE_ALT_ITEM 376S0972 337S4265 U1000 IVB,S R0MU,PRQ,L1,2.9,35W,2+2,1.25,4M,BGA CRITICAL 376S1017 ALL Rohm alt to Toshiba TABLE_ALT_ITEM 337S4269 PANTHERPOINT,C1,SLJ8C,PRQ,BD82HM77 U1800 CRITICAL 343S0534 IC,BCM57765B0,ENET&SD,8X8 U3900 CRITICAL 376S0937 376S0845 ALL Fairchild alt to Renesas 376S0777 376S0761 ALL AON alt to Siliconix TABLE_ALT_ITEM TABLE_ALT_ITEM TABLE_ALT_ITEM TABLE_ALT_ITEM 338S0753 U4100 IC,FW643E,1394B PHY/OHCI LINK/PCI-E,12 376S0957 376S0958 ALL Fairchild alt to Fairchild 376S0953 376S0958 ALL Fairchild alt to Renesas TABLE_ALT_ITEM CRITICAL TABLE_ALT_ITEM 338S1072 IC,T29,PRQ,S LJJY,FCBGA,15x15MM,C1 U3600 CRITICAL TABLE_ALT_ITEM T29:YES TABLE_ALT_ITEM 353S3055 IC,PI3VEDP212,X2 DISPLAYPORT 2:1 MUX,QFN U9390 377S0107 CRITICAL 377S0126 ALL ONsemi alt to Semtech TABLE_ALT_ITEM TABLE_ALT_ITEM 946-3827 UV_GLUE_J30 J30 MLB DYMAX ADHESIVE 29993-SC 0.48G CRITICAL 371S0709 UV_GLUE_J30 371S0652 ALL NXP alt to Infineon TABLE_ALT_ITEM TABLE_ALT_ITEM 516S0806 CONN,204P,SODIMM,SOCKET,DDR3,RAM,BGA,FOXCONN J3100 CRITICAL 514-0788 SODIMM:FOXCONN 514-0671 ALL Acon(w liteon) alt to Acon TABLE_ALT_ITEM TABLE_ALT_ITEM 516-0246 J2900 CONN,204P,SODIMM,DDR3,P=0.6MM,FOXCONN B TABLE_ALT_ITEM CPU_2_9GHZ CRITICAL 607-9310 SODIMM:FOXCONN 607-8722 ALL Renesas alternate to fairchild TABLE_ALT_ITEM TABLE_ALT_ITEM 516S0805 CONN,204P,SODIMM,SOCKET,DDR3,RAM,BGA,MOLEX J3100 CRITICAL SODIMM:MOLEX 516-0245 CONN,204P,SODIMM,DDR3,P=0.6MM,MOLEX J2900 CRITICAL SODIMM:MOLEX 516S0805 CONN,204P,SODIMM,SOCKET,DDR3,RAM,BGA,MOLEX J3100 CRITICAL SODIMM:HYBRID 516-0246 CONN,204P,SODIMM,DDR3,P=0.6MM,FOXCONN J2900 CRITICAL SODIMM:HYBRID 607-9311 607-8723 ALL Renesas alternate to fairchild TABLE_ALT_ITEM TABLE_ALT_ITEM Sub BOM PART NUMBER A DESCRIPTION REFERENCE DES CRITICAL 085-3092 QTY J30 MLB DEVELOPMENT DEVEL CRITICAL BOM OPTION DEVEL_BOM 607-8895 CMN PTS,PCBA,MLB,J30 CMNPTS CRITICAL J30_CMNPTS 607-8721 POWER_FETS PAIR,FAIRCHILD,DDR,J30 CSET1 CRITICAL FET_PAIR 607-8722 POWER_FETS PAIR,FAIRCHILD,5V_S3,J30 CSET2 CRITICAL FET_PAIR SYNC_MASTER=K90I_MLB SYNC_DATE=02/15/2011 PAGE TITLE BOM Configuration DRAWING NUMBER Apple Inc 051-9058 REVISION R 607-8723 POWER_FETS PAIR,FAIRCHILD,PBUS_CHARGER,J30 CRITICAL CSET3 FET_PAIR NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED 6.0.0 BRANCH PAGE OF 109 SHEET OF 86 SIZE D A NC_EDP_TXP MAKE_BASE=TRUE NC_EDP_TXN MAKE_BASE=TRUE NC_EDP_AUXP MAKE_BASE=TRUE NC_EDP_AUXN Functional Test Points NC NO_TESTs NO_TEST X19 CONN Fan Connectors I12 I15 I16 TRUE TRUE TRUE PP5V_S0 FAN_RT_PWM FAN_RT_TACH I303 52 I301 52 I302 (NEED TO ADD GND TP) I300 I299 D I554 I553 I555 MIC FUNC_TEST BI_MIC_LO TRUE BI_MIC_HI TRUE BI_MIC_SHIELD TRUE I298 61 62 I293 61 62 I288 61 62 I292 (NEED TO ADD GND TP) I295 I290 I271 I289 I227 I226 I228 I230 I229 I231 SPEAKER FUNC_TEST SPKRAMP_L_N_OUT TRUE SPKRAMP_L_P_OUT TRUE SPKRAMP_R_N_OUT TRUE SPKRAMP_R_P_OUT TRUE SPKRAMP_SUB_N_OUT TRUE SPKRAMP_SUB_P_OUT TRUE I595 60 61 85 I594 60 61 85 I593 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE 17 (NEED TP) PP3V3_WLAN PCIE_AP_D2R_PI_P 32 PCIE_AP_D2R_PI_N 32 PCIE_AP_R2D_P 32 PCIE_AP_R2D_N 32 PCIE_CLK100M_AP_CONN_P 32 PCIE_CLK100M_AP_CONN_N 32 PP3V3_S3RS4_BT_F 32 PCIE_WAKE_L 17 USB_BT_CONN_P 32 USB_BT_CONN_N 32 AP_CLKREQ_Q_L 32 AP_RESET_CONN_L 32 AP_TEMP_SMB_SDA_R 32 AP_TEMP_SMB_SCL_R 32 WIFI_EVENT_L_R 32 17 32 46 DEBUG VOLTAGE 81 81 81 I285 85 I414 85 I280 I281 24 32 I282 80 I283 80 I376 I278 I270 I416 I273 I274 I275 60 61 85 I417 60 61 85 I392 I391 60 61 85 I390 IPD_FLEX_CONN LVDS FUNC_TEST I372 I370 I259 I258 I260 I407 C I262 I261 I256 I257 I255 I252 I253 I254 I250 I251 I313 I246 I247 I248 I249 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE PP3V3_LCDVDD_SW_F (NEED PP3V3_S0_LCD_F PPVOUT_SW_LCDBKLT (NEED LVDS_DDC_CLK LVDS_DDC_DATA LVDS_IG_A_DATA_N LVDS_IG_A_DATA_P LVDS_IG_A_DATA_N LVDS_IG_A_DATA_P LVDS_IG_A_DATA_N LVDS_IG_A_DATA_P LVDS_CONN_A_CLK_F_N LVDS_CONN_A_CLK_F_P LED_RETURN_1 LED_RETURN_2 LED_RETURN_3 LED_RETURN_4 LED_RETURN_5 LED_RETURN_6 TP) 74 I371 74 I369 TP) 74 77 I368 74 I361 74 I366 17 74 80 I365 17 74 80 I363 17 74 80 I364 17 74 80 I362 17 74 80 I360 17 74 80 I359 74 85 I357 74 85 I358 74 77 I377 74 77 I564 74 77 I626 I345 B I265 I266 I628 I627 I346 (NEED TP) PP5V_SW_ODD SMC_ODD_DETECT SATA_ODD_D2R_C_P SATA_ODD_D2R_C_N SATA_ODD_R2D_P SATA_ODD_R2D_N SMC_SSD_TEMP_CTL_R HDD_OOB_TEMP I347 41 I349 41 45 I348 41 85 I350 41 85 I352 41 80 I351 41 80 I353 I327 I328 (NEED TO ADD GND TP) I329 I343 SATA HDD/IR/SIL I342 I341 I319 I314 I315 I318 I317 I307 I309 I625 I311 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE I383 53 54 I419 53 54 I382 53 54 I565 53 54 I380 (NEED PP5V_S0_HDD_FLT SATA_HDD_R2D_P SATA_HDD_R2D_N SATA_HDD_D2R_C_P SATA_HDD_D2R_C_N SYS_LED_ANODE_R IR_RX_OUT SMC_SSD_THROTTLE_R PP5V_S3_IR_R TP) 41 I339 41 80 I340 41 80 I338 41 80 I336 41 80 I337 41 I333 41 44 I335 I334 41 I332 (NEED TO ADD GND TP) I330 I331 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE PPVCORE_S0_CPU PPVCORE_S0_AXG PP1V2_S3_ENET_INTREG PP1V05_S0 PP1V5_S3RS0 PP1V8_S0 PP3V3_S0 PP5V_S0 PP3V3_S3 PP5V_S3 PPVCCSA_S0_CPU PP3V3_S5 PP3V42_G3H PPBUS_G3H PP3V3_ENET PP3V3_WLAN PP5V_SW_ODD PP5V_S0_HDD_FLT PP18V5_Z2 PP3V3_S0_LCD_F PP3V3_LCDVDD_SW_F PP4V5_AUDIO_ANALOG PP1V5_S3 SMC_PM_G2_EN PM_SLP_S4_L PM_SLP_S3_L 17 17 NC_CRT_IG_DDC_CLK TRUE MAKE_BASE=TRUE NC_CRT_IG_DDC_DATA TRUE MAKE_BASE=TRUE TP_CRT_IG_HSYNC TP_CRT_IG_VSYNC TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TP_LVDS_IG_CTRL_CLK TP_LVDS_IG_CTRL_DATA TP_PCH_LVDS_VBG NC_LVDS_IG_CTRL_CLK TRUE MAKE_BASE=TRUE NC_LVDS_IG_CTRL_DATA TRUE MAKE_BASE=TRUE NC_PCH_LVDS_VBG TRUE MAKE_BASE=TRUE 17 85 17 17 I321 I320 A I305 TRUE TRUE TRUE TRUE SMBUS_SMC_5_G3_SCL SMBUS_SMC_5_G3_SDA SYS_DETECT_L (NEED PPVBAT_G3H_CONN 16 85 16 16 TP_HDA_SDIN1 TP_HDA_SDIN2 TP_HDA_SDIN3 18 41 TP_PCI_PME_L TP_PCI_CLK33M_OUT3 74 16 74 16 57 62 16 45 73 16 TP_PCIE_CLK100M_PEBN TP_PCIE_CLK100M_PEBP 53 54 38 45 48 84 38 TP_FW643_SDA TP_FW643_SM TP_FW643_TCK TP_FW643_TMS TP_FW643_FW620_L TP_FW643_VBUF TP_FW643_OCR10_CTL TP) 63 64 I394 23 53 54 23 54 23 23 (NEED TP) 23 63 23 63 23 16 16 LPC+SPI DEBUG_CONN 16 16 I599 53 I600 53 I601 53 I602 53 I603 53 I604 53 I605 53 I606 53 I607 53 I608 53 I610 53 I611 53 I612 53 I614 53 I613 53 I617 53 I616 53 I618 53 I620 53 I619 53 I622 (NEED TO ADD GND TP) =PEG_R2D_C_N TRUE =PEG_D2R_P TRUE =PEG_D2R_N TRUE =PEG_R2D_C_P TRUE =PEG_R2D_C_N TRUE =PEG_D2R_P =PEG_D2R_N NC_PEG_R2D_CN NC_CLINK_CLK NC_CLINK_DATA NC_CLINK_RESET_L NC_FW643_SDA NC_FW643_SM NC_FW643_TCK NC_FW643_TMS NC_FW643_FW620_L NC_FW643_VBUF NC_FW643_OCR10_CTL NC_PEG_D2RN NC_PCH_GPIO64_CLKOUTFLEX0 TRUE MAKE_BASE=TRUE NC_PCH_GPIO65_CLKOUTFLEX1 TRUE MAKE_BASE=TRUE NC_PCH_GPIO66_CLKOUTFLEX2 TRUE MAKE_BASE=TRUE NC_PCH_GPIO67_CLKOUTFLEX3 TRUE MAKE_BASE=TRUE TP_PCIE_CLK100M_PE4N TP_PCIE_CLK100M_PE4P TP_PCIE_CLK100M_PE5N TP_PCIE_CLK100M_PE5P TP_PCIE_CLK100M_PE6N TP_PCIE_CLK100M_PE6P TP_PCIE_CLK100M_PE7N TP_PCIE_CLK100M_PE7P TP_PSOC_P1_3 TP_SATA_C_D2RN TP_SATA_C_D2RP TP_SATA_C_R2D_CN TP_SATA_C_R2D_CP TP_SATA_D_D2RN TP_SATA_D_D2RP TP_SATA_D_R2D_CN TP_SATA_D_R2D_CP TP_SATA_E_D2RN TP_SATA_E_D2RP TP_SATA_E_R2D_CN TP_SATA_E_R2D_CP TP_SATA_F_D2RN TP_SATA_F_D2RP TP_SATA_F_R2D_CN TP_SATA_F_R2D_CP 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 33 33 33 33 16 45 47 81 33 16 45 47 81 33 24 47 81 33 16 45 47 81 33 17 45 47 33 16 45 47 33 19 47 NC_PCIE_CLK100M_PE4N NC_PCIE_CLK100M_PE4P NC_PCIE_CLK100M_PE5N NC_PCIE_CLK100M_PE5P NC_PCIE_CLK100M_PE6N NC_PCIE_CLK100M_PE6P NC_PCIE_CLK100M_PE7N NC_PCIE_CLK100M_PE7P NC_PSOC_P1_3 NC_SATA_C_D2RN NC_SATA_C_D2RP NC_SATA_C_R2D_CN NC_SATA_C_R2D_CP NC_SATA_D_D2RN NC_SATA_D_D2RP NC_SATA_D_R2D_CN NC_SATA_D_R2D_CP NC_SATA_E_D2RN NC_SATA_E_D2RP NC_SATA_E_R2D_CN NC_SATA_E_R2D_CP NC_SATA_F_D2RN NC_SATA_F_D2RP NC_SATA_F_R2D_CN NC_SATA_F_R2D_CP TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TP_TBT_MONDC0 TP_TBT_MONDC1 TP_TBT_MONOBSP TP_TBT_MONOBSN TP_DP_T29SRC_ML_CP TP_DP_T29SRC_ML_CN TP_DP_T29SRC_AUXCH_CP TP_DP_T29SRC_AUXCH_CN TP_T29_PCIE_RESET0_L TP_T29_PCIE_RESET1_L TP_T29_PCIE_RESET2_L TP_T29_PCIE_RESET3_L 33 33 16 45 47 81 TRUE MAKE_BASE=TRUE 16 NC_FW643_AVREG TRUE MAKE_BASE=TRUE NC_FW643_TDI TRUE MAKE_BASE=TRUE TP_PCH_GPIO64_CLKOUTFLEX0 TP_PCH_GPIO65_CLKOUTFLEX1 TP_PCH_GPIO66_CLKOUTFLEX2 TP_PCH_GPIO67_CLKOUTFLEX3 16 45 47 81 MAKE_BASE=TRUE NC_PCIE_CLK100M_PEBN NC_PCIE_CLK100M_PEBP NC_TP_XDP_PCH_OBSFN_A TRUE MAKE_BASE=TRUE NC_TP_XDP_PCH_OBSFN_B TRUE MAKE_BASE=TRUE NC_TP_XDPPCH_HOOK2 TRUE MAKE_BASE=TRUE NC_TP_XDPPCH_HOOK3 TRUE MAKE_BASE=TRUE NC_TP_XDP_PCH_OBSFN_D TRUE MAKE_BASE=TRUE NC_TP_XDP_PCH_HOOK4 TRUE MAKE_BASE=TRUE NC_TP_XDP_PCH_HOOK5 TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE NC_TBT_MONDC0 NC_TBT_MONDC1 NC_TBT_MONOBSP NC_TBT_MONOBSN NC_DP_T29SRC_ML_CP NC_DP_T29SRC_ML_CN NC_DP_T29SRC_AUXCH_CP NC_DP_T29SRC_AUXCH_CN TP_T29_PCIE_RESET0_L TP_T29_PCIE_RESET1_L TP_T29_PCIE_RESET2_L TP_T29_PCIE_RESET3_L C 33 33 33 24 47 NO_TEST NC NO_TESTs 45 46 47 I500 TRUE 45 46 47 I499 TRUE 45 46 47 I498 TRUE 45 46 47 I497 TRUE I495 TRUE 45 46 47 45 46 47 I496 TRUE 47 I494 TRUE 47 I493 TRUE NC_FW2_TPBP NC_FW2_TPBN NC_FW2_TPBIAS NC_FW2_TPAP NC_FW2_TPAN NC_FW0_TPBP NC_FW0_TPBN NC_FW0_TPAP 40 40 40 40 I522 TRUE 40 I521 TRUE 40 I520 TRUE I519 TRUE I518 TRUE 40 I517 47 53 (NEED TO ADD GND TP) I581 TRUE I580 TRUE I582 TRUE I583 TRUE I584 TRUE I585 TRUE I586 TRUE I588 TRUE I587 TRUE (NEED TO ADD GND TP) 54 54 (NEED TO ADD GND TP) I547 TRUE I546 TRUE I545 TRUE I544 TRUE I543 TRUE I542 TRUE I541 TRUE I540 TRUE 81 81 81 40 47 19 47 56 PCH_VSS_NCTF PCH_VSS_NCTF PCH_VSS_NCTF XDP_PCH_AP_PWR_EN XDP_PCH_USB_HUB_SOFT_RST_L XDP_PCH_SDCONN_STATE_RST_L XDP_PCH_ENET_PWR_EN XDP_PCH_SDCONN_DET_L XDP_PCH_S5_PWRGD 23 XDP_PCH_PWRBTN_L 23 XDP_PCH_ISOLATE_CPU_MEM_L XDP_FW_CLKREQ_L XDP_AP_CLKREQ_L XDP_PCH_AUD_IPHS_SWITCH_EN TRUE 8 PCH_VSS_NCTF PCH_VSS_NCTF PCH_VSS_NCTF 81 81 81 TP_LVDS_IG_B_CLKN TP_LVDS_IG_B_CLKP TP_LVDS_IG_BKL_PWM TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE SMC_BS_ALRT_L PCH_VSS_NCTF PCH_VSS_NCTF PCH_VSS_NCTF PCH_VSS_NCTF PCH_VSS_NCTF PCH_VSS_NCTF PCH_VSS_NCTF PCH_VSS_NCTF 81 81 81 81 81 81 81 81 NC_LVDS_IG_B_CLKN NC_LVDS_IG_B_CLKP NC_LVDS_IG_BKL_PWM TRUE MAKE_BASE=TRUE NC_SMC_BS_ALRT_L A SYNC_MASTER=K90I_MLB PAGE TITLE FUNC TEST CAMERA/ALS CONN BIL CONN I326 I323 I324 I325 I308 TRUE TRUE TRUE TRUE TRUE PP3V42_G3H SMBUS_SMC_5_G3_SCL SMBUS_SMC_5_G3_SDA SMC_BIL_BUTTON_L SMC_LID_R I408 I409 45 48 84 I410 45 48 84 I297 45 46 63 I294 63 (NEED TO ADD GND TP) TRUE TRUE TRUE TRUE TRUE DRAWING NUMBER PP5V_S3_ALSCAMERA_F SMBUS_SMC_2_S3_SCL SMBUS_SMC_2_S3_SDA USB_CAMERA_CONN_P USB_CAMERA_CONN_N 17 45 48 84 17 45 48 84 32 80 17 32 80 17 TP_SDVO_TVCLKINN TP_SDVO_TVCLKINP TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE NC_SDVO_TVCLKINN NC_SDVO_TVCLKINP TP_SDVO_STALLN TP_SDVO_STALLP TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE NC_SDVO_STALLN NC_SDVO_STALLP TP_SDVO_INTN TP_SDVO_INTP TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE NC_SDVO_INTN NC_SDVO_INTP (NEED TO ADD GND TP) 17 Apple Inc 32 17 B 33 17 45 47 TRUE 53 =PEG_R2D_C_P TRUE MAKE_BASE=TRUE TP_XDP_PCH_OBSFN_A TP_XDP_PCH_OBSFN_B TP_XDPPCH_HOOK2 TP_XDPPCH_HOOK3 TP_XDP_PCH_OBSFN_D TP_XDP_PCH_HOOK4 TP_XDP_PCH_HOOK5 I491 TRUE NC_PEG_R2D_CP 16 53 54 I492 SMC_KDBLED_PRESENT_L 63 TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TP_FW643_AVREG TP_FW643_TDI TRUE KBDLED_ANODE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE 45 48 84 (NEED TO ADD GND TP) TRUE NC_PEG_D2RN 53 38 38 I596 D TRUE MAKE_BASE=TRUE 17 26 45 73 38 53 TP_CPU_RSVD NC_PEG_D2RP NC_PCI_PME_L NC_PCI_CLK33M_OUT3 TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE 17 26 32 45 73 53 54 53 TRUE MAKE_BASE=TRUE 16 53 54 LPC_AD LPC_AD LPC_AD LPC_AD LPC_CLK33M_LPCPLUS LPC_FRAME_L LPC_PWRDWN_L LPC_SERIRQ LPCPLUS_GPIO LPCPLUS_RESET_L PM_CLKRUN_L PP3V42_G3H PP5V_S0 SMC_RX_L SMC_TCK SMC_TDI SMC_TDO SMC_TMS SMC_TX_L SPI_ALT_CLK SPI_ALT_CS_L SPI_ALT_MISO SPI_ALT_MOSI SPIROM_USE_MLB TP_CPU_RSVD NC_PEG_R2D_CN 16 38 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TP_CPU_THERMDC TRUE NC_PEG_D2RP TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TP_CLINK_CLK TP_CLINK_DATA TP_CLINK_RESET_L 16 38 I597 TP_CPU_THERMDA NC_PEG_R2D_CP 41 53 54 I598 TRUE NC_CPU_RSVD 54 53 54 53 TP_EDP_AUX_N MAKE_BASE=TRUE 18 32 46 38 53 TRUE TRUE MAKE_BASE=TRUE KBD BACKLIGHT CONN I356 NC_HDA_SDIN1 NC_HDA_SDIN2 NC_HDA_SDIN3 TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE 53 54 53 TP_EDP_AUX_P MAKE_BASE=TRUE 45 48 84 45 48 84 NC_CPU_THERMDC NC_CPU_RSVD 38 PP18V5_DCIN_FUSE ADAPTER_SENSE TRUE MAKE_BASE=TRUE 17 85 BATT POWER CONN I322 NC_CRT_IG_HSYNC NC_CRT_IG_VSYNC 53 54 TRUE TRUE TP_EDP_TX_N MAKE_BASE=TRUE 17 (NEED TO ADD GND TP) DC POWER CONN TP_EDP_TX_P TRUE MAKE_BASE=TRUE 71 54 I304 PP3V3_S4 PP3V42_G3H WS_KBD1 WS_KBD2 WS_KBD3 WS_KBD4 WS_KBD5 WS_KBD6 WS_KBD7 WS_KBD8 WS_KBD9 WS_KBD10 WS_KBD11 WS_KBD12 WS_KBD13 WS_KBD14 WS_KBD15_CAP WS_KBD16_NUM WS_KBD17 WS_KBD18 WS_KBD19 WS_KBD20 WS_KBD21 WS_KBD22 WS_KBD23 WS_KBD_ONOFF_L WS_LEFT_SHIFT_KBD WS_LEFT_OPTION_KBD WS_CONTROL_KBD TP_CRT_IG_DDC_CLK TP_CRT_IG_DDC_DATA TRUE MAKE_BASE=TRUE NC_CPU_THERMDA 53 54 KEYBOARD CONN SATA ODD CONN I267 I386 54 74 77 I344 I269 I418 I312 I355 I268 PP3V3_S4 PP18V5_Z2 Z2_CS_L Z2_DEBUG3 Z2_MOSI Z2_MISO Z2_SCLK Z2_BOOST_EN Z2_HOST_INTN Z2_CLKIN Z2_KEY_ACT_L Z2_RESET PSOC_MISO PSOC_MOSI PSOC_SCLK SMBUS_SMC_2_S3_SCL SMBUS_SMC_2_S3_SDA PSOC_F_CS_L PICKB_L PP5V_S5_CUMULUS 74 77 I354 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE I388 (NEED TO ADD GND TP) 74 77 (NEED TO ADD GND TP) I264 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NC_CRT_IG_BLUE NC_CRT_IG_GREEN NC_CRT_IG_RED MAKE_BASE=TRUE I287 (NEED TO ADD GND TP) I374 TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE 81 60 61 85 I375 17 TP_CRT_IG_BLUE TP_CRT_IG_GREEN TP_CRT_IG_RED 051-9058 REVISION R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED 6.0.0 BRANCH PAGE OF 109 SHEET OF 86 SIZE D "G3Hot" (Always-Present) Rails 64 63 =PPBUS_G3H PPBUS_G3H 66 =PP3V3_S5_REG MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.8V MAKE_BASE=TRUE 35 PPVIN_SW_T29BST VOLTAGE=12.8V 50 =PPVIN_S5_HS_COMPUTING_ISNS =PPBUS_S0_LCDBKLT =PPBUS_S5_FWPWRSW =PPBUS_S0_VSENSE =PPVIN_SW_T29BST =PPVIN_S5_HS_COMPUTING_ISNS_R =PPVIN_S5_HS_OTHER_ISNS_R 77 39 50 35 50 50 PPBUS_S5_HS_COMPUTING_ISNS =PPVIN_S0_CPUIMVP =PPVIN_S3_DDRREG =PPVIN_S0_CPUVCCIOS0 =PPVIN_S0_VCCSAS0 =PPVIN_S0_CPUAXG 50 =PPVIN_S5_HS_OTHER_ISNS 63 =PP18V5_DCIN_CONN 67 70 65 69 PPBUS_S5_HS_OTHER_ISNS 72 =PP3V3_SUS_FET 66 =PP3V42_G3H_REG PP3V42_G3H 64 50 MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.42V MAKE_BASE=TRUE =PP3V3_S5_LPCPLUS =PP3V3_S5_SMC =PP3V42_G3H_BATT =PP3V42_G3H_CHGR =PP3V42_G3H_ONEWIREPROT =PP3V42_G3H_PWRCTL =PP3V42_G3H_SMBUS_SMC_BSA =PP3V42_G3H_SMCUSBMUX =PP3V42_G3H_TPAD =PPVIN_S5_SMCVREF =PPVBAT_G3_SYSCLK =PP3V42_G3H_AUDIO C 24 =PPVRTC_G3_OUT 72 =PP3V3_S4_FET 45 46 63 64 63 72 =PP3V3_S3_FET 53 72 =PP5V_SUS_FET 24 58 16 17 20 72 =PP3V3_S0_FET 66 =PP5V_S3_REG 54 22 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5V MAKE_BASE=TRUE =PP5V_S3_ALSCAMERA =PP5V_S3_AUDIO =PP5V_S3_AUDIO_AMP =PP5V_S3_DDRREG =PP5V_S3_IR =PP5V_S3_MEMRESET =PP5V_S3_ODD =PP5V_S3_P5VS0FET =PP5V_S3_USB =PP5V_S3_SYSLED 72 =PP5V_S0_FET PP5V_S0 32 57 60 67 41 44 26 41 72 42 46 MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=5V MAKE_BASE=TRUE =PP5V_S0_BKL =PP5V_S0_CPUIMVP =PP5V_S0_CPUVCCIOS0 =PP5V_S0_FAN_RT =PP5V_S0_HDD_ISNS_R =PP5V_S0_KBDLED =PP5V_S0_LPCPLUS =PP5V_S0_VCCSAS0 =PP5V_S0_PCH =PP5V_S0_VMON =PP5V_S0_ISNS =PP5V_S0_AUDIO A 49 =PP5V_S0_HDD_ISNS 77 68 69 70 52 49 54 47 65 22 24 73 49 PP5V_S0_HDD 76 19 =PPDDR_S3_REG 41 40 19 20 22 71 39 PP3V3_FW_FWPHY =PP3V3_FW_FET MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V MAKE_BASE=TRUE 20 24 20 22 =PP1V0_FW_FWPHY 67 31 T29 Rails (off when no cable) 35 PP15V_T29 =PP15V_T29_REG MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=17.8V MAKE_BASE=TRUE 72 49 =PPHV_SW_TBTAPWRSW =PP1V5_S3RS0_FET 72 PP1V5_S3RS0 35 PP3V3_T29 =PP3V3_T29_FET MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V MAKE_BASE=TRUE 56 =PP1V5_S3_CPU_VCCDDR 20 22 =PP1V5_S0_REG 71 10 12 15 26 =PPVDDIO_T29_CLK =PP3V3_T29_RTR =PP3V3_T29_PCH_GPIO PP1V5_S0 MIN_LINE_WIDTH=2 mm MIN_NECK_WIDTH=0.17 mm VOLTAGE=1.5V MAKE_BASE=TRUE 53 54 46 =PP1V5_S0_RDRVR =PP1V8R1V5_S0_AUDIO =PP3V3R1V5_S0_AUDIO =PP3V3R1V5_S0_PCH_VCCSUSHDA =PP1V5_S0_VMON 30 32 VOLTAGE=3.3V MAKE_BASE=TRUE 76 85 MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.5V MAKE_BASE=TRUE 71 46 VOLTAGE=3.3V MAKE_BASE=TRUE 38 39 29 22 73 D MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.0V MAKE_BASE=TRUE 27 =PP1V5_S3_P1V5S3RS0_FET =PP1V5_S3_DDR_ISNS_R 16 17 18 19 38 39 40 PP1V0_FW_FWPHY =PP1V0_FW_FET_R 26 MIN_LINE_WIDTH=0.8 MM MIN_NECK_WIDTH=0.1 MM VOLTAGE=1.5V MAKE_BASE=TRUE 20 40 22 39 PP1V5_S3 20 22 PP3V3_S0 =PPVP_FW_PORT1 =PPVP_FW_PHY_CPS_FET 14 =PP3V3_FW_FWPHY =PP3V3_S0_P1V05FWFET =PP1V5_S3_MEMRESET =PP1V5_S3_MEM_A =PP1V5_S3_MEM_B =PPVIN_S0_DDRREG_LDO =PPDDR_S3_MEMVREF 72 PP3V3_S3 PPVP_FW =PPBUS_FW_FET PP1V5_S3_DDR 73 VOLTAGE=3.3V MAKE_BASE=TRUE 39 MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=12.8V MAKE_BASE=TRUE MIN_LINE_WIDTH=0.8 MM MIN_NECK_WIDTH=0.1 MM VOLTAGE=1.5V MAKE_BASE=TRUE 24 41 35 24 33 34 35 16 19 PP1V05_T29 =PP1V05_T29_FET 35 MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V MAKE_BASE=TRUE 57 57 C =PP1V05_T29_RTR 20 22 24 34 73 32 26 =PPVTT_S3_DDR_BUF 67 31 PPVTTDDR_S3 MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=0.75V MAKE_BASE=TRUE 48 48 55 =PPVTT_S0_DDR_LDO 67 PP0V75_S0_DDRVTT MIN_LINE_WIDTH=2 mm MIN_NECK_WIDTH=0.17 mm VOLTAGE=0.75V MAKE_BASE=TRUE 25 25 1V05 S0 LDO =PP0V75_S0_MEM_VTT_A =PP0V75_S0_MEM_VTT_B =PPVTT_S0_VTTCLAMP 31 32 24 73 =PPVCCSA_S0_REG 65 27 71 PP1V05_S0_PCH_VCCADPLL =PP1V05_S0_LDO MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V MAKE_BASE=TRUE 29 26 PPVCCSA_S0_CPU =PP1V05_S0_PCH_VCCADPLL 22 MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=0.9V MAKE_BASE=TRUE 18 24 49 25 =PPVCCSA_S0_CPU 12 15 85 VOLTAGE=3.3V MAKE_BASE=TRUE =PP3V3_S0_KBDLED =PP3V3_S0_VMON =PPSPD_S0_MEM_A =PPSPD_S0_MEM_B =PP3V3_S0_P1V5S0 =PP3V3_S0_T29PWRCTL =PP3V3_S0_HS_OTHER_ISNS =PP3V3_S0_DPSDRVA =PP3V3_S0_P1V05S0LDO =PP3V3_S0_IMVPISNS =PP3V3_S0_XDP =PP3V3_S0_T29I2C MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.4MM VOLTAGE=5V MAKE_BASE=TRUE =PP5V_S0_HDD =PP1V5_S3_DDR_ISNS 49 73 =PP3V3_S0_HDD =PP3V3_S0_AUDIO =PP3V3_S0_BKL_VDDIO =PP3V3_S0_ISNS =PP3V3_S0_HS_COMPUTING_ISNS =PP3V3_S0_CPUTHMSNS =PP3V3_S0_LCD =PP3V3_S0_DP_DDC =PP3V3_S0_ENETPHY =PP3V3_S0_FAN_RT =PP3V3_S0_FWPWRCTL =PP3V3_S0_FWLATEVG =PP3V3_S0_P3V3T29FET =PP3V3_S0_SDCARD =PP3V3_S0_P1V8S0 =PP3V3_S0_ODD =PP3V3_FW_P3V3FWFET =PP3V3_S0_PCH =PP3V3_S0_PCH_GPIO =PP3V3_S0_PCH_VCC3_3_CLK =PP3V3_S0_PCH_VCC3_3_GPIO =PP3V3_S0_PCH_VCC3_3_HVCMOS =PP3V3_S0_PCH_VCC3_3_PCI =PP3V3_S0_PCH_VCC3_3_SATA =PP3V3_S0_PCH_VCCADAC =PP3V3_S0_PCH_VCCA_LVDS =PP3V3_S0_PWRCTL =PP3V3_S0_RSTBUF =PP3V3_S0_SB_PM =PP3V3_S0_SMBUS_PCH =PP3V3_S0_SMBUS_SMC_0_S0 =PP3V3_S0_SMBUS_SMC_B_S0 =PP3V3_S0_SMC 72 PP5V_SUS PP5V_S3 20 22 PP3V3_S4 MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.20MM 72 MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM VOLTAGE=3.3V MAKE_BASE=TRUE B 17 =PP3V3_S3_USB_HUB =PP3V3_S3_USB_RESET =PP3V3_S3_VREFMRGN =PP3V3_S3_WLAN =PP3V3_S3_SDBUF =PP3V3_S3_P3V3ENETFET =PP3V3_S3_PCH_GPIO =PP3V3_S3_ISNS =PP3V3_S3_USBMUX PP5V_S5 =PP5V_SUS_PCH 74 =PP3V3_S3_BT =PP3V3_S3_MEMRESET =PP3V3_S3_SMBUS_SMC_A_S3 =PP3V3_S3_SMBUS_SMC_MGMT =PP3V3_S3_SMS 46 MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=5V MAKE_BASE=TRUE =PP5V_S5_P1V5DDRFET =PP5V_S5_TPAD =PP5V_S5_P5VSUSFET 72 PP3V3_SUS MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM 42 5V Rails =PP5V_S5_LDO 26 73 48 MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3V MAKE_BASE=TRUE 66 46 =PP1V8_S0_CPU_VCCPLL =PP1V8_S0_PCH_VCCTX_LVDS =PP1V8_S0_PCH_VCC_DFTERM =PP1V8_S0_P1V05S0LDO =PP1V8R1V5_S0_PCH_VCCVRM =PPVDDIO_S0_SBCLK 72 =PP3V3_S4_TPAD =PP3V3_S4_SMC =PP3V3_S4_SD_HPD =PP3V3_S4_BT PPVRTC_G3H =PPVRTC_G3_PCH =PP3V3_S5_SMCBATLOW MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM 47 "FW" (FireWire) Rails PP1V8_S0 72 =PP3V3_SUS_PCH_VCCSUS_USB =PP3V3_SUS_PCH_VCCSUS_GPIO =PP3V3_SUS_PCH_VCCSUS =PP3V3_SUS_PCH_GPIO =PP3V3_SUS_PCH =PP3V3_SUS_PWRCTL =PP3V3_SUS_P1V05SUSLDO =PP3V3_SUS_SMC =PP3V3_SUS_ROM =PP3V3_SUS_PCH_VCC_SPI 66 MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.8V MAKE_BASE=TRUE 2A max supply 23 67 MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM VOLTAGE=18.5V MAKE_BASE=TRUE 63 =PP1V8_S0_REG 71 24 MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM PPDCIN_G3H =PPDCIN_S5_CHGR =PPDCIN_S5_VSENSE 85 VOLTAGE=3.3V MAKE_BASE=TRUE =PP3V3_S5_XDP =PP3V3_S0_P3V3S0FET =PP3V3_S3_P3V3S3FET =PP3V3_S5_CPU_VCCDDR =PP3V3_S4_P3V3S4FET =PP3V3_S5_LCD =PP3V3_S5_PCH =PP3V3_S5_PCHPWRGD =PP3V3_S5_PCH_VCCDSW =PP3V3_S5_SYSCLK =PP3V3_S5_VMON =PP3V3_S5_PWRCTL =PP3V3_S5_P3V3SUSFET =PP3V3_S4_TBTAPWRSW =PP3V3_S5_PCH_GPIO 68 69 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=12.8V MAKE_BASE=TRUE =PPVIN_S5_5VS3 =PPVIN_S5_3V3S5 1.8V/1.5V/1.2V/1.05V Rails PP3V3_S5 MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.8V MAKE_BASE=TRUE D 3.3V Rails PP1V05_SUS =PP1V05_SUS_LDO 71 MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V MAKE_BASE=TRUE 41 57 61 62 Chipset "VCore" Rails =PP1V05_SUS_PCH_JTAG 77 23 69 =PPVCORE_S0_CPU_REG PPVCORE_S0_CPU 50 51 =PPCPUVCCIO_S0_REG 70 PP1V05_S0 36 52 39 39 40 35 30 XW0800 SM 71 41 39 XW0801 SM 16 22 MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1V MAKE_BASE=TRUE ? mA 74 16 17 18 19 30 22 20 22 20 22 20 22 20 22 22 20 73 24 24 48 48 48 41 54 MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM VOLTAGE=1.25V MAKE_BASE=TRUE 49 =PPVCORE_S0_CPU =PPCPUVCORE_S0_VSENSE =PP1V05_S0_CPU_VCCIO =PPVCCIO_S0_CPUIMVP =PPVCCIO_S0_XDP =PPVCCIO_S0_SMC =PP1V05_S0_FWPWRCTL =PP1V05_FW_P1V0FWFET =PP1V05_S0_VMON =PP1V05_S0_P1V05T29FET 12 14 B 49 10 12 14 68 23 69 =PPVCORE_S0_AXG_REG PPVCORE_S0_AXG MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V MAKE_BASE=TRUE 46 39 39 =PPVCORE_S0_CPU_VCCAXG =PPAXGVCORE_S0_VSENSE 73 12 15 49 35 PP1V05_S0_PCH MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1V MAKE_BASE=TRUE 15 12 =PP1V05_S0_PCH_VCCIO_PLLPCIE =PP1V05_S0_PCH =PP1V05_S0_PCH_VCCIO =PP1V05_S0_PCH_VCCIO_PCIE =PP1V05_S0_PCH_VCCIO_SATA =PP1V05_S0_PCH_VCCASW =PP1V05_S0_PCH_VCCIO_USB =PP1V05_S0_PCH_VCC_CORE =PP1V05_S0_PCH_VCCIO_CLK =PP1V05_S0_PCH_VCCDIFFCLK =PP1V05_S0_PCH_VCCSSC =PP1V05_S0_PCH_V_PROC_IO =PP1V05_S0_PCH_VCCIO_PLLUSB =PP1V05_S0_PCH_VCC_DMI =PP1V05_S0_PCH_VCCIO_PLLFDI =PP1V05_S0_PCH_VCCDMI_FDI =PP1V5_S3_CPU_VCCDQ PP1V5_S3_CPU_VCCDQ MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.5V MAKE_BASE=TRUE 20 16 22 20 22 14 12 =PP1V05_S0_CPU_VCCPQE PP1V05_S0_CPU_VCCPQE MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V MAKE_BASE=TRUE 17 16 20 22 20 22 20 22 14 12 =PP1V8_S0_CPU_VCCPLL_R PP1V8_S0_CPU_VCCPLL_R MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.8V MAKE_BASE=TRUE 20 22 20 22 16 20 22 20 22 20 22 20 20 22 20 20 SYNC_MASTER=K90I_MLB SYNC_DATE=02/15/2011 PAGE TITLE Power Aliases 73 27 DRAWING NUMBER 29 35 Apple Inc ENET Rails 71 73 =PP3V3_ENET_FET PP3V3_ENET MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V MAKE_BASE=TRUE 50 75 49 23 24 36 71 24 24 48 R NOTICE OF PROPRIETARY PROPERTY: =PP3V3_ENET_PHY =PP3V3_ENET_SYSCLK =PPVDDIO_ENET_CLK 71 051-9058 REVISION THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED 6.0.0 BRANCH PAGE OF 109 SHEET OF 86 SIZE D A CPU signals 9 HEATSINK STANDOFFS 26 MEMVTT_EN =DDRVTT_EN 26 67 MAKE_BASE=TRUE Z0902 DP_EXTA_ML_C_P 81 75 STDOFF-4.5OD.98H-1.1-3.48-TH =PEG_R2D_C_P =PEG_R2D_C_N =PEG_D2R_P =PEG_D2R_N DP_EXTA_ML_C_N 81 75 33 81 17 33 81 17 =PP3V3_S0_DP_DDC TP_DP_IG_B_MLN 17 DPA_IG_AUX_CH_P 17 DPA_IG_AUX_CH_N 17 R0920 R0921 R0922 R0923 17 2.2K 2.2K 2.2K 2.2K 17 TP_DP_IG_C_MLP TP_DP_IG_C_MLN DPB_IG_AUX_CH_P DPB_IG_AUX_CH_N 17 TP_DP_IG_D_HPD MAKE_BASE=TRUE DP_EXTA_AUXCH_C_N 81 75 17 D 5% 1/16W MF-LF 402 MAKE_BASE=TRUE Z0904 DP_T29SNK0_HPD 33 MAKE_BASE=TRUE 17 DP_EXTA_AUXCH_C_P DPB_IG_HPD 33 81 MAKE_BASE=TRUE 81 75 T29 DP Ports 33 81 MAKE_BASE=TRUE TP_DP_IG_B_MLP MAKE_BASE=TRUE PCIE_T29_R2D_C_P MAKE_BASE=TRUE PCIE_T29_R2D_C_N MAKE_BASE=TRUE PCIE_T29_D2R_P MAKE_BASE=TRUE PCIE_T29_D2R_N FAN STANDOFF 5% 1/16W MF-LF 402 5% 1/16W MF-LF 402 5% 1/16W MF-LF 402 DP_T29SNK0_ML_C_P DP_T29SNK0_ML_C_N DP_T29SNK0_AUXCH_C_P MAKE_BASE=TRUE DP_T29SNK0_AUXCH_C_N 33 83 MAKE_BASE=TRUE 33 83 MAKE_BASE=TRUE 33 83 33 83 MAKE_BASE=TRUE DP_T29SNK1_HPD 33 MAKE_BASE=TRUE D STDOFF-4.5OD.98H-1.1-3.48-TH Z0905 STDOFF-4.5OD.98H-1.1-3.48-TH FW_PLUG_DET_L FW_PME_L 19 39 =FW_PME_L 38 39 17 MAKE_BASE=TRUE 17 BELOW CPU FW643_WAKE_L 39 TP_DP_IG_C_CTRL_CLK TP_DP_IG_C_CTRL_DATA TP_DP_IG_D_CTRL_CLK TP_DP_IG_D_CTRL_DATA DPB_IG_DDC_CLK DPB_IG_DDC_DATA DP_IG_D_CTRL_CLK MAKE_BASE=TRUE DP_IG_D_CTRL_DATA 16 16 16 16 LEFT OF CPU 81 16 MLB MOUNTING (TO C BRACKET) SCREW HOLES OMIT 81 16 NC_PCIE_EXCARD_D2RN TRUE MAKE_BASE=TRUE NC_PCIE_EXCARD_D2RP TRUE MAKE_BASE=TRUE NC_PCIE_EXCARD_R2D_CN TRUE MAKE_BASE=TRUE NC_PCIE_EXCARD_R2D_CP TRUE MAKE_BASE=TRUE NC_PCIE_CLK100M_EXCARDN TRUE MAKE_BASE=TRUE NC_PCIE_CLK100M_EXCARDP TRUE MAKE_BASE=TRUE PCIE_PCH_D2R_N PCIE_PCH_D2R_P PCIE_PCH_R2D_C_N PCIE_PCH_R2D_C_P PEG_CLK100M_P PEG_CLK100M_N 3R2P5 81 16 81 16 MAKE_BASE=TRUE MAKE_BASE=TRUE R0925 2.2K 2.2K 5% 1/16W MF-LF 402 C Z0908 Z0909 Z0910 3R2P5 3R2P5 3R2P5 1 17 17 NC_LVDS_IG_B_DATAP DP_EXTA_HPD DPA_IG_HPD 17 MAKE_BASE=TRUE OMIT OMIT Z0911 Z0912 3R2P5 3R2P5 LVDS_IG_B_CLK_N 17 80 5% 1/16W MF-LF 402 NC_LVDS_IG_A_DATAN MAKE_BASE=TRUE 74 17 80 LVDS_IG_A_DATA_P 17 80 NO_TEST=TRUE MAKE_BASE=TRUE 17 80 LVDS_IG_B_DATA_N NO_TEST=TRUE NC_LVDS_IG_A_DATAP LVDS_IG_A_DATA_N 17 80 LVDS_IG_DDC_CLK 17 LVDS_IG_DDC_DATA 17 LVDS_IG_BKL_PWM 17 LVDS_IG_PANEL_PWR 17 LVDS_IG_BKL_ON 17 USBHUB_DN1_N 25 NO_TEST=TRUE LVDS_DDC_CLK MAKE_BASE=TRUE PPBUS_SW_LCDBKLT_PWR LVDS_DDC_DATA MAKE_BASE=TRUE 77 PPBUS_SW_BKL LCD_BKLT_PWM MAKE_BASE=TRUE MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.375 MM VOLTAGE=12.6V MAKE_BASE=TRUE 5% 1/16W MF-LF 402 NC_PCH_CLKOUT_DPN TRUE MAKE_BASE=TRUE TP_PCH_CLKOUT_DPP 16 17 80 NO_TEST=TRUE 100K MAKE_BASE=TRUE TP_PCH_CLKOUT_DPN LVDS_IG_B_CLK_P LVDS_IG_B_DATA_P NC_LVDS_IG_B_DATAN R09081 77 16 TP_LVDS_IG_B_CLKN MAKE_BASE=TRUE MAKE_BASE=TRUE 74 TP_LVDS_IG_B_CLKP DPA_IG_DDC_CLK R0910 OMIT NO_TEST=TRUE DPA_IG_DDC_DATA MAKE_BASE=TRUE OMIT 33 83 BCM57765_CE_L_MS_INS_L MAKE_BASE=TRUE DP_EXTA_DDC_DATA MAKE_BASE=TRUE MLB MOUNTING (TO TOPCASE) SCREW HOLES OMIT 33 83 MAKE_BASE=TRUE MAKE_BASE=TRUE 75 NC_PCIE_PCH_D2RN NC_PCIE_PCH_D2RP NC_PCIE_PCH_R2D_CN NC_PCIE_PCH_R2D_CP NC_PEG_CLK100MP NC_PEG_CLK100MN TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE DP_EXTA_DDC_CLK 75 33 83 33 83 MAKE_BASE=TRUE MAKE_BASE=TRUE R0924 5% 1/16W MF-LF 402 75 Z0907 3R2P5 DP_T29SNK1_ML_C_P DP_T29SNK1_ML_C_N DP_T29SNK1_AUXCH_C_P MAKE_BASE=TRUE DP_T29SNK1_AUXCH_C_N MAKE_BASE=TRUE NC_BCM57765_CE_L_MS_INS_L OMIT Z0906 TP_DP_IG_D_MLP TP_DP_IG_D_MLN TP_DP_IG_D_AUXP TP_DP_IG_D_AUXN =PP3V3_S0_DP_DDC SMC_EXCARD_PWR_EN PCIE_EXCARD_D2R_N PCIE_EXCARD_D2R_P PCIE_EXCARD_R2D_C_N PCIE_EXCARD_R2D_C_P PCIE_CLK100M_EXCARD_N PCIE_CLK100M_EXCARD_P 17 17 MAKE_BASE=TRUE 17 MAKE_BASE=TRUE TP_SMC_EXCARD_PWR_EN Z0920 17 17 MAKE_BASE=TRUE MAKE_BASE=TRUE STDOFF-4.5OD.98H-1.1-3.48-TH 17 MAKE_BASE=TRUE =PPBUS_SW_BKL 74 LCD_IG_PWR_EN MAKE_BASE=TRUE 77 77 LCD_BKLT_EN C MAKE_BASE=TRUE NC_PCH_CLKOUT_DPP TRUE MAKE_BASE=TRUE NC_CPU_VCCIO_SEL MAKE_BASE=TRUE CPU_VCCIO_SEL 12 78 NO_TEST=TRUE USB Signals NC_USB3_EXTD_TXN MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE T29BST:N MAKE_BASE=TRUE USB3_EXTD_RX_N 18 80 53 USB3_EXTD_RX_P 14 12 18 80 53 =PP1V05_S0_CPU_VCCPQE 80 44 R0940 B ZS0900 ZS0901 ZS0902 ZS0910 1.4DIA-SHORT-SILVER-K99 1.4DIA-SHORT-SILVER-K99 1.4DIA-SHORT-SILVER-K99 1.4DIA-SHORT-SILVER-K99 SM SM SM SM DP_A_BIAS0 10 DP_A_BIAS2 75 10 EMI IO (SHORT) POGO PINS 1 80 45 USB_TPAD_P USB_IR_N USB_IR_P C0960 C0962 0.01UF 0.01UF 10% 10V X5R-CERM 0201 C0964 DPLL_REF_CLK_P DPLL_REF_CLK_N 5% 1/16W MF-LF 402 1.4DIA-SHORT-SILVER-K99 1.4DIA-SHORT-SILVER-K99 SM 80 45 USB_SMC_P NC_USB_EXTD_EHCIN MAKE_BASE=TRUE MAKE_BASE=TRUE R0941 MAKE_BASE=TRUE 1K NC_USB_EXTCN MAKE_BASE=TRUE MAKE_BASE=TRUE T29_A_BIAS_R2DP1 75 T29_A_BIAS_R2DN0 75 PM_SLP_S3_L MAKE_BASE=TRUE 76 76 75 51 1/20W 51 201 1/20W MF VOLTAGE=3.3V ZS0906 ZS0907 POGO-2.0OD-3.5H-K86-K87 POGO-2.0OD-3.5H-K86-K87 POGO-2.0OD-3.5H-K86-K87 POGO-2.0OD-3.5H-K86-K87 SM SM SM SM 1 R0973 201 1 MF VOLTAGE=3.3V ZS0922 ZS0923 ZS0924 POGO-2.0OD-3.5H-K86-K87 POGO-2.0OD-3.5H-K86-K87 POGO-2.0OD-3.5H-K86-K87 POGO-2.0OD-3.5H-K86-K87 POGO-2.0OD-3.5H-K86-K87 SM SM SM SM SM NO STUFF NO STUFF NO STUFF NO STUFF USB_EXTD_XHCI_P 18 80 CPU_THERMD_P 85 CPU_THERMD_N 85 MAKE_BASE=TRUE CPU_VTTSELECT 5% T29_A_BIAS_D2RN1 MF VOLTAGE=3.3V OUT T29_D2R_P 83 33 OUT T29_D2R_N 83 33 IN T29_R2D_C_P 83 33 IN T29_R2D_C_N 33 IN 33 IN T29_LSEO T29_LSEO 83 33 C0973 Digital Ground NC_T29_D2RP MAKE_BASE=TRUE NO_TEST=TRUE NC_T29_D2RN MAKE_BASE=TRUE GND NO_TEST=TRUE 0.01UF 10% 10V X5R-CERM 0201 0.01UF ZS0921 TP_CPU_THERMDN T29_A_BIAS_D2RP1 5% C0972 ZS0920 51 1/20W 51 TALL POGO PINS close to DIMM conn 18 80 MAKE_BASE=TRUE 201 1/20W 18 USB_EXTD_XHCI_N Unused T29 Ports R0972 A 18 USB3_EXTC_RX_P MAKE_BASE=TRUE 10% 10V X5R-CERM 0201 TP_CPU_VTT_SELECT ZS0905 USB3_EXTC_RX_N B NO_TEST=TRUE TP_CPU_THERMDP 0.01UF 10% 10V X5R-CERM 0201 EMI TALL POGO PINS MAKE_BASE=TRUE C0971 1 0.01UF ZS0904 18 NO_TEST=TRUE NC_USB_EXTD_XHCIP VOLTAGE=3.3V USB3_EXTC_TX_P T29_A_BIAS_R2DP0 5% C0970 T29_A_BIAS_R2DN1 18 NO_TEST=TRUE MAKE_BASE=TRUE MF 18 80 USB3_EXTC_TX_N NO_TEST=TRUE NC_USB_EXTD_XHCIN 5% 18 80 USB_EXTC_P NO_TEST=TRUE NC_USB3_EXTC_RXP MAKE_BASE=TRUE 18 USB_EXTC_N NO_TEST=TRUE MAKE_BASE=TRUE =TBT_S0_EN 18 USB_EXTD_EHCI_P NO_TEST=TRUE NC_USB3_EXTC_TXN MAKE_BASE=TRUE 73 45 26 17 NO_TEST=TRUE USB_EXTD_EHCI_N NO_TEST=TRUE NC_USB_EXTCP 5% 1/16W MF-LF 402 NO_TEST=TRUE NO_TEST=TRUE NC_USB3_EXTC_RXN R0970 25 NO_TEST=TRUE NC_USB3_EXTC_TXP T29_A_BIAS 25 USBHUB_DN2_P MAKE_BASE=TRUE NC_USB_EXTD_EHCIP 10% 10V X5R-CERM 0201 R0971 201 25 USBHUB_DN2_N NC_USB_SMCP DPLL_REF_CLKP 0.01UF 10% 10V X5R-CERM 0201 SM USBHUB_DN3_P NC_USB_SMCN MAKE_BASE=TRUE DPLL_REF_CLKN USB_SMC_N MAKE_BASE=TRUE ZS0909 25 MAKE_BASE=TRUE ZS0903 25 USBHUB_DN3_N MAKE_BASE=TRUE Unused eDP CLK 75 USB_TPAD_N MAKE_BASE=TRUE 1K T29_A_BIAS USBHUB_DN1_P MAKE_BASE=TRUE 5% 1/8W MF-LF 805 76 75 USB_BT_P MAKE_BASE=TRUE NO_TEST=TRUE 35 USB_BT_N MAKE_BASE=TRUE 80 44 =PP15V_T29_REG 80 32 NO_TEST=TRUE NC_USB3_EXTD_RXP R0960 80 32 18 NO_TEST=TRUE NC_USB3_EXTD_RXN =PPVIN_SW_T29BST 18 USB3_EXTD_TX_P MAKE_BASE=TRUE NC_USB3_EXTD_TXP 35 USB3_EXTD_TX_N NO_TEST=TRUE 10% 10V X5R-CERM 0201 MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM VOLTAGE=0V NC_T29_R2D_CP MAKE_BASE=TRUE NO_TEST=TRUE NC_T29_R2D_CN MAKE_BASE=TRUE NO_TEST=TRUE T29_LSOE MAKE_BASE=TRUE T29_LSOE MAKE_BASE=TRUE OUT 33 OUT 33 SYNC_MASTER=K90I_MLB SYNC_DATE=02/15/2011 PAGE TITLE Signal Aliases DRAWING NUMBER NO STUFF TBT JTAG Apple Inc Unused PGOOD signal 051-9058 REVISION R 23 19 IN 19 IN 19 OUT JTAG_ISP_TCK JTAG_TBT_TCK OUT 33 JTAG_TBT_TDI OUT 19 33 MAKE_BASE=TRUE JTAG_ISP_TDI MAKE_BASE=TRUE JTAG_ISP_TDO JTAG_TBT_TDO MAKE_BASE=TRUE TP_P1V5S3RS0_RAMP_DONE P1V5S3RS0_RAMP_DONE IN 72 DDRREG_PGOOD IN 67 MAKE_BASE=TRUE TP_DDRREG_PGOOD MAKE_BASE=TRUE IN 33 NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED 6.0.0 BRANCH PAGE OF 109 SHEET OF 86 SIZE D A NOTE: OMIT_TABLE 78 IN 78 17 IN 78 17 IN 78 17 IN 78 17 OUT 78 17 OUT 78 17 OUT 78 17 OUT 78 17 OUT 78 17 OUT 78 17 OUT 78 17 OUT 78 17 OUT 78 17 OUT 78 17 OUT 78 17 OUT 78 17 OUT 78 17 OUT 78 17 OUT 78 17 C 14 12 10 OUT 78 17 OUT 78 17 OUT 24.9 DMI_RX_0 DMI_RX_1 DMI_RX_2 DMI_RX_3 DMI_N2S_N DMI_N2S_N DMI_N2S_N DMI_N2S_N K1 M8 N4 R2 FDI_DATA_N FDI_DATA_N FDI_DATA_N FDI_DATA_N W6 V4 Y2 AC9 FDI_DATA_P FDI_DATA_P FDI_DATA_P FDI_DATA_P U6 W10 W3 AA7 FDI0_TX_0 FDI0_TX_1 FDI0_TX_2 FDI0_TX_3 FDI_DATA_P FDI_DATA_P FDI_DATA_P FDI_DATA_P W7 T4 AA3 AC8 FDI1_TX_0 FDI1_TX_1 FDI1_TX_2 FDI1_TX_3 OUT OUT 78 17 OUT 78 17 OUT 78 17 OUT 78 17 IN 78 17 IN FDI_FSYNC FDI_FSYNC 78 17 IN FDI_INT IN 17 IN 78 AA11 AC12 U11 FDI_LSYNC FDI_LSYNC EDP_COMP EDP_HPD FDI0_TX_0* FDI0_TX_1* FDI0_TX_2* FDI0_TX_3* FDI1_TX_0* FDI1_TX_1* FDI1_TX_2* FDI1_TX_3* FDI0_FSYNC FDI1_FSYNC FDI_INT AA10 AG8 FDI0_LSYNC FDI1_LSYNC AD2 AF3 EDP_ICOMPO EDP_COMPIO PLACE_NEAR=U1000.AF3:12.7MM AG11 BGA (1 OF 9) DMI_TX_0 DMI_TX_1 DMI_TX_2 DMI_TX_3 U7 W11 W1 AA6 78 17 17 K3 M7 P4 T3 IVY-BRIDGE 2C-35W DMI_TX_0* DMI_TX_1* DMI_TX_2* DMI_TX_3* FDI_DATA_N FDI_DATA_N FDI_DATA_N FDI_DATA_N 78 17 1% 1/16W MF-LF 402 N3 P7 P3 P11 DMI_N2S_P DMI_N2S_P DMI_N2S_P DMI_N2S_P OUT 78 17 =PP1V05_S0_CPU_VCCIO 78 R1030 78 IN 78 17 DMI_S2N_P DMI_S2N_P DMI_S2N_P DMI_S2N_P EDP_HPD EDP R1031 10K 6 1% 1/16W MF-LF 402 TP_EDP_AUX_N TP_EDP_AUX_P AG4 AF4 PLACE_NEAR=U1000.AG11:12.7MM 6 6 6 B PEG_ICOMPI G3 PEG_ICOMPO G1 PEG_RCOMPO G4 PCI EXPRESS BASED INTERFACE SIGNALS IN 78 17 U1000 DMI 78 17 DMI_RX_0* DMI_RX_1* DMI_RX_2* DMI_RX_3* INTEL FLEXIBLE DISPLAY INTERFACE SIGNALS IN M2 P6 P1 P10 EMBEDDED DISPLAY PORT D IN 78 17 DMI_S2N_N DMI_S2N_N DMI_S2N_N DMI_S2N_N EDP_AUX* EDP_AUX TP_EDP_TX_N TP_EDP_TX_N TP_EDP_TX_N TP_EDP_TX_N AC3 AC4 AE11 AE7 EDP_TX_0* EDP_TX_1* EDP_TX_2* EDP_TX_3* TP_EDP_TX_P TP_EDP_TX_P TP_EDP_TX_P TP_EDP_TX_P AC1 AA4 AE10 AE6 EDP_TX_0 EDP_TX_1 EDP_TX_2 EDP_TX_3 Intel Doc 467283 ChiefRiver Platform design guild rev0.71 section 2.2.12 recommendation NOTE: eDP_COMPIO and eDP_ICOMPO can not be left floating even if internal Graphics is disabled since they are shared with other interfaces NOTE: The EDP_HPD processor input is a low voltage active low signal Therefore, an inverting level shifter is required on the motherboard to convert the active high signal from Embedded DisplayPort sink device to low voltage signals for the processor (refer to latest Processor EDS for DC specifications) If HPD is disabled while eDP interface is still enabled, connect it to CPU VCCIo via a 10-kOhm pull-up resistor on the motherboard This signal can be left as no-connect if entire eDP interface is disabled 78 23 78 23 78 23 78 23 78 23 23 CPU_CFG CPU_CFG CPU_CFG CPU_CFG CPU_CFG 78 23 NOSTUFF R1044 R1045 1K 1K 5% 5% 5% 1/20W MF 201 201 1/20W MF CRITICAL =PP1V05_S0_CPU_VCCIO 1% 1/16W MF-LF 402 =PEG_D2R_N =PEG_D2R_N =PEG_D2R_N =PEG_D2R_N =PEG_D2R_N =PEG_D2R_N =PEG_D2R_N =PEG_D2R_N =PEG_D2R_N =PEG_D2R_N =PEG_D2R_N =PEG_D2R_N =PEG_D2R_N =PEG_D2R_N =PEG_D2R_N =PEG_D2R_N PEG_RX_0* PEG_RX_1* PEG_RX_2* PEG_RX_3* PEG_RX_4* PEG_RX_5* PEG_RX_6* PEG_RX_7* PEG_RX_8* PEG_RX_9* PEG_RX_10* PEG_RX_11* PEG_RX_12* PEG_RX_13* PEG_RX_14* PEG_RX_15* H22 J21 B22 D21 A19 D17 B14 D13 A11 B10 G8 A8 B6 H8 E5 K7 PEG_RX_0 PEG_RX_1 PEG_RX_2 PEG_RX_3 PEG_RX_4 PEG_RX_5 PEG_RX_6 PEG_RX_7 PEG_RX_8 PEG_RX_9 PEG_RX_10 PEG_RX_11 PEG_RX_12 PEG_RX_13 PEG_RX_14 PEG_RX_15 K22 K19 C21 D19 C19 D16 C13 D12 C11 C9 F8 C8 C5 H6 F6 K6 =PEG_D2R_P =PEG_D2R_P =PEG_D2R_P =PEG_D2R_P =PEG_D2R_P =PEG_D2R_P =PEG_D2R_P =PEG_D2R_P =PEG_D2R_P =PEG_D2R_P =PEG_D2R_P =PEG_D2R_P =PEG_D2R_P =PEG_D2R_P =PEG_D2R_P =PEG_D2R_P PEG_TX_0* PEG_TX_1* PEG_TX_2* PEG_TX_3* PEG_TX_4* PEG_TX_5* PEG_TX_6* PEG_TX_7* PEG_TX_8* PEG_TX_9* PEG_TX_10* PEG_TX_11* PEG_TX_12* PEG_TX_13* PEG_TX_14* PEG_TX_15* G22 C23 D23 F21 H19 C17 K15 F17 F14 A15 J14 H13 M10 F10 D9 J4 =PEG_R2D_C_N =PEG_R2D_C_N =PEG_R2D_C_N =PEG_R2D_C_N =PEG_R2D_C_N =PEG_R2D_C_N =PEG_R2D_C_N =PEG_R2D_C_N =PEG_R2D_C_N =PEG_R2D_C_N =PEG_R2D_C_N =PEG_R2D_C_N =PEG_R2D_C_N =PEG_R2D_C_N =PEG_R2D_C_N =PEG_R2D_C_N PEG_TX_0 PEG_TX_1 PEG_TX_2 PEG_TX_3 PEG_TX_4 PEG_TX_5 PEG_TX_6 PEG_TX_7 PEG_TX_8 PEG_TX_9 PEG_TX_10 PEG_TX_11 PEG_TX_12 PEG_TX_13 PEG_TX_14 PEG_TX_15 F22 A23 D24 E21 G19 B18 K17 G17 E14 C15 K13 G13 K10 G10 D8 K4 =PEG_R2D_C_P =PEG_R2D_C_P =PEG_R2D_C_P =PEG_R2D_C_P =PEG_R2D_C_P =PEG_R2D_C_P =PEG_R2D_C_P =PEG_R2D_C_P =PEG_R2D_C_P =PEG_R2D_C_P =PEG_R2D_C_P =PEG_R2D_C_P =PEG_R2D_C_P =PEG_R2D_C_P =PEG_R2D_C_P =PEG_R2D_C_P IN IN IN IN IN IN IN IN IN IN IN R1064 IN 49.9 49.9 IN IN 1% 1/16W MF-LF 402 1% 1/16W MF-LF 402 IN IN IN IN IN Note VOLTAGE=1.05V IN Note VOLTAGE=0V IN IN IN IN IN IN IN IN IN IN IN IN OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT PLACE_NEAR=U1000.H43:50.8MM PLACE_SIDE=BOTTOM =PPVCORE_S0_CPU NOSTUFF R1070 PLACE_NEAR=U1000.H45:50.8MM PLACE_SIDE=BOTTOM Note VOLTAGE=1.25V Note VOLTAGE=0V NOSTUFF 78 23 IN 78 23 IN 78 23 IN 78 23 IN 78 23 IN 78 23 IN 78 23 IN 78 23 IN 78 23 IN 78 23 IN 78 23 IN 78 23 IN 12 14 =PPVCORE_S0_CPU_VCCAXG NOSTUFF MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=0.75V 10 12 14 12 15 23 78 78 23 IN 78 23 IN 78 23 IN 23 IN 23 IN IN B50 C51 B54 D53 A51 C53 C55 H49 A55 H51 K49 K53 F53 G53 L51 F51 D52 L53 CPU_CFG CPU_CFG CPU_CFG CPU_CFG CPU_CFG CPU_CFG CPU_CFG CPU_CFG CPU_CFG CPU_CFG CPU_CFG CPU_CFG CPU_CFG CPU_CFG CPU_CFG CPU_CFG CPU_CFG CPU_CFG CFG_0 CFG_1 CFG_2 CFG_3 CFG_4 CFG_5 CFG_6 CFG_7 CFG_8 CFG_9 CFG_10 CFG_11 CFG_12 CFG_13 CFG_14 CFG_15 CFG_16 CFG_17 SA_DIMM_VREFDQ BE7 SB_DIMM_VREFDQ BG7 U1000 BGA (5 OF 9) RESERVED CPU_VCC_VALSENSE_P CPU_VCC_VALSENSE_N H43 VCC_VAL_SENSE K43 VSS_VAL_SENSE CPU_AXG_VALSENSE_P CPU_AXG_VALSENSE_N H45 VAXG_VAL_SENSE K45 VSSAXG_VAL_SENSE TP_CPU_VCC_DIE_SENSE F48 VCC_DIE_SENSE PPCPU_MEM_VREFDQ_A PPCPU_MEM_VREFDQ_B RSVD_30 RSVD_31 RSVD_32 RSVD_33 N42 NC L42 NC L45 NC L47 RSVD_34 RSVD_35 RSVD_36 RSVD_37 RSVD_38 M13 NC M14 NC U14 NC W14 NC P13 OUT 31 OUT 31 MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=0.75V D NC NC RSVD_39 AT49NC RSVD_40 K24 NC RSVD_41 RSVD_42 RSVD_43 RSVD_44 AH2 NC AG13 NC AM14 NC AM15 NC RSVD_45 N50 NC NOSTUFF R10651 R1071 49.9 49.9 1% 1/16W MF-LF 402 1% 1/16W MF-LF 402 85 OUT 85 OUT H48 RSVD_6 K48 RSVD_7 CPU_THERMD_P CPU_THERMD_N NOTE: Intel does not recommend to use BA19 this alnalog sense due to accuracy concern.NC AV19 NC AT21 NC BB21 NC BB19 PLACE_NEAR=U1000.K43:50.8MM NC PLACE_SIDE=BOTTOM AY21 NC BA22 NOTE: Intel validation sense lines per NC AY22 doc 439028 rev1.0 HR_PPDG sections 6.2.1 and 6.3.1 NC AU19 NC AU21 NC BD21 NC BD22 NC BD25 NC BD26 NC BG22 NC BE22 NC BG26 NC BE26 NC BF23 NC BE24 2 PLACE_NEAR=U1000.K45:50.8MM PLACE_SIDE=BOTTOM NC RSVD_8 RSVD_9 RSVD_10 RSVD_11 RSVD_12 RSVD_13 RSVD_14 RSVD_15 RSVD_16 RSVD_17 RSVD_18 RSVD_19 RSVD_20 RSVD_21 RSVD_22 RSVD_23 RSVD_24 RSVD_25 RSVD_26 RSVD_27 DC_TEST_A4 DC_TEST_C4 DC_TEST_D3 DC_TEST_D1 DC_TEST_A58 DC_TEST_A59 DC_TEST_C59 DC_TEST_A61 DC_TEST_C61 DC_TEST_D61 DC_TEST_BD61 DC_TEST_BE61 DC_TEST_BE59 DC_TEST_BG61 DC_TEST_BG59 DC_TEST_BG58 DC_TEST_BG4 DC_TEST_BG3 DC_TEST_BE3 DC_TEST_BG1 DC_TEST_BE1 DC_TEST_BD1 A4 TP_CPU_DC_TEST_A4 C4 CPU_DC_TEST_C4_D3 D3 D1 TP_CPU_DC_TEST_D1 A58 TP_CPU_DC_TEST_A58 A59 CPU_DC_TEST_C59_A59 C59 A61 CPU_DC_TEST_C61_A61 C61 D61 TP_CPU_DC_TEST_D61 BD61 TP_CPU_DC_TEST_BD61 BE61 CPU_DC_TEST_BE59_BE61 BE59 BG61 CPU_DC_TEST_BG59_BG61 BG59 BG58 TP_CPU_DC_TEST_BG58 BG4 TP_CPU_DC_TEST_BG4 BG3 CPU_DC_TEST_C4_BE3_BG3 BE3 BG1 CPU_DC_TEST_C4_BE1_BG1 BE1 BD1 TP_CPU_DC_TEST_BD1 C B CPU_CFG CPU_CFG CPU_CFG CPU_CFG 78 23 1K 1/20W A OMIT_TABLE 24.9 PLACE_NEAR=U1000.G3:12.7MM 78 23 EDP R1042 CPU_PEG_COMP Intel provides an internal pull-up OF 5-15k to VCCIO on all CFG signals R1010 CRITICAL 78 17 2C-35W IVY-BRIDGE 201 NOSTUFF R1046 R1047 1K 1K 1K 1K 1K 1K 5% 5% 5% 5% 5% 5% 1/20W MF NOSTUFF 201 R1040 1/20W MF NOSTUFF 1/20W MF 201 NOSTUFF NOSTUFF R1041 R1043 1/20W MF 201 201 R1049 1/20W MF NOSTUFF 1/20W MF 201 MF 201 2 SYNC_MASTER=MASTER SYNC_DATE=02/15/2011 PAGE TITLE CPU DMI/PEG/FDI/RSVD DRAWING NUMBER These can be Placed close to J2500 and Only for debug access Apple Inc FOR IVYBRIDGE PROCESSOR CFG [7] :PEG DEFER TRAINING R = (DEFAULT) IMMEDIATELY AFTER xxRESETB CFG [6:5] :PCIE BIFURCATION 11 = X16 (DEFAULT) CFG [4] :eDP ENABLE/DISABLE = DISABLED CFG [3] :PCIE x4 LANE REVERSAL = NORMAL OPERATION = LANES REVERSED CFG [2] :PCIE x16 LANE REVERSAL = NORMAL OPERATION = LANES REVERSED 051-9058 10 = X8 NOTICE OF PROPRIETARY PROPERTY: = WAIT FOR BIOS 01 = RSVD 00 = X8, X4, X4 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED = ENABLED SIZE D REVISION 6.0.0 BRANCH PAGE 10 OF 109 SHEET OF 86 A D D 14 12 10 OMIT_TABLE =PP1V05_S0_CPU_VCCIO CRITICAL U1000 1 R1102 1K 5% 5% 1/20W 1/20W MF 1/20W 2 201 MF NC 201 19 OUT C 78 45 78 46 19 R1103 CPU_PROCHOT_L 78 46 19 78 26 17 IN 78 17 R1121 PM_MEM_PWRGD 130 78 23 19 CPU_PECI A48 PECI C45 PROCHOT* PM_THRMTRIP_L D45 THERMTRIP* IN PM_SYNC C48 PM_SYNC IN CPU_PWRGD B46 UNCOREPWRGOOD PM_MEM_PWRGD_R 1% 1/16W MF-LF 402 BE45 SM_DRAMPWROK PLT_RESET_LS1V1_L 26 OUT D44 RESET* =MEM_RESET_L AT30 SM_DRAMRST* CPU_SM_RCOMP CPU_SM_RCOMP CPU_SM_RCOMP 78 78 78 14 12 10 BF44 SM_RCOMP_0 BE43 SM_RCOMP_1 BG43 SM_RCOMP_2 =PP1V05_S0_CPU_VCCIO B R1126 1% 1/16W MF-LF 402 IN CPU_RESET_L 2 R1112 140 75 24 23 16 78 IN 16 78 DPLL_REF_CLK AG3 DPLL_REF_CLK* AG1 DPLL_REF_CLK_P DPLL_REF_CLK_N BCLK_ITP N59 BCLK_ITP* N58 IN IN ITPCPU_CLK100M_P ITPCPU_CLK100M_N IN 16 78 IN 16 78 OUT 23 78 IN 23 78 IN 23 78 IN 23 78 IN 23 78 IN 23 78 (IPU) (IPU) PRDY* N53 PREQ* N55 XDP_CPU_PRDY_L XDP_CPU_PREQ_L C (IPU) (IPU) (IPU) TCK L56 TMS L55 TRST* J58 XDP_CPU_TCK XDP_CPU_TMS XDP_CPU_TRST_L (IPU) TDI M60 TDO L59 200 1% 1/16W MF-LF 402 OUT IN C49 CATERR* R1113 25.5 R1114 1% 1% 1/16W 1/16W 1/16W MF-LF MF-LF MF-LF 402 402 200 1% 402 JTAG & BPM R1120 CPU_CATERR_L CPU_PROCHOT_R_L 5% 1/20W MF 201 =PP1V5_S3_CPU_VCCDDR F49 PROC_SELECT* PWR MGMT 26 15 12 BI BI CPU_PROC_SEL_L C57 PROC_DETECT* DDR3 MISC 78 68 46 45 56 OUT DMI_CLK100M_CPU_P DMI_CLK100M_CPU_N 201 MF BCLK J3 BCLK* H2 BGA (2 OF 9) 1/20W MF 201 THERMAL 5% IVY-BRIDGE 2C-35W NOSTUFF 51 5% R1101 62 NOSTUFF R1104 1K CLOCKS NOSTUFF R1100 DBR* K58 (IPU) (IPU) (IPU) (IPU) (IPU) (IPU) (IPU) (IPU) BPM_0* BPM_1* BPM_2* BPM_3* BPM_4* BPM_5* BPM_6* BPM_7* XDP_CPU_TDI XDP_CPU_TDO OUT 23 78 XDP_DBRESET_L OUT 23 24 78 XDP_BPM_L XDP_BPM_L XDP_BPM_L XDP_BPM_L XDP_BPM_L XDP_BPM_L XDP_BPM_L XDP_BPM_L G58 E55 E59 G55 G59 H60 J59 J61 BI 23 78 BI 23 78 BI 23 78 BI 23 78 BI 23 BI 23 BI 23 BI 23 R1111 B 10K 5% 1/20W MF 201 R1125 43.2 1% 1/20W MF 201 A SYNC_MASTER=MASTER SYNC_DATE=02/15/2011 PAGE TITLE CPU CLOCK/MISC/JTAG DRAWING NUMBER Apple Inc 051-9058 R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED SIZE D REVISION 6.0.0 BRANCH PAGE 11 OF 109 SHEET 10 OF 86 A NO STUFF R7803 3.3V S0 FET 5% CRITICAL Q7830 1/10W SIA427DJ MF-LF 603 SC70-6L =PP3V3_S0_P3V3S0FET =PP3V3_S0_FET SIA427DJ D Q7800 CRITICAL S 3.3V S4 FET 3.3V S0 FET SC70-6L D Q7812 5% 1/16W MF-LF 402 G R7800 5.1K 3.3V S4 FET C7800 0.01UF P3V3S4_GATE 5% 1/16W MF-LF 402 SiA427 CHANNEL P-TYPE 8V/5V RDS(ON) 10% 16V X7R-CERM 0402 73 MOSFET IN G =P3V3S0_EN 91K S D MOSFET SiA427 CHANNEL P-TYPE 8V/5V C7830 RDS(ON) 0.01UF P3V3S0_SS 26 mOhm @1.8V LOADING 5% 1/16W MF-LF 402 3.2 A (EDP) 10% 16V X7R-CERM 0402 3.3V_SUS FET Q7820 26 mOhm @1.8V LOADING R7830 P3V3S0_EN_L 10% 16V X5R 402 P3V3S4_EN_L S =P3V3S4_EN 0.033UF 220K 5% 1/16W MF-LF 402 G IN C7809 R7802 D VESM 73 SOT563 Q7803 10% 16V X5R 402 =PP3V3_S4_FET 0.033UF 10K SSM6N37FEAPE SSM3K15AMFVAPE C7831 R7832 D G =PP3V3_S4_P3V3S4FET S D 7 CRITICAL 1.35 A (EDP) SIA427DJ SC70-6L D C7821 SOT563 CRITICAL Q7810 G SIA427DJ 73 72 0.01UF MOSFET SiA427 CHANNEL P-TYPE 8V/5V RDS(ON) 10% 16V X7R-CERM 0402 =PP5V_S5_P5VSUSFET C7841 LOADING 1.608 A (EDP) Q7822 R7842 D G 73 72 IN =P5V_3V3_SUS_EN 10% 16V X5R 402 5% 1/16W MF-LF 402 P5VSUS_EN_L S 0.033UF 220K SOT563 R7840 3.3K 0.01UF SiA427 CHANNEL RDS(ON) P-TYPE 8V/5V 16 mOhm @4.5V LOADING 100? mA (EDP) CRITICAL Q7860 DMP2018LFK DFN2563-6 =PP5V_S0_FET =PP5V_S3_P5VS0FET APN 376S0928 R7862 220K B SLG5AP020 TDFN ON CRITICAL SHDN* D G S PG NO STUFF 4.7UF 10% 6.3V X5R-CERM 603 CRITICAL D P1V5S0FET_GATE 5% 1/16W MF-LF 2402 Q7801 R7801 5% P1V5S0FET_GATE_R 1/16W MF-LF 402 SI7108DN G PWRPK-1212-8-HF P5V0S0_EN_L S =PP1V5_S3RS0_FET C7861 10% 16V X5R R7860 10K TPCP8102 CHANNEL P-TYPE B C7860 402 0.01UF P5V0S0_SS RDS(ON) 18 MOHM @4.5V LOADING 1.678 A (EDP) 5% 1/16W THRM PAD 402 Q7802 5.0V S0 FET MOSFET 0.033UF MF-LF GND VCC U7801 G D 1 20% 10V CERM 402 C7802 10% 16V X7R-CERM 0402 5.0V S0 FET =PP1V5_S3_P1V5S3RS0_FET 0.1UF P1V5CPU_EN MOSFET C7840 5% 1/16W MF-LF 402 =PP5V_S5_P1V5DDRFET C7801 IN 5V SUS FET P5VSUS_SS 1.5V S3/S0 FET 26 =PP5V_SUS_FET 31 mOhm @1.8V SSM6N37FEAPE SC70-6L C7810 P3V3S3_SS 5% 1/16W MF-LF 402 C CRITICAL D 100? mA (EDP) Q7840 G =P3V3S3_EN 5V_SUS FET 3.3V S3 FET S IN 47K LOADING SIA413DJ R7810 P3V3S3_EN_L S 26 mOhm @1.8V P-TYPE 8V/5V RDS(ON) 10% 16V X7R-CERM 0402 SOT563 73 10% 16V X5R 402 SiA427 CHANNEL SSM6N37FEAPE G C7811 0.033UF 5% 1/16W MF-LF 2402 5% 1/16W MF-LF 402 D =PP3V3_S3_FET G R7812 100K Q7812 D S =PP3V3_S3_P3V3S3FET C =P5V_3V3_SUS_EN MOSFET 0.01UF P3V3SUS_SS IN 3.3V SUS FET C7820 R7820 P3V3SUS_EN_L 12K S SC70-6L 10% 16V X5R 402 S 3.3V S3 FET 0.033UF 5% 1/16W MF-LF 402 Q7822 SSM6N37FEAPE =PP3V3_SUS_FET G R7822 100K D S =PP3V3_S5_P3V3SUSFET 10% 16V X7R-CERM 0402 D SSM3K15AMFVAPE 1.5V S3/S0 FET P1V5S3RS0_RAMP_DONE OUT MOSFET SI7108DN CHANNEL N-TYPE RDS(ON) mOhm @4.5V LOADING A (EDP) VESM 73 IN =P5VS0_EN G S A SYNC_MASTER=K90I_MLB SYNC_DATE=02/15/2011 PAGE TITLE Power FETs DRAWING NUMBER Apple Inc 051-9058 R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED SIZE D REVISION 6.0.0 BRANCH PAGE 78 OF 109 SHEET 72 OF 86 A S5 Rail Enables & PGOOD 73 73 10V CERM 402 VDD 343S0497 U7941 SMC_PM_G2_EN =PP3V3_S5_PWRCTL Threshold: ?? DLY > 10 ms S5PGOOD_DLY R7941 IN_A OUT_A* (IPD) (OD,IPU) OUT_A IN_B (OD,IPU) 2:1 + 1.3V - DLY_1C C7941 220PF P3V3S5_EN_L MAKE_BASE=TRUE C7942 Deep Sleep (S4) 66 10% 16V X5R 402 PM_SLP_S5_L Sleep (S3) =P3V3S5_EN_L OUT 0.033UF SMC_PM_G2_ENABLE Run (S0) PM_SLP_S4_L 1 1 0 Deep Sleep (S5) P3V3S5_EN_L_R NO STUFF MAKE_BASE=TRUE P5V3V3_REG_EN MAKE_BASE=TRUE =P5V3V3_REG_EN OUT Battery Off (G3Hot) 0 0 0 S5_PWRGD 45 32 26 17 PM_SLP_S4_L IN MAKE_BASE=TRUE C7970 R7911 10% 10V X5R-CERM 0201 S5_PWRGD (old name RSMRST_PWRGD) >SMC SMC >PM_DSW_PWRGD U7970 45 17 PM_SLP_S5_L 5% 1/16W MF-LF 402 PLACE_NEAR=Q7812.2:6mm G S IN P3V3_S4_EN =P3V3S4_EN MAKE_BASE=TRUE SOT891 SSM3K15AMFVAPE VESM P3V3S3_EN 72 OUT =TBTAPWRSW_EN 76 OUT S0 ENABLE IN =P3V3S3_EN OUT 72 =DDRREG_EN OUT 67 =USB_PWR_EN OUT 42 0.47UF 0.47UF 10% 6.3V CERM-X5R 402 10% 6.3V CERM-X5R 402 PLACE_NEAR=Q7812.2:6mm PLACE_NEAR=U7300.16:6mm 73 45 26 17 IN 100 PM_SLP_S3_L (PM_SLP_S3_R_L) PM_SLP_S3_R_L MAKE_BASE=TRUE 5% 1/16W MF-LF 402 2 5% 1/16W MF-LF 402 PLACE_NEAR=U7400.7:5mm C7910 C7912 R7978 SMC_S4_WAKESRC_EN 68 R7981 20K R7987 33K 5% 1/16W MF-LF 402 PLACE_NEAR=U7600.3:6mm 5% 1/16W MF-LF 402 R7988 R7986 5% 1/16W MF-LF 402 5.1K 39K 5% 1/16W MF-LF 402 PLACE_NEAR=U7770.3:6mm =P5VS0_EN OUT 72 =P3V3S0_EN OUT 72 =PBUSVSENS_EN OUT 50 PLACE_NEAR=U7760.B3:6mm PLACE_NEAR=U1800.G18:5mm PLACE_NEAR=U7100.15:6mm P1V8S0_EN =P1V8S0_EN OUT 71 =P1V5S0_EN OUT 71 MAKE_BASE=TRUE 73 =PP3V42_G3H_PWRCTL P1V5S0_EN 3.3V/5.0V Sus ENABLE C 0.1uF =PP3V3_S5_VMON R7956 46 45 150K 1% 1/16W MF-LF 402 R7951 15.0K 1% 1/16W MF-LF 402 IN SMC_BATLOW_L ALL_SYS_PWRGD 23 24 45 73 17 R7952 7.15K 1K NC Q2 ASMCC0179 NO STUFF DFN2015H4-8 R7917 =PP1V05_S0_VMON 1K 5% 1/16W MF-LF 402 S0PGD_BJT_GND_R =PP3V3_S5_PWRCTL R79571 100 P5V_DIV_VMON SENSE =PP3V3_SUS_PWRCTL 20% 10V CERM 402 U7930 RESET* =PP3V3_S0_PWRCTL 68 IN 71 IN NO STUFF 100 CPUIMVP_AXG_PGOOD 70 IN 100 U7960 ISL88042IRTEZ IN PVCCSA_PGOOD TDFN (IPU) V2MON CRITICAL MR* 1 15.0K 1% 1/16W MF-LF 4022 R7973 10K 353S2310 SOT23-6 MR* (90K IPU) PM_RSMRST_L OUT PM_ENET_EN_L PM_RSMRST_L goes to U1800.C21 100 100 IN WOL_EN G P3V3ENET_SS 10% 16V X7R-CERM 0402 "WLAN" = ("S3" && "AP_PWR_EN" && ("AC" || "S0")) NOTE: S3 term is guaranteed by S3 pull-up on open-drain AP_PWR_EN signal S Q7921 D PM_WLAN_EN_L SSM3K15AMFVAPE 73 45 26 17 IN OUT 32 Q7925 D G S 2N7002DW-X-G G SOT-363 AP_PWR_EN IN 18 23 32 PM_SLP_S3_L 5% 1/16W MF-LF 402 (AC_EN_L) AC_EN_L Q7920 NO STUFF IN SMC_ADAPTER_EN G S OUT SYNC_DATE=02/15/2011 Power Control 1/ENABLE R79291 D ALL_SYS_PWRGD SYNC_MASTER=K90I_MLB PAGE TITLE 2N7002DW-X-G SOT-363 C7922 0.01UF 100K WLAN Enable Generation D 5% 1/16W MF-LF 402 Q7920 D 2N7002DW-X-G DRAWING NUMBER SOT-363 (PM_SLP_S3_L) G Apple Inc S 051-9058 NOTICE OF PROPRIETARY PROPERTY: SIZE D REVISION 6.0.0 R THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED 23 24 45 73 5% 1/16W MF-LF 402 SOT-363 19 R7962 Q7925 S0PGOOD_ISL 330 =PP3V3_ENET_FET 5% 1/16W MF-LF 402 2N7002DW-X-G 46 45 17 R7922 NC NO STUFF R7964 D G 0.033UF 5% 1/16W MF-LF 402 17 100 S C7921 10% 16V X5R 402 10K R7966 1 R79211 5% 1/16W MF-LF 402 NC R7971 5% 1/16W MF-LF 402 S R7963 65 100K 5% 1/16W MF-LF 402 CPUVCCIOS0_PGOOD VDD =PP3V3_S3_P3V3ENETFET VESM 5% 1/16W MF-LF 402 20% 10V CERM 402 C7931 20% 50V CERM 402 5% 1/16W MF-LF 402 P1V8S0_PGOOD P5V3V3_PGOOD 0.001UF 5% 1/16W MF-LF 402 R7968 R7965 IN 10K =PP3V3_S0_VMON 66 B SOT-23-HF GND R79671 R7961 1% 1/16W MF-LF 4022 3.3V ENET FET NTR4101P VDD P1V5S0_PGOOD from U7710 V3MON P1V5_DIV_VMON S0PGOOD_ISL S0PGOOD_ISL ALL_SYS_PWRGD_R P1V05_DIV_VMON V4MON RST* 15.0K S0PGOOD_ISL 1% S0PGOOD_ISL GND THRM_PAD 1/16W MF-LF 4022 R7933 0.1uF CRITICAL 5% 1/16W MF-LF 402 Version in development) C7960 1% 1/16W MF-LF 402 10% 6.3V CERM-X5R 402 =PP3V3_SUS_PWRCTL C7930 No stuff C7931, 12ms Min delay time U7930 Sense input threhold is 3.07V Worst-Case Thresholds: S0PGOOD_ISL 6.04K 0.47UF Q7922 =PP1V5_S0_VMON =PP1V05_S0_VMON 73 S0PGOOD_ISL 0.1uF 1/16W MF-LF 402 2 C7986 PLACE_NEAR=U7930.6:2.3mm =PP5V_S0_VMON 4022 10% 6.3V CERM-X5R 402 3.3V SUS Detect 353S2809 S0 Rail PGOOD Circuitry A 0.47UF 10% 6.3V CERM-X5R 402 ENET Enable Generation 73 VMON_Q4_BASE R7960 S0PGOOD_ISL 6.04K R79701 1% 10K S0PGOOD_ISL 1/16W R79721 MF-LF 1% 0.47UF 10% 6.3V CERM-X5R 402 "ENET" = "S0" || ("S3" && "AC" && "WOL_EN") S4_PGOOD_CT CT 73 0.47UF C7988 72 TPS3808G33DBVRG4 73 S PLACE_NEAR=U7770.3:6mm CRITICAL 73 7 G C7981 Q4 Q2: 0.XXXV Q3: 0.640V 3.3V w/Divider: 2.345V Q4: 0.660V Thresholds: (ISL VDD: 2.734V-3.010V V2MON: 2.815V-3.099V V3MON: 0.572V-0.630V V4MON: 0.572V-0.630V OUT VFRQ Low: Fix Frequency VFRQ High: Variable Frequency 5% 1/16W MF-LF 402 CRITICAL 73 =P5V_3V3_SUS_EN C7987 CHGR VFRQ Generation R7955 B PM_SUS_EN MAKE_BASE=TRUE Q3 NC 50 65 OUT C VMON_Q3_BASE 5% 1/16W MF-LF 402 PP1V5_S0 PLACE_NEAR=U7100.15:6mm PLACE_NEAR=U7600.3:6mm GND Q1 R7954 =PP1V5_S0_VMON B 70 PLACE_NEAR=U7760.B3:6mm VESM PM_SLP_SUS_L Q7950 1% 1/16W MF-LF 402 IN 5% 1/16W MF-LF 402 73 VMON_Q2_BASE D =PVCCSA_EN MAKE_BASE=TRUE SSM3K15AMFVAPE Y R7953 1K PVCCSA_EN C 71 64 S0PGD_C VMON_3V3_DIV Q7931 U7940 74AUP1G3208 SOT891 A SMC_BATLOW_L:100K pull up on SMC page MAKE_BASE=TRUE CHGR_VFRQOUT VCC =1V05_S0_LDO_ENOUT =CPUVCCIOS0_EN OUT CPUVCCIOS0_EN 20% 10V CERM 402 5% 1/16W MF-LF 402 C7943 S0 Rail PGOOD (BJT Version) MAKE_BASE=TRUE 10K PLACE_NEAR=U7940.1:2.3mm =PP3V3_S0_VMON R7931 =PP3V3_S5_PWRCTL 73 73 D Q7911 MAKE_BASE=TRUE 74LVC1G32 5% 1/16W MF-LF 402 53 OUT 9.1K 5.1K 5% 1/16W MF-LF 402 PLACE_NEAR=U7300.16:6mm NO STUFF R7919 OUT MAKE_BASE=TRUE CPUVCORE ENABLE CPUIMVP_VR_ON D DDRREG_EN 0.1UF R7912 =PP3V3_S5_PWRCTL THRM PAD 10% 10V X5R-CERM 0402 TPAD_VBUS_EN PLACE_NEAR=U7970.6:3mm 46 45 0.068UF 66 R7974 NO STUFF C7913 45 OUT 66 PLACE_NEAR=U5701.3:6mm NC ALL_SYS_PWRGD 3.3K 5% 1/16W MF-LF 402 73 MAKE_BASE=TRUE (OD,IPU) =P5VS3_EN_L OUT MAKE_BASE=TRUE NC 73 45 24 23 1 P5VS3_EN_L R7914 PM_SLP_S3_L 1 3.3V S4 ENABLE OUT_B DLY GND 5% 25V C0G-CERM 0402 100 5% 1/16W MF-LF 402 SLG4AP012 TDFN MAKE_BASE=TRUE 73 CRITICAL D 0.1uF 20% 5% 1/16W MF-LF 402 State IN =PP3V42_G3H_PWRCTL =PP3V42_G3H_PWRCTL Internal pull-ups 100K +/- 20% C7940 45 R7913 3.3V,5V S3 ENABLE 68K BRANCH PAGE 79 OF 109 SHEET 73 OF 86 A D D LCD CONNECTOR LVDS CONNECTOR:518S0787 LCD_IG_PWR_EN CRITICAL J9000 20525-130E-01 F-RT-SM CRITICAL C9015 U9000 0.001UF FPF1009 ON =PP3V3_S5_LCD VIN_2 C GND C9009 0.1UF 10% 16V X7R-CERM 0402 31 10% 50V X7R-CERM 0402 2 FERR-120-OHM-1.5A VIN_1 1 0.001UF 10% 50V X7R-CERM 0402 L9004 MFET-2X2-8IN C9010 VOUT_1 PP3V3_LCDVDD_SW VOUT_2 VOLTAGE=3.3V MIN_LINE_WIDTH=0.30 MM THRM PAD C9011 10UF 10% 16V X7R-CERM 0402 20% 6.3V X5R 603 L9008 C9012 0.1UF CRITICAL PP3V3_LCDVDD_SW_F VOLTAGE=3.3V MIN_LINE_WIDTH=0.30 MM =PP3V3_S0_LCD NC 0402-LF MIN_NECK_WIDTH=0.20 MM 120-OHM-0.3A-EMI MIN_NECK_WIDTH=0.20 MM 2 0402-LF PP3V3_S0_LCD_F VOLTAGE=3.3V MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM (LVDS DDC POWER) 80 17 LVDS_IG_A_DATA_N 80 17 LVDS_IG_A_DATA_P C 10 1 R9008 10K 5% 1/16W MF-LF 402 LVDS_DDC_CLK LVDS_DDC_DATA R9009 80 17 LVDS_IG_A_DATA_N 11 10K 80 17 LVDS_IG_A_DATA_P 12 5% 1/16W MF-LF 402 80 17 LVDS_IG_A_DATA_N 14 80 17 LVDS_IG_A_DATA_P 15 13 16 CRITICAL L9080 90-OHM-100MA DLP11S 85 LVDS_CONN_A_CLK_F_N 17 85 LVDS_CONN_A_CLK_F_P 18 LVDS I/F SYM_VER-1 19 80 17 LVDS_IG_A_CLK_N 80 17 LVDS_IG_A_CLK_P 77 PPVOUT_SW_LCDBKLT 20 NC C9020 21 0.001UF 10% 50V X7R-CERM 0402 22 23 NC 24 LED BKLT I/F 25 26 27 28 77 LED_RETURN_1 77 LED_RETURN_2 77 LED_RETURN_3 77 LED_RETURN_4 77 LED_RETURN_5 33 77 LED_RETURN_6 34 29 30 NC B B 35 36 37 38 39 40 41 32 A SYNC_MASTER=K90I_MLB SYNC_DATE=02/15/2011 PAGE TITLE LVDS CONNECTOR DRAWING NUMBER Apple Inc 051-9058 R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED SIZE D REVISION 6.0.0 BRANCH PAGE 90 OF 109 SHEET 74 OF 86 A C9301 DP_EXTA_ML_C_N IN 81 C9302 DP_EXTA_ML_C_P IN C9303 DP_EXTA_ML_C_N IN D C9304 DP_EXTA_ML_C_P IN C9305 DP_EXTA_ML_C_N IN IN DP_EXTA_ML_C_P C9306 81 IN DP_EXTA_ML_C_N C9307 C9308 BI C9309 DP_EXTA_AUXCH_C_N BI DP_EXTA_ML_N OUT 0.47UF DP_EXTA_ML_P 75 81 IN C9372 83 33 IN T29_R2D_C_N T29_R2D_C_P DP_EXTA_ML_N 2 75 81 DP_EXTA_ML_P 75 81 DP_EXTA_ML_N 75 81 10% 16V X5R-CERM 0201 10% 16V X5R-CERM 0201 R9309 C9373 =PP3V3_S0_DPSDRVA DP_EXTA_AUXCH_N R9308 83 33 OUT 83 33 OUT 81 75 81 75 81 75 Note: Other Parade devices use 96/B6, so only 94/B4 are used for this part 81 75 81 75 81 75 81 75 NO STUFF 81 75 R9310 1K 5% 1/16W MF-LF 402 IN BI C9311 0.1UF 10% 16V X5R-CERM 0201 83 33 IN 83 33 IN C9382 T29_R2D_C_N T29_R2D_C_P 0.47UF C9383 R9312 1K 10% 16V X5R-CERM 0201 R9355 30 30 30 5% MF 1/20W 201 5% MF 1/20W 201 5% MF 1/20W 201 5% MF 1/20W 201 DP_EXTA_ML_P DP_EXTA_ML_N OUT_D1P OUT_D1N 28 27 DP_EXTA_ML_P DP_EXTA_ML_N IN_D2P IN_D2N OUT_D2P OUT_D2N 25 24 DP_EXTA_ML_P DP_EXTA_ML_N IN_D3P 10 IN_D3N OUT_D3P OUT_D3N 23 22 DP_EXTA_DDC_CLK DP_EXTA_DDC_DATA 14 IN_SCL 13 IN_SDA AC_AUXP AC_AUXN 20 19 DPSDRVA_I2C_CTL_EN 48 IN 48 BI B 23 16 IN 83 83 83 83 83 83 83 83 R9353 C9363 DP_SDRVA_ML_C_P DP_SDRVA_ML_C_N 0.1UF C9362 DP_SDRVA_ML_C_P DP_SDRVA_ML_C_N 0.1UF C9367 DP_SDRVA_ML_C_P DP_SDRVA_ML_C_N 0.1UF C9366 DP_SDRVA_AUXCH_C_P DP_SDRVA_AUXCH_C_N 0.1UF (IPD) OUT_HPD 31 (DP_SDRVA_HPD) C9369 32 DP_A_CA_DET CEXT 11 DPSDRVA_CEXT 0.1UF IN C9368 75 0.1UF DPSDRVA_REXT 12 REXT DP_AUXCH_ISOL 39 AUXDDC_OFF (IPD) 33 OUT 33 OUT =I2C_T29AMCU_SCL =I2C_T29AMCU_SDA T29DPA_HPD T29_A_BIAS_R T29_LSOE T29_LSOE OUT TBT_PWR_REQ_L 48 =TBT_WAKE_L: Desktops use PCIe WAKE# Mobiles use S4 WAKE# =TBT_WAKE_L OMIT OUT R93301 BI 76 IN 76 OUT 18 22 SWCLK 5% 1/20W MF 201 IN 76 IN 76 75 76 10K 46 75 TBT_A_HV_EN OUT 1K 5% 1/16W MF-LF 402 R9362 R9336 10K R9339 5% 1/20W MF 201 R9363 51 5% 1/20W MF 201 C9358 0.1UF DIN1_1+ DIN1_1- DP_SDRVA_AUXCH_P DP_SDRVA_AUXCH_N 19 18 AUX1+ AUX1- DP_SDRVA_HPD 17 HPD_1 T29_D2R1_BIASP T29_D2R1_BIASN 15 14 AUX2+ AUX2- 13 HPD_2 10 32 11 GPU_SEL AUX_SEL NC DP_A_PWRDWN T29_A_BIAS 20% 10V CERM 402 5% 1/20W MF 201 U9390 CBTL04DP081 HVQFN DOUT_0+ DOUT_0- T29DPA_ML_N T29DPA_ML_P T29: Unused OUT 76 83 76 83 BI T29DPA_ML_N BI 76 83 T29DPA_ML_P OUT 76 83 T29: LSX_A_R2P/P2R (P/N) DIN2_0+ DIN2_0DIN2_1+ DIN2_1- C9391 0.1UF 20% 10V CERM 402 100K VDD DOUT_1+ DOUT_1- 23 22 0.1UF CRITICAL (T29_A_LSX_P2R) (T29_A_LSX_R2P) C9390 AUX+ AUX- DP_A_EXT_AUXCH_P BI DP_A_EXT_AUXCH_N BI T29: RX_1 Bias Sink HPD_IN DP_A_EXT_HPD IN B 76 83 76 83 46 75 R9398 100K 5% 1/20W MF 201 LO=Port A HI=Port B THMPAD GND SIGNAL_MODEL=T29DP_MUX Note: U9390 ML/HPD defaults to T29 mode so that DP/T29 Display can detect host T29 support using I2C pull-ups on ML U9390 AUX defaults to DP mode because 100-ohm pull-downs would defeat DP Sink’s detection of DP Source SYNC_MASTER=K90I_MLB SYNC_DATE=02/15/2011 PAGE TITLE DRAWING NUMBER 1M 5% 1/16W MF-LF 402 Apple Inc 051-9058 NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED SIZE D REVISION R 5% 1/16W MF-LF 402 C 51 DisplayPort/T29 A MUXing T29_A_UC_ADDR R9330 provides pads for programming/debug of MCU, please make accessible If project has space for 10-pin programming header it should be used 27 26 P2R = Plug to Receptacle R2P = Receptacle to Plug 33 SWDIO DP_SDRVA_ML_N DP_SDRVA_ML_P 35 76 75 DIN1_0+ DIN1_0- 5% 1/16W MF-LF 402 75 R9335 1/20W 201 1/20W 201 VOLTAGE=3.3V R9399 DP_SDRVA_ML_N DP_SDRVA_ML_P R9334 I2C Addr: 0x26/0x27 (Wr/Rd) 5% MF 5% MF DP_A_BIAS2 31 30 CBTL04DP081 (353S3151) and PI3vEDP212 (353S3055) are footprint-compatible parts with similar pinouts NXP uses pin 10 for ML and HPD, Pericom uses pin 10 for ML and pin 11 for HPD 5% 1/16W MF-LF 402 IN 1/20W 201 NC 1K 10K 20% 10V CERM 402 T29_A_LSX_P2R T29_A_LSX_R2P T29_LSEO PIO0_6/SCK PIO1_6/RXD 23 PIO0_7/CTS# PIO1_7/TXD 24 PIO0_8/MISO/CT16B0_MAT0 PIO1_8/CT16B1_CAP0 PIO0_9/MOSI/CT16B0_MAT1 SWCLK/PIO0_10/SCK/CT16B0_MAT2 (OD) R/PIO0_11/AD0 (OD) THRM XTALIN VSS PAD 5% MF PP3V3_SW_TBTAPWR 76 75 Must be 3.3V DP A port power R9397 R9338 76 83 DP/T29 A Low-Speed MUX 5% 1/20W MF 201 0.1UF 76 83 OUT 10% 16V X7R-CERM 0402 51 C9331 OUT VOLTAGE=3.3V DP_A_BIAS R9393 T29DPA_CONFIG1_RC T29DPA_CONFIG2_RC TBT_A_HV_EN_R T29_A_UC_ADDR DP_A_EXT_HPD 16 17 18 19 20 76 83 DP_A_BIAS0 76 83 IN (D9360.2) U9359 74LVC1G04DBDCK 1 20% 10V CERM 402 1.5K CRITICAL 83 10 11 12 13 14 15 5% 1/16W MF-LF 402 1.5K IN Both R’s must connect to C in star topology DP Path Biasing R9361 1.5K 5% 1/20W MF 201 R9360 1.5K R9365 R9364 1K OMIT_TABLE HVQFN25 RESET#/PIO0_0 R/PIO1_0/AD1 PIO0_1/CLKOUT R/PIO1_1/AD2 PIO0_2/SSEL/CT16B0_CAP0 R/PIO1_2/AD3 (IPU) SWDIO/PIO1_3/AD4 PIO0_4/SCL (OD) PIO1_4/AD5/WAKEUP PIO0_5/SDA (OD) 17 T29_LSEO DP_SDRVA_ML_P DP_SDRVA_ML_N 83 Must be 3.3V DP A port power VDD 1/20W 201 1/20W 201 R9384 R9385 (D9360/D9361) 83 83 5% 1/20W MF 201 0.1UF K (D9382/D9383) 6.3V 0201 R9396 C9330 A 76 83 GND_VOID=TRUE (D9382/D9383) GND_VOID=TRUE (D9361.2) GND_VOID=TRUE 1.5K GND_VOID=TRUE 5% 1/20W 201 1.5K MF 5% 1/20W MF 201 SIGNAL_MODEL=T29PIN CKPLUS_WAIVE=NdifPr_badTerm 25 T29_A_RSVD_N 24 T29_A_RSVD_P TSLP-2-7 SIGNAL_MODEL=EMPTY 25 IN 6.3V 0201 K TSLP-2-7 BAR90-02LRH CRITICAL (All D’s) 6.3V 0201 10% 16V X5R-CERM 0201 10% 16V X5R-CERM 0201 5% 1/20W MF 201 21 IN 83 D9361 5% 1/20W MF 201 DP_SDRVA_ML_P DP_SDRVA_ML_N 83 U9330 48 83 83 LPC1112A 33 R9383 TSLP-2-7 BAR90-02LRH 83 51 CRITICAL DP_A_PWRDWN 20% X5R 20% X5R 6.3V 0201 83 5% MF 5% MF T29: TX_1 T29DPA_ML_C_P T29DPA_ML_C_N K A OMIT_TABLE R93921 PP3V3_SW_TBTAPWR 1 THMPAD 76 75 DP_A_CA_DET 20% X5R 20% X5R DP_A_PWRDWN Port A MCU 75 1.5K GND_VOID=TRUE TSLP-2-7 A D9383 GND_VOID=TRUE IC supports input high while Vcc = 0V 34 PD (IPD) GND D9382 76 83 OUT GND_VOID=TRUE K BAR90-02LRH OUT D 41 4.22K 83 A BAR90-02LRH T29_R2D_P T29_R2D_N 83 20% 6.3V CERM 402-LF PS8301 has internal ~150K pull-down on PD pin Okay to drive this pin even when VCC=0V per Parade (pin is 5V-tolerant) R9382 2 20% 4V CERM-X5R-1 201 2.2UF 33 R9319 1.5K D9360 5% 1/20W MF 201 76 83 GND_VOID=TRUE R9374 1.5K R9375 1.5K D9372/D9373: SIGNAL_MODEL=T29PIN D9364/D9365: SIGNAL_MODEL=EMPTY T29_D2R_C_P T29_D2R_C_N GND_VOID=TRUE 20% 4V CERM-X5R-1 201 PLACE_NEAR=U9310.11:2 mm C9319 K TSLP-2-7 BAR90-02LRH CRITICAL (All D’s) 76 83 IN (D9372/D9373) (D9365.2) SC70 10% 16V X5R-CERM 0201 10% 16V X5R-CERM 0201 IN_HPD CA_DET 75 A GND_VOID=TRUE GND_VOID=TRUE 20% 4V CERM-X5R-1 201 C9359 10% 16V X5R-CERM 0201 10% 16V X5R-CERM 0201 TSLP-2-7 10% 16V X7R-CERM 0402 1 DP_SDRVA_ML_C_P DP_SDRVA_ML_C_N (DP_SDRVA_AUXCH_P) (DP_SDRVA_AUXCH_N) =I2C_DPSDRVA_SCL =I2C_DPSDRVA_SDA 0.22UF C9361 K BAR90-02LRH 0.1UF 18 17 38 SCL_CTL 37 SDA_CTL 5% 1/20W MF 201 OUT_AUXP_SCL OUT_AUXN_SDA 36 I2C_ADDR0 (IPD) 35 I2C_ADDR1 (IPD) C9360 TSLP-2-7 IN (D9364.2) T29: TX_0 T29DPA_ML_C_P T29DPA_ML_C_N K A D9365 GND_VOID=TRUE TSLP-2-7 A D9373 =PP3V3_S0_DPSDRVA 75 270 16 IN_AUXP 15 IN_AUXN 26 I2C_CTL_EN (IPU) 0.22UF AUXCH Snoop Port, used by PS8301 during training DPSDRVA_I2C_ADDR0 DPSDRVA_I2C_ADDR1 DP_A_PWRDWN_R SDRV_PD 83 83 C9365 DP_SDRVA_ML_R_P DP_SDRVA_ML_R_N 5% 1/20W MF 201 IN_D1P IN_D1N OUT 83 270 30 29 0.22UF 0.22UF 83 30 C9364 DP_SDRVA_ML_R_P DP_SDRVA_ML_R_N R93521 OUT_D0P OUT_D0N DP_EXTA_HPD 83 83 VDD CRITICAL D9372 R9373 T29 Path Biasing K BAR90-02LRH GND_VOID=TRUE 1.5K 5% 1/20W MF 201 20% 4V CERM-X5R-1 GND_VOID=TRUE201 R9351 0.1UF IN_D0P IN_D0N 81 75 5% 1/16W MF-LF 402 A 83 A BAR90-02LRH T29_R2D_P T29_R2D_N 83 0.47UF R9308/R9309 maintain bias on C9308/C9309 to prevent spikes when U9310 AUXDDC_OFF transitions from high to low C9312 D9364 5% 1/20W MF 201 20% 4V CERM-X5R-1 201 GND_VOID=TRUE 1/20W 201 DP_EXTA_ML_P DP_EXTA_ML_N 0.47UF 75 81 5% MF 0.47UF 21 40 DP_EXTA_AUXCH_P DP_EXTA_AUXCH_N 81 75 75 1.5K R9372 T29_A_BIAS_R2DP1 T29_A_BIAS_R2DN1 C9381 QFN 1% 1/16W MF-LF 402 C9380 PS8301TQFN40GTR-A2 T29_D2R_C_P T29_D2R_C_N GND_VOID=TRUE 20% 4V CERM-X5R-1 201 GND_VOID=TRUE U9310 5% 1/20W MF 201 IN 1/20W 201 81 1M 20% 6.3V CERM 402-LF R9318 T29_D2R_N T29_D2R_P DP A Super-Driver Addr (W/R) 0x96/0x97 0xB6/0xB7 0x94/0x95 0xB4/0xB5 1K IN 75 10% 16V X5R-CERM 0201 PS8301 I2C Addresses: 5% 1/16W MF-LF 402 5% 1M MF DP_EXTA_AUXCH_P 75 2.2UF R9311 T29 A High-Speed Signals (C9380/C9381) C9310 1 0.47UF T29 signals are P/N-swapped after AC caps to improve layout 75 81 10% 16V X5R-CERM 0201 =PP3V3_S0_DPSDRVA A0 1 1 20% 4V CERM-X5R-1 201 GND_VOID=TRUE 83 33 R9350 A1 0 1 C9371 R9354 C C9370 20% 4V CERM-X5R-1 GND_VOID=TRUE 201 10% 16V 0.1UF X5R-CERM 0201 If GPU uses common pins for AUX_CH and DDC, alias nets together at GPU 75 IN 0.47UF 0.1UF 81 83 33 (C9370/C9371) T29_D2R_N T29_D2R_P T29_A_BIAS_R2DP0 T29_A_BIAS_R2DN0 75 81 10% 16V X5R-CERM 0201 0.1UF DP_EXTA_AUXCH_C_P OUT 10% 16V X5R-CERM 0201 0.1UF 81 DP_EXTA_ML_P 0.1UF 81 83 33 IN 0.47UF 0.1UF 81 75 81 10% 16V X5R-CERM 0201 0.1UF 81 DP_EXTA_ML_N 0.1UF 81 GND_VOID=TRUE 75 81 10% 16V X5R-CERM 0201 0.1UF 28 21 81 DP_EXTA_ML_P 10% 16V X5R-CERM 0201 0.1UF 29 20 16 12 C9300 DP_EXTA_ML_C_P IN 81 33 6.0.0 BRANCH PAGE 93 OF 109 SHEET 75 OF 86 A 3.3V/HV Power MUX V3P3 must be S4 to support wake from Thunderbolt devices =PP3V3_S4_TBTAPWRSW CRITICAL D CRITICAL C9487 C9480 20% 6.3V POLY-TANT CASE-B2-SM 20% 6.3V X5R-CERM-1 603 22UF 100UF C9481 0.1UF 19 20 1200mA 830mA 930mA (assumes 15V, 12W minimum) IHVS3 890mA 830mA 930mA (assumes 3S, 9-12.6V, 7.5-11.7W) V3P3OUT 18 OUT CRITICAL 0.1UF U9410 10% 50V X7R 603-1 10% 25V X5R-CERM 0603 MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=15V C9485 1 0.1UF QFN C9486 10UF 20% 6.3V X5R 603 20% 10V CERM 402 CD3210A0RGP 16 RSVD C9411 0.1UF 10% 50V X7R 603-1 RSVD 15 IN =TBTAPWRSW_EN 75 35 IN TBT_A_HV_EN 11 HV_EN ISET_S0 10 TBTAPWRSW_ISET_S0 IN =TBT_S0_EN 17 S0 ISET_S3 TBTAPWRSW_ISET_S3 TBTHV:P15V 73 75 PPHV_SW_TBTAPWR 12 14 VHV C9410 4.7UF D MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=3.3V V3P3 Max 1030mA 890mA PP3V3_SW_TBTAPWR 20V Max C9415 Min 1100mA IHVS0 20% 10V CERM 402 =PPHV_SW_TBTAPWRSW Nominal IV3P3 EN TBTAPWRSW_ISET_V3P3 ISET_V3P3 THRM PAD R9411 22.6K 1% 1/20W MF 201 22.6K 1% 1/20W MF 201 R9412 36.5K 1% 1/20W MF 201 TBTAPWRSW_ISET_S3_R TBTAPWRSW_ISET_S0_R TBTHV:P15V R94131 For 12V systems: 22.6K below TBTHV:P15V C TBTHV:P15V R94101 12V: See 21 13 GND 1% 1/20W MF 201 R9414 22.6K 1% 1/20W MF 201 Single-fault protection requires two R’s per HV ISET_Sx with CD3210 Single R on ISET_V3P3 OK C ILIM = 40000 / RISET PART NUMBER QTY DESCRIPTION REFERENCE DES 114S0338 RES,MTL FILM,1/16W,17.8K,1,0402,SMD,LF R9410,R9413 CRITICAL BOM OPTION TBTHV:P12V 114S0338 RES,MTL FILM,1/16W,17.8K,1,0402,SMD,LF R9411,R9414 TBTHV:P12V IHVS0/S3 Nominal 1120mA Min 1090mA Max 1170mA (12W minimum) Thunderbolt Connector A L9400 FERR-120-OHM-3A PP3V3RHV_SW_DPAPWR MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=18V 0603 C9400 C9405 0.01UF C9490 75 IN T29_A_BIAS_R 0.1UF 0.01UF 10% 50V X7R 402 For J9400 T29 SMT pads (3, 5, 17 & 19): GND_VOID=TRUE T29 Dir 10% 16V X7R-CERM 0402 83 75 OUT 83 75 OUT 1K 5% 1/20W MF 201 VOLTAGE=3.3V SIGNAL_MODEL=EMPTY 75 83 75 B IN IN 83 75 T29_A_BIAS_D2RN1 T29_A_BIAS_D2RP1 2.2K 5% 1/20W MF 201 GND_VOID=TRUE 1K 5% 1/20W MF 201 10 12 14 16 18 20 SIGNAL_MODEL=EMPTY T29DPA_ML_P T29DPA_ML_N T29: Unused BI BI 83 75 83 75 OUT OUT L9498 650NH-5%-0.430MA-0.52OHM 2.2K 5% 1/20W MF 201 GND_VOID=TRUE T29_D2R_C_P T29_D2R_C_N A BAR90-02LRH D9499 A K TSLP-2-7 83 83 K TSLP-2-7 BAR90-02LRH CRITICAL 83 75 BI DP_A_EXT_AUXCH_P DP_A_EXT_AUXCH_N OUT T29DPA_HPD OUT T29DPA_CONFIG1_RC 75 OUT T29DPA_CONFIG2_RC R94521 1M 5% 1/16W MF-LF 402 R9451 C9494 1M 5% 1/16W MF-LF 402 330PF 10% 50V X7R-CERM 0402 MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=0V DP Source must pull down HPD input with greater than or equal to 100K (DPv1.1a) C9495 330PF 10% 50V X7R-CERM 0402 0.01UF T29DPA_ML_P T29DPA_ML_N T29: TX_1 C9471 R9470 IN 75 83 IN 75 83 IN 75 83 R9471 470K 470K 5% 1/20W MF 201 5% 1/20W MF 201 T29DPA_ML_P T29DPA_ML_N BI B 75 83 T29DPA_ML_C_P 20% 4V CERM-X5R-1 T29DPA_ML_C_N 201 4V 0.47UF 20% CERM-X5R-1 201 GND_VOID=TRUE GND_VOID=TRUE 1 C9473 470K 5% 1/20W MF 201 R9401 10% 10V X5R-CERM 0201 C9401 12 5% 1/20W MF 201 0.47UF R9472 IN 75 83 IN 75 83 R9473 470K 5% 1/20W MF 201 470k R’s for ESD protection on AC-coupled signals 0.01UF 10% 50V X7R 402 SYNC_MASTER=K90I_MLB SYNC_DATE=02/15/2011 PAGE TITLE R9441 Thunderbolt Connector A 100K 5% 1/16W MF-LF 402 DRAWING NUMBER Apple Inc Sink HPD range: High: 2.0 - 5.0V Low: - 0.8V (Both C’s) 83 MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=18V C9402 10% 25V X5R-CERM 0201 T29DPA_ML_C_P 20% 4V CERM-X5R-1 T29DPA_ML_C_N 201 4V 0.47UF 20% CERM-X5R-1 201 GND_VOID=TRUE GND_VOID=TRUE 1 C9472 83 C9499 5% 50V CERM 402 (Both C’s) 0.47UF T29: LSX_R2P/P2R (P/N) T29DPA_D2R1_AUXCH_P T29DPA_D2R1_AUXCH_N CRITICAL 30PF 22 21 DPACONN_20_RC 5% 50V CERM 402 75 0.01UF GND_DPACONN_7_C SHIELD PINS GND_VOID=TRUE 0603 SIGNAL_MODEL=EMPTY 30PF 75 C9406 11 13 15 17 19 C9498 A SM PINS HOT_PLUG_DETECT GND CONFIG1 ML_LANE0P CONFIG2 ML_LANE0N GND GND ML_LANE3P ML_LANE1P ML_LANE3N ML_LANE1N GND GND AUX_CHP ML_LANE2P AUX_CHN ML_LANE2N DP_PWR RETURN 650NH-5%-0.430MA-0.52OHM (Both L’s) BI TOP ROW TH PINS L9499 GND_VOID=TRUE SIGNAL_MODEL=T29PIN 83 75 BOT ROW GND_VOID=TRUE C9470 GND_VOID=TRUE GND_VOID=TRUE 0603 SIGNAL_MODEL=EMPTY D9498 83 T29DPA_ML_P T29DPA_ML_N T29: TX_0 R9495 R9499 T29 Dir 83 10% 25V X5R-CERM 0201 F-RT-THSM GND_VOID=TRUE CRITICAL R94981 DP Dir DSPLYPRT-M97-1 R9494 51 5% 1/20W MF 201 MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=0V J9400 GND_VOID=TRUE OUT CRITICAL T29_D2R_C_P T29_D2R_C_N R94911 T29_A_BIAS DP Dir GND_DPACONN_1_C 051-9058 R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED SIZE D REVISION 6.0.0 BRANCH PAGE 94 OF 109 SHEET 76 OF 86 A PPBUS S0 LCDBkLT FET MOSFET CRITICAL Q9706 FDC638APZ CHANNEL P-TYPE RDS(ON) 43 mOhm @4.5V LOADING 0.715 A (EDP) FDC638APZ_SBMS001 SSOT6-HF R9788 BOTTOM AND PPBUS_SW_BKL ON THE SENSOR PAGE 10% 16V X7R-CERM 0402 1% 1/16W MF-LF 402 *LCD_BKLT_PWM SHOULD BE AWAY FROM BOOST CIRCUIT PLACE_NEAR=L9701.2:3mm =PP5V_S0_BKL CRITICAL CRITICAL L9701 D9701 33UH-1.8A-110MOHM LCDBKLT_EN_DIV D *C9797 AND C9799 SHOULD BE PLACED IN T-BONE FOR ACOUSTICS *PPBUS_SW_LCDBKLT_PWR_SW SHOULD BE KEPT AS SHORT AS POSSIBLE 0.1UF 301K C9782 PPBUS_S0_LCDBKLT_FUSED MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.6V 603-HF =PPBUS_S0_LCDBKLT 77 THERE IS A SENSE RESISTOR BETWEEN PPBUS_SW_LCDBKLT_PWR D MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.6V F9700 3AMP-32V-467 PPBUS_SW_LCDBKLT_PWR =PPBUS_SW_BKL CRITICAL C9712 R9789 1 10% 25V X5R 805 2 PLACE_NEAR=L9701.1:4mm SOD-123 C9713 0.1UF SWITCH_NODE=TRUE DIDT=TRUE 10% 25V X5R 402 A PPBUS_SW_LCDBKLT_PWR_SW MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=40V 1217AS-2SM 10UF 147K 1% 1/16W MF-LF 402 K PLACE_NEAR=U9701.A5:3mm PPVOUT_SW_LCDBKLT CRITICAL RB160M-60G C9796 220PF PLACE_NEAR=L9701.1:3mm CRITICAL C9797 10UF 10% 50V X7R-CERM 0402 C9799 74 MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.375 MM VOLTAGE=50V 10UF 10% 50V X5R 1210-1 10% 50V X5R 1210-1 PLACE_NEAR=D9701.2:5mm LCDBKLT_EN_L PLACE_NEAR=D9701.2:3mm Q9707 D SSM6N15AFE SOT563 PLACE_NEAR=U9701.D1:5mm PLACE_NEAR=U9701.D1:3mm C9710 IN G S LCD_BKLT_EN LCDBKLT_DISABLE Q9707 1 0.01UF 10% 25V X5R 603-1 10% 16V X7R-CERM 0402 2 XW9720 C9714 1UF SM PPVOUT_SW_LCDBKLT_FB VOLTAGE=40V MIN_LINE_WIDTH=0.1 MM MIN_NECK_WIDTH=0.1 MM PLACE_NEAR=C9797.1:5mm D SSM6N15AFE =PP3V3_S0_BKL_VDDIO SOT563 PLACE_NEAR=U9701.C4:4mm C C9711 C 0.1UF IN 10% 16V X7R-CERM 0402 S BKLT_PLT_RST_L 10K C4 R9755 C1 24 G D1 2 VIN VDDIO VLDO 5% 1/16W MF-LF 402 U9701 25-BUMP-MICRO 10K 5% 1/16W MF-LF 402 R9753 IN BI =I2C_BKL_1_SDA BKL_FSET 5% 1/16W MF-LF 402 B4 ISET FSET B1 BKLT:PROD B2 R9717 FB PLACE_NEAR=U9701.E5:10mm A5 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm R9731 301K B 1% 1/16W MF-LF 402 R9704 33 5% 1/16W MF-LF 402 BKL_PWM BKL_EN A4 PWM A3 EN C3 TP_BKL_FAULT R9715 D4 SCLK SDA FAULT CRITICAL PLACE_SIDE=BOTTOM 100K 1% 1/16W MF-LF 402 B5 LCD_BKLT_PWM D3 C9704 OUT1 E5 OUT2 OUT3 D5 OUT4 OUT5 E3 OUT6 E1 C5 E2 BKL_ISEN1 BKL_ISEN2 BKL_ISEN3 BKL_ISEN4 BKL_ISEN5 BKL_ISEN6 BOTTOM 90.9K Fpwm=9.62kHz see spec for others 1% 1/16W MF-LF 402 74 LED_RETURN_2 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm OUT 74 OUT 74 OUT 74 OUT 74 OUT 74 B R9719 PLACE_NEAR=U9701.C5:10mm MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm LED_RETURN_3 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm 5% 1/16W MF-LF 402 BKLT:PROD R9714 R9720 16.2K OUT BKLT:PROD I_LED=22.7mA R9716 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm 5% 1/16W MF-LF 402 BOTTOM 5% 50V C0G-CERM 0402 LED_RETURN_1 R9718 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm 33PF 5% 1/16W MF-LF 402 BKLT:PROD PLACE_NEAR=U9701.D5:10mm GND_SW GND_SW BKL_SCL BKL_SDA A2 GND_L PPBUS_SW_LCDBKLT_PWR IN B3 SW_0 SW_1 A1 5% 1/16W MF-LF 402 FILTER E4 R9757 77 C2 BOTTOM Addr: 0x58(Wr)/0x59(Rd) 48 BKL_ISET VSYNC GND_S 48 =I2C_BKL_1_SCL BKL_FLTR D2 LP8550 BKL_VSYNC_R R9741 PLACE_NEAR=U9701.E3:10mm 1% 1/16W MF-LF 402 PLACEMENT_NOTE=Keep away from noise nodes(E4, A1, A2, B1, B2 pins) MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm XW9710 SM GND_BKL_SGND BOTTOM LED_RETURN_4 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm 5% 1/16W MF-LF 402 BKLT:PROD MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=0V R9721 PLACE_NEAR=U9701.E2:10mm I_LED=369/Riset (EEPROM should set EN_I_RES=1) MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm BOTTOM LED_RETURN_5 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm 5% 1/16W MF-LF 402 BKLT:PROD R9722 PLACE_NEAR=U9701.E1:10mm MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm BOTTOM A PART NUMBER 103S0198 103S0198 QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION RES,THIN FLIM,1/16W,10.2 OHM,0.1,0402,SM R9717,R9718,R9719 BKLT:ENG RES,THIN FLIM,1/16W,10.2 OHM,0.1,0402,SM R9720,R9721,R9722 BKLT:ENG LED_RETURN_6 5% 1/16W MF-LF 402 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm SYNC_MASTER=J31_MLB 10.2 ohm resistors for current measurement on LED strings SYNC_DATE=07/08/2011 PAGE TITLE LCD Backlight Driver DRAWING NUMBER Apple Inc 051-9058 R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED SIZE D REVISION 6.0.0 BRANCH PAGE 97 OF 109 SHEET 77 OF 86 A CPU Signal Constraints CPU Net Properties TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP CPU_50S * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD NET_TYPE ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING TABLE_PHYSICAL_RULE_ITEM CPU_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD TABLE_PHYSICAL_RULE_ITEM CPU_27P4S * =27P4_OHM_SE =27P4_OHM_SE =27P4_OHM_SE =27P4_OHM_SE MIL PCIE_85D PCIE_PCH_TX DMI_S2N PCIE_85D PCIE_PCH_TX DMI_N2S PCIE_85D PCIE_PCH_RX DMI_N2S PCIE_85D PCIE_PCH_RX FDI_DATA PCIE_85D PCIE_PCH_RX FDI_DATA PCIE_85D PCIE_PCH_RX CPU_50S CPU_AGTL FDI_DATA_P FDI_DATA_N FDI_FSYNC CPU_50S CPU_AGTL FDI_LSYNC 17 CPU_50S CPU_AGTL FDI_INT 17 CPU_PECI CPU_50S CPU_COMP CPU_PECI 10 19 46 PM_SYNC CPU_50S CPU_AGTL PM_MEM_PWRGD CPU_50S CPU_AGTL PM_SYNC PM_MEM_PWRGD CPU_50S CPU_ITP XDP_DBRESET_L CPU_50S CPU_ITP CPU_50S CPU_ITP XDP_CPU_PRDY_L XDP_CPU_PREQ_L CPU_50S CPU_AGTL MIL NOTE: mil gap is for VCCSense pair, which Intel says to route with mil spacing without specifying a target impedance TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING TABLE_SPACING_RULE_HEAD WEIGHT SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM D CPU_AGTL * =STANDARD DMI_S2N_P DMI_S2N_N DMI_N2S_P DMI_N2S_N DMI_S2N TABLE_PHYSICAL_RULE_ITEM 17 17 17 17 17 17 17 TABLE_SPACING_RULE_ITEM ? CPU_AGTL TOP,BOTTOM =2x_DIELECTRIC ? D TABLE_SPACING_RULE_ITEM CPU_8MIL * MIL ? TABLE_SPACING_RULE_ITEM CPU_COMP * 20 MIL ? CPU_ITP * =2:1_SPACING ? CPU_VCCSENSE * 25 MIL ? TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM 10 17 10 17 26 Most CPU signals with impedance requirements are 50-ohm single-ended Some signals require 27.4-ohm single-ended impedance 10 23 24 SOURCE: Huron River SFF DG (DG-438297_v1.0), Section 4.18 and Huron River Platform Power Delivery DG v1.0 Section 2.7 PCI-Express 10 23 10 23 TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP PCIE_85D * =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF TABLE_PHYSICAL_RULE_ITEM CPU_50S CPU_AGTL CPU_SM_RCOMP CPU_27P4S CPU_COMP CPU_SM_RCOMP CPU_27P4S CPU_COMP CPU_SM_RCOMP CPU_27P4S CPU_COMP TABLE_PHYSICAL_RULE_ITEM CLK_PCIE_90D * =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT 20 MIL ? LINE-TO-LINE SPACING WEIGHT CPU_50S CPU_ITP CPU_50S CPU_AGTL CPU_50S CPU_AGTL CPU_PROCHOT_L CPU_50S CPU_AGTL CPU_PWRGD CPU_50S CPU_AGTL CPU_PROCHOT_L CPU_PWRGD PM_THRMTRIP_L CPU_50S CPU_8MIL PM_THRMTRIP_L DMI_CLK100M DMI_CLK100M_CPU_P DMI_CLK100M_CPU_N ITPCPU_CLK100M_P ITPCPU_CLK100M_N ITPXDP_CLK100M_P ITPXDP_CLK100M_N XDP_CPU_CLK100M_P XDP_CPU_CLK100M_N CPU_CATERR_L TABLE_SPACING_RULE_ITEM CLK_PCIE * TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER C * =3X_DIELECTRIC LAYER LINE-TO-LINE SPACING WEIGHT PCIE_PCH_TX2TX TOP,BOTTOM =4X_DIELECTRIC * =4X_DIELECTRIC ? * =3x_DIELECTRIC ? TABLE_SPACING_RULE_ITEM PCIE_PCH_TX2RX TOP,BOTTOM =5X_DIELECTRIC ? PCIE_PCH_RX2RX TOP,BOTTOM =4x_DIELECTRIC ? TABLE_SPACING_RULE_ITEM PCIE_PCH_RX2TX * =4x_DIELECTRIC ? * =3x_DIELECTRIC ? CLK_PCIE_90D CLK_PCIE DMI_CLK100M CLK_PCIE_90D CLK_PCIE ITPCPU_CLK100M CLK_PCIE_90D CLK_PCIE TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM PCIE_PCH_2OTHER TABLE_SPACING_RULE_ITEM PCIE_PCH_RX2TX TOP,BOTTOM =4x_DIELECTRIC ? PCIE_PCH_2OTHER TOP,BOTTOM =4x_DIELECTRIC ? TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM ITPCPU_CLK100M CLK_PCIE_90D CLK_PCIE I125 ITPCPU_CLK100M CLK_PCIE_90D CLK_PCIE I126 ITPCPU_CLK100M CLK_PCIE_90D CLK_PCIE I127 ITPCPU_CLK100M CLK_PCIE_90D CLK_PCIE I128 ITPCPU_CLK100M CLK_PCIE_90D CLK_PCIE CPU_27P4S CPU_COMP CPU_27P4S CPU_COMP XDP_TDI CPU_50S CPU_ITP XDP_TDO CPU_50S CPU_ITP XDP_TMS CPU_50S CPU_ITP XDP_TCK CPU_50S CPU_ITP TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET PCIE_PCH_TX *_PCH_TX * PCIE_PCH_TX2TX 23 10 45 12 10 45 46 68 10 19 23 10 19 46 ? TABLE_SPACING_RULE_ITEM PCIE_PCH_RX2RX 10 TABLE_SPACING_RULE_ITEM ? PCIE_PCH_TX2RX 10 10 TABLE_SPACING_RULE_HEAD SPACING_RULE_SET TABLE_SPACING_RULE_ITEM PCIE_PCH_TX2TX PM_EXT_TS_L PM_EXT_TS_L CPU_SM_RCOMP CPU_SM_RCOMP CPU_SM_RCOMP CPU_CFG CPU_CATERR_L CPU_VCCIO_SEL I121 EDP_COMP CPU_PEG_COMP C 10 16 10 16 10 16 10 16 16 23 16 23 23 23 9 TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM PCIE_PCH_TX *_PCH_RX * PCIE_PCH_TX2RX PCIE_PCH_RX *_PCH_RX * PCIE_PCH_RX2RX PCIE_PCH_RX *_PCH_TX * PCIE_PCH_RX2TX PCIE_PCH_TX * * PCIE_PCH_2OTHER TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM PCIE_PCH_RX * * PCIE_PCH_2OTHER XDP_TRST_L SOURCE: 471984_Cheif_River_MS_PDG_1.0 and the spacing rule is adjusted per SI team feedback B CPU_50S CPU_ITP XDP_BPM_L CPU_50S CPU_ITP XDP_BPM_R_L CPU_50S CPU_ITP (FSB_CPURST_L) CPU_50S CPU_ITP CPU_VCCAXG_SENSE CPU_27P4S CPU_VCCSENSE CPU_VCCAXG_SENSE CPU_27P4S CPU_VCCSENSE CPU_VCCSENSE CPU_27P4S CPU_VCCSENSE CPU_VCCSENSE CPU_27P4S CPU_VCCSENSE CPU_VCCAXG_SENSE CPU_27P4S CPU_VCCSENSE CPU_VCCAXG_SENSE CPU_27P4S CPU_VCCSENSE I115 CPU_VALSENSE CPU_27P4S CPU_VCCSENSE I116 CPU_VALSENSE CPU_27P4S CPU_VCCSENSE I117 CPU_VALSENSE CPU_27P4S CPU_VCCSENSE I118 CPU_VALSENSE CPU_27P4S CPU_VCCSENSE I119 CPU_VALSENSE CPU_27P4S CPU_VCCSENSE I120 CPU_VALSENSE CPU_27P4S CPU_VCCSENSE I122 CPU_SVIDALERT_L CPU_50S CPU_COMP I123 CPU_SVIDSCLK CPU_50S CPU_COMP XDP_CPU_TDI XDP_CPU_TDO XDP_CPU_TMS XDP_CPU_TCK XDP_CPU_TRST_L XDP_BPM_L CPU_CFG XDP_CPURST_L CPU_VCCSENSE_P CPU_VCCSENSE_N CPU_VCCIOSENSE_P CPU_VCCIOSENSE_N CPU_AXG_SENSE_P CPU_AXG_SENSE_N CPU_VDDQ_SENSE_P CPU_VDDQ_SENSE_N CPU_AXG_VALSENSE_P CPU_AXG_VALSENSE_N CPU_VCC_VALSENSE_P CPU_VCC_VALSENSE_N 10 23 10 23 10 23 10 23 10 23 10 23 23 23 12 68 CPU_VCCSA_VID CPU_VCCSA_VID B 12 68 12 70 12 70 12 68 12 68 12 12 9 9 CPU_VIDALERT_L I124 CPU_SVIDSOUT CPU_50S CPU_COMP 12 68 CPU_VIDSCLK 12 68 CPU_VIDSOUT 12 68 A SYNC_MASTER=K90I_MLB SYNC_DATE=02/15/2011 PAGE TITLE CPU Constraints DRAWING NUMBER Apple Inc 051-9058 R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED SIZE D REVISION 6.0.0 BRANCH PAGE 100 OF 109 SHEET 78 OF 86 A Memory Bus Constraints Memory Net Properties TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP MEM_37S * =37_OHM_SE =37_OHM_SE =37_OHM_SE =37_OHM_SE =STANDARD =STANDARD NET_TYPE ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING TABLE_PHYSICAL_RULE_ITEM MEM_A_CLK MEM_72D MEM_CLK MEM_A_CLK MEM_72D MEM_CLK MEM_A_CNTL MEM_37S MEM_CTRL MEM_A_CNTL MEM_37S MEM_CTRL MEM_A_CNTL MEM_37S MEM_CTRL MEM_A_CMD MEM_40S MEM_CMD TABLE_PHYSICAL_RULE_ITEM MEM_40S * =40_OHM_SE =40_OHM_SE =40_OHM_SE =40_OHM_SE =STANDARD =STANDARD MEM_A_CLK_P MEM_A_CLK_N 11 27 11 27 TABLE_PHYSICAL_RULE_ITEM MEM_72D * =72_OHM_DIFF =72_OHM_DIFF =72_OHM_DIFF =72_OHM_DIFF =72_OHM_DIFF =72_OHM_DIFF MEM_50S TOP,BOTTOM Y =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD TABLE_PHYSICAL_RULE_ITEM MEM_A_CKE MEM_A_CS_L MEM_A_ODT 11 27 11 27 11 27 TABLE_PHYSICAL_RULE_ITEM MEM_85D TOP,BOTTOM =85_OHM_DIFF Y =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF TABLE_PHYSICAL_RULE_ITEM MEM_50S D ISL10 N =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD MEM_A_CMD MEM_40S MEM_CMD MEM_A_CMD MEM_40S MEM_CMD MEM_A_CMD MEM_40S MEM_CMD MEM_A_CMD MEM_40S MEM_CMD MEM_A_DQ_BYTE0 MEM_50S MEM_DATA MEM_A_DQ_BYTE1 MEM_50S MEM_DATA MEM_A_DQ_BYTE2 MEM_50S MEM_DATA MEM_A_DQ_BYTE3 MEM_50S MEM_DATA MEM_A_DQ_BYTE4 MEM_50S MEM_DATA MEM_A_DQ_BYTE5 MEM_50S MEM_DATA MEM_A_DQ_BYTE6 MEM_50S MEM_DATA MEM_A_DQ_BYTE7 MEM_50S MEM_DATA MEM_A_DQS0 MEM_85D MEM_DQS MEM_A_DQS0 MEM_85D MEM_DQS MEM_A_DQS1 MEM_85D MEM_DQS MEM_A_DQS1 MEM_85D MEM_DQS MEM_A_DQS2 MEM_85D MEM_DQS MEM_A_DQS2 MEM_85D MEM_DQS MEM_A_DQS3 MEM_85D MEM_DQS MEM_A_DQS3 MEM_85D MEM_DQS MEM_A_DQS4 MEM_85D MEM_DQS MEM_A_DQS4 MEM_85D MEM_DQS MEM_A_DQS5 MEM_85D MEM_DQS MEM_A_DQS5 MEM_85D MEM_DQS MEM_A_DQS6 MEM_85D MEM_DQS MEM_A_DQS6 MEM_85D MEM_DQS MEM_A_DQS7 MEM_85D MEM_DQS MEM_A_DQS7 MEM_85D MEM_DQS MEM_B_CLK MEM_72D MEM_CLK TABLE_SPACING_RULE_ITEM MEM_B_CLK MEM_72D MEM_CLK TABLE_SPACING_RULE_ITEM MEM_B_CNTL MEM_37S MEM_CTRL MEM_B_CNTL MEM_37S MEM_CTRL MEM_B_CNTL MEM_37S MEM_CTRL MEM_B_CMD MEM_40S MEM_CMD TABLE_PHYSICAL_RULE_ITEM MEM_85D ISL10 N =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF MEM_50S ISL3,ISL4,ISL9 Y =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD MEM_85D ISL3,ISL4,ISL9 Y =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF TABLE_PHYSICAL_RULE_ITEM MEM_A_A MEM_A_BA MEM_A_RAS_L MEM_A_CAS_L MEM_A_WE_L 11 27 11 27 D 11 27 11 27 11 27 TABLE_PHYSICAL_RULE_ITEM C TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM MEM_CLK2MEM * =4:1_SPACING ? TABLE_SPACING_RULE_ITEM MEM_CTRL2CTRL * =3:1_SPACING ? MEM_CTRL2MEM * =2.5:1_SPACING ? TABLE_SPACING_RULE_ITEM MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N 11 28 11 28 11 28 11 28 11 28 11 28 11 28 11 28 11 28 11 28 11 28 11 28 11 28 11 28 C 11 28 11 28 11 28 11 28 11 28 11 28 11 28 11 28 11 28 11 28 TABLE_SPACING_RULE_ITEM MEM_CMD2CMD * =1.5:1_SPACING ? MEM_CMD2MEM * =3:1_SPACING ? MEM_DATA2DATA * =1.5:1_SPACING ? MEM_DATA2MEM * =3:1_SPACING ? TABLE_SPACING_RULE_ITEM MEM_B_CLK_P MEM_B_CLK_N MEM_B_CKE MEM_B_CS_L MEM_B_ODT 11 29 11 29 11 29 11 29 11 29 TABLE_SPACING_RULE_ITEM MEM_DQS2MEM * =3:1_SPACING ? MEM_2OTHER * 25 MILS ? TABLE_SPACING_RULE_ITEM Memory Bus Spacing Group Assignments TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET MEM_CLK MEM_CLK * MEM_CLK2MEM MEM_CLK MEM_CTRL * MEM_CLK2MEM NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET MEM_CMD MEM_CLK * MEM_CMD2MEM MEM_CMD MEM_CTRL * MEM_CMD2MEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CMD * MEM_CLK2MEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CMD MEM_CMD * TABLE_SPACING_ASSIGNMENT_ITEM MEM_CLK MEM_DATA * MEM_CLK2MEM MEM_CLK MEM_DQS * MEM_CLK2MEM NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET MEM_DATA * MEM_CMD2MEM MEM_CMD MEM_DQS * MEM_CMD2MEM NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET MEM_DATA MEM_CLK * MEM_DATA2MEM MEM_DATA MEM_CTRL * MEM_DATA2MEM MEM_DATA MEM_CMD * MEM_DATA2MEM MEM_DATA MEM_DATA * MEM_DATA2DATA MEM_DATA MEM_DQS * MEM_DATA2MEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CTRL2MEM MEM_CTRL * MEM_CTRL2CTRL MEM_CMD * MEM_CTRL2MEM MEM_CTRL MEM_DATA * MEM_CTRL2MEM MEM_DQS * MEM_CTRL2MEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET MEM_CLK * MEM_DQS2MEM NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE MEM_CTRL * MEM_DQS2MEM MEM_CLK * * MEM_CMD * MEM_DQS2MEM MEM_CTRL * * MEM_DATA * MEM_DQS2MEM MEM_CMD * * A MEM_DQS * MEM_DQS2MEM MEM_2OTHER MEM_50S MEM_DATA MEM_B_DQ_BYTE2 MEM_50S MEM_DATA MEM_B_DQ_BYTE3 MEM_50S MEM_DATA MEM_B_DQ_BYTE4 MEM_50S MEM_DATA MEM_B_DQ_BYTE5 MEM_50S MEM_DATA MEM_B_DQ_BYTE6 MEM_50S MEM_DATA MEM_B_DQ_BYTE7 MEM_50S MEM_DATA MEM_B_DQS0 MEM_85D MEM_DQS MEM_B_DQS0 MEM_85D MEM_DQS MEM_B_DQS1 MEM_85D MEM_DQS MEM_B_DQS1 MEM_85D MEM_DQS MEM_B_DQS2 MEM_85D MEM_DQS MEM_B_DQS2 MEM_85D MEM_DQS MEM_B_DQS3 MEM_85D MEM_DQS MEM_B_DQS3 MEM_85D MEM_DQS MEM_B_DQS4 MEM_85D MEM_DQS MEM_B_DQS4 MEM_85D MEM_DQS MEM_B_DQS5 MEM_85D MEM_DQS MEM_B_DQS5 MEM_85D MEM_DQS MEM_B_DQS6 MEM_85D MEM_DQS MEM_B_DQS6 MEM_85D MEM_DQS MEM_B_DQS7 MEM_85D MEM_DQS MEM_B_DQS7 MEM_85D MEM_DQS MEM_2OTHER * * MEM_2OTHER TABLE_SPACING_ASSIGNMENT_ITEM MEM_DQS * * MEM_2OTHER Need to support MEM_*-style wildcards! DDR3: Sandybridge SFF 2C when routed on Type-3 (Through hole) should follow rPGA guidelines per Huron River SFF DG rev1.0 (#438297) DQS intra-pair matching should be within 0.127mm, no inter-pair matching requirement DQ to DQS matching per byte lane should be within 0.127mm DQS to clock matching should be within [CLK-63.5mm] and [CLK+38.1mm] CLK intra-pair matching should be within 0.127mm, inter-pair matching should be within 0.0508mm CONTROL signals should be matched within [CLK-2.54mm] to [CLK+0.0mm] of CLK pairs A/BA/CMD signals should be matched within [CLK-12.7mm] to [CLK+12.7mm] of CLK pairs A/BA/CMD signals to each other should match within 5.08mm DQ/DQS/A/BA/cmd signal spacing is 4x dielectric, CLK is 5x dielectric Maximum length of any signal from die pad to SODIMM pad is 119.83mm, from procesor ball to SODIMM pad is 88.9mm SOURCE: Huron River Platform DG, Rev 1.01 (#436735), Section 2.5 MEM_B_DQ_BYTE1 TABLE_SPACING_ASSIGNMENT_ITEM MEM_DATA TABLE_SPACING_ASSIGNMENT_ITEM MEM_DQS MEM_DATA MEM_2OTHER TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_DQS MEM_50S TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_DQS SPACING_RULE_SET TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_DQS MEM_B_DQ_BYTE0 TABLE_SPACING_ASSIGNMENT_HEAD TABLE_SPACING_ASSIGNMENT_ITEM MEM_DQS MEM_CMD 11 29 MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ 11 29 11 28 11 28 11 28 11 28 B 11 28 11 28 11 28 11 28 TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM NET_SPACING_TYPE1 MEM_40S 11 29 TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CTRL MEM_B_CMD 11 29 TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CTRL MEM_CMD TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CTRL MEM_40S 11 29 TABLE_SPACING_ASSIGNMENT_HEAD TABLE_SPACING_ASSIGNMENT_ITEM * MEM_B_CMD MEM_CMD2CMD MEM_CMD TABLE_SPACING_ASSIGNMENT_HEAD MEM_CLK MEM_CMD TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CTRL MEM_CMD MEM_40S TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CLK MEM_40S MEM_B_CMD TABLE_SPACING_ASSIGNMENT_HEAD TABLE_SPACING_ASSIGNMENT_ITEM B MEM_B_CMD MEM_B_A MEM_B_BA MEM_B_RAS_L MEM_B_CAS_L MEM_B_WE_L MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N 11 28 11 28 11 28 11 28 11 28 11 28 11 28 11 28 11 28 11 28 11 28 11 28 11 28 11 28 SYNC_MASTER=K90I_MLB 11 28 SYNC_DATE=02/15/2011 PAGE TITLE Memory Constraints 11 28 DRAWING NUMBER Apple Inc 051-9058 R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED SIZE D REVISION 6.0.0 BRANCH PAGE 101 OF 109 SHEET 79 OF 86 A Digital Video Signal Constraints PCH Net Properties TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET ALLOW ROUTE ON LAYER? LAYER MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP NET_TYPE TABLE_PHYSICAL_RULE_ITEM DP_85D * =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF LVDS_90D * =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF SPACING_RULE_SET LAYER ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_HEAD LINE-TO-LINE SPACING TABLE_SPACING_RULE_HEAD WEIGHT SPACING_RULE_SET LAYER LINE-TO-LINE SPACING TABLE_SPACING_RULE_ITEM DP_PCH * =3x_DIELECTRIC ? DP_PCH_TX * =3x_DIELECTRIC ? TOP,BOTTOM =4x_DIELECTRIC ? DP_PCH_TX TOP,BOTTOM =4x_DIELECTRIC ? D =3x_DIELECTRIC LVDS_PCH_TX LVDS_90D LVDS_PCH_TX LVDS_90D LVDS_PCH_TX LVDS_90D LVDS_PCH_TX LVDS_PCH_TX TOP,BOTTOM =4x_DIELECTRIC ? LVDS_90D LVDS_PCH_TX LVDS_IG_A_DATA TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM * LVDS_90D LVDS_IG_A_CLK TABLE_SPACING_RULE_ITEM DP_PCH TABLE_SPACING_RULE_ITEM LVDS_PCH_TX LVDS_IG_A_CLK LVDS_IG_A_DATA WEIGHT LVDS_90D LVDS_PCH_TX I213 LVDS_90D LVDS_PCH_TX I214 LVDS_90D LVDS_PCH_TX I215 LVDS_90D LVDS_PCH_TX I216 LVDS_90D LVDS_PCH_TX SATA_HDD_R2D SATA_90D SATA3_PCH_TX TABLE_SPACING_RULE_ITEM ? SATA Interface Constraints LVDS_IG_A_CLK_P LVDS_IG_A_CLK_N LVDS_IG_A_DATA_P LVDS_IG_A_DATA_N LVDS_IG_A_DATA_P LVDS_IG_A_DATA_N LVDS_IG_B_DATA_P LVDS_IG_B_DATA_N LVDS_IG_B_CLK_P LVDS_IG_B_CLK_N 17 74 17 74 17 74 17 74 17 17 D 17 17 17 17 TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP SATA_90D * =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER * LINE-TO-LINE SPACING WEIGHT =3x_DIELECTRIC ? SPACING_RULE_SET * =3x_DIELECTRIC ? SATA_ICOMP * MIL ? SATA3_PCH_TX SATA_90D SATA3_PCH_TX LAYER LINE-TO-LINE SPACING WEIGHT =4x_DIELECTRIC ? SATA_HDD_R2D_CONN SATA_90D SATA3_PCH_TX SATA_HDD_D2R SATA_90D SATA3_PCH_RX SATA_HDD_D2R SATA_90D SATA3_PCH_RX SATA_HDD_D2R_CONN SATA_90D SATA3_PCH_RX SATA_HDD_D2R_CONN SATA_90D SATA3_PCH_RX SATA_ODD_R2D SATA_90D SATA_PCH_TX SATA_ODD_R2D SATA_90D SATA_PCH_TX SATA_ODD_R2D SATA_90D SATA_PCH_TX SATA_ODD_R2D SATA_90D SATA_PCH_TX SATA_ODD_D2R SATA_90D SATA_PCH_RX SATA_ODD_D2R SATA_90D SATA_PCH_RX SATA_HDD_R2D_CONN SATA_90D SATA3_PCH_TX SATA_HDD_R2D_CONN SATA_90D SATA3_PCH_TX SATA_HDD_D2R_CONN SATA_90D SATA3_PCH_RX SATA_HDD_D2R_CONN SATA_90D SATA3_PCH_RX USB_85D USB USB_85D USB USB_EXTA USB_85D USB USB_EXTA USB_85D USB USB_EXTB USB_85D USB USB_85D USB I219 USB_85D USB I220 USB_85D USB I221 USB_85D USB I222 USB_85D USB I223 USB_85D USB I224 USB_85D USB I225 USB_85D USB I226 USB_85D USB I247 USB_85D USB I248 USB_85D USB I250 USB_85D USB I249 USB_85D USB USB_85D USB3_PCH_RX USB_85D USB3_PCH_RX USB_85D USB3_PCH_TX USB_85D USB3_PCH_TX USB_85D USB3_PCH_RX USB_85D USB3_PCH_RX USB_85D USB3_PCH_TX I233 USB_85D USB3_PCH_TX I235 USB_85D USB3_PCH_RX I236 USB_85D USB3_PCH_RX I238 USB_85D USB3_PCH_TX I237 USB_85D USB3_PCH_TX I240 USB_85D USB3_PCH_RX I239 USB_85D USB3_PCH_RX I241 USB_85D USB3_PCH_TX I242 USB_85D USB3_PCH_TX I244 USB_85D USB3_PCH_TX I243 USB_85D USB3_PCH_TX I246 USB_85D USB3_PCH_TX I245 USB_85D USB3_PCH_TX USB_85D USB USB_85D USB USB_85D USB USB_85D USB USB_85D USB USB_85D USB USB_85D USB TABLE_SPACING_RULE_ITEM SATA_PCH_TX TOP,BOTTOM TABLE_SPACING_RULE_ITEM SATA_PCH_RX SATA_90D TABLE_SPACING_RULE_HEAD TABLE_SPACING_RULE_ITEM SATA_PCH_TX SATA_HDD_R2D SATA_HDD_R2D_CONN TABLE_SPACING_RULE_ITEM SATA_PCH_RX TOP,BOTTOM =4x_DIELECTRIC ? TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT =4X_DIELECTRIC ? TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT =5X_DIELECTRIC ? TABLE_SPACING_RULE_ITEM SATA3_PCH_TX2TX * TABLE_SPACING_RULE_ITEM SATA3_PCH_TX2TX TOP,BOTTOM TABLE_SPACING_RULE_ITEM SATA3_PCH_TX2RX * =5X_DIELECTRIC TABLE_SPACING_RULE_ITEM ? SATA3_PCH_TX2RX TOP,BOTTOM =6X_DIELECTRIC ? TABLE_SPACING_RULE_ITEM SATA3_PCH_RX2RX * =4x_DIELECTRIC TABLE_SPACING_RULE_ITEM ? SATA3_PCH_RX2RX TOP,BOTTOM =5x_DIELECTRIC ? TABLE_SPACING_RULE_ITEM SATA3_PCH_RX2TX * =5x_DIELECTRIC TABLE_SPACING_RULE_ITEM ? SATA3_PCH_RX2TX TOP,BOTTOM =6x_DIELECTRIC ? TABLE_SPACING_RULE_ITEM SATA3_PCH_2OTHER * =4x_DIELECTRIC TABLE_SPACING_RULE_ITEM ? SATA3_PCH_2OTHER TOP,BOTTOM =5x_DIELECTRIC PCH_SATA_ICOMP SATA_ICOMP ? USB_HUB1_UP C TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET TABLE_SPACING_ASSIGNMENT_ITEM SATA3_PCH_TX *_PCH_TX * SATA3_PCH_TX2TX SATA3_PCH_TX *_PCH_RX * SATA3_PCH_TX2RX SATA3_PCH_RX *_PCH_RX * SATA3_PCH_RX2RX TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM SATA3_PCH_RX *_PCH_TX * SATA3_PCH_RX2TX SATA3_PCH_TX * * SATA3_PCH_2OTHER TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM SATA3_PCH_RX * * SATA3_PCH_2OTHER SOURCE: 471984_Cheif_River_MS_PDG_1.0 and the spacing rule is adjusted per SI team feedback I228 USB3_EXT_RX I227 USB 2.0 Interface Constraints I229 USB3_EXT_TX TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET ALLOW ROUTE ON LAYER? LAYER MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP I230 DIFFPAIR NECK GAP I231 TABLE_PHYSICAL_RULE_ITEM PCH_USB_RBIAS * =STANDARD MIL MIL =STANDARD =STANDARD =STANDARD I232 TABLE_PHYSICAL_RULE_ITEM USB_85D * =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF B LAYER LINE-TO-LINE SPACING WEIGHT =2x_DIELECTRIC ? TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT =4x_DIELECTRIC ? TABLE_SPACING_RULE_ITEM USB * I234 =85_OHM_DIFF TABLE_SPACING_RULE_HEAD SPACING_RULE_SET USB3_EXT_RX USB3_EXT_TX TABLE_SPACING_RULE_ITEM USB TOP,BOTTOM SOURCE: Calpella Platform Design Guide for Ibex Peak M (DG-398905-398905_v1.5), Section 3.8 USB 3.0 Interface Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET ALLOW ROUTE ON LAYER? LAYER MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM USB_85D * =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LINE-TO-LINE SPACING WEIGHT USB3_PCH_TX2TX LAYER * =4X_DIELECTRIC ? USB3_PCH_TX2RX * =5X_DIELECTRIC ? SPACING_RULE_SET LINE-TO-LINE SPACING WEIGHT USB3_PCH_TX2TX TOP,BOTTOM LAYER =5X_DIELECTRIC ? USB3_PCH_TX2RX TOP,BOTTOM =6X_DIELECTRIC ? TABLE_SPACING_RULE_ITEM * =4x_DIELECTRIC ? * =5x_DIELECTRIC ? I252 USB_EXTC TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM USB3_PCH_RX2RX USB_EXTA USB3_PCH_RX2RX TOP,BOTTOM =5x_DIELECTRIC ? USB3_PCH_RX2TX TOP,BOTTOM =6x_DIELECTRIC ? USB_CAMERA TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM * =4x_DIELECTRIC TABLE_SPACING_RULE_ITEM ? USB3_PCH_2OTHER TOP,BOTTOM =5x_DIELECTRIC USB_CAMERA ? USB_85D USB USB_BT USB_85D USB USB_BT USB_85D USB I253 USB_BT USB_85D USB I254 USB_BT USB_85D USB USB_TPAD USB_85D USB USB_85D USB USB_85D USB USB_85D USB TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET USB3_PCH_TX *_PCH_TX * USB3_PCH_TX2TX TABLE_SPACING_ASSIGNMENT_ITEM A TABLE_SPACING_ASSIGNMENT_ITEM USB3_PCH_TX *_PCH_RX * USB3_PCH_TX2RX TABLE_SPACING_ASSIGNMENT_ITEM USB3_PCH_RX *_PCH_RX * USB_IR USB3_PCH_RX2RX TABLE_SPACING_ASSIGNMENT_ITEM USB3_PCH_RX *_PCH_TX * USB3_PCH_RX2TX USB3_PCH_TX * * USB3_PCH_2OTHER TABLE_SPACING_ASSIGNMENT_ITEM PCH_USB_RBIAS PCH_USB_RBIAS PCH_DIFFCLK_UNUSED_ CLK_PCIE_90D CLK_PCIE PCH_DIFFCLK_UNUSED_ CLK_PCIE_90D CLK_PCIE TABLE_SPACING_ASSIGNMENT_ITEM USB3_PCH_RX * * USB3_PCH_2OTHER SOURCE: 471984_Cheif_River_MS_PDG_1.0 and the spacing rule is adjusted per SI team feedback PCH_DIFFCLK_UNUSED_ CLK_PCIE_90D CLK_PCIE PCH_DIFFCLK_UNUSED_ CLK_PCIE_90D CLK_PCIE PCH_DIFFCLK_UNUSED_ CLK_PCIE_90D CLK_PCIE PCH_DIFFCLK_UNUSED_ CLK_PCIE_90D CLK_PCIE CPU_50S CLK_PCIE CPU_50S CLK_PCIE LPC_CLK33M USB_SMC_P USB_SMC_N 16 41 41 16 41 16 41 41 41 16 41 16 41 41 41 16 41 16 41 41 41 41 41 16 18 25 18 25 18 42 C 18 42 25 43 25 43 42 42 43 43 42 42 18 18 18 25 18 25 18 25 18 25 18 42 18 42 18 42 18 42 18 43 18 43 18 43 18 43 42 42 B 42 42 43 43 43 43 42 42 43 43 45 45 USB_EXTC_P USB_EXTC_N 18 18 TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM USB3_PCH_2OTHER USB3_EXTA_RX_P USB3_EXTA_RX_N USB3_EXTA_TX_P USB3_EXTA_TX_N USB3_EXTB_RX_P USB3_EXTB_RX_N USB3_EXTB_TX_P USB3_EXTB_TX_N USB3_EXTA_RX_F_P USB3_EXTA_RX_F_N USB3_EXTA_TX_F_P USB3_EXTA_TX_F_N USB3_EXTB_RX_F_P USB3_EXTB_RX_F_N USB3_EXTB_TX_F_P USB3_EXTB_TX_F_N USB3_EXTA_TX_C_P USB3_EXTA_TX_C_N USB3_EXTB_TX_C_P USB3_EXTB_TX_C_N 16 41 41 TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM USB3_PCH_RX2TX I251 TABLE_SPACING_RULE_HEAD SATA_HDD_R2D_C_P SATA_HDD_R2D_C_N SATA_HDD_R2D_P SATA_HDD_R2D_N SATA_HDD_D2R_P SATA_HDD_D2R_N SATA_HDD_D2R_C_P SATA_HDD_D2R_C_N SATA_ODD_R2D_C_P SATA_ODD_R2D_C_N SATA_ODD_R2D_P SATA_ODD_R2D_N SATA_ODD_D2R_P SATA_ODD_D2R_N SATA_HDD_R2D_RC_P SATA_HDD_R2D_RC_N SATA_HDD_D2R_RC_P SATA_HDD_D2R_RC_N PCH_SATAICOMP USB_HUB_UP_P USB_HUB_UP_N USB_EXTA_P USB_EXTA_N USB_EXTB_MUX_P USB_EXTB_MUX_N USB_EXTA_MUXED_F_P USB_EXTA_MUXED_F_N USB_EXTB_F_P USB_EXTB_F_N USB_EXTA_MUXED_P USB_EXTA_MUXED_N USB_EXTD_XHCI_P USB_EXTD_XHCI_N USB_EXTB_EHCI_P USB_EXTB_EHCI_N USB_EXTB_XHCI_P USB_EXTB_XHCI_N USB_CAMERA_P USB_CAMERA_N USB_CAMERA_CONN_P USB_CAMERA_CONN_N USB_BT_P USB_BT_N USB_BT_CONN_P USB_BT_CONN_N USB_TPAD_P USB_TPAD_N USB_IR_P USB_IR_N PCH_USB_RBIAS PCIE_CLK100M_PCH_P PCIE_CLK100M_PCH_N PCH_CLK96M_DOT_P PCH_CLK96M_DOT_N PCH_CLK100M_SATA_P PCH_CLK100M_SATA_N PCH_CLK14P3M_REFCLK PCH_CLK33M_PCIIN 18 32 18 32 32 32 32 32 32 32 53 53 SYNC_MASTER=K90I_MLB 44 SYNC_DATE=02/15/2011 PAGE TITLE PCH Constraints 44 18 DRAWING NUMBER 16 Apple Inc 16 16 16 051-9058 R NOTICE OF PROPRIETARY PROPERTY: SIZE D REVISION 6.0.0 BRANCH 16 16 16 16 24 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED PAGE 102 OF 109 SHEET 80 OF 86 A LPC Bus Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET ALLOW ROUTE ON LAYER? LAYER PCH Net Properties MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP Chipset Net Properties NET_TYPE DIFFPAIR NECK GAP ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING NET_TYPE TABLE_PHYSICAL_RULE_ITEM LPC_50S * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD ELECTRICAL_CONSTRAINT_SET TABLE_PHYSICAL_RULE_ITEM CLK_LPC_50S * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD LPC_AD LPC_50S LPC LPC_FRAME_L LPC_50S LPC LPC_RESET_L LPC_50S LPC LPC_CLK33M CLK_LPC_50S CLK_LPC LPC_CLK33M CLK_LPC_50S CLK_LPC =STANDARD LPC_AD LPC_FRAME_L LPC_RESET_L LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM LPC * MIL ? TABLE_SPACING_RULE_ITEM CLK_LPC D * MIL LPC_CLK33M CLK_LPC_50S CLK_LPC SMBUS_PCH_CLK SMB_50S SMB DP_EXTA_ML DP_85D DP_PCH_TX I251 DP_EXTA_ML DP_85D DP_PCH_TX 24 SMBus Interface Constraints SMBUS_PCH_DATA SMB_50S SMB LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP SMB_50S * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD TABLE_PHYSICAL_RULE_ITEM SMBUS_PCH_0_CLK SMB_50S SMB SMB_50S SMB SMBUS_SMC_B_S0_SCL SMB_50S SMB SMBUS_SMC_B_S0_SDA SMB_50S SMB HDA_BIT_CLK HDA_50S HDA HDA_50S HDA HDA_50S HDA HDA_50S HDA HDA_50S HDA HDA_50S HDA HDA_50S HDA HDA_50S HDA HDA_50S HDA HDA_50S HDA HDA_BIT_CLK HDA_BIT_CLK_R HDA_SYNC HDA_SYNC_R HDA_RST_R_L HDA_RST_L HDA_SDIN0 AUD_SDI_R HDA_SDOUT HDA_SDOUT_R CLK_SLOW_55S CLK_SLOW PM_CLK32K_SUSCLK TABLE_SPACING_RULE_HEAD LINE-TO-LINE SPACING WEIGHT HDA_SYNC TABLE_SPACING_RULE_ITEM SMB * =2x_DIELECTRIC ? HDA_RST_L HDA_SDIN0 HD Audio Interface Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET ALLOW ROUTE ON LAYER? LAYER MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP HDA_SDOUT TABLE_PHYSICAL_RULE_ITEM HDA_50S * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD SMBUS_PCH_CLK SMBUS_PCH_DATA SML_PCH_0_CLK SML_PCH_0_DATA SML_PCH_1_CLK SML_PCH_1_DATA SMBUS_PCH_0_DATA TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER I253 DP_85D DP_PCH_TX 18 24 I255 DP_85D DP_PCH_TX 24 45 I254 DP_EXTA_AUXCH DP_85D DP_PCH 24 47 I256 DP_EXTA_AUXCH ? SOURCE: Calpella Platform Design Guide for Ibex Peak M (DG-398905-398905_v1.5), Section 3.15 SPACING_RULE_SET LPC_CLK33M_SMC_R LPC_CLK33M_SMC LPC_CLK33M_LPCPLUS LAYER LINE-TO-LINE SPACING WEIGHT SPI_CLK TABLE_SPACING_RULE_ITEM HDA * =2x_DIELECTRIC SPI_MOSI SPI_MISO SIO Signal Constraints SPI_CS0 ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP C * =55_OHM_SE SPACING_RULE_SET LAYER =55_OHM_SE LINE-TO-LINE SPACING =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD WEIGHT TABLE_SPACING_RULE_ITEM * MIL SPI SPI_50S SPI SPI I288 SPI_50S SPI I289 SPI_50S SPI I290 SPI_50S SPI I291 SPI_50S SPI I292 SPI_50S SPI ? I293 SPI_50S SPI I294 SPI_50S SPI I295 SPI_50S SPI TABLE_PHYSICAL_RULE_HEAD ALLOW ROUTE ON LAYER? LAYER SPI SPI_50S SPI SPI Interface Constraints PHYSICAL_RULE_SET SPI_50S SPI_50S TABLE_SPACING_RULE_HEAD CLK_SLOW SPI DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM CLK_SLOW_55S SPI_50S SPI_50S TABLE_PHYSICAL_RULE_HEAD LAYER SPI ? SOURCE: Calpella Platform Design Guide for Ibex Peak M (DG-398905-398905_v1.5), Section 3.15 PHYSICAL_RULE_SET SPI_50S MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP PCIE_85D PCIE_PCH_TX PCIE_85D PCIE_PCH_TX DIFFPAIR NECK GAP PCIE_ENET_R2D PCIE_85D PCIE_PCH_TX TABLE_PHYSICAL_RULE_ITEM SPI_50S * =50_OHM_SE SPACING_RULE_SET LAYER =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD PCIE_85D PCIE_PCH_TX PCIE_85D PCIE_PCH_RX PCIE_85D PCIE_PCH_RX PCIE_85D PCIE_PCH_RX PCIE_85D PCIE_PCH_RX PCIE_85D PCIE_PCH_TX PCIE_85D PCIE_PCH_TX PCIE_85D PCIE_PCH_TX PCIE_85D PCIE_PCH_TX PCIE_85D PCIE_PCH_RX PCIE_85D PCIE_PCH_RX PCIE_85D PCIE_PCH_TX PCIE_85D PCIE_PCH_TX PCIE_85D PCIE_PCH_TX PCIE_85D PCIE_PCH_TX PCIE_85D PCIE_PCH_RX PCIE_85D PCIE_PCH_RX PCIE_85D PCIE_PCH_RX PCIE_85D PCIE_PCH_RX PCIE_85D PCIE_PCH_RX PCIE_85D PCIE_PCH_RX PCIE_85D PCIE_PCH_RX PCIE_85D PCIE_PCH_RX CLK_PCIE_90D CLK_PCIE CLK_PCIE_90D CLK_PCIE CLK_PCIE_90D CLK_PCIE CLK_PCIE_90D CLK_PCIE CLK_PCIE_90D CLK_PCIE CLK_PCIE_90D CLK_PCIE CLK_PCIE_90D CLK_PCIE CLK_PCIE_90D CLK_PCIE CLK_PCIE_90D CLK_PCIE CLK_PCIE_90D CLK_PCIE I235 CPU_27P4S CPU_COMP I236 CPU_27P4S CPU_COMP I237 CPU_27P4S CPU_COMP I238 CPU_27P4S CPU_COMP I239 CPU_27P4S CPU_COMP I240 CPU_27P4S CPU_COMP I241 CPU_27P4S CPU_COMP I242 CPU_27P4S CPU_COMP I243 CPU_27P4S CPU_COMP I244 CPU_27P4S CPU_COMP I245 CPU_27P4S CPU_COMP I246 CPU_27P4S CPU_COMP I247 CPU_27P4S CPU_COMP I248 CPU_27P4S CPU_COMP I249 CPU_27P4S CPU_COMP I250 CPU_27P4S CPU_COMP PCIE_ENET_D2R TABLE_SPACING_RULE_HEAD LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM SPI * MIL ? PCIE_AP_R2D PCIE_AP_D2R PCIE_FW_R2D B PCI-Express Signal Constraints PCIE_FW_D2R TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING TABLE_SPACING_RULE_HEAD WEIGHT SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM PCIE_T29_TX2TX * =3X_DIELECTRIC ? PCIE_T29_TX2RX * =4X_DIELECTRIC ? PCIE_T29_RX2RX * =3x_DIELECTRIC ? TABLE_SPACING_RULE_ITEM PCIE_T29_TX2TX TOP,BOTTOM =4X_DIELECTRIC ? PCIE_T29_TX2RX TOP,BOTTOM =5X_DIELECTRIC ? PCIE_T29_RX2RX TOP,BOTTOM =4x_DIELECTRIC ? TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM PCIE_T29_RX2TX * =4x_DIELECTRIC ? PCIE_T29_2OTHER * =3x_DIELECTRIC ? PCIE_AP_D2R PCIE_AP_R2D TABLE_SPACING_RULE_ITEM PCIE_T29_RX2TX TOP,BOTTOM =4x_DIELECTRIC ? PCIE_T29_2OTHER TOP,BOTTOM =4x_DIELECTRIC ? TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM PCIE_CLK100M_ENET TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET MCP_PE1_REFCLK TABLE_SPACING_ASSIGNMENT_ITEM PCIE_T29_TX *_TX * PCIE_T29_TX2TX TABLE_SPACING_ASSIGNMENT_ITEM PCIE_T29_TX *_RX * MCP_PE2_REFCLK PCIE_T29_TX2RX TABLE_SPACING_ASSIGNMENT_ITEM PCIE_T29_RX *_RX * PCIE_T29_RX2RX TABLE_SPACING_ASSIGNMENT_ITEM PCIE_T29_RX *_TX * PCIE_T29_RX2TX PCIE_T29_TX * * PCIE_T29_2OTHER PCIE_T29_RX * * PCIE_T29_2OTHER SPI_CLK_R SPI_CLK SPI_MOSI_R SPI_MOSI SPI_MISO SPI_CS0_R_L SPI_CS0_L SPI_MLB_CLK SPI_MLB_CS_L SPI_MLB_MOSI SPI_MLB_MISO SPI_SMC_MISO SPI_SMC_MOSI SPI_SMC_CLK SPI_SMC_CS_L PCIE_ENET_R2D_P PCIE_ENET_R2D_N PCIE_ENET_R2D_C_P PCIE_ENET_R2D_C_N PCIE_ENET_D2R_P PCIE_ENET_D2R_N PCIE_ENET_D2R_C_P PCIE_ENET_D2R_C_N PCIE_AP_R2D_P PCIE_AP_R2D_N PCIE_AP_R2D_C_P PCIE_AP_R2D_C_N PCIE_AP_D2R_P PCIE_AP_D2R_N PCIE_FW_R2D_P PCIE_FW_R2D_N PCIE_FW_R2D_C_P PCIE_FW_R2D_C_N PCIE_FW_D2R_P PCIE_FW_D2R_N PCIE_FW_D2R_C_P PCIE_FW_D2R_C_N PCIE_AP_D2R_PI_P PCIE_AP_D2R_PI_N PCIE_AP_R2D_PI_P PCIE_AP_R2D_PI_N PEG_CLK100M_P PEG_CLK100M_N PCIE_CLK100M_ENET_P PCIE_CLK100M_ENET_N PCIE_CLK100M_AP_P PCIE_CLK100M_AP_N PCIE_CLK100M_FW_P PCIE_CLK100M_FW_N PCIE_CLK100M_EXCARD_P PCIE_CLK100M_EXCARD_N DP_PCH DP_85D DP_PCH I258 DP_85D DP_PCH DP_EXTA_ML_C_P DP_EXTA_ML_C_N DP_EXTA_ML_P DP_EXTA_ML_N DP_EXTA_AUXCH_C_P DP_EXTA_AUXCH_C_N DP_EXTA_AUXCH_P DP_EXTA_AUXCH_N 75 75 75 75 75 75 75 D 75 16 48 16 48 16 48 16 48 16 48 16 57 16 16 57 16 16 16 57 16 57 57 16 57 16 24 I271 PCIE_T29_R2D PCIE_85D PCIE_T29_RX I273 PCIE_T29_R2D PCIE_85D PCIE_T29_RX PCIE_85D PCIE_T29_RX I272 PCIE_T29_R2D 16 47 I274 PCIE_T29_R2D PCIE_85D PCIE_T29_RX 47 I276 PCIE_T29_D2R PCIE_85D PCIE_T29_TX 16 47 I275 PCIE_T29_D2R PCIE_85D PCIE_T29_TX 47 I277 PCIE_T29_D2R PCIE_85D PCIE_T29_TX 16 47 I278 PCIE_T29_D2R PCIE_85D PCIE_T29_TX I279 PCIE_CLK100M_T29 CLK_PCIE_90D CLK_PCIE I280 PCIE_CLK100M_T29 CLK_PCIE_90D CLK_PCIE TABLE_SPACING_RULE_HEAD SPACING_RULE_SET DP_85D I257 16 48 =STANDARD PM_SUS_CLK SPACING I252 16 45 47 TABLE_SPACING_RULE_HEAD SPACING_RULE_SET PHYSICAL 16 45 47 16 47 47 PCIE_T29_R2D_C_P PCIE_T29_R2D_C_N PCIE_T29_R2D_P PCIE_T29_R2D_N PCIE_T29_D2R_P PCIE_T29_D2R_N PCIE_T29_D2R_C_P PCIE_T29_D2R_C_N 33 33 33 33 33 33 33 33 PCIE_CLK100M_T29_P PCIE_CLK100M_T29_N 16 33 16 33 46 47 56 46 47 56 C 46 47 56 46 47 56 Clock Net Properties NET_TYPE 45 46 45 46 ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING 45 46 I281 SYSCLK_CLK32K_RTC CLK_SLOW_55S CLK_SLOW SYSCLK_CLK32K_RTC I282 SYSCLK_CLK25M_SB CLK_25M_55S CLK_25M I283 CLK_25M_55S CLK_25M I284 CLK_25M_55S CLK_25M I285 CLK_25M_55S CLK_25M CLK_25M_55S CLK_25M CLK_25M_55S CLK_25M SYSCLK_CLK25M_SB SYSCLK_CLK25M_SB_R SYSCLK_CLK25M_ENET SYSCLK_CLK25M_ENET_R SYSCLK_CLK25M_T29 SYSCLK_CLK25M_T29_R 16 24 45 46 36 36 16 36 16 36 I286 SYSCLK_CLK25M_T29 16 36 I287 16 24 16 24 36 24 33 33 16 36 36 36 32 32 16 32 16 32 16 32 16 32 38 38 16 38 16 38 16 38 B 16 38 38 38 32 32 16 16 16 36 16 36 16 32 16 32 16 38 16 38 16 16 TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM SOURCE: 471984_Cheif_River_MS_PDG_1.0 and the spacing rule is adjusted per SI team feedback A System Clock Signal Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP CLK_SLOW_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM CLK_25M_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT PCH_VSS_NCTF PCH_VSS_NCTF PCH_VSS_NCTF TP_PCH_VSS_NCTF PCH_VSS_NCTF PCH_VSS_NCTF PCH_VSS_NCTF PCH_VSS_NCTF PCH_VSS_NCTF PCH_VSS_NCTF PCH_VSS_NCTF PCH_VSS_NCTF PCH_VSS_NCTF PCH_VSS_NCTF PCH_VSS_NCTF PCH_VSS_NCTF 6 6 81 81 6 SYNC_MASTER=K90I_MLB PCH Constraints DRAWING NUMBER Apple Inc * =2x_DIELECTRIC ? CLK_25M * =5x_DIELECTRIC ? NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED NOTE: 25MHz system clocks very sensitive to noise SIZE D 6.0.0 BRANCH TABLE_SPACING_RULE_ITEM 051-9058 REVISION R TABLE_SPACING_RULE_ITEM CLK_SLOW SYNC_DATE=02/15/2011 PAGE TITLE PAGE 103 OF 109 SHEET 81 OF 86 A CAESAR IV (Ethernet) Constraints Ethernet Net Properties TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP ENET_50S * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD NET_TYPE ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING TABLE_PHYSICAL_RULE_ITEM ENET_50S ENET_3X ENET_50S ENET_3X TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT =3:1_SPACING ? ENET_50S ENET_3X ENET_100D ENET_MDI ENET_100D ENET_MDI BCM5764_CLK25M_XTALI BCM5764_CLK25M_XTALO ENET_RESET_L 30 36 ENET_MDI_P ENET_MDI_N 36 37 TABLE_SPACING_RULE_ITEM ENET_3X * ENET_MDI 36 37 SOURCE: Broadcom 5764-DS04-RDS Page 38 TABLE_SPACING_RULE_HEAD SPACING_RULE_SET D LAYER LINE-TO-LINE SPACING WEIGHT 8MIL ? I166 CR_DATA ENET_50S ENET_CR_DATA I167 CR_DATA ENET_50S ENET_CR_DATA I168 CR_CLK ENET_50S ENET_CR_DATA I169 CR_DATA ENET_50S ENET_CR_DATA I170 CR_DATA ENET_50S ENET_CR_DATA I171 CR_CLK ENET_50S ENET_CR_DATA I172 CR_CLK ENET_50S ENET_CR_DATA TABLE_SPACING_RULE_ITEM ENET_CR_DATA * CAESAR IV (Ethernet PHY) Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? ENET_100D * =100_OHM_DIFF SPACING_RULE_SET LAYER MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF ENET_CR_DATA ENET_CR_CMD ENET_CR_CLK SDCONN_DATA SDCONN_CMD SDCONN_CLK SDCONN_CLK_L D 30 36 30 36 30 36 TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_HEAD LINE-TO-LINE SPACING WEIGHT 0.6 MM ? TABLE_SPACING_RULE_ITEM * ENET_MDI SOURCE: Broadcom 5764-DS04-RDS Page 38 C FireWire Interface Constraints C FireWire Net Properties TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP FW_110D * =110_OHM_DIFF =110_OHM_DIFF =110_OHM_DIFF =110_OHM_DIFF =110_OHM_DIFF =110_OHM_DIFF NET_TYPE ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT I158 FW_P0_TPA FW_110D FW_TP I159 FW_P0_TPA FW_110D FW_TP I160 FW_P0_TPB FW_110D FW_TP I161 FW_P0_TPB FW_110D FW_TP I162 FW_P1_TPA FW_110D FW_TP I163 FW_P1_TPA FW_110D FW_TP I164 FW_P1_TPB FW_110D FW_TP I165 FW_P1_TPB FW_110D FW_TP TABLE_SPACING_RULE_ITEM FW_TP * =3:1_SPACING ? FW_P0_TPA_P FW_P0_TPA_N FW_P0_TPB_P FW_P0_TPB_N FW_P1_TPA_P FW_P1_TPA_N FW_P1_TPB_P FW_P1_TPB_N 38 40 38 40 38 40 38 40 38 40 38 40 38 40 38 40 Port Not Used B B A SYNC_MASTER=K90I_MLB SYNC_DATE=02/15/2011 PAGE TITLE Ethernet/FW Constraints DRAWING NUMBER Apple Inc 051-9058 R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED SIZE D REVISION 6.0.0 BRANCH PAGE 104 OF 109 SHEET 82 OF 86 A DisplayPort Signal Constraints ELECTRICAL_CONSTRAINT_SET T29 I2C Signal Constraints I1 TABLE_PHYSICAL_RULE_HEAD LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP I2 TABLE_PHYSICAL_RULE_ITEM T29_I2C_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =55_OHM_SE I3 =STANDARD I4 LAYER LINE-TO-LINE SPACING WEIGHT =2x_DIELECTRIC ? I7 TABLE_SPACING_RULE_ITEM T29_I2C * T29_R2D0 T29_R2D0 T29_R2D1 T29_R2D1 I5 TABLE_SPACING_RULE_HEAD SPACING_RULE_SET I6 I8 D T29 SPI Signal Constraints I9 I10 T29_D2R0 T29_D2R0 T29_D2R1 T29_D2R1 TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP T29_SPI_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD I11 I12 TABLE_PHYSICAL_RULE_ITEM I13 I15 TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT I14 TABLE_SPACING_RULE_ITEM T29_SPI * I17 ? =2x_DIELECTRIC I16 I18 T29/DP Connector Signal Constraints I19 TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP T29DP_80D * =80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF I20 I21 TABLE_PHYSICAL_RULE_ITEM I22 DP_SDRVA_ML_EVEN DP_SDRVA_ML_EVEN DP_SDRVA_ML_ODD DP_SDRVA_ML_ODD DP_SDRVA_AUXCH DP_SDRVA_AUXCH TABLE_PHYSICAL_RULE_ITEM T29DP_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF I23 =100_OHM_DIFF I24 TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING TABLE_SPACING_RULE_HEAD WEIGHT SPACING_RULE_SET LAYER LINE-TO-LINE SPACING * =5x_DIELECTRIC I25 WEIGHT TABLE_SPACING_RULE_ITEM T29DP I26 TABLE_SPACING_RULE_ITEM ? T29DP TOP,BOTTOM =7x_DIELECTRIC ? I27 I28 I30 I29 SOURCE: Bill Cornelius’s T29 Routing Notes I31 I32 C I34 I33 T29_R2D2 T29_R2D2 T29_R2D3 T29_R2D3 I35 I36 I37 I39 I38 I40 T29_D2R2 T29_D2R2 T29_D2R3 T29_D2R3 I41 I42 I43 I44 I46 I45 I47 I48 I49 I50 I51 I52 DP_SDRVB_ML_EVEN DP_SDRVB_ML_EVEN DP_SDRVB_ML_ODD DP_SDRVB_ML_ODD DP_SDRVB_AUXCH DP_SDRVB_AUXCH I53 I54 I55 I56 I57 B T29 IC Net Properties ELECTRICAL_CONSTRAINT_SET I62 I61 I63 I64 DP_T29SNK0_ML DP_T29SNK0_ML I65 I66 I67 I68 DP_T29SNK0_AUXCH DP_T29SNK0_AUXCH I69 I70 I71 I72 DP_T29SNK1_ML DP_T29SNK1_ML I74 I73 I75 I76 DP_T29SNK1_AUXCH DP_T29SNK1_AUXCH I77 I78 I79 I80 A I81 I82 I83 I84 I85 I86 T29_SPI_CLK T29_SPI_MOSI T29_SPI_MISO T29_SPI_CS_L I87 I88 I89 I90 I58 I59 NET_TYPE PHYSICAL SPACING I60 DP_85D DP_85D DP_85D DP_85D DP_85D DP_85D DP_85D DP_85D DP_PCH_TX DP_PCH_TX DP_PCH_TX DP_PCH_TX DP_PCH DP_PCH DP_PCH DP_PCH DP_T29SNK0_ML_C_P DP_T29SNK0_ML_C_N DP_T29SNK0_ML_P DP_T29SNK0_ML_N DP_T29SNK0_AUXCH_C_P DP_T29SNK0_AUXCH_C_N DP_T29SNK0_AUXCH_P DP_T29SNK0_AUXCH_N DP_85D DP_85D DP_85D DP_85D DP_85D DP_85D DP_85D DP_85D DP_PCH_TX DP_PCH_TX DP_PCH_TX DP_PCH_TX DP_PCH DP_PCH DP_PCH DP_PCH DP_T29SNK1_ML_C_P DP_T29SNK1_ML_C_N DP_T29SNK1_ML_P DP_T29SNK1_ML_N DP_T29SNK1_AUXCH_C_P DP_T29SNK1_AUXCH_C_N DP_T29SNK1_AUXCH_P DP_T29SNK1_AUXCH_N DP_85D DP_85D DP_85D DP_85D DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DP_T29SRC_ML_C_P DP_T29SRC_ML_C_N DP_T29SRC_AUXCH_C_P DP_T29SRC_AUXCH_C_N T29_I2C_55S T29_I2C_55S T29_I2C T29_I2C I2C_T29_SCL I2C_T29_SDA T29_SPI_55S T29_SPI_55S T29_SPI_55S T29_SPI_55S T29_SPI T29_SPI T29_SPI T29_SPI T29_SPI_CLK T29_SPI_MOSI T29_SPI_MISO T29_SPI_CS_L T29DP_80D T29DP_80D T29DP_100D T29DP_100D T29DP T29DP T29DP T29DP T29_R2D_C_P T29_R2D_C_N T29_D2R_P T29_D2R_N T29/DP Net Properties NOTE: DisplayPort Physical/Spacing Constraints provided by Chipset or GPU page PHYSICAL_RULE_SET NET_TYPE PHYSICAL SPACING T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_100D T29DP_100D T29DP_100D T29DP_100D T29DP_100D T29DP_100D T29DP T29DP T29DP T29DP T29DP T29DP T29DP T29DP T29DP T29DP T29DP T29DP T29_R2D_P T29_R2D_N T29_R2D_P T29_R2D_N T29_R2D_C_F_P T29_R2D_C_F_N T29_D2R_C_P T29_D2R_C_N T29_D2R_C_P T29_D2R_C_N T29DPA_D2R1_AUXCH_P T29DPA_D2R1_AUXCH_N T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP T29DP T29DP T29DP T29DP T29DP T29DP T29DP T29DP T29DP T29DP T29DP DP_SDRVA_ML_C_P DP_SDRVA_ML_C_N DP_SDRVA_ML_R_P DP_SDRVA_ML_R_N DP_SDRVA_ML_P DP_SDRVA_ML_N DP_SDRVA_ML_P DP_SDRVA_ML_N DP_SDRVA_AUXCH_P DP_SDRVA_AUXCH_N DP_SDRVA_AUXCH_C_P DP_SDRVA_AUXCH_C_N T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP T29DP T29DP T29DP T29DP T29DP T29DPA_ML_P T29DPA_ML_N T29DPA_ML_C_P T29DPA_ML_C_N DP_A_EXT_AUXCH_P DP_A_EXT_AUXCH_N T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_100D T29DP_100D T29DP_100D T29DP_100D T29DP_100D T29DP_100D T29DP T29DP T29DP T29DP T29DP T29DP T29DP T29DP T29DP T29DP T29DP T29DP T29_R2D_P T29_R2D_N T29_R2D_P T29_R2D_N T29_R2D_C_F_P T29_R2D_C_F_N T29_D2R_C_P T29_D2R_C_N T29_D2R_C_P T29_D2R_C_N T29DPB_D2R3_AUXCH_P T29DPB_D2R3_AUXCH_N T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP T29DP T29DP T29DP T29DP T29DP T29DP T29DP T29DP T29DP T29DP T29DP DP_SDRVB_ML_C_P DP_SDRVB_ML_C_N DP_SDRVB_ML_R_P DP_SDRVB_ML_R_N DP_SDRVB_ML_P DP_SDRVB_ML_N DP_SDRVB_ML_P DP_SDRVB_ML_N DP_SDRVB_AUXCH_P DP_SDRVB_AUXCH_N DP_SDRVB_AUXCH_C_P DP_SDRVB_AUXCH_C_N T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP T29DP T29DP T29DP T29DP T29DP T29DPB_ML_P T29DPB_ML_N T29DPB_ML_C_P T29DPB_ML_C_N DP_B_EXT_AUXCH_P DP_B_EXT_AUXCH_N 75 75 75 75 75 76 75 76 D 75 76 75 76 76 76 75 75 75 75 75 83 75 83 75 75 75 75 75 75 75 76 75 76 75 76 75 76 75 76 75 76 C Only used on dual-port hosts 83 83 B 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 Only used on hosts supporting T29 video-in 33 48 SYNC_MASTER=K90I_MLB 33 48 SYNC_DATE=02/15/2011 PAGE TITLE T29 Constraints 33 DRAWING NUMBER 33 Apple Inc 33 33 051-9058 R NOTICE OF PROPRIETARY PROPERTY: SIZE D REVISION 6.0.0 BRANCH 33 75 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED 33 75 33 75 33 75 PAGE 105 OF 109 SHEET 83 OF 86 A SMC SMBus Net Properties TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 1TO1_DIFFPAIR * =STANDARD =STANDARD =STANDARD =STANDARD 0.1 MM 0.1 MM NET_TYPE ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING TABLE_PHYSICAL_RULE_ITEM D SMBUS_SMC_A_S3_SCL SMB_50S SMB SMBUS_SMC_A_S3_SDA SMB_50S SMB SMBUS_SMC_B_S0_SCL SMB_50S SMB SMBUS_SMC_B_S0_SDA SMB_50S SMB SMBUS_SMC_0_S0_SCL SMB_50S SMB SMBUS_SMC_0_S0_SDA SMB_50S SMB SMBUS_SMC_BSA_SCL SMB_50S SMB SMBUS_SMC_BSA_SDA SMB_50S SMB SMBUS_SMC_MGMT_SCL SMB_50S SMB SMBUS_SMC_MGMT_SDA SMB_50S SMB SMBUS_SMC_2_S3_SCL SMBUS_SMC_2_S3_SDA SMBUS_SMC_1_S0_SCL SMBUS_SMC_1_S0_SDA SMBUS_SMC_0_S0_SCL SMBUS_SMC_0_S0_SDA SMBUS_SMC_5_G3_SCL SMBUS_SMC_5_G3_SDA SMBUS_SMC_3_SCL SMBUS_SMC_3_SDA 45 48 45 48 45 48 45 48 45 48 45 48 45 48 45 48 D 45 48 45 48 SMBus Charger Net Properties NET_TYPE ELECTRICAL_CONSTRAINT_SET PHYSICAL CHGR_CSI 1TO1_DIFFPAIR 1TO1_DIFFPAIR CHGR_CSO 1TO1_DIFFPAIR 1TO1_DIFFPAIR SPACING CHGR_CSI_P CHGR_CSI_N 64 64 CHGR_CSO_P CHGR_CSO_N 64 64 C C B B A SYNC_MASTER=K90I_MLB SYNC_DATE=02/15/2011 PAGE TITLE SMC Constraints DRAWING NUMBER Apple Inc 051-9058 R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED SIZE D REVISION 6.0.0 BRANCH PAGE 106 OF 109 SHEET 84 OF 86 A TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET ALLOW ROUTE ON LAYER? LAYER MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP J30 Specific Net Properties J30 Specific Net Properties NET_TYPE NET_TYPE TABLE_PHYSICAL_RULE_ITEM SENSE_1TO1_55S * =55_OHM_SE =1:1_DIFFPAIR =55_OHM_SE =55_OHM_SE =1:1_DIFFPAIR =1:1_DIFFPAIR ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING THERM_1TO1_55S * =55_OHM_SE =1:1_DIFFPAIR =55_OHM_SE =55_OHM_SE =1:1_DIFFPAIR ELECTRICAL_CONSTRAINT_SET ENET_100D ENETCONN ENETCONN_P 37 ENET_100D ENETCONN ENETCONN_N 37 SATA_90D SATA_PCH_RX SATA_ODD_D2R_C_P 41 SATA_90D SATA_PCH_RX SATA_ODD_D2R_C_N 41 SATA_90D SATA3_PCH_RX SATA_HDD_D2R_RDROUT_P 41 SATA_90D SATA3_PCH_RX SATA_HDD_D2R_RDROUT_N 41 SATA3_PCH_TX SATA_HDD_R2D_RDRIN_P 41 TABLE_PHYSICAL_RULE_ITEM PHYSICAL SPACING =1:1_DIFFPAIR TABLE_PHYSICAL_RULE_ITEM DIFFPAIR * =1:1_DIFFPAIR =1:1_DIFFPAIR =1:1_DIFFPAIR =1:1_DIFFPAIR PCIE_CLK100M_AP TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET WEIGHT SATA_90D TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_RULE_ITEM D SENSE * =2:1_SPACING ? THERM * =2:1_SPACING ? CPU_COMP GND * SATA_90D GND_P2MM GND * SATA_HDD_R2D_RDRIN_N CLK_PCIE PCIE_CLK100M_AP_CONN_P PCIE_CLK100M_AP_CONN_N CHGR_CSI_R_P CHGR_CSI_R_N CHGR_CSO_R_P CHGR_CSO_R_N 41 SATA_90D SATA3_PCH_TX SATA_HDD_D2R_RDRIN_P 41 I298 SATA_90D SATA3_PCH_TX SATA_HDD_D2R_RDRIN_N 41 I297 SATA_90D SATA3_PCH_TX SATA_HDD_R2D_RDROUT_P 41 SATA_90D SATA3_PCH_TX SATA_HDD_R2D_RDROUT_N THERM_1TO1_55S THERM THMSNS_D1_P 51 THERM_1TO1_55S THERM THMSNS_D1_N 51 THERM_1TO1_55S THERM THMSNS_D2_P 51 THERM_1TO1_55S THERM THMSNS_D2_N 51 T29_THERMD_P 51 51 1TO1_DIFFPAIR GND_P2MM ? =2:1_SPACING SATA3_PCH_TX I295 TABLE_SPACING_ASSIGNMENT_ITEM CPU_VCCSENSE TABLE_SPACING_RULE_ITEM * CLK_PCIE CLK_PCIE_90D 1TO1_DIFFPAIR TABLE_SPACING_RULE_ITEM AUDIO CLK_PCIE_90D 1TO1_DIFFPAIR I296 SENSE_DIFFPAIR 1TO1_DIFFPAIR 32 32 64 D 64 64 64 41 TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT 25 MILS ? TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 TABLE_SPACING_RULE_ITEM ENETCONN * NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET I287 I288 TABLE_SPACING_ASSIGNMENT_ITEM ENET_MDI GND * SENSE_DIFFPAIR SENSE_DIFFPAIR THERM_1TO1_55S THERM THERM_1TO1_55S THERM T29_THERMD_N SENSE_DIFFPAIR THERM_1TO1_55S THERM T29THMSNS_D2_P THERM_1TO1_55S THERM T29THMSNS_D2_N SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE GND_P2MM TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM GND * =STANDARD TABLE_SPACING_ASSIGNMENT_HEAD ? NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET GND CLK_PCIE * GND_P2MM GND PCIE* * GND_P2MM GND SATA* * GND_P2MM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM SENSE_DIFFPAIR TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT SENSE_DIFFPAIR TABLE_SPACING_RULE_ITEM GND_P2MM * 0.20 MM TABLE_SPACING_ASSIGNMENT_ITEM 1000 GND USB* * GND_P2MM TABLE_SPACING_RULE_ITEM PWR_P2MM * 0.20 MM ISNS_HS_COMPUTING_N ISNS_HS_COMPUTING_P 50 50 TABLE_SPACING_ASSIGNMENT_ITEM SENSE_DIFFPAIR TABLE_SPACING_ASSIGNMENT_ITEM 1000 SB_POWER CLK_PCIE * PWR_P2MM SENSE_1TO1_55S SENSE ISNS_HS_OTHER_N ISNS_HS_OTHER_P CPUVCCIOS0_CS_N CPUVCCIOS0_CS_P 50 50 SPK_OUT DIFFPAIR AUDIO 49 70 SPK_OUT DIFFPAIR AUDIO 49 70 SPK_OUT DIFFPAIR AUDIO SPK_OUT DIFFPAIR AUDIO SPK_OUT DIFFPAIR AUDIO TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SB_POWER SATA* * SPKRAMP_L_P_OUT SPKRAMP_L_N_OUT SPKRAMP_SUB_P_OUT SPKRAMP_SUB_N_OUT SPKRAMP_R_P_OUT SPKRAMP_R_N_OUT SSM2315_SUB_N SSM2315_SUB_P SSM2315_L_N SSM2315_L_P SSM2315_R_N SSM2315_R_P AUD_LO2_N_R AUD_LO2_P_R AUD_LO1_N_R AUD_LO1_P_R AUD_LO2_N_L AUD_LO2_P_L SPKRAMP_INL_P SPKRAMP_INL_N SPKRAMP_INR_P SPKRAMP_INR_N SPKRAMP_INSUB_P SPKRAMP_INSUB_N PWR_P2MM SPACING_RULE_SET TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CLK GND * GND_P2MM MEM_CMD GND * GND_P2MM SB_POWER SATA* * PWR_P2MM MEM_CTRL GND * GND_P2MM GND * GND_P2MM SENSE_1TO1_55S SENSE CPUIMVP_ISNS1_P 49 68 69 SENSE_1TO1_55S SENSE I299 SENSE CPUIMVP_ISNS1_N CPUIMVP_ISNS2_P 49 69 SENSE_1TO1_55S 49 68 69 I300 SENSE_1TO1_55S SENSE CPUIMVP_ISNS2_N 49 69 SENSE_1TO1_55S SENSE SENSE CPUIMVP_ISNS1G_P CPUIMVP_ISNS1G_N 49 69 SENSE_1TO1_55S 49 69 SENSE_1TO1_55S SENSE CPUIMVP_ISNS2G_P 49 69 SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE CPUIMVP_ISUM_R_N CPUIMVP_ISUMG_R_P SENSE_1TO1_55S SENSE CPUIMVP_ISUMG_R_N 49 SENSE_1TO1_55S SENSE CPUIMVP_ISNSG_P 49 I309 SENSE_1TO1_55S SENSE CPUIMVP_ISNSG_N 49 SENSE_1TO1_55S SENSE CPUIMVP_ISNS_P 49 SENSE_1TO1_55S SENSE CPUIMVP_ISNS_N 49 I313 SENSE_1TO1_55S SENSE VCCSAS0_CS_P 65 SENSE_1TO1_55S SENSE VCCSAS0_CS_N 65 SENSE_1TO1_55S SENSE CPUIMVP_ISUMG_P SENSE_1TO1_55S SENSE CPUIMVP_ISUMG_N 68 69 SENSE_DIFFPAIR SENSE_1TO1_55S SENSE CPU_THERMD_P SENSE_1TO1_55S SENSE USB USB_TPAD_R_P USB_TPAD_R_N SENSE_DIFFPAIR SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE ISNS_5V_S0_HDD_P 49 SB_POWER PP3V3_S5 SENSE_1TO1_55S SENSE ISNS_5V_S0_HDD_R_N 49 SB_POWER PP3V3_S0 SENSE_1TO1_55S SENSE ISNS_5V_S0_HDD_R_P 49 SB_POWER PP1V5_S3RS0 SENSE_1TO1_55S SENSE ISNS_LCDBKLT_N SENSE_1TO1_55S SENSE ISNS_LCDBKLT_P SENSE_1TO1_55S SENSE ISNS_1V5_S3_DDR_P 49 SENSE_1TO1_55S SENSE ISNS_1V5_S3_DDR_N 49 49 SENSE_DIFFPAIR TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET TABLE_SPACING_ASSIGNMENT_ITEM MEM_DQS GND * TABLE_SPACING_ASSIGNMENT_ITEM GND_P2MM GND LVDS* * GND_P2MM I317 SENSE_DIFFPAIR I318 SENSE_DIFFPAIR SENSE_DIFFPAIR I322 SENSE_DIFFPAIR I321 SENSE_DIFFPAIR I249 SENSE_DIFFPAIR I250 I252 SENSE_DIFFPAIR I251 I253 TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP I254 I256 TABLE_PHYSICAL_RULE_ITEM MEM_40S * OVERRIDE OVERRIDE MEM_72D * OVERRIDE OVERRIDE 0.09 MM 400 MIL OVERRIDE OVERRIDE 0.09 MM 400 MIL I255 OVERRIDE OVERRIDE I281 SENSE_DIFFPAIR TABLE_PHYSICAL_RULE_ITEM OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE I282 OVERRIDE OVERRIDE I283 SENSE_DIFFPAIR TABLE_PHYSICAL_RULE_ITEM MEM_37S * OVERRIDE OVERRIDE MEM_85D * OVERRIDE OVERRIDE OVERRIDE OVERRIDE 0.09 MM 400 MIL OVERRIDE OVERRIDE 0.09 MM 400 MIL OVERRIDE I284 OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE 60 61 60 61 SENSE_DIFFPAIR TABLE_SPACING_ASSIGNMENT_ITEM MEM_DATA 60 61 60 61 SENSE_DIFFPAIR TABLE_SPACING_ASSIGNMENT_ITEM C 60 61 SPK_OUT DIFFPAIR AUDIO AUD_DIFF 1TO1_DIFFPAIR AUDIO AUD_DIFF 1TO1_DIFFPAIR AUDIO I302 AUD_DIFF 1TO1_DIFFPAIR AUDIO I301 AUD_DIFF 1TO1_DIFFPAIR AUDIO I304 AUD_DIFF 1TO1_DIFFPAIR AUDIO I303 AUD_DIFF 1TO1_DIFFPAIR AUDIO 49 69 I305 AUD_DIFF 1TO1_DIFFPAIR AUDIO 49 I307 AUD_DIFF 1TO1_DIFFPAIR AUDIO 49 I306 AUD_DIFF 1TO1_DIFFPAIR AUDIO 49 I310 AUD_DIFF 1TO1_DIFFPAIR AUDIO I308 AUD_DIFF 1TO1_DIFFPAIR AUDIO AUD_DIFF 1TO1_DIFFPAIR AUDIO I311 AUD_DIFF 1TO1_DIFFPAIR AUDIO I312 AUD_DIFF 1TO1_DIFFPAIR AUDIO AUD_DIFF 1TO1_DIFFPAIR AUDIO I314 AUD_DIFF 1TO1_DIFFPAIR AUDIO I315 AUD_DIFF 1TO1_DIFFPAIR AUDIO AUD_DIFF 1TO1_DIFFPAIR AUDIO USB_85D USB CPU_THERMD_N USB_85D ISNS_5V_S0_HDD_N 49 CPUIMVP_ISNS2G_N CPUIMVP_ISUM_R_P I316 60 61 60 60 60 C 60 60 60 57 60 57 60 57 60 57 60 57 60 57 60 60 60 60 60 60 60 53 53 GND GND TABLE_PHYSICAL_RULE_ITEM B OVERRIDE OVERRIDE OVERRIDE 0.076 MM 10 mm OVERRIDE OVERRIDE OVERRIDE OVERRIDE 0.1 MM 500 MIL OVERRIDE OVERRIDE OVERRIDE OVERRIDE TABLE_PHYSICAL_RULE_ITEM PCIE_85D * OVERRIDE OVERRIDE TOP OVERRIDE SENSE_DIFFPAIR I291 TABLE_PHYSICAL_RULE_ITEM USB_85D OVERRIDE I292 SENSE_1TO1_55S SENSE ISNS_1V5_S3_DDR_R_P I320 SENSE_1TO1_55S SENSE ISNS_1V5_S3_DDR_R_N 49 I293 LVDS_90D LVDS_PCH_TX LVDS_CONN_A_CLK_F_N 74 I294 LVDS_90D LVDS_PCH_TX LVDS_CONN_A_CLK_F_P 74 I319 SENSE_DIFFPAIR B TABLE_PHYSICAL_RULE_ITEM CPU_27P4S TOP OVERRIDE OVERRIDE CLK_PCIE_90D TOP OVERRIDE OVERRIDE 0.09 MM 400 MIL OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE TABLE_PHYSICAL_RULE_ITEM A OVERRIDE OVERRIDE OVERRIDE OVERRIDE 0.09 MM 400 MIL OVERRIDE OVERRIDE Memory Constraint Relaxations SYNC_MASTER=K90I_MLB SYNC_DATE=02/15/2011 PAGE TITLE Allow 0.127 mm necks for >0.127 mm lines for ARD fanout Project Specific Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER MEM_72D BOTTOM ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH 0.127 MM 6.35 MM DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP DRAWING NUMBER TABLE_PHYSICAL_RULE_ITEM Apple Inc TABLE_PHYSICAL_RULE_ITEM MEM_85D TOP 0.1 MM R NOTICE OF PROPRIETARY PROPERTY: SIZE D 6.0.0 6.35 MM THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED 051-9058 REVISION BRANCH PAGE 108 OF 109 SHEET 85 OF 86 A K90i Board-Specific Spacing & Physical Constraints TABLE_BOARD_INFO BOARD LAYERS BOARD AREAS BOARD UNITS (MIL or MM) TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM NO_TYPE,BGA MM ALLEGRO VERSION 16.2 TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP DEFAULT * Y =50_OHM_SE =50_OHM_SE 10 MM MM MM STANDARD * Y =DEFAULT =DEFAULT 10 MM =DEFAULT =DEFAULT TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET * * BGA BGA_P1MM MEM_CLK * BGA BGA_P2MM CLK_PCIE * BGA BGA_P2MM CLK_SLOW * BGA BGA_P2MM TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_ITEM DEFAULT * 0.1 MM TABLE_SPACING_ASSIGNMENT_ITEM ? TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET D LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH Y 0.110 MM MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP TOP,BOTTOM * =DEFAULT TABLE_SPACING_ASSIGNMENT_ITEM ? TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM 50_OHM_SE STANDARD DIFFPAIR NECK GAP BGA_P1MM * =DEFAULT TABLE_SPACING_ASSIGNMENT_ITEM ? TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM 50_OHM_SE * Y 0.080 MM 0.080 MM =STANDARD =STANDARD =STANDARD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP BGA_P2MM * =DEFAULT ? LINE-TO-LINE SPACING WEIGHT TABLE_PHYSICAL_RULE_HEAD TOP,BOTTOM Y 0.165 MM 0.165 MM LAYER ISL10 N 0.126 MM 0.126 MM 1.5:1_SPACING =STANDARD =STANDARD =STANDARD * 0.15 MM ISL3,ISL4,ISL9 Y 0.126 MM 0.126 MM =STANDARD =STANDARD * 0.2 MM * N =STANDARD =STANDARD =STANDARD =STANDARD 2X_DIELECTRIC * 0.140 MM ? 3X_DIELECTRIC * 0.210 MM ? 4X_DIELECTRIC * 0.280 MM ? TABLE_SPACING_RULE_ITEM 2.5:1_SPACING =STANDARD WEIGHT TABLE_SPACING_RULE_ITEM ? * 0.25 MM TABLE_SPACING_RULE_ITEM ? TABLE_PHYSICAL_RULE_ITEM 40_OHM_SE LINE-TO-LINE SPACING TABLE_SPACING_RULE_ITEM 2:1_SPACING =STANDARD LAYER TABLE_SPACING_RULE_ITEM ? TABLE_PHYSICAL_RULE_ITEM 40_OHM_SE TABLE_SPACING_RULE_HEAD SPACING_RULE_SET TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM 40_OHM_SE TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_RULE_HEAD SPACING_RULE_SET TABLE_PHYSICAL_RULE_ITEM 40_OHM_SE TABLE_SPACING_RULE_ITEM 3:1_SPACING * 0.3 MM TABLE_SPACING_RULE_ITEM ? 5X_DIELECTRIC * 0.350 MM ? 6X_DIELECTRIC * 0.420 MM ? 7X_DIELECTRIC * 0.490 MM ? TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH D 0.090 MM MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP 4:1_SPACING * 0.4 MM TABLE_SPACING_RULE_ITEM ? DIFFPAIR NECK GAP TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM 37_OHM_SE TOP,BOTTOM Y 0.190 MM 0.1 MM 37_OHM_SE ISL10 N 0.145 MM 0.1 MM =STANDARD =STANDARD =STANDARD 37_OHM_SE ISL3,ISL4,ISL9 Y 0.145 MM 0.1 MM =STANDARD =STANDARD =STANDARD 37_OHM_SE * N =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM www.qdzbwx.com TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM 27P4_OHM_SE TOP,BOTTOM Y 0.310 MM 0.2 MM 27P4_OHM_SE * Y 0.235 MM 0.2 MM =STANDARD =STANDARD =STANDARD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 55_OHM_SE TOP,BOTTOM Y 0.090 MM 0.090 MM 55_OHM_SE * Y 0.070 MM 0.070 MM =STANDARD =STANDARD =STANDARD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD C C TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 1:1_DIFFPAIR * Y =STANDARD =STANDARD =STANDARD 0.1 MM 0.1 MM TABLE_PHYSICAL_RULE_ITEM 72_OHM_DIFF * N =STANDARD =STANDARD =STANDARD =STANDARD 72_OHM_DIFF ISL3,ISL4,ISL9 Y 0.140 MM 0.140 MM =STANDARD 0.190 MM 0.190 MM 72_OHM_DIFF ISL10 N 0.140MM 0.140 MM 0.190 MM 0.190 MM 72_OHM_DIFF TOP,BOTTOM Y 0.175 MM 0.175 MM 0.200 MM 0.200 MM PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD MAXIMUM NECK LENGTH TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 85_DIFF_BGA * =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF 85_DIFF_BGA ISL3,ISL4 Y 0.075 MM 0.075 MM 0.125 MM 0.125 MM 85_DIFF_BGA ISL9,ISL10 Y 0.075 MM 0.075 MM 0.125 MM 0.125 MM TABLE_PHYSICAL_RULE_ITEM 85_OHM_DIFF * N =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM 85_OHM_DIFF ISL3,ISL4 Y 0.101 MM 0.1 MM 0.170 MM 0.170 MM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM 85_OHM_DIFF ISL9,ISL10 Y 0.101 MM 0.1 MM 0.170 MM 0.170 MM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM 85_OHM_DIFF TOP,BOTTOM Y 0.125 MM 0.1 MM 0.190 MM NOTE: 85_DIFF_BGA is 85-ohms differential impedance on outer layers and 80-ohms on inner layers 0.190 MM TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 90_DIFF_BGA * =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF 90_DIFF_BGA ISL3,ISL4 Y 0.075 MM 0.075 MM 0.125 MM 0.125 MM 90_DIFF_BGA ISL9,ISL10 Y 0.075 MM 0.075 MM 0.125 MM 0.125 MM TABLE_PHYSICAL_RULE_ITEM 90_OHM_DIFF * N =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM B 90_OHM_DIFF ISL3,ISL4 Y 0.091 MM 0.091 MM 0.180 MM 0.180 MM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM 90_OHM_DIFF ISL9,ISL10 Y 0.091 MM 0.091 MM 0.180 MM 0.180 MM B TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM 90_OHM_DIFF TOP,BOTTOM Y 0.111 MM 0.111 MM PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH NOTE: 90_DIFF_BGA is 90-ohms differential impedance on outer layers and 85-ohms on inner layers 0.200 MM 0.200 MM DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_HEAD MAXIMUM NECK LENGTH TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 100_DIFF_BGA * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF 100_DIFF_BGA ISL3,ISL4 Y 0.075 MM 0.075 MM 0.125 MM 0.125 MM 100_DIFF_BGA ISL9,ISL10 Y 0.075 MM 0.075 MM 0.125 MM 0.125 MM TABLE_PHYSICAL_RULE_ITEM 100_OHM_DIFF * N =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM 100_OHM_DIFF ISL3,ISL4 Y 0.076 MM 0.076 MM 0.250 MM 0.250 MM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM 100_OHM_DIFF ISL9,ISL10 Y 0.076 MM 0.076 MM 0.250 MM 0.250 MM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM 100_OHM_DIFF TOP,BOTTOM Y 0.085 MM 0.085 MM PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH 110_OHM_DIFF * N =STANDARD =STANDARD 110_OHM_DIFF ISL3,ISL4 Y 0.068 MM 110_OHM_DIFF ISL9,ISL10 Y 110_OHM_DIFF TOP,BOTTOM Y NOTE: 100_DIFF_BGA is 100-ohms differential impedance on outer layers and 95-ohms on inner layers 0.200 MM 0.200 MM MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP =STANDARD =STANDARD =STANDARD 0.068 MM 0.250 MM 0.250 MM 0.068 MM 0.068 MM 0.250 MM 0.250 MM 0.081 MM 0.081 MM 0.250 MM 0.250 MM DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_HEAD TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM NOTE: 110_DIFF is 110-ohms differential impedance on outer layers and 105-ohms on inner layers TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM NOTE: These are Intel recommended impedances for PEG, unused on K90i TABLE_PHYSICAL_RULE_HEAD A PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH 48_OHM_SE TOP,BOTTOM Y 0.165 MM 0.165 MM 48_OHM_SE * Y 0.090 MM 0.090 MM =STANDARD =STANDARD =STANDARD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP MAXIMUM NECK LENGTH TABLE_PHYSICAL_RULE_ITEM SYNC_MASTER=K90I_MLB SYNC_DATE=02/15/2011 PAGE TITLE TABLE_PHYSICAL_RULE_ITEM PCB Rule Definitions DRAWING NUMBER TABLE_PHYSICAL_RULE_HEAD Apple Inc TABLE_PHYSICAL_RULE_ITEM 80_OHM_DIFF * N =STANDARD =STANDARD 80_OHM_DIFF ISL3,ISL4 Y 0.115 MM 80_OHM_DIFF ISL9,ISL10 Y 0.115 MM 80_OHM_DIFF TOP,BOTTOM Y 0.140 MM =STANDARD =STANDARD =STANDARD 0.115 MM 0.180 MM 0.180 MM 0.115 MM 0.180 MM 0.180 MM 0.140 MM 0.190 MM 0.190 MM 051-9058 R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED TABLE_PHYSICAL_RULE_ITEM D 6.0.0 TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM SIZE REVISION BRANCH PAGE 109 OF 109 SHEET 86 OF 86 A ... AV3 AV1 BB1 BA3 BB5 BB3 BB7 BE8 BD4 BF6 AV10 BA2 BF3 USBP0N USBP0P C24 USBP1N USBP1P C25 USBP2N USBP2P C26 USBP3N USBP3P K28 USBP4N USBP4P E28 USBP5N USBP5P C28 USBP6N USBP6P C29 USBP7N USBP7P N28... AK46 B1 1 AK8 B1 5 AL16 B1 9 AL17 B2 3 AL19 B2 7 AL2 B3 1 AL21 B3 5 AL23 B3 9 AL26 B7 AL27 F45 AL31 BB12 AL33 BB16 AL34 BB20 AL48 BB22 AM11 BB24 AM14 BB28 AM36 BB30 AM39 BB38 AM43 BB4 AM45 BB46 AM46 BC14... SB_DQ_49 SB_DQ_50 SB_DQ_51 SB_DQ_52 SB_DQ_53 SB_DQ_54 SB_DQ_55 SB_DQ_56 SB_DQ_57 SB_DQ_58 SB_DQ_59 SB_DQ_60 SB_DQ_61 SB_DQ_62 SB_DQ_63 MEM _B_ BA MEM _B_ BA MEM _B_ BA BG39 BD42 AT22 SB_BS_0 SB_BS_1