8 CK APPD ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5% ALL CAPACITANCE VALUES ARE IN MICROFARADS ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ REV SCHEM,MLB,M59 ZONE ECN A ENG APPD DESCRIPTION OF CHANGE 463525 PRODUCTION RELEASE DATE DATE 9/19/2006 9/19/2006 09/19/2006 D D TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM C TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM B TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM N/A Power Block Diagram N/A BOM Configuration TABLE_TABLEOFCONTENTS_ITEM N/A TABLE_TABLEOFCONTENTS_ITEM N/A TABLE_TABLEOFCONTENTS_ITEM N/A TABLE_TABLEOFCONTENTS_ITEM N/A TABLE_TABLEOFCONTENTS_ITEM (MASTER) TABLE_TABLEOFCONTENTS_ITEM (MASTER) TABLE_TABLEOFCONTENTS_ITEM N/A Functional / ICT Test N/A Signal Aliases/Misc Comps N/A CPU OF 2-FSB (MASTER) CPU OF 2-PWR/GND (MASTER) CPU Decoupling & VID (MASTER) TABLE_TABLEOFCONTENTS_ITEM (MASTER) TABLE_TABLEOFCONTENTS_ITEM (MASTER) TABLE_TABLEOFCONTENTS_ITEM (MASTER) TABLE_TABLEOFCONTENTS_ITEM (MASTER) TABLE_TABLEOFCONTENTS_ITEM (MASTER) TABLE_TABLEOFCONTENTS_ITEM (MASTER) TABLE_TABLEOFCONTENTS_ITEM (MASTER) 10 CPU MISC1-TEMP SENSOR (MASTER) 11 CPU ITP700FLEX DEBUG (MASTER) 12 NB CPU Interface (MASTER) 13 NB PEG / Video Interfaces (MASTER) 14 NB Misc Interfaces (MASTER) NB DDR2 Interfaces (MASTER) 15 16 NB Power (MASTER) TABLE_TABLEOFCONTENTS_ITEM (MASTER) TABLE_TABLEOFCONTENTS_ITEM (MASTER) TABLE_TABLEOFCONTENTS_ITEM 07/25/2006 TABLE_TABLEOFCONTENTS_ITEM (MASTER) TABLE_TABLEOFCONTENTS_ITEM (MASTER) TABLE_TABLEOFCONTENTS_ITEM (MASTER) TABLE_TABLEOFCONTENTS_ITEM (MASTER) 17 NB Power (MASTER) 18 NB Grounds (MASTER) 19 NB (GM) Decoupling M59_MG 20 NB Config Straps (MASTER) 21 SB: OF (MASTER) SB: of (MASTER) 22 23 SB: OF 07/25/2006 TABLE_TABLEOFCONTENTS_ITEM (MASTER) TABLE_TABLEOFCONTENTS_ITEM (MASTER) TABLE_TABLEOFCONTENTS_ITEM (MASTER) TABLE_TABLEOFCONTENTS_ITEM (MASTER) TABLE_TABLEOFCONTENTS_ITEM (MASTER) TABLE_TABLEOFCONTENTS_ITEM (MASTER) TABLE_TABLEOFCONTENTS_ITEM M59_MG 24 SB: OF (MASTER) 25 SB Decoupling (MASTER) 26 SB Misc (MASTER) 27 M1 SMBus Connections (MASTER) 28 DDR2 SO-DIMM Connector A (MASTER) DDR2 SO-DIMM Connector B (MASTER) 29 30 Memory Active Termination (MASTER) TABLE_TABLEOFCONTENTS_ITEM (MASTER) TABLE_TABLEOFCONTENTS_ITEM (MASTER) TABLE_TABLEOFCONTENTS_ITEM (MASTER) TABLE_TABLEOFCONTENTS_ITEM 05/07/2006 TABLE_TABLEOFCONTENTS_ITEM (MASTER) TABLE_TABLEOFCONTENTS_ITEM (MASTER) TABLE_TABLEOFCONTENTS_ITEM (MASTER) TABLE_TABLEOFCONTENTS_ITEM (MASTER) TABLE_TABLEOFCONTENTS_ITEM (MASTER) 31 Memory Vtt Supply (MASTER) 32 DDR2 VRef (MASTER) 33 CLOCKS (MASTER) 34 Clock Termination M59_MG 37 Mobile Clocking (MASTER) PATA Connector (MASTER) 38 39 FireWire Link (TSB83AA22) (MASTER) 40 FireWire PHY (TSB83AA22) (MASTER) 41 (MASTER) ETHERNET CONTROLLER (MASTER) 42 (MASTER) Ethernet Connector (MASTER) Yukon Power Control (MASTER) 43 (MASTER) TABLE_TABLEOFCONTENTS_ITEM Sync (MASTER) FW PHY Power Supply (MASTER) FireWire Port Power (MASTER) FireWire Ports (MASTER) Camera Connector (MASTER) External USB Connector (MASTER) Left I/O Board Connector (MASTER) PCI-E Connections (MASTER) SMC (MASTER) 45 (MASTER) 46 (MASTER) 49 (MASTER) 52 (MASTER) 55 (MASTER) 57 (MASTER) 58 (MASTER) /x / TABLE_TABLEOFCONTENTS_ITEM System Block Diagram N/A Contents 44 59 (MASTER) SMC Support (MASTER) 60 (MASTER) LPC+ Debug Connector (MASTER) 61 (MASTER) Thermal Sensors (MASTER) 62 (MASTER) Current & Voltage Sensing (MASTER) 63 (MASTER) SPI BOOTROM (MASTER) 64 ALS Support Fan Connectors Sudden Motion Sensor (SMS) 67 TPM IMVP6 CPU VCore Regulator (MASTER) 5V / 1.5V Power Supply (MASTER) 2.5V & 1.2V Regulators M59_MG 1.8V Supply M59_MG 76 77 78 79 3.3V / 1.05V Power Supplies M59_MG 3.3V G3Hot Supply & Power Control M59_MG Power Aliases M59_MG 80 81 82 PBus-In,Batt & 3G Pwr Connectors (MASTER) ATI M56 PCI-E (MASTER) GPU (M56) Core Supplies (MASTER) ATI M56 Core Power (MASTER) 84 85 86 90 91 TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM C (MASTER) (MASTER) (MASTER) (MASTER) 75 89 (MASTER) (MASTER) 66 88 (MASTER) (MASTER) 65 87 su TABLE_TABLEOFCONTENTS_ITEM 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 (MASTER) (MASTER) 05/07/2006 05/07/2006 05/07/2006 08/01/2006 05/07/2006 (MASTER) (MASTER) (MASTER) (MASTER) (MASTER) ATI M56 Frame Buffer I/F (MASTER) GPU Straps M59_MG GDDR3 Frame Buffer A (MASTER) GDDR3 Frame Buffer B (MASTER) ATI M56 GPIO/DVO/Misc (MASTER) 07/25/2006 (MASTER) (MASTER) (MASTER) p: / TABLE_TABLEOFCONTENTS_ITEM Page TABLE_TABLEOFCONTENTS_HEAD N/A N/A 93 B (MASTER) ATI M56 Video Interfaces (MASTER) 94 07/25/2006 Internal Display Connectors M59_MG External Display Connector M59_MG M59 Specific Connectors (MASTER) LVDS Interface Pull-downs M59_MG Revision History N/A Napa Platform Constraints (MASTER) More System Constraints (MASTER) M59 Spacing & Physical Constraints (MASTER) M59 Net Properties (MASTER) 97 07/25/2006 98 (MASTER) 99 tt TABLE_TABLEOFCONTENTS_ITEM Sync Table of Contents h TABLE_TABLEOFCONTENTS_ITEM Contents 1 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 Date yc Page TABLE_TABLEOFCONTENTS_HEAD (.csa) om p Date /m (.csa) 08/01/2006 100 N/A 101 (MASTER) 102 (MASTER) 103 (MASTER) 104 (MASTER) TABLE_TABLEOFCONTENTS_ITEM DIMENSIONS ARE IN MILLIMETERS A Apple Computer Inc METRIC XX X.XX DRAFTER Schematic / PCB #’s PART NUMBER THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING QTY ENG APPD MFG APPD QA APPD DESIGNER RELEASE SCALE I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART ANGLES DESCRIPTION REFERENCE DES 051-7150 SCHEM,MLB,M59 SCH CRITICAL CRITICAL 820-2054 PCBF,MLB,M59 PCB CRITICAL A NOTICE OF PROPRIETARY PROPERTY DESIGN CK X.XXX BOM OPTION TITLE DO NOT SCALE DRAWING SCHEM,MLB,M59 NONE DRAWING SIZE TITLE=M59_MLB ABBREV=DRAWING THIRD ANGLE PROJECTION LAST_MODIFIED=Mon Sep 25 10:45:58 2006 MATERIAL/FINISH NOTED AS APPLICABLE D DRAWING NUMBER REV 051-7150 A.0.0 SHT 1 OF 84 GDDR3 Core Duo (Merom) CPU Frame Buffer THERMAL 128MB/256MB SENSOR ITP700FLEX CPU Debug Connector 479 BGA Inverter Connector P.76 D P.72-73 P.10 P.11 PWM P.7-9 D J2800 ATI M56P LCD Panel FSB Dual-Channel LVDS DDR2 SO-DIMM A "Expansion Slot" Connector (Lower/Outer) GPU P.76,79 PCIe x16 S-Video/Composite CH.A P.28 DVI-I/DL Connector Dual-Channel TMDS w/TV-Out Support 945GM NB P.67-71,74-75 P.77 P.99 RJ45 (Ethernet) Yukon Gig-E ENET Yukon Power Controller P.12-20 P.39 P.39 P.40 Controller Connectors P.44 P.37-38 Port Power PCI P.43 P.43 Connector P.46 SB yc SATA HDD/IR/SIL Connector USB USB Camera Connector B USB x2 Geyser KB/TP/BT C PCIe x1 PCIe x1 Left I/O & USB Audio Board USB Connector P.47 609 BGA P.21-26 B SMBus Connector PATA 66MHZ 16BITS h ODD Connector tt P.78 P.36 LPC 33MHZ BootROM Power SPI P.54 CK410 Clock TPM SB SMBus Controller H8S/2116 P.27 P.33-34 Supplies LPC Debug P.57-64,69 Connector P.58 P.51 ALS Temperature SMC SMBus Sensors A P.32 p: / P.45 BUFFER Azalia (HD-Audio) /m P.78 P.30-31 DDR2 VREF ICH7-M PHY Power USB x2 Right USB 2.0 PCIe x1 om p C & REGULATOR P.29 su DMI x4 TSB83AA22 FireWire FW DDR2 VTT "Factory Slot" Connector (Upper/Inner) 1466UFCBGA Connector 1394a/b (FireWire) DDR2 SO-DIMM B CH.B /x / LVDS Graphics MUX J2900 SMC SMBus x5 SYNC_MASTER=N/A SYNC_DATE=N/A NOTICE OF PROPRIETARY PROPERTY P.27 P.52 System Block Diagram P.55,78 SMS THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING P.57 Battery SMBus Fan Connector Connectors PWM/Tach I TO MAINTAIN THE DOCUMENT IN CONFIDENCE P.49-50 II NOT TO REPRODUCE OR COPY IT Analog P.56 P.66 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART Sensors SIZE P.53 APPLE COMPUTER INC DRAWING NUMBER D SCALE SHT NONE REV 051-7150 A.0.0 OF 84 A U8000 ENABLE J5500 Q7610 3.425 LIO Flex PPDCIN_G3H PP5V_S3 PP3V42_G3H G3Hot Connector 18.5V - 9V 5.0V 3.425V (LT3470) SMC_PM_G2_ENABLE D PM_SLP_S3_L 1.5V 5V D PM_SLP_S4_LS5V Q7615 U7600 Q3820 ENABLES J8200 5V/1.5V LIO Power PPBUS_G3H Connector 12.6V - 9V PP5V_S5 PP5V_S0 PP5V_S0_IDE_ODD 5.0V 5.0V 5V S5/S0 PP1V5_S0 (LTC3728) PM_SLP_S3_LS5V Q7945 NC SMC_PM_G2_ENABLE ENABLE IMVP_PWRGD_IN C 3.3V U7530 om p PP3V3_S5 ENABLES S5 3.3V CPU VCore S0 (ISL9504) (ISL6269B) PPVCORE_S0_CPU PGOOD 1.25V - 0.8V RSMRST_PWRGD "IMVP6" yc PM_SLP_S3_L PGOOD U7950 VR_PWRGOOD_DELAY ENABLE 1.05V Inverter PP3V3_S3 PP3V3_S3AC 3.3V 3.3V C PM_SLP_S4_LS5V PP2V5_S0 PM_SLP_S3BATT U7700 2.5V PGOOD U7800 ENABLE PP2V5_D3C 2.5V NC PM_SLP_S3BATT U7750 PP1V8_S3 PP1V2_D3C 1.2V 1.2V tt (LTC3412) PGOOD ENABLE h PP1V2_S3 S3 U8500 1.8V (TPS51117) B Q7770 1.2V =GPUVCORE_EN_L S3 P1V2R2V5D3C_EN_LS5V ENABLE IMVP_PWRGD_IN/ALL_SYS_PWRGD 1.8V Q7721 2.5V PGOOD p: / B PM_SLP_S3_LS5V_L PP2V5_S3 S3 1.05V (ISL6269B) PM_SLP_S4_L 2.5V ENABLE PP1V05_S0 S0 Connector Q7720 PM_SLP_S3BATT (TPS62510) /m J5500 Q4300 su U7900 IMVP_VR_ON ODD_PWR_EN_L (SB GPIO14) /x / 1.5V PGOOD P1V2R2V5D3C_EN_LS5V NC GPU VCore PGOOD PPVCORE_D3C_GPU Q7947 D3C NC Q7948 1.1V - 0.95V (ISL6269B) PP3V3_S0 PP3V3_D3C 3.3V 3.3V PGOOD PM_SLP_S3_L NC U3100 PM_SLP_S3_LS5V ENABLE A P3V3D3C_EN_L Power Block Diagram SYNC_MASTER=N/A Q7845 Q4500 SYNC_DATE=N/A NOTICE OF PROPRIETARY PROPERTY Q4501 0.9V (Vtt) PP0V9_S0 PP1V8_D3C PPBUS_S5_FWPORT 0.9V 1.8V 12.6V - 9V THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING S0 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE (TPS51100) II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE APPLE COMPUTER INC P1V8D3C_EN FW_PWRCTRL_GATE1 SHT NONE REV 051-7150 SCALE FW_PWRCTRL_GATE2_1/2 DRAWING NUMBER D A.0.0 OF 84 A 2.16Ghz BOMs BOMOPTION Groups TABLE_BOMGROUP_HEAD BOM NUMBER BOM NAME TABLE_BOMGROUP_HEAD BOM OPTIONS BOM GROUP BOM OPTIONS M59_COMMON ALTERNATE,COMMON,M59_COMMON1,M59_COMMON2,M59_COMMON3 M59_COMMON1 BOOTROM_FINAL,ENET_LOWPWR_EN,ENETPWR_S3AC,GPU_BB_CTL,D3CPGOOD_3V3 M59_COMMON2 ITP,KBDLED_HAS,LPCPLUS,LVDS_PD,MEMVREF_S3 M59_COMMON3 MEMVTT_EN_PU,RTUSB_ESD,SMC_PRGRM,USB_C_OC_PU,USB_D_OC_PU,USB_E_OC_PU VRAM_INF128 GPU_MEM_NOT_SAM,VRAM_128_INFINEON VRAM_SAM128 VRAM_128_SAMSUNG VRAM_INF256 GPU_MEM_256M,GPU_MEM_NOT_SAM,VRAM_256_INFINEON TABLE_BOMGROUP_ITEM 630-7849 PCBA,2.16GHZ,128VRAM,M59,MBP15 TABLE_BOMGROUP_ITEM EEE_WTE,M59_COMMON,CPU_2_16GHZ,VRAM_SAM128 TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM 2.33Ghz BOMs TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_HEAD D BOM NUMBER BOM NAME BOM OPTIONS 630-7851 PCBA,2.33GHZ,256VRAM,M59,MBP15 EEE_WTG,M59_COMMON,CPU_2_33GHZ,VRAM_SAM256 TABLE_BOMGROUP_ITEM D TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM VRAM_SAM256 GPU_MEM_256M,VRAM_256_SAMSUNG M59_TPM TPM TABLE_BOMGROUP_ITEM Bar Code Label / EEE #’s QTY REFERENCE DES LBL,P/N LABEL,PCB,28MM X MM [EEE:WTE] CRITICAL CRITICAL BOM OPTION EEE_WTE 826-4393 LBL,P/N LABEL,PCB,28MM X MM [EEE:WTG] CRITICAL EEE_WTG Module Parts PART NUMBER DESCRIPTION REFERENCE DES CRITICAL BOM OPTION IC,SGRAM,GDDR3,8MX32,700MHZ,136 FBGA U8900,U8950,U9000,U9050 CRITICAL VRAM_128_SAMSUNG 333S0350 IC,SGRAM,GDDR3,16MX32,700MHZ,136 FBGA U8900,U8950,U9000,U9050 CRITICAL VRAM_256_SAMSUNG 333S0358 IC,SGRAM,GDDR3,8MX32,700MHZ,136 FBGA U8900,U8950,U9000,U9050 CRITICAL VRAM_128_HYNIX 333S0351 IC,SGRAM,GDDR3,16MX32,700MHZ,136 FBGA U8900,U8950,U9000,U9050 CRITICAL VRAM_256_HYNIX 333S0376 IC,SGRAM,GDDR3,8MX32,700MHZ,136 FBGA U8900,U8950,U9000,U9050 CRITICAL VRAM_128_INFINEON 333S0377 IC,SGRAM,GDDR3,16MX32,600MHZ,136 FBGA U8900,U8950,U9000,U9050 CRITICAL VRAM_256_INFINEON 337S3391 IC,MDC,B2,PRQ,2.16G,34W,667M,4M,479BGA U0700 CRITICAL CPU_2_16GHZ 337S3393 IC,MDC,B2,PRQ,2.33G,34W,667M,4M,479BGA U0700 CRITICAL CPU_2_33GHZ 341S1922 IC,EFI,BOOTROM DEVELOPMENT (UNLOCKED),M59 U6301 CRITICAL BOOTROM_DEVEL 341S1923 IC,EFI,BOOTROM FINAL (LOCKED),M59 U6301 CRITICAL BOOTROM_FINAL 338S0274 IC,SMC,HS8/2116 U5800 CRITICAL SMC_BLANK 341S1929 IC,PRGRM,SMC (NEW),M59 U5800 CRITICAL SMC_PRGRM 338S0269 IC,945GM,NORTHBRIDGE U1200 CRITICAL CRITICAL om p C QTY 333S0354 /x / DESCRIPTION 826-4393 su PART NUMBER extra TPM options: SMC_TPM_GPIO2 SMC_TPM_GPIO1 SMC_TPM_PP IC,88E8053,GIGABIT ENET XCVR,64P QFN, NO U4101 338S0368 IC,ATI,M56L-LLP,GRPHXCRTL,LF 880BGA U8400 CRITICAL 341S1789 IC, TPM, 28-PIN TSSOP U6700 CRITICAL 341S1797 IC,EEPROM,SERIAL IIC,8KBIT,SO8 U4102 CRITICAL 343S0385 IC,ICH7M,BGA U2100 CRITICAL 353S1461 IC,ISL9504,SYNC REG CTRL,QFN48 U7530 CRITICAL 359S0109 LOW POWER CLOCK SYNTHESIZER, 68PIN U3301 CRITICAL TPM yc 338S0270 C /m Alternate Parts p: / B TABLE_ALT_HEAD PART NUMBER ALTERNATE FOR PART NUMBER 128S0094 BOM OPTION REF DES COMMENTS: 128S0060 ALL 330uF,2V,9MOHM,D2 128S0095 128S0060 ALL 330uF,2V,6MOHM,D2 128S0081 128S0061 ALL 150uF,6.3V,25MOHM,C2 376S0448 376S0445 ALL Si7806ADN for FDM6296 TABLE_ALT_ITEM TABLE_ALT_ITEM TABLE_ALT_ITEM B TABLE_ALT_ITEM TABLE_ALT_ITEM 353S1465 353S1461 ALL Screened ISL6262 for ISL9504 152S0287 152S0435 ALL Alternates for Coilcraft MSS5131 128S0093 128S0092 ALL 33uF,16V,D2 TABLE_ALT_ITEM h tt TABLE_ALT_ITEM BOM Configuration A SYNC_MASTER=N/A SYNC_DATE=N/A NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE APPLE COMPUTER INC DRAWING NUMBER D SCALE SHT NONE REV 051-7150 A.0.0 OF 84 A Functional Test Points Power Supply NO_TESTs TRUE TRUE GPUVCORE_COMP GPUVCORE_FSET 41C4 61B7 5B7 63C6 5B7 63D6 5C7 63A7 5B7 63B7 64C3 68C7 68C7 GPUBBP_ADJ GPUBBN_FB GPUVCORE_FB 68C7 GPUVCORE_FB_RC 68C3 TRUE GPUVCORE_ISEN GPUVCORE_UG IMVP6_COMP_RC 59B8 IMVP6_DFB 59B6 TRUE IMVP6_FB 59B7 TRUE IMVP6_OCSET 59C6 TRUE IMVP6_VDIFF 59C7 TRUE IMVP6_VDIFF_RC 59B8 TRUE P1V05S0_BOOT 63B5 TRUE P1V05S0_BOOT_R 63B5 TRUE P1V05S0_COMP 5D7 63A7 TRUE P1V05S0_COMP_R 63A7 TRUE P1V05S0_FB 63A7 P1V05S0_FB_RC 63A3 P1V05S0_FSET 5D7 63B7 TRUE P1V05S0_ISEN 63A5 TRUE P1V05S0_LG 63A5 TRUE P1V05S0_PHASE 63B5 TRUE P1V05S0_UG 63B5 TRUE P1V5S0_RUNSS 5D7 60C4 64C6 TRUE P3V3S5_BOOT 63D4 TRUE P3V3S5_BOOT_R 63D4 TRUE P3V3S5_COMP 5D7 63C6 TRUE P3V3S5_COMP_R 63C6 TRUE P3V3S5_FB 63C6 TRUE P3V3S5_FB_RC 63C2 TRUE P3V3S5_FSET 5D7 63D6 TRUE P3V3S5_ISEN 63C4 TRUE P3V3S5_LG 63C4 TRUE P3V3S5_UG 63D4 TRUE CK410_XTAL_IN 33C6 =PP5V_S0_FAN_LT TRUE TRUE FAN_LT_PWM FAN_LT_TACH TRUE TRUE FAN_RT_PWM FAN_RT_TACH SMC_BS_ALRT_L =SMBUS_BATT_SCL =SMBUS_BATT_SDA GND_BATT TRUE TRUE TRUE TRUE 56C7 65A1 56B6 56B6 49C5 50B2 66B5 27C1 66B5 27C1 66B5 66B5 D 56B3 56B3 Left I/O Data Connector 7B3 7B4 7C3 7C4 12B4 84D6 7D6 12B4 84D6 FUNC_TEST LPC+ Debug Connector 7B3 7B4 7C3 7C4 12B4 84D6 7B3 7B4 7C3 7C4 12B4 84D6 FUNC_TEST 7D6 12B4 84D6 =PP3V3_S5_LPCPLUS =PP5V_S0_LPCPLUS TRUE TRUE 7D6 12B4 84D6 7D6 12B4 84D6 7D8 12A4 12B4 84D6 68D5 TRUE TRUE 7D6 12B4 84D6 68C5 TRUE TRUE 7B3 7B4 7C3 7C4 12B6 12C6 12D6 84D6 68C5 GPUVCORE_PHASE FUNC_TEST TRUE 7D6 12C4 84D6 68C5 GPUVCORE_LG TRUE TRUE TRUE 7D6 12C4 84D6 68A3 TRUE TRUE TRUE 7C8 7D8 12C4 84C6 68B7 TRUE TRUE B 61B6 7D6 12C4 84D6 /x / P3V42G3H_FB 5B7 60C4 64C6 TRUE Battery Digital Connector FUNC_TEST 7C8 7D8 12C4 12D4 84D6 su TRUE 60C5 64A6 Fan Connectors FSB_A_L FSB_ADS_L FSB_ADSTB_L FSB_BNR_L FSB_BREQ0_L FSB_D_L FSB_DBSY_L FSB_DINV_L FSB_DRDY_L FSB_DSTBN_L FSB_DSTBP_L FSB_HIT_L FSB_HITM_L FSB_LOCK_L FSB_REQ_L om p P5VS5_RUNSS P1V5S0_RUNSS P1V2S3_RT P1V2S3_RUNSS P3V3S5_COMP P3V3S5_FSET P1V05S0_COMP P1V05S0_FSET 59B7 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE LPC_AD LPC_AD LPC_FRAME_L PM_CLKRUN_L BOOT_LPC_SPI_L SMC_TMS DEBUG_RST_L SMC_TRST_L SMC_TDO SMC_MD1 SMC_TX_L FWH_INIT_L PCI_CLK_PORT80_LPC LPC_AD LPC_AD INT_SERIRQ PM_SUS_STAT_L SMC_TDI SMC_TCK SMC_RST_L SMC_NMI SMC_RX_L SV_SET_UP TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE 51C4 65D3 51C4 65A1 21D4 49D7 51C4 58C6 21D4 49D7 51C4 58C6 21C5 49C7 51C4 58C6 22B3 49C7 51B4 49B5 50B2 51B4 26B1 51B4 49C1 51B4 49B5 50B2 51B4 49C1 51B4 46B5 49C7 50B2 50B3 51B4 21C4 50D3 51C5 34D6 51C5 21D4 49C7 51C5 58C6 21D4 49C7 51C5 58C6 23C8 49C7 51C5 58C6 23C5 49C5 50A2 51B5 58C6 49B5 50B2 51B5 49C5 50B2 51B5 49C3 50D6 51B5 49C1 51B5 46B5 49C7 50B2 50B3 51B5 23B6 23C3 51B5 FUNC_TEST =PP3V3_S3_LTALS ALS_GAIN LTALS_OUT GND TRUE TRUE TRUE TRUE 65C3 78C5 6D5 49B5 78C6 55C7 78C6 Thermal Diode Connectors FUNC_TEST HSTHMSNS_DX_P HSTHMSNS_DX_N RSFSTHMSNS_D_P RSFSTHMSNS_D_N TRUE TRUE TRUE TRUE 52C5 52C5 52D5 52C5 Other Func Test Points FUNC_TEST TRUE =PP1V05_S0_REG TRUE TRUE PM_SYSRST_L SMC_ONOFF_L 53A4 63A2 65D8 23C5 26C5 49B7 TPs per TRUE TRUE TRUE TRUE =PP1V8_S3_REG =PP1V5_S0_REG PPVCORE_S0_GPU PPVCORE_S0_CPU TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE ACZ_SDATAIN ACZ_SDATAOUT ACZ_BITCLK ACZ_RST_L EXCARD_OC_L LTUSB_OC_L LIO_BATT_ISENSE SMC_SYS_ISET SMC_BATT_ISET SMC_BATT_CHG_EN SMC_BC_ACOK SMC_ADAPTER_EN LIO_P3V3S0_EN_L LIO_DCIN_ISENSE LIO_P3V3S3_EN SMC_BATT_TRICKLE_EN_L SYS_ONEWIRE MINI_CLKREQ_L SMC_EXCARD_CP EXCARD_CLKREQ_L SMC_EXCARD_PWR_EN LIO_PLT_RESET_L ACZ_SYNC =USB2_LT_N =USB2_LT_P =USB2_EXCARD_N =USB2_EXCARD_P =PCIE_EXCARD_R2D_N =PCIE_EXCARD_R2D_P =PCIE_EXCARD_D2R_N =PCIE_EXCARD_D2R_P PCIE_CLK100M_EXCARD_P PCIE_CLK100M_EXCARD_N =PCIE_MINI_R2D_N =PCIE_MINI_R2D_P =PCIE_MINI_D2R_N =PCIE_MINI_D2R_P PCIE_CLK100M_MINI_P PCIE_CLK100M_MINI_N =SMBUS_LIO_SMC_SCL =SMBUS_LIO_SMC_SDA =SMBUS_LIO_SB_SCL =SMBUS_LIO_SB_SDA PCIE_WAKE_L 47D6 65C6 47C6 65A8 47C6 65B1 47D6 65D3 47D4 47C4 47A4 47A4 21C7 47B6 84B4 21C7 47B6 84B4 21C7 47B6 84B4 21C7 47B3 84B4 6C3 47C6 50B3 6D3 47C6 47C6 53C3 47C6 49B5 47B6 49B5 47C6 49D7 50A2 47B6 49C5 50A2 43B7 47C6 49D5 50A2 47B6 64C6 47B6 53C5 C 47B6 64A6 47B6 49D7 50A2 47C6 49B7 50B2 34A3 47C6 47B6 49B7 50A2 34A3 47C6 47B6 49B7 26C1 47C6 21C7 47B6 84B4 6D3 47C3 6D3 47C3 6C3 47C3 6C3 47C3 47B3 48C6 47B3 48C6 47B3 48B6 47B3 48C6 34C3 47B3 34B3 47B3 47B3 48C6 47B3 48C6 47C3 48C6 47C3 48C6 34D4 47C3 34D4 47C3 27D1 47C3 B 27D1 47C3 27B6 47C3 27B6 47C3 23C8 39C6 47C3 Left I/O Power Connector FUNC_TEST FUNC_TEST ISENSE_CAL_EN =PP5V_S0_ISENSECAL =PP1V5_S0_LIO =PPDCIN_G3H_LIO =PP5V_S5_LIO =PP3V42_G3H_LIO PP5V_S0_AUDIO_PWR PP5V_S0_AUDIO GND_AUDIO_PWR GND_AUDIO 49C5 50B2 50C6 78C2 Current Sense Calibration TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE 23C8 49C5 51C4 58C6 Left ALS Connector yc TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE 59C7 /m IMVP6_RBIAS IMVP6_COMP EXPOSED_VIA p: / TRUE TRUE TRUE TRUE C NO_TEST tt D CPU FSB NO_TESTs EXPOSED_VIA h NO_TEST 53A8 65A1 62C1 65B8 60C1 65C8 =PPBUS_G3H_LIO_CONN GND TRUE TRUE 49B7 53A8 65C3 66C4 Request for at least 10 GND test points NOTE: 10 additional GND test points are called out separately in these notes 65D1 GND TRUE TPs, with each of above TP pairs Camera Connector EXPOSED_VIA property indicates that the net A should have a via with 10-mil soldermask TRUE opening for use as engineering probe point Misc EXPOSED_VIA Nets Functional / ICT Test FUNC_TEST =PP5V_S3_CAMERA =USB2_CAMERA_N =USB2_CAMERA_P 45C3 65B1 6C3 45C3 SYNC_MASTER=N/A PPVBATT_G3C_RTC GND TRUE TRUE 26D6 SYNC_DATE=N/A NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING 6D3 45B3 Inverter Connector I TO MAINTAIN THE DOCUMENT IN CONFIDENCE FUNC_TEST EXPOSED_VIA TRUE TRUE TRUE TRUE RTC Battery Connector FUNC_TEST II NOT TO REPRODUCE OR COPY IT DMI_N2S_P DMI_N2S_N SB_CLK100M_SATA_P SB_CLK100M_SATA_N TRUE TRUE TRUE TRUE TRUE 14B4 22D2 14B4 22D2 21B6 34C3 21B6 34C3 GND_CHASSIS_INVERTER PPBUS_S0_INVERTER GND_INVERTER INVERTER_PWM PP5V_INVERTER_SW III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART 6A8 76B5 SIZE 76A5 76A5 APPLE COMPUTER INC 76B5 DRAWING NUMBER D SCALE SHT NONE REV 051-7150 A.0.0 OF 84 A USB Port "A" (Debug Port) = Right USB 2.0 Port 46B5 =USB2_RT_P 46B5 =USB2_RT_N USB2_RT_P USB_A_P 22C2 USB_A_N 22C2 USB_A_OC_L 22C4 22D8 MAKE_BASE=TRUE USB2_RT_N MAKE_BASE=TRUE NC_CPU_A32_L TP_CPU_A32_L 7C8 NC_MEM_A_A TP_CPU_A33_L 7B8 NC_MEM_B_A TP_CPU_A34_L 7B8 MAKE_BASE=TRUE NO_TEST=TRUE 28C3 MEM_B_A 29C3 NB_CFG 14C6 TP_SMC_RSTGATE_L MAKE_BASE=TRUE NO_TEST=TRUE NC_CPU_A33_L MAKE_BASE=TRUE NO_TEST=TRUE 7B8 TP_NB_CFG 78C6 49B5 5B2 7B8 TP_CPU_A37_L 7B8 =USB_TRACKPAD_P =USB_TRACKPAD_N TP_CPU_A38_L 7B8 USB_TRACKPAD_N NB_CFG NC_ENET_CTRL12 14C6 ENET_CTRL12 NB_CFG NC_ENET_CTRL25 14C6 ENET_CTRL25 47C3 5B1 =USB2_LT_P 47C3 5B1 =USB2_LT_N 7B8 NB_CFG 14C6 47C6 5C1 TP_NB_CFG NB_CFG USB2_LT_P USB2_LT_N LTUSB_OC_L Ethernet Power Management Support 14C6 7B8 TP_CPU_APM1_L 7B8 TP_CPU_EXTBREF 7B6 TP_CPU_HFPLL 7B8 NOTE: NB_CFG require test access TP_NB_CFG MAKE_BASE=TRUE NO_TEST=TRUE TP_SB_SUS_CLK SUS_CLK_SB SB_GPIO30 TP_CPU_SPARE0 7B6 NC_SB_XOR_T5 21C6 7B6 NC_SB_XOR_U5 TP_CPU_SPARE2 7B6 TP_CPU_SPARE4 7B6 NC_SB_XOR_V3 TP_SB_XOR_U5 21C6 TP_SB_XOR_V3 21C6 C TP_SB_XOR_V4 21C6 TP_SB_XOR_W3 NC_SB_XOR_W3 21C6 M59_INVERTER_PLT_RST_L FireWire Aliases =PP1V95_FWPHY_CORE_LDO 49D7 6D4 =PP3V3_FWPHY =PP3V3_FWPHY_CORE =PP3V3_FWLATEVG =PP3V3_FWLATEVG_ACTIVE 38D7 44B8 42C4 44A8 43A7 PP1V95_FWPHY =PP1V95_FWPHY 38D5 VOLTAGE=1.95V MIN_LINE_WIDTH=0.38 mm MIN_NECK_WIDTH=0.25 mm MAKE_BASE=TRUE =PP1V8_FWPHY_OSC 38B2 =SMC_FWRSTGATE_L 37A8 =FW_PCI_IDSEL 37B7 =FW_PCI_GNT_L 37D3 =FW_PCI_REQ_L 37D3 SMC_RSTGATE_L MAKE_BASE=TRUE 37C6 22A7 PCI_AD MAKE_BASE=TRUE PCI_GNT3_L 22B6 /m PCI_REQ3_L Top CPU TM Hole Chassis GNDs GND_CHASSIS_RTUSB 46B2 p: / =GND_CHASSIS_RTUSB =GND_CHASSIS_FW_PORT2L =GND_CHASSIS_FW_EMI_R 44A1 44A3 Left CPU TM Hole GND_CHASSIS_DVI_TOP MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=0V MAKE_BASE=TRUE 0.01UF C0600 =GND_CHASSIS_DVI2 =GND_CHASSIS_DVI4 77A5 77A3 R0601 =GND_CHASSIS_DVI1 =GND_CHASSIS_DVI3 =GND_CHASSIS_DVI5 77B5 77A2 77A2 SHLD-SM-LF USB_IR_P USB_IR_N 22C2 USB_G_P 22C2 USB_G_N 22C2 MAKE_BASE=TRUE 76A8 78C2 =USB_BT_P 78C2 =USB_BT_N USB_BT_P C MAKE_BASE=TRUE USB_BT_N MAKE_BASE=TRUE USB Port "H" = Reserved TP_USB_H_P 22C2 6C1 TP_USB_H_P 6C2 22C2 TP_USB_H_N 6C2 22C2 MAKE_BASE=TRUE TP_USB_H_N 22C2 6C1 MAKE_BASE=TRUE LVDS pulldown aliases 79B8 =LVDS_PD_U_CLK_N 79B8 =LVDS_PD_U_CLK_P LVDS_U_CLK_CONN_N 76B2 76D7 79C1 MAKE_BASE=TRUE LVDS_U_CLK_CONN_P 79C8 =LVDS_PD_U_DATA_P 76B2 76D7 79C1 79C8 =LVDS_PD_U_DATA_N LVDS_U_DATA_CONN_P 76C2 76D7 79D1 LVDS_U_DATA_CONN_N 76C2 76D7 79D1 MAKE_BASE=TRUE 79B8 =LVDS_PD_U_DATA_P 79B8 =LVDS_PD_U_DATA_N 79B8 =LVDS_PD_U_DATA_P 79B8 =LVDS_PD_U_DATA_N 79C8 =LVDS_PD_L_CLK_N LVDS_U_DATA_CONN_P 76C2 76D7 79C1 LVDS_U_DATA_CONN_P 76B2 76D7 79C1 LVDS_U_DATA_CONN_N 76C2 76D7 79D1 LVDS_L_CLK_CONN_N 79C8 =LVDS_PD_L_CLK_P 76C2 76D7 79C1 LVDS_L_CLK_CONN_P 79D8 =LVDS_PD_L_DATA_P 76C2 76D7 79C1 LVDS_L_DATA_CONN_P 76C2 76D7 79C1 MAKE_BASE=TRUE 79D8 =LVDS_PD_L_DATA_N LVDS_L_DATA_CONN_N 76C2 76D7 79C1 MAKE_BASE=TRUE 79D8 =LVDS_PD_L_DATA_P 79C8 =LVDS_PD_L_DATA_N LVDS_L_DATA_CONN_P 76C2 76D7 79C1 MAKE_BASE=TRUE MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=0V LVDS_L_DATA_CONN_N 76C2 76D7 79C1 MAKE_BASE=TRUE 79C8 =LVDS_PD_L_DATA_P 79C8 =LVDS_PD_L_DATA_N LVDS_L_DATA_CONN_P 76C2 76D7 79C1 MAKE_BASE=TRUE MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=0V LVDS_L_DATA_CONN_N 76C2 76D7 79C1 MAKE_BASE=TRUE GND_CHASSIS_DIMM_NOTCH 76D3 1GND_CHASSIS_LIOFLEX_HOLE MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=0V C0630 ZT0611 0.01UF HOLE-VIA-P5RP25 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=0V ZT0610 HOLE-VIA-P5RP25 1GND_CHASSIS_LNDACARD_HOLE C0631 0.01UF 10% 50V X7R 402 45B5 45C5 10% 50V X7R 402 C0611 10% 50V X7R 402 0.01UF ZT0631 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=0V SYNC_MASTER=N/A C0615 SYNC_DATE=N/A NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING C0614 0.01UF 10% 50V X7R 402 10% 50V X7R 402 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART C0610 0.01UF C0613 SIZE 0.01UF 10% 50V X7R 402 10% 50V X7R 402 APPLE COMPUTER INC DRAWING NUMBER D SHT NONE REV 051-7150 SCALE A 0.01UF C0612 0.01UF 1GND_CHASSIS_BATTCONN_HOLE HOLE-VIA-P5RP25 76A6 1 76C3 76B2 Signal Aliases/Misc Comps HOLE-VIA-P5RP25 10% 50V X7R 402 76D2 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=0V B 76C2 76D7 79C1 LVDS_U_DATA_CONN_N MAKE_BASE=TRUE GND_CHASSIS_RIGHT_FAN_HOLE GND_CHASSIS_RAMDOOR_HOLE_0 GND_CHASSIS_INVERTER =GND_CHASSIS_INVERTER =GND_CHASSIS_CAMERA 22C2 USB_F_N USB Port "G" = Bluetooth (M13L) HOLE-VIA-P5RP25 HOLE-VIA-P5RP25 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=0V =GND_CHASSIS_LCD1 =GND_CHASSIS_LCD2 =GND_CHASSIS_LCD3 =GND_CHASSIS_LCD4 USB_F_P MAKE_BASE=TRUE MAKE_BASE=TRUE ZT0612 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=0V MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=0V MAKE_BASE=TRUE =USB_IR_N ZT0615 GND_CHASSIS_RAMDOOR_HOLE_1 5A4 78B4 HOLE-VIA-P5RP25 GND_CHASSIS_LVDS 10% 50V X7R 402 =USB_IR_P Frame holes RAM door (Torx) holes HOLE-VIA-P5RP25 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=0V MAKE_BASE=TRUE 22C4 22D8 MAKE_BASE=TRUE ZT0630 22C2 USB_E_OC_L MAKE_BASE=TRUE 40B2 ZT0602 0.01UF 22C2 USB_E_N MAKE_BASE=TRUE ZT0613 Chassis connection to be made at the mounting hole east of the LVDS connector USB_E_P USB Port "F" = IR Receiver 78B4 GND_CHASSIS_RIGHT_FAN_NOTCH 44A1 USB2_EXCARD_N MAKE_BASE=TRUE Top GPU Right TM Hole ZT0614 44C1 22C4 22D8 MAKE_BASE=TRUE HOLE-VIA-P5RP25 =GND_CHASSIS_ENET =GND_CHASSIS_FW_PORT1 =GND_CHASSIS_FW_PORT2U 22C2 USB_D_OC_L MAKE_BASE=TRUE GND_CHASSIS_ENET C0602 22C2 USB_D_N MAKE_BASE=TRUE 5% 1/16W MF-LF 402 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=0V MAKE_BASE=TRUE USB2_EXCARD_P EXCARD_OC_L Bottom Left GPU TM Hole h GND_CHASSIS_DVI_BOT USB_D_P MAKE_BASE=TRUE Right CPU TM Hole tt 10% 50V X7R 402 =USB2_EXCARD_N Add blind vias per hole per side to GND MAKE_BASE=TRUE MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=0V MAKE_BASE=TRUE 47C3 5B1 Thermal Module Holes MAKE_BASE=TRUE 26D2 22B6 =USB2_EXCARD_P yc PP3V3_FWPHY =INVERTER_PWM_PLT_RST_L 47C3 5B1 50B3 47C6 5C1 om p 26C1 VOLTAGE=3.3V MIN_LINE_WIDTH=0.38 mm MIN_NECK_WIDTH=0.25 mm MAKE_BASE=TRUE USB2_CAMERA_N MAKE_BASE=TRUE Inverter PWM Reset Alias MAKE_BASE=TRUE NO_TEST=TRUE =PP3V3_FWPHY_REG USB2_CAMERA_P USB Port "E" = ExpressCard su NC_SB_XOR_V4 MAKE_BASE=TRUE NO_TEST=TRUE MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=0V MAKE_BASE=TRUE 22C4 22D8 MAKE_BASE=TRUE MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE B 22C2 USB_C_OC_L MAKE_BASE=TRUE OUT MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE =USB2_CAMERA_N UNUSED_USB_D_OC_L 39B8 ENET_LOWPWR_EN NOTE: BOM options "USB_G_OC_PU" and "ENET_LOWPWR_EN" are mutually-exclusive MAKE_BASE=TRUE NO_TEST=TRUE TP_CPU_SPARE1 MAKE_BASE=TRUE NO_TEST=TRUE NC_CPU_SPARE4 TP_SB_XOR_T5 5% 1/16W MF-LF 402 23C3 MAKE_BASE=TRUE MAKE_BASE=TRUE NO_TEST=TRUE =USB2_CAMERA_P 45C3 5A4 R0600 IN MAKE_BASE=TRUE NO_TEST=TRUE NC_CPU_SPARE2 22C2 USB_C_N MAKE_BASE=TRUE 14C6 22D8 22C4 MAKE_BASE=TRUE NO_TEST=TRUE 45B3 5A4 ENET_LOWPWR_EN NB_CFG MAKE_BASE=TRUE NC_CPU_SPARE1 USB_C_P USB Port "D" = Camera /x / TP_CPU_APM0_L MAKE_BASE=TRUE NO_TEST=TRUE NC_CPU_SPARE0 D MAKE_BASE=TRUE MAKE_BASE=TRUE NC_CPU_HFPLL 22C4 22D8 MAKE_BASE=TRUE TP_CPU_A39_L NC_CPU_EXTBREF 22C2 USB_B_OC_L MAKE_BASE=TRUE 39C8 MAKE_BASE=TRUE NO_TEST=TRUE TP_NB_CFG MAKE_BASE=TRUE NO_TEST=TRUE NC_CPU_APM1_L 22C2 USB_B_N USB Port "C" = Left USB 2.0 Port 39C8 MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NC_CPU_APM0_L USB_B_P MAKE_BASE=TRUE TP_NB_CFG MAKE_BASE=TRUE NO_TEST=TRUE NC_CPU_A39_L USB_TRACKPAD_P UNUSED_USB_B_OC_L 14C6 MAKE_BASE=TRUE NC_CPU_A38_L OG-503040 78C3 78C3 MAKE_BASE=TRUE NB_CFG TP_NB_CFG MAKE_BASE=TRUE NO_TEST=TRUE USB Port "B" = Trackpad (Geyser) MAKE_BASE=TRUE MAKE_BASE=TRUE NC_CPU_A37_L RTUSB_OC_L MAKE_BASE=TRUE ALS_GAIN MAKE_BASE=TRUE TP_CPU_A36_L MAKE_BASE=TRUE NO_TEST=TRUE SH0600 55C4 =RTUSB_OC_L MAKE_BASE=TRUE TP_CPU_A35_L NC_CPU_A36_L A =RTALS_GAIN 46C5 MAKE_BASE=TRUE NC_CPU_A35_L 42C1 6B7 49D7 MAKE_BASE=TRUE TP_NB_CFG MAKE_BASE=TRUE NO_TEST=TRUE 42C4 SMC_RSTGATE_L MAKE_BASE=TRUE NO_TEST=TRUE NC_CPU_A34_L MAKE_BASE=TRUE NO_TEST=TRUE D MEM_A_A A.0.0 OF 84 OMIT U0700 IO 84D6 12D4 5D5 IO 84D6 12C4 5D5 IO 84C6 12C4 5D5 IO 84D6 12B4 5D5 84D6 12B4 5D5 84D6 12A4 5D5 IO 84D6 12A4 5D5 IO 84D6 12C4 5D5 IO 84D6 12C4 5D5 IO 84D6 12C4 5D5 IO 84D6 12C4 5D5 IO 84D6 12C4 5D5 IO 84D6 12C4 5D5 84D6 12C4 5D5 84D6 12C4 5D5 84D6 12C4 5D5 84D6 12C4 5D5 84D6 12C4 5D5 84D6 12C4 5D5 84D6 12C4 5D5 C IO IO 84D6 12C4 5D5 84D6 12C4 5D5 84C6 12C4 5D5 84C6 21C4 21C2 84C6 21C4 84C6 21C4 84C6 21C4 84C6 21C4 84C6 21C4 FSB_REQ_L FSB_REQ_L FSB_REQ_L FSB_REQ_L FSB_REQ_L IO 84D6 12A4 5D5 P1 A15* R1 A16* L2 ADSTB0* IO IO IO IO IO IO IO IO IO IO OUT IN IN IN IN W6 A20* U4 A21* Y5 A22* U2 A23* R4 A24* T5 A25* T3 A26* W3 A27* W5 A28* Y4 A29* W2 A30* Y1 A31* V4 ADSTB1* IN FSB_LOCK_L IO LOCK* H4 84D6 12B4 5D5 RESET* RS0* B1 84D6 12C4 11B5 IN F3 F4 84D6 12A4 IN 84D6 12A4 IN G3 84D6 IN TRDY* G2 84D6 HIT* G6 E4 D5 STPCLK* C6 LINT0 B4 LINT1 A3 SMI* TP_CPU_A32_L 6D7 TP_CPU_A33_L 6D7 TP_CPU_A34_L 6D7 TP_CPU_A35_L 6D7 TP_CPU_A36_L 6D7 TP_CPU_A37_L 6D7 TP_CPU_A38_L 6D7 TP_CPU_A39_L 6D7 TP_CPU_APM0_L 6C7 TP_CPU_APM1_L AA1 RSVD1 AA4 RSVD2 AB2 RSVD3 AA3 RSVD4 M4 RSVD5 N5 RSVD6 T2 RSVD7 V3 RSVD8 B2 RSVD9 C3 RSVD10 TP_CPU_HFPLL B25 RSVD11 PLACE TESTPOINT ON FSB_IERR_L WITH A GND 0.1" AWAY 84C6 84C6 FSB_CPURST_L FSB_RS_L FSB_RS_L 12A4 FSB_RS_L 12A4 FSB_TRDY_L =PP1V05_S0_CPU IN FSB_HIT_L 5D5 FSB_HITM_L 84D6 12B4 5D5 IO 84D6 12B4 IO BPM0* BPM1* BPM2* BPM3* PRDY* PREQ* TCK TDI TDO TMS TRST* DBR* AD4 AD3 AD1 AC4 AC2 AC1 AC5 AA6 AB3 AB5 AB6 C20 THERMDA D21 A24 THERMDC A25 PROCHOT* THERMTRIP* BCLK0 BCLK1 RSVD12 RSVD13 RSVD14 RSVD15 RSVD16 RSVD17 RSVD18 RSVD19 RSVD20 C7 IO IO IO 54.9 OMIT 1% 1/16W MF-LF 402 U0700 IO IO IO IN IN R0704 OUT 5% 1/16W MF-LF 402 IN IN OUT CPU_PROCHOT_L 10B6 CPU_THERMD_P 10B6 CPU_THERMD_N 50C1 21C2 14B6 OUT OUT FSB_CLK_CPU_P 34D3 FSB_CLK_CPU_N IN TP_CPU_SPARE0 TP_CPU_SPARE1 TP_CPU_SPARE2 TP_CPU_SPARE3 TP_CPU_SPARE4 TP_CPU_SPARE5 TP_CPU_SPARE6 TP_CPU_SPARE7 D2 F6 D3 C1 AF1 D22 C23 C24 PM_THRMTRIP# SHOULD CONNECT TO ICH7-M AND GMCH WITHOUT T-ING (NO STUB) IN TP_CPU_EXTBREF T22 6C7 6C7 6C7 6C7 R0720 XDP_TMS 54.9 6C7 R0721 11B3 7C6 XDP_TDI 54.9 R0722 11B3 7C6 XDP_TCK 54.9 84D6 12D6 5D5 IO 84D6 12D6 5D5 IO IO 84D6 12D6 5D5 IO 84D6 12D6 5D5 IO 84D6 12D6 5D5 IO FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_DSTBN_L FSB_DSTBP_L FSB_DINV_L 84D6 12D6 5D5 IO 84D6 12D6 5D5 IO 84D6 12D6 5D5 IO IO 84D6 12D6 5D5 IO 84D6 12C6 5D5 IO 84D6 12C6 5D5 IO 84D6 12C6 5D5 IO 84D6 12B4 5D5 IO 84D6 12B4 5D5 IO 84D6 12C6 5D5 IO 84D6 12C6 5D5 IO 84D6 12C6 5D5 IO 84D6 12C6 5D5 IO 84D6 12C6 5D5 IO 84D6 12C6 5D5 IO 84D6 12C6 5D5 IO 84D6 12C6 5D5 IO 84D6 12C6 5D5 IO 84D6 12C6 5D5 IO 84D6 12C6 5D5 IO 84D6 12C6 5D5 IO 84D6 12C6 5D5 IO 84D6 12C6 5D5 84D6 12C6 5D5 R0705 1K 1% 1/16W MF-LF 402 E22 D0* F24 D1* E26 D2* 1% 1/16W MF-LF 402 34C6 OUT 34B6 OUT 34B6 OUT 84D6 12C6 5D5 IO IO IO 84D6 12B4 5D5 IO 84D6 12B4 5D5 IO 84D6 12B4 5D5 IO E25 D6* E23 D7* K24 D8* G24 D9* J24 D10* J23 D11* H26 D12* F26 D13* K22 D14* H25 D15* H23 DSTBN0* D32* D33* BGA (2 OF 4) D34* D35* D36* D37* D38* D39* D40* D41* D42* D43* D44* D45* D46* D47* DSTBN2* DSTBP2* G22 DSTBP0* J26 DINV0* DINV2* N22 D16* K25 D17* P26 D18* R23 D19* L25 D20* L22 D21* L23 D22* M23 D23* P25 D24* P22 D25* P23 D26* T24 D27* R24 D28* D48* D49* D50* D51* D52* D53* L26 D29* T25 D30* N24 D31* M24 DSTBN1* N25 DSTBP1* CPU_TEST1 C26 TEST1 CPU_TEST2 D25 TEST2 CPU_BSEL CPU_BSEL CPU_BSEL B22 BSEL0 B23 BSEL1 C21 BSEL2 D54* D55* D56* D57* D58* D59* D60* D61* D62* D63* DSTBN3* DSTBP3* DINV3* M26 DINV1* AD26 GTLREF A2 NC LAYOUT NOTE: 0.5" MAX LENGTH YONAH CPU H22 D3* F23 D4* G25 D5* FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_DSTBN_L FSB_DSTBP_L FSB_DINV_L CPU_GTLREF R0706 2.0K IO MISC 402 R0712 1% 402 51 5% 1/16W MF-LF 402 AB24 V24 V26 W25 U23 U25 U22 AB25 W22 Y23 AA26 Y26 Y22 AC26 AA24 W24 SLP* PSI* IO 84D6 12C6 84D6 12C6 84D6 12C6 84D6 12B6 84D6 12B6 84D6 12B6 84D6 12B6 84D6 12B6 84D6 12B6 84D6 12B6 84D6 12B6 84D6 12B6 84D6 12B4 V23 84D6 12B4 AC22 AC23 AB22 AA21 AB21 AC25 AD20 AE22 AF23 AD24 AE21 AD21 AE25 AF25 AF22 AF26 AD23 AE24 AC20 U26 U1 PWRGOOD IO 84D6 12C6 5D5 84D6 12C6 5D5 84D6 12B4 COMP1 DPSLP* DPWR* 84D6 12C6 5D5 84D6 12C6 5D5 Y25 R26 DPRSTP* R0730 AA23 COMP0 COMP2 COMP3 NOSTUFF h 1% 402 =PP1V05_S0_CPU 84C6 tt 1% 402 IO 84D6 12B4 5D5 SPARE[7-0],HFPLL: ROUTE TO TP VIA AND PLACE GND VIA W/IN 1000 MILS p: / 7B5 7D5 8C7 9B7 11B3 11C5 65D6 IO 84D6 12D6 5D5 84D6 12D6 5D5 OUT 34D3 A21 CPU_PROCHOT_L TO SMC AND CPU VR TO INFORM CPU IS HOT OUT PM_THRMTRIP_L 84D6 12D6 5D5 84D6 12D6 5D5 68 50D3 50C1 A22 =PP1V05_S0_CPU 11B3 7C6 7B5 7B6 7D5 8C7 9B7 11B3 11C5 65D6 R0703 XDP_BPM_L 84C6 11B3 XDP_BPM_L 84C6 11B3 XDP_BPM_L 84C6 11B3 XDP_BPM_L 84C6 11B3 XDP_BPM_L 84C6 11B3 XDP_BPM_L 11B3 7A8 XDP_TCK 11B3 7B8 XDP_TDI 11B5 XDP_TDO 11B3 7B8 XDP_TMS 11B3 XDP_TRST_L 26C6 11B4 XDP_DBRESET_L 84C6 11B3 65D6 11C5 11B3 9B7 8C7 7D5 7B6 B D A6 A20M* A5 FERR* C4 IGNNE* 6D7 6C7 IO FSB_IERR_L 21C4 CPU_INIT_L INIT* HITM* Y2 A17* U5 A18* R3 A19* CPU_STPCLK_L CPU_INTR CPU_NMI CPU_SMI_L IN IO FSB_BREQ0_L D20 B3 IERR* 1% 1/16W MF-LF 402 IO L5 REQ4* CPU_A20M_L CPU_FERR_L CPU_IGNNE_L IN 84D6 12C4 5D5 RS1* RS2* K3 REQ0* H2 REQ1* K2 REQ2* J3 REQ3* FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_ADSTB_L IO 84D6 12B4 F1 54.9 IO DATA GRP2 IO 84D6 12D4 5D5 E1 BR0* 84D6 12B4 R0702 IO FSB_DEFER_L 5D5 FSB_DRDY_L 5D5 FSB_DBSY_L DATA GRP3 84D6 12D4 5D5 P2 A12* L1 A13* P4 A14* DBSY* F21 84D6 DATA GRP0 IO 84D6 12B4 DATA GRP1 IO 84D6 12D4 5D5 H5 /x / 84D6 12D4 5D5 J1 A9* N3 A10* P5 A11* DEFER* DRDY* 7B5 7B6 7D5 8C7 9B7 11B3 11C5 65D6 su IO IO om p IO 84D6 12D4 5D5 IO 84D6 12C4 5D5 yc IO 84D6 12D4 5D5 84D6 12C4 5D5 E2 G5 BPRI* BGA =PP1V05_S0_CPU FSB_ADS_L FSB_BNR_L 12C4 FSB_BPRI_L H1 ADS* BNR* /m 84D6 12D4 5D5 (1 OF 4) CONTROL D IO K5 A6* M1 A7* N2 A8* XDP/ITP SIGNALS IO THERM IO 84D6 12D4 5D5 YONAH CPU HCLK 84D6 12D4 5D5 84D6 12D4 5D5 J4 A3* L4 A4* M3 A5* ADDR GROUP0 IO FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_ADSTB_L ADDR GROUP1 IO 84D6 12D4 5D5 RESERVED 84D6 12D4 5D5 FSB_D_L FSB_D_L FSB_D_L FSB_D_L 5D5 FSB_D_L 5D5 FSB_D_L 5D5 FSB_D_L 5D5 FSB_D_L 5D5 FSB_D_L 5D5 FSB_D_L 5D5 FSB_D_L 5D5 FSB_D_L 5D5 FSB_D_L 5D5 FSB_D_L 5D5 FSB_D_L 5D5 FSB_D_L 5D5 FSB_DSTBN_L 5D5 FSB_DSTBP_L 5D5 FSB_DINV_L 84D6 12B6 5D5 84D6 12B6 5D5 84D6 12B6 5D5 84D6 12B6 84D6 12B6 84D6 12B6 84D6 12B6 84D6 12B6 84D6 12B6 84D6 12B6 84D6 12B6 84D6 12B6 84D6 12B6 84D6 12B6 84D6 12B6 84D6 12B6 84D6 12B4 84D6 12B4 84D6 12B4 FSB_D_L FSB_D_L FSB_D_L 5D5 FSB_D_L 5D5 FSB_D_L 5D5 FSB_D_L 5D5 FSB_D_L 5D5 FSB_D_L 5D5 FSB_D_L 5D5 FSB_D_L 5D5 FSB_D_L 5D5 FSB_D_L 5D5 FSB_D_L 5D5 FSB_D_L 5D5 FSB_D_L 5D5 FSB_D_L 5D5 FSB_DSTBN_L 5D5 FSB_DSTBP_L 5D5 FSB_DINV_L IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO LAYOUT NOTE: COMP0,2 CONNECT WITH TRACE LENGTH SHORTER COMP1,3 CONNECT WITH TRACE LENGTH SHORTER IO IO IO IO IO R0716 IO IO IO 27.4 402 R0717 IO IO 54.9 1% IO 402 B R0718 IO CPU_COMP 84C6 CPU_COMP 84C6 CPU_COMP 84C6 CPU_COMP CPU_DPRSTP_L 21C4 CPU_DPSLP_L 12B4 FSB_DPWR_L 21C4 CPU_PWRGD 12A4 FSB_SLPCPU_L 59C7 CPU_PSI_L ZO=27.4OHM, MAKE THAN 0.5" ZO=55OHM, MAKE THAN 0.5" IO 84C6 V1 27.4 R0719 E5 B5 59C7 21C4 IN 84C6 IN D24 84D6 D6 D7 84C6 AE6 C IO 54.9 1% 402 IN IN IN IN NOSTUFF R0707 1K 5% 1/16W MF-LF 402 CHANGE THE PULLS RESISTOR VALUE PER NAPA PLATFORM DG REV 0.9 CPU OF 2-FSB WE THROUGH THE ITP700FLEX CONNECTOR CONNECT TO PDB XDP BUFFER BOARD ECM*50 SO THE TDI PULL UP THROUGH 54.9 OHM,TMS PULL UP THROUGH 54.9 OHM TCK PULL DOWN THROUGH 54.9 OHM(FOLLOW UP XDP DESIGN REFERENCE) A SYNC_MASTER=(MASTER) SYNC_DATE=(MASTER) NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE APPLE COMPUTER INC DRAWING NUMBER D SCALE SHT NONE REV 051-7150 A.0.0 OF 84 A OMIT A4 VSS_1 A8 VSS_2 A11 VSS_3 =PPVCORE_S0_CPU OMIT VCC_71 AC9 VCC_72 AC12 VCC_73 AC13 VCC_74 AC15 VCC_75 AC17 VCC_76 AC18 B7 VCC_10 B9 VCC_11 B10 VCC_12 VCC_77 AD7 VCC_78 AD9 VCC_79 AD10 B12 VCC_13 B14 VCC_14 B15 VCC_15 VCC_80 AD12 VCC_81 AD14 VCC_91 AE18 VCC_92 AE20 VCC_93 AF9 VCC_94 AF10 VCC_95 AF12 VCC_96 AF14 VCC_97 AF15 VCC_98 AF17 D15 VCC_30 D17 VCC_31 D18 VCC_32 E7 VCC_33 VCC_99 AF18 VCC_100 AF20 E9 VCC_34 E10 VCC_35 E12 VCC_36 VCCP_1 V6 VCCP_2 G21 E13 VCC_37 E15 VCC_38 E17 VCC_39 VCCP_3 J6 VCCP_4 K6 VCCP_5 M6 E18 VCC_40 E20 VCC_41 F7 VCC_42 VCCP_6 J21 VCCP_7 K21 VCCP_8 M21 F9 VCC_43 F10 VCC_44 F12 VCC_45 VCCP_9 N21 VCCP_10 N6 VCCP_11 R21 F14 VCC_46 F15 VCC_47 F17 VCC_48 VCCP_12 R6 VCCP_13 T21 F18 VCC_49 F20 VCC_50 AA7 VCC_51 AA9 VCC_52 AA10 VCC_53 AA12 VCC_54 AA13 VCC_55 AA15 VCC_56 AA17 VCC_57 AA18 VCC_58 AA20 VCC_59 AB9 VCC_60 AC10 VCC_61 =PP1V05_S0_CPU 7B5 7B6 7D5 9B7 11B3 11C5 65D6 (CPU IO POWER 1.05V) VCCP_14 T6 VCCP_15 V21 VCCP_16 W21 VCCA=1.5 ONLY VCCA B26 =PP1V5_S0_CPU 9B7 65C6 (CPU INTERNAL PLL POWER 1.5V) VID0 AD6 VID1 AF5 VID2 AE5 VID3 AF4 VID4 AE3 VID5 AF2 VID6 AE2 CPU_VID CPU_VID CPU_VID CPU_VID CPU_VID CPU_VID CPU_VID OUT 9C2 84B6 OUT 9C2 84B6 OUT 9C2 84B6 OUT 9C2 84B6 OUT 9C2 84B6 OUT 9C2 84B6 OUT 9C2 84B6 =PPVCORE_S0_CPU VID FOR CPU POWER SUPPLY IF NO USE, NEED PULL-UP OR PULL-DOWN R0802 100 1% 1/16W MF-LF AB10 VCC_62 AB12 VCC_63 AB14 VCC_64 402 CPU_VCCSENSE_P VSSSENSE AE7 CPU_VCCSENSE_N R0803 LAYOUT NOTE: CONNECT R0803 TO TP_VSSSENSE WITH NO STUB 100 1% 1/16W MF-LF 402 OUT 8D7 9D7 53A6 53D7 65D1 59B1 84B6 tt VCCSENSE AF7 OUT 59A1 84B6 h AB15 VCC_65 AB17 VCC_66 AB18 VCC_67 YONAH CPU BGA (4 OF 4) LAYOUT NOTE: CPU_VCCSENSE_P/CPU_VCCSENSE_N USE ZO=27.4 OHM DIFFERNTIAL TRACE ROUTING LAYOUT NOTE: PROVIDE A TEST POINT (WITH NO STUB) TO CONNECT A DIFFERENCTIAL PROBE BETWEEN VCCSENSE AND VSSSENSE AT THE LOCATION WHERE THE TWO 54.9 OHM RESISTORS TERMINATE THE 55 OHM TRANSMISSION LINE LAYOUT NOTE: VCCSENSE AND VSSSENSE LINES SHOULD BE OF EQUAL LENGTH P6 P21 VSS_84 P24 VSS_85 R2 VSS_86 R5 VSS_87 R22 VSS_88 R25 VSS_89 T1 B6 VSS_9 B8 VSS_10 B11 VSS_11 B13 VSS_12 B16 VSS_13 B19 VSS_14 VSS_90 T4 VSS_91 T23 VSS_92 T26 B21 VSS_15 B24 VSS_16 C5 VSS_17 C8 VSS_18 C11 VSS_19 VSS_96 U24 VSS_97 V2 VSS_98 V5 VSS_99 V22 VSS_100 V25 C14 VSS_20 C16 VSS_21 C19 VSS_22 VSS_101 W1 VSS_102 W4 VSS_103 W23 C2 VSS_23 C22 VSS_24 C25 VSS_25 D1 VSS_26 D4 VSS_27 VSS_104 W26 VSS_105 Y3 VSS_106 Y6 D8 VSS_28 D11 VSS_29 D13 VSS_30 VSS_109 AA2 VSS_110 AA5 VSS_111 AA8 D16 VSS_31 D19 VSS_32 D23 VSS_33 VSS_112 AA11 VSS_113 AA14 VSS_114 AA16 D26 VSS_34 E3 VSS_35 E6 VSS_36 VSS_115 AA19 VSS_116 AA22 VSS_117 AA25 E8 VSS_37 E11 VSS_38 E14 VSS_39 E16 VSS_40 E19 VSS_41 VSS_118 AB1 VSS_119 AB4 E21 VSS_42 E24 VSS_43 F5 VSS_44 VSS_123 AB16 VSS_124 AB19 VSS_125 AB23 F8 VSS_45 F11 VSS_46 F13 VSS_47 F16 VSS_48 F19 VSS_49 VSS_126 AB26 VSS_127 AC3 VSS_128 AC6 F2 VSS_50 F22 VSS_51 F25 VSS_52 VSS_131 AC14 VSS_132 AC16 VSS_133 AC19 G4 VSS_53 G1 VSS_54 G23 VSS_55 VSS_134 AC21 VSS_135 AC24 VSS_136 AD2 G26 VSS_56 H3 VSS_57 H6 VSS_58 VSS_137 AD5 VSS_138 AD8 VSS_139 AD11 H21 VSS_59 H24 VSS_60 J2 VSS_61 J5 VSS_62 J22 VSS_63 VSS_140 AD13 VSS_141 AD16 J25 VSS_64 K1 VSS_65 K4 VSS_66 VSS_145 AE1 VSS_146 AE4 VSS_147 AE8 K23 VSS_67 K26 VSS_68 L3 VSS_69 VSS_148 AE11 VSS_149 AE14 VSS_150 AE16 L6 VSS_70 L21 VSS_71 L24 VSS_72 M2 VSS_73 M5 VSS_74 VSS_151 AE19 VSS_152 AE23 M22 VSS_75 M25 VSS_76 N1 VSS_77 VSS_156 AF8 VSS_157 AF11 VSS_158 AF13 N4 VSS_78 N23 VSS_79 N26 VSS_80 P3 VSS_81 VSS_159 AF16 VSS_160 AF19 VSS_161 AF21 /x / VCC_88 AE13 VCC_89 AE15 VCC_90 AE17 su D9 VCC_26 D10 VCC_27 D12 VCC_28 D14 VCC_29 VCC_85 AE9 VCC_86 AE10 VCC_87 AE12 om p C15 VCC_23 C17 VCC_24 C18 VCC_25 VCC_82 AD15 VCC_83 AD17 VCC_84 AD18 yc C9 VCC_19 C10 VCC_20 C12 VCC_21 C13 VCC_22 B BGA (3 OF 4) A17 VCC_7 A18 VCC_8 A20 VCC_9 B17 VCC_16 B18 VCC_17 B20 VCC_18 C YONAH CPU /m D A12 VCC_4 A13 VCC_5 A15 VCC_6 U0700 VCC_68 AB20 VCC_69 AB7 VCC_70 AC7 p: / A7 VCC_1 A9 VCC_2 A10 VCC_3 A14 VSS_4 A16 VSS_5 A19 VSS_6 A23 VSS_7 A26 VSS_8 8B5 9D7 53A6 53D7 65D1 (CPU CORE POWER) U0700 VSS_82 VSS_83 D VSS_93 U3 VSS_94 U6 VSS_95 U21 VSS_107 Y21 VSS_108 Y24 C VSS_120 AB8 VSS_121 AB11 VSS_122 AB13 VSS_129 AC8 VSS_130 AC11 VSS_142 AD19 VSS_143 AD22 VSS_144 AD25 B VSS_153 AE26 VSS_154 AF3 VSS_155 AF6 VSS_162 AF24 CPU OF 2-PWR/GND A SYNC_MASTER=(MASTER) SYNC_DATE=(MASTER) NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE APPLE COMPUTER INC DRAWING NUMBER D SCALE SHT NONE REV 051-7150 A.0.0 OF 84 A D D CPU VCORE HF AND BULK DECOUPLING 65D1 53D7 53A6 8D7 8B5 =PPVCORE_S0_CPU 4x 330uF 20x 22uF 0805 C0900 C0901 C0902 C0903 1 C0904 C0905 C0906 C0907 C0908 22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF 20% 6.3V CERM 805 20% 6.3V CERM 805 20% 6.3V CERM 805 20% 6.3V CERM 805 20% 6.3V CERM 805 20% 6.3V CERM 805 20% 6.3V CERM 805 20% 6.3V CERM 805 20% 6.3V CERM 805 20% 6.3V CERM 805 2 2 2 2 CPU VCORE VID Connections C0909 22UF Resistors to allow for override of CPU VID Will probably be removed before production RP0990 C0911 C0914 C0915 C0916 =PP1V5_S0_CPU C0918 C0919 22UF 22UF 22UF 22UF 20% 6.3V CERM 805 20% 6.3V CERM 805 20% 6.3V CERM 805 20% 6.3V CERM 805 20% 6.3V CERM 805 2 CRITICAL C0950 20% 20% C0954 20% POLY D2T 2 2 84B6 8B7 84B6 8B7 84B6 8B7 2.5V POLY D2T CPU_VID CPU_VID CPU_VID CPU_VID IMVP6_VID IMVP6_VID IMVP6_VID IMVP6_VID 59C7 59C7 59C7 59C7 1/16W SM-LF RP0991 C 5% 84B6 8B7 84B6 8B7 84B6 8B7 CPU_VID CPU_VID CPU_VID NC IMVP6_VID IMVP6_VID IMVP6_VID 59C7 59C7 59C7 NC 1/16W SM-LF yc 330UF 2.5V POLY D2T CRITICAL C0953 330UF 2.5V POLY D2T CRITICAL C0952 330UF 2.5V C0981 0.01UF 20% 16V CERM 402 /m 10uF 20% 6.3V X5R 603 22UF 20% 6.3V CERM 805 1x 10uF, 1x 0.01uF C0980 C0917 22UF 20% 6.3V CERM 805 VCCA (CPU AVdd) Decoupling 65C6 8B7 22UF 20% 6.3V CERM 805 20% C C0913 22UF 330UF C0912 20% 6.3V CERM 805 CRITICAL 1 22UF 20% 6.3V CERM 805 /x / 22UF su C0910 om p 5% 84B6 8B7 B p: / B =PP1V05_S0_CPU tt VCCP (CPU I/O) Decoupling 1x 470uF, 6x 0.1uF 0402 C0935 1 470uF 20% 2.5V TANT D2T CRITICAL C0936 C0937 0.1UF 0.1UF 20% 10V CERM 402 20% 10V CERM 402 C0938 C0939 C0940 0.1UF 0.1UF 0.1UF 20% 10V CERM 402 20% 10V CERM 402 20% 10V CERM 402 h 65D6 11C5 11B3 8C7 7D5 7B6 7B5 2 C0941 0.1UF 20% 10V CERM 402 NOTE: This cap is shared between CPU and NB CPU Decoupling & VID A SYNC_MASTER=(MASTER) SYNC_DATE=(MASTER) NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE APPLE COMPUTER INC DRAWING NUMBER D SCALE SHT NONE REV 051-7150 A.0.0 OF 84 A D /x / D su CPU ZONE THERMAL SENSOR 65B3 =PP3V3_S0_THRM_SNR C1002 LAYOUT NOTE: LAYOUT NOTE: ADD GND GUARD TRACE ROUTE CPU_THERMD_P AND FOR CPU_THERMD_P AND CPU_THERMD_N ON SAME CPU_THERMD_N LAYER 0.1UF 10% 16V X5R 402 R10061 om p C 10K 5% 1/16W MF-LF 402 10 MIL TRACE 10 MIL SPACING C R1005 10K 5% 1/16W MF-LF 402 VDD ALERT*/ THRM_ALERT_L THM2* R1001 7C6 CPU_THERMD_P 499 1% 1/16W MF-LF 402 (TO CPU INTERNAL THERMAL DIODE) (TC0D) C1001 7C6 CPU_THERMD_N 499 2 10% 50V CERM 402 TMP401 MSOP THM* THRM_ALERT SCLK SDATA 27D1 SMB_THRM_CLK IO 27D1 SMB_THRM_DATA IO GND PLACE U1001 NEAR THE U1200 B h tt p: / B /m 1% 1/16W MF-LF 402 U1001 CRITICAL 0.001UF R1002 IN D+ D- THRM_CPU_DX_P THRM_CPU_DX_N yc OUT CPU MISC1-TEMP SENSOR A SYNC_MASTER=(MASTER) SYNC_DATE=(MASTER) NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE APPLE COMPUTER INC DRAWING NUMBER D SCALE SHT NONE REV 051-7150 A.0.0 OF 10 84 A 72B6 IO 72B6 IO 72B6 IO 72B6 IO 72B6 IO 72B6 IO 72B6 IO 72A6 IO 72A6 IO 72A6 IO 72A6 IO 72A6 IO 72A6 IO 72A6 IO 72A6 IO 72A6 IO 72A6 C IO 72A6 IO 72A6 IO 72A6 IO 72A6 IO 72A6 IO 72A6 IO 72A6 IO 72A6 IO 72B3 IO 1 40.2 1% 1/16W MF-LF 402 R8712 IO 72B3 IO 72B3 IO 72B3 IO 72B3 IO 72B3 IO 1% 1/16W MF-LF 402 IO 72B3 IO 72B3 IO 72B3 IO 72A3 IO 72A3 IO 72A3 IO 72A3 IO 72A3 IO 72A3 IO 72A3 IO 72A3 IO 72A3 IO 72A3 IO 72A3 IO 72A3 IO 72A3 IO 72A3 IO 72A3 IO 72A3 IO 72A3 IO 72A3 IO 40.2 IO 72B3 72B3 B IO 72A6 72B3 =PP1V8R2V0_S0_FB_GPU IO 72A6 72A3 IO 72A3 IO GPU_MVREFD0 GPU_MVREFS0 C8711 100 1% 1/16W MF-LF 402 100 0.1uF 10% 16V X5R 402 R8713 2 G30 F31 M27 M29 L28 L27 J27 H29 G29 G27 M26 L26 M25 L25 J25 G28 H27 H26 F26 G26 H25 H24 H23 H22 J23 J22 E23 D22 D23 E22 E20 F20 D19 D18 B19 B18 C17 B17 C14 B14 C13 B13 D17 E18 E17 F17 E15 E14 F14 D13 H18 H17 G18 G17 G15 G14 H14 J14 C31 C30 A27 C8713 A28 0.1uF 1% 1/16W MF-LF 402 G31 10% 16V X5R 402 72B6 DQMA_0* 72B6 DQMA_1* 72B6 DQMA_2* 72B6 DQMA_3* 72B3 DQMA_4* 72B3 DQMA_5* 72B3 DQMA_6* 72B3 DQMA_7* QSA_0 QSA_1 QSA_2 QSA_3 QSA_4 QSA_5 QSA_6 QSA_7 QSA_0* QSA_1* QSA_2* QSA_3* QSA_4* QSA_5* QSA_6* QSA_7* CLKA0 CLKA0* CSA0_0* CSA0_1* E24 72B8 72B5 E26 D27 F25 C26 B26 72B8 72B5 72B8 72B5 72B8 72B5 72B8 72B5 72B8 72B5 B27 72B8 72B5 72B8 72B5 E27 71C1 E29 72A8 72A5 B25 72A8 72A5 C25 72A8 72A5 D29 FB_A_DQM_L FB_A_DQM_L FB_A_DQM_L FB_A_DQM_L FB_A_DQM_L FB_A_DQM_L FB_A_DQM_L FB_A_DQM_L H31 J29 J26 G23 E21 B15 D14 J17 K25 F23 D20 B16 D16 H15 K31 72A8 K28 72A8 K26 72A8 G24 72A8 D21 72A5 C16 72A5 D15 72A5 J15 72A5 D31 72B8 E31 72B8 72B8 FB_A_WDQS FB_A_WDQS FB_A_WDQS FB_A_WDQS FB_A_WDQS FB_A_WDQS FB_A_WDQS FB_A_WDQS FB_A_CLK_P FB_A_CLK_N FB_A_CS_L IO 73A6 IO 73A6 IO OUT OUT OUT OUT OUT IO 73B6 IO OUT 73B6 IO OUT 73B6 IO 73B6 IO OUT OUT 73B6 IO IO 73B6 IO IO 73B6 IO IO 73B6 IO IO 73A6 IO IO 73A6 IO 73A6 IO IO IO IO IN IN IN IN IN IN IN IN OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT CASA0* C29 72A8 FB_A_CAS_L OUT WEA0* B31 72A8 FB_A_WE_L OUT CKEA1 CASA1* WEA1* B23 C23 72B5 FB_A_CS_L ODTA1 OUT OUT 70A8 70A5 69B8 65B6 70B8 =PP1V8R2V0_S0_FB_GPU OUT NC R8720 1 40.2 72B5 FB_A_CKE B24 72A5 FB_A_RAS_L B22 72A5 FB_A_CAS_L OUT B21 72A5 FB_A_WE_L OUT TP_FB_A_ODT OUT OUT OUT 1% 1/16W MF-LF 402 73A6 IO 73A6 IO 73A6 IO 73A6 IO 73A6 IO 73A6 IO 73A6 IO 73A6 IO 73A6 IO 73A3 IO 73A3 OUT C22 D24 IO 73B6 OUT 72B5 73B6 OUT OUT C19 IO IO FB_A_RAS_L FB_A_CLK_P FB_A_CLK_N 73A6 IO FB_A_CKE 72B5 IO 73B6 72A8 B20 IO 73A6 73B6 72B8 CLKA1 CLKA1* 73A6 OUT OUT B28 TP_FB_A_ODT IO OUT B30 F29 IO 73A6 OUT NC ODTA0 73A6 73A6 FB_A_RDQS 72A8 FB_A_RDQS 72A8 FB_A_RDQS 72A8 FB_A_RDQS 72A5 FB_A_RDQS 72A5 FB_A_RDQS 72A5 FB_A_RDQS 72A5 FB_A_RDQS K29 C28 OUT 72A8 J31 B29 OUT CKEA0 RASA1* (1.8V/ VDDRH0 2.0V) VSSRH0 D25 72B8 72B5 72B8 72B5 D28 FB_A_MA FB_A_MA FB_A_MA FB_A_MA FB_A_MA FB_A_MA FB_A_MA FB_A_MA FB_A_MA FB_A_MA FB_A_MA FB_A_MA TP_FB_A_MA12 FB_A_BA FB_A_BA FB_A_BA RASA0* CSA1_0* CSA1_1* MVREFD_0 MVREFS_0 F28 R8722 2 1% 1/16W MF-LF 402 IO 73A3 IO 73A3 IO 73A3 IO 73A3 IO 73A3 IO 73A3 IO 73A3 IO 73A3 IO 73A3 IO 73B3 IO 73B3 IO 73B3 IO 73B3 IO 73B3 IO 73B3 IO 73B3 IO 73B3 IO 73B3 IO 73B3 IO 73B3 IO 73B3 IO 73A3 IO 73A3 IO 73A3 IO 73A3 IO 73A3 IO 73A3 IO 73A3 IO 73A3 IO R8721 1 C8721 100 100 0.1uF 10% 16V X5R 402 R8723 2 PP1V8R2V0_S0_GPU_VDDRH1 C8723 L8715 =PP1V8R2V0_S0_FB_GPU 10% 16V X5R 402 GPU_TEST_MCLK GPU_TEST_YCLK GPU_MEMTEST 70B8 70B5 70A8 69B8 65B6 FERR-220-OHM =PP1V8R2V0_S0_FB_GPU PP1V8R2V0_S0_GPU_VDDRH0 0402 XW8715 SM A 5% 1/16W MF-LF 402 MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=1.8V 0402 C8715 C8716 C8725 1 C8726 1uF 1uF 1uF 1uF 10% 6.3V CERM 402 10% 6.3V CERM 402 10% 6.3V CERM 402 10% 6.3V CERM 402 XW8725 SM GND_GPU_VSSRH0 MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=0V C12 B11 C11 C8 B7 C7 B6 F12 D12 E11 F11 F9 D8 D7 F7 G12 G11 H12 H11 H9 E7 F8 G8 G6 G7 H8 J8 K8 L8 K9 L9 K5 L4 K4 L5 N5 N6 P4 R4 P2 R2 T3 T2 W3 W2 Y3 Y2 T4 R5 T5 T6 V5 W5 W6 Y4 R8 T8 R7 T7 V7 W7 W8 W9 B3 C3 F1 AA5 AA2 AA7 DQB_0 DQB_1 DQB_2 DQB_3 DQB_4 DQB_5 DQB_6 DQB_7 DQB_8 DQB_9 DQB_10 DQB_11 DQB_12 DQB_13 DQB_14 DQB_15 DQB_16 DQB_17 DQB_18 DQB_19 DQB_20 DQB_21 DQB_22 DQB_23 DQB_24 DQB_25 DQB_26 DQB_27 DQB_28 DQB_29 DQB_30 DQB_31 DQB_32 DQB_33 DQB_34 DQB_35 DQB_36 DQB_37 DQB_38 DQB_39 DQB_40 DQB_41 DQB_42 DQB_43 DQB_44 DQB_45 DQB_46 DQB_47 DQB_48 DQB_49 DQB_50 DQB_51 DQB_52 DQB_53 DQB_54 DQB_55 DQB_56 DQB_57 DQB_58 DQB_59 DQB_60 DQB_61 DQB_62 DQB_63 MAB_0 MAB_1 MAB_2 MAB_3 MAB_4 MAB_5 MAB_6 MAB_7 MAB_8 MAB_9 MAB_10 MAB_11 MAB_12 MAB_13 MAB_14 MAB_15 G4 73B8 73B5 E6 73B8 73B5 E4 73B8 73B5 73B6 DQMB_0* 73B6 DQMB_1* 73B6 DQMB_2* 73B6 DQMB_3* 73B3 DQMB_4* 73B3 DQMB_5* 73B3 DQMB_6* 73B3 DQMB_7* B8 QSB_0 QSB_1 QSB_2 QSB_3 QSB_4 QSB_5 QSB_6 QSB_7 B9 MVREFD_1 MVREFS_1 (1.8V/ VDDRH1 2.0V) VSSRH1 TEST_MCLK TEST_YCLK MEMTEST FB_B_MA FB_B_MA FB_B_MA 73B8 73B5 FB_B_MA 73B8 73B5 FB_B_MA 73B8 73B5 FB_B_MA 73B8 73B5 FB_B_MA 73B8 73B5 FB_B_MA 73B8 73B5 FB_B_MA 73B8 73B5 FB_B_MA 73B8 73B5 FB_B_MA 73B8 73B5 FB_B_MA 71C1 TP_FB_B_MA12 73A8 73A5 FB_B_BA 73A8 73A5 FB_B_BA 73A8 73A5 FB_B_BA H4 J5 G5 F4 H6 G3 G2 D4 F2 F5 D5 H2 H3 D9 G9 K7 M5 V2 W4 T9 4.7K 5% 1/16W MF-LF 402 OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT V8 FB_B_RDQS 73A8 FB_B_RDQS 73A8 FB_B_RDQS 73A8 FB_B_RDQS 73A5 FB_B_RDQS 73A5 FB_B_RDQS 73A5 FB_B_RDQS 73A5 FB_B_RDQS QSB_0* QSB_1* QSB_2* QSB_3* QSB_4* QSB_5* QSB_6* QSB_7* B10 73A8 V9 FB_B_WDQS 73A8 FB_B_WDQS 73A8 FB_B_WDQS 73A8 FB_B_WDQS 73A5 FB_B_WDQS 73A5 FB_B_WDQS 73A5 FB_B_WDQS 73A5 FB_B_WDQS CLKB0 CLKB0* B4 73B8 B5 FB_B_CLK_P 73B8 FB_B_CLK_N CSB0_0* CSB0_1* D2 73B8 FB_B_CS_L D10 H10 K6 N4 U2 U4 E10 G10 J7 M4 U3 V4 IO IO IO IO IO IO IO IO OUT OUT OUT OUT OUT OUT OUT C OUT IN IN IN IN IN IN IN IN OUT OUT OUT NC E3 CKEB0 C2 73B8 FB_B_CKE OUT RASB0* E2 73A8 FB_B_RAS_L OUT CASB0* D3 73A8 FB_B_CAS_L OUT WEB0* B2 73A8 FB_B_WE_L OUT ODTB0 D6 TP_FB_B_ODT OUT CLKB1 CLKB1* N2 P3 FB_B_CLK_P 73B5 FB_B_CLK_N CSB1_0* CSB1_1* K2 73B5 FB_B_CS_L 73B5 OUT OUT B OUT NC K3 CKEB1 L3 73B5 FB_B_CKE RASB1* J2 73A5 FB_B_RAS_L CASB1* L2 73A5 FB_B_CAS_L OUT WEB1* M2 73A5 FB_B_WE_L OUT ODTB1 J4 TP_FB_B_ODT OUT DRAM_RST D OUT 73A8 AA3 73A8 73A5 72A8 72A5 OUT FB_DRAM_RST OUT OUT R8733 4.7K 2 R8730 OUT FB_B_DQM_L FB_B_DQM_L FB_B_DQM_L FB_B_DQM_L FB_B_DQM_L FB_B_DQM_L FB_B_DQM_L FB_B_DQM_L 4.7K L8725 MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=1.8V FERR-220-OHM B12 E1 0.1uF 1% 1/16W MF-LF 402 R8731 70B8 70A5 65B6 69B8 70B5 IO 73A3 40.2 FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ GPU_MVREFD1 GPU_MVREFS1 1% 1/16W MF-LF 402 h R8711 H30 D26 /x / IO L30 MAA_0 MAA_1 MAA_2 MAA_3 MAA_4 MAA_5 MAA_6 MAA_7 MAA_8 MAA_9 MAA_10 MAA_11 MAA_12 MAA_13 MAA_14 MAA_15 su 72B6 L31 DQA_0 DQA_1 DQA_2 DQA_3 DQA_4 DQA_5 DQA_6 DQA_7 DQA_8 DQA_9 DQA_10 DQA_11 DQA_12 DQA_13 DQA_14 DQA_15 DQA_16 DQA_17 DQA_18 DQA_19 DQA_20 DQA_21 DQA_22 DQA_23 DQA_24 DQA_25 DQA_26 DQA_27 DQA_28 DQA_29 DQA_30 DQA_31 DQA_32 DQA_33 DQA_34 DQA_35 DQA_36 DQA_37 DQA_38 DQA_39 DQA_40 DQA_41 DQA_42 DQA_43 DQA_44 DQA_45 DQA_46 DQA_47 DQA_48 DQA_49 DQA_50 DQA_51 DQA_52 DQA_53 DQA_54 DQA_55 DQA_56 DQA_57 DQA_58 DQA_59 DQA_60 DQA_61 DQA_62 DQA_63 om p IO M30 yc IO 72B6 M31 /m 72B6 FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ p: / IO 72B8 72B5 72B8 72B5 tt IO 72B6 BGA (4 OF 7) MEMORY INTERFACE A 72B6 M56P BGA (3 OF 7) READ STROBE D R8710 OMIT U8400 WRITE STROBE BOM options provided by this page: (NONE) 70B5 69B8 65B6 70A8 70A5 OMIT U8400 M56P Signal aliases required by this page: (NONE) MEMORY INTERFACE B Power aliases required by this page: - =PP1V8R2V0_S0_FB_GPU READ STROBE WRITE STROBE Page Notes 5% 1/16W MF-LF 402 R8732 243 1% 1/16W MF-LF 402 ATI M56 Frame Buffer I/F GND_GPU_VSSRH1 SYNC_MASTER=(MASTER) MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=0V SYNC_DATE=(MASTER) NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE APPLE COMPUTER INC DRAWING NUMBER D SCALE SHT NONE REV 051-7150 A.0.0 OF 70 84 A ROMCFGID[3 0] 65A3 0000 0010 0100 0110 =PP3V3_D3C_GPU_GPIOS NO STUFF R8800 D Misc 10K 10K 10K 10K 5% 1/16W MF-LF 402 5% 1/16W MF-LF 402 5% 1/16W MF-LF 402 5% 1/16W MF-LF 402 5% 1/16W MF-LF 402 GPU_GPIO_2 74D3 GPU_GPIO_3 74D3 GPU_GPIO_4 74D3 GPU_GPIO_5 74D3 GPU_GPIO_6 74D3 GPU_GPIO_7 74D3 GPU_GPIO_8 74C3 GPU_GPIO_9 74C3 GPU_GPIO_10 74C3 GPU_GPIO_11 74C3 GPU_GPIO_12 74C3 GPU_GPIO_13 74C3 GPU_GPIO_14 TX_DEEMPH_EN TESTIN[2] Reserved TESTIN[3] Reserved TESTIN[4] DEBUG_ACCESS TESTIN[5] Reserved TESTIN[6] Reserved R8803 GPU_GPIO_15 74C3 GPU_GPIO_16 10K 10K 5% 1/16W MF-LF 402 5% 1/16W MF-LF 402 5% 1/16W MF-LF 402 5% 1/16W MF-LF 402 IPD IPD ENA_BL TESTIN[7] ROMSO TESTWR 74D5 GPU_GPIO_21 74D5 GPU_GPIO_22 74D5 GPU_GPIO_23 74D5 GPU_GPIO_24 74D5 GPU_GPIO_25 GPU_BLON ROMSCK 79A4 MAKE_BASE=TRUE ROMIDCFG[3] TESTOUT[8] TP_GPU_GPIO_10 IPD TESTOUT[9] ROMIDCFG[0] IPD TESTOUT[10] ROMIDCFG[1] IPD TESTOUT[11] ROMIDCFG[2] Required for debug access MAKE_BASE=TRUE Required for debug access Required for debug access 74D5 GPU_GPIO_26 GPU_GPIO_27 NC_GPU_GPIO_14 NO_TEST=TRUE TESTIN[9] PWRCNTL GPU_VCORE_LOW 68B4 SS_IN GPU_CLK27MSS_IN 34B2 34B4 Thm Mon Int NC_GPU_GPIO_17 NO_TEST=TRUE NC_GPU_GPIO_18 MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE NC_GPU_GPIO_19 NC_GPU_GPIO_20 NC_GPU_GPIO_21 NC_GPU_GPIO_22 NC_GPU_GPIO_23 MAKE_BASE=TRUE NO_TEST=TRUE GPU_MEM_256M NC_GPU_GPIO_25 MAKE_BASE=TRUE NO_TEST=TRUE NC_GPU_GPIO_26 MAKE_BASE=TRUE NO_TEST=TRUE GPU_MEMID MAKE_BASE=TRUE GPU_GPIO_28 74C5 GPU_GPIO_29 74C5 GPU_GPIO_30 74C5 GPU_GPIO_31 74C5 GPU_GPIO_32 74C5 GPU_GPIO_33 74C5 GPU_GPIO_34 R8827 10K 5% 1/16W MF-LF 402 Renamed signals NC_GPU_GPIO_28 MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE GPU_CLK27M GPU_XTALIN NC_GPU_XTALOUT MAKE_BASE=TRUE 74A5 NC_GPU_GPIO_29 NC_GPU_GPIO_30 NC_GPU_GPIO_31 NC_GPU_GPIO_32 NC_GPU_GPIO_33 NC_GPU_GPIO_34 MAKE_BASE=TRUE 74A5 TP_ATI_ROMCS_L 74A3 TP_FB_A_MA12 70D5 TP_FB_B_MA12 70D1 GPU_GENERICA 74C3 GPU_GENERICB 74C3 GPU_GENERICC 74C3 GPU_VGA_R 75C3 GPU_VGA_G 75C3 GPU_VGA_B 75C3 GPU_VGA_HSYNC 75B3 GPU_VGA_VSYNC 75B3 GPU_TV_Y 75B3 GPU_TV_C 75B3 GPU_TV_COMP 75B3 LVDS_U_DATA_P 75B3 LVDS_U_DATA_N 75B3 LVDS_L_DATA_P 75A3 LVDS_L_DATA_N 75A3 ATI_DVPCLK 74C3 ATI_DVPCNTL 74B3 74C3 ATI_DVPDATA 74B3 NO_TEST=TRUE NC_FB_A_MA12 MAKE_BASE=TRUE NO_TEST=TRUE NC_FB_B_MA12 MAKE_BASE=TRUE NO_TEST=TRUE NC_GPU_GENERICA MAKE_BASE=TRUE NO_TEST=TRUE NC_GPU_GENERICB MAKE_BASE=TRUE NO_TEST=TRUE NC_GPU_GENERICC MAKE_BASE=TRUE NO_TEST=TRUE NC_GPU_VGA_R MAKE_BASE=TRUE C NO_TEST=TRUE NC_GPU_VGA_G MAKE_BASE=TRUE NO_TEST=TRUE NC_GPU_VGA_B MAKE_BASE=TRUE NO_TEST=TRUE TP_GPU_VGA_HSYNC MAKE_BASE=TRUE TP_GPU_VGA_VSYNC MAKE_BASE=TRUE NC_GPU_TV_Y MAKE_BASE=TRUE NO_TEST=TRUE NC_GPU_TV_C MAKE_BASE=TRUE NO_TEST=TRUE NC_GPU_TV_COMP MAKE_BASE=TRUE NO_TEST=TRUE NC_LVDS_U_DATAP MAKE_BASE=TRUE NO_TEST=TRUE NC_LVDS_U_DATAN MAKE_BASE=TRUE NO_TEST=TRUE NC_LVDS_L_DATAP MAKE_BASE=TRUE NO_TEST=TRUE NC_LVDS_L_DATAN MAKE_BASE=TRUE NO_TEST=TRUE NC_ATI_DVPCLK MAKE_BASE=TRUE NO_TEST=TRUE NC_ATI_DVPCNTL MAKE_BASE=TRUE NO_TEST=TRUE NC_ATI_DVPDATA MAKE_BASE=TRUE NO_TEST=TRUE B Required for debug access TP_ATI_DVPDATA ATI_DVPDATA 74A3 74B3 MAKE_BASE=TRUE Also required: GPIO10 - GPIO13 65A3 =PP3V3_D3C_GPU R8890 h MAKE_BASE=TRUE NO_TEST=TRUE GPU_XTALOUT NO_TEST=TRUE NC_ATI_ROMCS_L p: / 74D5 5% 1/16W MF-LF 402 tt B 10K 5% 1/16W MF-LF 402 Required for debug access TESTIN[8] MAKE_BASE=TRUE 74D5 10K GPU_MEM_NOT_SAM R8811 yc 74D5 GPU_GPIO_20 NO STUFF /m GPU_GPIO_19 2 Unused signals MAKE_BASE=TRUE 74D5 2 R8813 MAKE_BASE=TRUE Reserved ROMSI GPU_GPIO_17 GPU_GPIO_18 GPU_MEM_64M 34B4 34B2 VDD_VCL MAKE_BASE=TRUE 74D5 R8808 10K MAKE_BASE=TRUE 74C3 R8805 10K MAKE_BASE=TRUE 74C3 NO STUFF /x / GPU_GPIO_1 74D3 TX_PWRS_ENb TESTIN[1] R8801 NO STUFF su 74D3 TESTIN[0] IPD D R8824 10K 5% 1/16W MF-LF 402 Straps IPD GPU_MEM_256M R8812 om p C GPU_GPIO_0 GPU_MEM_256M R8809 10K 74D3 NO STUFF R8806 5% 1/16W MF-LF 402 GPU_DEEPMH_EN TestBus NO STUFF R8804 128MB 256MB 64MB Reserved 10K Serial ROM NO STUFF R8802 = = = = 75A3 75A3 R8891 4.7K 4.7K 5% 1/16W MF-LF 402 5% 1/16W MF-LF 402 GPU_DDC_B_CLK GPU_DDC_B_DATA GPU Straps A SYNC_MASTER=M59_MG SYNC_DATE=07/25/2006 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE APPLE COMPUTER INC DRAWING NUMBER D SCALE SHT NONE REV 051-7150 A.0.0 OF 71 84 A C8902 C8903 C8904 0.1uF 0.1uF 0.1uF 10% 16V X5R 402 10% 16V X5R 402 10% 16V X5R 402 10% 16V X5R 402 2 L8910 PP1V8_S0_FB_A0_VDDA0 MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=1.8V 0402 L8915 FERR-220-OHM VDD5 V2 VDD6 VDD7 PP1V8_S0_FB_A0_VDDA1 MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=1.8V 0402 C8910 C8915 0.1uF 0.1uF 10% 16V X5R 402 10% 16V X5R 402 U8900.J1 22UF 20% 6.3V CERM 805 2 C8921 C8922 1 C8924 C8925 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 10% 16V X5R 402 10% 16V X5R 402 10% 16V X5R 402 10% 16V X5R 402 10% 16V X5R 402 10% 16V X5R 402 2 2 R8932 2.37K 2.37K 1% 1/16W MF-LF 402 1% 1/16W MF-LF 402 FERR-220-OHM B9 VDDQ3 VDDQ4 VSSQ3 VSSQ4 B12 VDDQ5 VSSQ5 D4 VDDQ6 VDDQ7 VSSQ6 VSSQ7 D9 E9 VDDQ8 VSSQ8 G2 VSSQ9 VSSQ10 G11 J9 VDDQ11 VSSQ11 L11 VSSQ12 VSSQ13 P1 N12 VDDQ14 VDDQ15 VSSQ14 VSSQ15 P9 R1 VDDQ16 VSSQ16 T1 FB_A0_VREF1 C R8933 5.49K 1 1% 1/16W MF-LF 402 C8931 IN 0.1uF 0.1uF 10% 16V X5R 402 10% 16V X5R 402 2 20% 6.3V CERM 805 IN 72B5 70D5 IN 72B5 70D5 IN 72B5 70D5 IN 72B5 70D5 IN 72B5 70D5 IN 72B5 70D5 IN 72B5 70D5 IN 72B5 70D5 IN 70B5 IN 70B5 IN 70B5 IN 70B5 70B5 IN IN 70B5 IN 70B5 IN 60.4 1% 1/16W MF-LF 402 1% 1/16W MF-LF 402 70C5 70C5 70C5 70C5 OUT OUT OUT OUT 70C5 IN 70C5 IN 70C5 IN 70C5 IN 72A5 70D5 IN 72A5 70D5 72A5 70D5 IN IN 121 FB_A_CKE FB_A_CLK_P FB_A_CLK_N FB_A_CS_L FB_A_WE_L FB_A_CAS_L FB_A_RAS_L C8976 R8982 2 2 VDD6 VDD7 A3 VSS1 VSS2 A10 VSS3 VSS4 G12 VSS5 L12 VSS6 VSS7 V3 VSSA0 J1 VSSA1 J12 VDDQ0 VSSQ0 B1 A12 VDDQ1 VDDQ2 VSSQ1 VSSQ2 B4 VDDQ3 VDDQ4 VSSQ3 VSSQ4 B12 C9 C12 VDDQ5 VSSQ5 D4 E1 VDDQ6 VDDQ7 VSSQ6 VSSQ7 D9 E4 E9 VDDQ8 VSSQ8 G2 D1 D12 VDDQ9 VDDQ10 VSSQ9 VSSQ10 G11 J9 VDDQ11 VSSQ11 L11 N1 VDDQ12 VDDQ13 VSSQ12 VSSQ13 P1 VDDQ14 VDDQ15 VSSQ14 VSSQ15 P9 N12 R1 VDDQ16 VSSQ16 T1 R4 VDDQ17 VDDQ18 VSSQ17 VSSQ18 T4 R9 R12 VDDQ19 VSSQ19 T12 V1 VDDQ20 VDDQ21 VREF1 D B9 J4 VREF0 BOM options provided by this page: (NONE) V10 A1 H1 Signal aliases required by this page: (NONE) L1 VDDA1 H12 Power aliases required by this page: - =PP1V8_S0_FB_VDD - =PP1V8_S0_FB_VDDQ G1 VDDA0 V12 FB_A1_VREF1 FBGA (2 OF 2) VSS0 K1 N9 FB_A1_VREF0 U8950 K12 N4 MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm R8981 Bits can be swapped FB_A_RDQS FB_A_RDQS FB_A_RDQS FB_A_RDQS E3 70D5 DM1 E10 70C5 DM2 DM3 N10 70C5 DQ0 B2 70D7 H2 K3 A6 L4 A7 A8/AP C2 70D7 C3 70D7 DQ4 DQ5 E2 70D7 DQ6 F2 70D7 F3 70D7 DQ7 G3 70D7 H9 CKE 70D7 DQ8 B11 J11 CK CK* 70D7 DQ9 B10 70D7 DQ10 C11 F4 CS* 70D7 DQ11 C10 H4 70D7 DQ12 70D7 DQ13 E11 F9 WE* CAS* H10 RAS* 70D7 DQ14 F11 70D7 DQ15 70C7 DQ16 G10 A9 ZQ MF V4 SEN 70D7 DQ17 L10 RESET 70C7 DQ18 N11 70D7 DQ19 M10 70C7 DQ20 70C7 DQ21 R11 P10 P3 RDQS0 RDQS1 RDQS2 RDQS3 F10 M11 R10 70C7 DQ22 T11 T10 D2 WDQS0 70C7 DQ23 DQ24 D11 WDQS1 DQ25 L3 70C7 P11 DQ26 DQ27 N2 70C7 P2 WDQS2 WDQS3 R2 70C7 BA0 DQ28 G9 DQ29 DQ30 R3 70C7 DQ31 T3 70C7 G4 NC NC DQ3 B3 70D7 L9 D10 FB_A_BA FB_A_BA FB_A_BA A9 DQ1 DQ2 N3 A10 A11 D3 FB_A_WDQS FB_A_WDQS FB_A_WDQS FB_A_WDQS FB_A_DQM_L FB_A_DQM_L FB_A_DQM_L 70C5 FB_A_DQM_L DM0 FBGA A4 A5 BA1 H3 BA2 J2 RFU1 J3 RFU2 5.49K U8900 V9 2 VDDQ20 VDDQ21 (1 OF 2) A4 FB_DRAM_RST C8975 10% 16V X5R 402 V1 A2 A3 J10 100 0.1uF 1% 1/16W MF-LF 402 A1 M4 1% 1/16W MF-LF 402 C8974 10% 16V X5R 402 1% 1/16W MF-LF 402 A0 K11 243 0.1uF T12 K9 K2 R8949 C8973 10% 16V X5R 402 VSSQ19 K10 K4 R8948 U8900.J12 0.1uF VDDQ19 H11 M9 VDD5 V2 C4 10% 16V X5R 402 R12 R8990 CRITICAL OMIT 1% 1/16W MF-LF 402 FB_A_MA FB_A_MA FB_A_MA FB_A_MA FB_A_MA FB_A_MA FB_A_MA FB_A_MA FB_A_MA FB_A_MA FB_A_MA FB_A_MA M12 C1 0.1uF 2.37K R8947 FB_A0_ZQ FB_A0_MF FB_A0_SEN 72A5 70A1 73A8 73A5 IN 10% 16V X5R 402 10% 16V X5R 402 2.37K R8983 FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ M2 70C7 M3 70C7 T2 70C7 IN 72B8 70D5 IN IN 72B8 70D5 IN IN 72B8 70D5 IN IN 72B8 70D5 IN 72B8 70D5 IN IO IO IO IO IO IO IO 72B8 70D5 IN 72B8 70D5 IN 72B8 70D5 IN 72B8 70D5 IN 72B8 70D5 IN 72B8 70D5 IN 72B8 70D5 IN 1% 1/16W MF-LF 402 R8992 121 1% 1/16W MF-LF 402 1% 1/16W MF-LF 402 R8991 1K 5% 1/16W MF-LF 402 2 L2 P4 P12 T9 C C8983 0.1uF 0.1uF 10% 16V X5R 402 10% 16V X5R 402 60.4 1% 1/16W MF-LF 402 121 R8995 60.4 1% 1/16W MF-LF 402 R8996 R8993 C8981 R8994 121 1% 1/16W MF-LF 402 5.49K 121 yc 121 0.1uF 0.1uF R8980 GDDR3 vendor/device identification scheme R8945 10% 16V X5R 402 T9 /m IN 72B5 70D5 R8943 C8965 10% 16V X5R 402 0.1uF P12 p: / IN 72B5 70D5 P4 tt IN 72B5 70D5 C8972 T4 h R8941 5% 1/16W MF-LF 402 A 2 C8971 VSSQ17 VSSQ18 MFHIGH 1K B 1 22UF how these bits are mapped for GPU to support K4J52324QC-BC20 1% 1/16W MF-LF 402 MFHIGH 60.4 1% 1/16W MF-LF 402 M1 VDD3 VDD4 E12 C8970 1% 1/16W MF-LF 402 16MX32-GDDR3-500MHZ 121 1% 1/16W MF-LF 402 MFHIGH 121 1% 1/16W MF-LF 402 F1 =PP1V8_S0_FB_VDDQ within byte-lane, but software must know R8946 121 72B5 70D5 R8944 VDD1 VDD2 F12 Connect to designated pin, then GND C8933 DQA0-7 or DQA8-15 R8942 C8960 U8900.J1 NOTE: U8900 DQ0-7 MUST connect to GPU R8940 VDD0 Page Notes MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm 5.49K 1% 1/16W MF-LF 402 2 MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=1.8V 0402 om p R8931 MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm 10% 16V X5R 402 PP1V8_S0_FB_A1_VDDA1 VDDQ17 VDDQ18 VREF1 0.1uF 10% 16V X5R 402 PP1V8_S0_FB_A1_VDDA0 R9 H12 C8954 0.1uF 0.1uF L2 VDDQ12 VDDQ13 C8953 10% 16V X5R 402 L8965 73D8 73D5 72D8 65B6 VDDQ9 VDDQ10 VREF0 0.1uF MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=1.8V 0402 D12 J4 H1 C8952 10% 16V X5R 402 D1 E4 V12 0.1uF A2 A11 V11 B4 FB_A0_VREF0 J12 VSSQ1 VSSQ2 R4 MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm VSSA1 VDDQ1 VDDQ2 N9 R8930 A12 N1 J1 B1 N4 FERR-220-OHM VSSA0 2 C8951 L8960 VSSQ0 C9 C8926 V10 L1 VDDQ0 C12 C8923 V3 20% 6.3V CERM 805 A1 E12 1 L12 VSS6 VSS7 1 22UF VDDA1 =PP1V8_S0_FB_VDDQ C8920 VSS5 C8950 K12 E1 72D5 65B6 73D8 73D5 IN G12 G1 VDDA0 C4 Connect to designated pin, then GND VSS3 VSS4 K1 C1 U8900.J12 FBGA (2 OF 2) 1% 1/16W MF-LF 402 R8997 121 CRITICAL OMIT 1% 1/16W MF-LF 402 FB_A_MA FB_A_MA FB_A_MA FB_A_MA FB_A_MA FB_A_MA FB_A_MA FB_A_MA FB_A_MA FB_A_MA FB_A_MA FB_A_MA A0 U8950 DM0 E3 70C5 IN A1 FBGA DM1 E10 70C5 IN K10 A2 A3 (1 OF 2) DM2 DM3 N10 70C5 DQ0 B2 70C7 DQ1 DQ2 B3 70C7 DQ3 C3 70C7 DQ4 DQ5 E2 70C7 DQ6 F2 70C7 M9 H2 A4 A5 K3 A6 L4 A7 A8/AP K4 K2 M4 A9 IO IN IO 70B5 IN IO 70B5 IN IO 70B5 IO 70B5 IO 70B5 IN IO 70B5 IN IN IN FB_A_CKE FB_A_CLK_P FB_A_CLK_N FB_A_CS_L FB_A_WE_L FB_A_CAS_L FB_A_RAS_L IO IO IO IO IO IO IO IO 73A5 72A8 70A1 73A8 IN 70C5 70C5 70C5 70C5 OUT DQ7 G3 70C7 CKE 70C7 DQ8 B11 J11 CK CK* 70C7 DQ9 B10 70C7 DQ10 C11 F4 CS* 70C7 DQ11 C10 H4 70B7 DQ12 70B7 DQ13 E11 F9 WE* CAS* H10 RAS* 70B7 DQ14 F11 70B7 DQ15 70B7 DQ16 G10 A9 ZQ MF V4 SEN 70B7 DQ17 L10 RESET 70B7 DQ18 N11 70B7 DQ19 M10 70B7 DQ20 70B7 DQ21 R11 OUT OUT 70B7 DQ22 T11 OUT T10 V9 FB_A_RDQS FB_A_RDQS FB_A_RDQS FB_A_RDQS D3 D10 P10 P3 RDQS0 RDQS1 RDQS2 RDQS3 70C5 IN IO 70C5 IO 70C5 IN IO 70C5 IN 72A8 70D5 IN IO IO IO 72A8 70D5 72A8 70D5 IN IN IN FB_A_WDQS FB_A_WDQS FB_A_WDQS FB_A_WDQS FB_A_BA FB_A_BA FB_A_BA R8998 243 5% 1/16W MF-LF 402 1% 1/16W MF-LF 402 R8999 100 2 NC NC R10 WDQS0 D11 WDQS1 DQ25 L3 70B7 P11 DQ26 DQ27 N2 70B7 P2 WDQS2 WDQS3 R2 70B7 BA0 DQ28 G9 DQ29 DQ30 R3 70B7 DQ31 T3 70B7 BA1 H3 BA2 J2 RFU1 J3 RFU2 IO M11 D2 G4 F10 70B7 DQ23 DQ24 IO IO F3 70C7 H9 A4 FB_DRAM_RST C2 70C7 L9 J10 FB_A1_ZQ FB_A1_MF FB_A1_SEN N3 A10 A11 K11 IO 70B5 FB_A_DQM_L FB_A_DQM_L FB_A_DQM_L 70C5 FB_A_DQM_L K9 H11 K4J52324QC-BC20 D M12 V11 FERR-220-OHM M1 VDD3 VDD4 A10 MFHIGH F1 F12 A3 VSS1 VSS2 16MX32-GDDR3-500MHZ 0.1uF VSS0 MFHIGH 2 C8901 U8900 MFHIGH 20% 6.3V CERM 805 VDD1 VDD2 CRITICAL OMIT =PP1V8_S0_FB_VDD /x / 1 22UF VDD0 K4J52324QC-BC20 C8900 A2 A11 IN K4J52324QC-BC20 73D8 73D5 72D8 65B6 16MX32-GDDR3-500MHZ CRITICAL OMIT =PP1V8_S0_FB_VDD 16MX32-GDDR3-500MHZ 72D5 65B6 73D8 73D5 IN su M2 70B7 M3 70B7 T2 70B7 FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ IN IN IO B IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO GDDR3 Frame Buffer A IO IO SYNC_MASTER=(MASTER) IO IO SYNC_DATE=(MASTER) NOTICE OF PROPRIETARY PROPERTY IO THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING IO IO I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART 5% 1/16W MF-LF 402 SIZE APPLE COMPUTER INC DRAWING NUMBER D SCALE SHT NONE REV 051-7150 A.0.0 OF 72 84 A C9002 C9003 C9004 0.1uF 0.1uF 0.1uF 10% 16V X5R 402 10% 16V X5R 402 10% 16V X5R 402 10% 16V X5R 402 2 L9010 PP1V8_S0_FB_B0_VDDA0 MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=1.8V 0402 L9015 FERR-220-OHM VDD5 V2 VDD6 VDD7 PP1V8_S0_FB_B0_VDDA1 MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=1.8V 0402 C9010 C9015 0.1uF 0.1uF 10% 16V X5R 402 10% 16V X5R 402 U9000.J1 22UF 20% 6.3V CERM 805 2 C9021 C9022 1 C9024 C9025 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 10% 16V X5R 402 10% 16V X5R 402 10% 16V X5R 402 10% 16V X5R 402 10% 16V X5R 402 10% 16V X5R 402 2 2 R9032 2.37K 2.37K 1% 1/16W MF-LF 402 1% 1/16W MF-LF 402 FERR-220-OHM B9 VDDQ3 VDDQ4 VSSQ3 VSSQ4 B12 VDDQ5 VSSQ5 D4 VDDQ6 VDDQ7 VSSQ6 VSSQ7 D9 E9 VDDQ8 VSSQ8 G2 VSSQ9 VSSQ10 G11 J9 VDDQ11 VSSQ11 L11 VSSQ12 VSSQ13 P1 N12 VDDQ14 VDDQ15 VSSQ14 VSSQ15 P9 R1 VDDQ16 VSSQ16 T1 FB_B0_VREF1 C 20% 6.3V CERM 805 2 C9071 R9041 IN IN 73B5 70D1 IN 73B5 70D1 IN 73B5 70D1 IN 73B5 70D1 IN 73B5 70D1 IN IN 73B5 70D1 IN 73B5 70D1 IN 73B5 70D1 IN 70B1 IN 70B1 IN 70B1 IN 70B1 70B1 IN IN 70B1 IN 70B1 IN 2 R9043 121 60.4 1% 1/16W MF-LF 402 1% 1/16W MF-LF 402 70C1 70C1 70C1 70C1 OUT OUT OUT OUT 70C1 IN 70C1 IN 70C1 IN 70C1 IN 73A5 70D1 IN 73A5 70D1 73A5 70D1 IN IN 0.1uF 10% 16V X5R 402 10% 16V X5R 402 FB_B_CKE FB_B_CLK_P FB_B_CLK_N FB_B_CS_L FB_B_WE_L FB_B_CAS_L FB_B_RAS_L C9074 C9075 C9076 0.1uF 10% 16V X5R 402 10% 16V X5R 402 2 V1 VDDQ20 VDDQ21 1% 1/16W MF-LF 402 R9082 2 2 VDD6 VDD7 A3 VSS1 VSS2 A10 VSS3 VSS4 G12 VSS5 L12 VSS6 VSS7 V3 VSSA0 J1 VSSA1 J12 VDDQ0 VSSQ0 B1 A12 VDDQ1 VDDQ2 VSSQ1 VSSQ2 B4 VDDQ3 VDDQ4 VSSQ3 VSSQ4 B12 C9 C12 VDDQ5 VSSQ5 D4 E1 VDDQ6 VDDQ7 VSSQ6 VSSQ7 D9 E4 E9 VDDQ8 VSSQ8 G2 D1 D12 VDDQ9 VDDQ10 VSSQ9 VSSQ10 G11 J9 VDDQ11 VSSQ11 L11 N1 VDDQ12 VDDQ13 VSSQ12 VSSQ13 P1 VDDQ14 VDDQ15 VSSQ14 VSSQ15 P9 N12 R1 VDDQ16 VSSQ16 T1 R4 VDDQ17 VDDQ18 VSSQ17 VSSQ18 T4 R9 R12 VDDQ19 VSSQ19 T12 V1 VDDQ20 VDDQ21 VREF1 D B9 J4 VREF0 BOM options provided by this page: (NONE) V10 A1 H1 Signal aliases required by this page: (NONE) L1 VDDA1 H12 Power aliases required by this page: - =PP1V8_S0_FB_VDD - =PP1V8_S0_FB_VDDQ G1 VDDA0 V12 FB_B1_VREF1 FBGA (2 OF 2) VSS0 K1 N9 FB_B1_VREF0 U9050 K12 N4 MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm R9081 FB_B_RDQS FB_B_RDQS FB_B_RDQS FB_B_RDQS DM0 E3 FBGA DM1 E10 70C1 DM2 DM3 N10 70C1 DQ0 B2 70D3 K3 A6 L4 A7 A8/AP B3 70D3 C2 70D3 C3 70D3 DQ4 DQ5 E2 70D3 DQ6 F2 70D3 F3 70D3 DQ7 G3 70D3 H9 CKE 70C3 DQ8 B11 J11 CK CK* 70D3 DQ9 B10 70C3 DQ10 C11 F4 CS* 70D3 DQ11 C10 H4 70C3 DQ12 70C3 DQ13 E11 F9 WE* CAS* H10 RAS* 70C3 DQ14 F11 70C3 DQ15 70C3 DQ16 G10 A9 ZQ MF V4 SEN 70C3 DQ17 L10 RESET 70C3 DQ18 N11 70C3 DQ19 M10 70C3 DQ20 70C3 DQ21 R11 P10 P3 RDQS0 RDQS1 RDQS2 RDQS3 F10 M11 R10 70C3 DQ22 T11 T10 D2 WDQS0 70C3 DQ23 DQ24 D11 WDQS1 DQ25 L3 70D3 P11 DQ26 DQ27 N2 70D3 P2 WDQS2 WDQS3 R2 70D3 BA0 DQ28 G9 DQ29 DQ30 R3 70D3 DQ31 T3 70D3 G4 NC NC DQ3 N3 L9 D10 FB_B_BA FB_B_BA FB_B_BA A9 DQ1 DQ2 70C1 A10 A11 D3 FB_B_WDQS FB_B_WDQS FB_B_WDQS FB_B_WDQS FB_B_DQM_L FB_B_DQM_L FB_B_DQM_L 70D1 FB_B_DQM_L U9000 (1 OF 2) H2 BA1 H3 BA2 J2 RFU1 J3 RFU2 R9083 FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ M2 70D3 M3 70D3 T2 70D3 IN 73B8 70D1 IN IN 73B8 70D1 IN IN 73B8 70D1 IN IN 73B8 70D1 IN 73B8 70D1 IN IO IO 73B8 70D1 IO IN 73B8 70D1 IN 73B8 70D1 IN IO IO IO IO 73B8 70D1 IN 73B8 70D1 IN 73B8 70D1 IN 73B8 70D1 IN 1% 1/16W MF-LF 402 R9092 121 121 1% 1/16W MF-LF 402 1% 1/16W MF-LF 402 1% 1/16W MF-LF 402 R9091 1K 5% 1/16W MF-LF 402 2 L2 P4 P12 T9 C C9083 0.1uF 0.1uF 10% 16V X5R 402 10% 16V X5R 402 60.4 1% 1/16W MF-LF 402 121 R9095 60.4 1% 1/16W MF-LF 402 R9096 R9093 C9081 R9094 121 5.49K 1% 1/16W MF-LF 402 A2 A3 A4 A5 5.49K A1 V9 0.1uF 1% 1/16W MF-LF 402 A0 A4 FB_DRAM_RST C9073 10% 16V X5R 402 T12 K9 J10 100 U9000.J12 0.1uF VSSQ19 K10 M4 243 VDD5 V2 C4 10% 16V X5R 402 VDDQ19 H11 K11 R9049 M12 C1 0.1uF R12 CRITICAL OMIT 1% 1/16W MF-LF 402 K2 1% 1/16W MF-LF 402 121 K4 R9048 om p 0.1uF M9 10% 16V X5R 402 10% 16V X5R 402 2.37K R9047 FB_B_MA FB_B_MA FB_B_MA FB_B_MA FB_B_MA FB_B_MA FB_B_MA FB_B_MA FB_B_MA FB_B_MA FB_B_MA FB_B_MA 0.1uF 0.1uF 2.37K R9090 FB_B0_ZQ FB_B0_MF FB_B0_SEN 72A5 70A1 73A5 72A8 IN 10% 16V X5R 402 R9080 R9045 C9065 10% 16V X5R 402 0.1uF T9 yc C9072 P12 /m IN 73B5 70D1 A 1 22UF p: / 1% 1/16W MF-LF 402 M1 VDD3 VDD4 E12 C9070 P4 tt 60.4 1% 1/16W MF-LF 402 F1 =PP1V8_S0_FB_VDDQ T4 h B IN VDD1 VDD2 F12 Connect to designated pin, then GND C9033 K4J52324QC-BC20 121 1% 1/16W MF-LF 402 C9060 U9000.J1 R9046 121 5% 1/16W MF-LF 402 73B5 70D1 R9044 1 MFHIGH R9042 C9031 1% 1/16W MF-LF 402 1K 73B5 70D1 1% 1/16W MF-LF 402 121 73B5 70D1 16MX32-GDDR3-500MHZ R9040 1 5.49K 1% 1/16W MF-LF 402 2 VDD0 Page Notes MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm MFHIGH R9033 5.49K MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=1.8V 0402 VSSQ17 VSSQ18 MFHIGH R9031 MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm 10% 16V X5R 402 PP1V8_S0_FB_B1_VDDA1 VDDQ17 VDDQ18 VREF1 0.1uF 10% 16V X5R 402 PP1V8_S0_FB_B1_VDDA0 R9 H12 C9054 0.1uF 0.1uF L2 VDDQ12 VDDQ13 C9053 10% 16V X5R 402 L9065 73D8 72D8 72D5 65B6 VDDQ9 VDDQ10 VREF0 0.1uF MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=1.8V 0402 D12 J4 H1 C9052 10% 16V X5R 402 D1 E4 V12 0.1uF A2 A11 V11 B4 FB_B0_VREF0 J12 VSSQ1 VSSQ2 R4 MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm VSSA1 VDDQ1 VDDQ2 N9 R9030 A12 N1 J1 B1 N4 FERR-220-OHM VSSA0 2 C9051 L9060 VSSQ0 C9 C9026 V10 L1 VDDQ0 C12 C9023 V3 20% 6.3V CERM 805 A1 E12 1 L12 VSS6 VSS7 1 22UF VDDA1 =PP1V8_S0_FB_VDDQ C9020 VSS5 C9050 K12 E1 72D5 65B6 73D5 72D8 IN G12 G1 VDDA0 C4 Connect to designated pin, then GND VSS3 VSS4 K1 C1 U9000.J12 FBGA (2 OF 2) 1% 1/16W MF-LF 402 R9097 121 CRITICAL OMIT 1% 1/16W MF-LF 402 FB_B_MA FB_B_MA FB_B_MA FB_B_MA FB_B_MA FB_B_MA FB_B_MA FB_B_MA FB_B_MA FB_B_MA FB_B_MA FB_B_MA A0 U9050 DM0 E3 70C1 IN A1 FBGA DM1 E10 70C1 IN K10 A2 A3 (1 OF 2) DM2 DM3 N10 70C1 DQ0 B2 70B3 DQ1 DQ2 B3 70B3 DQ3 C3 70B3 DQ4 DQ5 E2 70B3 DQ6 F2 70B3 M9 H2 A4 A5 K3 A6 L4 A7 A8/AP K4 K2 M4 A9 IO IN IO 70B1 IN IO 70B1 IN IO 70B1 IO 70B1 IO 70B1 IN IO 70B1 IN IN IN FB_B_CKE FB_B_CLK_P FB_B_CLK_N FB_B_CS_L FB_B_WE_L FB_B_CAS_L FB_B_RAS_L IO IO IO IO IO IO IO IO 72A8 72A5 70A1 73A8 IN 70C1 70C1 70C1 70C1 OUT DQ7 G3 70B3 CKE 70B3 DQ8 B11 J11 CK CK* 70B3 DQ9 B10 70B3 DQ10 C11 F4 CS* 70B3 DQ11 C10 H4 70C3 DQ12 70C3 DQ13 E11 F9 WE* CAS* H10 RAS* 70C3 DQ14 F11 70C3 DQ15 70C3 DQ16 G10 A9 ZQ MF V4 SEN 70C3 DQ17 L10 RESET 70C3 DQ18 N11 70C3 DQ19 M10 70C3 DQ20 70C3 DQ21 R11 OUT OUT 70C3 DQ22 T11 OUT T10 V9 FB_B_RDQS FB_B_RDQS FB_B_RDQS FB_B_RDQS D3 D10 P10 P3 RDQS0 RDQS1 RDQS2 RDQS3 70C1 IO 70C1 IO 70C1 IN IO 70C1 IN 73A8 70D1 IN IO IO IO 73A8 70D1 73A8 70D1 IN IN IN IN FB_B_WDQS FB_B_WDQS FB_B_WDQS FB_B_WDQS FB_B_BA FB_B_BA FB_B_BA R9098 243 5% 1/16W MF-LF 402 1% 1/16W MF-LF 402 R9099 100 2 NC NC R10 WDQS0 D11 WDQS1 DQ25 L3 70B3 P11 DQ26 DQ27 N2 70B3 P2 WDQS2 WDQS3 R2 70B3 BA0 DQ28 G9 DQ29 DQ30 R3 70B3 DQ31 T3 70B3 BA1 H3 BA2 J2 RFU1 J3 RFU2 IO M11 D2 G4 F10 70C3 DQ23 DQ24 IO IO F3 70B3 H9 A4 FB_DRAM_RST C2 70B3 L9 J10 FB_B1_ZQ FB_B1_MF FB_B1_SEN N3 A10 A11 K11 IO 70B1 FB_B_DQM_L FB_B_DQM_L FB_B_DQM_L 70C1 FB_B_DQM_L K9 H11 K4J52324QC-BC20 D M12 V11 FERR-220-OHM M1 VDD3 VDD4 A10 MFHIGH F1 F12 A3 VSS1 VSS2 16MX32-GDDR3-500MHZ 0.1uF VSS0 MFHIGH 2 C9001 U9000 MFHIGH 20% 6.3V CERM 805 VDD1 VDD2 CRITICAL OMIT =PP1V8_S0_FB_VDD /x / 1 22UF VDD0 K4J52324QC-BC20 C9000 A2 A11 IN K4J52324QC-BC20 73D8 72D8 72D5 65B6 16MX32-GDDR3-500MHZ CRITICAL OMIT =PP1V8_S0_FB_VDD 16MX32-GDDR3-500MHZ 72D5 65B6 73D5 72D8 IN su M2 70B3 M3 70B3 T2 70B3 FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ IN IN IO B IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO GDDR3 Frame Buffer B IO IO SYNC_MASTER=(MASTER) IO IO SYNC_DATE=(MASTER) NOTICE OF PROPRIETARY PROPERTY IO THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING IO IO I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART 5% 1/16W MF-LF 402 SIZE APPLE COMPUTER INC DRAWING NUMBER D SCALE SHT NONE REV 051-7150 A.0.0 OF 73 84 A Page Notes Power aliases required by this page: - =PP3V3_GPU_GPIOS - =PP2V5_PVDD - =PP1V8_GPU_LVDS_PLL 68C4 65A3 Signal aliases required by this page: - =I2C_GPU_TMDS_SDA - I2C data line for external TMDS transmitters - =I2C_GPU_TMDS_SCL - I2C clock line for external TMDS transmitters =PP3V3_S0_GPU OMIT U8400 BGA 71B8 71B8 71B8 71B8 71B8 71B8 71B8 71B8 71B8 71B8 71B8 71B8 71B8 71B8 71B8 71B8 71B8 65A3 GPU_GPIO_18 GPU_GPIO_19 GPU_GPIO_20 GPU_GPIO_21 GPU_GPIO_22 GPU_GPIO_23 GPU_GPIO_24 GPU_GPIO_25 GPU_GPIO_26 GPU_GPIO_27 GPU_GPIO_28 GPU_GPIO_29 GPU_GPIO_30 GPU_GPIO_31 GPU_GPIO_32 GPU_GPIO_33 GPU_GPIO_34 AE13 AF13 AF9 AG7 AE10 AE9 AF7 AF8 AH6 AF10 AG10 AH9 AJ8 AH8 AG9 AH7 AG8 GPIO_18 GPIO_19 GPIO_20 GPIO_21 GPIO_22 GPIO_23 GPIO_24 GPIO_25 GPIO_26 GPIO_27 GPIO_28 GPIO_29 GPIO_30 GPIO_31 GPIO_32 GPIO_33 GPIO_34 =PP3V3_S0_GPU_VDDR3 Typically