Apple macbook pro retina 15, a1398

8 ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5% ALL CAPACITANCE VALUES ARE IN MICROFARADS ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ REV ECN DESCRIPTION OF REVISION CK APPD DATE 2012-05-09 SCHEM,MLB,KEPLER,2PHASE,D2 FSB, 5/9/2012 (.csa) D Date Page Contents TABLE_TABLEOFCONTENTS_HEAD TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM C TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM B 1 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM Sync Table of Contents D2_KEPLER System Block Diagram D2_KEPLER Power Block Diagram D2_KEPLER Revision History D2_KEPLER BOM Configuration (.csa) 01/13/2012 TABLE_TABLEOFCONTENTS_HEAD 01/13/2012 TABLE_TABLEOFCONTENTS_ITEM 01/13/2012 TABLE_TABLEOFCONTENTS_ITEM 01/13/2012 TABLE_TABLEOFCONTENTS_ITEM 01/13/2012 TABLE_TABLEOFCONTENTS_ITEM 01/13/2012 TABLE_TABLEOFCONTENTS_ITEM 01/13/2012 TABLE_TABLEOFCONTENTS_ITEM 01/13/2012 TABLE_TABLEOFCONTENTS_ITEM 01/13/2012 TABLE_TABLEOFCONTENTS_ITEM D2_KEPLER BOM Variants D2_KEPLER Functional / ICT Test D2_KEPLER Power Aliases D2_KEPLER Signal Aliases D2_KEPLER 10 CPU DMI/PEG/FDI/RSVD D2_KEPLER CPU CLOCK/MISC/JTAG D2_KEPLER 11 12 CPU DDR3 INTERFACES 01/13/2012 TABLE_TABLEOFCONTENTS_ITEM 01/13/2012 TABLE_TABLEOFCONTENTS_ITEM 01/13/2012 TABLE_TABLEOFCONTENTS_ITEM 01/13/2012 TABLE_TABLEOFCONTENTS_ITEM 01/13/2012 TABLE_TABLEOFCONTENTS_ITEM 03/05/2012 TABLE_TABLEOFCONTENTS_ITEM 03/05/2012 TABLE_TABLEOFCONTENTS_ITEM D2_KEPLER 13 CPU POWER D2_KEPLER 14 CPU POWER AND GND D2_KEPLER 16 CPU DECOUPLING-I D2_SEAN CPU DECOUPLING-II D2_SEAN 17 18 PCH SATA/PCIe/CLK/LPC/SPI 01/13/2012 TABLE_TABLEOFCONTENTS_ITEM 01/13/2012 TABLE_TABLEOFCONTENTS_ITEM 01/13/2012 TABLE_TABLEOFCONTENTS_ITEM 01/13/2012 TABLE_TABLEOFCONTENTS_ITEM 03/19/2012 TABLE_TABLEOFCONTENTS_ITEM 01/13/2012 TABLE_TABLEOFCONTENTS_ITEM 03/19/2012 TABLE_TABLEOFCONTENTS_ITEM D2_KEPLER 19 PCH DMI/FDI/PM/Graphics D2_KEPLER 20 PCH PCI/USB/TP/RSVD D2_KEPLER 21 PCH GPIO/MISC/NCTF D2_KEPLER 22 PCH POWER D2_CLEAN 23 PCH GROUNDS D2_KEPLER PCH DECOUPLING D2_CLEAN 24 25 CPU & PCH XDP 01/13/2012 TABLE_TABLEOFCONTENTS_ITEM 01/13/2012 TABLE_TABLEOFCONTENTS_ITEM 01/13/2012 TABLE_TABLEOFCONTENTS_ITEM 01/13/2012 TABLE_TABLEOFCONTENTS_ITEM 01/13/2012 TABLE_TABLEOFCONTENTS_ITEM 01/13/2012 TABLE_TABLEOFCONTENTS_ITEM 01/13/2012 TABLE_TABLEOFCONTENTS_ITEM D2_KEPLER 26 Chipset Support D2_KEPLER 27 USB HUB & MUX D2_KEPLER 28 CPU Memory S3 Support D2_KEPLER 29 DDR3 SDRAM Bank A (1 OF 2) D2_KEPLER 30 DDR3 SDRAM Bank A (2 OF 2) D2_KEPLER DDR3 SDRAM Bank B (1 OF 2) D2_KEPLER 31 32 DDR3 SDRAM Bank B (2 OF 2) 01/13/2012 TABLE_TABLEOFCONTENTS_ITEM 01/13/2012 TABLE_TABLEOFCONTENTS_ITEM 01/13/2012 TABLE_TABLEOFCONTENTS_ITEM 01/13/2012 TABLE_TABLEOFCONTENTS_ITEM 01/13/2012 TABLE_TABLEOFCONTENTS_ITEM 01/13/2012 TABLE_TABLEOFCONTENTS_ITEM 01/13/2012 TABLE_TABLEOFCONTENTS_ITEM 01/13/2012 TABLE_TABLEOFCONTENTS_ITEM 01/13/2012 TABLE_TABLEOFCONTENTS_ITEM 01/13/2012 TABLE_TABLEOFCONTENTS_ITEM 01/13/2012 TABLE_TABLEOFCONTENTS_ITEM 01/13/2012 TABLE_TABLEOFCONTENTS_ITEM D2_KEPLER 33 DDR3 Termination D2_KEPLER 34 DDR3/FRAMEBUF VREF MARGINING D2_KEPLER 35 X29/ALS/CAMERA CONNECTOR D2_KEPLER 36 Thunderbolt Host (1 of 2) D2_KEPLER 37 Thunderbolt Host (2 of 2) D2_KEPLER Thunderbolt Power Support D2_KEPLER 38 44 RIO CONNECTOR D2_KEPLER 45 SSD CONNECTOR D2_KEPLER 46 USB 3.0 CONNECTORS D2_KEPLER 49 SMC D2_KEPLER SMC Support D2_KEPLER 50 51 LPC+SPI Debug Connector 01/13/2012 TABLE_TABLEOFCONTENTS_ITEM 01/13/2012 TABLE_TABLEOFCONTENTS_ITEM 03/05/2012 TABLE_TABLEOFCONTENTS_ITEM D2_KEPLER 52 SMBus Connections D2_KEPLER 53 Voltage & Load Side Current Sensing D2_SEAN TABLE_TABLEOFCONTENTS_ITEM Date Page 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 Contents Sync 54 High Side and CPU/AXG Current Sensing D2_SEAN Thermal Sensors D2_SEAN 55 56 Fan Connectors D2_KEPLER KEYBOARD/TRACKPAD (1 OF 2) D2_KEPLER 57 58 KEYBOARD/TRACKPAD (2 OF 2) (.csa) 03/05/2012 TABLE_TABLEOFCONTENTS_HEAD 03/05/2012 TABLE_TABLEOFCONTENTS_ITEM 01/13/2012 TABLE_TABLEOFCONTENTS_ITEM 01/13/2012 TABLE_TABLEOFCONTENTS_ITEM 01/13/2012 TABLE_TABLEOFCONTENTS_ITEM 01/13/2012 TABLE_TABLEOFCONTENTS_ITEM 01/13/2012 TABLE_TABLEOFCONTENTS_ITEM 03/16/2012 TABLE_TABLEOFCONTENTS_ITEM 03/16/2012 TABLE_TABLEOFCONTENTS_ITEM D2_KEPLER 59 DIGITAL ACCELEROMETER & GYRO D2_KEPLER 61 SPI ROM D2_KEPLER 62 AUDIO: CODEC/REGULATOR D2_CARA AUDIO: HEADPHONE FILTER D2_CARA 63 64 03/16/2012 AUDIO: IV SENSE D2_CARA AUDIO: IV SENSE FILTER D2_CARA AUDIO: SPEAKER AMP D2_CARA AUDIO: JACK D2_CARA AUDIO: JACK TRANSLATORS D2_CARA DC-In & Battery Connectors D2_KEPLER PBus Supply & Battery Charger D2_KEPLER System Agent Supply D2_KEPLER 5V / 3.3V Power Supply D2_KEPLER 1V5R1V35V DDR3 SUPPLY D2_KEPLER CPU IMVP7 & AXG VCore Regulator D2_SEAN CPU IMVP7 & AXG VCore Output D2_SEAN CPU VCCIO (1V0R1V05 S0) POWER SUPPLY D2_KEPLER Misc Power Supplies D2_KEPLER Power FETs D2_KEPLER Power Control 1/ENABLE D2_KEPLER KEPLER PCI-E D2_KEPLER KEPLER CORE/FB POWER D2_SEAN KEPLER FRAME BUFFER I/F D2_SEAN 1V05 GPU / 1V35 FB POWER SUPPLY D2_SEAN GDDR5 Frame Buffer A D2_SEAN GDDR5 Frame Buffer B D2_SEAN KEPLER EDP/DP/GPIO D2_SEAN KEPLER GPIOS,CLK & STRAPS D2_SEAN KEPLER PEX PWR/GNDS D2_SEAN GFX IMVP VCore Regulator D2_SEAN 65 91 92 93 94 95 96 97 98 99 D Date Page Contents Sync 102 01/13/2012 PCH Constraints D2_KEPLER PCH Constraints D2_KEPLER 103 01/13/2012 105 01/13/2012 Thunderbolt Constraints D2_KEPLER SMC Constraints D2_KEPLER GPU (Kepler) CONSTRAINTS D2_KEPLER Project Specific Constraints D2_CLEAN PCB Rule Definitions D2_KEPLER 106 01/13/2012 107 01/13/2012 108 03/15/2012 109 01/13/2012 130 03/05/2012 DEBUG SENSORS AND ADC D2_SEAN SMC12 SENSORS EXTENDED D2_KEPLER 132 01/13/2012 TABLE_TABLEOFCONTENTS_ITEM 03/16/2012 66 03/16/2012 67 03/16/2012 68 03/16/2012 69 01/13/2012 70 01/13/2012 71 C 01/13/2012 72 01/13/2012 73 01/13/2012 74 03/05/2012 75 03/05/2012 76 01/13/2012 77 01/13/2012 78 01/13/2012 79 01/13/2012 80 01/13/2012 81 03/05/2012 82 03/05/2012 83 03/05/2012 84 03/05/2012 85 03/05/2012 86 03/05/2012 87 03/05/2012 88 03/05/2012 89 B 03/05/2012 90 01/13/2012 eDP Display Connector D2_KEPLER eDP Mux D2_SEAN eDP Muxed Graphics Support D2_SEAN Thunderbolt Connector A D2_KEPLER Thunderbolt Connector B D2_KEPLER 91 03/05/2012 92 03/05/2012 94 01/13/2012 96 01/13/2012 97 01/13/2012 LCD Backlight Driver (LP8545) D2_KEPLER PCH VCCIO (1.05V) POWER SUPPLY D2_KEPLER Power Sequencing EG/PCH S0 D2_KEPLER CPU Constraints D2_KEPLER Memory Constraints D2_KEPLER 98 01/13/2012 99 01/13/2012 100 01/13/2012 101 01/13/2012 TABLE_TABLEOFCONTENTS_ITEM A A DRAWING TITLE SCHEM,MLB,KEPLER,2PHASE,D2 DRAWING NUMBER Schematic / PCB #’s PART NUMBER QTY Apple Inc DESCRIPTION REFERENCE DES CRITICAL 051-9589 SCHEM,MLB,KEPLER_2PHASE,D2 SCH CRITICAL 820-3332 PCBF,MLB,KEPLER_2PHASE,D2 PCB CRITICAL BOM OPTION R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED DRAWING TITLE=MLB ABBREV=ABBREV LAST_MODIFIED=Wed May 13:50:52 2012 051-9589 REVISION 4.18.0 BRANCH PAGE OF 132 SHEET OF 99 SIZE D J2500,J2550 INTEL CPU U8000 GRAPHICS 2.X GHZ AMD WHISTLER IVY BRIDGE XDP CONN PG 23 J2900 PG PG 73 J3100 DIMMS DDR3-1067/1333MHZ DIMM D J6950 D PG 26,28 DC/BATT POWER SUPPLY PG 63 GPIO FDI DMI RTC PG 19 PG 17 PG 17 PG 16 U4900 U6100 SPI TEMP SENSOR Boot ROM CLOCK U2700 Misc CK5G05 PG 55 PG 44 CLK PG 19 POWER SENSE BUFFER PG 24 PG 44 PG 16 J5650,5660 FAN CONN AND CONTROL SPI J4501 PG 51 SATA2.0/3(GB/S) PG 16 CONN SATA2.0/3(GB/S) ODD SATA SATA2.0/3(GB/S) PG 41 INTEL SATA J5100 SATA3.0/6(GB/S) CONN SATA3.0/6(GB/S) LPC MOBILE SATA2.0/3(GB/S) B,0 PG 46 ADC BSB Fan Prt SMC Port80,serial PG 16 HDD SATA C Ser LPC + SPI CONN PANTHER-POINT J4500 PG 44 U4900 C PG 16 U1800 PG 41 J3402 U3600 PWR CAMERA PG 31 CTRL DP OUT J4501 IR USB PG 17 U9320 PG 41 RGB OUT HUB DP MUX PG 84 10 11 12 13 33 U3700 J5713 TRACKPAD/KEYBOARD PG 53 USB J3401 BLUETOOTH PG 31 HUB PCI (RESERVATION) PG PG 18 MINI DP PORT PG 18 USB TMDS OUT J9400 (UP TO 14 DEVICES) LVDS OUT PG 33 EXTERNAL C PG 33 DVI OUT PG 83 EXTERNAL B HDMI OUT XP25-5G J4610 PG 18 J4600 EXTERNAL A U9370 PG 34 PG 34 B B JTAG SMB DDC MUX SMBUS PG 16 PG 16 PG 83 CONNECTION PCI-E PG 47 HDA PEG (UP TO 16 LINES) PG 16 PG 16 PG 16 DIMM LCD PANEL PG 26,28 U9600 U6201 AUDIO GMUX CODEC PG 86 PG 56 U6610,6620,6630 U4100 U3900 A GB FW643 LINE TIN E-NET J3401 FILTER HEADPHONE SPEATKER FILTER AMP PG 58 PG 59 SYNC_MASTER=D2_KEPLER PG 38 PG 57 System Block Diagram PG 36 AirPort DRAWING NUMBER PG 31 J4310 J4000 Apple Inc J3500 E-NET SDCARD READER CONN CONN CONN PG 37 NOTICE OF PROPRIETARY PROPERTY: AUDIO SPEATKER THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED PG 37 PG 63 PG 60 4.18.0 J6700,J6750 CONN 051-9589 REVISION R FIREWIRE PG 40 SYNC_DATE=01/13/2012 PAGE TITLE BCM57765 BRANCH PAGE OF 132 SHEET OF 99 SIZE D A D6990 D2 POWER SYSTEM ARCHITECTURE PP18V5_DCIN_CONN SMC PWRGD SMC_RESET_L NCP303LSN U5000 (PAGE 45) R6990 ENABLE PPBUS_G3H SMC AVREF SUPPLY 3.425V G3HOT PP3V3_S5_AVREF_SMC PP3V42_G3H PM6640 SMC_PBUS_VSENSE VIN U6990 J6900 V F7040 D VOUT PP3V3_S5_SMC (PAGE 45) Q5315 SMC_TPAD_RST_L D PPBUS_G3H F6905 6A FUSE AC (PAGE 62) REF3333 SMC_ONOFF_L R7020 U5001 DCIN(16.5V) 8A FUSE A ADAPTER U7000 PPVBAT_G3H VIN VIN VOUT IN PP5V_S3_GFXIMVP6_VDD VDD ISL6259HRTZ SMC_DCIN_ISENSE V A VOUT R7640 SMC_GPU_VSENSE PPVCORE_GPU PP5V_S0_CPUVTTS0 VIN 1.05V GPU VCORE ISL6263C A R7050 SMC_GPU_ISENSE CPUVTTS0_EN VR_ON SMC_BATT_ISENSE TPS22924 U4202 CPUVTTS0_PGOOD U8900 SMC_RESET_L SMC_CPU_FSB_ISENSE ISL95870 U7600 U5410 PBUS SUPPLY/ BATTERY CHARGER PPCPUVTT_S0 A VOUT PGOOD EN EN PGOOD (PAGE 70) GPUVCORE_PGOOD GPUVCORE_EN FW_PWR_EN (PAGE 82) (PAGE 64) PP1V0_FW_FWPHY (PAGE 39) SMC_CPU_VSENSE J6950 PPVBAT_G3H_CHGR_R CPU VCORE SMC_CPU_HI_ISENSE A (9 TO 12.6V) 3S2P V R5388/U5388 Q7055 PPVBATT_G3H_CONN A VOUT VIN PANTHER_POINT SMC_CPU_ISENSE SYS_RERST# U7400 CPUIMVP7_VR_ON VR_ON RSMRST# CPUIMVP7_AXG_PGOOD PGOOD ACPRESENT (PAGE 67) www.qdzbwx.com PM_PCH_PWRGD PLT_RERST_L PS_PWRGD PLTRST# CPU_PWRGD U1800 C GMUX PB16B PROCPWRGD P1V1GPU_EN EG_RAIL1_EN U9600 PB17B EG_RAIL2_EN P3V3GPU_EN EG_RAIL3_EN GPUVCORE_EN U2850 PP5V_S3_DDRREG PM_MEM_PWRGD C SMC_ADAPTER_EN B DRAMPWROK U5440 PB17A PM_PWRBTN_L PWRBTN# ISL95831 CHGR_BGATE PPVCORE_S0_CPU (PAGE 16~21) SMC_CPU_DDR_VSENSE R7350 XP25-5 PB18A EG_RAIL4_EN S5 P1V0GPU_EN (PAGE 86) EN1 PPDDR_S3_REG VOUT1 DDRVTT_EN VOUT1 S3 R5413 1.003V(L/H) A VOUT2 EN2 1.503V(R/H) 0.75V PP1V5_S3 A PP1V0_S0GPU_REG VIN P1V5FB_EN SMC VLDOIN 1.5V DDRREG_EN PM_ALL_GPU_PGOOD PL32A V SMC_DDR_ISENSE VIN PPVTT_S0_DDR_LDO VOUT2 SM_DRAMPWROK CPU PP1V5_GPU_REG TPS51116 U7300 SMC_GPU_1V8_ISENSE DDRREG_PGOOD 4.5V VIN MAX8840 EN U6200 PGOOD (PAGE 66) U4900 ISL6236 RC P60 (PAGE 85) DELAY SMC_PM_G2_EN P1V0GPU_PGOOD POK1 U1000 PP3V3_S0 U9500 P3V3S5_EN PP4V5_AUDIO_ANALOG PP1V5_S3 P1V5FB_PGOOD POK2 VCCCPUPWRGD VOUT (PAGE 9~14) RESET* Q7860 Q7801 P1V5CPU_EN (PAGE 44) PP5V_S0 VIN ON PP1V5_S3RS0 G SLG5AP020 U7801 VIN P5VS3_EN EN1 PANTHER-POINT VREG5 5V VOUT1 PP5V_S3 P5VS0_EN P1V5S0FET_GATE PM_ALL_GPU_PGOOD (L/H) MOBILE PP3V3_S5 PM_SLP_S5_L P3V3S5_EN SLP_S5#(E4) EN2 Q9806 B 3.3V PP3V3_S5 VOUT2 U7980 RC TPS51125 U7201 P5VS3_EN P1V8FB_EN BKLT_PLT_RST_L && LCD_BKLT_NO DDRREG_EN DELAY U1800 PWRGD(P12) PP1V8_GPUIFPX (P64) G SLG5AP020 U7880 RSMRST_PWRGD RSMRST_OUT(P15) CPUIMVP_VR_ON P3V3GPU_EN IMVP_VR_ON(P16) PM_SYSRST_L Q7810 SYSRST(PA2) U9701 ENA PM_RSMRST_L 99ms DLY PWR_BUTTON(P90) VIN LP8550 BKLT_EN RSMRST_IN(P13) SMC_ONOFF_L P1V8GPUIFPXFET_GATE P5V3V3_PGOOD P3V3S3_EN VIN ON PP3V3_S0GPU (PAGE 65) PGOOD RC ALL_SYS_PWRGD Q7880 Q7870 DELAY SMC PP1V8_S0 (R/H) VOUT PP3V3_S3 PPVOUT_S0_LCDBKLT Q7922 PP3V3_ENET PP3V3_S0_PWRCTL PM_PWRBTN_L P17(BTN_OUT) (PAGE 87) PM_SLP_S4_L P1V8S0_PGOOD PM_SLP_S5_L SLP_S4#(H7) SLP_S5_L(P95) P3V3S3_EN P5V3V3_PGOOD PM_SLP_S3_L&&WOL_EN||SMC_ADAPTER_EN Q4260 U4201 PP3V3_S0_FET RES* SLP_S4_L(P94) TPS22924 PFWBOOST SLP_S3#(P12) SMC_RESET_L PM_SLP_S4_L Q7830 PM_SLP_S3_L S0PGOOD_PWROK PP3V3_FW_FWPHY PM_SLP_S3_L SLP_S3_L(P93) H8S2117 (PAGE 39) (PAGE 16~21) EN U4900 (PAGE 45) PP3V3_S0 P3V3S0_EN FW_PWR_EN SMC_ADAPTER_EN&&PM_SLP_S3_L VCC PP3V3_S0 R7978 V2MON U7971 ISL8014A EN RC V4MON (PAGE Q7850 PP1V2_S0 SYNC_MASTER=D2_KEPLER SYNC_DATE=01/13/2012 PAGE TITLE Power Block Diagram P3V3S0_EN P1V2S0_EN VIN P1V2ENET_EN CPUVTTS0_EN DELAY ISL8014A U7760 (PAGE 70) VOUT PGOOD DRAWING NUMBER PP1V2_ENET Apple Inc P1V2ENET_PGOOD PBUSVSENS_EN NOTICE OF PROPRIETARY PROPERTY: P1V5CPU_EN THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED 051-9589 REVISION R DELAY 72) TRST = 200mS P1V2S0_EN EN RC RST* PP1V05_S0 P1V8S0_PGOOD P5VS0_EN DELAY RC PGOOD V3MON P1V8S0_EN DELAY RC PP1V8_S0 VOUT U7720 (PAGE 70) A ISL88042IRTJJZ PP1V5_S0 VIN P1V8_S0_EN PM_SLP_S3_L_R 4.18.0 BRANCH PAGE OF 132 SHEET OF 99 SIZE D A D D C C B B A SYNC_MASTER=D2_KEPLER SYNC_DATE=01/13/2012 PAGE TITLE Revision History DRAWING NUMBER Apple Inc 051-9589 REVISION R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED 4.18.0 BRANCH PAGE OF 132 SHEET OF 99 SIZE D A BOM Variants (continued on CSA 6) Bar Code Labels / EEEE #’s (continued on CSA 6) Alternate Parts TABLE_BOMGROUP_HEAD BOM NUMBER BOM NAME TABLE_ALT_HEAD PART NUMBER BOM OPTIONS QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION PART NUMBER ALTERNATE FOR PART NUMBER 128S0257 BOM OPTION REF DES COMMENTS: 128S0264 ALL Kemet alt to Sanyo 353S3527 353S3528 ALL Pericom eDP MUX 353S3526 353S3528 ALL TI eDP MUX 376S0855 376S0613 ALL Diodes alt to Toshiba 376S0855 376S0613 ALL Diodes alt to Toshiba 376S1076 376S0634 ALL Diodes alt to On Semi 376S0903 376S0796 ALL Fairchild alt to Siliconix 376S0977 376S0859 ALL Diodes alt to Toshiba 376S1053 376S0604 ALL Diodes alt to Fairchild 128S0311 128S0329 ALL NEC alt to Sanyo 138S0739 138S0706 ALL Samsung alt to Murata 197S0434 197S0343 ALL Epson Alt to TXC 197S0435 197S0343 ALL NDK Alt to TXC 197S0432 197S0431 ALL NDK Alt to Epson 197S0452 197S0181 ALL Epson Alt to TXC 197S0453 197S0181 ALL NDK Alt to TXC 685-0017 685-0016 ALL Sanyo POSCAP/Mylar alt to Kemet 376S0975 376S1081 ALL Toshiba alt to diodes 371S0709 371S0652 ALL NXP alt to infineon 371S0713 371S0558 ALL DDS alt to ST 377S0126 377S0066 ALL New Semtech package 377S0147 377S0066 ALL On Semi alt to Semtech 152S0461 152S1645 ALL Cyntec alt to Vishay 376S1080 376S0820 ALL Diodes alt to On Semi 155S0667 155S0583 ALL Panasonic alt to TDK TABLE_BOMGROUP_ITEM 085-3726 D2,MLB,KEPLER,DEV D2_DEVEL:ENG 085-4776 D2,MLB,KEPLER,FSB DEV D2_DEVEL:FSB 607-9546 D2,MLB,KEPLER_2PHASE,COMMON D2_COMMON,POSCAP_MYLAR_PAIR 685-0016 PBUS PAIR,KEMET POSCAP,TALL MYLAR,D2 PBUS_CAP:KEMET 685-0017 PBUS PAIR,SANYO POSCAP,SHORT MYLAR,D2 PBUS_CAP:SANYO 639-3378 PCBA,2.3G,8G_HYN,VRAM_HYN,MLB_KEPLER,D2,DY3V BASE_BOM,CPU_IVY:2_3GHZ,FB_2G_HYNIX_A_DIE,EEEE:DY3V,DEVEL_BOM,RAM_2G_HYNIX_1600 639-3379 PCBA,2.3G,8G_HYN,VRAM_SAM,MLB_KEPLER,D2,DY3W BASE_BOM,CPU_IVY:2_3GHZ,FB_2G_SAMSUNG,EEEE:DY3W,DEVEL_BOM,RAM_2G_HYNIX_1600 639-3380 PCBA,2.3G,8G_SAM,VRAM_HYN,MLB_KEPLER,D2,DY3Y BASE_BOM,CPU_IVY:2_3GHZ,FB_2G_HYNIX_A_DIE,EEEE:DY3Y,DEVEL_BOM,RAM_2G_SAMSUNG_1600 825-7563 LABEL,MLB/LIO,MBA [EEEE:DY3V] CRITICAL EEEE:DY3V 825-7563 LABEL,MLB/LIO,MBA [EEEE:DY3W] CRITICAL EEEE:DY3W 825-7563 LABEL,MLB/LIO,MBA [EEEE:DY3Y] CRITICAL EEEE:DY3Y 825-7563 LABEL,MLB/LIO,MBA [EEEE:DY40] CRITICAL EEEE:DY40 825-7563 LABEL,MLB/LIO,MBA [EEEE:DY43] CRITICAL EEEE:DY43 825-7563 LABEL,MLB/LIO,MBA [EEEE:DY44] CRITICAL EEEE:DY44 825-7563 LABEL,MLB/LIO,MBA [EEEE:DY45] CRITICAL EEEE:DY45 825-7563 LABEL,MLB/LIO,MBA [EEEE:DY4C] CRITICAL EEEE:DY4C TABLE_ALT_ITEM TABLE_BOMGROUP_ITEM TABLE_ALT_ITEM TABLE_BOMGROUP_ITEM TABLE_ALT_ITEM TABLE_BOMGROUP_ITEM TABLE_ALT_ITEM TABLE_BOMGROUP_ITEM TABLE_ALT_ITEM VREFDQ:M1_M3 TABLE_BOMGROUP_ITEM D TABLE_ALT_ITEM D TABLE_BOMGROUP_ITEM TABLE_ALT_ITEM TABLE_BOMGROUP_ITEM TABLE_ALT_ITEM TABLE_BOMGROUP_ITEM 639-3381 PCBA,2.3G,8G_SAM,VRAM_SAM,MLB_KEPLER,D2,DY40 BASE_BOM,CPU_IVY:2_3GHZ,FB_2G_SAMSUNG,EEEE:DY40,DEVEL_BOM,RAM_2G_SAMSUNG_1600 639-3384 PCBA,2.3G,16G_HYN,VRAM_HYN,MLB_KEPLER,D2,DY43 BASE_BOM,CPU_IVY:2_3GHZ,FB_2G_HYNIX_A_DIE,EEEE:DY43,DEVEL_BOM,RAM_4G_HYNIX_1600 639-3385 PCBA,2.3G,16G_HYN,VRAM_SAM,MLB_KEPLER,D2,DY44 BASE_BOM,CPU_IVY:2_3GHZ,FB_2G_SAMSUNG,EEEE:DY44,DEVEL_BOM,RAM_4G_HYNIX_1600 639-3386 PCBA,2.3G,16G_SAM,VRAM_HYN,MLB_KEPLER,D2,DY45 BASE_BOM,CPU_IVY:2_3GHZ,FB_2G_HYNIX_A_DIE,EEEE:DY45,DEVEL_BOM,RAM_4G_SAMSUNG_1600 639-3387 PCBA,2.3G,16G_SAM,VRAM_SAM,MLB_KEPLER,D2,DY4C BASE_BOM,CPU_IVY:2_3GHZ,FB_2G_SAMSUNG,EEEE:DY4C,DEVEL_BOM,RAM_4G_SAMSUNG_1600 639-2821 PCBA,2.6G,8G_HYN,VRAM_HYN,MLB_KEPLER,D2,DRF1 BASE_BOM,CPU_IVY:2_6GHZ,FB_2G_HYNIX_A_DIE,EEEE:DRF1,DEVEL_BOM,RAM_2G_HYNIX_1600 639-2825 PCBA,2.6G,8G_HYN,VRAM_SAM,MLB_KEPLER,D2,DRF4 BASE_BOM,CPU_IVY:2_6GHZ,FB_2G_SAMSUNG,EEEE:DRF4,DEVEL_BOM,RAM_2G_HYNIX_1600 639-2817 PCBA,2.6G,8G_SAM,VRAM_HYN,MLB_KEPLER,D2,DRDN BASE_BOM,CPU_IVY:2_6GHZ,FB_2G_HYNIX_A_DIE,EEEE:DRDN,DEVEL_BOM,RAM_2G_SAMSUNG_1600 639-2815 PCBA,2.6G,8G_SAM,VRAM_SAM,MLB_KEPLER,D2,DRDW BASE_BOM,CPU_IVY:2_6GHZ,FB_2G_SAMSUNG,EEEE:DRDW,DEVEL_BOM,RAM_2G_SAMSUNG_1600 639-2979 PCBA,2.6G,16G_HYN,VRAM_HYN,MLB_KEPLER,D2,DT9H BASE_BOM,CPU_IVY:2_6GHZ,FB_2G_HYNIX_A_DIE,EEEE:DT9H,DEVEL_BOM,RAM_4G_HYNIX_1600 639-2980 PCBA,2.6G,16G_HYN,VRAM_SAM,MLB_KEPLER,D2,DT9D BASE_BOM,CPU_IVY:2_6GHZ,FB_2G_SAMSUNG,EEEE:DT9D,DEVEL_BOM,RAM_4G_HYNIX_1600 639-2981 PCBA,2.6G,16G_SAM,VRAM_HYN,MLB_KEPLER,D2,DT9F BASE_BOM,CPU_IVY:2_6GHZ,FB_2G_HYNIX_A_DIE,EEEE:DT9F,DEVEL_BOM,RAM_4G_SAMSUNG_1600 825-7563 LABEL,MLB/LIO,MBA [EEEE:DRF1] CRITICAL EEEE:DRF1 825-7563 LABEL,MLB/LIO,MBA [EEEE:DRF4] CRITICAL EEEE:DRF4 825-7563 LABEL,MLB/LIO,MBA [EEEE:DRDN] CRITICAL EEEE:DRDN 825-7563 LABEL,MLB/LIO,MBA [EEEE:DRDW] CRITICAL EEEE:DRDW 825-7563 LABEL,MLB/LIO,MBA [EEEE:DT9H] CRITICAL EEEE:DT9H 825-7563 LABEL,MLB/LIO,MBA [EEEE:DT9D] CRITICAL EEEE:DT9D 825-7563 LABEL,MLB/LIO,MBA [EEEE:DT9F] CRITICAL EEEE:DT9F 825-7563 LABEL,MLB/LIO,MBA [EEEE:DT9G] CRITICAL EEEE:DT9G 825-7563 LABEL,MLB/LIO,MBA [EEEE:F0HN] CRITICAL EEEE:F0HN 825-7563 LABEL,MLB/LIO,MBA [EEEE:F0HR] CRITICAL EEEE:F0HR 825-7563 LABEL,MLB/LIO,MBA [EEEE:DYW4] CRITICAL EEEE:DYW4 825-7563 LABEL,MLB/LIO,MBA [EEEE:F0HV] CRITICAL EEEE:F0HV TABLE_ALT_ITEM TABLE_BOMGROUP_ITEM TABLE_ALT_ITEM TABLE_BOMGROUP_ITEM TABLE_ALT_ITEM TABLE_BOMGROUP_ITEM TABLE_ALT_ITEM TABLE_BOMGROUP_ITEM TABLE_ALT_ITEM TABLE_BOMGROUP_ITEM TABLE_ALT_ITEM TABLE_BOMGROUP_ITEM TABLE_ALT_ITEM TABLE_BOMGROUP_ITEM TABLE_ALT_ITEM TABLE_BOMGROUP_ITEM TABLE_ALT_ITEM TABLE_BOMGROUP_ITEM TABLE_ALT_ITEM TABLE_BOMGROUP_ITEM TABLE_ALT_ITEM TABLE_BOMGROUP_ITEM TABLE_ALT_ITEM TABLE_BOMGROUP_ITEM 639-2982 PCBA,2.6G,16G_SAM,VRAM_SAM,MLB_KEPLER,D2,DT9G BASE_BOM,CPU_IVY:2_6GHZ,FB_2G_SAMSUNG,EEEE:DT9G,DEVEL_BOM,RAM_4G_SAMSUNG_1600 639-3618 PCBA,2.7G,8G_HYN,VRAM_HYN,MLB_KEPLER,D2,F0HN BASE_BOM,CPU_IVY:2_7GHZ,FB_2G_HYNIX_A_DIE,EEEE:F0HN,DEVEL_BOM,RAM_2G_HYNIX_1600 639-3619 PCBA,2.7G,8G_HYN,VRAM_SAM,MLB_KEPLER,D2,F0HR BASE_BOM,CPU_IVY:2_7GHZ,FB_2G_SAMSUNG,EEEE:F0HR,DEVEL_BOM,RAM_2G_HYNIX_1600 639-3561 PCBA,2.7G,8G_SAM,VRAM_HYN,MLB_KEPLER,D2,DYW4 BASE_BOM,CPU_IVY:2_7GHZ,FB_2G_HYNIX_A_DIE,EEEE:DYW4,DEVEL_BOM,RAM_2G_SAMSUNG_1600 639-3620 PCBA,2.7G,8G_SAM,VRAM_SAM,MLB_KEPLER,D2,F0HV BASE_BOM,CPU_IVY:2_7GHZ,FB_2G_SAMSUNG,EEEE:F0HV,DEVEL_BOM,RAM_2G_SAMSUNG_1600 639-3627 PCBA,2.7G,16G_HYN,VRAM_HYN,MLB_KEPLER,D2,F0HM BASE_BOM,CPU_IVY:2_7GHZ,FB_2G_HYNIX_A_DIE,EEEE:F0HM,DEVEL_BOM,RAM_4G_HYNIX_1600 639-3562 PCBA,2.7G,16G_HYN,VRAM_SAM,MLB_KEPLER,D2,DYW5 BASE_BOM,CPU_IVY:2_7GHZ,FB_2G_SAMSUNG,EEEE:DYW5,DEVEL_BOM,RAM_4G_HYNIX_1600 825-7563 LABEL,MLB/LIO,MBA [EEEE:F0HM] CRITICAL EEEE:F0HM 825-7563 LABEL,MLB/LIO,MBA [EEEE:DYW5] CRITICAL EEEE:DYW5 825-7563 LABEL,MLB/LIO,MBA [EEEE:F0HY] CRITICAL EEEE:F0HY 825-7563 LABEL,MLB/LIO,MBA [EEEE:F0HT] CRITICAL EEEE:F0HT TABLE_ALT_ITEM TABLE_BOMGROUP_ITEM TABLE_ALT_ITEM TABLE_BOMGROUP_ITEM TABLE_ALT_ITEM TABLE_BOMGROUP_ITEM C TABLE_ALT_ITEM C TABLE_BOMGROUP_ITEM Programmables TABLE_BOMGROUP_ITEM TABLE_ALT_ITEM TABLE_ALT_ITEM 341S3584 IC,TRKPD/KYBD CNTRLR,DVB,D2 U5701 CRITICAL TPAD_PSOC:PROG 107S0232 107S0129 ALL Cyntec alt to TFT 337S2983 IC,TP PSOC,QFN,BLANK U5701 CRITICAL TPAD_PSOC:BLANK 197S0466 197S0464 ALL Epson alt to NDK 341S3597 IC,EEPROM,CACTUS RIDGE (8.1) FSB,D2 U3690 CRITICAL TBTROM:PROG 341S3564 341S3565 ALL Avnet eDP MUX alt to Renesas 335S0865 EEPROM,256KBIT,SPI,5MHZ,1.8V,2X3QFN U3690 CRITICAL TBTROM:BLANK 335S0852 IC,GPU ROM,D2,BLANK U8701 CRITICAL GPUROM:BLANK 341S3565 IC,EDP MUX-95C, (RENESAS) V3.2.8,DVB,D2 U9100 CRITICAL DPMUXMCU:PROG 337S4313 IC,MCU,H8S/2113,9X9MM,TLP-145V U9100 CRITICAL DPMUXMCU:BLANK TABLE_BOMGROUP_ITEM TABLE_ALT_ITEM TABLE_BOMGROUP_ITEM 639-3628 PCBA,2.7G,16G_SAM,VRAM_HYN,MLB_KEPLER,D2,F0HY BASE_BOM,CPU_IVY:2_7GHZ,FB_2G_HYNIX_A_DIE,EEEE:F0HY,DEVEL_BOM,RAM_4G_SAMSUNG_1600 639-3629 PCBA,2.7G,16G_SAM,VRAM_SAM,MLB_KEPLER,D2,F0HT BASE_BOM,CPU_IVY:2_7GHZ,FB_2G_SAMSUNG,EEEE:F0HT,DEVEL_BOM,RAM_4G_SAMSUNG_1600 TABLE_ALT_ITEM TABLE_BOMGROUP_ITEM BOM Groups TABLE_BOMGROUP_HEAD BOM GROUP BOM OPTIONS D2_COMMON ALTERNATE,COMMON,D2_COMMON1,D2_COMMON2,D2_PROGPARTS,D2_PVB D2_COMMON1 CPUMEM_S0,SMC_DEBUG_YES,DPMUX:HOCO,TBTRTR:PRQ,TBTBST:Y,TBTHV:P15V,HUB_2NONREM,USBHUB2512B,SPEAKERID,SMC_PACKAGE:PROD,SKIP_5V3V3:AUDIBLE,CHGR_5V:LDO,P1V5S0:LDO D2_COMMON2 EDP:YES,MIKEY,PPCPUVCCIO:IVB,PPDDR:1V35,LPCPLUS_CONN:YES,LPCPLUS_R:YES,KBD_BL:SANDWICH,CAPS:INT,BTPWR:S4,XDP,XDP_CPU:BPM,GPU:2P,TPAD_5V:LDO_S5 TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM DRAM VREF Configs TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_HEAD BOM GROUP BOM OPTIONS TABLE_BOMGROUP_ITEM D2_PVB VREF:PROD,D_BKL:PROD,SENSOR_NONPROD:N D2_PROGPARTS SMC_PROG:FSB,BOOTROM_PROG:FSB,DPMUXMCU:PROG,TPAD_PSOC:PROG,TBTROM:PROG D2_DEVEL:ENG ALTERNATE,IVB_PPT_XDP,S0PGOOD_ISL,DPMUX_DEBUG,DDRVREF_DAC,VREF:ENG_M3,SENSOR_NONPROD:Y,D_BKL:DEV D2_DEVEL:FSB ALTERNATE,IVB_PPT_XDP IVB_PPT_XDP XDP_CONN,XDP_PCH TABLE_BOMGROUP_ITEM VREF:PROD VREFDQ:M1_M3,VREFCA:LDO VREF:ENG_M3 VREFDQ:M1_M3,VREFCA:LDO_DAC VREF:ENG_LDO VREFDQ:M1_DAC,VREFCA:LDO_DAC TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM DRAM SPD Straps TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_HEAD Module Parts B A PART NUMBER 337S4266 QTY BOM GROUP BOM OPTIONS RAM_4G_HYNIX_1600_S RAMCFG3:L,RAMCFG2:L,RAMCFG1:L,RAMCFG0:L RAM_1G_SAMSUNG_1600 RAMCFG3:L,RAMCFG2:L,RAMCFG1:L,RAMCFG0:H RAM_4G_SAMSUNG_1600_S RAMCFG3:L,RAMCFG2:L,RAMCFG1:H,RAMCFG0:L TABLE_BOMGROUP_ITEM DESCRIPTION REFERENCE DES CRITICAL U1000 IVB,S R0MP,PRQ,E1,2.3,45W,4+2,1.2,6M,BGA CRITICAL BOM OPTION 337S4267 IVB,S R0MM,PRQ,E1,2.6,45W,4+2,1.25,6M,BGA U1000 CRITICAL CPU_IVY:2_6GHZ 337S4268 IVB,S R0MK,PRQ,E1,2.7,45W,4+2,1.25,8M,BGA U1000 CRITICAL CPU_IVY:2_7GHZ 337S4269 PANTHER POINT,C1,SLJ8C,PRQ,BD82HM77 U1800 CRITICAL 337S4256 IC,GPU,NV GK107-GTX-PS-A2 U8000 CRITICAL 338S1113 IC,TBT,CR-4C,B1,PRQ,CIO,228 12X12 FC-CSP U3600 CRITICAL TBTRTR:PRQ 333S0622 32 IC,SDRAM,DDR3-1600,256MX8,78FBGA,HYNIX,C-DIE,38NM CRITICAL 2G_HYNIX_1600 333S0623 32 IC,SDRAM,DDR3-1600,256MX8,78FBGA,SAMSUNG CRITICAL 2G_SAMSUNG_1600 333S0628 32 IC,SDRAM,DDR3-1600,256MX8,78FBGA,D-DIE,ELPIDA CRITICAL 2G_ELPIDA_1600 U2900,U2910,U2920,U2930,U2940,U2950,U2960,U2970,U3000,U3010,U3020,U3030,U3040,U3050,U3060,U3070,U3100,U3110,U3120,U3130,U3140,U3150,U3160,U3170,U3200,U3210,U3220,U3230,U3240,U3250,U3260,U3270 U2900,U2910,U2920,U2930,U2940,U2950,U2960,U2970,U3000,U3010,U3020,U3030,U3040,U3050,U3060,U3070,U3100,U3110,U3120,U3130,U3140,U3150,U3160,U3170,U3200,U3210,U3220,U3230,U3240,U3250,U3260,U3270 U2900,U2910,U2920,U2930,U2940,U2950,U2960,U2970,U3000,U3010,U3020,U3030,U3040,U3050,U3060,U3070,U3100,U3110,U3120,U3130,U3140,U3150,U3160,U3170,U3200,U3210,U3220,U3230,U3240,U3250,U3260,U3270 333S0625 32 IC,SDRAM,DDR3-1600,512MX8,78FBGA,HYNIX 333S0624 32 IC,SDRAM,DDR3-1600,512MX8,78FBGA,C-DIE,SAMSUNG 333S0629 32 IC,SDRAM,DDR3-1600,512MX8,78FBGA,B-DIE,ELPIDA 333S0630 IC,SDRAM,GDDR5,64MX32,A-DIE,HYNIX 333S0631 IC,SDRAM,GDDR5,64MX32,D-DIE,SAMSUNG 128S0264 30 CAP,TANT,POLY,68UF,20%,16V,50MOHM,D2E 128S0257 30 CAP,TANT,POLY,68UF,20%,16V,50MOHM,D,LF 725-1614 INSULATOR,SHORT,REAR,MLB,D2 CRITICAL 4G_SAMSUNG_1600 CRITICAL 4G_ELPIDA_1600 U8400,U8450,U8500,U8550 CRITICAL FB_2G_HYNIX_A_DIE U8400,U8450,U8500,U8550 CRITICAL FB_2G_SAMSUNG CRITICAL PBUS_CAP:SANYO CRITICAL PBUS_CAP:KEMET CRITICAL PBUS_CAP:SANYO U2900,U2910,U2920,U2930,U2940,U2950,U2960,U2970,U3000,U3010,U3020,U3030,U3040,U3050,U3060,U3070,U3100,U3110,U3120,U3130,U3140,U3150,U3160,U3170,U3200,U3210,U3220,U3230,U3240,U3250,U3260,U3270 C8921,C8922,C8920,C8926,C7554,C7560,C7561,C7513,C7514,C7523,C7524,C7533,C7534,C7570,C7571,C7572,C7040,C7240,C7242,C7280,C7282,C7330,C7331,C7575,C7620,C7621,C8307,C8356,C9820,C9821 C8921,C8922,C8920,C8926,C7554,C7560,C7561,C7513,C7514,C7523,C7524,C7533,C7534,C7570,C7571,C7572,C7040,C7240,C7242,C7280,C7282,C7330,C7331,C7575,C7620,C7621,C8307,C8356,C9820,C9821 REAR_INSULATOR 725-1648 INSULATOR,TALL,REAR,MLB,D2 REAR_INSULATOR CRITICAL 725-1568 INSULATOR,CPU,D2 CPU_INSULATOR CRITICAL 725-1569 INSULATOR,GPU,D2 GPU_INSULATOR CRITICAL 725-1621 INSULATOR,PCH,D2 PCH_INSULATOR CRITICAL TABLE_BOMGROUP_ITEM RAM_1G_HYNIX_1600 RAMCFG3:L,RAMCFG2:L,RAMCFG1:H,RAMCFG0:H RAM_4G_ELPIDA_1600_S RAMCFG3:L,RAMCFG2:H,RAMCFG1:L,RAMCFG0:L RAM_2G_SAMSUNG_1600 2G_SAMSUNG_1600,RAMCFG3:L,RAMCFG2:H,RAMCFG1:L,RAMCFG0:H RAM_2G_SAMSUNG_1333 RAMCFG3:L,RAMCFG2:H,RAMCFG1:H,RAMCFG0:L RAM_2G_HYNIX_1600 2G_HYNIX_1600,RAMCFG3:L,RAMCFG2:H,RAMCFG1:H,RAMCFG0:H RAM_4G_SAMSUNG_1600 4G_SAMSUNG_1600,RAMCFG3:H,RAMCFG2:L,RAMCFG1:L,RAMCFG0:L TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM 4G_HYNIX_1600 U2900,U2910,U2920,U2930,U2940,U2950,U2960,U2970,U3000,U3010,U3020,U3030,U3040,U3050,U3060,U3070,U3100,U3110,U3120,U3130,U3140,U3150,U3160,U3170,U3200,U3210,U3220,U3230,U3240,U3250,U3260,U3270 B TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM CRITICAL U2900,U2910,U2920,U2930,U2940,U2950,U2960,U2970,U3000,U3010,U3020,U3030,U3040,U3050,U3060,U3070,U3100,U3110,U3120,U3130,U3140,U3150,U3160,U3170,U3200,U3210,U3220,U3230,U3240,U3250,U3260,U3270 TABLE_BOMGROUP_ITEM CPU_IVY:2_3GHZ TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM RAM_4G_HYNIX_1600 4G_HYNIX_1600,RAMCFG3:H,RAMCFG2:L,RAMCFG1:L,RAMCFG0:H RAM_2G_ELPIDA_1600_S RAMCFG3:H,RAMCFG2:L,RAMCFG1:H,RAMCFG0:L RAM_2G_ELPIDA_1600 2G_ELPIDA_1600,RAMCFG3:H,RAMCFG2:L,RAMCFG1:H,RAMCFG0:H RAM_4G_ELPIDA_1600 4G_ELPIDA_1600,RAMCFG3:H,RAMCFG2:H,RAMCFG1:L,RAMCFG0:L RAM_2G_SAMSUNG_1600_S RAMCFG3:H,RAMCFG2:H,RAMCFG1:L,RAMCFG0:H RAM_2G_HYNIX_1600_S RAMCFG3:H,RAMCFG2:H,RAMCFG1:H,RAMCFG0:L TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM DEVELOPMENT/BASE BOM PART NUMBER PBUS_CAP:KEMET PD Parts DESCRIPTION REFERENCE DES 085-3726 D2 MLB KEPLER DEVEL BOM DEVEL CRITICAL DEVEL_BOM 085-4776 D2 MLB KEPLER FSB DEVEL BOM DEVEL_FSB CRITICAL DEVEL_FSB_BOM 607-9546 D2 MLB KEPLER 2PHASE BASE BOM BASE CRITICAL BASE_BOM 685-0016 QTY PBUS PAIR,KEMET POSCAP,TALL MYLAR,D2 POSCAP_MYLAR CRITICAL CRITICAL BOM OPTION SYNC_MASTER=D2_KEPLER SYNC_DATE=01/13/2012 PAGE TITLE BOM Configuration POSCAP_MYLAR_PAIR DRAWING NUMBER SMC Apple Inc 051-9589 REVISION R 806-2897 825-7697 946-3819 825-7841 CAN,COVER,2,J5 CAN_COVER1,CAN_COVER2 CRITICAL 341S3308 IC,SMC,DEVELOPMENT-FSB,A3,D2 U4900 CRITICAL SMC_PROG:FSB TEXT,LABEL,MLB,D2 TEXT_LABEL CRITICAL 341S3309 IC,SMC,PVB,A3,2.2F36,D2 U4900 CRITICAL SMC_PROG:PVB D2 MLB DYMAX ADHESIVE SEE-CURE 29993-SC EDGE_BOND CRITICAL LBL,PART CONFIG,BOARDS,D2 CONFIG_LABEL CRITICAL NOTICE OF PROPRIETARY PROPERTY: EFI ROM 341S3595 IC,EFI,ROM,FSB, D2 U6100 CRITICAL BOOTROM_PROG:FSB THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED 4.18.0 BRANCH PAGE OF 132 SHEET OF 99 SIZE D A BOM Variants (continued from CSA 5) Bar Code Labels / EEEE #’s (continued from CSA 5) TABLE_BOMGROUP_HEAD BOM NUMBER BOM NAME BOM OPTIONS 639-3382 PCBA,2.3G,8G_ELP,VRAM_HYN,MLB_KEPLER,D2,DY41 BASE_BOM,CPU_IVY:2_3GHZ,FB_2G_HYNIX_A_DIE,EEEE:DY41,DEVEL_BOM,RAM_2G_ELPIDA_1600 639-3383 PCBA,2.3G,8G_ELP,VRAM_SAM,MLB_KEPLER,D2,DY42 BASE_BOM,CPU_IVY:2_3GHZ,FB_2G_SAMSUNG,EEEE:DY42,DEVEL_BOM,RAM_2G_ELPIDA_1600 639-3445 PCBA,2.3G,16G_ELP,VRAM_HYN,MLB_KEPLER,D2,DYJ5 BASE_BOM,CPU_IVY:2_3GHZ,FB_2G_HYNIX_A_DIE,EEEE:DYJ5,DEVEL_BOM,RAM_4G_ELPIDA_1600 639-3446 PCBA,2.3G,16G_ELP,VRAM_SAM,MLB_KEPLER,D2,DYJ6 BASE_BOM,CPU_IVY:2_3GHZ,FB_2G_SAMSUNG,EEEE:DYJ6,DEVEL_BOM,RAM_4G_ELPIDA_1600 PART NUMBER DESCRIPTION REFERENCE DES 825-7563 QTY LABEL,MLB/LIO,MBA [EEEE:DY41] CRITICAL CRITICAL BOM OPTION EEEE:DY41 825-7563 LABEL,MLB/LIO,MBA [EEEE:DY42] CRITICAL EEEE:DY42 825-7563 LABEL,MLB/LIO,MBA [EEEE:DYJ5] CRITICAL EEEE:DYJ5 825-7563 LABEL,MLB/LIO,MBA [EEEE:DYJ6] CRITICAL EEEE:DYJ6 825-7563 LABEL,MLB/LIO,MBA [EEEE:DRF0] CRITICAL EEEE:DRF0 825-7563 LABEL,MLB/LIO,MBA [EEEE:DRDP] CRITICAL EEEE:DRDP 825-7563 LABEL,MLB/LIO,MBA [EEEE:DRDT] CRITICAL EEEE:DRDT 825-7563 LABEL,MLB/LIO,MBA [EEEE:DRDQ] CRITICAL EEEE:DRDQ 825-7563 LABEL,MLB/LIO,MBA [EEEE:F0JD] CRITICAL EEEE:F0JD 825-7563 LABEL,MLB/LIO,MBA [EEEE:F0J3] CRITICAL EEEE:F0J3 825-7563 LABEL,MLB/LIO,MBA [EEEE:F0J4] CRITICAL EEEE:F0J4 825-7563 LABEL,MLB/LIO,MBA [EEEE:F0JC] CRITICAL EEEE:F0JC TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM 639-2818 PCBA,2.6G,8G_ELP,VRAM_HYN,MLB_KEPLER,D2,DRF0 BASE_BOM,CPU_IVY:2_6GHZ,FB_2G_HYNIX_A_DIE,EEEE:DRF0,DEVEL_BOM,RAM_2G_ELPIDA_1600 639-2820 PCBA,2.6G,8G_ELP,VRAM_SAM,MLB_KEPLER,D2,DRDP BASE_BOM,CPU_IVY:2_6GHZ,FB_2G_SAMSUNG,EEEE:DRDP,DEVEL_BOM,RAM_2G_ELPIDA_1600 639-2823 PCBA,2.6G,16G_ELP,VRAM_HYN,MLB_KEPLER,D2,DRDT BASE_BOM,CPU_IVY:2_6GHZ,FB_2G_HYNIX_A_DIE,EEEE:DRDT,DEVEL_BOM,RAM_4G_ELPIDA_1600 639-2819 PCBA,2.6G,16G_ELP,VRAM_SAM,MLB_KEPLER,D2,DRDQ BASE_BOM,CPU_IVY:2_6GHZ,FB_2G_SAMSUNG,EEEE:DRDQ,DEVEL_BOM,RAM_4G_ELPIDA_1600 639-3632 PCBA,2.7G,8G_ELP,VRAM_HYN,MLB_KEPLER,D2,F0JD BASE_BOM,CPU_IVY:2_7GHZ,FB_2G_HYNIX_A_DIE,EEEE:F0JD,DEVEL_BOM,RAM_2G_ELPIDA_1600 639-3633 PCBA,2.7G,8G_ELP,VRAM_SAM,MLB_KEPLER,D2,F0J3 BASE_BOM,CPU_IVY:2_7GHZ,FB_2G_SAMSUNG,EEEE:F0J3,DEVEL_BOM,RAM_2G_ELPIDA_1600 639-3630 PCBA,2.7G,16G_ELP,VRAM_HYN,MLB_KEPLER,D2,F0J4 BASE_BOM,CPU_IVY:2_7GHZ,FB_2G_HYNIX_A_DIE,EEEE:F0J4,DEVEL_BOM,RAM_4G_ELPIDA_1600 TABLE_BOMGROUP_ITEM D Elipda DQ’d Keeping for PRQ D TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM 639-3631 PCBA,2.7G,16G_ELP,VRAM_SAM,MLB_KEPLER,D2,F0JC BASE_BOM,CPU_IVY:2_7GHZ,FB_2G_SAMSUNG,EEEE:F0JC,DEVEL_BOM,RAM_4G_ELPIDA_1600 C C B B A SYNC_MASTER=D2_KEPLER SYNC_DATE=01/13/2012 PAGE TITLE BOM Variants DRAWING NUMBER Apple Inc 051-9589 REVISION R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED 4.18.0 BRANCH PAGE OF 132 SHEET OF 99 SIZE D A FUNC_TEST Functional Test Points FUNC_TEST I1596 TRUE I1597 TRUE I1599 D TRUE I1600 TRUE I1601 TRUE I1602 TRUE I1603 TRUE I1604 TRUE I1605 TRUE I1606 I1608 TRUE TRUE I1609 TRUE I1607 TRUE I1611 J3501 - airport FUNC_TEST AP_CLKREQ_Q_L 34 AP_RESET_CONN_L 34 PCIE_AP_D2R_PI_N 34 92 PCIE_AP_D2R_PI_P 34 92 PCIE_AP_R2D_N 34 92 PCIE_AP_R2D_P 34 92 PCIE_CLK100M_AP_CONN_N 34 96 PCIE_CLK100M_AP_CONN_P 34 96 PCIE_WAKE_L 18 34 PP3V3_S3RS4_BT_F 34 PP3V3_WLAN 34 42 USB_BT_CONN_N 34 91 USB_BT_CONN_P 34 91 WIFI_EVENT_L 34 41 42 GND 4X GND TRUE TRUE I1610 TRUE I1613 TRUE I1614 TRUE I1612 I1615 TRUE TRUE TRUE C TRUE I1618 TRUE I1619 TRUE I1617 TRUE I1621 TRUE I1620 TRUE I1623 TRUE I1624 TRUE I1622 TRUE I1625 TRUE I1626 TRUE I1628 TRUE I1629 TRUE I1627 TRUE I1631 TRUE I1630 TRUE I1633 TRUE I1634 TRUE I1632 TRUE I1635 TRUE HDMI_EG_CLK_C_N HDMI_EG_CLK_C_P HDMI_EG_DATA_C_N HDMI_EG_DATA_C_N HDMI_EG_DATA_C_N HDMI_EG_DATA_C_P HDMI_EG_DATA_C_P HDMI_EG_DATA_C_P PCIE_CLK100M_ENET_N PCIE_CLK100M_ENET_P PCIE_ENET_D2R_N PCIE_ENET_D2R_P PCIE_ENET_R2D_C_N PCIE_ENET_R2D_C_P USB3_EXTB_RX_N USB3_EXTB_RX_P USB3_EXTB_TX_C_N USB3_EXTB_TX_C_P USB_EXTB_N USB_EXTB_P GND TRUE TRUE TRUE I1659 TRUE I1657 TRUE I1661 TRUE I1660 TRUE I1663 TRUE B TRUE I1638 TRUE I1639 TRUE I1637 TRUE I1641 TRUE I1640 TRUE I1643 TRUE I1644 TRUE I1642 TRUE I1645 TRUE I1646 TRUE I1648 TRUE I1649 TRUE I1647 TRUE I1651 TRUE I1650 TRUE I1785 TRUE TRUE TRUE I1668 TRUE I1669 TRUE I1667 TRUE I1671 I1654 PP3V42_G3H SMC_LID_R GND TRUE TRUE I1670 TRUE I1673 TRUE 41 44 94 I1674 TRUE 34 91 I1672 34 91 TRUE I1683 TRUE I1793 TRUE FAN_LT_PWM FAN_LT_TACH PP5V_S0 GND TRUE TRUE I1676 TRUE I1678 TRUE I1679 TRUE 38 77 95 I1677 TRUE 38 77 95 I1681 TRUE TRUE 38 77 95 38 77 95 I1685 TRUE 38 77 95 I1686 TRUE 38 77 95 I1687 TRUE 38 77 95 I1689 TRUE 17 38 92 I1688 TRUE 17 38 92 I1691 TRUE 17 38 92 I1690 TRUE 17 38 92 I1692 TRUE 17 38 92 I1694 TRUE 17 38 92 I1693 TRUE 19 38 91 I1695 TRUE 19 38 91 I1799 TRUE 38 97 38 97 I1800 TRUE I1697 TRUE 26 38 91 I1797 TRUE 26 38 91 I1798 TRUE I1817 TRUE I1818 TRUE 19X GND TRUE TRUE I1682 TRUE I1795 TRUE FAN_RT_PWM FAN_RT_TACH PP5V_S0 GND TRUE TRUE J5100 - lpc + spi I1733 TRUE LPCPLUS_GPIO LPCPLUS_RESET_L LPC_AD LPC_AD LPC_AD LPC_AD LPC_CLK33M_LPCPLUS LPC_FRAME_L LPC_PWRDWN_L LPC_SERIRQ PM_CLKRUN_L PP5V_S0 SMC_RESET_L SMC_ROMBOOT SMC_RX_L SMC_TCK SMC_TDI SMC_TDO SMC_TMS SMC_TX_L SPIROM_USE_MLB SPI_ALT_CLK SPI_ALT_CS_L SPI_ALT_MISO SPI_ALT_MOSI TP_SMC_MD1 TP_SMC_TRST_L GND I1735 TRUE I1734 TRUE I1736 TRUE I1738 TRUE I1737 TRUE I1740 TRUE I1739 TRUE I1741 TRUE 20 43 25 43 17 41 43 82 92 17 41 43 82 92 17 41 43 82 92 17 41 43 82 92 25 43 92 17 41 43 82 92 Z2_CS_L Z2_DEBUG3 Z2_MOSI Z2_MISO Z2_SCLK Z2_HOST_INTN Z2_CLKIN Z2_KEY_ACT_L Z2_RESET PSOC_F_CS_L PICKB_L PP3V3_S4 PP5V_S5 PSOC_MISO PSOC_MOSI PSOC_SCLK SMBUS_SMC_2_S3_SCL SMBUS_SMC_2_S3_SDA GND TRUE 17 41 43 I1802 I1803 TRUE I1696 TRUE I1698 TRUE I1699 TRUE I1700 TRUE I1702 TRUE I1701 TRUE I1703 TRUE I1704 TRUE I1705 TRUE I1707 TRUE I1706 TRUE I1708 TRUE I1709 TRUE I1710 TRUE I1712 TRUE I1711 TRUE I1713 TRUE I1715 TRUE 42 48 48 3X P5V_S0 5X GND I1714 TRUE I1717 TRUE I1716 TRUE I1718 TRUE I1720 TRUE I1719 TRUE I1722 TRUE I1721 TRUE I1723 TRUE TRUE 18 41 43 I1743 TRUE A TRUE I1730 TRUE I1729 TRUE KBDLED_ANODE1 KBDLED_ANODE2 SMC_KBDLED_PRESENT_L GND TRUE 53 54 58 I1759 TRUE 53 54 58 I1760 TRUE 53 58 I1761 TRUE 59 I1763 TRUE TRUE 58 59 I1742 TRUE I1745 TRUE I1744 TRUE 41 42 43 61 42 43 41 42 43 TRUE I1746 TRUE 4X 58 I1762 TRUE I1764 TRUE I1766 TRUE I1765 TRUE I1768 TRUE 59 I1767 TRUE 59 I1769 TRUE 59 I1770 TRUE 59 I1771 TRUE I1773 TRUE I1772 TRUE I1774 TRUE I1775 TRUE 57 59 96 I1776 TRUE 57 59 96 I1777 TRUE 57 59 96 I1779 TRUE 57 59 96 I1778 TRUE I1780 TRUE 58 2X GND I1748 TRUE I1747 TRUE I1750 TRUE I1749 TRUE SPKRCONN_L_ID SPKRCONN_L_OUT_N SPKRCONN_L_OUT_P SPKRCONN_SL_OUT_N SPKRCONN_SL_OUT_P GND 41 42 43 41 42 43 20 43 52 43 43 TRUE 59 43 I1781 TRUE I1782 TRUE 43 J6803 - R speaker 43 43 2X GND 49 I1751 TRUE I1753 TRUE I1752 TRUE I1755 TRUE I1754 TRUE TRUE SPKRCONN_R_ID SPKRCONN_R_OUT_N SPKRCONN_R_OUT_P SPKRCONN_SR_OUT_N SPKRCONN_SR_OUT_P GND TRUE 49 DP_INT_AUX_N DP_INT_AUX_P DP_INT_ML_N DP_INT_ML_N DP_INT_ML_N DP_INT_ML_N DP_INT_ML_P DP_INT_ML_P DP_INT_ML_P DP_INT_ML_P LCD_FSS LCD_HPD_CONN LED_RETURN_1 LED_RETURN_2 LED_RETURN_3 LED_RETURN_4 LED_RETURN_5 LED_RETURN_6 PP5VR3V3_SW_LCD PPVOUT_S0_LCDBKLT GND 57 59 96 57 59 96 TRUE TRUE TRUE J6900 - DC PWR 49 I1756 TRUE 49 I1758 TRUE 49 I1757 TRUE ADAPTER_SENSE PP18V5_DCIN_FUSE TDM_ONEWIRE_MPM GND TRUE TRUE TRUE 60 2X 60 TRUE TRUE 60 2X GND TRUE TRUE 49 POWER RAILS 49 TRUE FUNC_TEST TRUE TRUE TRUE PM_SLP_S3_L TRUE PP0V75_S0_DDRVTT PP1V05_S0 49 49 TRUE 18 27 38 41 70 TRUE TRUE TRUE 49 41 44 94 2X GND PP1V8_S0 TRUE PP3V3_S0 96 TRUE PP3V3_S0GPU PP3V3_S3 TRUE PP3V3_S5 TRUE TRUE 49 TRUE TRUE 41 44 94 49 TRUE 49 TRUE 49 TRUE PP3V3_S5_AVREF_SMC PP3V42_G3H PP5V_S0 TRUE TRUE TRUE TRUE 96 TRUE 41 42 TRUE TRUE TRUE 49 TRUE 49 TRUE PP5V_S3 PP5V_S5 PPBUS_G3H PPDCIN_G3H 49 TRUE PPVCORE_GPU 49 TRUE PPVCORE_S0_CPU 49 TRUE PPVTTDDR_S3 8 TRUE TRUE TRUE TRUE TRUE 8X GND 81 95 81 95 TRUE TRUE 49 17 49 17 49 17 17 49 TP_PCIE_5_D2RN TP_PCIE_5_D2RP TP_PCIE_5_R2D_CN TP_PCIE_5_R2D_CP 81 95 18 81 95 18 81 95 18 81 95 18 81 95 18 81 95 18 81 82 18 81 18 81 86 18 81 86 18 81 86 17 81 86 17 81 86 17 3X 81 81 86 99 16X GND 84 93 84 93 35 84 93 19 35 84 93 19 35 84 93 35 84 93 84 93 84 93 85 93 85 93 35 85 93 35 85 93 35 85 93 35 85 93 17 85 93 17 85 93 35 77 95 35 77 95 35 95 35 95 35 83 95 35 83 95 49 35 95 35 95 35 77 95 35 77 95 35 95 17 35 95 17 35 83 95 17 35 83 95 17 35 95 17 35 95 17 17 MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE NC_PCIE_5_D2RN NC_PCIE_5_D2RP NC_PCIE_5_R2D_CN NC_PCIE_5_R2D_CP 17 17 17 17 MAKE_BASE=TRUE 49 17 49 17 49 17 49 17 TP_PCIE_6_D2RN TP_PCIE_6_D2RP TP_PCIE_6_R2D_CN TP_PCIE_6_R2D_CP TRUE TP_PCIE_7_D2RN TP_PCIE_7_D2RP TP_PCIE_7_R2D_CN TP_PCIE_7_R2D_CP TRUE TP_PCIE_8_D2RN TP_PCIE_8_D2RP TP_PCIE_8_R2D_CN TP_PCIE_8_R2D_CP TRUE TP_PCIE_PE5_D2RN TP_PCIE_PE5_D2RP TP_PCIE_PE5_R2D_CN TP_PCIE_PE5_R2D_CP TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE NC_PCIE_6_D2RN NC_PCIE_6_D2RP NC_PCIE_6_R2D_CN NC_PCIE_6_R2D_CP 49 17 49 17 49 17 49 17 MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE TRUE TRUE TRUE TRUE TRUE NO_TEST TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TP_CRT_IG_BLUE TP_CRT_IG_GREEN TP_CRT_IG_RED TP_CRT_IG_DDC_CLK TP_CRT_IG_DDC_DATA TP_CRT_IG_HSYNC TP_CRT_IG_VSYNC TP_LVDS_IG_CTRL_CLK TP_LVDS_IG_CTRL_DATA TP_PCH_LVDS_VBG TRUE NC_CRT_IG_BLUE NC_CRT_IG_GREEN NC_CRT_IG_RED NC_CRT_IG_DDC_CLK NC_CRT_IG_DDC_DATA NC_CRT_IG_HSYNC NC_CRT_IG_VSYNC NC_LVDS_IG_CTRL_CLK NC_LVDS_IG_CTRL_DATA NC_PCH_LVDS_VBG TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TP_HDA_SDIN1 TP_HDA_SDIN2 TP_HDA_SDIN3 TP_PCI_AD TP_PCI_C_BE_L TP_PCI_GNT3_L TP_PCI_GNT2_L TP_PCI_GNT1_L TP_PCI_GNT0_L TP_PCI_PAR TP_PCI_RESET_L TP_PCI_PME_L TP_PCI_CLK33M_OUT3 TP_PCH_NV_RCOMP TP_NV_DQ TP_NV_DQS TP_NV_CE_L TP_NV_ALE TP_NV_CLE TP_NV_RB_L TP_NV_WR_RE_L TP_NV_WE_CK_L TP_PCIE_CLK100M_PE4N TP_PCIE_CLK100M_PE4P TP_PCIE_CLK100M_PE5N TP_PCIE_CLK100M_PE5P TP_PCIE_CLK100M_PE6N TP_PCIE_CLK100M_PE6P TP_PCIE_CLK100M_PE7N TP_PCIE_CLK100M_PE7P TP_PSOC_P1_3 TP_SATA_B_D2RN TP_SATA_B_D2RP TP_SATA_B_R2D_CN TP_SATA_B_R2D_CP TP_SATA_D_D2RN TP_SATA_D_D2RP TP_SATA_D_R2D_CN TP_SATA_D_R2D_CP TP_SATA_E_D2RN TP_SATA_E_D2RP TP_SATA_E_R2D_CN TP_SATA_E_R2D_CP TP_SATA_F_D2RN TP_SATA_F_D2RP TP_SATA_F_R2D_CN TP_SATA_F_R2D_CP TP_SMC_P41 TRUE NC_HDA_SDIN1 TRUE MAKE_BASE=TRUE NC_HDA_SDIN2 TRUE MAKE_BASE=TRUE NC_HDA_SDIN3 TRUE MAKE_BASE=TRUE NC_PCI_AD TRUE MAKE_BASE=TRUE NC_PCI_C_BE_L TRUE MAKE_BASE=TRUE NC_PCI_GNT3_L TRUE MAKE_BASE=TRUE NC_PCI_GNT2_L TRUE MAKE_BASE=TRUE NC_PCI_GNT1_L TRUE MAKE_BASE=TRUE NC_PCI_GNT0_L TRUE MAKE_BASE=TRUE NC_PCI_PAR TRUE MAKE_BASE=TRUE NC_PCI_RESET_L TRUE MAKE_BASE=TRUE NC_PCI_PME_L TRUE MAKE_BASE=TRUE NC_PCI_CLK33M_OUT3 TRUE MAKE_BASE=TRUE NC_PCH_NV_RCOMP TRUE MAKE_BASE=TRUE NC_NV_DQ TRUE MAKE_BASE=TRUE NC_NV_DQS TRUE MAKE_BASE=TRUE NC_NV_CE_L TRUE MAKE_BASE=TRUE NC_NV_ALE TRUE MAKE_BASE=TRUE NC_NV_CLE TRUE MAKE_BASE=TRUE NC_NV_RB_L TRUE MAKE_BASE=TRUE NC_NV_WR_RE_L TRUE MAKE_BASE=TRUE NC_NV_WE_CK_L TRUE MAKE_BASE=TRUE NC_PCIE_CLK100M_PE4N TRUE MAKE_BASE=TRUE NC_PCIE_CLK100M_PE4P TRUE MAKE_BASE=TRUE NC_PCIE_CLK100M_PE5N TRUE MAKE_BASE=TRUE NC_PCIE_CLK100M_PE5P TRUE MAKE_BASE=TRUE NC_PCIE_CLK100M_PE6N TRUE MAKE_BASE=TRUE NC_PCIE_CLK100M_PE6P TRUE MAKE_BASE=TRUE NC_PCIE_CLK100M_PE7N TRUE MAKE_BASE=TRUE NC_PCIE_CLK100M_PE7P TRUE MAKE_BASE=TRUE NC_PSOC_P1_3 TRUE MAKE_BASE=TRUE NC_SATA_B_D2RN TRUE MAKE_BASE=TRUE NC_SATA_B_D2RP TRUE MAKE_BASE=TRUE NC_SATA_B_R2D_CN TRUE MAKE_BASE=TRUE NC_SATA_B_R2D_CP TRUE MAKE_BASE=TRUE NC_SATA_D_D2RN TRUE MAKE_BASE=TRUE NC_SATA_D_D2RP TRUE MAKE_BASE=TRUE NC_SATA_D_R2D_CN TRUE MAKE_BASE=TRUE NC_SATA_D_R2D_CP TRUE MAKE_BASE=TRUE NC_SATA_E_D2RN TRUE MAKE_BASE=TRUE NC_SATA_E_D2RP TRUE MAKE_BASE=TRUE NC_SATA_E_R2D_CN TRUE MAKE_BASE=TRUE NC_SATA_E_R2D_CP TRUE MAKE_BASE=TRUE NC_SATA_F_D2RN TRUE MAKE_BASE=TRUE NC_SATA_F_D2RP TRUE MAKE_BASE=TRUE NC_SATA_F_R2D_CN TRUE MAKE_BASE=TRUE NC_SATA_F_R2D_CP TRUE MAKE_BASE=TRUE NC_SMC_P41 TRUE MAKE_BASE=TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TP_HDMI_CEC 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 NC_PCIE_7_D2RN NC_PCIE_7_D2RP NC_PCIE_7_R2D_CN NC_PCIE_7_R2D_CP NO_TEST TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TP_DVPDATA TP_DVPCNTL_M TP_DVPCNTL TP_DVPCNTL NC_DVPDATA NC_DVPCNTL_M NC_DVPDATA NC_DVPDATA 17 49 17 2X GND 17 48 17 MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE 93 85 35 93 84 35 3X P5V_S0 5X GND TP_PCIE_PE6_D2RN TP_PCIE_PE6_D2RP TP_PCIE_PE6_R2D_CN TP_PCIE_PE6_R2D_CP 2X 50 2X 50 50 4X GND 93 84 35 93 84 35 TP SM BEAD-PROBE BP0733 SIGNAL_MODEL=EMPTY SM BEAD-PROBE BP0734 SIGNAL_MODEL=EMPTY SM BEAD-PROBE BP0735 SIGNAL_MODEL=EMPTY SM BEAD-PROBE BP0731 SIGNAL_MODEL=EMPTY SM BEAD-PROBE BP0732 SIGNAL_MODEL=EMPTY 35 35 MAKE_BASE=TRUE 35 TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE 35 NC_PCIE_PE5_D2RN NC_PCIE_PE5_D2RP NC_PCIE_PE5_R2D_CN NC_PCIE_PE5_R2D_CP 35 35 35 TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE 35 NC_PCIE_PE6_D2RN NC_PCIE_PE6_D2RP NC_PCIE_PE6_R2D_CN NC_PCIE_PE6_R2D_CP 35 TP_TBT_XTAL25OUT TP_TBT_PCIE_RESET0_L TP_TBT_PCIE_RESET1_L TP_TBT_PCIE_RESET2_L TP_TBT_PCIE_RESET3_L TP_DP_TBTSRC_ML_CP TP_DP_TBTSRC_ML_CN TP_DP_TBTSRC_AUXCH_CP TP_DP_TBTSRC_AUXCH_CN NO_TEST TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE 41 42 42 41 42 42 69 98 69 98 99 99 81 98 81 98 99 99 C NC_DP_IG_D_HPD TRUE MAKE_BASE=TRUE NC_DP_IG_D_CTRL_CLK TRUE MAKE_BASE=TRUE NC_DP_IG_D_CTRL_DATA TRUE MAKE_BASE=TRUE NC_DP_IG_D_MLP TRUE MAKE_BASE=TRUE NC_DP_IG_D_MLN TRUE MAKE_BASE=TRUE NC_DP_IG_D_AUXP TRUE MAKE_BASE=TRUE NC_DP_IG_D_AUXN TRUE MAKE_BASE=TRUE TP_SDVO_TVCLKINN TP_SDVO_TVCLKINP TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE NC_SDVO_TVCLKINN NC_SDVO_TVCLKINP TP_SDVO_STALLN TP_SDVO_STALLP TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE NC_SDVO_STALLN NC_SDVO_STALLP TP_SDVO_INTN TP_SDVO_INTP TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE NC_SDVO_INTN NC_SDVO_INTP 18 18 TP_GPU_BUFRST_L TP_GPU_GSTATE TP_GPU_GSTATE TP_GPU_MIOA_D TP_GPU_MIOA_DE NC_GPU_BUFRST_L TRUE MAKE_BASE=TRUE NC_GPU_GSTATE TRUE MAKE_BASE=TRUE NC_GPU_GSTATE TRUE MAKE_BASE=TRUE NC_GPU_MIOA_D TRUE MAKE_BASE=TRUE NC_GPU_MIOA_DE TRUE MAKE_BASE=TRUE TP_LVDS_EG_BKL_PWM LVDS_IG_B_CLK_N LVDS_IG_B_CLK_P LVDS_IG_BKL_PWM NC_LVDS_EG_BKL_PWM TRUE MAKE_BASE=TRUE NC_LVDS_IG_B_CLKN TRUE MAKE_BASE=TRUE NC_LVDS_IG_B_CLKP TRUE MAKE_BASE=TRUE NC_LVDS_IG_BKL_PWM TRUE MAKE_BASE=TRUE B NC_TBT_XTAL25OUT NC_TBT_PCIE_RESET0_L NC_TBT_PCIE_RESET1_L NC_TBT_PCIE_RESET2_L NC_TBT_PCIE_RESET3_L NC_DP_TBTSRC_ML_CP NC_DP_TBTSRC_ML_CN NC_DP_TBTSRC_AUXCH_CP NC_DP_TBTSRC_AUXCH_CN TRUE TRUE TRUE MAKE_BASE=TRUE TRUE TRUE TRUE TRUE TRUE TP_PCIE_PE7_D2RN TP_PCIE_PE7_D2RP TP_PCIE_PE7_R2D_CN TP_PCIE_PE7_R2D_CP TRUE TP_PCIE_PE8_D2RN TP_PCIE_PE8_D2RP TP_PCIE_PE8_R2D_CN TP_PCIE_PE8_R2D_CP TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE NC_SMC_BS_ALRT_L MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE PCH_VSS_NCTF PCH_VSS_NCTF PCH_VSS_NCTF PCH_VSS_NCTF PCH_VSS_NCTF PCH_VSS_NCTF PCH_VSS_NCTF PCH_VSS_NCTF SYNC_MASTER=D2_KEPLER 7 SYNC_DATE=01/13/2012 PAGE TITLE NC_PCIE_PE7_D2RN NC_PCIE_PE7_D2RP NC_PCIE_PE7_R2D_CN NC_PCIE_PE7_R2D_CP Functional / ICT Test NC_LPC_DREQ0_L MAKE_BASE=TRUE TP_LPC_DREQ0_L DRAWING NUMBER 17 TRUE Apple Inc 17 MAKE_BASE=TRUE MAKE_BASE=TRUE TRUE TRUE PCH_VSS_NCTF PCH_VSS_NCTF PCH_VSS_NCTF PCH_VSS_NCTF PCH_VSS_NCTF PCH_VSS_NCTF PCH_VSS_NCTF PCH ALIASES 17 NC_PCIE_PE8_D2RN NC_PCIE_PE8_D2RP NC_PCIE_PE8_R2D_CN NC_PCIE_PE8_R2D_CP 17 17 17 TP_CLINK_CLK TP_CLINK_DATA TP_CLINK_RESET_L TP_PCIE_CLK100M_PEBN TP_PCIE_CLK100M_PEBP TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE 26 26 Thunderbolt NO_TESTs NC_PCIE_8_D2RN NC_PCIE_8_D2RP NC_PCIE_8_R2D_CN NC_PCIE_8_R2D_CP MAKE_BASE=TRUE TP TP 26 NC_HDMI_CEC TRUE MAKE_BASE=TRUE SMC_BS_ALRT_L MAKE_BASE=TRUE 48 TP TP 26 MAKE_BASE=TRUE 49 PLACEABLE BEAD-PROBES FOR TBT TBT_B_R2D_C_P TBT_B_R2D_C_P TBT_A_R2D_C_P TBT_A_D2R_P TBT_A_D2R_N 26 TP_DP_IG_D_HPD TP_DP_IG_D_CTRL_CLK TP_DP_IG_D_CTRL_DATA TP_DP_IG_D_MLP TP_DP_IG_D_MLN TP_DP_IG_D_AUXP TP_DP_IG_D_AUXN MAKE_BASE=TRUE 93 85 35 26 NC_DP_IG_C_HPD TRUE MAKE_BASE=TRUE NC_DP_IG_C_CTRL_CLK TRUE MAKE_BASE=TRUE NC_DP_IG_C_CTRL_DATA TRUE MAKE_BASE=TRUE NC_DP_IG_C_MLP TRUE MAKE_BASE=TRUE NC_DP_IG_C_MLN TRUE MAKE_BASE=TRUE NC_DP_IG_C_AUXP TRUE MAKE_BASE=TRUE NC_DP_IG_C_AUXN TRUE MAKE_BASE=TRUE 18 D TP_DP_IG_C_HPD TP_DP_IG_C_CTRL_CLK TP_DP_IG_C_CTRL_DATA TP_DP_IG_C_MLP TP_DP_IG_C_MLN TP_DP_IG_C_AUXP TP_DP_IG_C_AUXN GPU NO_TESTs MAKE_BASE=TRUE 49 TRUE 81 86 17 TRUE TRUE 81 95 NO_TEST 49 TRUE NC NO_TESTs NC NO_TESTs 49 NC_TP_CPU_RSVD NC_TP_CPU_RSVD NC_TP_CPU_RSVD NC_TP_CPU_RSVD NC_TP_CPU_RSVD NC_TP_CPU_RSVD NC_TP_CPU_RSVD_NCTF TRUE 81 95 TBT_A_D2R_C_P TBT_A_D2R_C_N TBT_A_D2R_P TBT_A_D2R_N TBT_A_R2D_C_P TBT_A_R2D_C_N TBT_A_R2D_P TBT_A_R2D_N TBT_B_D2R_C_P TBT_B_D2R_C_N TBT_B_D2R_P TBT_B_D2R_N TBT_B_R2D_C_P TBT_B_R2D_C_N TBT_B_R2D_P TBT_B_R2D_N DP_TBTSNK0_ML_C_P DP_TBTSNK0_ML_C_N DP_TBTSNK0_ML_P DP_TBTSNK0_ML_N DP_TBTSNK0_AUXCH_C_P DP_TBTSNK0_AUXCH_C_N DP_TBTSNK0_AUXCH_P DP_TBTSNK0_AUXCH_N DP_TBTSNK1_ML_C_P DP_TBTSNK1_ML_C_N DP_TBTSNK1_ML_P DP_TBTSNK1_ML_N DP_TBTSNK1_AUXCH_C_P DP_TBTSNK1_AUXCH_C_N DP_TBTSNK1_AUXCH_P DP_TBTSNK1_AUXCH_N 49 NC_SMC_FAN_3_TACH NC_SMC_FAN_3_CTL NC_SMC_FAN_2_TACH NC_SMC_FAN_2_CTL NC_FW2_TPBP NC_FW2_TPBN NC_FW2_TPBIAS NC_FW2_TPAP NC_FW2_TPAN NC_FW0_TPBP NC_FW0_TPBN NC_FW0_TPAP NC_ESTARLDO_EN NC_ALS_GAIN NC_USB_HUB_PRTPWR2 NC_USB_HUB_PRTPWR3 NC_USB_HUB_PRTPWR4 NC_USB_HUB_OCS2 NC_USB_HUB_OCS3 NC_USB_HUB_OCS4 NC_SMC_XOSC1 NC_SMC_ODD_DETECT NC_SMC_SYS_LED NC_SMC_HIB_L NC_SMBUS_SMC_4_ASF_SDA NC_SMBUS_SMC_4_ASF_SCL NC_SMC_T25_EN_L NC_SMC_T25_ISENSE NC_ISNS_P1V5R1V35_CPUDDRP NC_ISNS_P1V5R1V35_CPUDDRN NC_ISNS_LCDBKLTP NC_ISNS_LCDBKLTN NC_ISNS_LCD_PANELP NC_ISNS_LCD_PANELN NC_ISNS_AIRPORTP NC_ISNS_AIRPORTN TRUE NO_TEST TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TP_CPU_RSVD TP_CPU_RSVD TP_CPU_RSVD TP_CPU_RSVD TP_CPU_RSVD TP_CPU_RSVD TP_CPU_RSVD_NCTF 60 NC NO_TESTs NO_TEST TRUE 41 44 57 59 96 TRUE CPU NO_TESTs NO_TEST=TRUE 57 59 96 61 59 49 49 8X 60 41 44 J9000 - eDP 96 J6802 - L speaker 41 42 43 PPVBAT_G3H_CONN SMBUS_SMC_5_G3_SCL SMBUS_SMC_5_G3_SDA SYS_DETECT_L GND 58 41 42 43 41 42 43 ICT Test Points J6950 - battery 4X 58 CON_DMIC_CLK CON_DMIC_PWR CON_DMIC_SDA1 CON_DMIC_SDA2 GND J5815 - kbd backlight I1728 AUD_HP_PORT_L AUD_HP_PORT_R AUD_SPDIF_OUT_JACK AUD_TIPDET_INV AUD_TYPEDET CH_HS_GND CH_HS_MIC PP3V3_S0 US_HS_GND US_HS_MIC GND J6801 - 3-mic TRUE PP3V3_S4 PP3V42_G3H WS_CONTROL_KBD WS_KBD1 WS_KBD10 WS_KBD11 WS_KBD12 WS_KBD13 WS_KBD14 WS_KBD15_CAP WS_KBD16_NUM WS_KBD17 WS_KBD18 WS_KBD19 WS_KBD2 WS_KBD20 WS_KBD21 WS_KBD22 WS_KBD23 WS_KBD3 WS_KBD4 WS_KBD5 WS_KBD6 WS_KBD7 WS_KBD8 WS_KBD9 WS_KBD_ONOFF_L WS_LEFT_OPTION_KBD WS_LEFT_SHIFT_KBD GND FUNC_TEST 18 25 41 43 J5713 - keyboard TRUE 8 I1731 J5700 - ipd flex 38 77 95 J5660 - right fan I1684 TRUE I1675 J5650 - left fan I1680 TRUE 41 44 94 34 ENET_CLKREQ_L 17 38 ENET_RESET_L 25 HDMI_EG_DDC_CLK 38 77 HDMI_EG_DDC_DATA 38 77 HDMI_HPD_L 38 42 82 I2C_DPMUX_A_SCL 44 I2C_DPMUX_A_SDA 44 PM_SLP_S3_L 18 27 38 41 70 PM_SLP_S4_L 18 27 34 38 40 41 70 PP1V5_S0_RIO PP3V3_S3 3X P3V3_S3 PP3V3_S4 PP5V_S4 5X P5V_S4 SDCONN_STATE_CHANGE_RIO 25 38 SD_PWR_EN 38 USB_EXTB_OC_L 24 38 GND 10X GND TRUE TRUE I1666 J5050 - hall effect I1653 TRUE I1665 J4410 - rio flex I1636 TRUE I1658 I1662 J4400 - rio coax I1616 TRUE I1655 I1664 J3502 - ALS camera PP5V_S3_ALSCAMERA_F SMBUS_SMC_2_S3_SCL SMBUS_SMC_2_S3_SDA USB_CAMERA_CONN_N USB_CAMERA_CONN_P GND I1652 I1656 J6701 - audio flex NC_CLINK_CLK NC_CLINK_DATA NC_CLINK_RESET_L NC_PCIE_CLK100M_PEBN NC_PCIE_CLK100M_PEBP 051-9589 REVISION R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED 4.18.0 BRANCH PAGE OF 132 SHEET OF 99 SIZE D A 61 60 =PPBUS_G3H PPBUS_G3H G3H Rails MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm =PPBUS_S0_LCDBKLT =PPVIN_S5_HS_OTHER_ISNS_R 46 46 46 D 46 =PPVIN_S5_HS_GPU_ISNS 64 =PP18V5_DCIN_CONN 60 =PP18V5_DCIN_ISOL MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM 60 =PP3V42_G3H_REG C =PP3V42_G3H_AUDIO =PP3V42_G3H_TDM =PP3V42_S3_HALL 58 60 42 For PCH RTC Power =PPVRTC_G3_OUT 25 5V Rails =PP5V_S5_LDO 61 45 PP3V42_G3H VOLTAGE=3.42V MAKE_BASE=TRUE =PP3V3_S5_LPCPLUS =PP3V3_S5_SMC =PP3V42_G3H_CHGR =PP3V42_G3H_ONEWIREPROT =PP3V42_G3H_PWRCTL =PP3V42_G3H_SMBUS_SMC_5 =PP3V42_G3H_SMCUSBMUX =PP3V42_G3H_TPAD =PPVIN_S5_SMCVREF =PPVBAT_G3_SYSCLK 43 41 42 78 61 70 60 70 44 40 49 42 25 69 =PP5V_S3_FET =PPVRTC_G3_PCH VOLTAGE=5V MAKE_BASE=TRUE 69 69 49 PP5V_SUS VOLTAGE=5V MAKE_BASE=TRUE 23 PP5V_S4 VOLTAGE=5V MAKE_BASE=TRUE =PP5V_S4_RIO =PP5V_S4_P5VS0FET =PP5V_S4_P5VS3FET =PP5V_S0_LCD =PP5V_S3_LTUSB =PP5V_S4_ISNS =PP5V_S4_TPAD =PP5V_S4_AUDIO PP5V_S3 38 69 69 81 40 49 53 59 VOLTAGE=5V MAKE_BASE=TRUE =PP5V_S3_ISNS =PP5V_S3_ALSCAMERA =PP5V_S3_DDRREG =PP5V_S0_FET 99 34 64 =PP5V_S3_DEBUG_ADC_AVDD =PP5V_S3_DEBUG_ADC_DVDD =PP5V_S3_DEBUG_ISNS =PP5V_S3_MEMRESET PP5V_S0 =PP5V_S0_P1V5_LDO 3.3V Rails A 69 =PP3V3_S4_FET 36 =PP3V3_S4_TBT_R 38 =PP3V3_S4_RIO 69 =PP3V3_SUS_FET =PP5V_S0GPU_P1V0P1V35_GPU =PP5V_S0_AUDIO_XW =PP5V_S0_BKL =PP5V_S0_CPUIMVP =PP5V_S0_CPUVCCIOS0 =PP5V_S0_FAN_LT =PP5V_S0_FAN_RT =PP5V_S0_GFXIMVP =PP5V_S0_KBDLED =PP5V_S0_LPCPLUS =PP5V_S0_PCH =PP5V_S0_PCHVCCIOS0 =PP5V_S0_RMC =PP5V_S0_VCCSAS0 =PP5V_S0_VMON PP3V3_S4 MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.1 MM 52 =PP3V3_SUS_ROM =PP3V3_SUS_PCH_VCC_SPI 98 98 =PP3V3_S4_TBTBPWRSW 85 PP3V3_S3 74 86 65 66 67 48 48 80 50 43 23 25 =PP3V3_S3_BT =PP3V3_S3_DPMUX_UC =PP3V3_S3_ISNS =PP3V3_S3_MEMRESET =PP3V3_S3_PCH_GPIO =PP3V3_S3_RIO =PP3V3_S3_SMBUS_SMC_2_S3 =PP3V3_S3_SMBUS_SMC_3 =PP3V3_S3_TPAD =PP3V3_S3_USBMUX =PP3V3_S3_USB_HUB =PP3V3_S3_USB_RESET =PP3V3_S3_VREFMRGN =PP3V3_S3_WLAN =PP3V3_S3_GYRO =PP3V3_S3_SMS =PP3V3_S3_SDBUF PP3V3_S0 87 37 =PP3V3_TBTLC_FET 70 =PP1V05_TBTLC_FET =PP1V5_S3RS0_FET_ISNS 69 27 38 44 =PP1V5_S0_REG 68 26 VOLTAGE=3.3V 68 21 23 =PP3V3_SUS_PCH_VCCSUS_GPIO 21 23 =PP3V3_SUS_PCH_GPIO 17 18 19 20 =PP3V3_SUS_PCH_VCCSUS_USB 21 23 =PP1V05_TBTCIO_FET 71 77 78 79 20 21 23 25 69 =PP3V3_S0GPU_MISC_FET PP3V3_S0GPU_MISC 68 MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.10MM VOLTAGE=3.3V MAKE_BASE=TRUE VOLTAGE=1.8V MAKE_BASE=TRUE D =PP3V3_GPU_MISC PP1V5R1V35_S3 77 27 33 69 64 45 PP1V5R1V35_MEM 28 29 30 31 PP1V5_S3RS0_CPUDDR 96 70 TP_P1V8GPU_EN 88 74 33 =PP1V5_S0_AUDIO 34 =PP3V3R1V5_S0_PCH_VCCSUSHDA 21 23 25 PP1V5_S0_RIO 51 =PP1V5_S0_RIO_LDO 68 51 MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM 25 96 =PPVTT_S3_DDR_BUF 64 33 =P1V8GPU_EN 11 14 16 27 PP1V5_S0 26 PP1V5R1V35_S0GPU =PP1V5R1V35_GPU_REG MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.5V MAKE_BASE=TRUE 53 =PP1V5_S0_RIO 38 PPVTTDDR_S3 C =PP1V35_GPU_FBVDDQ =PP1V35_GPU_S0_FB VOLTAGE=1.5V MAKE_BASE=TRUE 72 75 76 73 MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=0.75V MAKE_BASE=TRUE 59 53 58 =PPVTT_S0_DDR_LDO 64 PP0V75_S0_DDRVTT 88 TP_GPU_PGOOD2 =PP1V8_GPU_FET MIN_LINE_WIDTH=2 mm MIN_NECK_WIDTH=0.17 mm VOLTAGE=0.75V MAKE_BASE=TRUE 86 47 13 82 83 44 35 78 82 68 =PP1V05_SUS_LDO MAKE_BASE=TRUE =PP0V75_S0_MEM_VTT_A =PP0V75_S0_MEM_VTT_B =PPVTT_S0_VTTCLAMP PP1V05_SUS 32 32 74 PP1V0_S0GPU_ISNS =PP1V05_S0GPU_REG 27 MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM 48 47 46 67 =PPCPUVCCIO_S0_REG =PP1V05_SUS_PCH_JTAG PP1V05_S0 24 MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V MAKE_BASE=TRUE 46 45 98 99 81 =PP1V05_S0_CPU_VCCIO 17 23 17 18 19 20 25 37 23 77 77 73 79 77 79 10 11 13 14 15 =PPVCCIO_S0_XDP =PPVCCIO_S0_CPUIMVP =PPVCCIO_S0_SMC =PP1V05_S0_VMON =PP1V05_S0_RMC 37 VOLTAGE=1.05V MAKE_BASE=TRUE =PP1V0_GPU_DPLL =PP1V0_GPU_DP_AB =PP1V0_GPU_DP_CD =PP1V05_GPU_IFPCD_IOVDD =PP1V05_GPU_IFPEF_IOVDD =PP1V05_GPU_PEX_IOVDD =PP1V05_GPU_PEX_PLLVDD MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V MAKE_BASE=TRUE 48 24 45 =PPVCORE_GPU_REG PPVCORE_GPU MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM 65 42 VOLTAGE=1.0V MAKE_BASE=TRUE =PPVCORE_GPU 72 79 =PPVCORE_S0_GFX_REG 80 70 98 21 23 87 =PPPCHVCCIO_S0_REG 21 23 21 23 23 70 88 25 39 25 70 44 44 44 39 25 37 50 70 47 24 MIN_NECK_WIDTH=0.15 MM MAKE_BASE=TRUE 20 PP1V05_PCHVCCIO_S0 MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V MAKE_BASE=TRUE =PP1V05_S0_PCH_VCCIO_PLLPCIE =PP1V05_S0_PCH_VCCADPLL =PP1V05_S0_PCH_VCCIO =PP1V05_S0_PCH_VCCIO_PCIE =PP1V05_S0_PCH_VCCIO_SATA =PP1V05_S0_PCH_VCCIO_CLK =PP1V05_S0_PCH_VCCIO_USB =PP1V05_S0_PCH_VCC_CORE =PP1V05_S0_PCH_VCCASW =PP1V05_S0_PCH_VCCIO_CLK =PP1V05_S0_PCH_VCCDIFFCLK =PP1V05_S0_PCH =PP1V05_S0_PCH_VCCSSC =PP1V05_S0_PCH_V_PROC_IO =PP1V05_S0_PCH_VCCIO_PLLUSB =PP1V05_S0_PCH_VCC_DMI =PP1V05_S0_PCH_VCCIO_PLLFDI =PP1V05_S0_PCH_VCCDMI_FDI =PP1V05_S0_P1V05TBTFET_R GND 21 =LVDS_VCCA 23 MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.085MM VOLTAGE=0V 21 23 MAKE_BASE=TRUE 21 18 17 21 23 Chipset "VCore" Rails 21 23 21 23 66 =PPVCORE_S0_CPU_REG PPVCORE_S0_CPU MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM 21 23 MAKE_BASE=TRUE VOLTAGE=1.25V =PPVCORE_S0_CPU 21 23 21 23 66 45 =PPVCORE_S0_AXG_REG 13 15 45 98 PPVCORE_S0_AXG MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM 17 21 23 17 23 MAKE_BASE=TRUE VOLTAGE=1.05V =PPVCORE_S0_CPU_VCCAXG 13 14 16 21 23 16 13 21 23 =PP1V5_S3_CPU_VCCDQ PP1V5_S3_CPU_VCCDQ MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM 21 21 23 15 13 =PP1V05_S0_CPU_VCCPQE 99 62 =PPVCCSA_S0_REG PP1V05_S0_CPU_VCCPQE MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM 21 21 MAKE_BASE=TRUE VOLTAGE=1.5V VOLTAGE=1.05V MAKE_BASE=TRUE PPVCCSA_S0_REG MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM 99 VOLTAGE=0.9V MAKE_BASE=TRUE =PPVCCSA_S0_CPU 13 16 Defined here since TBT page does not know PBUS voltage PPVIN_SW_TBTBST 37 I1679 25 VOLTAGE=12.8V 35 36 37 SYNC_DATE=01/13/2012 PAGE TITLE 37 VOLTAGE=1.05V MAKE_BASE=TRUE Power Aliases Backlight Rails 99 36 =PPBUS_SW_BKL PPBUS_SW_BKL DRAWING NUMBER MIN_LINE_WIDTH=0.5 MM MAKE_BASE=TRUE MIN_NECK_WIDTH=0.25 MM VOLTAGE=12.6V PPBUS_S0_LCDBKLT_PWR VOLTAGE=1.05V MAKE_BASE=TRUE Apple Inc 86 051-9589 REVISION R =PP1V05_TBTCIO_RTR 36 41 SMC_T25_EN_L NC_SMC_T25_EN_L NOTICE OF PROPRIETARY PROPERTY: 4.18.0 BRANCH MAKE_BASE=TRUE 37 =PP15V_TBT_REG PP15V_TBT MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=15V MAKE_BASE=TRUE =PPHV_SW_TBTAPWRSW =PPHV_SW_TBTBPWRSW 70 42 B 21 23 PP1V05_TBTCIO MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM =PP3V3_SUS_PCH_VCCSUS =PP3V3_SUS_CNTRL =PP3V3_SUS_SMC =PP1V8_S0_PCH_VCC_DFTERM =PPVDDIO_S0_SBCLK =PP1V8_S0_P1V5_LDO PP1V8_S0_CPU_VCCPLL_R MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.5V MAKE_BASE=TRUE 26 =PP1V05_TBTLC_RTR 37 MIN_NECK_WIDTH=0.2 MM 80 23 =PP1V5_S3RS0_VMON =PP1V5_S3_CPU_VCCDDR 44 34 MAKE_BASE=TRUE 77 MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.5V MAKE_BASE=TRUE 19 25 PP1V05_TBTLC MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM 25 42 PP3V3_SUS MIN_LINE_WIDTH=0.6 MM =PP3V3_GPU_IFPX_PLLVDD =PP3V3_S0_GFX3V3BIAS =PP3V3_GPU_VDD33 15 SYNC_MASTER=D2_KEPLER 37 49 =PP3V3_S4_BT VOLTAGE=3.3V 99 VOLTAGE=3.3V MAKE_BASE=TRUE =PP3V3_TBT_PCH_GPIO =PPVDDIO_TBT_CLK =PP3V3_TBTLC_RTR 62 21 =PP1V5R1V35_S3_MEM_A =PP1V5R1V35_S3_MEM_B 34 82 PP3V3_TBTLC MIN_LINE_WIDTH=0.4 MM 98 PP3V3_S0GPU MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.17 mm VOLTAGE=1.5V MAKE_BASE=TRUE TBT RAILS VOLTAGE=3.3V MAKE_BASE=TRUE =PP3V3_S4_SMC =PPVIN_S3_MEM_ISNS 45 VOLTAGE=3.3V MAKE_BASE=TRUE =PP3V3_S0_SB_PM =PP3V3_S0_SMBUS_PCH =PP3V3_S0_SMBUS_SMC_0_S0 =PP3V3_S0_SMBUS_SMC_1_S0 =PP3V3_S0_SSD =PP3V3_S0_SYSCLK =PP3V3_S0_TBTI2C =PP3V3_S0_TBTPWRCTL =PP3V3_S0_TPAD =PP3V3_S0_VMON =PP3V3_S0_X29THMSNS =PP3V3_S0_XDP =PP3V3_S0_DDR3THMSNS =PP3V3_S0_SPKRTHMSNS 27 =PP3V3_S4_TPAD =PP3V3_SUS_P1V05SUSLDO 23 21 98 VOLTAGE=5V MAKE_BASE=TRUE MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM 68 24 =PP3V3_S0_AUDIO =PP3V3_S0_AUDIO_DIG =PP3V3_S0_BKL_VDDIO =PP3V3_S0_CPUTHMSNS =PP3V3_S0_CPU_VCCIO_SEL =PP3V3_S0_DPMUX =PP3V3_S0_DPMUXI2C =PP3V3_S0_DPMUX_UC =PP3V3_S0_FAN_LT =PP3V3_S0_FAN_RT =PP3V3_S0_GPUTHMSNS =PP3V3_S0_HS_ISNS =PP3V3_S0_IMVPISNS =PP3V3_S0_ISNS =PP3V3_S0_LCD =PP3V3_S0_P1V8GPUFET =PP3V3_S0_P3V3TBTFET =PP3V3_S0_PCH =PP3V3_S0_PCH_GPIO =PP3V3_S0_PCH_VCC3_3_CLK =PP3V3_S0_PCH_VCC3_3_GPIO =PP3V3_S0_PCH_VCC3_3_HVCMOS =PP3V3_S0_PCH_VCC3_3_PCI =PP3V3_S0_PCH_VCC3_3_SATA =PP3V3_S0_PCH_VCCADAC =PP3V3_S0_PWRCTL =PP3V3_S0_RSTBUF =PP3V3_S0_SATAMUX 17 18 21 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm 69 =PP3V3_S0_FET VOLTAGE=3.42V MAKE_BASE=TRUE PP5V_S5 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm B 70 84 =PP3V3_S0GPU_FET MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.10MM VOLTAGE=3.3V MAKE_BASE=TRUE =PP1V5_S3_MEMRESET =PPDDR_S3_MEMVREF =PPVIN_S3_P1V5S3RS0_FET =PPVIN_S0_DDRREG_LDO =PPVIN_S3_MEM_ISNS_R 25 =PP3V3_S4_TBTAPWRSW "GPU" Rails 88 69 MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.17 mm VOLTAGE=1.5V MAKE_BASE=TRUE 42 MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.075 mm =PP5V_SUS_PCH =PP5V_S4_REG 69 PPVRTC_G3H =PPDDR_S3_REG 64 =PP3V3_S5_XDP MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM 18 70 MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM VOLTAGE=18.5V MAKE_BASE=TRUE MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM 63 =PP3V3_S3_FET =PP1V8_S0_CPU_VCCPLL_R 15 13 =PP3V3_S5_VMON 69 =PP5V_S5_P1V5S3RS0FET =PP5V_S5_P5VSUSFET =PP5V_S5_TPAD =PP5V_SUS_FET 69 70 63 MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.1 MM 69 68 =PP3V3_S5_PWRCTL 61 MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.2 MM 63 68 =PP3V3_S5_SMCBATLOW =PP3V3_S5_SYSCLK PP1V8_S0 MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.5V MAKE_BASE=TRUE =PP1V8_S0_PCH_VCCTX_LVDS 27 80 MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.2 MM 69 20 =PP1V8R1V5_S0_PCH_VCCVRM =PP1V8_S0_AUDIO =PP1V8_S0_CPU_VCCPLL =PP1V8_S0_GPUFET 69 21 23 VOLTAGE=18.5V MAKE_BASE=TRUE =PPDCIN_S5_CHGR_ISOL =PPDCIN_S5_VSENSE 69 =PP3V3_S5_PCH_VCCDSW VOLTAGE=12.8V MAKE_BASE=TRUE =PPDCIN_S5_CHGR PPDCIN_G3H_ISOL 4A max supply 69 =PP3V3_S5_PCH_GPIO 74 =PPVIN_S5_P5VP3V3 PPDCIN_G3H =PP1V8_S0_REG 68 87 PPVIN_S5_HS_OTHER_ISNS MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM 1.8V/1.5V/1.2V/1.05V Rails 69 62 VOLTAGE=12.8V MAKE_BASE=TRUE MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm 60 =PP3V3_S5_PCHPWRGD 65 66 PPVIN_S5_HS_GPU_ISNS MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm =PPVIN_S5_HS_OTHER_ISNS 66 VOLTAGE=12.8V MAKE_BASE=TRUE =PPVIN_S0_GFXIMVP =PPVIN_S0GPU_P1V5P1V0 46 67 =PP3V3_S4_DPBPWRSW =PP3V3_S4_P3V3S4FET =PP3V3_S5_CPU_VCCDDR =PP3V3_S5_P1V2P1V8 =PP3V3_S5_P1V5S0 =PP3V3_S5_P3V3SUSFET =PP3V3_S5_PCH 45 =PPVIN_S0_CPUIMVP =PPVIN_S3_DDRREG =PPVIN_S0_CPUVCCIOS0 =PPVIN_S0_CPUAXG =PPVIN_S0_VCCSAS0 =PPVIN_S0_PCHVCCIOS0 96 VOLTAGE=3.3V MAKE_BASE=TRUE =PP3V3_S4_DPAPWRSW 37 PPVIN_S5_HS_COMPUTING_ISNS MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm PP3V3_S5 =PP3V3_GPU_P3V3GPUFET =PP3V3_GPU_MISC_P3V3GPUMISCFET =PP3V3_S0_P3V3S0FET =PP3V3_S3_P3V3S3FET 86 =PPVIN_S5_HS_GPU_ISNS_R =PPVIN_SW_TBTBST =PPBUS_S0_VSENSE =PPBUS_G3H_T25_R =PPVIN_S5_HS_COMPUTING_ISNS =PP3V3_S5_REG MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM =PPVIN_S5_HS_COMPUTING_ISNS_R 46 63 VOLTAGE=12.8V MAKE_BASE=TRUE 84 99 37 =PP1V05_S0_P1V05TBTFET PP1V05_S0_P1V05TBTFET MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM 85 VOLTAGE=1.05V MAKE_BASE=TRUE THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED PAGE OF 132 SHEET OF 99 SIZE D A Frame Holes ZT0915 T29 / GMUX JTAG Signals GND_BATT_CHGND ZT0970 TH-NSP GND_CHASSIS_MLBCAN1 ZT0950 TH-NSP GND_CHASSIS_FAN ZT0974 TH-NSP =DDRVTT_EN TBT_LSOE ZT0972 TH-NSP TBT_LSOE TBT_LSEO_LSOE3 TBT_LSEO Unused PEG signals NC_PEG_D2R_P =PEG_D2R_P NO_TEST=TRUE TBT_LSEO_LSOE2 TBT_LSEO MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE EG_RESET_L 82 GPU_RESET_L 71 78 IG_BKLT_EN 82 SL-1.1X0.45-1.4x0.75 18 LVDS_IG_BKL_ON 18 LVDS_IG_PANEL_PWR THERMAL MODULE STANDOFFS EG_CLKREQ_IN_L 78 82 EG_CLKREQ_OUT_L 82 82 SH0920 SH0927 SH0926 STDOFF-4.5OD2.15H-SM STDOFF-4.5OD2.15H-SM STDOFF-4.5OD2.15H-SM DP_TBTSNK0_HPD_IG PCIE_TBT_D2R_P 92 35 PCIE_TBT_D2R_N 82 STDOFF-4.5OD1.8H-SM 92 35 PCIE_TBT_R2D_C_P 92 35 PCIE_TBT_R2D_C_N DPB_IG_HPD STDOFF-4.5OD2.15H-SM SH0929 STDOFF-4.5OD2.15H-SM 17 SH0923 17 STDOFF-4.5OD1.8H-SM 17 92 17 92 17 =PEG_R2D_C_P 10 =PEG_R2D_C_N 10 NC_LVDS_IG_A_CLK_N PEG_D2R_P PEG_D2R_N 10 MAKE_BASE=TRUE =PEG_D2R_N 10 MAKE_BASE=TRUE PEG_R2D_C_P 89 71 PEG_R2D_C_N =PEG_R2D_C_P 10 =PEG_R2D_C_N 10 TRUE MAKE_BASE=TRUE PCIE_CLK100M_EXCARD_P NC_PCIE_CLK100M_EXCARD_P TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE TBT_D2R_N MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE NO_TEST=TRUE TBT_R2D_C_P MAKE_BASE=TRUE NC_TBT_R2D_CP MAKE_BASE=TRUE NC_TBT_R2D_CN DPLL_REF_CLKN TRUE MAKE_BASE=TRUE 11 89 17 TP_PCH_CLKOUT_DPP DPLL_REF_CLKP TRUE MAKE_BASE=TRUE 11 89 TP_PCH_GPIO66_CLKOUTFLEX2 17 TP_PCH_GPIO67_CLKOUTFLEX3 APN 806-2247 BR0901 SM SM SM SHLD-J5-USB SHLD-J5-CAN-FENCE-MDP-2 SHLD-J5-CAN-FENCE-MDP-1 SD_PWR_EN TP_FW_PWR_EN TH SH0951 DPMUX_UC_BOOT_TX DPMUX_UC_TX 82 DPMUX_UC_BOOT_RX DPMUX_UC_RX 17 PCIE_FW_R2D_C_P 17 SATA_ODD_D2R_N 17 91 SATA_ODD_D2R_P 17 91 SATA_ODD_R2D_C_N 17 91 SATA_ODD_R2D_C_P 17 91 C NO_TEST=TRUE 82 82 NC_SATA_ODD_D2R_P SSD PCIE SIGNALS PCIE_SSD_D2R_P =PEG_D2R_P 92 39 20 24 25 ENET_LOW_PWR 25 FW_PWR_EN 25 MAKE_BASE=TRUE 10 NC_SATA_ODD_R2D_C_N MAKE_BASE=TRUE MAKE_BASE=TRUE =PEG_D2R_N PCIE_SSD_D2R_N 92 39 ENET_LOW_PWR_PCH NC_SATA_ODD_D2R_N MAKE_BASE=TRUE 10 NC_SATA_ODD_R2D_C_P MAKE_BASE=TRUE PCIE_SSD_R2D_C_P 92 39 MAKE_BASE=TRUE =PEG_R2D_C_P 10 =PEG_R2D_C_N 10 MAKE_BASE=TRUE MAKE_BASE=TRUE MLB-MTG-BRKT-J5 SH0952 82 MAKE_BASE=TRUE 38 17 PCIE_FW_R2D_C_N NO_TEST=TRUE MAKE_BASE=TRUE NC_PCH_GPIO64_CLKOUTFLEX0 TRUE MAKE_BASE=TRUE NC_PCH_GPIO65_CLKOUTFLEX1 TRUE MAKE_BASE=TRUE NC_PCH_GPIO66_CLKOUTFLEX2 TRUE MAKE_BASE=TRUE NC_PCH_GPIO67_CLKOUTFLEX3 TRUE MAKE_BASE=TRUE SD_PWR_EN_PCH SH0950 MAKE_BASE=TRUE MAKE_BASE=TRUE 17 17 PCIE_FW_D2R_P NO_TEST=TRUE NC_PCIE_FW_R2D_CN NO_TEST=TRUE NC_PCIE_FW_R2D_CP TP_PCH_CLKOUT_DPN TP_PCH_GPIO65_CLKOUTFLEX1 18 PCIE_FW_D2R_N NO_TEST=TRUE NC_PCIE_FW_D2RP NO_TEST=TRUE DPMUX TX & RX 17 TP_PCH_GPIO64_CLKOUTFLEX0 18 LVDS_IG_DDC_DATA NO_TEST=TRUE NC_PCIE_FW_D2RN NO_TEST=TRUE 17 18 91 LVDS_IG_DDC_CLK NO_TEST=TRUE NC_LVDS_IG_DDC_DATA NC_TBT_D2RN MAKE_BASE=TRUE 17 18 91 LVDS_IG_B_DATA_P NO_TEST=TRUE NC_LVDS_IG_DDC_CLK UNUSED TBT PORTS TBT_D2R_P NC_TBT_D2RP MAKE_BASE=TRUE 18 91 LVDS_IG_B_DATA_N NO_TEST=TRUE NC_LVDS_IG_B_DATA_P MAKE_BASE=TRUE MAKE_BASE=TRUE STDOFF-4.9OD2.38H-SM-SL-2.6X2NP-2 18 91 LVDS_IG_A_DATA_P NO_TEST=TRUE NC_LVDS_IG_B_DATA_N 1 LVDS_IG_A_DATA_N NO_TEST=TRUE NC_LVDS_IG_A_DATA_P MAKE_BASE=TRUE TBT_R2D_C_N STDOFF-4.9OD2.38H-SM-2 18 91 MAKE_BASE=TRUE 89 71 SH0945 18 91 LVDS_IG_A_CLK_P NO_TEST=TRUE NC_LVDS_IG_A_DATA_N =PEG_D2R_P STDOFF-4.5OD1.9H-SM SH0946 LVDS_IG_A_CLK_N NO_TEST=TRUE NC_LVDS_IG_A_CLK_P MAKE_BASE=TRUE 89 88 71 NC_PCIE_CLK100M_EXCARD_N PCIE_CLK100M_EXCARD_N SH0924 18 NO_TEST=TRUE MAKE_BASE=TRUE 89 88 71 SH0930 10 18 82 NC_PCIE_EXCARD_D2R_N NC_PCIE_EXCARD_D2R_P NC_PCIE_EXCARD_R2D_C_N NC_PCIE_EXCARD_R2D_C_P TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE STDOFF-4.5OD2.15H-SM =PEG_D2R_N MAKE_BASE=TRUE PCIE_EXCARD_D2R_N PCIE_EXCARD_D2R_P PCIE_EXCARD_R2D_C_N PCIE_EXCARD_R2D_C_P 18 LVDS_IG_B_DATA_N GPU signals MAKE_BASE=TRUE 17 LVDS_IG_B_DATA_P 18 82 SH0928 18 91 NO_TEST=TRUE NC_LVDS_IG_B_DATAN MAKE_BASE=TRUE DPA_IG_HPD DP_TBTSNK1_HPD_IG 10 MAKE_BASE=TRUE MAKE_BASE=TRUE SH0925 LVDS_IG_A_DATA_N NO_TEST=TRUE NC_LVDS_IG_B_DATAP =PEG_D2R_P MAKE_BASE=TRUE MAKE_BASE=TRUE SH0922 MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE PEG_CLKREQ_L 92 35 82 18 91 NO_TEST=TRUE NC_LVDS_IG_A_DATAN MAKE_BASE=TRUE IG_LCD_PWR_EN PEX_CLKREQ_L 17 STDOFF-4.5OD2.15H-SM 10 LVDS_IG_A_DATA_P NO_TEST=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE STDOFF-4.5OD2.15H-SM-1 =PEG_R2D_C_N MAKE_BASE=TRUE T29 Signals Through PEG MAKE_BASE=TRUE SH0921 10 MAKE_BASE=TRUE MAKE_BASE=TRUE NC_LVDS_IG_A_DATAP =PEG_R2D_C_P NO_TEST=TRUE NC_PEG_R2D_C_N MAKE_BASE=TRUE D 10 NO_TEST=TRUE MAKE_BASE=TRUE GMUX ALIASES ZT0973 TH-NSP GND_CHASSIS_MLBCAN4 =PEG_D2R_N NC_PEG_R2D_C_P GND_CHASSIS_MLBCAN6 SL-1.1X0.45-1.4x0.75 10 NO_TEST=TRUE NC_PEG_D2R_N SL-1.1X0.45-1.4x0.75 GND 27 64 MAKE_BASE=TRUE SL-1.1X0.45-1.4x0.75 GND_CHASSIS_MLBCAN3 ZT0975 TH-NSP CPU_VTTSELECT MAKE_BASE=TRUE MEMVTT_EN 27 MAKE_BASE=TRUE SL-1.1X0.45-1.4x0.75 C TP_CPU_VTT_SELECT GND_CHASSIS_MLBCAN5 CPUIMVP_VID MAKE_BASE=TRUE ZT0971 TH-NSP GND_CHASSIS_MLBCAN2 D CPU_VID SL-1.1X0.45-1.4x0.75 SL-2.3X3.9-2.9X4.5 1 CPU signals 2.8R2.3 PCIE_SSD_R2D_C_N 92 39 MAKE_BASE=TRUE MAKE_BASE=TRUE TP_PCIE_CLK100M_FW_P PCIE_CLK100M_FW_P 17 92 PCIE_CLK100M_FW_N 17 92 MAKE_BASE=TRUE TP_PCIE_CLK100M_FW_N MAKE_BASE=TRUE NC_DP_IG_MLP MAKE_BASE=TRUE POGO PINS SMT GND TEST PONTS NC_PCH_FDI_DATA_N MAKE_BASE=TRUE B SH0932 SH0933 POGO-2.3OD-5.5H-SM-LOW-FORCE POGO-2.3OD-5.5H-SM-LOW-FORCE POGO-2.3OD-5.5H-SM-LOW-FORCE SM SM SM ZT0990 ZT0991 ZT0992 2.1SM2.0MM-CIR 2.1SM2.0MM-CIR 2.1SM2.0MM-CIR SMT-PAD-NSP SMT-PAD-NSP SMT-PAD-NSP MAKE_BASE=TRUE 18 =FDI_DATA_P 18 =FDI_FSYNC 18 NC_PCH_FDI_FSYNC MAKE_BASE=TRUE R0950 37 =PPVIN_SW_TBTBST NC_PCH_FDI_LSYNC MAKE_BASE=TRUE =FDI_LSYNC =PP15V_TBT_REG 37 B SYNC_DATE=01/13/2012 A 5% 1/8W MF-LF 805 NO_TEST=TRUE 18 NO_TEST=TRUE MAKE_BASE=TRUE POGO-2.3OD-5.5H-SM-LOW-FORCE SM SH0934 SH0935 SH0936 POGO-2.3OD-5.5H-SM-LOW-FORCE POGO-2.3OD-5.5H-SM-LOW-FORCE POGO-2.3OD-5.5H-SM-LOW-FORCE SM SM SM MAKE_BASE=TRUE 10 89 FDI_DATA_P 10 89 NC_CPU_FDI_FSYNC SMT-PAD-NSP NC_CPU_FDI_LSYNC MAKE_BASE=TRUE 10 89 NC_USB3_EXTD_TX_N FDI_LSYNC 10 89 NC_USB3_EXTD_RX_P MAKE_BASE=TRUE MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE SH0960 91 34 2.8OD1.2ID-1.35H-SM USB_BT_P 26 USBHUB_DN1_N 26 MAKE_BASE=TRUE MAKE_BASE=TRUE 91 34 USB_BT_N 91 49 USB_TPAD_P 91 49 SH0941 SH0944 SH0961 2.8OD1.2ID-1.35H-SM 2.8OD1.2ID-1.35H-SM 2.8OD1.2ID-1.35H-SM 2.8OD1.2ID-1.35H-SM 1 USB_TPAD_N USBHUB_DN2_P 26 USBHUB_DN2_N 26 USBHUB_DN3_P 26 USBHUB_DN3_N 26 USBHUB_DN4_P 26 MAKE_BASE=TRUE 91 41 USB_SMC_P MAKE_BASE=TRUE 91 41 USB_SMC_N MAKE_BASE=TRUE PU_USBHUB_DN4P MAKE_BASE=TRUE Digital Ground A PU_USBHUB_DN4N SH0943 2.8OD1.2ID-1.35H-SM 2.8OD1.2ID-1.35H-SM 20 20 20 MLB_RAMCFG1 R09101 1K 5% 1/20W MF 201 R09121 RAMCFG1:L MLB_RAMCFG0 RAMCFG0:L RAMCFG2:L R0911 1K 5% 1/20W MF 201 1K 5% 1/20W MF 201 R09131 NO_TEST=TRUEI1188 NC_USB3_EXTC_TX_N MAKE_BASE=TRUE NO_TEST=TRUEI1189 NC_USB3_EXTC_RX_P MAKE_BASE=TRUE NO_TEST=TRUEI1190 NC_USB3_EXTC_RX_N MAKE_BASE=TRUE NO_TEST=TRUEI1192 NC_USB_EXTC_P MAKE_BASE=TRUE NO_TEST=TRUEI1191 NC_USB_EXTC_N 19 91 USB3_EXTC_TX_N 19 91 USB3_EXTC_RX_P 19 91 USB3_EXTC_RX_N 19 91 USB_EXTC_P 19 91 USB_EXTC_N USBHUB_DN4_N 19 91 NO_TEST=TRUE 26 SYNC_MASTER=D2_KEPLER PAGE TITLE =PP5V_S0_AUDIO_XW Signal Aliases 1K 5% 1/20W MF 201 DRAWING NUMBER XW0902 Apple Inc SM XW0903 PP5V_S0_AUDIO_AMP_L 57 MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM VOLTAGE=5V PP5V_S0_AUDIO_AMP_R MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM VOLTAGE=5V 57 051-9589 REVISION R NOTICE OF PROPRIETARY PROPERTY: SM 19 USB3_EXTC_TX_P NO_TEST=TRUEI1187 NC_USB3_EXTC_TX_P MAKE_BASE=TRUE RAMCFG3:L MLB_RAMCFG2 19 USB_EXTD_EHCI_N MAKE_BASE=TRUE MLB_RAMCFG3 20 SH0942 19 USB_EXTD_EHCI_P NO_TEST=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE SH0940 19 USB3_EXTD_RX_N NO_TEST=TRUE NC_USB_EXTD_EHCI_N MAKE_BASE=TRUE MAKE_BASE=TRUE 19 USB3_EXTD_RX_P NO_TEST=TRUE NC_USB_EXTD_EHCI_P USB SIGNALS USBHUB_DN1_P 19 USB3_EXTD_TX_N NO_TEST=TRUE NC_USB3_EXTD_RX_N 1 UNUSED USB SIGNALS USB3_EXTD_TX_P NO_TEST=TRUE FDI_FSYNC NO_TEST=TRUE MAKE_BASE=TRUE NC_USB3_EXTD_TX_P MAKE_BASE=TRUE NO_TEST=TRUE 2.1SM2.0MM-CIR FDI_DATA_N NO_TEST=TRUE NC_CPU_FDI_DATA_P ZT0993 SH0937 18 TBTBST:N NO_TEST=TRUE NC_CPU_FDI_DATA_N =FDI_DATA_N 18 TP_DP_IG_B_MLN NO_TEST=TRUE NO_TEST=TRUE NC_PCH_FDI_DATA_P SH0931 MAKE_BASE=TRUE TP_DP_IG_B_MLP NO_TEST=TRUE NC_DP_IG_MLN UNUSED FDI SIGNALS THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED 4.18.0 BRANCH PAGE OF 132 SHEET OF 99 SIZE D =PP1V05_S0_CPU_VCCIO OMIT_TABLE U1000 BGA IN R8 89 18 IN DMI_S2N_N U10 89 18 IN 89 18 IN DMI_S2N_P T9 89 18 IN DMI_S2N_P R6 89 18 IN DMI_S2N_P U8 89 18 OUT DMI_N2S_N N4 89 18 OUT DMI_N2S_N R4 89 18 OUT DMI_N2S_N OUT DMI_N2S_N 89 18 DMI_N2S_P 89 18 OUT DMI_N2S_P P3 89 18 OUT DMI_N2S_P T5 C OUT V7 OUT FDI_DATA_N W8 89 OUT FDI_DATA_N AA8 89 OUT FDI_DATA_N AC10 89 U4 89 OUT FDI_DATA_N 89 OUT FDI_DATA_N W2 89 OUT FDI_DATA_N V1 89 OUT FDI_DATA_N Y5 W6 OUT FDI_DATA_P 89 OUT FDI_DATA_P 89 OUT FDI_DATA_P Y9 89 OUT FDI_DATA_P AA10 OUT W10 FDI_DATA_P U2 W4 89 OUT FDI_DATA_P 89 OUT FDI_DATA_P V3 OUT FDI_DATA_P AA6 89 89 IN FDI_FSYNC AC8 89 IN FDI_FSYNC AA2 89 18 IN FDI_INT AD9 89 IN FDI_LSYNC AB3 89 IN FDI_LSYNC AB7 89 82 OUT DP_INT_IG_ML_N AG2 89 82 OUT DP_INT_IG_ML_N AF1 89 82 OUT DP_INT_IG_ML_N AE6 89 82 OUT DP_INT_IG_ML_N AG6 89 82 OUT DP_INT_IG_ML_P AG4 89 82 OUT DP_INT_IG_ML_P AF3 89 82 OUT DP_INT_IG_ML_P AF7 89 82 OUT DP_INT_IG_ML_P AG8 89 82 BI DP_INT_IG_AUX_P AE4 89 82 BI DP_INT_IG_AUX_N AE2 15 14 13 11 10 =PP1V05_S0_CPU_VCCIO 1K 5% 1/16W MF-LF 1% 1/16W MF-LF 402 DMI_TX0* DMI_TX1* DMI_TX2* DMI_TX3* DMI_TX0 DMI_TX1 DMI_TX2 DMI_TX3 FDI0_TX0* FDI0_TX1* FDI0_TX2* FDI0_TX3* AB1 89 CPU_EDP_COMP DP_INT_IG_HPD_L D PEG_RX0 PEG_RX1 PEG_RX2 PEG_RX3 PEG_RX4 PEG_RX5 PEG_RX6 PEG_RX7 PEG_RX8 PEG_RX9 PEG_RX10 PEG_RX11 PEG_RX12 PEG_RX13 PEG_RX14 PEG_RX15 FDI1_TX0* FDI1_TX1* FDI1_TX2* FDI1_TX3* FDI0_TX0 FDI0_TX1 FDI0_TX2 FDI0_TX3 FDI1_TX0 FDI1_TX1 FDI1_TX2 FDI1_TX3 FDI0_FSYNC FDI1_FSYNC FDI_INT PEG_TX0* PEG_TX1* PEG_TX2* PEG_TX3* PEG_TX4* PEG_TX5* PEG_TX6* PEG_TX7* PEG_TX8* PEG_TX9* PEG_TX10* PEG_TX11* PEG_TX12* PEG_TX13* PEG_TX14* PEG_TX15* FDI1_LSYNC FDI0_LSYNC EDP_TX0* EDP_TX1* EDP_TX2* EDP_TX3* EDP_TX0 EDP_TX1 EDP_TX2 EDP_TX3 EDP_AUX EDP_AUX* AC2 EDP_ICOMPO EDP_COMPIO AE8 EDP_HPD* PEG_TX0 PEG_TX1 PEG_TX2 PEG_TX3 PEG_TX4 PEG_TX5 PEG_TX6 PEG_TX7 PEG_TX8 PEG_TX9 PEG_TX10 PEG_TX11 PEG_TX12 PEG_TX13 PEG_TX14 PEG_TX15 Q1031 82 DP_INT_IG_HPD IN 2N7002TXG G SOT-523-3 S 89 24 10 CPU_CFG 89 24 10 CPU_CFG EDP:YES 2 G2 CPU_CFG 89 24 10 CPU_CFG CPU_CFG 89 24 10 CPU_CFG 89 24 10 CPU_CFG 89 24 10 CPU_CFG R1010 1% 1/16W MF-LF 402 89 CPU_PEG_COMP H1 F3 F23 =PEG_D2R_N IN =PEG_D2R_N IN H21 =PEG_D2R_N IN H19 =PEG_D2R_N IN J20 =PEG_D2R_N IN G18 =PEG_D2R_N IN K17 =PEG_D2R_N IN F15 =PEG_D2R_N IN IN H15 =PEG_D2R_N H13 =PEG_D2R_N IN H11 =PEG_D2R_N IN J12 =PEG_D2R_N IN IN E8 =PEG_D2R_N G10 =PEG_D2R_N IN J8 =PEG_D2R_N IN =PEG_D2R_N IN F7 TP SIGNAL_MODEL=EMPTY SM BEAD-PROBE BP1004 U1000 BB57 IVY-BRIDGE BB43 BGA BB25 (IPU) (5 OF 11) RESERVED BB17 (IPU) OMIT_TABLE 89 24 10 CPU_CFG B57 89 24 10 CPU_CFG D57 89 24 10 CPU_CFG B55 89 24 10 CPU_CFG A54 89 24 10 CPU_CFG A58 89 24 10 CPU_CFG D55 (IPU) BB13 89 24 10 CPU_CFG C56 (IPU) BA48 89 24 10 CPU_CFG E54 (IPU) BA16 89 24 CPU_CFG J54 (IPU) AY45 89 24 CPU_CFG G56 (IPU) AY41 89 24 CPU_CFG F55 (IPU) AY17 89 24 CPU_CFG K55 (IPU) AY15 89 24 CPU_CFG F57 (IPU) AY13 89 24 CPU_CFG E58 (IPU) AW50 89 24 CPU_CFG H57 (IPU) AW46 89 24 CPU_CFG H55 (IPU) AW42 89 24 10 CPU_CFG D53 (IPU) AW14 89 24 CPU_CFG K57 (IPU) H23 G22 =PEG_D2R_P IN K23 =PEG_D2R_P IN K21 =PEG_D2R_P IN F19 =PEG_D2R_P IN K19 =PEG_D2R_P IN IN H17 =PEG_D2R_P K15 =PEG_D2R_P IN G14 =PEG_D2R_P IN J16 =PEG_D2R_P IN =PEG_D2R_P IN K13 F11 =PEG_D2R_P IN K11 =PEG_D2R_P IN F9 =PEG_D2R_P IN H9 =PEG_D2R_P IN H7 =PEG_D2R_P IN TP TP =PEG_D2R_P IN A22 =PEG_R2D_C_N OUT B23 =PEG_R2D_C_N OUT C18 =PEG_R2D_C_N OUT D21 =PEG_R2D_C_N OUT B19 =PEG_R2D_C_N OUT E20 =PEG_R2D_C_N OUT A14 =PEG_R2D_C_N OUT D17 =PEG_R2D_C_N OUT =PEG_R2D_C_N OUT E16 =PEG_R2D_C_N OUT D13 =PEG_R2D_C_N OUT A10 =PEG_R2D_C_N OUT B11 =PEG_R2D_C_N OUT D9 =PEG_R2D_C_N OUT B7 =PEG_R2D_C_N OUT E12 =PEG_R2D_C_N OUT C22 =PEG_R2D_C_P OUT D23 =PEG_R2D_C_P OUT A18 =PEG_R2D_C_P OUT B21 =PEG_R2D_C_P OUT D19 =PEG_R2D_C_P OUT F21 =PEG_R2D_C_P OUT C14 =PEG_R2D_C_P OUT B17 =PEG_R2D_C_P OUT D15 =PEG_R2D_C_P OUT F17 =PEG_R2D_C_P OUT B13 =PEG_R2D_C_P OUT C10 =PEG_R2D_C_P OUT D11 =PEG_R2D_C_P OUT B9 =PEG_R2D_C_P OUT D7 =PEG_R2D_C_P OUT F13 =PEG_R2D_C_P OUT QTY SM BEAD-PROBE BP1011 SM BEAD-PROBE BP1012 SIGNAL_MODEL=EMPTY NOTE: Intel is investigating processor driven VREF_DQ generation This connection is to support the same (IPU) (IPU) (IPU) BB15 CFG AJ10 G64 AH5 BJ42 AD5 BJ34 AC6 BJ22 AC4 BH43 P7 RSVD BH25 BH23 N6 M9 BH21 M5 BH19 L10 BG62 L6 BG34 L4 BG26 L2 BG22 K49 (DDR_VREF1) (THERMDA) K47 NC NC NC NC NC NC NC NC BF63 NC NC NC NC NC NC NC NC NC NC NC BE32 K9 G52 BE16 G48 K7 BF43 BF41 K5 RSVD BF35 J50 BF25 J4 BF23 J2 BF21 H49 BF19 H47 BF3 PPCPU_MEM_VREFDQ_A MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0.75V AA4 BH35 BG4 PPCPU_MEM_VREFDQ_B MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0.75V 89 33 B15 PART NUMBER NC NC NC NC NC NC NC NC NC NC NC NC NC NC SIGNAL_MODEL=EMPTY 89 33 G6 89 24 10 CPU_CFG 89 24 10 89 24 10 AJ6 PLACE_NEAR=U1000.AB1:12.7mm PEG_RX0* PEG_RX1* PEG_RX2* PEG_RX3* PEG_RX4* PEG_RX5* PEG_RX6* PEG_RX7* PEG_RX8* PEG_RX9* PEG_RX10* PEG_RX11* PEG_RX12* PEG_RX13* PEG_RX14* PEG_RX15* DMI_RX0 DMI_RX1 DMI_RX2 DMI_RX3 24.9 R1031 402 R2 FDI_DATA_N 89 89 B N2 OUT 89 R1030 U6 DMI_N2S_P 89 18 OMIT_TABLE P1 OUT 89 18 N8 DMI_S2N_P (1 OF 11) PEG_ICOMPI PEG_ICOMPO PEG_RCOMPO DMI_RX0* DMI_RX1* DMI_RX2* DMI_RX3* DMI R10 DMI_S2N_N INTEL FLEXIBLE DISPLAY INTERFACE SIGNALS PCI EXPRESS BASED INTERFACE SIGNALS N10 DMI_S2N_N IN EMBEDDED DISPLAY PORT D DMI_S2N_N IN 89 18 89 18 24.9 IVY-BRIDGE 89 18 10 11 13 14 15 (THERMDC) H5 (DDR_VREF0) BE6 G4 BD33 F5 BD29 D49 BD19 D25 BD15 D3 BD13 C52 BC42 C24 BC30 C4 BC14 B53 B25 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC D C B DESCRIPTION REFERENCE DES CRITICAL BOM OPTION 116S0066 RES,MTL FILM,1/16W,1K,0402,SMD,LF R1031 EDP:YES 116S0090 RES,MTL FILM,1/16W,10K,0402,SMD,LF R1031 EDP:NO EDP:YES NOSTUFF R1042 R1044 1K A 1 R1045 1K 1 R1046 1K NOSTUFF NOSTUFF R1047 1K R1040 1K NOSTUFF NOSTUFF R1041 1K NOSTUFF R1043 1K R1049 1K 1K 5% 5% 5% 5% 5% 5% 5% 5% 5% 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W MF-LF MF-LF MF-LF MF-LF MF-LF MF-LF MF-LF MF-LF MF-LF 402 402 402 402 402 402 2 402 402 402 A PAGE TITLE CPU DMI/PEG/FDI/RSVD DRAWING NUMBER These can be Placed close to J2500 and Only for debug access CPU_CFG should be pulled down to enable EDP Apple Inc 051-9589 R CFG [7] :PEG DEFER TRAINING = (DEFAULT) IMMEDIATELY AFTER xxRESETB CFG [6:5] :PCIE BIFURCATION 11 = X16 (DEFAULT) CFG [4] :eDP ENABLE/DISABLE = DISABLED CFG [3] :PCIE x4 LANE REVERSAL = NORMAL OPERATION = LANES REVERSED CFG [2] :PCIE x16 LANE REVERSAL = NORMAL OPERATION = LANES REVERSED 10 = X8 = WAIT FOR BIOS 01 = RSVD NOTICE OF PROPRIETARY PROPERTY: 00 = X8, X4, X4 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED = ENABLED SIZE D REVISION 4.18.0 BRANCH PAGE 10 OF 132 SHEET 10 OF 99 85 C9620 V3P3 must be S4 to support wake from Thunderbolt devices 1 2 C9681 22UF 20% 6.3V X5R-CERM-1 603 0.1UF Min 1030mA 830mA 830mA V3P3OUT OUT C9615 10% 25V X5R-CERM 0603 C9610 12 PPHV_SW_TBTBPWR 14 MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=15V VHV C9685 CRITICAL 0.1UF 10% 16V X5R-CERM 0201 CD3210A0RGP QFN 16 70 IN =TBTBPWRSW_EN 37 35 IN TBT_B_HV_EN RSVD C9686 BI 93 35 BI C9630 DP_TBTPB_AUXCH_C_N DP_TBTPB_AUXCH_C_P ISET_V3P3 0.1UF 20% 6.3V CERM-X5R 0402 10% 25V X5R 402 TBTBPWRSW_ISET_V3P3 10 TBTBPWRSW_ISET_S0 IN =TBT_S0_EN 17 ISET_S3 S0 93 35 IN 85 C9632 DP_TBTPB_ML_C_P DP_TBTPB_ML_C_N TBTHV:P15V 0.22UF R9611 22.6K 1% 1/20W MF 201 35 R9612 1% 1/20W MF 201 REFERENCE DES CRITICAL RES,MTL FILM,1/20W,17.8K,1,0201,SMD,LF R9610,R9613 TBTHV:P12V 118S0145 RES,MTL FILM,1/20W,17.8K,1,0201,SMD,LF R9611,R9614 TBTHV:P12V L9600 10% 50V X7R-CERM 0402 TBTBCONN_20_RC GND_VOID=TRUE 4V 201 93 6.3V 0201 93 20% X5R OUT 0.47UF C9677 2 TBT Dir TBT_B_LSTX TBT_B_LSRX_UNBUF 14 10 20% X5R 6.3V 0201 35 IN 35 IN TBT_B_DP_PWRDN 35 OUT DP_TBTPB_HPD 13 12 R9626 CA_DET 18 TBT_B_CONFIG1_RC LSTX LSRX DPMLO+ DPMLO- 19 DP_B_LSX_ML_P DP_B_LSX_ML_N 20 HPDOUT HPD 17 85 93 85 93 85 R9628 100K 5% 1/20W MF 201 TBTBCONN_1_C C9605 12 0.01UF 10% 25V X5R-CERM 0201 5% 1/20W MF 201 For J9600 TBT SMT pads (3, 5, 17 & 19): GND_VOID=TRUE DP Dir (Both C’s) (0-18.9V) TBT Dir C9670 TBT_B_R2D_P 93 TBT_B_R2D_N TBTBCONN_7_C 470K A2 A4 A6 A8 A10 A12 A14 A16 A18 A20 5% MF DP_TBTPB_ML_P DP_TBTPB_ML_N R9679 470K 1/20W 201 CRITICAL 5% 1/20W MF 201 SIGNAL_MODEL=TBTPIN GND_VOID=TRUE MDP-D2 F-RT-TH GND0 HPD ML_LANE0P CONFIG1 ML_LANE0N CONFIG2 GND1 GND2 ML_LANE3P ML_LANE1P ML_LANE1N ML_LANE3N GND3 GND4 ML_LANE2P AUX_CHP ML_LANE2N AUX_CHN RETURN DP_PWR C9606 10% 25V X5R-CERM 0201 D9698 A K BAR90-02LRH D9699 TSLP-2-7 A 93 K BAR90-02LRH 4V 201 93 TBT_B_D2R1_AUXDDC_P TBT_B_D2R1_AUXDDC_N 6.3V 0201 TBT_B_R2D_C_P TBT_B_R2D_C_N 20% X5R IN 35 93 IN 35 93 6.3V 0201 GND_VOID=TRUE R9670 470K R9671 470K 5% 1/20W MF 201 5% 1/20W MF 201 (0-18.9V) DP_B_LSX_ML_P DP_B_LSX_ML_N 85 93 B 85 93 TBT: LSX_R2P/P2R (P/N) GND_VOID=TRUE (Both C’s) C9672 93 93 514-0803 20% X5R 0.22UF TBT_B_R2D_P TBT_B_R2D_N C9673 6.3V 0201 TBT_B_R2D_C_P TBT_B_R2D_C_N 20% X5R 0.22UF IN 35 93 IN 35 93 6.3V 0201 TBT: TX_1 GND_VOID=TRUE TSLP-2-7 GND_VOID=TRUE R9672 470K 650NH-5%-0.430MA-0.52OHM DP_B_AUXCH_DDC_P DP_B_AUXCH_DDC_N 0.22UF 0.01UF A1 A3 A5 A7 A9 A11 A13 A15 A17 A19 20% X5R GND_VOID=TRUE SHIELD PINS (Both D’s) GND_VOID=TRUE TBT_B_D2R_C_P TBT_B_D2R_C_N 4V 201 MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=18.9V GND_VOID=TRUE C9671 PORT A 2.2K 5% 1/20W MF 201 1/20W 201 R9699 2.2K TBT: TX_0 0.22UF L9698 93 85 85 TBT_B_HPD GND THMPAD CRITICAL 93 85 85 93 DP_PD 1M J9400 5% MF 20% CERM-X5R-1 85 93 TBT: LSX_A_R2P/P2R (P/N) 5% 1/20W MF 201 DP Dir SIGNAL_MODEL=EMPTY TBT: Unused 6.3V 0201 GND_VOID=TRUE 20% CERM-X5R-1 0.47UF DP+ DP- S11 S10 S9 S8 S7 S6 GND_VOID=TRUE OUT 10% 50V X7R-CERM 0402 5% 1/20W MF 201 TBT_B_BIAS (Both C’s) 93 35 C9601 R9698 93 35 CA_DETOUT 11 GND R9695 20% X5R 0.22UF TBT_B_D2R_P TBT_B_D2R_N 16 DP_TBTPB_ML_P DP_TBTPB_ML_N SHIELD PINS R9678 0.22UF DP_B_AUXCH_DDC_N DP_B_AUXCH_DDC_P 22 1K SIGNAL_MODEL=EMPTY 23 TBT: RX_1 Bias Sink TBT_B_CONFIG1_BUF GND_VOID=TRUE 1K C9676 C TBT_B_D2R_C_P TBT_B_D2R_C_N 5% 1/20W MF 201 85 93 S5 S4 S3 S2 S1 93 20% CERM-X5R-1 C9679 0.1UF AUXIOAUXIO+ DDC_DAT DDC_CLK 93 93 4V 201 R9694 B B 10% 16V X5R-CERM 0201 MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=18.9V GND_VOID=TRUE MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=18V 0.01UF 20% CERM-X5R-1 C9678 OUT PP3V3RHV_SW_TBTBPWR 0.01UF R9601 (Both C’s) 0.47UF DP_TBTPB_DDC_DATA DP_TBTPB_DDC_CLK MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=15V GND_VOID=TRUE DP_TBTPB_ML_C_P DP_TBTPB_ML_C_N 0603 C9600 Max 1170mA (12W minimum) C9675 AUXAUX+ FERR-120-OHM-3A BOM OPTION AUXIO_EN Thunderbolt Connector B CRITICAL ILIM = 40000 / RISET 118S0145 0.47UF C9660 10% 16V X5R-CERM 0201 C9674 DP_TBTPB_AUXCH_N DP_TBTPB_AUXCH_P A Y = B 1% 1/20W MF 201 Single-fault protection requires two R’s per HV ISET_Sx with CD3210 Single R on ISET_V3P3 OK 22.6K TBT_B_D2R_P TBT_B_D2R_N OUT 36.5K 1% 1/20W MF 201 Y TBT_B_LSRX 24 C R9614 1% 1/20W MF 201 DESCRIPTION DP_AUXIO_EN VCC 22.6K D 0.1UF BIASOUT 22.6K Min 1090mA IN 93 C9633 BIASIN TBTHV:P15V R96131 Nominal IHVS0/S3 1120mA 83 PP3V3_SW_TBTBPWR TBTHV:P15V R96101 12V: See below 21 C QTY BI 6.3V 0201 SOT891 TBTHV:P15V 85 C9625 20% X5R U9660 TBTBPWRSW_ISET_S3_R TBTBPWRSW_ISET_S0_R PART NUMBER 83 82 35 IN TBTBPWRSW_ISET_S3 THRM PAD 13 GND For 12V systems: 93 10% 16V X5R-CERM 0201 0.1UF 93 35 IN CRITICAL ISET_S0 HV_EN 93 C9631 0.22UF TBT_B_BIAS VOLTAGE=3.3V 74AUP1T97 84 70 CBTL05023 TBT_B_CIO_SEL IN 10% 16V X5R-CERM 0201 0.1UF C9611 10UF 93 35 15 RSVD EN 11 0.1UF U9610 10% 25V X5R 402 85 MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=3.3V 18 V3P3 4.7UF IN 5% 1/20W MF 201 HVQFN 35 84 25 93 35 100K 5% 1/20W MF 201 SIGNAL_MODEL=TBT_MUX PP3V3_SW_TBTBPWR =PPHV_SW_TBTBPWRSW IN 10K U9620 Max 1200mA 930mA (assumes 15V, 12W minimum) 930mA (assumes 3S, 9-12.6V, 7.5-11.7W) 10% 16V X5R-CERM 0201 18V Max 93 35 R9629 R9627 25 Nominal IV3P3 1100mA IHVS0 890mA IHVS3 890mA 20 OUT VDD CRITICAL 19 93 35 C9680 100UF 20% 6.3V POLY-TANT CASE-B2-SM OUT 10% 16V X5R-CERM 0201 =PP3V3_S4_TBTBPWRSW C9687 93 35 0.1UF 10% 16V X5R-CERM 0201 CRITICAL C9621 0.1UF 21 D PP3V3_SW_TBTBPWR 3.3V/HV Power MUX 15 GND_VOID=TRUE R9673 470K 5% 1/20W MF 201 5% 1/20W MF 201 0603 SIGNAL_MODEL=EMPTY C9698 1 30PF 5% 50V C0G-NP0 0402 CRITICAL C9699 2 470k R’s for ESD protection on AC-coupled signals L9699 30PF 650NH-5%-0.430MA-0.52OHM 5% 50V C0G-NP0 0402 0603 GND_VOID=TRUE SIGNAL_MODEL=EMPTY A 85 TBT_B_HPD 85 TBT_B_CONFIG1_RC SYNC_MASTER=D2_KEPLER 35 OUT C9602 0.01UF TBT_B_CONFIG2_RC R9652 1 1M 5% 1/20W MF 201 R9651 1M 2 5% 1/20W MF 201 C9694 1 330PF 10% 16V X7R-CERM 0201 C9695 10% 16V X7R-CERM 0201 10% 16V X5R-CERM 0201 Thunderbolt Connector B DRAWING NUMBER Apple Inc 100K 330PF R9641 SYNC_DATE=01/13/2012 PAGE TITLE DP Source must pull down HPD input with greater than or equal to 100K (DPv1.1a) 051-9589 R Sink HPD range: High: 2.0 - 5.0V Low: - 0.8V 5% 1/20W MF 201 NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED SIZE D REVISION 4.18.0 BRANCH PAGE 96 OF 132 SHEET 85 OF 99 A PPBUS S0 LCDBkLT FET CRITICAL Q9706 MOSFET FDC638APZ CHANNEL P-TYPE RDS(ON) 43 mOhm @4.5V LOADING 0.715 A (EDP) FDC638APZ_SBMS001 SSOT6-HF PPBUS_SW_LCDBKLT_PWR MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.6V 603-HF C9782 R9788 BOTTOM 99 THERE IS A SENSE RESISTOR BETWEEN PPBUS_SW_LCDBKLT_PWR AND PPBUS_SW_BKL ON THE SENSOR PAGE NEED VALUE CHANGES FOR 55V AND 96 LEDS !!! 0.1UF 301K 10% 16V X7R-CERM 0402 1% 1/16W MF-LF 402 =PP5V_S0_BKL LCDBKLT_EN_DIV *L9710, Q9701, D9701, C9715-C9719 SHOULD ALL BE PLACED NEAR EACH OTHER R9789 PLACE_NEAR=L9710.2:3MM CRITICAL 147K C9715, C9716 SHOULD BE PLACED IN T-BONE SAME FOR C9718,C9719 CRITICAL L9710 1% 1/16W MF-LF 402 PPBUS_S0_LCDBKLT_PWR 86 PLACE_NEAR=L9710.1:5MM LCDBKLT_EN_L SOT563 MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.25 MM C9713 C9712 MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM VOLTAGE=50V DEM8030C-SM 152S1527 10% 25V X5R 805 10% 25V X5R 402 C9715, C9716 SHOULD BE PLACED ON TOP SIDE PLACE C9718,C9719 ON BOTTOM SIDE D9701 POWERDI-123 A PLACE_NEAR=D9701.2:5MM K CRITICAL DFLS2100 SWITCH_NODE=TRUE 0.1UF 10UF D SSM6N15FEAPE 22UH-20%-2.4A-0.105OHM VOLTAGE=12.6V PPBUS_S0_LCDBKLT_PWR_SW PLACE_NEAR=L9710.1:3MM CRITICAL Q9707 D D MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.6V F9700 3AMP-32V-467 =PPBUS_S0_LCDBKLT PPBUS_S0_LCDBKLT_FUSED C9715 1 2.2UF 10% 100V X7R-CERM 1210 PPBUS_S0_LCDBKLT_PWR_SW SHOULD BE KEPT AS SHORT AS POSSIBLE PLACE_NEAR=D9701.2:5MM CRITICAL C9716 CRITICAL 2.2UF 10% 100V X7R-CERM 1210 C9718 2.2UF PPVOUT_S0_LCDBKLT C9719 2.2UF 10% 100V X7R-CERM 1210 81 99 MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.25 MM VOLTAGE=55V CRITICAL C9717 1000PF 10% 100V X7R-CERM 1210 10% 100V X7R-CERM 0603 PLACE_NEAR=R9708.1:5MM G 82 S LCD_BKLT_EN IN PLACE_NEAR=D9701.2:3MM LCDBKLT_DISABLE PLACE_NEAR=D9701.2:3MM Q9707 =PP3V3_S0_BKL_VDDIO D SSM6N15FEAPE PLACE_NEAR=U9701.8:3MM SOT563 R9708 PLACE_NEAR=U9701.22:5MM PLACE_NEAR=U9701.22:3MM C G 25 0.01UF S BKLT_PLT_RST_L IN C9714 C9710 1UF 10% 16V X7R-CERM 0402 PLACE_NEAR=L9710.2:3MM C9711 10% 25V X5R 603-1 1% 1/16W MF-LF 402 10% 16V X7R-CERM 0402 C 63.4K 0.1UF CRITICAL Q9701 BKL_FET_CNTL SI7812DN PWRPK-1212-8 MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM R9709 59.0K VDDIO 1% 1/16W MF-LF 402 23 22 VIN VLDO U9701 R9757 MF-LF PPBUS_S0_LCDBKLT_PWR 301K 13 BKL_ISEN2 14 BKL_ISEN3 BKL_SDA 11 SDA OUT4 16 BKL_ISEN4 PWM TP_BKL_FAULT FAULT BKLT_EN EN R9714 R9704 5% 1/16W MF-LF 402 LCD_BKLT_PWM SHOULD BE KEPT AWAY FROM BOOST CIRCUIT R9765 10K (EEPROM should set EN_I_RES=1) 1% 1/16W MF-LF 402 IN OUT2 1% 1/16W MF-LF 402 1 BKL_ISEN1 OUT3 100K LCD_BKLT_PWM R9717 SCLK R9715 15.4K 82 OUT1 12 D_BKL:DEV PLACE_NEAR=U9701.12:10MM ISET 1% 1/16W MF-LF 402 B BKL_FB 17 OUT6 18 BKL_ISEN6 VSYNC CRITICAL 19 BKL_VSYNC_R I_LED=23.96MA I_LED=369/Riset R9716 1% 1/16W MF-LF 402 NO STUFF OUT 81 10.2 LED_RETURN_2 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm OUT 81 OUT 81 D_BKL:DEV R9719 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm R9755 10K THRM PAD (APN: 353S3376) PWM RES = 9+3 10.2 B LED_RETURN_3 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm 0.1% 1/16W TF 402 5% 1/16W MF-LF 402 D_BKL:DEV R9720 PLACE_NEAR=U9701.16:10MM 10.2 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm LED_RETURN_4 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm 0.1% 1/16W TF 402 FPWM=19.2KHZ details in spec OUT 81 D_BKL:DEV R9721 PLACE_NEAR=U9701.17:10MM MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm C9704 10.2 LED_RETURN_5 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm 0.1% 1/16W TF 402 XW9710 5% 50V C0G-CERM 0402 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm 0.1% 1/16W TF 402 PLACE_NEAR=U9701.14:10MM 33PF LED_RETURN_1 R9718 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm 12.7K 5% 1/16W MF-LF 402 D_BKL:DEV PLACE_NEAR=U9701.13:10MM BKL_ISEN5 OUT5 10.2 0.1% 1/16W TF 402 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm 402 R9731 86 21 LVDS_BKL_PWM_RC 1/16W FB MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm 402 5% BKL_SW 25 =I2C_BKL_1_SDA MF-LF 24 10 GND_L 44 1/16W SW BKL_SCL 15 5% FILTER GND_S BKL_FLT 20 GND_SW FSET R9753 =I2C_BKL_1_SCL BKL_FSET BKL_ISET R9753 AND R9757 NEED TO BE 402 PACK FOR LAB ACCESS 44 GD LP8545SQX-EXTJ LLP OUT 81 SM BKL_SGND D_BKL:DEV R9722 PLACE_NEAR=U9701.9:10MM MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=0V PLACE_NEAR=U9701.18:10MM MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm PLACE XW9710 AWAY FROM U9701.1 AND U9701.15 ADD VIAS IN TPAD OF U9701 PART NUMBER A 116S0004 QTY DESCRIPTION RES, 0OHM, 0402 10.2 LED_RETURN_6 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm 0.1% 1/16W TF 402 REFERENCE DES R9717,R9718,R9719,R9720,R9721,R9722 CRITICAL OUT 81 BOM OPTION D_BKL:PROD SYNC_MASTER=D2_KEPLER SYNC_DATE=01/13/2012 PAGE TITLE LCD Backlight Driver (LP8545) DRAWING NUMBER Apple Inc 051-9589 R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED SIZE D REVISION 4.18.0 BRANCH PAGE 97 OF 132 SHEET 86 OF 99 A D D PCH VCCIO (1.05V S0) REGULATOR 8 =PPVIN_S0_PCHVCCIOS0 =PP5V_S0_PCHVCCIOS0 XW9801 PCHVCCIOS0_BOOT_RC SM 87 =PPPCHVCCIO_S0_REG 97 R98011 PCH_VCCIOSENSE_P 5% 1/16W MF-LF 402 PCH_VCCIOSENSE_N Vout = 0.5V * (1 + Ra / Rb) R9804 1 3.01K 1% 1/16W MF-LF 402 R9844 R98301 PVCC 70 IN 1UF UTQFN =PCHVCCIOS0_EN PCHVCCIOS0_FB FB PCHVCCIOS0_SREF SREF EN CRITICAL PCHVCCIOS0_VO VO PCHVCCIOS0_OCSET OCSET 20% 16V POLY-TANT CASE-D2E-SM 2 C9822 1000PF 10% 16V X5R 402 5% 25V NP0-C0G 402 C PLACE_NEAR=Q9830.1:1.5mm 376S0953 MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm DIDT=TRUE ISL95870 1% 1/16W MF-LF 402 C9830 68UF 20% 16V POLY-TANT CASE-D2E-SM PCHVCCIOS0_VBST U9800 3.01K C9821 68UF VCC PLACE_NEAR=U1800.BJ6:1MM OMIT_TABLE CRITICAL 14 97 C9820 5% 1/10W MF-LF 603 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5V SM 20% 10V X5R 603 PP5V_S0_PCHVCCIOS0_VCC XW9802 13 C OMIT_TABLE CRITICAL MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm DIDT=TRUE 10UF 2.2 PLACE_NEAR=U1800.BJ8:1MM C9801 BOOT 12 UGATE 11 PHASE 10 LGATE 15 CRITICAL MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm GATE_NODE=TRUE DIDT=TRUE CRITICAL Q9830 PCHVCCIOS0_DRVH RJK0214DPA CRITICAL WPAK2 L9830 0.001 1% 1W MF-1 0612 0.68UH-20%-23A-0.0034OHM PCHVCCIOS0_LL R9840 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm SWITCH_NODE=TRUE DIDT=TRUE PIMB103T 152S1651 PPPCHVCCIO_S0_REG_R MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V =PPPCHVCCIO_S0_REG CRITICAL C9849 OUT PCHVCCIOS0_PGOOD PGOOD PCHVCCIOS0_RTN RTN PCHVCCIOS0_DRVL FSEL MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm GATE_NODE=TRUE DIDT=TRUE C9823 20% 2V TANT CASE-B4-SM 1000PF 1% 1/16W MF-LF 402 2 GND 2.74K B PCHVCCIOS0_FSEL R9845 1% 1/16W MF-LF 402 C9802 C9804 1 10PF 5% 50V C0G-CERM 0402 2 C9805 2 0.047UF 5% 50V C0G-CERM 0402 10% 16V X7R-CERM 0402 C9848 270UF 20% 2V TANT CASE-B4-SM 5% 1/16W MF-LF 402 C9803 10PF R9803 CRITICAL 2.2UF 10% 16V X5R 603 PGND 12A MAX OUTPUT f = 300 kHz 16 2.74K R9805 5% 25V NP0-C0G 402 270UF PLACE_NEAR=L9830.2:1.5mm 70 87 Vout = 1.05V R9841 XW9800 PCHVCCIOS0_CS_P 99 97 PCHVCCIOS0_CS_N B 2.0K SM PCHVCCIOS0_AGND 99 97 1% 1/16W MF-LF 402 2 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0V C9840 1000PF PLACE_NEAR=U9800.1:1mm 5% 25V NP0-C0G 402 R9842 2.0K 1% 1/16W MF-LF 402 (PCHVCCIOS0_OCSET) (PCHVCCIOS0_VO) OCP = R9841 x 8.5uA / R9840 OCP = 14.4A A SYNC_MASTER=D2_KEPLER SYNC_DATE=01/13/2012 PAGE TITLE PCH VCCIO (1.05V) POWER SUPPLY DRAWING NUMBER Apple Inc 051-9589 R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED SIZE D REVISION 4.18.0 BRANCH PAGE 98 OF 132 SHEET 87 OF 99 A EXT GPU PWRGD Pullup =PP3V3_S0_PWRCTL 88 70 Unused PGOOD signal GPU Rail Sequencing R9900 KEPLER GPU REQUIRES RAILS TO COME up in the following order: 1) GPU_3.3V 2) IFPX IOVDD - 1.8V D R9901 100K 100K 5% 1/20W MF 201 5% 1/20W MF 201 R9902 100K 5% 1/20W MF 201 88 70 D =PP3V3_S0_PWRCTL 3) GPUVCORE NO STUFF 4) FBVDDQ/GDDR5 1.35V 5) PEXVDD/Q R9991 OR IFPY IOVDD - 1.05V =P3V3GPU_MISC_EN 82 EG_RAIL1_EN P3V3GPU_EN EG_RAIL2_EN P1V8GPU_EN EG_RAIL3_EN =P1V35FB_EN MAKE_BASE=TRUE 82 EG_RAIL5_EN P1V05_S0GPU_EN 69 IN =PP3V3_S0GPU_FET GPU_PGOOD1 OUT 82 IN =PP1V8_GPU_FET GPU_PGOOD2 OUT 82 80 IN GPUVCORE_PGOOD GPU_PGOOD3 OUT 82 74 IN GPUFB_PGOOD OUT 82 74 IN OUT 82 MAKE_BASE=TRUE 5% 1/16W MF-LF 402 TP_DDRREG_PGOOD 80 OUT P1V35GPUFB_EN OUT 74 OUT 74 10K =GPUVCORE_EN MAKE_BASE=TRUE 82 69 OUT GPUVCORE_EN EG_RAIL4_EN OUT =P1V8GPU_EN MAKE_BASE=TRUE 82 69 =P3V3GPU_EN MAKE_BASE=TRUE 82 OUT GPU_PGOOD4 MAKE_BASE=TRUE P1V05_S0GPU_PGOOD MAKE_BASE=TRUE CPUIMVP_AXG_PGOOD IN 65 DDRREG_PGOOD IN 64 P1V5S3RS0_RAMP_DONE IN 69 MAKE_BASE=TRUE TP_P1V5S3RS0_RAMP_DONE PM_ALL_GPU_PGOOD MAKE_BASE=TRUE NOTE: NO PU ON 3V3 AND 1V8 PGOODS SINCE THEY ARE SYNTHETIC =P1V05_GPU_EN MAKE_BASE=TRUE NOTE 2: CHECK IF 1V8 IS READ AS LOGIC HIGH BY GMUX NOTE: 1V8 MAY NOT BE REQUIRED FOR KEPLER IF THERE IS NO LVDS C C PEG_R2D_P PEG_R2D_P 71 89 71 89 1 R9910 R9915 82 82 5% 1/20W MF 201 5% 1/20W MF 201 NOSTUFF NOSTUFF PEG_R2D_N PEG_R2D_N 71 89 71 89 PEG_R2D_P PEG_R2D_P 71 89 71 89 1 R9913 R9917 82 82 5% 1/20W MF 201 5% 1/20W MF 201 NOSTUFF NOSTUFF PEG_R2D_N PEG_R2D_N 71 89 71 89 PLACE R9910 - R9917 CLOSE TO U8000 B B PCIE TEST STRUCTURES (FOR LAB USE) PEG_D2R_P PEG_D2R_P 71 89 71 89 R9924 R9920 82 82 5% 1/20W MF 201 5% 1/20W MF 201 NOSTUFF NOSTUFF PEG_D2R_N PEG_D2R_N 71 89 71 89 PEG_D2R_P 71 89 R9927 82 5% 1/20W MF 201 A NOSTUFF SYNC_MASTER=D2_KEPLER PEG_D2R_N SYNC_DATE=01/13/2012 PAGE TITLE 71 89 Power Sequencing EG/PCH S0 PLACE R9920 - R9927 CLOSE TO U1000 DRAWING NUMBER Apple Inc 051-9589 R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED SIZE D REVISION 4.18.0 BRANCH PAGE 99 OF 132 SHEET 88 OF 99 A CPU Signal Constraints CPU Net Properties TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP CPU_50S * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD NET_TYPE ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING TABLE_PHYSICAL_RULE_ITEM DMI_S2N PCIE_85D PCIE DMI_S2N PCIE_85D PCIE DMI_N2S PCIE_85D PCIE DMI_N2S PCIE_85D PCIE FDI_DATA PCIE_85D PCIE TABLE_PHYSICAL_RULE_ITEM CPU_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD TABLE_PHYSICAL_RULE_ITEM CPU_27P4S * =27P4_OHM_SE =27P4_OHM_SE =27P4_OHM_SE =27P4_OHM_SE MIL MIL NOTE: mil gap is for VCCSense pair, which Intel says to route with mil spacing without specifying a target impedance TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING SPACING_RULE_SET LAYER LINE-TO-LINE SPACING D CPU_AGTL * =STANDARD CPU_AGTL TOP,BOTTOM =2x_DIELECTRIC CPU_8MIL * CPU_VID * 0.457 MM ? TABLE_SPACING_RULE_ITEM CPU_COMP * 20 MIL ? CPU_ITP * =2:1_SPACING ? PCIE_85D PCIE CPU_AGTL CPU_50S CPU_AGTL FDI_INT CPU_50S CPU_AGTL FDI_LSYNC FDI_INT I125 DMI_CLK100M CLK_PCIE_90D CLK_PCIE DMI_CLK100M_CPU_P 11 17 I126 DMI_CLK100M CLK_PCIE_90D CLK_PCIE DMI_CLK100M_CPU_N 11 17 I127 DP_INT_ML DP_85D DISPLAYPORT I128 DP_INT_ML DP_85D DISPLAYPORT DP_INT_IG_ML_P DP_INT_IG_ML_N I129 DP_INT_AUX DP_85D DISPLAYPORT I131 DP_INT_AUX DP_85D DISPLAYPORT I132 CPU_EDP_COMP CPU_27P4S CPU_COMP I130 CPU_PEG_COMP CPU_27P4S CPU_COMP I133 CPU_CFG CPU_50S CPU_ITP XDP_CLK_CPU CLK_PCIE_90D CLK_PCIE XDP_CLK_CPU CLK_PCIE_90D CLK_PCIE XDP_CLK_PCH CLK_PCIE_90D CLK_PCIE XDP_CLK_PCH CLK_PCIE_90D CLK_PCIE DPLL_REF_CLK120M CLK_PCIE_90D CLK_PCIE CLK_PCIE 10 10 10 D 10 18 TABLE_SPACING_RULE_ITEM ? MIL 10 18 CPU_50S ? TABLE_SPACING_RULE_ITEM 10 18 10 FDI_DATA TABLE_SPACING_RULE_ITEM ? 10 18 FDI_LSYNC WEIGHT TABLE_SPACING_RULE_ITEM 10 18 FDI_FSYNC TABLE_SPACING_RULE_HEAD WEIGHT DMI_S2N_P DMI_S2N_N DMI_N2S_P DMI_N2S_N FDI_DATA_P FDI_DATA_N FDI_FSYNC TABLE_SPACING_RULE_ITEM CPU_VREF * 12 MIL ? TABLE_SPACING_RULE_ITEM 10 82 10 82 TABLE_SPACING_RULE_ITEM CPU_VCCSENSE * 25 MIL ? Most CPU signals with impedance requirements are 50-ohm single-ended Some signals require 27.4-ohm single-ended impedance SOURCE: IVB PLATFORM DG , Tables 205-207 PCI-Express TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM PCIE_85D * =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF I138 TABLE_PHYSICAL_RULE_ITEM CLK_PCIE_90D * =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT 15 MIL ? SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT 15 MIL ? TABLE_SPACING_RULE_ITEM PCIE * DPLL_REF_CLK120M CLK_PCIE_90D XDP_TDI CPU_50S CPU_ITP XDP_TDO CPU_50S CPU_ITP XDP_TMS CPU_50S CPU_ITP XDP_TCK CPU_50S CPU_ITP XDP_TRST_L CPU_50S CPU_ITP XDP_BPM CPU_50S CPU_ITP XDP_BPM_L CPU_50S CPU_ITP I134 XDP_BDRESET_L CPU_50S CPU_ITP I135 XDP_PRDY_L CPU_50S CPU_ITP I136 XDP_PREQ_L CPU_50S CPU_ITP CPU_CATERR_L CPU_50S CPU_AGTL CPU_PROC_SEL_L CPU_50S CPU_AGTL CPU_PECI CPU_50S CPU_VID CPU_PROCHOT_L CPU_50S CPU_AGTL XDP_CPU_PWRGD CPU_50S CPU_ITP PM_THRMTRIP_L CPU_50S CPU_8MIL I139 TABLE_SPACING_RULE_HEAD TABLE_SPACING_RULE_ITEM PCIE TOP,BOTTOM TABLE_SPACING_RULE_ITEM CLK_PCIE * 20 MIL ? C I115 PEG TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? PEG_80D * =80_OHM_DIFF MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP =80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF TABLE_PHYSICAL_RULE_ITEM I150 PM_SYNC CPU_50S CPU_AGTL PM_MEM_PWRGD CPU_50S CPU_AGTL CPU_PWRGD CPU_50S CPU_AGTL CPU_SM_RCOMP DP_INT_IG_AUX_P DP_INT_IG_AUX_N CPU_EDP_COMP CPU_PEG_COMP CPU_CFG ITPCPU_CLK100M_P ITPCPU_CLK100M_N ITPXDP_CLK100M_P ITPXDP_CLK100M_N DPLL_REF_CLKP DPLL_REF_CLKN XDP_CPU_TDI XDP_CPU_TDO XDP_CPU_TMS XDP_CPU_TCK XDP_CPU_TRST_L XDP_BPM_L XDP_BPM_L XDP_DBRESET_L XDP_CPU_PRDY_L XDP_CPU_PREQ_L CPU_CATERR_L CPU_PROC_SEL_L CPU_PECI CPU_PROCHOT_L XDP_CPU_PWRGD PM_THRMTRIP_L PM_SYNC PM_MEM_PWRGD CPU_PWRGD CPU_SM_RCOMP 10 82 10 82 10 10 10 24 11 17 11 17 17 24 17 24 11 11 11 24 11 24 11 24 11 24 11 24 11 24 11 24 11 24 25 11 24 C 11 24 11 41 11 20 11 20 42 11 41 42 65 24 11 20 42 11 18 11 18 27 11 20 24 CPU_27P4S CPU_COMP CPU_50S CPU_VID CPU_VIDSOUT 13 65 CPU_50S CPU_VID CPU_VIDSCLK 13 65 CPU_50S 11 TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM PEG_RXRX * =4X_DIELECTRIC ? PEG_TXTX * =4X_DIELECTRIC ? CPU_VID CPU_VIDALERT_L CPU_55S CPU_VID CPU_VCCSA_VID CPU_VCCSENSE CPU_27P4S CPU_VCCSENSE CPU_VCCSENSE CPU_27P4S CPU_VCCSENSE CPU_VCCSENSE_P CPU_VCCSENSE_N CPU_VCCSENSE CPU_27P4S CPU_VCCSENSE CPU_VCCIOSENSE_P 13 67 CPU_VCCSENSE CPU_27P4S CPU_VCCSENSE CPU_VCCIOSENSE_N 13 67 CPU_VCCSENSE CPU_27P4S CPU_VCCSENSE CPU_AXG_SENSE_P 13 65 CPU_VCCSENSE CPU_27P4S CPU_VCCSENSE CPU_AXG_SENSE_N I120 CPU_VCCSENSE CPU_27P4S CPU_VCCSENSE CPU_VCC_VALSENSE_P 13 I121 CPU_VCCSENSE CPU_27P4S CPU_VCCSENSE CPU_VCC_VALSENSE_N 13 I122 CPU_VCCSENSE CPU_27P4S CPU_VCCSENSE I123 CPU_VCCSENSE CPU_27P4S CPU_VCCSENSE CPU_AXG_VALSENSE_N 13 I137 CPU_VCCSASENSE CPU_50S CPU_AGTL CPU_VCCSASENSE 13 62 PPCPU_MEM_VREFDQ_A PPCPU_MEM_VREFDQ_B 13 65 TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM PEG_TXRX * =10X_DIELECTRIC ? 13 62 13 65 13 65 TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET TABLE_SPACING_ASSIGNMENT_ITEM PEG_D2R PEG_D2R * PEG_RXRX PEG_R2D PEG_R2D * PEG_TXTX TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM PEG_D2R PEG_R2D * PEG_TXRX B I140 CPU_MEM_VREF CPU_VREF I141 CPU_MEM_VREF CPU_VREF I144 CPU_MEM_VREF CPU_VREF I145 CPU_MEM_VREF CPU_VREF I146 CPU_MEM_VREF CPU_VREF I147 CPU_MEM_VREF CPU_VREF I148 XDP_CLK_ITP CLK_PCIE_90D CLK_PCIE I149 XDP_CLK_ITP CLK_PCIE_90D CLK_PCIE PEG_R2D PEG_D2R PEG_80D PEG_R2D PEG_80D PEG_R2D PEG_80D PEG_R2D PEG_80D PEG_R2D PEG_80D A PEG_D2R PEG_80D PEG_D2R PEG_80D PEG_D2R PEG_80D PEG_D2R CPU_AXG_VALSENSE_P PP0V75_S3_MEM_VREFDQ_A PP0V75_S3_MEM_VREFDQ_B PP0V75_S3_MEM_VREFCA_A PP0V75_S3_MEM_VREFCA_B XDP_CPU_CLK100M_P XDP_CPU_CLK100M_N PEG_R2D_P PEG_R2D_N PEG_R2D_C_P PEG_R2D_C_N PEG_D2R_P PEG_D2R_N PEG_D2R_C_P PEG_D2R_C_N 13 65 13 B 10 33 10 33 28 29 33 30 31 33 28 29 33 30 31 33 24 24 71 88 71 88 71 71 71 88 71 88 71 71 SYNC_MASTER=D2_KEPLER SYNC_DATE=01/13/2012 PAGE TITLE CPU Constraints DRAWING NUMBER Apple Inc 051-9589 R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED SIZE D REVISION 4.18.0 BRANCH PAGE 100 OF 132 SHEET 89 OF 99 A Memory Bus Constraints Memory Net Properties TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP MEM_37S * =37_OHM_SE =37_OHM_SE =37_OHM_SE =37_OHM_SE =STANDARD =STANDARD MEM_40S * =40_OHM_SE =40_OHM_SE =40_OHM_SE =40_OHM_SE =STANDARD =STANDARD ELECTRICAL_CONSTRAINT_SET NET_TYPE SPACING PHYSICAL TABLE_PHYSICAL_RULE_ITEM MEM_A_CLK MEM_A_CLK MEM_72D MEM_72D MEM_CLK MEM_CLK MEM_A_CLK_P MEM_A_CLK_N MEM_A_CNTL MEM_A_CNTL MEM_A_CNTL1 MEM_A_CNTL MEM_37S MEM_37S MEM_37S MEM_37S MEM_CTRL MEM_CTRL MEM_CTRL MEM_CTRL MEM_A_CKE MEM_A_CS_L MEM_A_CS_L MEM_A_CS_L MEM_A_CNTL MEM_A_CNTL1 MEM_A_CNTL MEM_A_CMD MEM_A_CMD MEM_A_CMD MEM_A_CMD MEM_A_CMD MEM_37S MEM_37S MEM_37S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_CTRL MEM_CTRL MEM_CTRL MEM_CMD MEM_CMD MEM_CMD MEM_CMD MEM_CMD MEM_A_ODT MEM_A_ODT MEM_A_ODT MEM_A_A MEM_A_BA MEM_A_RAS_L MEM_A_CAS_L MEM_A_WE_L MEM_A_DQ_BYTE0 MEM_A_DQ_BYTE1 MEM_A_DQ_BYTE2 MEM_A_DQ_BYTE3 MEM_A_DQ_BYTE4 MEM_A_DQ_BYTE5 MEM_A_DQ_BYTE6 MEM_A_DQ_BYTE7 MEM_50S MEM_50S MEM_50S MEM_50S MEM_50S MEM_50S MEM_50S MEM_50S MEM_A_DQ_BYTE0 MEM_A_DQ_BYTE1 MEM_A_DQ_BYTE2 MEM_A_DQ_BYTE3 MEM_A_DQ_BYTE4 MEM_A_DQ_BYTE5 MEM_A_DQ_BYTE6 MEM_A_DQ_BYTE7 MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQS0 MEM_A_DQS0 MEM_A_DQS1 MEM_A_DQS1 MEM_A_DQS2 MEM_A_DQS2 MEM_A_DQS3 MEM_A_DQS3 MEM_A_DQS4 MEM_A_DQS4 MEM_A_DQS5 MEM_A_DQS5 MEM_A_DQS6 MEM_A_DQS6 MEM_A_DQS7 MEM_A_DQS7 MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_B_CLK MEM_B_CLK MEM_72D MEM_72D MEM_CLK MEM_CLK MEM_B_CLK_P MEM_B_CLK_N MEM_B_CNTL MEM_37S MEM_CTRL MEM_B_CKE I111 MEM_B_CNTL1 MEM_B_CNTL0 MEM_37S MEM_37S MEM_CTRL MEM_CTRL MEM_B_CKE MEM_B_CKE I109 MEM_B_CNTL MEM_B_CNTL MEM_B_CNTL0 MEM_37S MEM_37S MEM_37S MEM_CTRL MEM_CTRL MEM_CTRL MEM_B_CS_L MEM_B_ODT MEM_B_ODT MEM_B_CMD MEM_B_CMD6 MEM_B_CMD MEM_B_CMD MEM_B_CMD MEM_B_CMD MEM_B_CMD MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_CMD MEM_CMD MEM_CMD MEM_CMD MEM_CMD MEM_CMD MEM_CMD MEM_B_A MEM_B_A MEM_B_A MEM_B_BA MEM_B_RAS_L MEM_B_CAS_L MEM_B_WE_L MEM_B_DQ_BYTE0 MEM_B_DQ_BYTE1 MEM_B_DQ_BYTE2 MEM_B_DQ_BYTE3 MEM_B_DQ_BYTE4 MEM_B_DQ_BYTE5 MEM_B_DQ_BYTE6 MEM_B_DQ_BYTE7 MEM_50S MEM_50S MEM_50S MEM_50S MEM_50S MEM_50S MEM_50S MEM_50S MEM_B_DQ_BYTE0 MEM_B_DQ_BYTE1 MEM_B_DQ_BYTE2 MEM_B_DQ_BYTE3 MEM_B_DQ_BYTE4 MEM_B_DQ_BYTE5 MEM_B_DQ_BYTE6 MEM_B_DQ_BYTE7 MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQS0 MEM_B_DQS0 MEM_B_DQS1 MEM_B_DQS1 MEM_B_DQS2 MEM_B_DQS2 MEM_B_DQS3 MEM_B_DQS3 MEM_B_DQS4 MEM_B_DQS4 MEM_B_DQS5 MEM_B_DQS5 MEM_B_DQS6 MEM_B_DQS6 MEM_B_DQS7 MEM_B_DQS7 MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N TABLE_PHYSICAL_RULE_ITEM 12 28 29 32 12 28 29 32 TABLE_PHYSICAL_RULE_ITEM MEM_72D * =72_OHM_DIFF =72_OHM_DIFF =72_OHM_DIFF =72_OHM_DIFF =72_OHM_DIFF =72_OHM_DIFF MEM_50S * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD TABLE_PHYSICAL_RULE_ITEM I101 TABLE_PHYSICAL_RULE_ITEM MEM_85D D * =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF I102 TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT =4:1_SPACING ? I103 TABLE_SPACING_RULE_ITEM MEM_CLK2MEM * I104 TABLE_SPACING_RULE_ITEM MEM_CTRL2CTRL * =3:1_SPACING ? MEM_CTRL2MEM * =2.5:1_SPACING ? MEM_CMD2CMD * =1.5:1_SPACING ? TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM 12 28 29 32 12 29 32 12 28 32 D 12 29 32 12 28 32 12 28 29 32 12 28 29 32 12 28 29 32 12 28 29 32 12 28 29 32 TABLE_SPACING_RULE_ITEM MEM_CMD2MEM * =3:1_SPACING ? MEM_DATA2DATA * =1.5:1_SPACING ? MEM_DATA2MEM * =3:1_SPACING ? TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM MEM_DQS2MEM * =3:1_SPACING ? MEM_2OTHER * 25 MILS ? TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM MEM_DQBL2BL * 16 MILS ? MEM_DQCH2CH * 25 MILS ? I105 TABLE_SPACING_RULE_ITEM I106 Memory Bus Spacing Group Assignments TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE TABLE_SPACING_ASSIGNMENT_ITEM MEM_CLK MEM_* * MEM_CLK2MEM SPACING_RULE_SET TABLE_SPACING_ASSIGNMENT_ITEM MEM_CMD MEM_* * MEM_CMD2MEM MEM_CMD MEM_CMD * MEM_CMD2CMD TABLE_SPACING_ASSIGNMENT_ITEM C TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET MEM_CTRL MEM_* * MEM_CTRL2MEM TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET MEM_*_DQ_BYTE* MEM_* * MEM_DATA2MEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CTRL MEM_CTRL * MEM_CTRL2CTRL TABLE_SPACING_ASSIGNMENT_ITEM MEM_*_DQ_BYTE* =SAME * MEM_DATA2DATA MEM_A_DQ_BYTE* MEM_A_DQ_BYTE* * MEM_DQBL2BL TABLE_SPACING_ASSIGNMENT_ITEM 12 28 29 12 28 29 12 28 29 12 28 29 12 28 29 12 28 29 12 28 29 12 28 29 12 28 29 12 28 29 12 28 29 12 28 29 12 28 29 12 28 29 12 28 29 12 28 29 12 28 29 12 28 29 C 12 28 29 12 28 29 12 28 29 12 28 29 12 28 29 12 28 29 TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET TABLE_SPACING_ASSIGNMENT_ITEM MEM_B_DQ_BYTE* MEM_B_DQ_BYTE* * MEM_DQBL2BL MEM_A_DQ_BYTE* MEM_B_DQ_BYTE* * MEM_DQCH2CH TABLE_SPACING_ASSIGNMENT_ITEM MEM_DQS MEM_* * MEM_DQS2MEM NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET MEM_* * * MEM_2OTHER TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_HEAD TABLE_SPACING_ASSIGNMENT_ITEM I110 DDR3 (Memory Down): DQ signals should be matched within 0.508mm of associated DQS pair DQS intra-pair matching should be within 0.127mm, no inter-pair matching requirement DQS to clock matching should be within [CLK-139.73mm] and [CLK-30.48mm] CLK intra-pair matching should be within 0.127mm, inter-pair matching should be within 0.508mm CONTROL signals should be matched within [CLK-2.54mm] to [CLK+0mm] of CLK pairs A/BA/CMD signals should be matched within [CLK-2.54mm] to [CLK+2.54mm] of CLK pairs DQ/DQS/A/BA/cmd signal spacing is 4x dielectric, CLK is 5x dielectric Maximum length of any signal from die pad to first DRAM device is 139.7mm max, to last DRAM device is 194.31mm max I108 I107 SOURCE: Chief River SFF Platform DG, Rev 0.7 (#460452), Section 2.6.3 B A 12 30 31 32 12 30 31 32 12 31 32 12 30 32 12 30 31 32 12 31 32 12 30 32 12 30 31 32 12 30 31 32 12 30 31 32 B 12 30 31 32 12 30 31 32 12 30 31 32 12 30 31 32 12 30 31 12 30 31 12 30 31 12 30 31 12 30 31 12 30 31 12 30 31 12 30 31 12 30 31 12 30 31 12 30 31 12 30 31 12 30 31 12 30 31 12 30 31 12 30 31 12 30 31 12 30 31 12 30 31 12 30 31 12 30 31 12 30 31 12 30 31 SYNC_MASTER=D2_KEPLER SYNC_DATE=01/13/2012 PAGE TITLE Memory Constraints 12 30 31 DRAWING NUMBER Apple Inc 051-9589 R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED SIZE D REVISION 4.18.0 BRANCH PAGE 101 OF 132 SHEET 90 OF 99 A Digital Video Signal Constraints PCH Net Properties TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET ALLOW ROUTE ON LAYER? LAYER MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP NET_TYPE TABLE_PHYSICAL_RULE_ITEM PCH_DP_90D * =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF LVDS_85D * =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF SPACING_RULE_SET LAYER ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_HEAD LINE-TO-LINE SPACING TABLE_SPACING_RULE_HEAD WEIGHT SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM PCH_DISPLAYPORT ISL3,ISL4,ISL9,ISL10 =4:1_SPACING TABLE_SPACING_RULE_ITEM ? PCH_DISPLAYPORT TOP,BOTTOM =4:1_SPACING ? LVDS TOP,BOTTOM =4:1_SPACING ? TABLE_SPACING_RULE_ITEM LVDS D ISL3,ISL4,ISL9,ISL10 =4:1_SPACING TABLE_SPACING_RULE_ITEM ? LVDS_85D LVDS LVDS_IG_A_CLK LVDS_85D LVDS LVDS_85D LVDS LVDS_IG_A_DATA LVDS_85D LVDS LVDS_IG_A_DATA3 LVDS_85D LVDS LVDS_IG_A_DATA3 LVDS_85D LVDS LVDS_IG_B_DATA LVDS_85D LVDS LVDS_IG_B_DATA LVDS_85D LVDS SATA_HDD_R2D SATA_90D SATA SATA_90D SATA SATA_90D SATA SATA_90D SATA SATA_90D SATA SATA_90D SATA SATA_90D SATA SATA_90D SATA SATA_90D SATA SATA_90D SATA SATA_90D SATA SATA_90D SATA LVDS_IG_B_DATA_P LVDS_IG_B_DATA_N SATA_HDD_R2D_C_P SATA_HDD_R2D_C_N SATA_HDD_D2R_P SATA_HDD_D2R_N SATA_SSD_D2R_MUX_OUT_P SATA_SSD_D2R_MUX_OUT_N SATA_SSD_R2D_MUX_IN_P SATA_SSD_R2D_MUX_IN_N SATA_SSD_D2R_P SATA_SSD_D2R_N SATA_SSD_R2D_P SATA_SSD_R2D_N SATA_90D SATA SATA_HDD_R2D_UF_P SATA_90D SATA SATA_HDD_R2D_UF_N SATA_90D SATA SATA_90D SATA SATA_90D SATA SATA_90D SATA SATA_90D SATA SATA_90D SATA SATA_90D SATA SOURCE: HR PLATFORM DESIGN GUIDE, TABLES 191,193 SATA Interface Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP SATA_90D * =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF TABLE_PHYSICAL_RULE_ITEM SATA_HDD_D2R TABLE_PHYSICAL_RULE_ITEM SATA_37SE * =37_OHM_SE =37_OHM_SE =37_OHM_SE =37_OHM_SE =37_OHM_SE =37_OHM_SE SATA_HDD_D2R TABLE_PHYSICAL_RULE_ITEM SATA_50SE * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE SATA_HDD_R2D TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT =5:1_SPACING ? TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT =5:1_SPACING ? TABLE_SPACING_RULE_ITEM SATA ISL3,ISL4,ISL9,ISL10 I232 TOP,BOTTOM SATA_HDD_D2R I233 TABLE_SPACING_RULE_ITEM SATA I234 SATA_HDD_R2D TABLE_SPACING_RULE_ITEM SATA_ICOMP * 15 MIL I235 ? I218 LVDS_IG_A_CLK_P LVDS_IG_A_CLK_N LVDS_IG_A_DATA_P LVDS_IG_A_DATA_N LVDS_IG_A_DATA_P LVDS_IG_A_DATA_N LVDS_IG_A_CLK LVDS_IG_A_DATA SATA_HDD_R2D I219 18 18 18 D 18 18 18 18 18 17 39 17 39 17 39 17 39 39 39 39 39 39 39 39 39 SOURCE: HR PLATFORM DESIGN GUIDE, TABLES 191,193 SATA_90D SATA SATA_ODD_R2D_C_P SATA_ODD_R2D_C_N SATA_ODD_R2D_P SATA_ODD_R2D_N SATA_ODD_D2R_P SATA_ODD_D2R_N SATA_ODD_D2R_UF_P SATA_ODD_D2R_UF_N PCH_SATA3_ICOMP SATA_50SE SATA_ICOMP PCH_SATA3COMP 17 PCH_SATA_ICOMP SATA_37SE SATA_ICOMP PCH_SATAICOMP 17 USB_HUB1_UP USB_85D USB USB_85D USB USB_85D USB USB_85D USB USB_85D USB USB_85D USB USB_85D USB USB_85D USB USB_85D USB USB_85D USB USB_85D USB USB_85D USB USB_85D USB USB_85D USB USB_85D USB USB_85D USB USB_85D USB USB_85D USB USB_85D USB USB_85D USB USB_85D USB USB_85D USB USB_IR USB_85D USB USB_85D USB PCH_USB_RBIAS PCH_USB_RBIAS USB_RBIAS USB_T29A USB_85D USB USB_85D USB USB_85D USB USB_85D USB USB_85D USB USB_85D USB USB_85D USB USB_85D USB USB_85D USB3 USB_85D USB3 USB_85D USB3 USB_85D USB3 USB_85D USB3 USB_85D USB3 USB_85D USB3 USB_85D USB3 USB_85D USB3 USB_85D USB3 USB_85D USB3 USB_85D USB3 USB_EXTB_XHCI_P USB_EXTB_XHCI_N USB_EXTB_EHCI_P USB_EXTB_EHCI_N USB_HUB_UP_P USB_HUB_UP_N USB_EXTA_P USB_EXTA_N USB_EXTB_P USB_EXTB_N USB_EXTC_P USB_EXTC_N USB_CAMERA_CONN_P USB_CAMERA_CONN_N USB_BT_P USB_BT_N USB_BT_CONN_P USB_BT_CONN_N USB_BT_WAKE_P USB_BT_WAKE_N USB_TPAD_P USB_TPAD_N USB_SMC_P USB_SMC_N PCH_USB_RBIAS USB_EXTD_XHCI_P USB_EXTD_XHCI_N USB_EXTA_MUXED_P USB_EXTA_MUXED_N USB_CAMERA_P USB_CAMERA_N USB_LT1_P USB_LT1_N USB3_EXTB_TX_P USB3_EXTB_TX_N USB3_EXTB_RX_P USB3_EXTB_RX_N USB3_EXTC_TX_P USB3_EXTC_TX_N USB3_EXTC_RX_P USB3_EXTC_RX_N USB3_EXTA_TX_P USB3_EXTA_TX_N USB3_EXTA_RX_P USB3_EXTA_RX_N SATA_ODD_R2D SATA_ODD_R2D C SATA_ODD_D2R SATA_ODD_D2R USB 2.0 Interface Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET ALLOW ROUTE ON LAYER? LAYER MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP I213 DIFFPAIR NECK GAP 17 17 C 17 17 TABLE_PHYSICAL_RULE_ITEM PCH_USB_RBIAS * =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD I236 TABLE_PHYSICAL_RULE_ITEM USB_85D * =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF I237 USB_HUB1_UP TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT =4:1_SPACING ? TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT =4:1_SPACING ? USB_HUB2_UP TABLE_SPACING_RULE_ITEM USB ISL3,ISL4,ISL9,ISL10 TABLE_SPACING_RULE_ITEM USB TOP,BOTTOM TABLE_SPACING_RULE_ITEM USB_RBIAS * 15 MIL USB_EXTA ? USB_EXTB USB_EXTC SOURCE: HR PLATFORM DESIGN GUIDE, TABLES 191,193 USB_CAMERA USB_BT USB_BT USB 3.0 INTERFACE CONSTRAINTS I260 TABLE_SPACING_RULE_HEAD B SPACING_RULE_SET LAYER LINE-TO-LINE SPACING SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM USB3 ISL3,ISL4,ISL9,ISL10 =5:1_SPACING I259 TABLE_SPACING_RULE_HEAD WEIGHT USB_BT USB_TPAD TABLE_SPACING_RULE_ITEM ? USB3 TOP,BOTTOM =5:1_SPACING ? SOURCE: CR SFF PLATFORM DESIGN GUIDE V0.7, TABLE 4-211, 1X1+ I238 I239 I245 System Clock Signal Constraints I244 TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH =55_OHM_SE =55_OHM_SE MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP I247 DIFFPAIR NECK GAP * =55_OHM_SE =55_OHM_SE =STANDARD USB_CAMERA I246 TABLE_PHYSICAL_RULE_ITEM CLK_SLOW_55S USB_EXTA =STANDARD I248 USB_EXTA TABLE_PHYSICAL_RULE_ITEM CLK_25M_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD I249 =STANDARD I220 I221 TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING USB3_EXTB_TX WEIGHT I222 USB3_EXTB_RX TABLE_SPACING_RULE_ITEM CLK_SLOW * =2x_DIELECTRIC I223 ? I224 TABLE_SPACING_RULE_ITEM CLK_25M * =5x_DIELECTRIC ? NOTE: 25MHz system clocks very sensitive to noise USB3_EXTC_TX I225 I226 USB3_EXTC_RX I227 I230 USB3_EXTA_TX I229 I228 USB3_EXTA_RX I231 A 19 26 19 26 19 26 19 26 19 26 19 26 19 40 19 40 26 38 26 38 19 19 34 34 34 34 34 34 34 34 49 41 41 19 19 26 19 26 40 40 19 34 19 34 40 40 19 38 19 38 19 38 19 38 19 19 19 19 19 40 19 40 19 40 19 40 Clock Net Properties ELECTRICAL_CONSTRAINT_SET B 49 SYNC_MASTER=D2_KEPLER SYNC_DATE=01/13/2012 PAGE TITLE NET_TYPE PHYSICAL SPACING PCH Constraints DRAWING NUMBER I256 I255 SYSCLK_CLK32K_RTC SYSCLK_CLK25M_SB I254 I253 SYSCLK_CLK25M_ENET I252 I251 SYSCLK_CLK25M_TBT I250 CLK_SLOW_55S CLK_25M_55S CLK_25M_55S CLK_25M_55S CLK_25M_55S CLK_25M_55S CLK_25M_55S CLK_SLOW CLK_25M CLK_25M CLK_25M CLK_25M CLK_25M CLK_25M SYSCLK_CLK32K_RTC SYSCLK_CLK25M_SB SYSCLK_CLK25M_SB_R SYSCLK_CLK25M_ENET SYSCLK_CLK25M_ENET_R SYSCLK_CLK25M_TBT SYSCLK_CLK25M_TBT_R 17 25 Apple Inc R 17 25 17 25 35 35 051-9589 NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED SIZE D REVISION 4.18.0 BRANCH PAGE 102 OF 132 SHEET 91 OF 99 A LPC Bus Constraints PCH Net Properties TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP NET_TYPE TABLE_PHYSICAL_RULE_ITEM LPC_50S * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD CLK_LPC_50S * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT MIL ? TABLE_SPACING_RULE_ITEM LPC * LPC_AD LPC_FRAME_L LPC_RESET_L LPC_AD LPC_50S LPC LPC_FRAME_L LPC_50S LPC LPC_RESET_L LPC_50S LPC PCH_LPC_CLK0 CLK_LPC_50S CLK_LPC CLK_LPC_50S CLK_LPC CLK_LPC_50S CLK_LPC SMBUS_PCH_CLK SMB_50S SMB SMBUS_PCH_DATA SMB_50S SMB SMBUS_PCH_0_CLK SMB_50S SMB SMBUS_PCH_0_DATA SMB_50S SMB SMBUS_PCH_1_CLK SMB_50S SMB SMBUS_PCH_1_DATA SMB_50S SMB HDA_BIT_CLK HDA_50S HDA HDA_50S HDA HDA_50S HDA HDA_50S HDA HDA_50S HDA HDA_50S HDA HDA_50S HDA HDA_50S HDA HDA_50S HDA HDA_50S HDA SPI_55S SPI SPI_55S SPI SPI_55S SPI SPI_55S SPI SPI_MISO SPI_55S SPI SPI_CS0 SPI_55S SPI SPI_55S SPI PCIE_85D PCIE PCIE_85D PCIE PCIE_85D PCIE PCIE_85D PCIE PCIE_85D PCIE PCIE_85D PCIE PCIE_85D PCIE PCIE_85D PCIE PCIE_85D PCIE PCIE_85D PCIE PCIE_85D PCIE PCIE_85D PCIE PCIE_85D PCIE PCIE_85D PCIE PCIE_85D PCIE PCIE_85D PCIE PCIE_85D PCIE PCIE_85D PCIE TABLE_SPACING_RULE_ITEM CLK_LPC * MIL ? D SMBus Interface Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP SMBUS_PCH_CLK SMBUS_PCH_DATA SML_PCH_0_CLK SML_PCH_0_DATA SML_PCH_1_CLK SML_PCH_1_DATA DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM SMB_50S * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD HDA_BIT_CLK HDA_BIT_CLK_R HDA_SYNC HDA_SYNC_R HDA_RST_R_L HDA_RST_L HDA_SDIN0 AUD_SDI_R HDA_SDOUT HDA_SDOUT_R TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM SMB * =2x_DIELECTRIC HDA_SYNC ? HDA_RST_L HD Audio Interface Constraints HDA_SDIN0 TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP HDA_SDOUT TABLE_PHYSICAL_RULE_ITEM HDA_50S * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD LPC_CLK33M_SMC_R LPC_CLK33M_SMC LPC_CLK33M_LPCPLUS 17 41 43 82 17 41 43 82 25 19 25 25 41 25 43 D 17 44 17 44 17 44 17 44 17 44 17 44 17 53 17 17 53 17 17 17 53 17 53 53 17 53 17 25 TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT =2x_DIELECTRIC ? SPI_CLK SPI_CLK_R SPI_CLK SPI_MOSI_R SPI_MOSI SPI_MISO SPI_CS0_R_L SPI_CS0_L TABLE_SPACING_RULE_ITEM HDA * SPI_MOSI SIO Signal Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 17 43 43 17 43 43 17 43 17 43 43 TABLE_PHYSICAL_RULE_ITEM C CLK_SLOW_55S * SPACING_RULE_SET LAYER =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD TABLE_SPACING_RULE_HEAD LINE-TO-LINE SPACING PCIE_ENET_R2D WEIGHT TABLE_SPACING_RULE_ITEM CLK_SLOW * MIL ? PCIE_ENET_D2R SPI Interface Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM SPI_55S * SPACING_RULE_SET LAYER =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD PCIE_AP_R2D TABLE_SPACING_RULE_HEAD LINE-TO-LINE SPACING PCIE_AP_D2R WEIGHT PCIE_ENET_R2D_P PCIE_ENET_R2D_N PCIE_ENET_R2D_C_P PCIE_ENET_R2D_C_N PCIE_ENET_D2R_P PCIE_ENET_D2R_N PCIE_ENET_D2R_C_P PCIE_ENET_D2R_C_N PCIE_AP_R2D_P PCIE_AP_R2D_N PCIE_AP_R2D_C_P PCIE_AP_R2D_C_N PCIE_AP_D2R_P PCIE_AP_D2R_N C 17 38 17 38 17 38 17 38 34 34 17 34 17 34 17 34 17 34 TABLE_SPACING_RULE_ITEM SPI * MIL ? I275 PCIE_AP_D2R I276 I278 PCIE_AP_D2R I277 PCIE_TBT_D2R PCIE_85D PCIE PCIE_85D PCIE PCIE_85D PCIE PCIE_85D PCIE PCIE_85D PCIE PCIE_85D PCIE PCIE_85D PCIE PCIE_85D PCIE PCIE_85D PCIE PCIE_85D PCIE PCIE_85D PCIE PCIE_85D PCIE CLK_PCIE_90D CLK_PCIE CLK_PCIE_90D CLK_PCIE CLK_PCIE_90D CLK_PCIE CLK_PCIE_90D CLK_PCIE CLK_PCIE_90D CLK_PCIE CLK_PCIE_90D CLK_PCIE CLK_PCIE_90D CLK_PCIE I259 CLK_PCIE_90D CLK_PCIE I258 CPU_50S CLK_PCIE I260 CPU_50S CLK_PCIE 1:1_DIFFPAIR CLK_PCIE 1:1_DIFFPAIR CLK_PCIE CLK_PCIE_90D CLK_PCIE CLK_PCIE_90D CLK_PCIE CLK_PCIE_90D CLK_PCIE CLK_PCIE_90D CLK_PCIE CLK_PCIE_90D CLK_PCIE CLK_PCIE_90D CLK_PCIE CLK_PCIE_90D CLK_PCIE CLK_PCIE_90D CLK_PCIE CLK_PCIE_90D CLK_PCIE CLK_PCIE_90D CLK_PCIE CLK_PCIE_90D CLK_PCIE CLK_PCIE_90D CLK_PCIE PCIE_TBT_R2D PCIE_TBT_D2R PCIE_TBT_R2D B I271 PCIE_TBT_D2R I273 I274 PCIE_TBT_R2D I272 I253 PCIE_CLK100M I254 I262 PCIE_CLK100M_TBT_ I261 I255 I257 I256 I279 PCIE_CLK100M_TBT_ PCIE_CLK100M I280 PCIE_CLK100M PCIE_CLK100M_ENET PCIE_CLK100M_AP PCIE_CLK100M_FW A I281 PCIE_CLK100M_FW I282 PCIE_CLK100M_EXCARD I263 PCIE_TBT_R2D PCIE_85D PCIE I264 PCIE_TBT_R2D PCIE_85D PCIE I265 PCIE_TBT_R2D PCIE_85D PCIE I267 PCIE_TBT_R2D PCIE_85D PCIE I266 PCIE_TBT_D2R PCIE_85D PCIE I268 PCIE_TBT_D2R PCIE_85D PCIE I270 PCIE_TBT_D2R PCIE_85D PCIE I269 PCIE_TBT_D2R PCIE_85D PCIE PCIE_AP_D2R_PI_P PCIE_AP_D2R_PI_N PCIE_AP_R2D_PI_P PCIE_AP_R2D_PI_N PCIE_SSD_D2R_MUX_OUT_P PCIE_SSD_D2R_MUX_OUT_N PCIE_SSD_R2D_C_P PCIE_SSD_R2D_C_N PCIE_SSD_D2R_P PCIE_SSD_D2R_N PCIE_SSD_R2D_MUX_IN_P PCIE_SSD_R2D_MUX_IN_N PCIE_SSD_D2R_C_P PCIE_SSD_D2R_C_N PCIE_SSD_R2D_P PCIE_SSD_R2D_N PCIE_CLK100M_PCH_P PCIE_CLK100M_PCH_N PCIE_CLK100M_TBT_P PCIE_CLK100M_TBT_N PCH_CLK96M_DOT_P PCH_CLK96M_DOT_N PCH_CLK100M_SATA_P PCH_CLK100M_SATA_N PCH_CLK14P3M_REFCLK PCH_CLK33M_PCIIN PEX_TSTCLK_O_P PEX_TSTCLK_O_N PEG_CLK100M_P PEG_CLK100M_N PCIE_CLK100M_ENET_P PCIE_CLK100M_ENET_N PCIE_CLK100M_AP_P PCIE_CLK100M_AP_N PCIE_CLK100M_FW_P PCIE_CLK100M_FW_N PCIE_CLK100M_SSD_P PCIE_CLK100M_SSD_N PCIE_CLK100M_EXCARD_P PCIE_CLK100M_EXCARD_N PCIE_TBT_R2D_C_P PCIE_TBT_R2D_C_N PCIE_TBT_R2D_P PCIE_TBT_R2D_N PCIE_TBT_D2R_P PCIE_TBT_D2R_N PCIE_TBT_D2R_C_P PCIE_TBT_D2R_C_N 34 34 34 34 39 39 39 39 39 39 39 B 39 39 39 39 39 17 17 17 35 17 35 17 17 17 17 17 17 25 71 95 71 95 17 71 17 71 17 38 17 38 17 34 17 34 17 17 17 39 17 39 17 SYNC_MASTER=D2_KEPLER SYNC_DATE=01/13/2012 PAGE TITLE PCH Constraints 17 DRAWING NUMBER 35 35 Apple Inc 35 051-9589 R 35 35 35 NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED D 4.18.0 35 35 SIZE REVISION BRANCH PAGE 103 OF 132 SHEET 92 OF 99 A DisplayPort Signal Constraints NET_TYPE ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING Thunderbolt SPI Signal Constraints TBT_A_R2D TBTDP_85D TBTDP TBT_A_R2D TBTDP_85D TBTDP TBTDP_85D TBTDP TBTDP_85D TBTDP DP_TBTPA_ML DP_85D DISPLAYPORT DP_TBTPA_ML DP_85D DISPLAYPORT DP_85D DISPLAYPORT DP_85D DISPLAYPORT DP_85D DISPLAYPORT DP_85D DISPLAYPORT TBTDP_85D TBTDP TBTDP_85D TBTDP TBT_A_D2R TBTDP_85D TBTDP TBT_A_D2R TBTDP_85D TBTDP TBT_A_AUXCH DP_85D DISPLAYPORT TBT_A_AUXCH DP_85D DISPLAYPORT DP_85D DISPLAYPORT DP_85D DISPLAYPORT DP_85D DISPLAYPORT TABLE_PHYSICAL_RULE_HEAD LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM TBT_SPI_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT =2x_DIELECTRIC ? TABLE_SPACING_RULE_ITEM TBT_SPI D * Thunderbolt/DP Net Properties NOTE: DisplayPort Physical/Spacing Constraints provided by Chipset or GPU page PHYSICAL_RULE_SET Thunderbolt/DP Connector Signal Constraints TBT_A_R2D_C_P TBT_A_R2D_C_N TBT_A_R2D_P TBT_A_R2D_N DP_TBTPA_ML_C_P DP_TBTPA_ML_C_N DP_TBTPA_ML_P DP_TBTPA_ML_N DP_A_LSX_ML_P DP_A_LSX_ML_N 35 84 35 84 84 84 35 84 35 84 84 D 84 84 84 TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TBTDP_80D * =80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TBTDP_85D * =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF TBT_A_D2R_C_P TBT_A_D2R_C_N TBT_A_D2R_P TBT_A_D2R_N 84 84 35 84 35 84 TABLE_PHYSICAL_RULE_ITEM TBTDP_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM TBTDP * =5x_DIELECTRIC TABLE_SPACING_RULE_ITEM ? TBTDP TOP,BOTTOM =7x_DIELECTRIC ? DP_85D DISPLAYPORT TBTDP_85D TBTDP TBTDP_85D TBTDP TBT_B_R2D TBTDP_85D TBTDP TBT_B_R2D TBTDP_85D TBTDP TBTDP_85D TBTDP TBTDP_85D TBTDP DP_TBTPB_ML DP_85D DISPLAYPORT DP_TBTPB_ML DP_85D DISPLAYPORT DP_85D DISPLAYPORT DP_85D DISPLAYPORT DP_85D DISPLAYPORT DP_85D DISPLAYPORT TBTDP_85D TBTDP TBTDP_85D TBTDP TBT_B_D2R TBTDP_85D TBTDP TBT_B_D2R TBTDP_85D TBTDP TBT_B_AUXCH DP_85D DISPLAYPORT TBT_B_AUXCH DP_85D DISPLAYPORT DP_85D DISPLAYPORT DP_85D DISPLAYPORT DP_85D DISPLAYPORT NOTE: Thunderbolt high-speed nets are NOT directly assigned to TBTDP_*D physical rules TABLE_PHYSICAL_ASSIGNMENT symbols must be used to create the assignments Proper differential impedance depends on mDP connector used For 514-0637: R2D nets (SMT pins) = 80D, D2R nets (TH pins) = 100D SOURCE: Bill Cornelius’s Thunderbolt Routing Notes C TBT_B_D2R DP_85D DISPLAYPORT TBTDP_85D TBTDP TBTDP_85D TBTDP DP_TBTPA_AUXCH_C_P DP_TBTPA_AUXCH_C_N DP_TBTPA_AUXCH_P DP_TBTPA_AUXCH_N DP_A_AUXCH_DDC_P DP_A_AUXCH_DDC_N TBT_A_D2R1_AUXDDC_P TBT_A_D2R1_AUXDDC_N TBT_B_R2D_C_P TBT_B_R2D_C_N TBT_B_R2D_P TBT_B_R2D_N DP_TBTPB_ML_C_P DP_TBTPB_ML_C_N DP_TBTPB_ML_P DP_TBTPB_ML_N DP_B_LSX_ML_P DP_B_LSX_ML_N TBT_B_D2R_C_P TBT_B_D2R_C_N TBT_B_D2R_P TBT_B_D2R_N DP_TBTPB_AUXCH_C_P DP_TBTPB_AUXCH_C_N DP_TBTPB_AUXCH_P DP_TBTPB_AUXCH_N DP_B_AUXCH_DDC_P DP_B_AUXCH_DDC_N TBT_B_D2R1_AUXDDC_P TBT_B_D2R1_AUXDDC_N 35 84 35 84 84 84 84 84 84 84 35 85 35 85 85 85 35 85 35 85 85 85 85 C 85 85 Only used on dual-port hosts 85 35 85 35 85 35 85 35 85 85 85 85 85 85 85 Thunderbolt IC Net Properties NET_TYPE ELECTRICAL_CONSTRAINT_SET B PHYSICAL SPACING DP_85D DISPLAYPORT DP_85D DISPLAYPORT DP_85D DISPLAYPORT DP_85D DISPLAYPORT TBT_SPI_CLK TBT_SPI_55S TBT_SPI TBT_SPI_MOSI TBT_SPI_55S TBT_SPI TBT_SPI_MISO TBT_SPI_55S TBT_SPI TBT_SPI_CS_L TBT_SPI_55S TBT_SPI DP_TBTSRC_ML_C_P DP_TBTSRC_ML_C_N DP_TBTSRC_AUXCH_C_P DP_TBTSRC_AUXCH_C_N TBT_SPI_CLK TBT_SPI_MOSI TBT_SPI_MISO TBT_SPI_CS_L A Only used on hosts supporting Thunderbolt video-in 35 35 B 35 35 SYNC_MASTER=D2_KEPLER SYNC_DATE=01/13/2012 PAGE TITLE Thunderbolt Constraints DRAWING NUMBER Apple Inc 051-9589 R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED SIZE D REVISION 4.18.0 BRANCH PAGE 105 OF 132 SHEET 93 OF 99 A SMC SMBus Net Properties TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 1TO1_DIFFPAIR * =STANDARD =STANDARD =STANDARD =STANDARD 0.1 MM 0.1 MM NET_TYPE ELECTRICAL_CONSTRAINT_SET SPACING PHYSICAL TABLE_PHYSICAL_RULE_ITEM D SMBUS_SMC_2_S3_SCL SMB_50S SMB SMBUS_SMC_2_S3_SDA SMB_50S SMB SMBUS_SMC_1_S0_SCL SMB_50S SMB SMBUS_SMC_1_S0_SDA SMB_50S SMB SMBUS_SMC_0_S0_SCL SMB_50S SMB SMBUS_SMC_0_S0_SDA SMB_50S SMB SMBUS_SMC_5_SCL SMB_50S SMB SMBUS_SMC_5_SDA SMB_50S SMB SMBUS_SMC_3_SCL SMB_50S SMB SMBUS_SMC_3_SDA SMB_50S SMB SMBUS_SMC_2_S3_SCL SMBUS_SMC_2_S3_SDA SMBUS_SMC_1_S0_SCL SMBUS_SMC_1_S0_SDA SMBUS_SMC_0_S0_SCL SMBUS_SMC_0_S0_SDA SMBUS_SMC_5_SCL SMBUS_SMC_5_SDA SMBUS_SMC_3_SCL SMBUS_SMC_3_SDA 41 44 41 44 41 44 41 44 41 44 41 44 D 41 44 41 44 SMBus Charger Net Properties NET_TYPE ELECTRICAL_CONSTRAINT_SET PHYSICAL CHGR_CSI 1TO1_DIFFPAIR 1TO1_DIFFPAIR CHGR_CSO 1TO1_DIFFPAIR 1TO1_DIFFPAIR SPACING CHGR_CSI_P CHGR_CSI_N 61 61 CHGR_CSO_P CHGR_CSO_N 61 61 C C B B A SYNC_MASTER=D2_KEPLER SYNC_DATE=01/13/2012 PAGE TITLE SMC Constraints DRAWING NUMBER Apple Inc 051-9589 R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED SIZE D REVISION 4.18.0 BRANCH PAGE 106 OF 132 SHEET 94 OF 99 A GDDR5 Frame Buffer Signal Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH GDDR5 FB A Net Properties MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP NET_TYPE DIFFPAIR NECK GAP ELECTRICAL_CONSTRAINT_SET GDDR5 FB B Net Properties PHYSICAL NET_TYPE ELECTRICAL_CONSTRAINT_SET SPACING PHYSICAL SPACING TABLE_PHYSICAL_RULE_ITEM GDDR5_45R50SE * =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD 12.7 MM =STANDARD I453 TABLE_PHYSICAL_RULE_ITEM GDDR5_45SE * =45_OHM_SE =45_OHM_SE =45_OHM_SE =STANDARD =45_OHM_SE =STANDARD I454 TABLE_PHYSICAL_RULE_ITEM GDDR5_80D * =80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF I452 =80_OHM_DIFF I451 TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM GDDR5_CLK * =5x_DIELECTRIC D * =3x_DIELECTRIC ? GDDR5_CLK TOP,BOTTOM * =3x_DIELECTRIC * =5x_DIELECTRIC I447 TABLE_SPACING_RULE_ITEM ? GDDR5_CMD TOP,BOTTOM ? =4x_DIELECTRIC I446 TABLE_SPACING_RULE_ITEM ? GDDR5_DATA TOP,BOTTOM I445 ? =5x_DIELECTRIC TABLE_SPACING_RULE_ITEM GDDR5_EDC I449 ? =5x_DIELECTRIC TABLE_SPACING_RULE_ITEM GDDR5_DATA I448 TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM GDDR5_CMD I450 TABLE_SPACING_RULE_HEAD WEIGHT I444 TABLE_SPACING_RULE_ITEM ? GDDR5_EDC TOP,BOTTOM ? =5x_DIELECTRIC I442 I443 Digital Video Signal Constraints I440 TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP I441 DIFFPAIR NECK GAP I439 TABLE_PHYSICAL_RULE_ITEM DP_85D * =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF I437 TABLE_PHYSICAL_RULE_ITEM HDMI_90D * =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF I438 =90_OHM_DIFF I435 TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT DISPLAYPORT * =3x_DIELECTRIC ? TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT DISPLAYPORT TOP,BOTTOM =4x_DIELECTRIC ? TABLE_SPACING_RULE_ITEM * =3x_DIELECTRIC I402 TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM HDMI I436 I400 I401 TABLE_SPACING_RULE_ITEM ? HDMI TOP,BOTTOM =4x_DIELECTRIC ? I398 I399 DisplayPort/TMDS intra-pair matching should be 0.127mm DIsplayPort AUX CH intra-pair matching should be 0.127mm Inter-pair matching should be within 2.54cm I397 Max Length 241.3mm I395 Max length 330.2mm I396 MAX LENGTH OF DISPLAYPORT/TMDS TRACES: 13 INCHES I394 SOURCE: Calpella SFF DG Rev 1.5 (407364) and Family GPU DG-04202-001-v04 I392 I393 I390 I391 I389 I388 C I387 I385 I386 I384 I383 I382 I380 I381 I379 I378 I377 I376 I375 I374 I373 I372 I371 FB_A0_CLK FB_A0_CLK FB_A1_CLK FB_A1_CLK FB_A0_CMD FB_A1_CMD FB_A0_CMD FB_A1_CMD FB_A0_CMD FB_A1_CMD FB_A0_CMD FB_A1_CMD FB_A0_CMD FB_A1_CMD FB_A0_CMD_R FB_A1_CMD_R FB_A0_CMD FB_A1_CMD FB_A0_EDC0 FB_A0_EDC1 FB_A0_EDC2 FB_A0_EDC3 FB_A1_EDC0 FB_A1_EDC1 FB_A1_EDC2 FB_A1_EDC3 FB_A0_DBI_L0 FB_A0_DBI_L1 FB_A0_DBI_L2 FB_A0_DBI_L3 FB_A1_DBI_L0 FB_A1_DBI_L1 FB_A1_DBI_L2 FB_A1_DBI_L3 FB_A0_WCLK0 FB_A0_WCLK0 FB_A0_WCLK1 FB_A0_WCLK1 FB_A1_WCLK0 FB_A1_WCLK0 FB_A1_WCLK1 FB_A1_WCLK1 FB_A0_DQ_BYTE0 FB_A0_DQ_BYTE1 FB_A0_DQ_BYTE2 FB_A0_DQ_BYTE3 FB_A1_DQ_BYTE0 FB_A1_DQ_BYTE1 FB_A1_DQ_BYTE2 FB_A1_DQ_BYTE3 FB_A0_CMD_R FB_A1_CMD_R GDDR5_80D GDDR5_80D GDDR5_80D GDDR5_80D GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_80D GDDR5_80D GDDR5_80D GDDR5_80D GDDR5_80D GDDR5_80D GDDR5_80D GDDR5_80D GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_CLK GDDR5_CLK GDDR5_CLK GDDR5_CLK GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_EDC GDDR5_EDC GDDR5_EDC GDDR5_EDC GDDR5_EDC GDDR5_EDC GDDR5_EDC GDDR5_EDC GDDR5_DATA GDDR5_DATA GDDR5_DATA GDDR5_DATA GDDR5_DATA GDDR5_DATA GDDR5_DATA GDDR5_DATA GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_DATA GDDR5_DATA GDDR5_DATA GDDR5_DATA GDDR5_DATA GDDR5_DATA GDDR5_DATA GDDR5_DATA GDDR5_CMD GDDR5_CMD FB_A0_CLK_P FB_A0_CLK_N FB_A1_CLK_P FB_A1_CLK_N FB_A0_A FB_A1_A FB_A0_ABI_L FB_A1_ABI_L FB_A0_RAS_L FB_A1_RAS_L FB_A0_CAS_L FB_A1_CAS_L FB_A0_WE_L FB_A1_WE_L FB_A0_CKE_L FB_A1_CKE_L FB_A0_CS_L FB_A1_CS_L FB_A0_EDC FB_A0_EDC FB_A0_EDC FB_A0_EDC FB_A1_EDC FB_A1_EDC FB_A1_EDC FB_A1_EDC FB_A0_DBI_L FB_A0_DBI_L FB_A0_DBI_L FB_A0_DBI_L FB_A1_DBI_L FB_A1_DBI_L FB_A1_DBI_L FB_A1_DBI_L FB_A0_WCLK_P FB_A0_WCLK_N FB_A0_WCLK_P FB_A0_WCLK_N FB_A1_WCLK_P FB_A1_WCLK_N FB_A1_WCLK_P FB_A1_WCLK_N FB_A0_DQ FB_A0_DQ FB_A0_DQ FB_A0_DQ FB_A1_DQ FB_A1_DQ FB_A1_DQ FB_A1_DQ FB_A0_RESET_L FB_A1_RESET_L 73 75 I473 73 75 I474 73 75 I472 73 75 I470 73 75 I471 73 75 I468 73 75 I469 73 75 I467 73 75 I466 73 75 I465 73 75 I464 73 75 I463 73 75 I462 73 75 I460 73 75 I461 73 75 I459 73 75 I457 73 75 I458 73 75 I455 73 75 I456 73 75 I434 73 75 I433 73 75 I432 73 75 I430 73 75 I431 73 75 I429 73 75 I428 73 75 I427 73 75 I426 73 75 I424 73 75 I425 73 75 I423 73 75 I422 73 75 I421 73 75 I420 73 75 I419 73 75 I418 73 75 I417 73 75 I416 73 75 I414 73 75 I415 73 75 I412 73 75 I413 73 75 I411 73 75 I410 73 75 I409 73 75 I408 73 75 I407 73 75 I406 73 75 I404 73 75 I405 73 75 I403 FB_B0_CLK FB_B0_CLK FB_B1_CLK FB_B1_CLK FB_B0_CMD FB_B1_CMD FB_B0_CMD FB_B1_CMD FB_B0_CMD FB_B1_CMD FB_B0_CMD FB_B1_CMD FB_B0_CMD FB_B1_CMD FB_B0_CMD_R FB_B1_CMD_R FB_B0_CMD FB_B1_CMD FB_B0_EDC0 FB_B0_EDC1 FB_B0_EDC2 FB_B0_EDC3 FB_B1_EDC0 FB_B1_EDC1 FB_B1_EDC2 FB_B1_EDC3 FB_B0_DBI_L0 FB_B0_DBI_L1 FB_B0_DBI_L2 FB_B0_DBI_L3 FB_B1_DBI_L0 FB_B1_DBI_L1 FB_B1_DBI_L2 FB_B1_DBI_L3 FB_B0_WCLK0 FB_B0_WCLK0 FB_B0_WCLK1 FB_B0_WCLK1 FB_B1_WCLK0 FB_B1_WCLK0 FB_B1_WCLK1 FB_B1_WCLK1 FB_B0_DQ_BYTE0 FB_B0_DQ_BYTE1 FB_B0_DQ_BYTE2 FB_B0_DQ_BYTE3 FB_B1_DQ_BYTE0 FB_B1_DQ_BYTE1 FB_B1_DQ_BYTE2 FB_B1_DQ_BYTE3 FB_B0_CMD_R FB_B1_CMD_R GDDR5_80D GDDR5_80D GDDR5_80D GDDR5_80D GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_80D GDDR5_80D GDDR5_80D GDDR5_80D GDDR5_80D GDDR5_80D GDDR5_80D GDDR5_80D GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_CLK GDDR5_CLK GDDR5_CLK GDDR5_CLK GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_EDC GDDR5_EDC GDDR5_EDC GDDR5_EDC GDDR5_EDC GDDR5_EDC GDDR5_EDC GDDR5_EDC GDDR5_DATA GDDR5_DATA GDDR5_DATA GDDR5_DATA GDDR5_DATA GDDR5_DATA GDDR5_DATA GDDR5_DATA GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_DATA GDDR5_DATA GDDR5_DATA GDDR5_DATA GDDR5_DATA GDDR5_DATA GDDR5_DATA GDDR5_DATA GDDR5_CMD GDDR5_CMD FB_B0_CLK_P FB_B0_CLK_N FB_B1_CLK_P FB_B1_CLK_N FB_B0_A FB_B1_A FB_B0_ABI_L FB_B1_ABI_L FB_B0_RAS_L FB_B1_RAS_L FB_B0_CAS_L FB_B1_CAS_L FB_B0_WE_L FB_B1_WE_L FB_B0_CKE_L FB_B1_CKE_L FB_B0_CS_L FB_B1_CS_L FB_B0_EDC FB_B0_EDC FB_B0_EDC FB_B0_EDC FB_B1_EDC FB_B1_EDC FB_B1_EDC FB_B1_EDC FB_B0_DBI_L FB_B0_DBI_L FB_B0_DBI_L FB_B0_DBI_L FB_B1_DBI_L FB_B1_DBI_L FB_B1_DBI_L FB_B1_DBI_L FB_B0_WCLK_P FB_B0_WCLK_N FB_B0_WCLK_P FB_B0_WCLK_N FB_B1_WCLK_P FB_B1_WCLK_N FB_B1_WCLK_P FB_B1_WCLK_N FB_B0_DQ FB_B0_DQ FB_B0_DQ FB_B0_DQ FB_B1_DQ FB_B1_DQ FB_B1_DQ FB_B1_DQ FB_B0_RESET_L FB_B1_RESET_L 73 76 73 76 73 76 73 76 73 76 73 76 73 76 73 76 D 73 76 73 76 73 76 73 76 73 76 73 76 73 76 73 76 73 76 73 76 73 76 73 76 73 76 73 76 73 76 73 76 73 76 73 76 73 76 73 76 73 76 73 76 73 76 73 76 73 76 73 76 73 76 C 73 76 73 76 73 76 73 76 73 76 73 76 73 76 73 76 73 76 73 76 73 76 73 76 73 76 73 76 73 76 73 76 73 76 MUXGFX & DP AUX MUX NET PROPERTIES NET_TYPE ELECTRICAL_CONSTRAINT_SET DP_INT_ML DP_INT_AUXCH B I347 DP_INT_AUXCH I348 I349 DP_INT_AUXCH I350 I341 DP_INT_ML I342 I343 DP_INT_ML I344 I345 DP_INT_ML I346 I333 DP_INT_AUXCH I334 I336 DP_INT_AUXCH I335 I338 DP_INT_AUXCH I337 I339 DP_INT_AUXCH I340 I351 TBT_A_AUXCH I352 I353 TBT_B_AUXCH I354 I355 DP_INT_ML I356 A I363 DP_INT_ML I364 I357 TBT_A_AUXCH I358 I359 TBT_B_AUXCH I361 I360 DP_INT_ML I362 I365 DP_INT_ML I366 PHYSICAL SPACING DP_85D DISPLAYPORT DP_85D DISPLAYPORT DP_85D DISPLAYPORT DP_85D DISPLAYPORT DP_85D DISPLAYPORT DP_85D DISPLAYPORT DP_85D DISPLAYPORT DP_85D DISPLAYPORT DP_85D DISPLAYPORT DP_85D DISPLAYPORT DP_85D DISPLAYPORT DP_85D DISPLAYPORT DP_85D DISPLAYPORT DP_85D DISPLAYPORT DP_85D DISPLAYPORT DP_85D DISPLAYPORT DP_85D DISPLAYPORT DP_85D DISPLAYPORT DP_85D DISPLAYPORT DP_85D DISPLAYPORT DP_85D DISPLAYPORT DP_85D DISPLAYPORT DP_85D DISPLAYPORT DP_85D DISPLAYPORT DP_85D DISPLAYPORT DP_85D DISPLAYPORT DP_85D DISPLAYPORT DP_85D DISPLAYPORT DP_85D DISPLAYPORT DP_85D DISPLAYPORT DP_85D DISPLAYPORT DP_85D DISPLAYPORT DP_85D DISPLAYPORT DP_85D DISPLAYPORT DP_85D DISPLAYPORT DP_85D DISPLAYPORT DP_85D DISPLAYPORT DP_85D DISPLAYPORT DP_INT_ML_C_P DP_INT_ML_C_N DP_INT_AUX_C_P DP_INT_AUX_C_N DP_INT_AUX_P DP_INT_AUX_N DP_INT_EG_AUX_P DP_INT_EG_AUX_N DP_INT_ML_P DP_INT_ML_N DP_INT_ML_F_P DP_INT_ML_F_N DP_INT_EG_ML_P DP_INT_EG_ML_N DPA_IG_AUX_CH_P DPA_IG_AUX_CH_N DPB_IG_AUX_CH_P DPB_IG_AUX_CH_N DP_TBTSNK0_EG_AUXCH_P DP_TBTSNK0_EG_AUXCH_N DP_TBTSNK1_EG_AUXCH_P DP_TBTSNK1_EG_AUXCH_N DP_TBTSNK0_AUXCH_C_P DP_TBTSNK0_AUXCH_C_N DP_TBTSNK1_AUXCH_C_P DP_TBTSNK1_AUXCH_C_N DP_TBTSNK0_ML_C_P DP_TBTSNK0_ML_C_N DP_TBTSNK1_ML_C_P DP_TBTSNK1_ML_C_N DP_TBTSNK0_AUXCH_P DP_TBTSNK0_AUXCH_N DP_TBTSNK1_AUXCH_P DP_TBTSNK1_AUXCH_N DP_TBTSNK0_ML_P DP_TBTSNK0_ML_N DP_TBTSNK1_ML_P DP_TBTSNK1_ML_N 81 82 Kepler Net Properties 81 82 81 82 NET_TYPE ELECTRICAL_CONSTRAINT_SET PHYSICAL B SPACING 81 82 GPU_CLK27M CLK_SLOW_55S CLK_SLOW GPU_CLK27M CLK_SLOW_55S CLK_SLOW GPU_CLK27M CLK_SLOW_55S CLK_SLOW GPU_CLK27M CLK_SLOW_55S CLK_SLOW GPU_OSC_27M_XTALIN GPU_OSC_27M_XTALOUT GPU_OSC_27M_XTAL_BUFFOUT GPU_OSC_27M_SSIN 81 81 77 82 77 78 77 78 77 77 82 81 81 81 81 77 82 77 82 18 83 18 83 18 83 PEX_TSTCLK_O_P PEX_TSTCLK_O_N 1:1_DIFFPAIR 18 83 1:1_DIFFPAIR 71 92 71 92 77 83 77 83 HDMI_DATA HDMI_90D HDMI HDMI_90D HDMI HDMI_90D HDMI HDMI_90D HDMI HDMI_EG_DATA_C_P HDMI_EG_DATA_C_N HDMI_EG_CLK_C_P HDMI_EG_CLK_C_N 77 83 77 83 HDMI_CLK 35 83 38 77 38 77 38 77 38 77 35 83 35 83 35 83 35 77 35 77 35 77 SYNC_MASTER=D2_KEPLER 35 77 SYNC_DATE=01/13/2012 PAGE TITLE 35 GPU (Kepler) CONSTRAINTS 35 DRAWING NUMBER 35 35 Apple Inc 35 051-9589 R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED 35 D 4.18.0 35 35 SIZE REVISION BRANCH PAGE 107 OF 132 SHEET 95 OF 99 A TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET ALLOW ROUTE ON LAYER? LAYER MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP D2 Specific Net Properties D2 Specific Net Properties NET_TYPE NET_TYPE TABLE_PHYSICAL_RULE_ITEM SENSE_1TO1_55S * =55_OHM_SE =1:1_DIFFPAIR =55_OHM_SE =55_OHM_SE =1:1_DIFFPAIR =1:1_DIFFPAIR ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING TABLE_PHYSICAL_RULE_ITEM THERM_1TO1_55S * =55_OHM_SE =1:1_DIFFPAIR =55_OHM_SE =55_OHM_SE =1:1_DIFFPAIR =1:1_DIFFPAIR SENSE_DIFFPAIR CPUTHMSNS_D2_P 47 THERM CPUTHMSNS_D2_N THERM_1TO1_55S THERM DDR3THMSNS_D1_P THERM_1TO1_55S THERM DDR3THMSNS_D1_N THERM_1TO1_55S THERM THERM_1TO1_55S TABLE_PHYSICAL_RULE_ITEM DIFFPAIR * =1:1_DIFFPAIR AUDIODIFF * =1:1_DIFFPAIR 0.1 MM THERM_55S_CPUIMVPISNS1 * =1:1_DIFFPAIR =55_OHM_SE =1:1_DIFFPAIR =1:1_DIFFPAIR =1:1_DIFFPAIR 0.1 MM 10 MM 0.1 MM 0.1 MM =55_OHM_SE =55_OHM_SE 0.2 MM 0.2 MM SENSE_DIFFPAIR PCIE_CLK100M_AP CLK_PCIE_90D CLK_PCIE 47 CLK_PCIE_90D CLK_PCIE 47 1TO1_DIFFPAIR 47 1TO1_DIFFPAIR TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM SENSE_DIFFPAIR SENSE_DIFFPAIR D PCIE_CLK100M_AP_CONN_P PCIE_CLK100M_AP_CONN_N CHGR_CSI_R_P CHGR_CSI_R_N CHGR_CSO_R_P CHGR_CSO_R_N 34 34 61 61 THERM_1TO1_55S THERM GPUTHMSNS_D_P 47 THERM_1TO1_55S THERM GPUTHMSNS_D_N 47 THERM_1TO1_55S THERM GPU_TDIODE_P 47 77 (USB_EXTA) USB_85D USB USB2_EXTA_MUXED_P THERM_1TO1_55S THERM GPU_TDIODE_N 47 77 (USB_EXTA) USB_85D USB USB2_EXTA_MUXED_N SENSE_1TO1_55S SENSE VCCSAS0_CS_P 45 62 (USB_EXTA) USB_85D USB SENSE_1TO1_55S SENSE VCCSAS0_CS_N 45 62 (USB_EXTA) USB_85D USB USB2_LT1_P USB2_LT1_N SENSE_1TO1_55S SENSE VCCSAISNS_R_P 45 USB_85D USB CONN_USB2_BT_P SENSE_1TO1_55S SENSE VCCSAISNS_R_N 45 USB_85D USB SENSE_1TO1_55S SENSE ISNS_1V5_MEM_R_P 45 USB_85D USB SENSE_1TO1_55S SENSE ISNS_1V5_MEM_R_N 45 USB_85D USB SENSE_1TO1_55S SENSE CPUVCCIOS0_CS_P 45 67 AUDIODIFF AUDIO SPKRAMP_LIN_P SENSE_1TO1_55S SENSE CPUVCCIOS0_CS_N 45 67 AUDIODIFF AUDIO SPKRAMP_LIN_N 57 SENSE_1TO1_55S SENSE CPUVCCIOISNS_R_P 45 AUDIODIFF AUDIO SPKRAMP_RIN_P 57 SENSE_1TO1_55S SENSE CPUVCCIOISNS_R_N 45 AUDIODIFF AUDIO SPKRAMP_RIN_N 57 SENSE_1TO1_55S SENSE GPUISENS_N AUDIODIFF AUDIO SSM2375SL_P SENSE_1TO1_55S SENSE GPUISENS_P AUDIODIFF AUDIO SSM2375SL_N SENSE_1TO1_55S SENSE ISNS_1V5_MEM_N 45 AUDIODIFF AUDIO SSM2375SR_P SENSE_1TO1_55S SENSE ISNS_1V5_MEM_P 45 AUDIODIFF AUDIO SENSE_1TO1_55S SENSE ISNS_AIRPORT_N 96 1TO1_DIFFPAIR 1TO1_DIFFPAIR 61 61 D TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET TABLE_SPACING_RULE_ITEM CPU_COMP GND * GND_P2MM TABLE_SPACING_RULE_ITEM CPU_VCCSENSE GND * GND_P2MM TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING SENSE_DIFFPAIR WEIGHT TABLE_SPACING_ASSIGNMENT_ITEM SENSE * =2:1_SPACING ? THERM * =2:1_SPACING ? AUDIO * =2:1_SPACING ? SENSE_DIFFPAIR TABLE_SPACING_ASSIGNMENT_ITEM SENSE_DIFFPAIR CONN_USB2_BT_N USB_LT2_P USB_LT2_N TABLE_SPACING_RULE_ITEM SENSE_DIFFPAIR SENSE_DIFFPAIR AUDIO_DIFFPAIR AUDIO_DIFFPAIR 57 TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT =STANDARD ? SENSE_DIFFPAIR TABLE_SPACING_RULE_ITEM GND * TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE I367 SENSE_DIFFPAIR AUDIO_DIFFPAIR I368 SPACING_RULE_SET AUDIO_DIFFPAIR TABLE_SPACING_ASSIGNMENT_ITEM CLK_PCIE GND * GND_P2MM PCIE GND * GND_P2MM SATA GND * GND_P2MM TABLE_SPACING_ASSIGNMENT_ITEM SENSE_DIFFPAIR SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT 0.20 MM 1000 I381 SENSE_1TO1_55S SENSE ISNS_AIRPORT_N 96 SENSE_1TO1_55S SENSE ISNS_AIRPORT_P 96 SENSE_1TO1_55S SENSE ISNS_AIRPORT_P 96 TABLE_SPACING_RULE_HEAD TABLE_SPACING_ASSIGNMENT_ITEM SENSE_DIFFPAIR I382 TABLE_SPACING_RULE_ITEM * GND_P2MM TABLE_SPACING_ASSIGNMENT_ITEM USB GND * 0.20 MM I358 GND_P2MM * TABLE_SPACING_RULE_ITEM PWR_P2MM SENSE_DIFFPAIR 1000 SB_POWER * PWR_P2MM SENSE_1TO1_55S SENSE ISNS_AIRPORT_R_N 99 SENSE_1TO1_55S SENSE ISNS_AIRPORT_R_P 99 I387 AREA_TYPE SATA SB_POWER * PWR_P2MM SENSE_DIFFPAIR TABLE_SPACING_ASSIGNMENT_ITEM GND MEM_CLK * USB SB_POWER * MEM_CMD SENSE ISNS_LCDBKLT_N SENSE_1TO1_55S SENSE ISNS_LCDBKLT_P I390 GND_P2MM * I391 SENSE_1TO1_55S SENSE GPUFB_CS_P 74 99 GND MEM_CTRL * GND_P2MM SENSE_DIFFPAIR TABLE_SPACING_ASSIGNMENT_ITEM GND * MEM_*_DQ_BYTE* AUDIO DIFFPAIR AUDIO DIFFPAIR AUDIO DIFFPAIR AUDIO DIFFPAIR AUDIO DIFFPAIR AUDIO DIFFPAIR AUDIO DIFFPAIR I392 SENSE_1TO1_55S SENSE GPUFB_CS_N 74 99 I360 SENSE_1TO1_55S SENSE ISNS_PP1V0_S0GPU_R_P 98 I359 SENSE_1TO1_55S SENSE ISNS_PP1V0_S0GPU_R_N 98 SENSE_1TO1_55S SENSE ISNS_PP1V8_S0GPU_P SENSE_1TO1_55S SENSE ISNS_PP1V8_S0GPU_N SENSE_1TO1_55S SENSE ISNS_PP1V8_S0GPU_R_P SENSE_1TO1_55S SENSE ISNS_PP1V8_S0GPU_R_N SENSE_1TO1_55S SENSE P1V05_GPU_CS_P 74 98 SENSE_1TO1_55S AUDIO_DIFFPAIR AUDIO DIFFPAIR AUDIO DIFFPAIR AUDIO DIFFPAIR AUDIO DIFFPAIR AUDIO DIFFPAIR AUDIO DIFFPAIR AUDIO DIFFPAIR AUDIO DIFFPAIR AUDIO DIFFPAIR AUDIO DIFFPAIR AUDIO DIFFPAIR AUDIO DIFFPAIR AUDIO DIFFPAIR AUDIO DIFFPAIR AUDIO DIFFPAIR AUDIO DIFFPAIR AUDIO DIFFPAIR AUDIO DIFFPAIR AUDIO DIFFPAIR AUDIO DIFFPAIR AUDIO DIFFPAIR AUDIO DIFFPAIR AUDIO GND_P2MM TABLE_SPACING_ASSIGNMENT_ITEM C AUDIO_DIFFPAIR I389 SSM2375SR_N DIFFPAIR PWR_P2MM TABLE_SPACING_ASSIGNMENT_ITEM GND SENSE_1TO1_55S SPACING_RULE_SET TABLE_SPACING_ASSIGNMENT_ITEM AUDIO_DIFFPAIR I388 TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE2 AUDIO_DIFFPAIR I357 TABLE_SPACING_ASSIGNMENT_ITEM CLK_PCIE NET_SPACING_TYPE1 AUDIO_DIFFPAIR AUDIO_DIFFPAIR AUDIO_DIFFPAIR TABLE_SPACING_ASSIGNMENT_HEAD GND_P2MM NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET SENSE_DIFFPAIR TABLE_SPACING_ASSIGNMENT_ITEM GND MEM_DQS * TABLE_SPACING_ASSIGNMENT_ITEM GND_P2MM LVDS GND * SENSE_DIFFPAIR TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER MEM_40S * OVERRIDE OVERRIDE ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH 0.09 MM 100 MIL OVERRIDE OVERRIDE AUDIO_DIFFPAIR GND_P2MM DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP OVERRIDE OVERRIDE AUDIO_DIFFPAIR SENSE P1V05_GPU_CS_N 74 98 I393 SENSE_1TO1_55S SENSE ISNS_PP1V5_S0GPU_R_P 99 I394 SENSE_1TO1_55S SENSE ISNS_PP1V5_S0GPU_R_N 99 I396 SENSE_1TO1_55S SENSE CPUIMVP_ISNS1G_P 46 66 I395 46 66 TABLE_PHYSICAL_RULE_ITEM OVERRIDE OVERRIDE SENSE_DIFFPAIR TABLE_PHYSICAL_RULE_ITEM MEM_72D * OVERRIDE OVERRIDE MEM_37S * OVERRIDE OVERRIDE OVERRIDE OVERRIDE 0.09 MM 100 MIL OVERRIDE OVERRIDE 0.09 MM 100 MIL OVERRIDE OVERRIDE SENSE_DIFFPAIR_42 OVERRIDE OVERRIDE SENSE_DIFFPAIR_42 SENSE_1TO1_55S SENSE CPUIMVP_ISNS1G_N SENSE_DIFFPAIR SENSE_1TO1_55S SENSE CPUIMVP_ISNS1G_R_P 46 SENSE_1TO1_55S SENSE CPUIMVP_ISNS1G_R_N 46 SENSE_1TO1_55S SENSE ISNS_HS_OTHER_P 46 I411 SENSE_1TO1_55S SENSE ISNS_HS_OTHER_N 46 I412 SENSE_1TO1_55S SENSE ISNS_HS_GPU_P 46 AUDIO_DIFFPAIR AUDIO_DIFFPAIR TABLE_PHYSICAL_RULE_ITEM OVERRIDE OVERRIDE OVERRIDE OVERRIDE I409 AUDIO_DIFFPAIR I410 SPKRCONN_SL_OUT_P_R SPKRCONN_SL_OUT_N_R SPKRCONN_SL_OUT_P SPKRCONN_SL_OUT_N LSPKR_VSENSE_FILT_P LSPKR_VSENSE_FILT_N RSPKR_VSENSE_FILT_P RSPKR_VSENSE_FILT_N SPKRCONN_SR_OUT_P_R SPKRCONN_SR_OUT_N_R SPKRCONN_SR_OUT_P SPKRCONN_SR_OUT_N SPKRCONN_L_OUT_P SPKRCONN_L_OUT_N SPKRCONN_R_OUT_P SPKRCONN_R_OUT_N SPKRCONN_S_OUT_P SPKRCONN_S_OUT_N LSPKR_ISENSE_FILT_P LSPKR_ISENSE_FILT_N RSPKR_ISENSE_FILT_P RSPKR_ISENSE_FILT_N 57 59 57 59 57 59 C 57 59 57 59 57 59 57 59 57 59 RSUBIN_P RSUBIN_N 57 57 TABLE_PHYSICAL_RULE_ITEM MEM_85D * OVERRIDE OVERRIDE PCIE_85D * OVERRIDE OVERRIDE OVERRIDE OVERRIDE 0.09 MM 100 MIL OVERRIDE OVERRIDE 0.09 MM 10 mm OVERRIDE SENSE_DIFFPAIR OVERRIDE OVERRIDE TABLE_PHYSICAL_RULE_ITEM OVERRIDE OVERRIDE OVERRIDE 0.1 MM 500 MIL OVERRIDE OVERRIDE OVERRIDE OVERRIDE SENSE_DIFFPAIR OVERRIDE OVERRIDE OVERRIDE OVERRIDE I414 SENSE_1TO1_55S SENSE ISNS_HS_GPU_N 46 SENSE_1TO1_55S SENSE ISNS_HS_COMPUTING_P 46 SENSE_1TO1_55S SENSE ISNS_HS_COMPUTING_N 46 AUDIO_DIFFPAIR AUDIO_DIFFPAIR TABLE_PHYSICAL_RULE_ITEM USB_85D TOP OVERRIDE OVERRIDE SENSE_DIFFPAIR I413 I415 AUDIO_DIFFPAIR TABLE_PHYSICAL_RULE_ITEM CPU_27P4S BOTTOM OVERRIDE OVERRIDE OVERRIDE OVERRIDE 0.23 MM 100 MIL OVERRIDE OVERRIDE SENSE_DIFFPAIR OVERRIDE OVERRIDE I343 AUDIO_DIFFPAIR I344 I345 AUDIO_DIFFPAIR I346 B I348 AUDIO_DIFFPAIR I347 I350 AUDIO_DIFFPAIR I349 I351 AUDIO_DIFFPAIR I352 I353 AUDIO_DIFFPAIR I354 I355 AUDIO_DIFFPAIR I356 AUDIO_DIFFPAIR AUDIO_DIFFPAIR Graphics ,SATA Constraint Relaxations AUDIO_DIFFPAIR SENSE_1TO1_55S SENSE CPUIMVP_ISNS_P 46 SENSE_1TO1_55S SENSE CPUIMVP_ISNS_N 46 AUDIODIFF AUDIO ADC1_VSENSE_P AUDIODIFF AUDIO ADC1_VSENSE_N AUDIODIFF AUDIO ADC2_VSENSE_P AUDIODIFF AUDIO ADC2_VSENSE_N AUDIODIFF AUDIO ADC2_ISENSE_P 96 AUDIODIFF AUDIO ADC2_ISENSE_N AUDIODIFF AUDIO ADC2_ISENSE_P AUDIODIFF AUDIO ADC2_ISENSE_N AUDIODIFF AUDIO SPKR_R_RSENSE_P AUDIODIFF AUDIO SPKR_R_RSENSE_N AUDIODIFF AUDIO SPKR_L_RSENSE_P AUDIODIFF AUDIO SPKR_L_RSENSE_N AUDIODIFF AUDIO AUD_LO1_L_P 53 57 AUDIODIFF AUDIO AUD_LO1_L_N 53 57 AUDIODIFF AUDIO AUD_LO1_R_P 53 57 AUDIODIFF AUDIO AUD_LO1_R_N 53 57 AUDIODIFF AUDIO AUD_LO2_L_P 53 57 AUDIODIFF AUDIO AUD_LO2_L_N 53 57 AUDIODIFF AUDIO AUD_LO2_R_P 53 57 AUDIODIFF AUDIO AUD_LO2_R_N 53 57 AUDIODIFF AUDIO AUD_MIC_INL_P 53 58 53 58 Alternate diffpair width/gap through BGA fanout areas (95-ohm diff) I417 TABLE_PHYSICAL_ASSIGNMENT_HEAD NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET I418 AUDIO_DIFFPAIR I416 LSUBIN_P LSUBIN_N AUDIO_DIFFPAIR AUDIODIFF AUDIO LSPKR_VSENSE_IN_P I364 AUDIO_DIFFPAIR AUDIODIFF AUDIO LSPKR_VSENSE_IN_N I365 AUDIO_DIFFPAIR AUDIODIFF AUDIO I366 AUDIO_DIFFPAIR AUDIODIFF AUDIO RSPKR_VSENSE_IN_N I371 AUDIO_DIFFPAIR AUDIODIFF AUDIO LSPKR_ISENSE_RDIVIDE_P 96 I372 AUDIO_DIFFPAIR AUDIODIFF AUDIO LSPKR_ISENSE_RDIVIDE_N 96 I376 AUDIO_DIFFPAIR AUDIODIFF AUDIO RSPKR_ISENSE_RDIVIDE_P AUDIODIFF AUDIO RSPKR_ISENSE_RDIVIDE_N AUDIODIFF AUDIO LSPKR_VSENSE_RDIVIDE_P AUDIODIFF AUDIO LSPKR_VSENSE_RDIVIDE_N AUDIODIFF AUDIO RSPKR_VSENSE_RDIVIDE_P AUDIODIFF AUDIO RSPKR_VSENSE_RDIVIDE_N USB_85D USB USB_85D USB I375 I378 AUDIO_DIFFPAIR I379 I386 I385 AUDIO_DIFFPAIR AUDIODIFF AUDIO AUD_MIC_INL_N AUDIO_DIFFPAIR AUDIODIFF AUDIO AUD_SPKRAMP_LIN_P 57 AUDIODIFF AUDIO AUD_SPKRAMP_LIN_N 57 AUDIODIFF AUDIO AUD_SPKRAMP_RIN_P 57 AUDIO_DIFFPAIR 57 SSM4321SR_P SSM4321SR_N SSM4321SL_P SSM4321SL_N I363 96 57 RSPKR_VSENSE_IN_P B USB_TPAD_R_P USB_TPAD_R_N 26 49 SB_POWER PP3V3_S5 SB_POWER PP3V3_S0 SB_POWER PP1V5_S3RS0_CPUDDR 26 49 TABLE_PHYSICAL_ASSIGNMENT_ITEM LVDS_85D BGA LVDS_85D DP_85D BGA 100_DIFF_BGA TABLE_PHYSICAL_ASSIGNMENT_ITEM AUDIO_DIFFPAIR TABLE_PHYSICAL_ASSIGNMENT_ITEM SATA_90D BGA 100_DIFF_BGA AUDIODIFF AUDIO AUD_SPKRAMP_RIN_N 57 GND TABLE_PHYSICAL_ASSIGNMENT_ITEM CLK_PCIE_90D BGA AUDIO_DIFFPAIR AUDIO AUD_SPKRAMP_LSUBIN_P 57 AUDIODIFF AUDIO AUD_SPKRAMP_LSUBIN_N 57 AUDIODIFF AUDIO AUD_SPKRAMP_RSUBIN_P 57 AUDIODIFF AUDIO AUD_SPKRAMP_RSUBIN_N 57 AUDIODIFF AUDIO LSPKR_INTIV_RSENSE_P AUDIODIFF AUDIO LSPKR_INTIV_RSENSE_N AUDIODIFF AUDIO RSPKR_INTIV_RSENSE_P AUDIODIFF AUDIO RSPKR_INTIV_RSENSE_N AUDIODIFF AUDIO LSPKR_INTIV_P AUDIODIFF AUDIO LSPKR_INTIV_N 100_DIFF_BGA I361 A AUDIODIFF AUDIO_DIFFPAIR I362 Memory Constraint Relaxations I397 AUDIO_DIFFPAIR I398 Allow 0.127 mm necks for >0.127 mm lines for ARD fanout I399 AUDIO_DIFFPAIR TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM MEM_72D BOTTOM 0.127 MM 6.35 MM I400 I401 I403 TOP 0.1 MM AUDIO_DIFFPAIR I402 TABLE_PHYSICAL_RULE_ITEM MEM_85D AUDIO_DIFFPAIR I405 AUDIO_DIFFPAIR I406 I407 AUDIO_DIFFPAIR I408 SYNC_MASTER=D2_CLEAN Project Specific Constraints DRAWING NUMBER Apple Inc AUDIO RSPKR_INTIV_P AUDIODIFF AUDIO RSPKR_INTIV_N AUDIODIFF AUDIO ISNS_TBT_N 99 AUDIODIFF AUDIO ISNS_TBT_P 99 AUDIODIFF AUDIO ISNS_TBT_R_N 99 AUDIODIFF AUDIO ISNS_TBT_R_P 99 SYNC_DATE=03/15/2012 PAGE TITLE AUDIODIFF 6.35 MM I404 GND 051-9589 R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED SIZE D REVISION 4.18.0 BRANCH PAGE 108 OF 132 SHEET 96 OF 99 A 15" MBP BOARD-SPECIFIC SPACING & PHYSICAL CONSTRAINTS TABLE_BOARD_INFO BOARD LAYERS BOARD AREAS BOARD UNITS (MIL or MM) ALLEGRO VERSION TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM NO_TYPE,BGA MM 16.2 Stackup-Defined Spacing Rules TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM DEFAULT * Y =50_OHM_SE =50_OHM_SE 10 MM MM MM STANDARD * Y =DEFAULT =DEFAULT 10 MM =DEFAULT =DEFAULT PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 55_OHM_SE TOP,BOTTOM Y 0.090 MM 0.090 MM Note: Outer dielectric is 0.058 mm nominal, Inner dielectric is 0.053 mm nominal TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM * * BGA P072_SPACE TABLE_PHYSICAL_RULE_HEAD D LAYER LINE-TO-LINE SPACING WEIGHT DEFAULT * 0.1 MM ? TABLE_SPACING_RULE_HEAD SPACING_RULE_SET TABLE_SPACING_RULE_ITEM LAYER LINE-TO-LINE SPACING WEIGHT TABLE_PHYSICAL_RULE_ITEM 55_OHM_SE * Y 0.076 MM 0.076 MM =STANDARD =STANDARD =STANDARD D TABLE_SPACING_RULE_HEAD SPACING_RULE_SET TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM STANDARD * ? =DEFAULT 1:1_SPACING TOP,BOTTOM 0.058 MM ? 2:1_SPACING TOP,BOTTOM 0.116 MM ? 3:1_SPACING TOP,BOTTOM 0.174 MM ? 4:1_SPACING TOP,BOTTOM 0.232 MM ? 5:1_SPACING TOP,BOTTOM 0.290 MM ? 1:1_SPACING ISL3,ISL4,ISL9,ISL10 0.053 MM ? 2:1_SPACING ISL3,ISL4,ISL9,ISL10 0.106 MM ? 3:1_SPACING ISL3,ISL4,ISL9,ISL10 0.159 MM ? 4:1_SPACING ISL3,ISL4,ISL9,ISL10 0.212 MM ? 5:1_SPACING ISL3,ISL4,ISL9,ISL10 0.265 MM ? 1:1_SPACING ISL2,ISL5,ISL6,ISL7,ISL8,ISL11 0.101 MM ? 2:1_SPACING ISL2,ISL5,ISL6,ISL7,ISL8,ISL11 0.202 MM ? 3:1_SPACING ISL2,ISL5,ISL6,ISL7,ISL8,ISL11 0.303 MM ? 4:1_SPACING ISL2,ISL5,ISL6,ISL7,ISL8,ISL11 0.404 MM ? 5:1_SPACING ISL2,ISL5,ISL6,ISL7,ISL8,ISL11 0.505 MM ? TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP BGA_P1MM * ? 0.1 MM DIFFPAIR NECK GAP TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM 50_OHM_SE TOP,BOTTOM Y 0.090 MM 0.090 MM 50_OHM_SE * Y 0.070 MM 0.070 MM BGA_P2MM * 0.2 MM ? P072_SPACE * 0.071 MM ? TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM =STANDARD =STANDARD =STANDARD TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM 45_OHM_SE TOP,BOTTOM Y 0.116 MM 0.116 MM 15" MBP Specific Net Properties TABLE_SPACING_RULE_ITEM NET_TYPE TABLE_PHYSICAL_RULE_ITEM 45_OHM_SE * Y 0.085 MM LAYER ALLOW ROUTE ON LAYER? 0.085 MM =STANDARD =STANDARD =STANDARD ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP TABLE_PHYSICAL_RULE_ITEM 40_OHM_SE TOP,BOTTOM Y 0.145 MM TABLE_SPACING_RULE_ITEM DIFFPAIR NECK GAP 0.095 MM I1 40_OHM_SE * Y 0.105 MM 0.090 MM AUDIODIFF AUDIO AUDIODIFF AUDIO ADC1_ISENSE_N SENSE_DIFFPAIR_42 THERM_55S_CPUIMVPISNS1 THERM CPUIMVP_ISNS1_P 46 65 66 THERM_55S_CPUIMVPISNS1 THERM CPUIMVP_ISNS1_N 46 66 THERM_1TO1_55S THERM CPUIMVP_ISNS2G_P 46 66 THERM_1TO1_55S THERM CPUIMVP_ISNS2G_N 46 66 THERM_1TO1_55S THERM CPUIMVP_ISNS2_P 46 65 66 THERM_1TO1_55S THERM CPUIMVP_ISNS2_N 46 66 THERM_55S_CPUIMVPISNS1 THERM CPUIMVP_ISNS3_P 46 65 66 THERM_55S_CPUIMVPISNS1 TABLE_SPACING_RULE_ITEM I2 TABLE_PHYSICAL_RULE_ITEM =STANDARD =STANDARD I3 =STANDARD I4 TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH 37_OHM_SE TOP,BOTTOM Y 0.165 MM 0.095 MM MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP I5 I7 TABLE_PHYSICAL_RULE_ITEM C 37_OHM_SE * Y 0.120 MM 0.090 MM =STANDARD =STANDARD =STANDARD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP SENSE_DIFFPAIR SENSE_DIFFPAIR I10 THERM CPUIMVP_ISNS3_N 46 66 THERM_1TO1_55S THERM CPUIMVP_ISUM_R_P 46 THERM_1TO1_55S THERM CPUIMVP_ISUM_R_N 46 THERM_1TO1_55S THERM CPUIMVP_ISUMG_R_P 46 THERM_1TO1_55S THERM CPUIMVP_ISUMG_R_N 46 THERM_1TO1_55S THERM GFXIMVP_ISNS1_P 80 THERM_1TO1_55S THERM GFXIMVP_ISNS1_N 80 THERM_1TO1_55S THERM GFXIMVP_ISNS2_P 80 THERM_1TO1_55S THERM GFXIMVP_ISNS2_N 80 THERM_1TO1_55S THERM ISNS_CPU_DDR_R_P 98 THERM_1TO1_55S THERM ISNS_CPU_DDR_R_N 98 TABLE_PHYSICAL_RULE_HEAD TABLE_PHYSICAL_RULE_ITEM 27P4_OHM_SE TOP,BOTTOM Y 0.265 MM 0.095 MM 27P4_OHM_SE * Y 0.190 MM 0.1 MM I11 SENSE_DIFFPAIR I12 I13 SENSE_DIFFPAIR TABLE_PHYSICAL_RULE_ITEM =STANDARD =STANDARD I14 =STANDARD I15 TABLE_PHYSICAL_RULE_HEAD LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 72_OHM_DIFF * N =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD 72_OHM_DIFF ISL3,ISL4,ISL9,ISL10 Y 0.124 MM 0.124 MM 0.200 MM 0.200 MM 72_OHM_DIFF ISL2,ISL11 Y 0.124 MM 0.124 MM 0.200 MM 0.200 MM 72_OHM_DIFF TOP,BOTTOM Y 0.140 MM 0.140 MM 0.120 MM 0.120 MM TABLE_PHYSICAL_RULE_ITEM I17 SENSE_DIFFPAIR SENSE_DIFFPAIR TABLE_PHYSICAL_RULE_ITEM I20 TABLE_PHYSICAL_RULE_ITEM I21 I23 SENSE_DIFFPAIR PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 80_OHM_DIFF * N =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD I26 I28 TABLE_PHYSICAL_RULE_ITEM 80_OHM_DIFF ISL3,ISL4,ISL9,ISL10 Y 0.096 MM 0.096 MM 0.126 MM 0.126 MM 80_OHM_DIFF ISL2,ISL11 Y 0.096 MM 0.096 MM 0.126 MM 0.126 MM SENSE_DIFFPAIR THERM ISNS_LCD_PANEL_P THERM ISNS_LCD_PANEL_N THERM_1TO1_55S THERM ISNS_P1V5R1V35_CPUDDR_P THERM_1TO1_55S THERM ISNS_P1V5R1V35_CPUDDR_N THERM_1TO1_55S THERM ISNS_SSD_P 39 99 THERM_1TO1_55S THERM ISNS_SSD_R_P 99 THERM_1TO1_55S THERM ISNS_SSD_R_N 99 80_OHM_DIFF 0.120 MM 0.160 MM 0.120 MM 0.160 MM TOP,BOTTOM Y PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? SENSE_DIFFPAIR THERM_1TO1_55S THERM PCHVCCIOS0_CS_P 87 99 THERM_1TO1_55S THERM PCHVCCIOS0_CS_N 87 99 SENSE_DIFFPAIR THERM_1TO1_55S THERM PCH_VCCIOSENSE_P 87 MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 85_OHM_DIFF * N =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD TOP,BOTTOM 0.116 MM ? 3x_DIELECTRIC TOP,BOTTOM 0.174 MM ? 4x_DIELECTRIC TOP,BOTTOM 0.232 MM ? 5x_DIELECTRIC TOP,BOTTOM 0.290 MM ? 1x_DIELECTRIC ISL3,ISL4,ISL9,ISL10 0.053 MM ? 2x_DIELECTRIC ISL3,ISL4,ISL9,ISL10 0.106 MM ? 3x_DIELECTRIC ISL3,ISL4,ISL9,ISL10 0.159 MM ? 4x_DIELECTRIC ISL3,ISL4,ISL9,ISL10 0.212 MM ? 5x_DIELECTRIC ISL3,ISL4,ISL9,ISL10 0.265 MM ? 1X_DIELECTRIC ISL2,ISL5,ISL6,ISL7,ISL8,ISL11 0.101 MM ? 2x_DIELECTRIC ISL2,ISL5,ISL6,ISL7,ISL8,ISL11 0.202 MM ? 3x_DIELECTRIC ISL2,ISL5,ISL6,ISL7,ISL8,ISL11 0.303 MM ? 4x_DIELECTRIC ISL2,ISL5,ISL6,ISL7,ISL8,ISL11 0.404 MM ? 5x_DIELECTRIC ISL2,ISL5,ISL6,ISL7,ISL8,ISL11 0.505 MM ? TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM THERM_1TO1_55S THERM PCH_VCCIOSENSE_N 87 TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM I31 TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM I67 SENSE_DIFFPAIR 40_OHM_SE THERM GPUVCORE_SENSE_P 79 80 I68 SENSE_DIFFPAIR 40_OHM_SE THERM GPUVCORE_SENSE_N 79 80 TABLE_PHYSICAL_RULE_HEAD 2x_DIELECTRIC TABLE_SPACING_RULE_ITEM SENSE_DIFFPAIR I29 I32 ? TABLE_SPACING_RULE_ITEM 39 99 ISNS_SSD_N TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM WEIGHT 0.058 MM TABLE_SPACING_RULE_ITEM THERM I27 I30 THERM_1TO1_55S THERM_1TO1_55S THERM_1TO1_55S I25 TABLE_PHYSICAL_RULE_ITEM LINE-TO-LINE SPACING TABLE_SPACING_RULE_ITEM I24 TABLE_PHYSICAL_RULE_HEAD LAYER TOP,BOTTOM TABLE_SPACING_RULE_ITEM SENSE_DIFFPAIR I22 TABLE_PHYSICAL_RULE_ITEM SPACING_RULE_SET 1x_DIELECTRIC TABLE_SPACING_RULE_ITEM I18 I19 C TABLE_SPACING_RULE_HEAD TABLE_SPACING_RULE_ITEM SENSE_DIFFPAIR I16 PHYSICAL_RULE_SET TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM I8 I9 TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM SENSE_DIFFPAIR I6 TABLE_PHYSICAL_RULE_ITEM ADC1_ISENSE_P AUDIO_DIFFPAIR TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM B TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM 85_OHM_DIFF ISL3,ISL4,ISL9,ISL10 Y 0.089 MM 0.089 MM 0.180 MM 0.180 MM 85_OHM_DIFF ISL2,ISL11 Y 0.089 MM 0.089 MM 0.180 MM 0.180 MM 85_OHM_DIFF TOP,BOTTOM Y 0.110 MM 0.110 MM 0.180 MM 0.180 MM TABLE_PHYSICAL_RULE_ITEM MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP GPU_FBGND_SENSE 73 74 THERM P1V05_GPU_PEX_IOVDD_SNS_P 74 79 74 79 I53 THERM_1TO1_55S I55 THERM_1TO1_55S THERM_1TO1_55S THERM P1V05_GPU_PEX_IOVDD_SNS_N SENSE_DIFFPAIR THERM_1TO1_55S THERM SPKRL_THMSNS_D2_P THERM_1TO1_55S THERM SPKRL_THMSNS_D2_N SENSE_DIFFPAIR THERM_1TO1_55S THERM SPKR_THMSNS_D2_P THERM_1TO1_55S THERM SPKR_THMSNS_D2_N THERM_1TO1_55S THERM TBT_THERMD_P 47 THERM_1TO1_55S THERM TBT_THERMD_N 47 THERM_1TO1_55S THERM X29THMSNS_D2_P THERM_1TO1_55S THERM X29THMSNS_D2_N THERM_1TO1_55S THERM VDDCIS0_CS_P I56 TABLE_PHYSICAL_RULE_HEAD ALLOW ROUTE ON LAYER? THERM THERM I33 LAYER 73 74 THERM_1TO1_55S TABLE_PHYSICAL_RULE_ITEM PHYSICAL_RULE_SET GPU_FBVDDQ_SENSE I54 I34 I35 TABLE_PHYSICAL_RULE_ITEM 90_OHM_DIFF * N =STANDARD =STANDARD 90_OHM_DIFF ISL3,ISL4,ISL9,ISL10 Y 0.081 MM 0.081 MM =STANDARD =STANDARD =STANDARD 0.200 MM 0.200 MM I36 TABLE_PHYSICAL_RULE_ITEM I37 90_OHM_DIFF ISL2,ISL11 Y 0.081 MM 0.081 MM 0.200 MM 0.200 MM 90_OHM_DIFF TOP,BOTTOM Y 0.099 MM 0.090 MM 0.200 MM 0.200 MM I39 TABLE_PHYSICAL_RULE_ITEM LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP I57 DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM 100_OHM_DIFF * N =STANDARD =STANDARD =STANDARD =STANDARD SENSE_DIFFPAIR I58 SENSE_DIFFPAIR THERM_1TO1_55S THERM VDDCIS0_CS_N I59 SENSE_DIFFPAIR THERM_1TO1_55S THERM GFXIMVP6_VSEN_P I60 SENSE_DIFFPAIR THERM_1TO1_55S THERM GFXIMVP6_VSEN_N =STANDARD TABLE_PHYSICAL_RULE_ITEM 100_OHM_DIFF ISL3,ISL4,ISL9,ISL10 Y 0.065 MM 0.065 MM 0.200 MM 0.200 MM 100_OHM_DIFF ISL2,ISL11 Y 0.065 MM 0.065 MM 0.200 MM 0.200 MM 100_OHM_DIFF TOP,BOTTOM Y 0.079 MM 0.079 MM 0.200 MM 0.200 MM I41 USB_85D USB3 I42 USB_85D USB3 I43 USB_85D USB3 I44 USB_85D USB3 I45 USB_85D USB3 I46 USB_85D USB3 I47 USB_85D USB3 I48 USB_85D USB3 I49 USB_85D USB3 I50 USB_85D USB3 I70 USB_85D USB3 I69 USB_85D USB3 TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 100_DIFF_BGA * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF TABLE_PHYSICAL_RULE_ITEM A SENSE_DIFFPAIR I40 TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET SENSE_DIFFPAIR I38 TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM 100_DIFF_BGA ISL3,ISL4 Y 0.075 MM 0.075 MM 0.125 MM 0.125 MM 100_DIFF_BGA ISL9,ISL10 Y 0.075 MM 0.075 MM 0.125 MM 0.125 MM TABLE_PHYSICAL_RULE_ITEM B USB3_EXTA_TX_F_P USB3_EXTA_TX_F_N USB3_EXTA_RX_F_P USB3_EXTA_RX_F_N USB3_EXTA_TX_C_P USB3_EXTA_TX_C_N USB3_EXTB_TX_C_P USB3_EXTB_TX_C_N USB3_EXTB_RX_RC_P USB3_EXTB_RX_RC_N USB3_EXTA_RX_RC_P USB3_EXTA_RX_RC_N 40 40 38 38 38 38 SYNC_MASTER=D2_KEPLER 40 SYNC_DATE=01/13/2012 PAGE TITLE 40 PCB Rule Definitions NOTE: 100_DIFF_BGA is 100-ohms differential impedance on outer layers and 95-ohms on inner layers DRAWING NUMBER Apple Inc 051-9589 R TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 1:1_DIFFPAIR * Y =STANDARD =STANDARD =STANDARD 0.1 MM 0.1 MM TABLE_PHYSICAL_RULE_ITEM I61 CLK_25M I62 CLK_25M P1V5_GPU_VSNS P1V0S0_VSNS NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED SIZE D REVISION 4.18.0 BRANCH PAGE 109 OF 132 SHEET 97 OF 99 A GPU 1.0V CURRENT SENSE SENSOR_NONPROD:Y SENSOR_NONPROD:Y =PP5V_S3_DEBUG_ISNS RD003 SENSOR_NONPROD:Y CD043 PP5V_S3_DEBUG_ADC_AVDD_FILT 20% 10V X7R-CERM 0402 SENSOR_NONPROD:Y SENSOR_NONPROD:Y P1V05_GPU_CS_P 96 74 P1V05_GPU_CS_N PLACE_NEAR=UD000 3:5MM DFN 96 ISNS_PP1V0_S0GPU_R_P V+ 1% 4.53K 1V0_GPU_IOUT D V- 402 THRM 0.1UF 20% 6.3V X5R 603 20% 10V CERM 402 ADC_CH4 98 AVDD SENSOR_NONPROD:Y CD042 2 96 ISNS_PP1V0_S0GPU_R_N ADC_CH1 23 98 ADC_CH2 24 98 ADC_CH3 98 ADC_CH4 98 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 22 NC PLACE_NEAR=UD000.4:5MM 1% SENSOR_NONPROD:Y 402 1SENSOR_NONPROD:Y RD042 RD043 1M 1M SIGNAL_MODEL=EMPTY 1% 1/16W MF-LF 402 10UF 20% 6.3V X5R 603 D DVDD UD000 10% 16V CERM 402 1/16W MF-LF CD012 SENSOR_NONPROD:Y 0.22UF 4.22K SENSOR_NONPROD:Y 10UF 20% 10V CERM 402 SENSOR_NONPROD:Y 1% 1/16W MF-LF 402 RD041 CD002 0.1UF RD044 1/16W MF-LF CD001 SENSOR_NONPROD:Y 5% 1/16W MF-LF 402 21 96 74 4.22K IG2C OPA2333 SENSOR_NONPROD:Y 12 RD040 MIN_NECK_WIDTH=0.25MM VOLTAGE=5V SENSOR_NONPROD:Y CD007 =PP5V_S3_DEBUG_ADC_DVDD MIN_LINE_WIDTH=0.3MM MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.25MM VOLTAGE=5V UD080 SENSOR_NONPROD:Y 10 PP5V_S3_DEBUG_ADC_DVDD_FILT 5% 1/16W MF-LF 402 0.1UF EDP Current: 2.846A RD018 10 =PP5V_S3_DEBUG_ADC_AVDD 13 98 NC NC NC 1% 1/16W MF-LF 402 SIGNAL_MODEL=EMPTY GAIN: 237X RD007 AD0 AD1 QFN 14 SDA SCL 5% 1/16W MF-LF 402 17 ADC_SDA 16 ADC_SCL =I2C_SMC_ADCS_SDA 15 SENSOR_NONPROD:Y COM PLACE_NEAR=U4900.F1:10mm 33 LTC2309 RD002 VREF REFCOMP =I2C_SMC_ADCS_SCL IN 44 5% 1/16W MF-LF 402 ADC_VREF ADC_REFCOMP SENSOR_NONPROD:Y SENSOR_NONPROD:Y THRM PAD SENSOR_NONPROD:Y CD004 CD006 10UF 20% 10V CERM 402 CD000 0.1UF 25 20 19 18 11 10 GND 44 PLACE_NEAR=U4900.E4:10mm 33 BI SENSOR_NONPROD:Y 2.2UF 20% 6.3V X5R 603 20% 6.3V CERM 402-LF CPU DDR CURRENT SENSE 98 =PP5V_S3_DEBUG_ISNS SENSOR_NONPROD:Y CD082 C C 0.1UF 20% 10V CERM 402 SENSOR_NONPROD:Y EDP CURRENT: 5.0A SENSOR_NONPROD:Y 69 IN NC_ISNS_P1V5R1V35_CPUDDRP UD082 RD081 7.68K 1 97 ISNS_CPU_DDR_R_P SC70-5 V+ 1% PLACE_NEAR=UD000.4:5MM OPA333DCKG4 + RD085 1/16W IC3C SENSOR_NONPROD:Y 4.53K ISNS_CPU_DDR_IOUT ADC_CH2 98 MF-LF - RD082 69 IN NC_ISNS_P1V5R1V35_CPUDDRN 1% 1/16W MF-LF 402 V- 402 0.22UF 7.68K 97 ISNS_CPU_DDR_R_N Gain: 130x SENSOR_NONPROD:Y SENSOR_NONPROD:Y CD081 1% 1/16W 20% 6.3V X5R 402 PLACE_NEAR=UD000.4:5MM MF-LF 402 SENSOR_NONPROD:Y SENSOR_NONPROD:Y RD083 RD084 1M 1M 1% SIGNAL_MODEL=EMPTY 1/16W MF-LF SENSOR_NONPROD:Y 1% 402 1/16W SIGNAL_MODEL=EMPTY LD000 MF-LF 402 120OHM-0.3A =PP5V_S0_RMC PP5V_S0_RMC_FLT MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=5V 0402 SENSOR_NONPROD:Y PLACE_NEAR=RD305.1:5MM PLACE_NEAR=CD010.1:2MM =PPVCORE_S0_CPU B PPVCORE_S0_RMC MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.1V CD009 99 45 10UF 1UF SM IN CD010 XWD000 45 15 13 LCD PANEL CURRENT SENSE SENSOR_NONPROD:Y CPU_VCORE_C SENSOR_NONPROD:Y 20% 6.3V CERM-X5R 0402 10.2 =PP1V05_S0_RMC 100 5% 1/16W MF-LF 402 2 0.1% 1/16W TF 402 PP1V05_S0_RMC_R DD000 SOD-523 A B 20% 10V CERM 402 SENSOR_NONPROD:Y V+ EDP CURRENT: 1.0A PLACE_NEAR=UD000.22:5MM ILDC UD070 SENSOR_NONPROD:Y MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V CD070 0.1UF RD009 RD000 SENSOR_NONPROD:Y 10% 16V X5R 402 SENSOR_NONPROD:Y =PP3V3_S0_ISNS RD071 INA214 81 IN NC_ISNS_LCD_PANELN 81 IN NC_ISNS_LCD_PANELP ININ+ SC70 OUT LCD_DRV_IOUT ADC_CH3 K REF SENSOR_NONPROD:Y 4.53K 98 1% 1/16W MF-LF 402 BAT54XV2T1 GND SENSOR_NONPROD:Y SENSOR_NONPROD:Y CD003 SENSOR_NONPROD:Y RD011 1 11K 10UF 20% 6.3V CERM-X5R 0402 SENSOR_NONPROD:Y 0.1% 1/16W MF 402 SENSOR_NONPROD:Y RD001 2 GAIN: 100X 0.1% 1/16W MF 402 10% 16V X7R-CERM 0402 SENSOR_NONPROD:Y NO_TEST=TRUE + V+ RD005 10.2 RD004 A 0.1% 1/16W MF 402 0.1UF 10% 16V X7R-CERM 0402 SENSOR_NONPROD:Y 11K SENSOR_NONPROD:Y CD005 RD006 10% 16V X7R-CERM 0402 UD002 SOD-523 COMP_CPU_VCORE_RMC V- CPU_VCORE_RMC_DIV - A K CPU_VCORE_RMCP + V+ SENSOR_NONPROD:Y VCRP OPA365 RD020 SOT23 BAT54XV2T1 VSNS_CPU_VCORE_RMC_OUT 4.53K ADC_CH1 NO_TEST=TRUE 0.1% 1/16W TF 402 CPU_VCORE_RMCN NO_TEST=TRUE 1% 1/16W MF-LF 402 V- - 2 OUT 98 SENSOR_NONPROD:Y 1.00K PLACE_NEAR=UD000.22:5MM SENSOR_NONPROD:Y DD001 SOT23 NO_TEST=TRUE NO_TEST=TRUE SENSOR_NONPROD:Y SENSOR_NONPROD:Y OPA365 CD018 20% 6.3V X5R 402 0.1UF SENSOR_NONPROD:Y UD001 1V05_S0_RMC_DIV SENSOR_NONPROD:Y 0.1UF 1.00K CD071 0.22UF CD008 CD020 0.22UF 0.1% 1/16W MF 402 SIGNAL_MODEL=EMPTY SYNC_MASTER=D2_SEAN SENSOR_NONPROD:Y RD021 RD008 DEBUG SENSORS AND ADC 1K 10 SYNC_DATE=03/05/2012 PAGE TITLE SENSOR_NONPROD:Y PLACE_NEAR=RD305.1:5MM 10% 10V CERM 402 DRAWING NUMBER 1% 1/16W MF-LF 402 5% 1/16W MF-LF 402 Apple Inc R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED 051-9589 SIZE D REVISION 4.18.0 BRANCH PAGE 130 OF 132 SHEET 98 OF 99 A LCD BKLT Current Sense 99 TBT (T29) CURRENT SENSE =PP5V_S3_ISNS CD200 0.1UF SENSOR_NONPROD:Y 20% 10V CERM 402 99 98 45 =PP3V3_S0_ISNS EDP Current: 0.715A SENSOR_NONPROD:Y V+ =PPBUS_SW_BKL UD200 D INA214 NC_ISNS_LCDBKLTN XWD200 SM RD201 NC_ISNS_LCDBKLTP IN- OUT SC70 IN+ REF SMC_LCDBKLT_ISENSE RD259 ISNS_TBT_P 931 1% 1W MF 0612 CD201 0.22UF 20% 6.3V X5R 402 GAIN: 100X =PP1V05_S0_P1V05TBTFET GND_SMC_AVSS 96 931 ISNS_TBT_N UD250 V+ PLACE_NEAR=UD4900.A8:5MM 4.53K ISNS_TBT_IOUT GAIN: 1074.11X ISNS_TBT_R_N SMC_TBT_ISENSE 1% 1/16W MF-LF 402 V- - SMC_ADC23 RD255 SC70-5 CD250 PLACE_NEAR=U4900.A8:5MM 20% 6.3V X5R 402 GND_SMC_AVSS 41 RD253 1M 1% 1/20W MF 201 42 45 46 99 RD254 1M =PP3V3_S0_ISNS 42 0.22UF 1% 1/20W MF 201 41 42 45 46 99 D IHSC OPA333DCKG4 + SSD CURRENT SENSE 20% 10V CERM 402 ISNS_TBT_R_P RD252 PLACE_NEAR=U4900.G1:5MM 37 1% 1/20W MF 201 0.001 SENSOR_NONPROD:Y SENSOR_NONPROD:Y 96 CRITICAL GND PPBUS_SW_LCDBKLT_PWR =PP1V05_S0_P1V05TBTFET_R 42 1% 1/16W MF-LF 402 86 RD251 4.53K LCDBKLT_IOUT CD251 0.1UF SENSE RESISTOR 0.001 OHM EDP CURRENT: 3.0 A IBLC SMC_ADC17 PLACE_NEAR=U4900.G1:5MM 1% 1/20W MF 201 CD258 0.1UF Sense Resistor 0.005 Ohm EDP CURRENT: 5A 97 39 RD260 7.68K ISNS_SSD_P 97 ISNS_SSD_R_P UD240 OPA333DCKG4 1% 1/16W MF-LF 402 + V+ RD261 97 39 RD264 4.53K ISNS_SSD_IOUT - 99 SMC_SSD_ISENSE 1% 1/16W MF-LF 402 GAIN: 130X 97 ISNS_SSD_R_N =PP5V_S3_ISNS 42 CD282 CD240 0.22UF 20% 6.3V X5R 402 1% C GPU FB (1.35V/1.5V) CURRENT SENSE IHDC SMC_ADC6 PLACE_NEAR=U4900.A3:5MM SC70-5 V- 7.68K ISNS_SSD_N 20% 10V CERM 402 1/16W MF-LF 402 0.1UF EDP Current: 7.8A Rsense(R8380)=0.002 Ohm PLACE_NEAR=U4900.A3:5MM UD280 RD281 GND_SMC_AVSS RD262 96 74 V+ C SMC_ADC19 4.53K P1V5_S0GPU_IOUT SMC_GPU_P1V35_ISENSE 42 1/16W V- MF-LF 1% 1/16W MF-LF 402 402 SIGNAL_MODEL=EMPTY 1% 1/16W MF-LF 402 SIGNAL_MODEL=EMPTY RD285 DFN 1% 1M 1% 1/16W MF-LF 402 96 ISNS_PP1V5_S0GPU_R_P IG3C PLACE_NEAR=U4900.H2:5MM OPA2333 7.68K GPUFB_CS_P RD263 1M 41 42 45 46 99 20% 10V CERM 402 THRM RD282 96 74 CD281 0.22UF 7.68K GPUFB_CS_N 96 20% 6.3V X5R 402 ISNS_PP1V5_S0GPU_R_N Gain: 130x 1% 1/16W PLACE_NEAR=U4900.H2:5MM MF-LF 402 GND_SMC_AVSS 41 42 45 46 99 RD283 1M 1% www.qdzbwx.com =PP3V3_S3_ISNS RD284 1M X29 AIRPORT CURRENT SENSE 1/16W 1% 402 SIGNAL_MODEL=EMPTY 1/16W SIGNAL_MODEL=EMPTY MF-LF SENSOR_NONPROD:Y MF-LF 402 CD230 0.1UF RD230 SENSOR_NONPROD:Y 2.61K 34 PP3V3_WLAN_R NC_ISNS_AIRPORTP 96 ISNS_AIRPORT_R_P UD230 OPA333DCKG4 1% 1/16W MF-LF 402 + V+ XWD235 SM RD231 PP3V3_WLAN_F NC_ISNS_AIRPORTN B RD234 4.53K ISNS_AIRPORT_IOUT 2 IAPC SMC_ADC22 SMC_X29_ISENSE 1% 1/16W MF-LF 402 PCH VCORE CURRENT SENSE 42 SENSOR_NONPROD:Y CD231 96 ISNS_AIRPORT_R_N 0.22UF GAIN: 383X SENSOR_NONPROD:Y 1% SENSOR_NONPROD:Y PLACE_NEAR=U4900.B8:5MM SC70-5 V- - 2.61K 34 20% 10V CERM 402 SENSOR_NONPROD:Y 1/16W MF-LF 402 20% 6.3V X5R 402 =PP3V3_S0_ISNS 99 98 45 SENSOR_NONPROD:Y RD232 RD233 1M GND_SMC_AVSS V+ 41 42 45 46 99 EDP CURRENT:6.0A SIGNAL_MODEL=EMPTY 1M 1% 1/16W MF-LF 402 CD221 0.1UF 20% 10V CERM 402 SENSOR_NONPROD:Y MF-LF 97 87 402 IN- PCHVCCIOS0_CS_N IN SENSOR_NONPROD:Y 97 87 OUT CRITICAL SC70 PCH_CORE_IOUT 4.53K 1% 1/16W MF-LF 402 REF SMC_PCH_CORE_ISENSE CD222 0.22UF PLACE_NEAR=U4900.A7:5MM 2 402 GND_SMC_AVSS QTY 116S0114 DESCRIPTION REFERENCE DES RES,MTL FILM,100K,5,1/16W,0402,SMD,LF CRITICAL 42 SENSOR_NONPROD:Y 20% 6.3V X5R GND PART NUMBER SMC_ADC21 RD223 INA210 IN+ PCHVCCIOS0_CS_P IN ISBC SENSOR_NONPROD:Y PLACE_NEAR=U4900.A7:5mm UD220 SENSOR_NONPROD:Y 1% 1/16W SIGNAL_MODEL=EMPTY B PLACE_NEAR=U4900.B8:5MM Sense Resistor 0.005 Ohm EDP Current: 1.06A 41 42 45 46 99 Gain:200x BOM OPTION SENSOR_NONPROD:N CD201,CD222,CD231 LCD BKLT Voltage Sense XWD250 CPU VCCSA VOLTAGE SENSE SM 86 81 PLACE_NEAR=R7140.1:2MM XWD245 A =PPVCCSA_S0_REG VCCSA_VSENSE_IN 4.53K VC2C SMC_ADC20 RD214 SM 62 PPVOUT_S0_LCDBKLT SMC_CPU_SA_VSENSE 1% 1/16W MF-LF 402 0.22UF RD256 100K 42 CD211 PLACE_NEAR=U4900.7:5MM VOUT_S0_LCDBKLT_XW 1% 1/16W MF-LF 402 VOUT_S0_LCDBKLT_DIV PLACE_NEAR=U4900.B7:5MM 20% 6.3V X5R 402 RD257 RD258 4.53K 1% 1/16W MF-LF 402 SMC_LCDBKLT_VSENSE 0.22UF 1% 402 DRAWING NUMBER 42 20% 6.3V X5R 402 051-9589 PLACE_NEAR=U4900.G2:5MM 41 42 45 46 99 NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED SIZE D REVISION R GND_SMC_AVSS SMC12 SENSORS EXTENDED CD252 1/16W MF-LF SYNC_DATE=01/13/2012 PAGE TITLE Apple Inc 4.64K SYNC_MASTER=D2_KEPLER VBLC SMC_ADC16 PLACE_NEAR=U4900.G2:5MM 4.18.0 BRANCH PAGE 132 OF 132 SHEET 99 OF 99 A ... OPTIONS TABLE_BOMGROUP_ITEM D2_PVB VREF:PROD,D_BKL:PROD,SENSOR_NONPROD:N D2_PROGPARTS SMC_PROG:FSB,BOOTROM_PROG:FSB,DPMUXMCU:PROG,TPAD_PSOC:PROG,TBTROM:PROG D2_DEVEL:ENG ALTERNATE,IVB_PPT_XDP,S0PGOOD_ISL,DPMUX_DEBUG,DDRVREF_DAC,VREF:ENG_M3,SENSOR_NONPROD:Y,D_BKL:DEV... DRAWING NUMBER PP1V2_ENET Apple Inc P1V2ENET_PGOOD PBUSVSENS_EN NOTICE OF PROPRIETARY PROPERTY: P1V5CPU_EN THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR... Revision History DRAWING NUMBER Apple Inc 051-9589 REVISION R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO