apple macbook pro 13 a1278 k24 820 2530

8 ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5% ALL CAPACITANCE VALUES ARE IN MICROFARADS ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ REV ECN DESCRIPTION OF REVISION C 0000734528 CK APPD DATE PRODUCTION RELEASED 2009-06-04 K24 MLB SCHEMATIC 6/12/2009 D (.csa) Date Page Contents TABLE_TABLEOFCONTENTS_HEAD TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM C TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM B TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 Sync Table of Contents (.csa) System Block Diagram 08/22/2007 TABLE_TABLEOFCONTENTS_HEAD 12/12/2007 TABLE_TABLEOFCONTENTS_ITEM T18_MLB 03/13/2008 Power Block Diagram TABLE_TABLEOFCONTENTS_ITEM DRAGON TABLE_TABLEOFCONTENTS_ITEM BOM Configuration M97_MLB TABLE_TABLEOFCONTENTS_ITEM Revision History M97_MLB TABLE_TABLEOFCONTENTS_ITEM FUNC TEST M97_MLB 04/21/2008 Power Aliases TABLE_TABLEOFCONTENTS_ITEM BEN TABLE_TABLEOFCONTENTS_ITEM SIGNAL ALIAS M97_MLB CPU FSB T18_MLB 10 12/12/2007 11 CPU Power & Ground T18_MLB CPU Decoupling RAYMOND 12 13 eXtended Debug Port(MiniXDP) TABLE_TABLEOFCONTENTS_ITEM 12/12/2007 TABLE_TABLEOFCONTENTS_ITEM 03/31/2008 TABLE_TABLEOFCONTENTS_ITEM 11/07/2008 TABLE_TABLEOFCONTENTS_ITEM 04/04/2008 TABLE_TABLEOFCONTENTS_ITEM 04/04/2008 TABLE_TABLEOFCONTENTS_ITEM 04/04/2008 TABLE_TABLEOFCONTENTS_ITEM 04/04/2008 TABLE_TABLEOFCONTENTS_ITEM K19_MLB 14 MCP CPU Interface T18_MLB 15 MCP Memory Interface T18_MLB 16 MCP Memory Misc T18_MLB MCP PCIe Interfaces T18_MLB 17 18 MCP Ethernet & Graphics 04/04/2008 TABLE_TABLEOFCONTENTS_ITEM 04/04/2008 TABLE_TABLEOFCONTENTS_ITEM 04/04/2008 TABLE_TABLEOFCONTENTS_ITEM 06/26/2008 TABLE_TABLEOFCONTENTS_ITEM 04/04/2008 TABLE_TABLEOFCONTENTS_ITEM 04/04/2008 TABLE_TABLEOFCONTENTS_ITEM 12/12/2007 TABLE_TABLEOFCONTENTS_ITEM T18_MLB 19 MCP PCI & LPC T18_MLB 20 MCP SATA & USB T18_MLB 21 MCP HDA & MISC T18_MLB 22 MCP Power & Ground T18_MLB 25 MCP Standard Decoupling T18_MLB MCP Graphics Support T18_MLB 26 28 SB Misc 04/05/2008 TABLE_TABLEOFCONTENTS_ITEM 03/31/2008 TABLE_TABLEOFCONTENTS_ITEM 06/30/2008 TABLE_TABLEOFCONTENTS_ITEM 05/09/2008 TABLE_TABLEOFCONTENTS_ITEM 04/04/2008 TABLE_TABLEOFCONTENTS_ITEM 04/22/2008 TABLE_TABLEOFCONTENTS_ITEM 01/30/2009 TABLE_TABLEOFCONTENTS_ITEM 05/23/2008 TABLE_TABLEOFCONTENTS_ITEM 07/01/2008 TABLE_TABLEOFCONTENTS_ITEM 04/04/2008 TABLE_TABLEOFCONTENTS_ITEM 11/02/2008 TABLE_TABLEOFCONTENTS_ITEM 12/22/2008 TABLE_TABLEOFCONTENTS_ITEM RAYMOND 29 FSB/DDR3 Vref Margining BEN 31 DDR3 SO-DIMM Connector A BEN 32 DDR3 SO-DIMM Connector B BEN 33 DDR3 Support T18_MLB 34 Right Clutch Connector YITE SECUREDIGITAL CARD READER VEMURI 35 37 Ethernet PHY (RTL8211CL) SUMA 38 Ethernet & AirPort Support SUMA 39 ETHERNET CONNECTOR SUMA 41 FireWire LLC/PHY (FW643) K19_MLB FireWire Port Power YUN_K19_MLB 42 TABLE_TABLEOFCONTENTS_ITEM Date Page T17_MLB D 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 Contents Sync 43 FireWire Ports (.csa) 11/02/2008 TABLE_TABLEOFCONTENTS_HEAD 12/04/2008 TABLE_TABLEOFCONTENTS_ITEM K19_MLB 45 SATA Connectors K19_MLB 46 External USB Connectors 01/18/2008 TABLE_TABLEOFCONTENTS_ITEM 05/28/2008 TABLE_TABLEOFCONTENTS_ITEM 06/26/2008 TABLE_TABLEOFCONTENTS_ITEM 05/28/2008 TABLE_TABLEOFCONTENTS_ITEM 05/09/2008 TABLE_TABLEOFCONTENTS_ITEM 04/21/2008 TABLE_TABLEOFCONTENTS_ITEM 02/04/2008 TABLE_TABLEOFCONTENTS_ITEM YUAN.MA 48 Front Flex Support YUAN.MA 49 SMC T18_MLB 50 SMC Support YUAN.MA 51 LPC+SPI Debug Connector CHANGZHANG 52 K24 SMBUS CONNECTIONS BEN VOLTAGE SENSING YUNWU 53 54 Current Sensing YUNWU Thermal Sensors YUNWU 55 56 Fan CHANGZHANG WELLSPRING YUAN.MA WELLSPRING YUAN.MA 57 Date Page 12/17/2008 TABLE_TABLEOFCONTENTS_ITEM 03/20/2008 TABLE_TABLEOFCONTENTS_ITEM 01/18/2008 TABLE_TABLEOFCONTENTS_ITEM 71 72 73 74 75 76 77 78 79 80 81 Contents Sync 97 12/05/2008 LCD BACKLIGHT DRIVER KIRAN LCD Backlight Support YITE CPU/FSB Constraints T18_MLB Memory Constraints T18_MLB MCP Constraints T18_MLB MCP Constraints T18_MLB Ethernet Constraints T18_MLB FireWire Constraints K19_MLB SMC Constraints T18_MLB K24 SPECIAL CONSTRAINTS M97_MLB K24 RULE DEFINITIONS M97_MLB 98 06/30/2008 100 01/04/2008 101 01/04/2008 102 01/04/2008 103 12/14/2007 104 03/19/2008 105 12/01/2008 106 01/04/2008 C 107 109 04/22/2008 58 05/09/2008 59 06/26/2008 SMS YUNWU SPI ROM CHANGZHANG AUDIO: CODEC/REGULATOR AUDIO AUDIO: LINE INPUT FILTER AUDIO AUDIO: HEADPHONE FILTER AUDIO AUDI0: SPEAKER AMP AUDIO AUDIO: JACK AUDIO AUDIO: JACK TRANSLATORS AUDIO DC-In & Battery Connectors YUNWU PBUS Supply/Battery Charger RAYMOND 5V/3.3V SUPPLY RAYMOND 1.5V/0.75V DDR3 SUPPLY RAYMOND IMVP6 CPU VCore Regulator RAYMOND MCP CORE REGULATOR K19_MLB 61 05/02/2008 62 03/04/2009 63 01/31/2009 65 02/03/2009 66 12/18/2008 67 03/20/2009 68 03/20/2009 69 12/11/2008 70 01/31/2008 72 02/08/2008 73 01/31/2008 74 01/31/2008 75 B 12/10/2008 76 02/08/2008 CPU VTT(1.05V) SUPPLY RAYMOND MISC POWER SUPPLIES RAYMOND POWER SEQUENCING YUAN.MA POWER FETS YUAN.MA LVDS CONNECTOR NMARTIN DISPLAYPORT SUPPORT AMASON DisplayPort Connector AMASON 77 01/23/2008 78 12/11/2008 79 12/11/2008 90 04/04/2008 93 04/18/2008 94 06/30/2008 TABLE_TABLEOFCONTENTS_ITEM A A DRAWING TITLE SCHEM,MLB,K24 Schematic / PCB #’s DRAWING NUMBER Apple Inc 051-7898 REVISION R PART NUMBER QTY DESCRIPTION REFERENCE DES 051-7898 SCHEM,MLB,K24 SCH CRITICAL 820-2530 PCBF,MLB,K24 PCB CRITICAL CRITICAL BOM OPTION NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED C.0.0 BRANCH PAGE OF 109 SHEET OF 81 SIZE D U1000 U1300 INTEL CPU XDP CONN 2.X OR 3.X GHZ PG 12 PENRYN PG FSB D D J6950 64-Bit 800/1067/1333 MHz DC/BATT POWER SUPPLY PG 13 PG 60 J2900 UDIMMs MAIN FSB INTERFACE GPIOs DDR2-800MHZ DDR3-1067/1333MHZ MEMORY DIMM PG 14 U4900 PG 25,26 TEMP SENSOR PG 41 Misc CLK PG 24 U6100 SYNTH POWER SENSE PG 45 SPI Boot ROM J4510 J5650,5600,5610,5611,5660,5720,5730,5750 FAN CONN AND CONTROL SPI SATA PG 52 Conn 1.05V/3GHZ PG 48,49 PG 20 PG 38 HD NVIDIA J4520 J4900 B,0 SATA Conn PG 38 C Ser Fan ADC BSB J5100 MCP79 SATA 1.05V/3GHZ Prt SMC LPC Conn LPC PG 19 ODD Port80,serial PG 41 C PG 43 PG 18 U1400 J9000 PWR LVDS CONN CTRL LVDS OUT PG 71 RGB OUT J4720 J3500 DP OUT SD CARD READER J4700 J4710 J4710 TRACKPAD/ KEYBOARD Bluetooth J9400 IR J3900,4635,4655 CAMERA EXTERNAL USB Connectors HDMI OUT PG 30 PG 40 PG 40 PG 40 PG 40 PG 16 PG 34 11 PCI-E B PG 34 UP TO 20 LANES3 FIREWIRE PORT FW643 CONN J4310 USB PG 17 PG 19 TMDS OUT PG 71 DVI OUT (UP TO 12 DEVICES) PG 39 DISPLAY PORT CONN B SMB SMB PG 20 PG 34 CONN RGMII HDA PCI PG 44 DIMM’s (UP TO FOUR PORTS) PG 17 PG 18 PG 20 J3400 Mini PCI-E AirPort U6200 Audio PG 28 Codec PG 53 U6301 U6400 U6500 U6600,6605,6610,6620 U3700 A GB Line In Line Out Speaker E-NET Amp Amp Amp Amps PG 54 PG 55 PG 56 PG 57 HEADPHONE SYNC_MASTER=T18_MLB SYNC_DATE=12/12/2007 System Block Diagram PG 31 DRAWING NUMBER Apple Inc U3900 J6800,6801,6802,6803 NOTICE OF PROPRIETARY PROPERTY: Audio Conn THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED Conns PG 33 PG 56 SIZE 051-7898 D REVISION C.0.0 R E-NET A PAGE TITLE RTL8211CL BRANCH PAGE OF 109 SHEET OF 8 K24 POWER SYSTEM ARCHITECTURE PP18V5_DCIN_CONN D6905 02 PPVIN_G3H_P3V42G3H D6905 V 7A FUSE PPVBAT_G3H_CHGR_REG D 01 ENABLE PP3V42_G3H_REG 03 3.425V G3HOT LT3470 VOUT U6990 PBUS_VSENSE SMC PWRGD 04 RN5VD30A-F U5000 Q5315 D 23 R5492 PPBUS_G3H_CPU_ISNS PPBUS_G3H_CPU_ISNS_R PPBUS_G3H 02 F7000 PP5V_S0_CPUVTTS0 VIN AC DCIN(16.5V) ADAPTER IN CPUVTTS0_EN (S0) CHGR_EN (S5) F6905 6A FUSE (1.05V) VOUT 31 PLTRST* CPUVTTS0_PGOOD V 01 CPU VCORE 06 P1V05ENET_EN 1.05V SO PP1V05_ENET_FET PPBUS_G3H 4.5V AUDIO VIN TPS7174S (Q3841) U6200 11 11-1 P3V3S3_EN RC DELAY PM_SLP_S4_L PP4V5_AUDIO_ANALOG RESET* U1000 PP1V05_S5_REG 08 02 Q7940 PP5V_S3_REG PP5V_S0_FET P16 SLP_S3# 11-3 P60 P5VRTS0_EN_L 04 U4900 DDRREG_EN RC DELAY U1400 SMC_PM_G2_EN Q7800 (S5) 02 11-2 SMC_PM_G2_EN P5VLTS3_EN RC DELAY 5V (RT) VOUT1 PP5V_S3 PP5V_S3_REG VOUT2 EN2 17 (4A MAX CURRENT) PP3V3_S5_REG P3V3S5_EN_L 15-1 VIN EN1 05 PCI_RESET0# 3.3V PP3V3_S5 P5VS0_EN 07 (4A MAX CURRENT) Q7910 TPS51125 U7200 PGOOD1,2 PP3V3_S3_FET 13 VREG3 VIN BKLT_EN B P3V3S3_EN LP8543 U9701 ENA P5V3V3_PGOOD PPVOUT_S0_LCDBKLT VOUT PP3V3_S0_FET 15 RSMRST_OUT(P15) PWRGD(P12) 18 09 Q3801 PM_ENET_EN_L SMC 24 ALL_SYS_PWRGD Q7930 RSMRST_PWRGD SMC_ONOFF_L P3V3S0_EN 16 05 Q3810 99ms DLY IMVP_VR_ON(P16) RSMRST_IN(P13) PLT_RST* PWR_BUTTON(P90) P17(BTN_OUT) RST* P3V3_ENET_FET P5V3V3_PGOOD Q3802 P3V3ENET_EN_L MCPCORESO_PGOOD CPUVTTS0_PGOOD WOL_EN SMC_ADAPTER_EN 04-1 VIN =DDRREG_EN =DDTVTT_EN PM_SLP_S3_L RC DELAY RC DELAY P1V8S0_EN 16-3 MCPDDR_EN 16-2 16-2 P1V05S0_EN (S0) P3V3S0_EN (S0) SLP_S5_L SLP_S4_L SLP_S3_L P5V_LT_S3_PGOOD S3 TO S0 FETS 02 A 32 U7750 VOUT SMC 15 PM_SLP_S3_L PWRGOOD VOUT EN ISL8009 C CPU 22 1.05V (S5) 06 P1V05_S5_EN FSB_CPURST_L VR_PWRGOOD_DELAY PGOOD FETS CHGR_BGATE CPU_RESET# U1400 U7400 CPU_PWRGD 30 U2850 28 25 PPVBAT_G3H_CHGR_OUT CPUPWRGD(GPIO49) 26 (44A MAX CURRENT) SMC_CPU_ISENSE IMVP_VR_ON VR_ON Q7050 29 PPVCORE_S0_CPU ISL9504B LPC_RESET_L RSMRST* MCP_PS_PWRGD PS_PWRGD SMC_CPU_VSENSE VOUT VIN MCP79 06-1 PWRBTN* PGOOD A J6950 BATT_POS_F MCP79 SMC_BATT_ISENSE 02 (9 TO 12.6V) PP1V05_S0 (8A MAX CURRENT) TPS51117 U7600 U5403 ISL6258A U7000 3S2P VOUT CPUVTT ENABLES VIN PBUS SUPPLY/ BATTERY CHARGER C EN_PSV S5 S3 PP1V5_S0_FET PP1V5_S0 1.5V TPS62202 U7760 PP1V5_S3_REG (12A MAX CURRENT) VOUT1 14 TPS51116 U7300 PP1V8_S0_REG MCP_CORE VOUT2 EN2 PM_PWRBTN_L SMC_RESET_L SLP_S4_L(P94) SLP_S3_L(P93) U4900 19-1 PP3V3_S0 V1 PP1V5_S0 V2 PP1V05_S0 V3 20 MCPCORES0_EN 25 RST* PP0V75_S0_REG (1A MAX CURRENT) 16-2 PPVCORE_S0_MCP_REG_R R7572 LTC2909 U7870 SYNC_MASTER=DRAGON SYNC_DATE=03/13/2008 RC DELAY CPUVTTS0_EN MCPCORES0_EN 16-3 16-4 PBUSVSENS_EN (S0) Power Block Diagram PPVCORE_S0_MCP DRAWING NUMBER (25A MAX CURRENT) Apple Inc P5VRTS0_EN_L (S0) 5V (LT) 16-2 EN1 NOTICE OF PROPRIETARY PROPERTY: VOUT1 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED VIN 16-1 02 ISL6236 U7500 A PAGE TITLE SIZE 051-7898 D REVISION C.0.0 R RC DELAY B 1.8V LDO (Q7901 & Q7971) 0.75V VOUT2 IMVP_VR_ON 10 SLP_S5_L(P95) S0PGOOD_PWROK 21 PM_RSMRST_L BRANCH PAGE OF 109 SHEET OF BOM Variants Bar Code Labels / EEE #’s TABLE_BOMGROUP_HEAD BOM NUMBER BOM NAME BOM OPTIONS 630-9923 PCBA,MLB,BETTER,K24 K24_COMMON,CPU_2_26GHZ,EEE_6GC,KB_BL PART NUMBER DESCRIPTION REFERENCE DES 826-4393 QTY LBL,P/N LABEL,PCB,28MM X MM [EEE:6G4] CRITICAL CRITICAL BOM OPTION EEE_6G4 826-4393 LBL,P/N LABEL,PCB,28MM X MM [EEE:6GC] CRITICAL EEE_6GC 826-4393 LBL,P/N LABEL,PCB,28MM X MM [EEE:6GD] CRITICAL EEE_6GD TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM 630-9924 PCBA,MLB,BEST,K24 K24_COMMON,CPU_2_53GHZ,EEE_6GD,KB_BL BOM Groups D D TABLE_BOMGROUP_HEAD BOM GROUP BOM OPTIONS TABLE_BOMGROUP_ITEM K24_COMMON COMMON,ALTERNATE,K24_MCP,K24_MISC,K24_DEBUG_PROD,K24_PROGPARTS K24_MCP MCP_B03,BOOT_MODE_USER,MCPSEQ_SMC K24_MISC ONEWIRE_PU,DP_ESD,MIKEY,BKLT_PROD,SUPERCAP_NO,LDO_NO TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM K24 BOARD STACK-UP TABLE_BOMGROUP_ITEM K24_PROGPARTS BOOTROM_PROG,SMC_PROG,IR_PROG,WELLSPRING_PROG K24_DEBUG_ENG DEVEL_BOM,SMC_DEBUG_YES,XDP K24_DEBUG_PVT DEVEL_BOM,BMON_PROD,SMC_DEBUG_YES,XDP,NO_VREFMRGN K24_DEBUG_PROD BMON_PROD,SMC_DEBUG_YES,XDP,LPCPLUS_NOT,NO_VREFMRGN K24_DEVEL_ENG BMON_ENG,XDP_CONN,LPCPLUS,VREFMRGN,FWPHY_WAKE_YES TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM Top 10 11 BOTTOM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM K24_DEVEL_PVT LPCPLUS Module Parts PART NUMBER C QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION 337S3646 PDC,SLG8E,PRQ,2.0,25W,1066,M0,3M,BGA U1000 CRITICAL CPU_2_0GHZ 337S3704 PDC,SLGE2,PRQ,2.26,25W,1066,R0,3M,BGA U1000 CRITICAL CPU_2_26GHZ 337S3639 PDC,SLB4N,PRQ,2.4,25W,1066,M0,3M,BGA U1000 CRITICAL CPU_2_4GHZ 337S3756 PDC,SLGFG,PRQ,2.53,25W,1066,R0,3M,BGA U1000 CRITICAL CPU_2_53GHZ 337S3761 PDC,SLGLA,PRQ,2.66,25W,1066,E0,3M,BGA U1000 CRITICAL CPU_2_66GHZ 338S0710 IC,GMCP,MCP79,35X35MM,BGA1437,B03 U1400 CRITICAL MCP_B03 Programmable Parts 338S0563 IC,SMC,HS8/2117,9X9MM,TLP,HF U4900 CRITICAL 341S2445 335S0610 341S2441 338S0375 SMC_BLANK IC,SMC,K24 U4900 CRITICAL SMC_PROG IC,FLASH,SPI,32MBIT,3.3V,86MHZ,8-SOP U6100 CRITICAL BOOTROM_BLANK IC,PRGRM,EFI BOOTROM,UNLOCK,K24 U6100 CRITICAL BOOTROM_PROG IC,CY7C63833,ENCORE II,USB CONTROLLER U4800 CRITICAL IR_BLANK 341S2093 IC,IR CONTROLLER,M97 U4800 CRITICAL IR_PROG 337S2983 IC,PSOC+ W/ USB,56 PIN,MLF,CY8C24794 U5701 CRITICAL WELLSPRING_BLANK 341S2503 IC,PRGRM,WELLSPRING CONTROLLER U5701 CRITICAL WELLSPRING_PROG SIGNAL GROUND SIGNAL(High SIGNAL(High GROUND POWER POWER GROUND SIGNAL(High SIGNAL(High GROUND SIGNAL Speed) Speed) C Speed) Speed) LOCKED BOOTROM APN IS 341S2443 Alternate Parts TABLE_ALT_HEAD PART NUMBER ALTERNATE FOR PART NUMBER BOM OPTION REF DES COMMENTS: 152S0778 152S0693 ALL CYNTEC AS ALTERNATE 152S0796 152S0685 ALL CYNTEC AS ALTERNATE 157S0058 157S0055 ALL DELTA AS ALTERNATE 104S0018 104S0023 ALL DALE/VISHAY AS ALTERNATE 128S0093 128S0218 ALL KEMET AS ALTERNATE 152S0874 152S0516 ALL MAGLAYERS AS ALTERNATE 152S0847 152S0586 ALL MAGLAYERS AS ALTERNATE 152S1025 152S1024 ALL TOKO AS ALTERNATE 337S3769 337S3704 ALL INTEL P7550 CPU AS ALTERNATE 353S2718 353S2310 ALL INTERSIL AS ALTERNATE TABLE_ALT_ITEM B B TABLE_ALT_ITEM TABLE_ALT_ITEM TABLE_ALT_ITEM TABLE_ALT_ITEM TABLE_ALT_ITEM TABLE_ALT_ITEM TABLE_ALT_ITEM TABLE_ALT_ITEM TABLE_ALT_ITEM A A SYNC_MASTER=M97_MLB PAGE TITLE BOM Configuration DRAWING NUMBER DEVELOPMENT BOM Apple Inc PART NUMBER 085-0741 QTY DESCRIPTION REFERENCE DES K24 MLB DEVELOPMENT BOM DEVEL CRITICAL CRITICAL NOTICE OF PROPRIETARY PROPERTY: DEVEL_BOM THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED D REVISION C.0.0 R BOM OPTION SIZE 051-7898 BRANCH PAGE OF 109 SHEET OF 8 Revision History D D C C B B A A SYNC_MASTER=M97_MLB PAGE TITLE Revision History DRAWING NUMBER Apple Inc NOTE: All page numbers are csa, not PDF THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED See page for csa -> PDF mapping D REVISION C.0.0 R NOTICE OF PROPRIETARY PROPERTY: SIZE 051-7898 BRANCH PAGE OF 109 SHEET OF Functional Test Points Fan Connectors D I12 I15 I16 PP5V_S0 FAN_RT_PWM FAN_RT_TACH TRUE TRUE TRUE (NEED TP) 6D3 7D5 I303 47B4 I301 47C4 I302 (NEED TO ADD GND TP) I238 I237 I239 MIC FUNC_TEST TRUE BI_MIC_LO TRUE BI_MIC_HI TRUE BI_MIC_SHIELD I300 I299 I298 I293 56C2 57B1 I297 56C2 57B1 I294 56C2 57B1 I288 I227 I226 I228 I230 I229 I231 SPEAKER TRUE TRUE TRUE TRUE TRUE TRUE FUNC_TEST SPKRAMP_L_N_OUT SPKRAMP_L_P_OUT SPKRAMP_R_N_OUT SPKRAMP_R_P_OUT SPKRAMP_SUB_N_OUT SPKRAMP_SUB_P_OUT I292 I296 55A2 56B2 I291 55B2 56B2 I295 55C2 56A2 I290 55C2 56B2 I271 55B2 56B2 I289 RIGHT CLUTCH CONN PP5V_S3_BTCAMERA_F TRUE PCIE_MINI_D2R_P TRUE PCIE_MINI_D2R_N TRUE PCIE_MINI_R2D_P TRUE PCIE_MINI_R2D_N TRUE PCIE_CLK100M_MINI_CONN_P TRUE PCIE_CLK100M_MINI_CONN_N TRUE USB_CAMERA_CONN_P TRUE USB_CAMERA_CONN_N TRUE (NEED PP5V_WLAN TRUE PCIE_WAKE_L TRUE SMBUS_SMC_A_S3_SCL TRUE SMBUS_SMC_A_S3_SDA TRUE CONN_USB2_BT_P TRUE CONN_USB2_BT_N TRUE MINI_CLKREQ_Q_L TRUE MINI_RESET_CONN_L TRUE DEBUG VOLTAGE 29C7 I287 16B6 29C7 75D3 I285 16B6 29C7 75D3 I284 29C7 75D3 I280 29C7 75D3 I281 29C7 75D3 I282 29C7 75D3 I376 29B7 76C3 I283 29B7 76C3 6C3 29C5 16B6 29C7 TP) I279 I278 I270 6C5 43D2 79D3 I379 6C5 43D2 79D3 I273 29B7 76C3 I274 29B7 76B3 I275 29C7 I276 29A7 (NEED TO ADD GND TP) I272 55C2 56B2 I393 I392 I232 I233 I259 I258 C I260 I245 I262 I261 I256 I257 I255 I252 I253 I254 I250 I251 I313 I246 I247 I248 I249 I395 THERMAL FUNC_TEST MCPTHMSNS_D2_P TRUE MCPTHMSNS_D2_N TRUE LVDS FUNC_TEST PP3V3_LCDVDD_SW_F TRUE PP3V3_S0_LCD_F TRUE PPVOUT_S0_LCDBKLT TRUE LVDS_IG_DDC_CLK TRUE LVDS_IG_DDC_DATA TRUE LVDS_IG_A_DATA_N TRUE LVDS_IG_A_DATA_P TRUE LVDS_IG_A_DATA_N TRUE LVDS_IG_A_DATA_P TRUE LVDS_IG_A_DATA_N TRUE LVDS_IG_A_DATA_P TRUE LVDS_IG_A_CLK_F_N TRUE LVDS_IG_A_CLK_F_P TRUE LED_RETURN_1 TRUE LED_RETURN_2 TRUE LED_RETURN_3 TRUE LED_RETURN_4 TRUE LED_RETURN_5 TRUE LED_RETURN_6 TRUE TP_BKL_SYNC TRUE 46B5 80D3 I375 46B5 80D3 I374 I372 I370 I371 6C3 68C2 68C3 I369 6C3 68B2 71C1 I368 17B3 68C5 I361 17A3 68C5 I366 17B3 68C2 75B3 I365 17B3 68C2 75B3 I363 17B3 68C2 75B3 I364 17B3 68C2 75B3 I362 17B3 68C2 75B3 I360 17B3 68C2 75B3 I359 68C2 75B3 I357 68C2 75B3 I358 68B3 71B1 I377 68B3 71B1 I378 I265 I266 68C2 I354 I355 SATA ODD CONN (NEED PP5V_SW_ODD TRUE SMC_ODD_DETECT TRUE SATA_ODD_D2R_C_P TRUE SATA_ODD_D2R_C_N TRUE SATA_ODD_R2D_P TRUE SATA_ODD_R2D_N TRUE I349 TP) 6C3 I348 37D3 I350 37C7 40B8 I352 37C6 75A3 I351 37C6 75A3 I353 37C6 75A3 I327 6A7 37C6 75A3 (NEED TO ADD GND TP) I328 SATA HDD/IR/SIL I343 I342 I314 I315 I318 I317 I307 I309 I311 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE PP5V_S0_HDD_FLT SATA_HDD_R2D_P SATA_HDD_R2D_N SATA_HDD_D2R_C_P SATA_HDD_D2R_C_N SYS_LED_ANODE_R IR_RX_OUT PP5V_S3_IR_R (NEED TP) I341 6C3 37B6 I339 37A5 75A3 I340 37A5 75A3 I338 37B5 75A3 I336 37B5 75A3 I337 37A7 I333 37A7 39D4 I335 37A7 (NEED TO ADD GND TP) I334 I332 I330 I331 I322 I321 I320 A I305 I387 48C8 49C3 I386 48C8 49C3 I385 48C8 49C3 I383 48C8 49C3 I382 49C3 49C5 I381 48D8 49C3 I380 PPVCORE_S0_CPU PPVCORE_S0_MCP PP0V75_S0 PP1V05_S0 PP1V5_S0 PP1V8_S0 PP5V_S0 PP3V3_S0 PP1V5_S3 PP3V3_S3 PP5V_S3 PP1V1R1V05_S5 PP3V3_S5 PP3V42_G3H PPBUS_G3H PP3V3_ENET_PHY PP1V2R1V05_ENET PP3V3_G3_RTC PP5V_WLAN PP5V_SW_ODD PP5V_S0_HDD_FLT PP3V3_S5_AVREF_SMC PP18V5_S3 PP3V3_S3_LDO PP3V3_LCDVDD_SW_F PPVOUT_S0_LCDBKLT PP4V5_AUDIO_ANALOG SMC_PM_G2_EN PM_SLP_S4_L PM_SLP_S3_L D 7D7 7C7 7C7 7D7 7C6 7B6 6D7 7D5 7D5 7D3 6B5 7D3 7C3 7B3 7B3 6A7 6B5 7D1 7C1 7B5 7B5 20C8 21A5 24D4 6D5 29C5 6B7 37D3 6B7 37B6 40D4 41C6 6C5 49C1 49D3 6C5 49B4 49C3 6C7 68C2 6C7 68B2 71C1 52A5 52D2 52D7 C 40D5 60C5 66D8 20C3 40C5 41A2 66C8 20C3 32B7 35A5 40C5 66D5 70D8 48C6 49C3 (NEED TO ADD GND TP) 48C8 49C1 48C8 49C1 48C8 49C1 48C8 49C1 48C8 49C1 6D5 43D2 79D3 6D5 43D2 79D3 48C8 49C1 48D8 49C1 DC POWER CONN PP18V5_DCIN_FUSE TRUE ADAPTER_SENSE TRUE (NEED TP) 58D6 58D7 (NEED TO ADD GND TP) 68B3 71A1 I329 I319 48C8 49C3 KEYBOARD CONN 68B3 71B1 I347 I267 I388 I304 I346 I269 I389 6C3 49C1 49D3 68B3 71B1 I345 I268 I390 6C3 49B4 49C3 I312 I344 B I391 68B3 71B1 (NEED TO ADD GND TP) I264 IPD_FLEX_CONN PP3V3_S3_LDO TRUE PP18V5_S3 TRUE Z2_CS_L TRUE Z2_DEBUG3 TRUE Z2_MOSI TRUE Z2_MISO TRUE Z2_SCLK TRUE Z2_BOOST_EN TRUE Z2_HOST_INTN TRUE Z2_CLKIN TRUE Z2_KEY_ACT_L TRUE Z2_RESET TRUE PSOC_MISO TRUE PSOC_MOSI TRUE PSOC_SCLK TRUE SMBUS_SMC_A_S3_SDA TRUE SMBUS_SMC_A_S3_SCL TRUE PSOC_F_CS_L TRUE PICKB_L TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE BATT POWER CONN SMBUS_SMC_BSA_SCL TRUE SMBUS_SMC_BSA_SDA TRUE SYS_DETECT_L TRUE BATT_POS_F TRUE 6A7 43C5 79D3 43C5 79D3 I356 58A8 (NEED TP) 58A7 58B8 59A3 I394 (NEED TO ADD GND TP) TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE PP3V3_S3 PP3V42_G3H WS_KBD1 WS_KBD2 WS_KBD3 WS_KBD4 WS_KBD5 WS_KBD6 WS_KBD7 WS_KBD8 WS_KBD9 WS_KBD10 WS_KBD11 WS_KBD12 WS_KBD13 WS_KBD14 WS_KBD15_CAP WS_KBD16_NUM WS_KBD17 WS_KBD18 WS_KBD19 WS_KBD20 WS_KBD21 WS_KBD22 WS_KBD23 WS_KBD_ONOFF_L WS_LEFT_SHIFT_KBD WS_LEFT_OPTION_KBD WS_CONTROL_KBD 6D3 7D3 6A7 6D3 7D1 48C6 48D2 48C6 48D2 48C6 48D2 48C6 48D2 48C6 48D2 48C6 48D2 48C6 48D2 B 48C6 48D2 48C6 48D2 48C6 48D2 48C6 48D2 48C6 48D2 48C6 48D2 48C2 48C6 48C2 48C2 48C2 48D6 48C2 48D7 48C2 48D7 48C2 48D7 48C2 48D7 48C2 48D7 48C2 48D7 48C2 48B3 48B5 48C2 48B3 48B5 48C2 48B3 48B5 48C2 (NEED TO ADD GND TP) KBD BACKLIGHT CONN (NEED KBDLED_ANODE TRUE TRUE SMC_KDBLED_PRESENT_L TP) 49A4 49A4 49A6 A SYNC_MASTER=M97_MLB (NEED TO ADD GND TP) PAGE TITLE FUNC TEST I326 I323 I324 I325 I308 BATT SIGNAL CONN (NEED PP3V42_G3H TRUE SMBUS_SMC_BSA_SCL TRUE SMBUS_SMC_BSA_SCL TRUE SMC_BIL_BUTTON_L TRUE SMC_LID_R TRUE DRAWING NUMBER TP) Apple Inc 6B5 6D3 7D1 NOTICE OF PROPRIETARY PROPERTY: 6A7 43C5 79D3 40C5 58C4 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED 58C2 (NEED TO ADD GND TP) D REVISION C.0.0 R 6A7 43C5 79D3 SIZE 051-7898 BRANCH PAGE OF 109 SHEET OF 8 "S0,S0M" RAILS =PPVCORE_S0_CPU_REG (CPU VCORE PWR) PPVCORE_S0_CPU 67B6 =PP5V_S0_FET =PPVCORE_S0_CPU =PPVCORE_S0_CPU_VSENSE 10B5 10D6 11D6 44D8 D 64C2 =PPCPUVTT_S0_REG PP1V05_S0 6D3 =PP1V05_S0_CPU =PP1V05_S0_MCP_FSB =PP1V05_S0_SMC_LS =PP1V05_S0_MCP_PEX_DVDD =PP1V05_S0_MCP_AVDD_UF =PP1V05_S0_MCP_SATA_DVDD =PP1V05_S0_MCP_HDMI_VDD =PP1V05_S0_VMON =PP1V05_S0_MCP_PLL_UF_R =PP1V05_FW_P1V05FWFET =PP1V05_FWPWRCTL =PPMCPCORE_S0_REG (MCP VCORE AFTER SENSE RES) 9D5 10C6 11B6 12D6 13A2 13B7 21D3 22C8 =PP5V_S0_HDD =PP5V_S0_LPCPLUS =PP5V_S0_FAN_RT 42D5 =PP5V_S0_CPU_IMVP 62D8 7A8 22D6 67C6 =PP3V3_S0_FET 47C5 66A8 65B3 35B4 PPVCORE_S0_MCP 6D3 MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V MAKE_BASE=TRUE 21D5 22D8 67D6 PP3V3_S0 =PPVTT_S0_VTTCLAMP =PP0V75_S0_MEM_VTT_A =PP0V75_S0_MEM_VTT_B 67D1 =PP1V5_S0_FET 67B3 26A4 27A4 PP1V5_S0 6D3 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.5V MAKE_BASE=TRUE =PP1V5_S0_CPU =PP1V5_S0_VMON =PP1V8R1V5_S0_MCP_MEM =PP1V5_S0_MEM_MCP =PP1V5_S0_MCP_PLL_VLDO 10B6 11B6 66A8 15C3 15C7 22C8 27B3 65B6 =PP3V3_S5_SMC =PP3V3_S5_LPCPLUS =PP3V42_G3H_RTC_D =PP3V42_G3H_BMON_ISNS 6B5 6D3 =PP3V3_S3_SMBUS_SMC_A_S3 =PP3V3_S3_PDCISENS =PP3V3_S3_SMBUS_SMC_MGMT =PP3V3_S3_VREFMRGN =PP3V3_S3_WLAN =PP3V3_S3_MCP_GPIO =PP3V3_S3_TPAD =PP3V3_S3_SMS =PP3V3_S3_CARDREADER 6D3 12D6 20C2 21B3 22B8 43D3 41C8 43C5 66B3 66C8 66D8 59A8 59C6 59D5 D 38B8 48B5 48C2 48C3 48C5 58C2 58C4 40D4 41C1 41C3 41C7 41D8 42C7 42C8 42D5 24D8 45B8 61B3 =PP3V42_G3H_ONEWIRE =PP3V42_G3H_AUDIO 43B5 25D8 58D2 56B6 29A6 20A3 58D1 58C8 48A6 48B5 48C5 48D2 =PP18V5_DCIN_CONN PP18V5_G3H MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.3 MM VOLTAGE=18.5V MAKE_BASE=TRUE 50B7 30D7 =PP18V5_G3H_CHGR 59D8 PPBUS_G3H 6C3 23D4 23C7 37C7 37D6 60B8 =PP5V_S3_REG PP5V_S3 6D3 59C1 =PPBUS_G3H MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5V MAKE_BASE=TRUE 43D5 43C3 43D8 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.3 MM VOLTAGE=12.6V MAKE_BASE=TRUE =PP5V_S3_EXTUSB =PP5V_S3_IR =PP5V_S3_BTCAMERA =PP5V_S3_VTTCLAMP =PP5V_S3_MCPDDRFET =PP5V_S3_SYSLED =PP5V_S3_TPAD =PP5V_S3_WLAN =PP5V_S3_1V5S30V75S0 =PP5V_S3_AUDIO =PP5V_S3_AUDIO_AMP =PP5V_S3_P5VS0FET =PP5V_S3_ODD 47C5 52A8 52D2 56D8 57B8 57D3 62D8 68C5 17C1 18D1 20A4 22B6 =PP3V3R1V5_S0_MCP_HDA =PP3V3_S0_SMC =PP3V3_S0_MCPTHMSNS =PP3V3_S0_CPUTHMSNS =PP3V3_S0_DPCONN =PPSPD_S0_MEM_A =PPSPD_S0_MEM_B =PP3V3_S0_PWRCTL =PP3V3_S0_VMON =PP3V3_S0_CPUVTTISNS =PP3V3_S0_TPAD =PP3V3_S0_SMBUS_MCP_1 =PP3V3_S0_P1V8S0 =PP3V3_S0_BKL_VDDIO =PP3V3_S0_MCPDDRISNS =PP3V3_S0_MCP_PLL_VLDO =PP3V3_S0_P3V3FWFET =PP3V3_S0_FWPWRCTL MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0.75V MAKE_BASE=TRUE 27D7 28C6 37B8 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V MAKE_BASE=TRUE 63D4 66B5 =PP3V3_S0_MCP_PLL_UF 6D3 26D7 PP3V3_S3 71D4 =PP3V3_S0_LCD =PP3V3_S0_MCP_GPIO C PP0V75_S0 =PP3V3_S3_FET 6A7 6B5 6D3 =PPVIN_S5_SMCVREF =PP3V42_G3H_SMBUS_SMC_BSA =PP3V42_G3H_PWRCTL =PP3V42_G3H_CHGR =PP3V42_G3H_SMCUSBMUX =PP3V42_G3H_TPAD =PP3V42_G3H_BATT 67D3 69B6 64C8 =PP3V3_S0_IMVP 44D8 PP3V42_G3H 49A5 =PP3V3_S0_XDP =PP3V3_S0_MCP =PP3V3_S0_MCP_DAC_UF =PP3V3_S0_MCP_VPLL_UF =PP3V3_S0_ODD =PP3V3_S0_SMBUS_SMC_0_S0 =PP3V3_S0_SMBUS_SMC_B_S0 =PP3V3_S0_SMBUS_MCP_0 =PP3V3_S0_FAN_RT =PP3V3_S0_AUDIO 35C6 =PP3V42_G3H_REG 58B4 MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.42V MAKE_BASE=TRUE =PP1V5_S3_HDD MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V MAKE_BASE=TRUE 17A6 23D7 6D3 =PP1V5_S3_P1V5S0FET =PP1V5_S3_MEM_A =PP1V5_S3_MEM_B =PP1V5_S3_MEMRESET 37B3 22D4 =PPVCORE_S0_MCP_VSENSE =PP0V75_S0_REG PP1V5_S3 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.5V MAKE_BASE=TRUE 7A8 22D8 =PPVCORE_S0_MCP 61C8 =PP1V5_S3_REG 6D3 6D7 =PP5V_S0_KBDLED =PP5V_S0_DP_AUX_MUX =PP5V_S0_CPUVTTS0 =PP5V_S0_BKL =PP5V_S0_MCPREG =PP5V_S0_VMON MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V MAKE_BASE=TRUE 63C7 63C1 63B8 PP5V_S0 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5V MAKE_BASE=TRUE 6D3 MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.3 MM VOLTAGE=1.25V MAKE_BASE=TRUE "G3H" RAILS "S3" RAILS 61C1 62D1 20D3 20D8 22A8 41A1 41D3 46B6 46D6 70B8 70C8 26A8 =PPBUS_S0_LCDBKLT =PPVIN_S0_MCPCORE =PPVIN_S5_1V5S30V75S0 =PPVIN_S5_3V3S5 =PPVIN_S3_5VS3 =PPBUS_G3HRS5 =PPBUS_S5_FWPWRSW =PPCPUVCORE_VTT_ISNS_R 38C7 37A8 39D7 29C3 67A3 67D4 41B8 49B6 49D7 29C1 72D8 63D5 61C2 60C3 60C6 60C7 C 44B8 35B7 45B8 (BEFORE HIGH SIDE SENSING RES.) 61C5 52A8 52D2 54D5 56B6 55B7 55C7 55D7 67B8 37D5 27A8 66A5 66A8 61D8 25D3 =PPVTT_S3_DDR_BUF PPVTT_S3_DDR_BUF 45B7 MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=0.75V MAKE_BASE=TRUE 45C7 49A6 =PPCPUVCORE_VTT_ISNS PPBUS_G3H_CPU_ISNS MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.3 MM VOLTAGE=12.6V MAKE_BASE=TRUE (AFTER HIGH SIDE CPU VCORE & CPU VTT SENSING RES.) =PPVIN_S0_CPUVTTS0 =PPVIN_S5_CPU_IMVP 43C8 65D8 64C6 62C3 62D4 62D8 71C7 45D8 65C6 35D6 35B1 35D2 "FIREWIRE" RAILS 65C5 =PP1V8_S0_REG PP1V8_S0 6D3 MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.8V MAKE_BASE=TRUE "S5" RAILS =PP3V3R1V8_S0_MCP_IFP_VDD =PP1V8_S0_AUDIO B =PP1V05_S0_MCP_PLL_UF =PP3V3_FW_FET PP3V3_FW MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V MAKE_BASE=TRUE "ENET" RAILS 52D7 32D2 65B1 22C4 35D4 17B6 23D7 =PP3V3_ENET_FET 65A5 PP3V3_ENET_PHY =PP1V05_S5_REG 6C3 MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V MAKE_BASE=TRUE PP1V05_S0_MCP_PLL_UF MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V MAKE_BASE=TRUE =PP3V3_ENET_MCP_RMGT =PP3V3_ENET_PHY PP1V1R1V05_S5 =PP1V05_S5_MCP_VDD_AUXC =PP1V05_ENET_P1V05ENETFET 36D5 36B6 35D8 34B1 34D2 35C7 =PP3V3_FW_FWPHY =PP3V3_S0_P1V05FWFET 6D3 MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V MAKE_BASE=TRUE B 21A3 22D8 32C4 35B1 PPVP_FW =PPBUS_S5_FW_FET 17D3 17D7 22A5 22B6 MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=12.6V MAKE_BASE=TRUE 31D7 =PPVP_FW_PORT1 =PPVP_FW_PHY_CPS_FET 36C3 36C6 32B2 =PP1V05_ENET_FET PP1V2R1V05_ENET 6C3 MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V MAKE_BASE=TRUE 60B1 =PP1V05_ENET_MCP_PLL_MAC =PP1V05_ENET_MCP_RMGT =PP1V05_ENET_PHY =PP3V3_S5_REG 22A8 22D1 PP1V05_S0_MCP_PEX_AVDD 17D3 22D6 31D2 16B3 206 mA (A01) 16A3 MAKE_BASE=TRUE 206 mA (A01) A 22D8 7D7 =PP1V05_S0_MCP_PEX_DVDD0 =PP1V05_S0_MCP_PEX_DVDD1 =PP1V05_S0_MCP_PEX_DVDD 16B6 57 mA (A01) 16A6 206 mA (A01) 22D2 PP1V05_S0_MCP_SATA_AVDD =PP1V05_S0_MCP_SATA_AVDD0 =PP1V05_S0_MCP_SATA_AVDD1 MAKE_BASE=TRUE 6D3 35C5 =PP3V3_S5_MCP_GPIO =PP3V3_S5_ROM =PP3V3_S5_LCD =PP3V3_S5_MCP =PP3V3_S5_MCPPWRGD =PP3V3_S5_PWRCTL =PP3V3_S5_P1V05ENETFET =PP3V3_S5_P3V3S3FET =PP3V3_S5_P3V3S0FET =PP3V3_S5_P1V05S5 =PP3V3_S5_MEMRESET =PP3V3_S5_P3V3ENETFET =PP3V3_S5_DP_PORT_PWR =PP3V3_FW_LATEVG =PP3V3_FW_LATEVG_ACTIVE =PP3V3_S5_P1V05FWFET PEX & SATA AVDD/DVDD aliases =PP1V05_S0_MCP_PEX_AVDD0 =PP1V05_S0_MCP_PEX_AVDD1 PP3V3_S5 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V MAKE_BASE=TRUE 19B6 127 mA (A01) =PP1V0_FW_FET PP1V05_FW MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V MAKE_BASE=TRUE 17C7 19C1 42B5 42C7 51C6 =PP1V0_FW_FWPHY 34D8 35D3 68C8 21B3 22B8 24B8 66B3 32C5 67D8 67C8 65B8 28C4 32D5 70D8 36A7 35A8 SYNC_MASTER=BEN SYNC_DATE=04/21/2008 Power Aliases 19B6 127 mA (A01) DRAWING NUMBER 22D6 7D7 =PP1V05_S0_MCP_SATA_DVDD =PP1V05_S0_MCP_SATA_DVDD0 =PP1V05_S0_MCP_SATA_DVDD1 127 mA (A01) A PAGE TITLE 35C7 19B6 Apple Inc 43 mA (A01) 19B6 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED D REVISION C.0.0 R NOTICE OF PROPRIETARY PROPERTY: SIZE 051-7898 BRANCH PAGE OF 109 SHEET OF 8 PCI-E ALIASES HEATSINK STANDOFFS Z0902 16D6 16C6 Z0901 STDOFF-4.5OD.98H-1.1-3.48-TH STDOFF-4.5OD.98H-1.1-3.48-TH =PEG_D2R_P NC_PEG_D2R_P 16D3 16C3 =PEG_R2D_C_N NC_PEG_R2D_C_N NO_TEST=TRUE 16D3 16C3 D ABOVE CPU 16C6 16C3 Z0904 Z0903 NC_PEG_R2D_C_P PEG_PRSNT_L TP_PEG_PRSNT_L PEG_CLK100M_P 16C3 17C6 17C6 MCP_TV_DAC_VREF MCP_CLK27M_XTALIN NC_MCP_TV_DAC_VREF 17C6 MCP_CLK27M_XTALOUT NC_MCP_CLK27M_XTALOUT MAKE_BASE=TRUE 17C3 CRT_IG_R_C_PR NC_CRT_IG_R_C_PR NO_TEST=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE 17C3 CRT_IG_B_COMP_PB NC_CRT_IG_B_COMP_PB 17C3 CRT_IG_HSYNC NC_CRT_IG_HSYNC NO_TEST=TRUE 16B6 PCIE_EXCARD_D2R_P TP_PCIE_EXCARD_D2R_P 16B6 PCIE_EXCARD_D2R_N TP_PCIE_EXCARD_D2R_N 17C3 ETHERNET ALIASES MAKE_BASE=TRUE NC_CRT_IG_G_Y_Y NO_TEST=TRUE TP_PEG_CLK100M_N MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE NO_TEST=TRUE CRT_IG_G_Y_Y TP_MEM_A_A15 TP_MEM_B_A15 MAKE_BASE=TRUE MAKE_BASE=TRUE UNUSED EXPRESS CARD LANE BELOW CPU 27D5 NC_MCP_CLK27M_XTALIN NO_TEST=TRUE 17C3 MEM_A_A MEM_B_A 26D5 MAKE_BASE=TRUE CRT_IG_VSYNC 32B5 MAKE_BASE=TRUE NC_CRT_IG_VSYNC NO_TEST=TRUE MAKE_BASE=TRUE =P3V3ENET_EN =P1V05ENET_EN =PP3V3_ENET_PHY_VDDREG =RTL8211_REGOUT =RTL8211_ENSWREG 32C5 MAKE_BASE=TRUE NO_TEST=TRUE BELOW MCP UNUSED ADDRESS PINS MAKE_BASE=TRUE NO_TEST=TRUE 17C6 SO-DIMM ALIASES UNUSED CRT & TV-OUT INTERFACE MCP_TV_DAC_RSET NC_MCP_TV_DAC_RSET NO_TEST=TRUE TP_PEG_CLK100M_P PEG_CLK100M_N 1 MAKE_BASE=TRUE MAKE_BASE=TRUE STDOFF-4.5OD.98H-1.1-3.48-TH STDOFF-4.5OD.98H-1.1-3.48-TH MAKE_BASE=TRUE =PEG_R2D_C_P NO_TEST=TRUE LEFT OF CPU MAKE_BASE=TRUE 16D6 16C6 NO_TEST=TRUE DACS ALIASES UNUSED GPU LANES =PEG_D2R_N NC_PEG_D2R_N NO_TEST=TRUE 31C2 31C2 MAKE_BASE=TRUE 31C6 PM_SLP_RMGT_L D 20C3 MAKE_BASE=TRUE TP_PP3V3_ENET_PHY_VDDREG MAKE_BASE=TRUE NC_RTL8211_REGOUT MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE 16B3 PCIE_EXCARD_R2D_C_P TP_PCIE_EXCARD_R2D_C_P 16B3 PCIE_EXCARD_R2D_C_N TP_PCIE_EXCARD_R2D_C_N 16C6 PCIE_EXCARD_PRSNT_L TP_PCIE_EXCARD_PRSNT_L LVDS ALIASES MAKE_BASE=TRUE MAKE_BASE=TRUE FAN STANDOFF 17B3 NO_TEST=TRUE MAKE_BASE=TRUE 16C6 Z0905 EXCARD_CLKREQ_L TP_EXCARD_CLKREQ_L 17B3 16C3 PCIE_CLK100M_EXCARD_P TP_PCIE_CLK100M_EXCARD_P 16C3 PCIE_CLK100M_EXCARD_N TP_PCIE_CLK100M_EXCARD_N MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM VOLTAGE=0V LVDS_IG_A_DATA_N 5% 1/16W MF-LF 402 MAKE_BASE=TRUE 17B3 LVDS_IG_B_CLK_P NC_LVDS_IG_B_CLK_P LVDS_IG_B_CLK_N NC_LVDS_IG_B_CLK_N NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE R0931 22 NC_LVDS_IG_A_DATA_N3 17B3 MAKE_BASE=TRUE TP_RTL8211_CLK125 MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE STDOFF-4.5OD.98H-1.1-3.48-TH 31B6 UNUSED LVDS SIGNALS NC_LVDS_IG_A_DATA_P3 LVDS_IG_A_DATA_P MAKE_BASE=TRUE 17B3 LVDS_IG_B_DATA_P NC_LVDS_IG_B_DATA_P 17B3 LVDS_IG_B_DATA_N NC_LVDS_IG_B_DATA_N NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE FW ALIASES MAKE_BASE=TRUE 18B7 FW_PME_L FW_PLUG_DET_L =FW_PME_L FW643_WAKE_L 35B1 35D7 MAKE_BASE=TRUE MLB MOUNTING (TO C BRACKET) SCREW HOLES OMIT 3R2P5 Z0907 NOSTUFF R0950 OMIT 3R2P5 Z0906 MISC MCP79 ALIASES FIREWIRE PRESENT SIGNALS 35D3 16C6 PCIE_FW_PRSNT_L TP_CPU_PECI_MCP 16B6 GMUX_JTAG_TCK_L GMUX_JTAG_TDO 18D4 GMUX_JTAG_TDI TP_GMUX_JTAG_TCK_L MAKE_BASE=TRUE TP_GMUX_JTAG_TDO MAKE_BASE=TRUE TP_GMUX_JTAG_TDI 18D4 GMUX_JTAG_TMS TP_GMUX_JTAG_TMS MAKE_BASE=TRUE 5% 1/16W MF-LF 402 MAKE_BASE=TRUE CPU_PECI_MCP 13B6 35C8 34B2 16B6 C C MAKE_BASE=TRUE MAKE_BASE=TRUE USB ALIASES MLB MOUNTING (TO TOPCASE) SCREW HOLES OMIT Z0908 3R2P5 OMIT Z0909 3R2P5 19C3 19C3 OMIT Z0910 3R2P5 19D3 19D3 19C3 19C3 OMIT Z0911 3R2P5 OMIT Z0912 3R2P5 USB_EXTC_P USB_EXTC_N USB_EXTD_P USB_EXTD_N USB_EXCARD_P USB_EXCARD_N 19D3 USB_MINI_P 19D3 USB_MINI_N UNUSED USB PORTS TP_USB_EXTC_P TP_USB_EXTC_N TP_USB_EXTD_P TP_USB_EXTD_N TP_USB_EXCARD_P TP_USB_EXCARD_N TP_USB_MINI_P MAKE_BASE=TRUE TP_USB_MINI_N LAN ALIASES MAKE_BASE=TRUE MAKE_BASE=TRUE 17D6 MAKE_BASE=TRUE 17D6 MAKE_BASE=TRUE 17D6 =MCP_MII_RXER =MCP_MII_COL =MCP_MII_CRS MCP_MII_PD MAKE_BASE=TRUE R0930 47K MAKE_BASE=TRUE DP HOTPLUG PULL-DOWN 17B6 =DVI_HPD_GMUX_INT FSB MHZ BSEL 402 MAKE_BASE=TRUE CPU FSB FREQUENCY STRAPS 5% 1/16W MF-LF MAKE_BASE=TRUE 73C3 9B4 IN CPU_BSEL MAKE_BASE=TRUE =MCP_BSEL OUT 13A7 HPLUG_DET2 MAKE_BASE=TRUE 0 0 1 1 0 1 0 1 1 1 266 133 200 (166) 333 100 (400) (RSVD) R0940 20K 5% 1/16W MF-LF 402 B EMI IO POGO PINS ZS0900 1.4DIA-SHORT-EMI-MLB-M97-M98 SM OMIT ZS0901 SM OMIT 1.4DIA-SHORT-EMI-MLB-M97-M98 ZS0902 SM OMIT 1.4DIA-SHORT-EMI-MLB-M97-M98 PART NUMBER 870-1801 QTY ZS0903 ZS0908 1.4DIA-SHORT-EMI-MLB-M97-M98 1.4DIA-SHORT-EMI-MLB-M97-M98 SM DESCRIPTION REFERENCE DES POGO PIN,SHORT,EMI,MLB,K19/K24 CRITICAL ZS0900,ZS0901,ZS0902,ZS0903,ZS0908,ZS0909 OMIT SM OMIT B ZS0909 SM OMIT 1.4DIA-SHORT-EMI-MLB-M97-M98 BOM OPTION CRITICAL EMI POGO PINS ZS0904 ZS0905 ZS0906 2.0DIA-TALL-EMI-MLB-M97-M98 2.0DIA-TALL-EMI-MLB-M97-M98 2.0DIA-TALL-EMI-MLB-M97-M98 SM SM SM 1 ZS0907 2.0DIA-TALL-EMI-MLB-M97-M98 SM A A SYNC_MASTER=M97_MLB PAGE TITLE SIGNAL ALIAS DRAWING NUMBER Apple Inc THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED D REVISION C.0.0 R NOTICE OF PROPRIETARY PROPERTY: SIZE 051-7898 BRANCH PAGE OF 109 SHEET OF 8 OMIT BI 73D3 13C6 BI 73D3 13C6 BI 73D3 13C6 BI 73D3 13C6 BI 73D3 13C6 BI 73D3 13C6 BI 73D3 13C6 BI 73D3 13B6 BI 73D3 13B6 BI 73D3 13B6 BI 73D3 13B6 BI 73D3 13B6 BI 73C3 13C6 BI 73C3 13C6 BI 73C3 13C6 BI 73C3 13C6 BI 73C3 13C6 BI 73C3 13C6 BI 73C3 13C6 BI 73C3 13C6 BI 73C3 13C6 BI 73C3 13C6 BI 73C3 13C6 BI 73C3 13C6 C BI 73D3 13B6 BI 73C3 13C6 BI 73C3 13C6 BI 73C3 13C6 BI 73C3 13C6 BI 73C3 13C6 BI 73C3 13C6 BI 73C3 13C6 BI 73C3 13B6 BI 73C3 13A3 73C3 13B7 73C3 13A3 K3 FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_ADSTB_L Y2 CPU_A20M_L OUT CPU_FERR_L CPU_IGNNE_L IN IN 73B3 13A3 IN 73C3 13A3 IN 73C3 13A3 IN 73B3 13A3 FSB_REQ_L FSB_REQ_L FSB_REQ_L FSB_REQ_L FSB_REQ_L IN CPU_STPCLK_L CPU_INTR CPU_NMI CPU_SMI_L TP_CPU_RSVD_M4 TP_CPU_RSVD_N5 TP_CPU_RSVD_T2 TP_CPU_RSVD_V3 TP_CPU_RSVD_B2 TP_CPU_RSVD_F6 TP_CPU_RSVD_D2 TP_CPU_RSVD_D22 TP_CPU_RSVD_D3 N2 J1 N3 P5 P2 L2 P4 P1 R1 M1 H2 K2 J3 L1 U5 R3 W6 U4 Y5 U1 R4 T5 T3 W2 W5 Y4 U2 V4 W3 AA4 AB2 AA3 V1 A6 A5 C4 D5 C6 B4 A3 M4 N5 T2 V3 B2 F6 D2 D22 D3 REQ0* REQ1* REQ2* REQ3* REQ4* A17* A18* A19* A20* A21* A22* A23* A24* A25* A26* A27* A28* A29* A30* A31* A32* A33* A34* A35* ADSTB1* E1 FSB_DEFER_L FSB_DRDY_L FSB_DBSY_L BR0* F1 FSB_BREQ0_L IERR* INIT* B3 CPU_INIT_L IN LOCK* H4 FSB_LOCK_L BI RESET* RS0* RS1* RS2* TRDY* C1 FSB_CPURST_L FSB_RS_L FSB_RS_L FSB_RS_L FSB_TRDY_L HIT* HITM* G6 BPM0* BPM1* BPM2* BPM3* PRDY* PREQ* TCK TDI TDO TMS TRST* DBR* G5 F21 D20 F3 F4 G3 G2 E4 AD4 AD3 AD1 AC4 AC2 AC1 AC5 AA6 AB3 AB5 AB6 C20 BI 13B6 73C3 BI 13B6 73C3 BI 13B3 73C3 BI 13B3 73C3 BI 13B6 73C3 BI 13B6 73C3 BI 13B6 73C3 =PP1V05_S0_CPU 7D7 10C6 11B6 12D6 R10001 54.9 1% 1/16W MF-LF 402 D 73B3 CPU_IERR_L FSB_HIT_L FSB_HITM_L XDP_BPM_L XDP_BPM_L XDP_BPM_L XDP_BPM_L XDP_BPM_L XDP_BPM_L XDP_TCK XDP_TDI XDP_TDO XDP_TMS XDP_TRST_L XDP_DBRESET_L 13A3 73C3 13B6 73C3 IN 12C2 13A3 73C3 IN 13A6 73C3 IN 13A6 73C3 IN 13A6 73C3 IN 13B6 73C3 BI 13B6 73C3 BI 13B6 73C3 BI 12C6 73A3 BI 12C6 73A3 BI 12C6 73A3 BI 12C6 73A3 BI OMIT R1001 1% 1/16W MF-LF 402 12C6 73A3 12C6 73A3 BI THERMTRIP* RSVD0 RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 RSVD6 RSVD7 RSVD8 73D3 13D3 BI 73D3 13D3 BI BI IN BI 9B6 12B3 73A3 73D3 13D3 BI IN 9B6 12B3 73A3 73D3 13D3 IN 9A6 12B3 73A3 73D3 13D3 BI 73D3 13D3 BI 12B3 24A3 R1002 46D5 80D3 B25 OUT 46D5 80D3 C7 PM_THRMTRIP_L OUT 13B7 41C4 73B3 A21 BI OUT OUT 73D3 13D3 OUT FSB_CLK_CPU_P FSB_CLK_CPU_N BI 73D3 13D3 73D3 13D3 OUT A22 IN IN 13B6 41D4 62C8 73C3 13B3 73B3 13B3 73B3 R1005 1K CPU JTAG Support B R1090 XDP_TMS 73A3 12B3 9C6 XDP_TDI 54.9 1 54.9 1% 1/16W MF-LF 402 BI 73D3 13D3 BI 73D3 13D6 BI 73D3 13D6 BI 73D3 13D6 BI 73D3 13D3 BI 73D3 13D3 BI 73D3 13D3 BI 73D3 13D3 BI 73D3 13D3 BI 73D3 13C3 BI 73D3 13C3 BI 73D3 13C3 BI 73D3 13C3 BI 73D3 13C3 BI 73D3 13C3 BI XDP_TDO BI 73D3 13C3 BI 73D3 13C3 BI 73D3 13C3 BI 73D3 13D6 BI 73D3 13D6 BI 73D3 13D6 BI R1006 2.0K R1092 54.9 1% 1/16W MF-LF 402 NO STUFF C1014 PLACEMENT_NOTE=Place R1092 near ITP connector (if present) 10% 16V X5R 402 R1010 1 0.1uF NO STUFF 1% 1/16W MF-LF 402 2 73C3 8B2 73C3 8B2 73C3 8B2 NO STUFF R1093 73A3 12B6 9C6 R1094 73A3 12B3 9C6 XDP_TRST_L 649 1% 1/16W MF-LF 402 5% 1/16W MF-LF 402 R10111 NO STUFF 1K 54.9 XDP_TCK BI 73D3 13C3 1% 1/16W MF-LF 402 BI FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_DSTB_L_N FSB_DSTB_L_P FSB_DINV_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_DSTB_L_N FSB_DSTB_L_P FSB_DINV_L 73B3 25B1 CPU_GTLREF R1091 73A3 12B3 9C6 1% 1/16W MF-LF 402 BI 73D3 13D3 73D3 13C3 73A3 12B3 9C6 BI 73D3 13D3 9B6 12B3 73A3 H CLK BCLK0 BCLK1 BI 73D3 13D3 CPU_PROCHOT_L CPU_THERMD_P CPU_THERMD_N A24 73D3 13D3 9A6 12B6 73A3 5% 1/16W MF-LF 402 D21 BI IN THERMAL PROCHOT* THERMDA THERMDC 73D3 13D3 73D3 13D3 54.9 68 A20M* FERR* IGNNE* STPCLK* LINT0 LINT1 SMI* DEFER* DRDY* DBSY* H5 E2 5% 1/16W MF-LF 402 F24 E26 G22 F23 G25 E25 E23 K24 G24 J24 J23 H22 F26 K22 H23 J26 H26 H25 N22 K25 P26 R23 L23 M24 L22 M23 P25 P23 P22 T24 R24 L25 T25 N25 L26 M26 N24 AD26 C23 D25 C24 AF26 AF1 A26 C3 B22 B23 C21 D0* D1* D2* D3* D4* D5* D6* D7* D8* D9* D10* D11* D12* D13* D14* D15* DSTBN0* DSTBP0* DINV0* D16* D17* D18* D19* D20* D21* D22* D23* D24* D25* D26* D27* D28* D29* D30* D31* DSTBN1* DSTBP1* DINV1* GTLREF TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 TEST7 BSEL0 BSEL1 BSEL2 U1000 PENRYN FCBGA OF D32* D33* D34* D35* D36* D37* D38* D39* D40* D41* D42* D43* D44* D45* D46* D47* DSTBN2* DSTBP2* DINV2* D48* D49* D50* D51* D52* D53* D54* D55* D56* D57* D58* D59* D60* D61* D62* D63* DSTBN3* DSTBP3* DINV3* COMP0 COMP1 COMP2 COMP3 MISC DPRSTP* DPSLP* DPWR* PWRGOOD SLP* PSI* Y22 AB24 V24 V26 V23 T22 U25 U23 Y25 W22 Y23 W24 W25 AA23 AA24 AB25 Y26 AA26 U22 AE24 AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21 AC22 AD23 AF22 AC23 AE25 AF24 AC20 FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_DSTB_L_N FSB_DSTB_L_P FSB_DINV_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_DSTB_L_N FSB_DSTB_L_P FSB_DINV_L BI 13C3 73D3 BI 13C3 73D3 BI 13C3 73D3 BI 13C3 73D3 BI 13C3 73D3 BI 13C3 73D3 BI 13C3 73D3 BI 13C3 73D3 BI 13C3 73D3 BI 13C3 73D3 BI 13C3 73D3 BI 13C3 73D3 BI 13C3 73D3 BI 13C3 73D3 BI 13C3 73D3 BI 13B3 73D3 BI 13D6 73D3 BI 13D6 73D3 BI 13D6 73D3 BI 13B3 73D3 BI 13B3 73D3 BI 13B3 73D3 BI 13B3 73D3 BI 13B3 73D3 BI 13B3 73D3 BI 13B3 73D3 BI 13B3 73D3 BI 13B3 73D3 BI 13B3 73D3 BI 13B3 73D3 BI 13B3 73D3 BI 13B3 73D3 BI 13B3 73D3 BI 13B3 73D3 BI 13B3 73D3 BI 13D6 73D3 BI 13D6 73D3 BI 13D6 73D3 C B R26 73A3 CPU_COMP U26 73B3 CPU_COMP AA1 73B3 CPU_COMP Y1 E5 B5 D24 D6 D7 AE6 73B3 CPU_COMP CPU_DPRSTP_L CPU_DPSLP_L FSB_DPWR_L CPU_PWRGD FSB_CPUSLP_L CPU_PSI_L IN 13A3 62C7 73B3 IN 13A3 73B3 IN 13A3 73B3 IN 12C7 13A3 73C3 IN 13A3 73B3 OUT R1023 R1021 54.9 54.9 1% 1/16W MF-LF 402 62C7 1% 1/16W MF-LF 402 5% 1/16W MF-LF 402 R1022 27.4 R1012 1K CPU_TEST1 CPU_TEST2 TP_CPU_TEST3 CPU_TEST4 TP_CPU_TEST5 TP_CPU_TEST6 TP_CPU_TEST7 OUT CPU_BSEL OUT CPU_BSEL OUT CPU_BSEL E22 DATA GRP BI 73D3 13C6 H1 DATA GRP 73D3 13D6 OF FSB_ADS_L FSB_BNR_L FSB_BPRI_L ADS* BNR* BPRI* DATA GRP BI M3 FCBGA DATA GRP 73D3 13D6 K5 PENRYN CONTROL BI L4 U1000 XDP/ITP SIGNALS BI 73D3 13D6 L5 A3* A4* A5* A6* A7* A8* A9* A10* A11* A12* A13* A14* A15* A16* ADSTB0* ADDR GROUP0 BI 73D3 13D6 J4 ADDR GROUP1 73D3 13D6 FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_ADSTB_L ICH BI RESERVED D 73D3 13D6 PLACEMENT_NOTE=Place C1014 within 12.7mm of CPU PLACEMENT_NOTE=Place R1005 within 12.7mm of CPU PLACEMENT_NOTE=Place R1006 within 12.7mm of CPU 2 R1020 27.4 1% 1/16W MF-LF 402 1% 1/16W MF-LF 402 PLACEMENT_NOTE (all resistors): 1% 1/16W MF-LF 402 Place within 12.7mm of CPU A SYNC_MASTER=T18_MLB SYNC_DATE=12/12/2007 A PAGE TITLE CPU FSB DRAWING NUMBER SYNC FROM T18 CHANGE CPU FROM SOCKET TO BGA SYMBOL Apple Inc 051-7898 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED D REVISION C.0.0 R NOTICE OF PROPRIETARY PROPERTY: SIZE BRANCH PAGE 10 OF 109 SHEET OF 8 A4 P6 A8 (CPU CORE POWER) P21 OMIT A11 =PPVCORE_S0_CPU D A7 A10 A12 OMIT AB7 U1000 AC7 FCBGA A15 A A A A (SV (SV (SV (LV Design Target) HFM) LFM) Design Target) OF A14 U1000 A16 PENRYN P24 R2 R5 FCBGA A19 AC9 PENRYN A13 R22 OF A23 R25 AF2 T1 B6 T4 B8 T23 AC12 B11 T26 AC13 B13 U3 A17 AC15 B16 U6 A18 AC17 B19 U21 A20 AC18 B21 U24 B7 AD7 B24 V2 B9 AD9 C5 V5 B10 AD10 C8 V22 B12 AD12 C11 V25 B14 AD14 C14 W1 B15 AD15 C16 W4 B17 AD17 C19 W23 B18 AD18 C2 W26 B20 AE9 C22 Y3 C9 AE10 C25 Y6 C10 AE12 D1 Y21 C12 AE13 D4 Y24 C13 AE15 D8 AA2 C15 AE17 D11 AA5 C17 AE18 D13 AA8 C18 AE20 D16 AA11 AF9 D19 AA14 D10 AF10 D23 AA16 D12 AF12 D26 AA19 D14 AF14 E3 AA22 D15 AF15 VCC D9 E6 AA25 D17 AF17 E8 AB1 D18 AF18 E11 E7 AF20 VCC (CPU IO POWER 1.05V) E14 =PP1V05_S0_CPU E9 7D7 9D5 11B6 12D6 VSS E19 AB13 E21 AB16 E24 AB19 G21 V6 E13 J6 E15 K6 F5 AB23 E17 M6 F8 AB26 E18 J21 F11 AC3 E20 K21 F13 AC6 F7 M21 F16 AC8 N21 F19 AC11 F2 AC14 VCCP F10 N6 F12 R21 F22 AC16 F14 R6 F25 AC19 F15 T21 G4 AC21 F17 T6 G1 AC24 F18 V21 F20 W21 AA7 (CPU INTERNAL PLL POWER 1.5V) =PP1V5_S0_CPU (BR1#) 7B6 11B6 B26 AA9 AA10 VCCA C26 VID0 VID1 VID2 VID3 VID4 VID5 VID6 AD6 130 mA AA12 AA13 AA15 AA17 AA18 AA20 AB9 AC10 AF5 AE5 AF4 AE3 AF3 AE2 CPU_VID CPU_VID CPU_VID CPU_VID CPU_VID CPU_VID CPU_VID AF7 AD13 H24 AD16 AD19 J5 AD22 OUT 62C7 73A3 J22 AD25 OUT 62C7 73A3 J25 AE1 OUT 62C7 73A3 K1 AE4 K4 AE8 OUT 62C7 73A3 OUT 62C7 73A3 7D7 10D6 11D6 R1100 100 1% 1/16W MF-LF 402 CPU_VCCSENSE_P OUT 62A5 73A3 PLACEMENT_NOTE=Place R1100 within 25.4mm of CPU, no stubs PLACEMENT_NOTE=Place R1101 within 25.4mm of CPU, no stubs AE7 AD11 H21 62C7 73A3 AB17 VSSSENSE AD8 H6 62C7 73A3 AB15 AB18 AD5 H3 OUT AB12 VCCSENSE AD2 G26 OUT AB10 AB14 G23 J2 =PPVCORE_S0_CPU CPU_VCCSENSE_N OUT 62A5 73A3 K23 AE11 K26 AE14 L3 AE16 L6 AE19 L21 AE23 L24 AE26 M2 A2 M5 AF6 R1101 M22 AF8 100 M25 AF11 N1 AF13 N4 AF16 N23 AF19 N26 AF21 1% 1/16W MF-LF 402 P3 B1 C AB8 AB11 E12 4500 mA (before VCC stable) 2500 mA (after VCC stable) D AB4 VSS E16 E10 F9 B 44 41 30.4 23 AB20 A9 C 7D7 10B5 11D6 B A25 (Socket-P KEY) A AF25 SYNC_MASTER=T18_MLB SYNC_DATE=12/12/2007 A PAGE TITLE CPU Power & Ground SYNC FROM T18 CHANGE CPU FROM SOCKET TO BGA SYMBOL DRAWING NUMBER Apple Inc THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED SIZE D REVISION C.0.0 R NOTICE OF PROPRIETARY PROPERTY: BRANCH PAGE 11 OF 109 SHEET OF Current numbers from Merom for Santa Rosa EMTS, doc #20905 051-7898 1.5V S0 FET 3.3V S3 FET (1.5V S0 FET FOR DDR3 MEM, MCP79 AND CPU) CRITICAL Q7910 =PP1V5_S3_P1V5S0FET 7D3 FDC638P_G 3.3V S3 FET SM =PP3V3_S3_FET MOSFET FDC638P CHANNEL P-TYPE D Q7901 ROME 0.033UF 10K X5R 402 2 C7910 R7910 0.182 A (EDP) 7C3 P3V3S3_SS Q7903 SSM3K15FV D 10K 10% MF-LF 402 16V CERM R7903 Q7971 5% 1/16W MF-LF 402 SOD-VESM-HF 66B6 47K G S 1 Q7971 D C7903 10% 10V CERM 402 MOSFET Rome SenseFET CHANNEL N-TYPE MCPDDR_EN_L_RC SSM6N15FEAPE RDS(ON) SOT563 LOADING 3.3V S0 FET 66C1 IN G OUT 7C8 1.5V S0 FET 0.068UF 5% 1/16W MF-LF 402 =P3V3S3_EN IN P1V5_S0_SENSE S OUT P1V5_S0_KELVIN =PP1V5_S0_FET R7971 G SOT563 MCPDDR_EN_L D KELVIN S SSM6N15FEAPE 100K 402 G MCPDDR_SS 5% 1/16W MF-LF 402 5% 1/16W 20% 10V CERM 402 R7901 =PP5V_S3_MCPDDRFET 0.01UF 47K P3V3S3_EN_L LOADING NC 0.1UF 48 mOhm @4.5V RDS(ON) 10% 16V 5% 1/16W MF-LF 402 C7902 45D8 GND C7911 SENSE R7912 D DFN 45C8 D CRITICAL 7D4 =PP3V3_S5_P3V3S3FET 7A3 S 6.3 mOHM @4.5V VGS 5A (EDP) =MCPDDR_EN CRITICAL Q7930 C C FDC606P_G SOT-6 =PP3V3_S0_FET 3.3V S0 FET 7D6 X5R 402 MF-LF 402 D 26 MOHM @4.5V RDS(ON) 1.431 A (EDP) LOADING C7930 0.01UF 47K P3V3S0_SS Q7905 SSM3K15FV R7930 P3V3S0_EN_L P-TYPE G 10% 16V 5% 1/16W FDC606P CHANNEL 0.033UF 100K MOSFET C7931 R7932 S =PP3V3_S5_P3V3S0FET 7A3 5% 1/16W 10% MF-LF 402 16V CERM 402 D S SOD-VESM-HF MCP79 DDRVTT FET 66C1 G =P3V3S0_EN IN B MCP79 DDR PAD LEAKAGE IS HIGH ENOUGH THAT NVIDIA RECOMMENDS UNPOWERING DURING SLEEP IN ORDER TO SUPPORT UNPOWERING RAIL, HARDWARE MUST GUARANTEE MEM_CKE SIGNALS ARE LOW BEFORE RAIL IS TURNED OFF, AND REMAINS LOW UNTIL AFTER RAIL TURNS BACK ON OR DIMMS WILL EXIT SELF-REFRESH PREMATURELY MEM_VTT_EN OUTPUT FROM MCP79 USED TO ENABLE CLAMP ON VTT RAIL, WHICH PULLS ALL CKE SIGNALS LOW THROUGH VTT TERMINATION RESISTORS 5.0V S0 FET B CRITICAL Q7940 =PP5V_S3_P5VS0FET =PP5V_S0_FET 5.0V S0 FET 7D6 R7975 10% 16V X5R 5% 1/16W MF-LF D S =PPVTT_S0_VTTCLAMP LOADING 13.5 MOHM @4.5V 1/16W MF-LF Q7945 90mA max load @ 0.9V 81mW max power CKT FROM T18 R7976 D S SSM6N15FEAPE SOT563 100K 5% 1/16W MF-LF 402 10% 16V CERM 402 402 D VTTCLAMP_L Q7975 5% SSM3K15FV =PP5V_S3_VTTCLAMP 1.7 A (EDP) 0.01UF P5V0S0_SS 10 5% 1/10W MF-LF 603 7C3 47K RDS(ON) C7940 R7940 P5V0S0_EN_L P-TYPE 402 TPCP8102 CHANNEL G 0.033UF 47K 402 R7942 C7941 MOSFET 7C7 7C3 TPCP8102 376S0778 23V1K-SM G VTTCLAMP_EN SOD-VESM-HF Q7975 D 66C1 IN G S NO STUFF C7976 SSM6N15FEAPE 20% 50V CERM 402 =P5VS0_EN A 61C8 24C1 IN =DDRVTT_EN G 0.001UF SOT563 S SYNC_MASTER=YUAN.MA SYNC_DATE=12/11/2008 A PAGE TITLE POWER FETS DRAWING NUMBER Apple Inc 051-7898 SIZE D REVISION C.0.0 R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED BRANCH PAGE 79 OF 109 SHEET OF D D CHECK IF LVDS_IG_PANEL_PWR GLITCHES ON POWER UP 17B6 LCD CONNECTOR LVDS_IG_PANEL_PWR LVDS CONNECTOR:518S0650 R9014 1K CRITICAL J9000 5% 1/16W MF-LF 402 20474-030E-11 C9015 CRITICAL 0.001UF U9000 FPF1009 ON 7A3 =PP3V3_S5_LCD VIN_2 C GND C9009 0.1UF 10% 50V X7R 402 L9004 MFET-2X2 VIN_1 C9010 FERR-120-OHM-1.5A VOUT_1 PP3V3_LCDVDD_SW VOUT_2 VOLTAGE=3.3V MIN_LINE_WIDTH=0.30 MM MIN_NECK_WIDTH=0.20 MM THRM PAD C9011 0.1UF 10% 16V X5R 402 10% 16V X5R 402 1 =PP3V3_S0_LCD R9008 100K 5% 1/16W MF-LF 402 17A3 6C7 PP3V3_LCDVDD_SW_F MIN_NECK_WIDTH=0.20 MM VOLTAGE=3.3VMIN_LINE_WIDTH=0.30 MM L9008 CRITICAL 10UF 17B3 6C7 6C7 6C3 6B7 0402-LF 7C5 10% 50V X7R 402 120-OHM-0.3A-EMI C9012 20% 6.3V X5R 603 32 0.001UF 2 0402-LF F-RT-SM 31 6C7 TP_BKL_SYNC PP3V3_S0_LCD_F C MIN_LINE_WIDTH=0.25 MM VOLTAGE=3.3V MIN_NECK_WIDTH=0.20 MM 17B3 6C7 75B3 17B3 6C7 75B3 (LVDS DDC POWER) R9009 17B3 6C7 75B3 75B3 17B3 6C7 100K 5% 1/16W MF-LF 402 LVDS_IG_A_DATA_N LVDS_IG_A_DATA_P 10 LVDS_IG_A_DATA_N LVDS_IG_A_DATA_P 11 12 13 75B3 17B3 6C7 75B3 17B3 6C7 LVDS_IG_DDC_CLK LVDS_IG_DDC_DATA LVDS_IG_A_DATA_N LVDS_IG_A_DATA_P 14 15 16 CRITICAL L9080 90-OHM-200MA AMC2012-SM LVDS_IG_A_CLK_F_N 6C7 LVDS_IG_A_CLK_F_P 75B3 6C7 17 75B3 18 LVDS I/F SYM_VER-1 75B3 17B3 LVDS_IG_A_CLK_N LVDS_IG_A_CLK_P 19 NC 20 21 75B3 17B3 71B1 6C7 71B1 6C7 71B1 6C7 71B1 6B7 71B1 6B7 71A1 6B7 71C1 6C7 6C3 PPVOUT_S0_LCDBKLT 22 NC LED_RETURN_1 LED_RETURN_2 LED_RETURN_3 LED_RETURN_4 LED_RETURN_5 LED_RETURN_6 23 24 LED BKLT I/F 25 26 27 28 29 NC B 30 B 33 34 A SYNC_MASTER=NMARTIN SYNC_DATE=04/04/2008 A PAGE TITLE LVDS CONNECTOR DRAWING NUMBER Apple Inc 051-7898 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED D REVISION C.0.0 R NOTICE OF PROPRIETARY PROPERTY: SIZE BRANCH PAGE 90 OF 109 SHEET OF 8 17B6 17B6 17B6 17B6 17B6 17B6 17B6 17B6 17B6 D 17A3 17A3 =MCP_HDMI_TXC_P =MCP_HDMI_TXC_N =MCP_HDMI_TXD_P =MCP_HDMI_TXD_N =MCP_HDMI_TXD_P =MCP_HDMI_TXD_N =MCP_HDMI_TXD_P =MCP_HDMI_TXD_N =MCP_HDMI_HPD =MCP_HDMI_DDC_CLK =MCP_HDMI_DDC_DATA DP_ML_P DP_ML_N DP_ML_P DP_ML_N DP_ML_P DP_ML_N DP_ML_P DP_ML_N DP_HPD 70C8 75C3 MAKE_BASE=TRUE 70C8 75C3 MAKE_BASE=TRUE 70C1 75C3 MAKE_BASE=TRUE 70C1 75C3 MAKE_BASE=TRUE 70C1 75C3 MAKE_BASE=TRUE 70C1 75C3 MAKE_BASE=TRUE 70C1 75C3 MAKE_BASE=TRUE 70C1 75C3 MAKE_BASE=TRUE 70A8 D MAKE_BASE=TRUE DP_IG_DDC_CLK DP_IG_DDC_DATA 69C8 MAKE_BASE=TRUE 69C8 MAKE_BASE=TRUE DP_AUX_CH_C_N BI C9300 R9300 DP_IG_DDC_DATA 69D1 BI 33 0.1UF 5% 1/16W MF-LF 402 DP_IG_DDC_CLK 69D1 BI 75B3 DP_AUX_CH_SW_N 10% 16V X5R 402 Display Port Interoperability spec says that sources or sinks which both DP and DVI must depend on the external adapter for pull ups on DDC lines (since DP AUX CH has 100K pull up/down on the MLB) DP_AUX_CH_C_P BI R9301 33 5% 1/16W MF-LF 402 70C8 75B3 70C8 75B3 C9301 0.1UF 75B3 DP_AUX_CH_SW_P 10% 16V X5R 402 C D Q9300 SSM6N15FEAPE Q9300 S G D S C SSM6N15FEAPE SOT563 SOT563 G DP_IG_AUX_CH_P 75B3 17B6 BI 75B3 17B6 BI DP_IG_AUX_CH_N =PP5V_S0_DP_AUX_MUX 7D5 R9302 100K 5% 1/16W MF-LF 402 R9306 1K 5% 1/16W MF-LF 402 DDC_CA_DET_LS5V_L B B Q9301 D SSM3K15FV SOD-VESM-HF S G DP_CA_DET 70B8 IN DP_IG_CA_DET OUT 17B6 A SYNC_MASTER=AMASON SYNC_DATE=04/18/2008 A PAGE TITLE DISPLAYPORT SUPPORT DRAWING NUMBER Apple Inc 051-7898 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED D REVISION C.0.0 R NOTICE OF PROPRIETARY PROPERTY: SIZE BRANCH PAGE 93 OF 109 SHEET OF 8 Port Power Switch DP_ESD CRITICAL CRITICAL L9400 7A3 66D5 40C5 35A5 32B7 20C3 6C3 IN =PP3V3_S5_DP_PORT_PWR IN EN PM_SLP_S3_L FERR-120-OHM-3A TPS2051B SOT23 OUT PP3V3_S0_DPILIM OC* MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=3.3V TP_DPPWR_OC_L 0603 GND C9400 RCLAMP0524P SLP2510P8 SLP2510P8 PP3V3_S0_DPPWR MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=3.3V 4.7UF D D9410 RCLAMP0524P IO NC 20% 6.3V X5R-CERM 402 IO NC IO NC IO NC GND U9480 DP_ESD CRITICAL D9410 GND D 3 10 CRITICAL C9480 1 2 22UF 20% 6.3V X5R-CERM-1 603 C9481 C9485 4.7UF 20% 6.3V X5R-CERM-1 603 C9486 1 20% 6.3V X5R-CERM-1 603 22UF 22UF 20% 6.3V X5R-CERM 402 R9420 100K 5% 1/16W MF-LF 402 CRITICAL HDMI_CEC J9400 DSPLYPRT-M97-1 FL9400 F-RT-THSM C R9425 1M FL9403 12-OHM-100MA IN DP_ML_P C9414 75C3 69D1 IN DP_ML_N C9415 BI DP_AUX_CH_C_P BI DP_AUX_CH_C_N 75C3 DP_ML_C_P 10% 16V X5R 402 75C3 DP_ML_C_N 10% 16V X5R 402 0.1uF 0.1uF 75B3 69C4 TCM1210-4SM SYM_VER-2 BOT ROW TOP ROW TH PINS SM PINS 75B3 75B3 10 DP_ML_CONN_P DP_ML_CONN_N 12 ML_LANE3N GND AUX_CHP AUX_CHN DP_PWR 14 16 18 75B3 69D4 70B8 7C5 20 R9443 R9442 100K 5% 1/16W MF-LF 402 69B7 OUT 5% 1/16W MF-LF 402 DP_CA_DET 5% 1/16W MF-LF 402 2 G DP_CA_DET_L_Q IO NC IO NC C9411 75C3 DP_ML_C_N 10% DP_ML_N 10% SYM_VER-2 C9412 DP_ML_P 75C3 DP_ML_C_N C9413 10% DP_ML_N 75C3 DP_ML_C_P C9416 10% DP_ML_P 75C3 DP_ML_C_N C9417 10% DP_ML_N 0.1uF FL9402 12-OHM-100MA TCM1210-4SM 75C3 DP_ML_C_P 0.1uF 75B3 DP_ML_CONN_P 17 19 0.1uF 13 15 0.1uF 75B3 DP_ML_CONN_N 16V 16V 16V 16V 16V 16V X5R X5R X5R X5R X5R X5R 402 402 402 402 402 402 IN 69D1 75C3 IN 69D1 75C3 IN 69D1 75C3 IN 69D1 75C3 IN 69D1 75C3 IN 69D1 75C3 21 DP_ESD CRITICAL D9411 RCLAMP0524P D9400 SLP2510P8 RCLAMP0504F SC70-6-1 SOT-363 S G DP_CA_DET_Q R9422 DP to DVI/HDMI Cable Adapter (CA) has 100k pull-up to DP_PWR 1M Q9440 must have Drain to Gate leakage of 5MOhm 5% 1/16W MF-LF 402 IO NC IO NC B =PP3V3_S0_DPCONN R9445 R9444 10K 5% 1/16W MF-LF 402 69D1 DP_ESD CRITICAL 2N7002DW-X-G 70C8 7C5 DP_ML_CONN_P DP_ML_CONN_N 10 D Q9440 B 75B3 11 DP_ML_P 75B3 10% 514-0637 GND 2N7002DW-X-G S SYM_VER-2 SLP2510P8 D SOT-363 12-OHM-100MA TCM1210-4SM C9410 100K Q9440 C 0.1uF ML_LANE1N GND ML_LANE2P ML_LANE2N RETURN 22 RCLAMP0524P R9421 SYM_VER-2 75C3 DP_ML_C_P FL9401 12-OHM-100MA TCM1210-4SM SHIELD PINS D9411 100K DP_ML_CONN_P DP_ML_CONN_N 0.1uF DP_ESD CRITICAL =PP3V3_S0_DPCONN 75B3 HOT_PLUG_DETECT GND CONFIG1 ML_LANE0P CONFIG2 ML_LANE0N GND GND ML_LANE3P ML_LANE1P 75B3 GND 75C3 69D1 5% 1/16W MF-LF 402 OUT 10K 5% 1/16W MF-LF 402 DP_HPD R9446 100K 5% 1/16W MF-LF 402 MCP79 requires pull Q9441 down HPD input with 2N7002DW-X-G SOT-363 100K if DP_HPD is used D S G DP_HPD_L_Q D Q9441 2N7002DW-X-G A SOT-363 S G DP_HPD_Q SYNC_MASTER=AMASON SYNC_DATE=06/30/2008 A PAGE TITLE R9423 100K 5% 1/16W MF-LF 402 DisplayPort Connector DP Source must pull down HPD input with greater than or equal to 100K (DPv1.1a) DRAWING NUMBER Apple Inc 051-7898 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED D REVISION C.0.0 R NOTICE OF PROPRIETARY PROPERTY: SIZE BRANCH PAGE 94 OF 109 SHEET OF 8 *L9701, D9701, C9796, C9797, C9799, C9712 AND C9713 SHOULD ALL BE PLACED NEAR EACHOTHER *PPVOUT_S0_LCDBKLT_SW SHOULD BE KEPT AS SHORT AS POSSIBLE * LVDS_IG_BKL_PWM SHOULD BE AWAY FROM BOOST CIRCUIT BKLT_VLDO_EN_L NO STUFF Q9701 NTUD3127CXXG SOT-963 N-CHANNEL D NO STUFF R9701 G D BKLT_EN_R S BKLT_EN 71B6 D 5% 1/16W MF-LF 402 D NO STUFF R9735 G S 100K 1% 1/16W MF-LF 402 P-CHANNEL MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM =PP5V_S0_BKL 7D5 NO STUFF VOLTAGE=5V R9702 5% 1/16W MF-LF CRITICAL 402 PPBUS_S0_LCDBKLT_PWR PPVIN_BKL CRITICAL 5% 1/16W MF-LF 402 C D9701 SOD-123 22UH-2.5A R9700 72C3 71B7 CRITICAL L9701 BKLT_PROD C9712 10UF MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.375 MM C9713 PPBUS_S0_LCDBKLT_PWR_SW IHLP2525CZ-SM VOLTAGE=6V 10% 25V X5R 805 2 C9710 1UF C9711 0.1UF 10% 16V X5R 402 10% 25V X5R 603-1 VDDIO 23 0.01UF 22 C9714 10% 16V CERM 402 200PF 5% 1/16W MF-LF 402 C9799 2.2UF 10% 100V X7R 1210 C9797 C 2.2UF 10% 100V X7R 1210 BKL_SWGND 71B5 71C5 PPVIN_BKL_R 7B5 =PP3V3_S0_BKL_VDDIO 5% 1/16W MF-LF 402 C9796 5% 100V CERM 1206 BKL_VLDO 100K VOLTAGE=50V R9703 71B5 71C2 6C3 6C7 68B2 MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.375 MM 1 10% 25V X5R 402 BKL_SWGND R9716 PPVOUT_S0_LCDBKLT RB160M-40 VOLTAGE=50V SWITCH_NODE=TRUE 0.1UF MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.375 MM VLDO VIN CRITICAL U9701 LP8543SQX LLP NO STUFF R9714 100K NC 5% 1/16W MF-LF 402 ALSI IF_SEL=1 FOR SMBUS IF_SEL=0 FOR I2C 20 ADR 5% 43B6 =I2C_BKL_1_SDA R9757 1/16W MF-LF 5% 1/16W BKL_SCL 10 SCLK BKL_SDA 11 SDA 402 MF-LF PPBUS_S0_LCDBKLT_PWR 71D3 BKL_ISEN2 OUT3 14 BKL_ISEN3 OUT4 16 BKL_ISEN4 OUT5 17 TP_BKL_FAULT FAULT OUT6 18 BKLT_EN EN OUT7 19 0.1UF 10% 25V X5R 402 1% 1/16W MF-LF 402 GND_SW R9715 100K C9723 BKL_SWGND HIGH CURRENT NEED VIAS BKL_ISEN5 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm OUT 6C7 68B3 LED_RETURN_2 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm BKLT_PROD OUT 6C7 68B3 OUT 6C7 68B3 OUT 6B7 68B3 OUT 6B7 68B3 OUT 6B7 68B3 B R9719 THRM PAD LED_RETURN_3 5% 1/16W MF-LF 402 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm BKLT_PROD R9720 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm 71C5 71C2 5% 1/16W MF-LF 402 BKL_ISEN6 NC XW9700 SM NO STUFF LED_RETURN_1 BKLT_PROD R9718 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm 5% 1/16W MF-LF 402 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm 1% 1/16W MF-LF 402 301K 1 BKL_ISEN1 OUT2 13 PWM R9731 72C3 71C7 402 LVDS_IG_BKL_PWM_RC B OUT1 12 OMIT 15 GND_L R9717 FB 21 25 R9753 GND_S =I2C_BKL_1_SCL SW 24 IF_SEL BKL_IF_SEL 43B6 ALSO LED_RETURN_4 5% 1/16W MF-LF 402 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm BKLT_PROD BKL_SWGND R9721 PLACEMENT_NOTE=SW9700 PLACE NEAR C9712 C9713 R9704 72B7 17B6 IN LVDS_IG_BKL_PWM 1 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm 5% 1/16W MF-LF 402 NO STUFF XW9710 SM C9704 33PF R9704 SHOULD BE 47K IF RC FILTER IS USED 5% 50V CERM 402 BKL_SGND LED_RETURN_5 5% 1/16W MF-LF 402 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm BKLT_PROD R9722 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm 5% 1/16W MF-LF 402 LED_RETURN_6 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm BKLT_PROD A SYNC_MASTER=KIRAN SYNC_DATE=12/05/2008 A PAGE TITLE PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION 103S0198 RES,THIN FLIM,1/16W,10.2 OHM,0.1,0402,SM R9717,R9718,R9719,R9720,R9721,R9722 BKLT_ENG 116S0005 RES,1/16W,0.1 OHM,1%,0402,SM R9700 BKLT_ENG PART NUMBER 353S2670 QTY DESCRIPTION REFERENCE DES IC,LP8543,WHT LED BKLT CTRLR,QFN24,PROD U9701 CRITICAL BOM OPTION LCD BACKLIGHT DRIVER CRITICAL DRAWING NUMBER Apple Inc 051-7898 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED D REVISION C.0.0 R NOTICE OF PROPRIETARY PROPERTY: SIZE BRANCH PAGE 97 OF 109 SHEET OF 8 CRITICAL Q9806 FDC638APZ_SBMS001 PPBUS S0 LCDBkLT FET SSOT6-HF F9800 0402-HF PPBUS_S0_LCDBKLT_FUSED MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.6V MOSFET FDC638APZ CHANNEL P-TYPE D 2 1 MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.6V R9808 LOADING 0.1UF 1% 1/16W MF-LF 43 mOhm @4.5V C9802 301K RDS(ON) 10% 16V X5R 402 402 0.4 A (EDP) D =PPBUS_S0_LCDBKLT IN 2AMP-32V 7C1 PPBUS_S0_LCDBKLT_EN_DIV R9809 147K 1% 1/16W MF-LF 402 PPBUS_S0_LCDBKLT_EN_L Q9807 D S SSM6N15FEAPE SOT563 72B7 17B6 LVDS_IG_BKL_ON IN G PPBUS_S0_LCDBKLT_PWR Q9807 OUT 71B7 71C7 MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.6V BKLT_EN_L D S SSM6N15FEAPE SOT563 C 24C1 BKLT_PLT_RST_L IN G C B B LVDS_IG_BKL_ON LVDS_IG_BKL_PWM R9840 1K 5% 1/16W MF-LF 402 17B6 72C8 17B6 71A7 R9841 1K 5% 1/16W MF-LF 402 MCP HAS INTERNAL 10K PULL-UP FOR THESE SIGNALS A SYNC_MASTER=YITE SYNC_DATE=06/30/2008 A PAGE TITLE LCD Backlight Support DRAWING NUMBER Apple Inc 051-7898 SIZE D REVISION C.0.0 R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED BRANCH PAGE 98 OF 109 SHEET OF FSB (Front-Side Bus) Constraints LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH CPU / FSB Net Properties TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP NET_TYPE DIFFPAIR NECK GAP ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING TABLE_PHYSICAL_RULE_ITEM FSB_50S * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD FSB_DATA_GROUP0 FSB_50S FSB_DATA FSB_DATA_GROUP0 FSB_50S FSB_DATA FSB_DSTB0 FSB_DSTB_50S FSB_DSTB FSB_DSTB0 FSB_DSTB_50S FSB_DSTB TABLE_PHYSICAL_RULE_ITEM * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =1:1_DIFFPAIR =1:1_DIFFPAIR TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM FSB_DATA * =2x_DIELECTRIC ? FSB_DSTB * =3x_DIELECTRIC ? TABLE_SPACING_RULE_ITEM FSB_DATA TOP,BOTTOM =4x_DIELECTRIC ? FSB_DSTB TOP,BOTTOM =5x_DIELECTRIC ? TABLE_SPACING_RULE_ITEM D TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM FSB_ADDR * =STANDARD TABLE_SPACING_RULE_ITEM ? FSB_ADDR TOP,BOTTOM =3x_DIELECTRIC ? TABLE_SPACING_RULE_ITEM FSB_ADSTB * =2x_DIELECTRIC ? FSB_1X * =STANDARD ? FSB 4X Signal Groups FSB_DSTB_50S TABLE_SPACING_RULE_ITEM FSB_ADSTB TOP,BOTTOM =4x_DIELECTRIC ? FSB_1X TOP,BOTTOM =3x_DIELECTRIC ? TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM All 4x/2x/1x FSB signals with impedance requirements are 50-ohm single-ended FSB 2X Signals FSB 4X signals / groups shown in signal table on right Signals within each 4x group should be matched within ps of strobe DSTB# complementary pairs should be matched within ps of each other, all DSTB#s matched to +/- 300 ps Spacing is 2x dielectric between DATA#, DINV# signals, with 3x dielectric spacing to the DSTB#s DSTB# complementary pairs are spaced normally and are NOT routed as differential pairs FSB 2X signals / groups shown in signal table on right Signals within each 2x group should be matched within 20 ps ADTSB#s should be matched +/- 300 ps Spacing is 1x dielectric between ADDR#, REQ# signals, with 2x dielectric spacing to ADSTB# FSB 1X signals shown in signal table on right Signals within each 1x group should be matched to CPU clock, +0/-1000 mils FSB 1X Signals Design Guide recommends each strobe/signal group is routed on the same layer Intel Design Guide recommends FSB signals be routed only on internal layers NOTE: Intel Design Guide allows closer spacing if signal lengths can be shortened SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2 SOURCE: Santa Rosa Platform DG, Rev 1.5 (#22294), Sections 4.2 & 4.3 CPU Signal Constraints FSB_DATA_GROUP1 FSB_50S FSB_DATA FSB_DATA_GROUP1 FSB_50S FSB_DATA FSB_DSTB1 FSB_DSTB_50S FSB_DSTB FSB_DSTB1 FSB_DSTB_50S FSB_DSTB FSB_DATA_GROUP2 FSB_50S FSB_DATA FSB_DATA_GROUP2 FSB_50S FSB_DATA FSB_DSTB2 FSB_DSTB_50S FSB_DSTB FSB_DSTB2 FSB_DSTB_50S FSB_DSTB FSB_DATA_GROUP3 FSB_50S FSB_DATA FSB_DATA_GROUP3 FSB_50S FSB_DATA FSB_DSTB3 FSB_DSTB_50S FSB_DSTB FSB_DSTB3 FSB_DSTB_50S FSB_DSTB FSB_ADDR_GROUP0 FSB_50S FSB_ADDR FSB_ADDR_GROUP0 FSB_50S FSB_ADDR FSB_ADSTB0 FSB_50S FSB_ADSTB FSB_ADDR_GROUP1 FSB_50S FSB_ADDR FSB_ADSTB1 FSB_50S FSB_ADSTB FSB_1X FSB_50S FSB_1X FSB_BREQ0_L FSB_50S FSB_1X FSB_BREQ1_L FSB_50S FSB_1X FSB_1X FSB_50S FSB_1X FSB_1X FSB_50S FSB_1X FSB_1X FSB_50S FSB_1X FSB_1X FSB_50S FSB_1X FSB_1X FSB_50S FSB_1X FSB_1X FSB_50S FSB_1X FSB_1X FSB_50S FSB_1X FSB_1X FSB_50S FSB_1X FSB_CPURST_L FSB_50S FSB_1X FSB_1X FSB_50S FSB_1X FSB_1X FSB_50S FSB_1X CPU_ASYNC CPU_50S CPU_AGTL CPU_BSEL CPU_50S CPU_AGTL CPU_FERR_L CPU_50S CPU_8MIL CPU_ASYNC CPU_50S CPU_AGTL CPU_INIT_L CPU_50S CPU_AGTL CPU_ASYNC_R CPU_50S CPU_AGTL CPU_ASYNC_R CPU_50S CPU_AGTL CPU_PROCHOT_L CPU_50S CPU_AGTL CPU_PWRGD CPU_50S CPU_AGTL CPU_ASYNC CPU_50S CPU_AGTL CPU_ASYNC CPU_50S CPU_AGTL PM_THRMTRIP_L CPU_50S CPU_8MIL FSB_CPUSLP_L CPU_50S CPU_AGTL CPU_FROM_SB CPU_50S CPU_AGTL CPU_DPRSTP_L CPU_50S CPU_AGTL TABLE_PHYSICAL_RULE_HEAD C PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM CPU_50S * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD TABLE_PHYSICAL_RULE_ITEM CPU_27P4S * =27P4_OHM_SE =27P4_OHM_SE =27P4_OHM_SE =27P4_OHM_SE MIL MIL NOTE: mil gap is for VCCSense pair, which Intel says to route with mil spacing without specifying a target impedance TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM CPU_AGTL * =STANDARD ? CPU_8MIL * MIL ? TABLE_SPACING_RULE_ITEM CPU_AGTL TOP,BOTTOM =2x_DIELECTRIC ? TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM CPU_COMP * 25 MIL ? CPU_GTLREF * 25 MIL ? TABLE_SPACING_RULE_ITEM SR DG recommends at least 25 mils, >50 mils preferred TABLE_SPACING_RULE_ITEM CPU_ITP * =2:1_SPACING ? CPU_VCCSENSE * 25 MIL ? TABLE_SPACING_RULE_ITEM Most CPU signals with impedance requirements are 55-ohm single-ended Some signals require 27.4-ohm single-ended impedance SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2 SOURCE: Santa Rosa Platform DG, Rev 0.9 (#20517), Sections 4.4 & 5.8.2.4 MCP FSB COMP Signal Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP * =50_OHM_SE =50_OHM_SE B =50_OHM_SE =50_OHM_SE CPU_50S CPU_AGTL MCP_50S MCP_FSB_COMP MCP_CPU_COMP MCP_50S MCP_FSB_COMP MCP_CPU_COMP MCP_50S MCP_FSB_COMP MCP_CPU_COMP MCP_50S MCP_FSB_COMP FSB_CLK_CPU CLK_FSB_100D CLK_FSB FSB_CLK_CPU CLK_FSB_100D CLK_FSB FSB_CLK_ITP CLK_FSB_100D CLK_FSB =STANDARD FSB_CLK_ITP CLK_FSB_100D CLK_FSB FSB_CLK_MCP CLK_FSB_100D CLK_FSB FSB_CLK_MCP CLK_FSB_100D CLK_FSB CPU_IERR_L CPU_50S PM_DPRSLPVR CPU_50S CPU_AGTL (See above) CPU_50S CPU_AGTL CPU_GTLREF CPU_50S CPU_GTLREF =STANDARD TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM MCP_FSB_COMP * MIL ? SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2.4 FSB Clock Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM CLK_FSB_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF LAYER LINE-TO-LINE SPACING WEIGHT LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM CLK_FSB * =3x_DIELECTRIC CPU_COMP CPU_50S CPU_COMP CPU_COMP CPU_27P4S CPU_COMP CPU_COMP CPU_50S CPU_COMP CPU_COMP CPU_27P4S CPU_COMP XDP_TDI CPU_50S CPU_ITP XDP_TDO CPU_50S CPU_ITP XDP_TMS CPU_50S CPU_ITP TABLE_SPACING_RULE_HEAD SPACING_RULE_SET TABLE_SPACING_RULE_ITEM ? CLK_FSB TOP,BOTTOM =4x_DIELECTRIC FSB_D_L FSB_DINV_L FSB_DSTB_L_P FSB_DSTB_L_N FSB_D_L FSB_DINV_L FSB_DSTB_L_P FSB_DSTB_L_N FSB_A_L FSB_REQ_L FSB_ADSTB_L FSB_A_L FSB_ADSTB_L FSB_ADS_L FSB_BREQ0_L FSB_BREQ1_L FSB_BNR_L FSB_BPRI_L FSB_DBSY_L FSB_DEFER_L FSB_DRDY_L FSB_HIT_L FSB_HITM_L FSB_LOCK_L FSB_CPURST_L FSB_RS_L FSB_TRDY_L CPU_A20M_L CPU_BSEL CPU_FERR_L CPU_IGNNE_L CPU_INIT_L CPU_INTR CPU_NMI CPU_PROCHOT_L CPU_PWRGD CPU_SMI_L CPU_STPCLK_L PM_THRMTRIP_L FSB_CPUSLP_L CPU_DPSLP_L CPU_DPRSTP_L FSB_DPWR_L MCP_BCLK_VML_COMP_VDD MCP_BCLK_VML_COMP_GND MCP_CPU_COMP_VCC MCP_CPU_COMP_GND FSB_CLK_CPU_P FSB_CLK_CPU_N FSB_CLK_ITP_P FSB_CLK_ITP_N FSB_CLK_MCP_P FSB_CLK_MCP_N CPU_IERR_L =100_OHM_DIFF TABLE_SPACING_RULE_HEAD SPACING_RULE_SET FSB_D_L FSB_DINV_L FSB_DSTB_L_P FSB_DSTB_L_N 9C4 13D3 9C4 13D6 9C4 13D6 9C4 13D6 9B4 9C4 13C3 13D3 9B4 13D6 9B4 13D6 D 9B4 13D6 9C2 13B3 13C3 9C2 13D6 9C2 13D6 9C2 13D6 9B2 9C2 13B3 9B2 13D6 9B2 13D6 9B2 13D6 9D8 13C6 13D6 9D8 13B6 9D8 13B6 9C8 9D8 13C6 9C8 13B6 9D6 13B6 9D6 13B6 13B6 9D6 13B6 9D6 13B3 9D6 13B6 9D6 13B3 9D6 13B6 9D6 13B6 9D6 13B6 C 9D6 13B6 9D6 12C2 13A3 9D6 13A6 9D6 13B6 9C8 13A3 8B2 9B4 9C8 13B7 9C8 13A3 9D6 13A3 9C8 13A3 9B8 13A3 9C5 13B6 41D4 62C8 9B2 12C7 13A3 9B8 13A3 9C8 13A3 9C6 13B7 41C4 9B2 13A3 9B2 13A3 9B2 13A3 62C7 9B2 13A3 13A6 13A6 13A6 13A6 DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM MCP_50S CPU_ASYNC MCP_CPU_COMP FSB_D_L FSB_DINV_L FSB_DSTB_L_P FSB_DSTB_L_N 9B6 13B3 9B6 13B3 B 12C3 13B3 12C3 13B3 13A4 13A4 9D6 PM_DPRSLPVR IMVP_DPRSLPVR CPU_GTLREF CPU_COMP CPU_COMP CPU_COMP CPU_COMP 20C7 62D8 62C7 9B4 25B1 9B3 9B3 9B3 9B3 ? SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2.5 A XDP_TCK CPU_50S CPU_ITP XDP_TRST_L CPU_50S CPU_ITP XDP_BPM_L CPU_50S CPU_ITP XDP_BPM_L5 CPU_50S CPU_ITP (FSB_CPURST_L) CPU_50S CPU_ITP CPU_50S CPU_8MIL CPU_50S CPU_8MIL CPU_VCCSENSE CPU_27P4S CPU_VCCSENSE CPU_VCCSENSE CPU_27P4S CPU_VCCSENSE (CPU_VCCSENSE) (CPU_VCCSENSE) CPU_27P4S CPU_VCCSENSE CPU_27P4S CPU_VCCSENSE XDP_TDI XDP_TDO XDP_TMS XDP_TCK XDP_TRST_L XDP_BPM_L XDP_BPM_L XDP_CPURST_L CPU_VID IMVP6_VID CPU_VCCSENSE_P CPU_VCCSENSE_N IMVP6_VSEN_P IMVP6_VSEN_N 9B6 9C6 12B3 9B6 9C6 12B3 9B6 9C6 12B3 9A6 9C6 12B6 9A6 9C6 12B3 9C6 12C6 9C5 12C6 12C4 10B6 62C7 10B5 62A5 10A5 62A5 SYNC_MASTER=T18_MLB SYNC_DATE=01/04/2008 A PAGE TITLE CPU/FSB Constraints DRAWING NUMBER Apple Inc 051-7898 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED D REVISION C.0.0 R NOTICE OF PROPRIETARY PROPERTY: SIZE BRANCH PAGE 100 OF 109 SHEET OF 8 Memory Bus Constraints LAYER ALLOW ROUTE ON LAYER? Memory Net Properties TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP NET_TYPE DIFFPAIR NECK GAP ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING TABLE_PHYSICAL_RULE_ITEM MEM_40S * =40_OHM_SE =40_OHM_SE =40_OHM_SE =40_OHM_SE =STANDARD =STANDARD MEM_A_CLK MEM_70D_VDD MEM_CLK MEM_A_CLK MEM_70D_VDD MEM_CLK MEM_A_CNTL MEM_40S_VDD MEM_CTRL MEM_A_CNTL MEM_40S_VDD MEM_CTRL MEM_A_CNTL MEM_40S_VDD MEM_CTRL MEM_A_CMD MEM_40S_VDD MEM_CMD MEM_A_CMD MEM_40S_VDD MEM_CMD MEM_A_CMD MEM_40S_VDD MEM_CMD MEM_A_CMD MEM_40S_VDD MEM_CMD MEM_A_CMD MEM_40S_VDD MEM_CMD MEM_A_DQ_BYTE0 MEM_40S MEM_DATA MEM_A_DQ_BYTE1 MEM_40S MEM_DATA MEM_A_DQ_BYTE2 MEM_40S MEM_DATA MEM_A_DQ_BYTE3 MEM_40S MEM_DATA MEM_A_DQ_BYTE4 MEM_40S MEM_DATA MEM_A_DQ_BYTE5 MEM_40S MEM_DATA MEM_A_DQ_BYTE6 MEM_40S MEM_DATA MEM_A_DQ_BYTE7 MEM_40S MEM_DATA MEM_A_DQ_BYTE0 MEM_40S MEM_DATA MEM_A_DQ_BYTE1 MEM_40S MEM_DATA MEM_A_DQ_BYTE2 MEM_40S MEM_DATA MEM_A_DQ_BYTE3 MEM_40S MEM_DATA MEM_A_DQ_BYTE4 MEM_40S MEM_DATA MEM_A_DQ_BYTE5 MEM_40S MEM_DATA MEM_A_DQ_BYTE6 MEM_40S MEM_DATA MEM_A_DQ_BYTE7 MEM_40S MEM_DATA MEM_A_DQS0 MEM_70D MEM_DQS MEM_A_DQS0 MEM_70D MEM_DQS MEM_A_DQS1 MEM_70D MEM_DQS MEM_A_DQS1 MEM_70D MEM_DQS MEM_A_DQS2 MEM_70D MEM_DQS MEM_A_DQS2 MEM_70D MEM_DQS MEM_A_DQS3 MEM_70D MEM_DQS MEM_A_DQS3 MEM_70D MEM_DQS MEM_A_DQS4 MEM_70D MEM_DQS MEM_A_DQS4 MEM_70D MEM_DQS MEM_A_DQS5 MEM_70D MEM_DQS MEM_A_DQS5 MEM_70D MEM_DQS MEM_A_DQS6 MEM_70D MEM_DQS MEM_A_DQS6 MEM_70D MEM_DQS MEM_A_DQS7 MEM_70D MEM_DQS MEM_A_DQS7 MEM_70D MEM_DQS MEM_B_CLK MEM_70D_VDD MEM_CLK MEM_B_CLK MEM_70D_VDD MEM_CLK MEM_B_CNTL MEM_40S_VDD MEM_CTRL MEM_B_CNTL MEM_40S_VDD MEM_CTRL MEM_B_CNTL MEM_40S_VDD MEM_CTRL TABLE_PHYSICAL_RULE_ITEM MEM_40S_VDD * =40_OHM_SE =40_OHM_SE =40_OHM_SE =40_OHM_SE =STANDARD =STANDARD MEM_A_CLK_P MEM_A_CLK_N 14B5 26C5 26C7 14B5 26C5 26C7 TABLE_PHYSICAL_RULE_ITEM MEM_70D * =70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF MEM_70D_VDD * =70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_HEAD SPACING_RULE_SET D LAYER LINE-TO-LINE SPACING WEIGHT =4:1_SPACING ? TABLE_SPACING_RULE_ITEM MEM_CLK2MEM * TABLE_SPACING_RULE_ITEM MEM_CTRL2CTRL * =2:1_SPACING ? MEM_CTRL2MEM * =2.5:1_SPACING ? MEM_A_CKE MEM_A_CS_L MEM_A_ODT MEM_A_A MEM_A_BA MEM_A_RAS_L MEM_A_CAS_L MEM_A_WE_L 14A5 26D5 26D7 14B5 26C5 26C7 14B5 26C5 14B5 14C5 26C5 26C7 14C5 26C5 26C7 D 14C5 26C5 14C5 26C7 14C5 26C7 TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM MEM_CMD2CMD * =1.5:1_SPACING ? TABLE_SPACING_RULE_ITEM MEM_CMD2MEM * =3:1_SPACING ? TABLE_SPACING_RULE_ITEM MEM_DATA2DATA * =1.5:1_SPACING ? TABLE_SPACING_RULE_ITEM MEM_DATA2MEM * =3:1_SPACING ? TABLE_SPACING_RULE_ITEM MEM_DQS2MEM * =3:1_SPACING ? MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ 14B7 26C2 26C4 26D2 26D4 14B7 26C2 26C4 14B7 14C7 26B2 26B4 26C2 26C4 14C7 26C2 26C4 14C7 26B5 26B7 26C5 26C7 14C7 14D7 26B5 26B7 14D7 26B5 26B7 14D7 26A5 26A7 26B5 26B7 TABLE_SPACING_RULE_ITEM MEM_2OTHER * 25 MIL ? Memory Bus Spacing Group Assignments TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET TABLE_SPACING_ASSIGNMENT_ITEM MEM_CLK MEM_CLK * MEM_CLK2MEM MEM_CLK MEM_CTRL * MEM_CLK2MEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CMD MEM_CLK * MEM_CMD2MEM MEM_CMD MEM_CTRL * MEM_CMD2MEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CLK MEM_CMD * MEM_CLK2MEM MEM_CLK MEM_DATA * MEM_CLK2MEM MEM_CMD MEM_CMD * MEM_CMD2CMD MEM_CMD MEM_DATA * MEM_CMD2MEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_DQS * MEM_CLK2MEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CMD MEM_DQS * MEM_CMD2MEM TABLE_SPACING_ASSIGNMENT_HEAD C NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET MEM_CTRL MEM_CLK * MEM_CTRL2MEM TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET MEM_DATA MEM_CLK * MEM_DATA2MEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CTRL MEM_CTRL * MEM_CTRL2CTRL MEM_CTRL MEM_CMD * MEM_CTRL2MEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_DATA MEM_CTRL * MEM_DATA2MEM MEM_DATA MEM_CMD * MEM_DATA2MEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CTRL MEM_DATA * MEM_CTRL2MEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_DATA MEM_DATA * MEM_DATA2DATA TABLE_SPACING_ASSIGNMENT_ITEM MEM_CTRL MEM_DQS * MEM_CTRL2MEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_DATA MEM_DQS * MEM_DATA2MEM TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE MEM_CLK * MEM_DQS2MEM MEM_DQS MEM_CTRL * MEM_DQS2MEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CLK * * MEM_2OTHER MEM_CTRL * * MEM_2OTHER TABLE_SPACING_ASSIGNMENT_ITEM MEM_CMD * MEM_DQS2MEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CMD * * MEM_2OTHER TABLE_SPACING_ASSIGNMENT_ITEM MEM_DQS MEM_DATA * MEM_DQS2MEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_DATA * * MEM_DQS * MEM_DQS2MEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_DQS * * MEM_B_CMD MEM_40S_VDD MEM_CMD MEM_B_CMD MEM_40S_VDD MEM_CMD MEM_B_CMD MEM_40S_VDD MEM_CMD MEM_B_CMD MEM_40S_VDD MEM_CMD MEM_B_CMD MEM_40S_VDD MEM_CMD MEM_B_DQ_BYTE0 MEM_40S MEM_DATA MEM_B_DQ_BYTE1 MEM_40S MEM_DATA MEM_B_DQ_BYTE2 MEM_40S MEM_DATA MEM_B_DQ_BYTE3 MEM_40S MEM_DATA MEM_B_DQ_BYTE4 MEM_40S MEM_DATA MEM_B_DQ_BYTE5 MEM_40S MEM_DATA MEM_B_DQ_BYTE6 MEM_40S MEM_DATA MEM_B_DQ_BYTE7 MEM_40S MEM_DATA MEM_B_DQ_BYTE0 MEM_40S MEM_DATA MEM_B_DQ_BYTE1 MEM_40S MEM_DATA MEM_B_DQ_BYTE2 MEM_40S MEM_DATA MEM_B_DQ_BYTE3 MEM_40S MEM_DATA MEM_B_DQ_BYTE4 MEM_40S MEM_DATA MEM_2OTHER Need to support MEM_*-style wildcards! DDR2: B DQ signals should be matched within 20 ps of associated DQS pair DQS intra-pair matching should be within ps, no inter-pair matching requirement All DQS pairs should be matched within 100 ps of clocks CLK intra-pair matching should be within ps, inter-pair matching should be within 140 ps A/BA/cmd signals should be matched within 75 ps, no CLK matching requirement All memory signals maximum length is 1.005 ps CLK minimum length is 594 ps (lengths include substrate) DQ/A/BA/cmd signal spacing is 3x dielectric, DQS/CLK is 4x dielectric DDR3: DQ signals should be matched within ps of associated DQS pair DQS intra-pair matching should be within ps, inter-pair matching shoulw be within 180 ps No DQS to clock matching requirement CLK intra-pair matching should be within ps, inter-pair matching should be within ps A/BA/cmd signals should be matched within ps of CLK pairs All memory signals maximum length is 1.005 ps CLK minimum length is 594 ps (lengths include substrate) DQ/A/BA/cmd signal spacing is 3x dielectric, DQS/CLK is 4x dielectric MEM_B_DQ_BYTE5 MEM_40S MEM_DATA SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.3 SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Section 6.2 MEM_B_DQ_BYTE6 MEM_40S MEM_DATA MEM_B_DQ_BYTE7 MEM_40S MEM_DATA MCP MEM COMP Signal Constraints MEM_B_DQS0 MEM_70D MEM_DQS MEM_B_DQS0 MEM_70D MEM_DQS MEM_B_DQS1 MEM_70D MEM_DQS MEM_B_DQS1 MEM_70D MEM_DQS MEM_B_DQS2 MEM_70D MEM_DQS MEM_B_DQS2 MEM_70D MEM_DQS MEM_B_DQS3 MEM_70D MEM_DQS MEM_B_DQS3 MEM_70D MEM_DQS MEM_B_DQS4 MEM_70D MEM_DQS MEM_B_DQS4 MEM_70D MEM_DQS MEM_B_DQS5 MEM_70D MEM_DQS MEM_B_DQS5 MEM_70D MEM_DQS MEM_B_DQS6 MEM_70D MEM_DQS MEM_B_DQS6 MEM_70D MEM_DQS MEM_B_DQS7 MEM_70D MEM_DQS MEM_B_DQS7 MEM_70D MEM_DQS MCP_MEM_COMP MCP_MEM_COMP MCP_MEM_COMP MCP_MEM_COMP MCP_MEM_COMP MCP_MEM_COMP TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM MCP_MEM_COMP * Y MIL MIL =STANDARD =STANDARD =STANDARD TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM MCP_MEM_COMP * MIL 14B7 26C2 14B7 26B5 14B7 26B7 14B7 26B5 MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N 14B7 26A7 14D5 26C2 14D5 26D2 14D5 26C4 14D5 26C4 14D5 26B2 14D5 26C2 C 14D5 26C4 14D5 26C4 14D5 26B7 14D5 26B7 14D5 26B5 14D5 26B5 14D5 26B7 14D5 26B7 14D5 26A5 MEM_B_CLK_P MEM_B_CLK_N 14D5 26A5 14B1 27C5 27C7 MEM_B_CKE MEM_B_CS_L MEM_B_ODT 14B1 27C5 27C7 14A1 27D5 27D7 14B1 27C5 27C7 14B1 27C5 MEM_2OTHER TABLE_SPACING_ASSIGNMENT_ITEM MEM_DQS 14B7 26B4 TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_DQS 14A7 26C2 SPACING_RULE_SET TABLE_SPACING_ASSIGNMENT_ITEM MEM_DQS 14A7 26C4 TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CLK MEM_A_DM MEM_A_DM MEM_A_DM MEM_A_DM MEM_A_DM MEM_A_DM MEM_A_DM MEM_A_DM ? SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.3.4 A MEM_B_A MEM_B_BA MEM_B_RAS_L MEM_B_CAS_L MEM_B_WE_L MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DM MEM_B_DM MEM_B_DM MEM_B_DM MEM_B_DM MEM_B_DM MEM_B_DM MEM_B_DM MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MCP_MEM_COMP_VDD MCP_MEM_COMP_GND 14B1 14C1 27C5 27C7 14C1 27C5 27C7 14C1 27C5 14C1 27C7 14C1 27C7 14B3 27C2 27C4 27D2 27D4 14B3 27C2 27C4 14B3 14C3 27C2 27C4 14C3 27B2 27B4 27C2 27C4 B 14C3 27B5 27B7 27C5 27C7 14C3 14D3 27B5 27B7 14D3 27B5 27B7 14D3 27A5 27A7 27B5 27B7 14A3 27C4 14A3 27C2 14B3 27C2 14B3 27B4 14B3 27B5 14B3 27B7 14B3 27B5 14B3 27A7 14D1 27C2 14D1 27D2 14D1 27C4 14D1 27C4 14D1 27C4 14D1 27C4 14D1 27B2 14D1 27C2 14D1 27B7 14D1 27B7 14D1 27B5 14D1 27B5 14D1 27B7 14D1 27B7 14D1 27A5 SYNC_MASTER=T18_MLB SYNC_DATE=01/04/2008 A PAGE TITLE Memory Constraints 14D1 27A5 DRAWING NUMBER 15C6 15C6 Apple Inc 051-7898 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED D REVISION C.0.0 R NOTICE OF PROPRIETARY PROPERTY: SIZE BRANCH PAGE 101 OF 109 SHEET OF 8 NET_TYPE PCI-Express ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP PCIE_90D * =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF PCIE_MINI_R2D TABLE_PHYSICAL_RULE_ITEM CLK_PCIE_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF PCIE PCIE_90D PCIE PCIE_90D PCIE PCIE_90D PCIE PCIE_90D PCIE PCIE_90D PCIE PCIE_90D PCIE PCIE_90D PCIE PCIE_90D PCIE PCIE_90D PCIE PCIE_90D PCIE PCIE_90D PCIE PCIE_90D PCIE PCIE_90D PCIE CLK_PCIE_100D CLK_PCIE CLK_PCIE_100D CLK_PCIE CLK_PCIE_100D CLK_PCIE CLK_PCIE_100D CLK_PCIE CLK_PCIE_100D CLK_PCIE CLK_PCIE_100D CLK_PCIE PCIE_CLK100M_FC_P PCIE_CLK100M_FC_N MCP_PEX_COMP MCP_PEX_CLK_COMP =100_OHM_DIFF PCIE_MINI_D2R TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING TABLE_SPACING_RULE_HEAD WEIGHT SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM PCIE * =3X_DIELECTRIC D * ? 20 MIL PCIE TOP,BOTTOM =4X_DIELECTRIC ? ? TABLE_SPACING_RULE_ITEM MCP_PEX_COMP * MIL PCIE_FW_R2D ? SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.4 PCIE_FW_D2R MCP_PE1_REFCLK MCP_PE4_REFCLK MCP_PEX_CLK_COMP C 6D5 29C7 6D5 29C7 16B3 29C5 16B3 29C5 6D5 16B6 29C7 6D5 16B6 29C7 TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM CLK_PCIE PCIE_MINI_R2D_P PCIE_MINI_R2D_N PCIE_MINI_R2D_C_P PCIE_MINI_R2D_C_N PCIE_MINI_D2R_P PCIE_MINI_D2R_N PCIE_90D TABLE_PHYSICAL_RULE_ITEM PCIE_FW_R2D_P PCIE_FW_R2D_N PCIE_FW_R2D_C_P PCIE_FW_R2D_C_N PCIE_FW_D2R_P PCIE_FW_D2R_N PCIE_FW_D2R_C_P PCIE_FW_D2R_C_N PCIE_CLK100M_MINI_P PCIE_CLK100M_MINI_N PCIE_CLK100M_MINI_CONN_P PCIE_CLK100M_MINI_CONN_N 34C3 34C3 D 16B3 34C1 16B3 34C1 16B6 34C1 16B6 34C1 34C3 34C3 16C3 29C5 16C3 29C5 6D5 29C7 6D5 29C7 16A6 C Digital Video Signal Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM DP_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF LVDS_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF MCP_DV_COMP * Y 20 MIL 20 MIL =STANDARD =STANDARD =STANDARD TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING * =3x_DIELECTRIC SPACING_RULE_SET LAYER LINE-TO-LINE SPACING * DISPLAYPORT DP_100D DISPLAYPORT TMDS_IG_TXD DP_100D DISPLAYPORT DP_ML DP_100D DISPLAYPORT DP_100D DISPLAYPORT DP_100D DISPLAYPORT DP_100D DISPLAYPORT DP_100D DISPLAYPORT DP_100D DISPLAYPORT DP_100D DISPLAYPORT DP_100D DISPLAYPORT DP_100D DISPLAYPORT DP_100D DISPLAYPORT TABLE_SPACING_RULE_ITEM ? =3x_DIELECTRIC DISPLAYPORT DP_100D TMDS_IG_TXD WEIGHT DISPLAYPORT TOP,BOTTOM =4x_DIELECTRIC ? TABLE_SPACING_RULE_ITEM LVDS DP_100D TMDS_IG_TXC TABLE_SPACING_RULE_ITEM LVDS ? TOP,BOTTOM =4x_DIELECTRIC DP_ML ? LVDS intra-pair matching should be mils Pairs should be within 100 mils of clock length DisplayPort/TMDS intra-pair matching should be ps Inter-pair matching should be within 150 ps DIsplayPort AUX CH intra-pair matching should be ps No relationship to other signals Max length of LVDS/DisplayPort/TMDS traces: 12 inches SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Sections 2.5.3 & 2.5.4 DP_AUX_CH SATA Interface Constraints LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP DP_ML_P DP_ML_C_P DP_ML_N DP_ML_C_N DP_IG_AUX_CH_P DP_IG_AUX_CH_N DP_AUX_CH_SW_P DP_AUX_CH_SW_N DP_AUX_CH_C_P DP_AUX_CH_C_N MCP_HDMI_RSET MCP_HDMI_VPROBE MCP_HDMI_RSET MCP_DV_COMP MCP_HDMI_VPROBE MCP_DV_COMP LVDS_IG_A_CLK LVDS_100D LVDS LVDS_100D LVDS LVDS_100D LVDS LVDS_100D LVDS LVDS_IG_A_DATA LVDS_100D LVDS LVDS_IG_A_DATA LVDS_100D LVDS DP_ML DP_100D DISPLAYPORT DP_100D DISPLAYPORT TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET TMDS_IG_TXC_P TMDS_IG_TXC_N TMDS_IG_TXD_P TMDS_IG_TXD_N TABLE_SPACING_RULE_HEAD WEIGHT TABLE_SPACING_RULE_ITEM DISPLAYPORT TMDS_IG_TXC 69D1 70C1 70C8 70C2 70C7 69D1 70C1 70C8 70C2 70C7 17B6 69C7 17B6 69C7 69C6 69C5 69C4 70C8 69D4 70C8 17A6 23C7 17A6 23C7 TABLE_PHYSICAL_RULE_ITEM SATA_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF SATA_90D_HDD * =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF TABLE_PHYSICAL_RULE_ITEM LVDS_IG_A_CLK TABLE_SPACING_RULE_HEAD B SPACING_RULE_SET LAYER LINE-TO-LINE SPACING TABLE_SPACING_RULE_HEAD WEIGHT SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM SATA * =4x_DIELECTRIC TABLE_SPACING_RULE_ITEM ? SATA TOP,BOTTOM =3x_DIELECTRIC LVDS_IG_A_CLK_P LVDS_IG_A_CLK_F_P LVDS_IG_A_CLK_N LVDS_IG_A_CLK_F_N LVDS_IG_A_DATA_P LVDS_IG_A_DATA_N 17B3 68B3 6C7 68C2 17B3 68B3 6C7 68C2 B 6C7 17B3 68C2 6C7 17B3 68C2 ? TABLE_SPACING_RULE_ITEM SATA_TERMP * MIL ? I183 SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.7.1 I182 MCP_IFPAB_RSET MCP_IFPAB_RSET MCP_IFPAB_VPROBE MCP_DV_COMP MCP_IFPAB_VPROBE SATA_HDD_R2D SATA_HDD_D2R SATA_ODD_R2D A SATA_ODD_D2R MCP_SATA_TERMP DP_ML_CONN_P DP_ML_CONN_N SATA_90D_HDD SATA SATA_90D_HDD SATA SATA_90D_HDD SATA SATA_90D_HDD SATA SATA_90D_HDD SATA SATA_90D_HDD SATA SATA_90D_HDD SATA SATA_90D_HDD SATA SATA_90D_HDD SATA SATA_90D_HDD SATA SATA_90D_HDD SATA SATA_90D_HDD SATA SATA_100D SATA SATA_100D SATA SATA_100D SATA SATA_100D SATA SATA_100D SATA SATA_100D SATA SATA_100D SATA SATA_100D SATA SATA_100D SATA SATA_100D SATA SATA_100D SATA SATA_100D SATA SATA_HDD_R2D_C_P SATA_HDD_R2D_C_N SATA_HDD_R2D_P SATA_HDD_R2D_N SATA_HDD_R2D_UF_P SATA_HDD_R2D_UF_N SATA_HDD_D2R_P SATA_HDD_D2R_N SATA_HDD_D2R_C_P SATA_HDD_D2R_C_N SATA_HDD_D2R_UF_P SATA_HDD_D2R_UF_N SATA_ODD_R2D_C_P SATA_ODD_R2D_C_N SATA_ODD_R2D_P SATA_ODD_R2D_N SATA_ODD_R2D_UF_P SATA_ODD_R2D_UF_N SATA_ODD_D2R_P SATA_ODD_D2R_N SATA_ODD_D2R_C_P SATA_ODD_D2R_C_N SATA_ODD_D2R_UF_P SATA_ODD_D2R_UF_N SATA_TERMP MCP_SATA_TERMP 70C3 70C4 70C5 70C3 70C4 70C5 17A3 23C6 17A3 23C6 19D6 37A2 19D6 37A2 6B7 37A5 6B7 37A5 37A4 37A4 19D6 37B2 19D6 37B2 6B7 37B5 6B7 37B5 37B4 37B4 19D6 37C3 19D6 37C3 6B7 37C6 SYNC_MASTER=T18_MLB SYNC_DATE=01/04/2008 MCP Constraints 37C4 DRAWING NUMBER 37C4 Apple Inc 19D6 37C3 19D6 37C3 6B7 37C6 A PAGE TITLE 6A7 6B7 37C6 051-7898 D REVISION C.0.0 R NOTICE OF PROPRIETARY PROPERTY: SIZE BRANCH 6B7 37C6 37C4 37C4 19A6 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED PAGE 102 OF 109 SHEET OF 8 PCI Bus Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP PCI_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD NET_TYPE PHYSICAL ELECTRICAL_CONSTRAINT_SET SPACING TABLE_PHYSICAL_RULE_ITEM MCP_DEBUG PCI_55S PCI PCI_AD PCI_55S PCI PCI_AD24 PCI_55S PCI PCI_AD PCI_55S PCI PCI_AD PCI_55S PCI PCI_C_BE_L PCI_55S PCI PCI_CNTL PCI_55S PCI PCI_CNTL PCI_55S PCI PCI_CNTL PCI_55S PCI PCI_CNTL PCI_55S PCI PCI_CNTL PCI_55S PCI PCI_CNTL PCI_55S PCI PCI_CNTL PCI_55S PCI PCI_REQ0_L PCI_55S PCI PCI_GNT0_L PCI_55S PCI PCI_REQ1_L PCI_55S PCI PCI_GNT1_L PCI_55S PCI PCI_INTW_L PCI_55S PCI PCI_INTX_L PCI_55S PCI PCI_INTY_L PCI_55S PCI PCI_INTZ_L PCI_55S PCI MCP_PCI_CLK2 CLK_PCI_55S CLK_PCI CLK_PCI_55S CLK_PCI LPC_AD LPC_55S LPC LPC_FRAME_L LPC_55S LPC LPC_RESET_L LPC_55S LPC MCP_LPC_CLK0 CLK_LPC_55S CLK_LPC CLK_LPC_55S CLK_LPC CLK_LPC_55S CLK_LPC USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB TABLE_PHYSICAL_RULE_ITEM CLK_PCI_55S * SPACING_RULE_SET LAYER =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD TABLE_SPACING_RULE_HEAD LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM PCI * =STANDARD ? TABLE_SPACING_RULE_ITEM CLK_PCI D * MIL ? SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.8 LPC Bus Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM LPC_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD TABLE_PHYSICAL_RULE_ITEM CLK_LPC_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT MIL ? TABLE_SPACING_RULE_ITEM LPC * TABLE_SPACING_RULE_ITEM CLK_LPC * MIL USB 2.0 Interface Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER 12C3 18D7 D 18D2 18D7 18D2 18D7 ? SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.9.1 ALLOW ROUTE ON LAYER? MCP_DEBUG PCI_AD PCI_AD PCI_AD PCI_PAR PCI_C_BE_L PCI_IRDY_L PCI_DEVSEL_L PCI_PERR_L PCI_SERR_L PCI_STOP_L PCI_TRDY_L PCI_FRAME_L PCI_REQ0_L PCI_GNT0_L PCI_REQ1_L PCI_GNT1_L PCI_INTW_L PCI_INTX_L PCI_INTY_L PCI_INTZ_L MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP PCI_CLK33M_MCP_R PCI_CLK33M_MCP LPC_AD LPC_FRAME_L LPC_RESET_L 18C5 18C5 18B3 40C8 42D3 42D5 18C3 40C8 42D5 18C3 24D4 TABLE_PHYSICAL_RULE_ITEM MCP_USB_RBIAS * =STANDARD MIL MIL =STANDARD =STANDARD =STANDARD TABLE_PHYSICAL_RULE_ITEM USB_90D * =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT =2x_DIELECTRIC ? TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT =4x_DIELECTRIC ? TABLE_SPACING_RULE_ITEM USB C * USB_EXTA TABLE_SPACING_RULE_ITEM USB TOP,BOTTOM SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.10.1 LPC_CLK33M_SMC_R LPC_CLK33M_SMC LPC_CLK33M_LPCPLUS USB_EXTA_P USB_EXTA_N USB_EXTA_MUXED_P USB_EXTA_MUXED_N CONN_USB_EXTA_P CONN_USB_EXTA_N 18B3 24B4 24B1 40C8 24B1 42D3 19D3 38A8 19D3 38A8 38C4 C 38C4 38C3 38C3 SMBus Interface Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP SMB_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD SPACING_RULE_SET LAYER TABLE_PHYSICAL_RULE_ITEM USB_CAMERA TABLE_SPACING_RULE_HEAD LINE-TO-LINE SPACING WEIGHT =2x_DIELECTRIC ? TABLE_SPACING_RULE_ITEM SMB * USB_BT SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.11.1 HD Audio Interface Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP USB_TPAD DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM HDA_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING USB_IR WEIGHT TABLE_SPACING_RULE_ITEM HDA * =2x_DIELECTRIC ? USB_EXTB TABLE_SPACING_RULE_ITEM MCP_HDA_COMP * MIL ? SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.12.1 USB_SD B SIO Signal Constraints USB_CAMERA_P USB_CAMERA_N USB_CAMERA_CONN_P USB_CAMERA_CONN_N USB_BT_P USB_BT_N CONN_USB2_BT_P CONN_USB2_BT_N USB_TPAD_P USB_TPAD_N USB_TPAD_R_P USB_TPAD_R_N USB_IR_P USB_IR_N USB_EXTB_P USB_EXTB_N CONN_USB_EXTB_P CONN_USB_EXTB_N USB_CARDREADER_P USB_CARDREADER_N 19D3 29B5 19D3 29B5 6D5 29B7 6D5 29B7 19D3 29B5 19C3 29B5 6D5 29B7 6D5 29B7 19D3 48B8 19D3 48B8 48B7 48B7 19D3 39D7 19D3 39D7 19C3 38A4 19C3 38B4 38B3 38B3 19C3 30C7 19C3 30C7 B TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM CLK_SLOW_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD MCP_USB_RBIAS_GND MCP_USB_RBIAS MCP_USB_RBIAS SMBUS_MCP_0_CLK SMB_55S SMB SMBUS_MCP_0_DATA SMB_55S SMB SMBUS_MCP_1_CLK SMB_55S SMB SMBUS_MCP_1_DATA SMB_55S SMB SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.13 HDA_BIT_CLK HDA_55S HDA HDA_55S HDA SPI Interface Constraints HDA_SYNC HDA_55S HDA HDA_55S HDA HDA_55S HDA HDA_55S HDA TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM CLK_SLOW * MIL ? TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH =55_OHM_SE =55_OHM_SE MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP HDA_55S HDA HDA_55S HDA HDA_55S HDA HDA_55S HDA HDA_BIT_CLK HDA_BIT_CLK_R HDA_SYNC HDA_SYNC_R HDA_RST_R_L HDA_RST_L HDA_SDIN0 HDA_SDIN_CODEC HDA_SDOUT HDA_SDOUT_R MCP_HDA_COMP MCP_HDA_PULLDN_COMP CLK_SLOW_55S CLK_SLOW CLK_SLOW_55S CLK_SLOW PM_CLK32K_SUSCLK_R PM_CLK32K_SUSCLK SPI_55S SPI SPI_55S SPI SPI_55S SPI SPI_55S SPI SPI_55S SPI SPI_55S SPI SPI_55S SPI SPI_55S SPI SPI_55S SPI SPI_55S SPI SPI_55S SPI SPI_55S SPI SPI_55S SPI DIFFPAIR NECK GAP HDA_RST_L TABLE_PHYSICAL_RULE_ITEM SPI_55S * =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD HDA_SDIN0 TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT HDA_SDOUT TABLE_SPACING_RULE_ITEM SPI * MIL ? MCP_HDA_PULLDN_COMP SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.14 MCP_SUS_CLK SPI_CLK A SPI_MOSI SPI_MISO SPI_CS0 SMBUS_MCP_0_CLK SMBUS_MCP_0_DATA SMBUS_MCP_1_CLK SMBUS_MCP_1_DATA SPI_CLK_R SPI_CLK SPI_ALT_CLK SPI_MOSI_R SPI_MOSI SPI_ALT_MOSI SPI_MISO SPI_MISO_R SPI_ALT_MISO SPI_CS0_R_L SPI_CS0_L SPI_CS1_R_L SPI_CS1_R_L_USE_MLB 19C4 12B6 20C3 43D8 12B6 20C3 43D8 20C3 43B8 20C3 43B8 20D2 52C7 20A7 20D4 20D2 52C7 20A7 20D4 20A7 20D4 20D2 52C7 20D7 52C7 20D2 52C7 20A7 20D4 20C7 20B3 24B4 24B1 40C5 20B3 42A5 42C8 51C5 42C5 42D3 20B3 42A5 42C7 51C4 SYNC_MASTER=T18_MLB SYNC_DATE=12/14/2007 A PAGE TITLE MCP Constraints 42C5 42D5 DRAWING NUMBER 20B3 42A5 42B7 51C4 Apple Inc 42B5 42D5 051-7898 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED D REVISION C.0.0 R 20B3 42B7 NOTICE OF PROPRIETARY PROPERTY: SIZE BRANCH PAGE 103 OF 109 SHEET OF 8 MCP RGMII (Ethernet) Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP MCP_MII_COMP * =STANDARD 7.5 MIL 7.5 MIL =STANDARD =STANDARD =STANDARD NET_TYPE ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING TABLE_PHYSICAL_RULE_ITEM MCP_MII_COMP_VDD MCP_MII_COMP_GND MCP_MII_COMP MCP_MII_COMP MCP_MII_COMP MCP_MII_COMP MCP_CLK25M_BUF0 ENET_MII_55S MCP_BUF0_CLK ENET_MII_55S MCP_BUF0_CLK ENET_INTR_L ENET_MII_55S ENET_MII TABLE_PHYSICAL_RULE_ITEM ENET_MII_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT MCP_CLK25M_BUF0_R RTL8211_CLK25M_CKXTAL1 17C6 17C6 17C3 32A5 31B6 32A3 TABLE_SPACING_RULE_ITEM MCP_BUF0_CLK * =3:1_SPACING ? ENET_MII * 12 MIL ? TABLE_SPACING_RULE_ITEM D SOURCE: MCP73 Interface DG (DG-02974-001_v01), Sections 2.7.2 & 2.7.4 88E1116R (Ethernet PHY) Constraints ENET_MDIO ENET_MII_55S ENET_MII ENET_MDC ENET_MII_55S ENET_MII ENET_PWRDWN_L ENET_MII_55S ENET_MII ENET_MII_55S ENET_MII ENET_MII_55S ENET_MII ENET_MII_55S ENET_MII ENET_RXD ENET_MII_55S ENET_MII ENET_RXD_STRAP ENET_MII_55S ENET_MII ENET_RXD ENET_MII_55S ENET_MII ENET_MII_55S ENET_MII ENET_MII_55S ENET_MII ENET_TXCLK ENET_MII_55S ENET_MII ENET_TXD0 ENET_MII_55S ENET_MII ENET_TXD ENET_MII_55S ENET_MII ENET_TXD ENET_MII_55S ENET_MII ENET_CLK125M_TXCLK_R ENET_CLK125M_TXCLK ENET_TXD ENET_TXD ENET_TX_CTRL ENET_MII_55S ENET_MII ENET_RESET_L ENET_MDI_100D ENET_MDI ENET_MDI_100D ENET_MDI ENET_MDI_100D ENET_MDI ENET_MDI_100D ENET_MDI ENET_MDI_P ENET_MDI_N ENET_MDI_TRAN_P ENET_MDI_TRAN_N ENET_RXCLK TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP ENET_MDI_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT 25 MIL ? TABLE_SPACING_RULE_ITEM ENET_MDI * SOURCE: MCP73 Interface DG (DG-02974-001_v01), Section 2.7.4 ENET_INTR_L ENET_MDIO ENET_MDC ENET_PWRDWN_L ENET_MDI ENET_CLK125M_RXCLK_R ENET_CLK125M_RXCLK ENET_RXD_R ENET_RXD ENET_RXD ENET_RX_CTRL ENET_RXCTL_R 17C3 31B6 17D3 31B6 D 31C4 17D6 31C1 31C4 17D6 31C1 17D6 31C1 17D6 31B1 31B4 31C6 17D3 31C8 17D3 31C6 17D3 31C6 17D3 31B6 17C3 31B7 31B3 33B8 33C8 31B3 33B8 33C8 33B4 33C4 33C5 33B4 33C4 33C5 C C B B A SYNC_MASTER=T18_MLB SYNC_DATE=03/19/2008 A PAGE TITLE Ethernet Constraints DRAWING NUMBER Apple Inc 051-7898 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED D REVISION C.0.0 R NOTICE OF PROPRIETARY PROPERTY: SIZE BRANCH PAGE 104 OF 109 SHEET OF 8 FireWire Interface Constraints FireWire Net Properties TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? NET_TYPE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING TABLE_PHYSICAL_RULE_ITEM FW_110D * =110_OHM_DIFF =110_OHM_DIFF =110_OHM_DIFF =110_OHM_DIFF =110_OHM_DIFF =110_OHM_DIFF FW_P0_TPA FW_110D FW_TP FW_P0_TPA FW_110D FW_TP FW_P0_TPB FW_110D FW_TP FW_P0_TPB FW_110D FW_TP FW_P1_TPA FW_110D FW_TP FW_P1_TPA FW_110D FW_TP FW_P1_TPB FW_110D FW_TP FW_P1_TPB FW_110D FW_TP TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM FW_TP * =3:1_SPACING ? FW_P0_TPA_P FW_P0_TPA_N FW_P0_TPB_P FW_P0_TPB_N FW_P1_TPA_P FW_P1_TPA_N FW_P1_TPB_P FW_P1_TPB_N 34B6 36C4 34C6 36C4 34B6 36C4 34B6 36C4 34B6 36B8 34B6 36B8 34B6 36B8 34B6 36B8 D D Port Not Used SD CARD NET PROPERTIES NET_TYPE ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING SD CARD INTERFACE CONSTRAINTS TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP I23 SD_DATA SD_55S SD_INTERFACE I24 SD_DATA SD_55S SD_INTERFACE I25 SD_DATA SD_55S SD_INTERFACE I26 SD_DATA SD_55S SD_INTERFACE I27 SD_DATA SD_55S SD_INTERFACE I28 SD_DATA SD_55S SD_INTERFACE I29 SD_DATA SD_55S SD_INTERFACE I30 SD_DATA SD_55S SD_INTERFACE TABLE_PHYSICAL_RULE_ITEM SD_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM SD_INTERFACE * =3X_DIELECTRIC ? I32 SD_CLK SD_55S SD_INTERFACE I31 SD_CMD SD_55S SD_INTERFACE SD_D SD_D SD_D SD_D SD_D SD_D SD_D SD_D 30C2 30C2 30C2 30C2 30C2 30C2 30C2 30C2 SD_CLK SD_CMD 30C2 30C2 C C B B A SYNC_MASTER=K19_MLB SYNC_DATE=12/01/2008 A PAGE TITLE FireWire Constraints DRAWING NUMBER Apple Inc 051-7898 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED D REVISION C.0.0 R NOTICE OF PROPRIETARY PROPERTY: SIZE BRANCH PAGE 105 OF 109 SHEET OF 8 SMC SMBus Net Properties TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP NET_TYPE DIFFPAIR NECK GAP ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING TABLE_PHYSICAL_RULE_ITEM 1TO1_DIFFPAIR * =STANDARD =STANDARD =STANDARD =STANDARD 0.1 MM 0.1 MM D SMBUS_SMC_A_S3_SCL SMB_55S SMB SMBUS_SMC_A_S3_SDA SMB_55S SMB SMBUS_SMC_B_S0_SCL SMB_55S SMB SMBUS_SMC_B_S0_SDA SMB_55S SMB SMBUS_SMC_0_S0_SCL SMB_55S SMB SMBUS_SMC_0_S0_SDA SMB_55S SMB SMBUS_SMC_BSA_SCL SMB_55S SMB SMBUS_SMC_BSA_SDA SMB_55S SMB SMBUS_SMC_MGMT_SCL SMB_55S SMB SMBUS_SMC_MGMT_SDA SMB_55S SMB SMBUS_SMC_A_S3_SCL SMBUS_SMC_A_S3_SDA SMBUS_SMC_B_S0_SCL SMBUS_SMC_B_S0_SDA SMBUS_SMC_0_S0_SCL SMBUS_SMC_0_S0_SDA SMBUS_SMC_BSA_SCL SMBUS_SMC_BSA_SDA SMBUS_SMC_MGMT_SCL SMBUS_SMC_MGMT_SDA 6C5 6D5 43D2 6C5 6D5 43D2 43C2 43C2 43D5 43D5 6A7 43C5 6A7 43C5 D 43B5 43B5 SMBus Charger Net Properties NET_TYPE ELECTRICAL_CONSTRAINT_SET PHYSICAL CHGR_CSI 1TO1_DIFFPAIR 1TO1_DIFFPAIR CHGR_CSO 1TO1_DIFFPAIR 1TO1_DIFFPAIR SPACING CHGR_CSI_P CHGR_CSI_N CHGR_CSO_P CHGR_CSO_N C C B B A SYNC_MASTER=T18_MLB SYNC_DATE=01/04/2008 A PAGE TITLE SMC Constraints DRAWING NUMBER Apple Inc 051-7898 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED D REVISION C.0.0 R NOTICE OF PROPRIETARY PROPERTY: SIZE BRANCH PAGE 106 OF 109 SHEET OF 8 K24 SENSOR NET PROPERTIES TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP NET_TYPE DIFFPAIR NECK GAP ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING TABLE_PHYSICAL_RULE_ITEM DIFFPAIR * =STANDARD =STANDARD =STANDARD =STANDARD 0.1 MM 0.1 MM DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR D DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR CHGR_CSO_R_P CHGR_CSO_R_N CPUTHMSNS_D2_P CPUTHMSNS_D2_N CPU_THERMD_P CPU_THERMD_N ISNS_CPUVTT_P ISNS_CPUVTT_N ISNS_P1V5S0MCP_P ISNS_P1V5S0MCP_N ISNS_PVCORES0MCP_P ISNS_PVCORES0MCP_N MCPTHMSNS_D2_P MCPTHMSNS_D2_N MCP_THMDIODE_P MCP_THMDIODE_N 45A8 59B3 45A8 59B3 46C5 46C5 9C6 46D5 9C6 46D5 45B7 45B7 D 6C7 46B5 6C7 46B5 20C3 46B5 20C3 46B5 C C B B A A SYNC_MASTER=M97_MLB PAGE TITLE K24 SPECIAL CONSTRAINTS DRAWING NUMBER Apple Inc 051-7898 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED D REVISION C.0.0 R NOTICE OF PROPRIETARY PROPERTY: SIZE BRANCH PAGE 107 OF 109 SHEET OF 8 K24 BOARD-SPECIFIC SPACING & PHYSICAL CONSTRAINTS TABLE_BOARD_INFO BOARD LAYERS BOARD AREAS BOARD UNITS (MIL or MM) ALLEGRO VERSION TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM NO_TYPE,BGA_P1MM MM 15.5.1 TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT 0.1 MM ? TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET * * BGA_P1MM BGA_P1MM TABLE_SPACING_RULE_ITEM DEFAULT * TABLE_SPACING_RULE_ITEM STANDARD TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP * =DEFAULT ? DEFAULT * Y =50_OHM_SE 0.100MM 30 MM MM MM * Y =DEFAULT =DEFAULT 12.7 MM =DEFAULT =DEFAULT MEM_CLK * BGA_P1MM BGA_P1MM * =DEFAULT ? BGA_P2MM * =DEFAULT ? * BGA_P1MM BGA_P2MM CLK_LPC * BGA_P1MM BGA_P2MM BGA_P3MM MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP * =DEFAULT ? TOP,BOTTOM Y STANDARD TABLE_PHYSICAL_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM CLK_PCI * BGA_P1MM BGA_P2MM CLK_PCIE * BGA_P1MM BGA_P2MM CLK_SLOW * BGA_P1MM BGA_P2MM TABLE_SPACING_ASSIGNMENT_ITEM DIFFPAIR NECK GAP D TABLE_SPACING_RULE_HEAD SPACING_RULE_SET TABLE_PHYSICAL_RULE_ITEM 55_OHM_SE BGA_P1MM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_PHYSICAL_RULE_HEAD MINIMUM LINE WIDTH MEM_40S_VDD TABLE_PHYSICAL_ASSIGNMENT_ITEM BGA_P2MM CLK_FSB TABLE_SPACING_RULE_ITEM LAYER STANDARD TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM PHYSICAL_RULE_SET PHYSICAL_RULE_SET BGA_P1MM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM D AREA_TYPE MEM_40S DIFFPAIR NECK GAP STANDARD ALLOW ROUTE ON LAYER? TABLE_PHYSICAL_ASSIGNMENT_HEAD NET_PHYSICAL_TYPE TABLE_SPACING_ASSIGNMENT_ITEM 0.090 MM LAYER LINE-TO-LINE SPACING WEIGHT 0.090 MM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM 55_OHM_SE * Y 0.076 MM 0.076 MM =STANDARD =STANDARD 1.5:1_SPACING * 0.15 MM ? 2:1_SPACING * 0.2 MM ? TABLE_SPACING_ASSIGNMENT_ITEM FSB_DSTB =STANDARD FSB_DSTB BGA_P1MM BGA_P3MM TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH 50_OHM_SE TOP,BOTTOM Y 0.115 MM 0.115 MM MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP TABLE_SPACING_RULE_ITEM DIFFPAIR NECK GAP 2.5:1_SPACING * 0.25 MM ? 3:1_SPACING * 0.3 MM ? 4:1_SPACING * 0.4 MM ? LINE-TO-LINE SPACING WEIGHT TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM 50_OHM_SE * Y 0.076 MM 0.076 MM =STANDARD =STANDARD =STANDARD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER TABLE_PHYSICAL_RULE_ITEM 40_OHM_SE TOP,BOTTOM Y 0.165 MM 0.100 MM 40_OHM_SE * Y 0.126 MM 0.100 MM =STANDARD =STANDARD =STANDARD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_SPACING_RULE_ITEM 2X_DIELECTRIC TOP,BOTTOM 0.140 MM ? 3X_DIELECTRIC TOP,BOTTOM 0.210 MM ? 4X_DIELECTRIC TOP,BOTTOM 0.280 MM ? 5X_DIELECTRIC TOP,BOTTOM 0.350 MM ? 2X_DIELECTRIC * 0.126 MM ? 3X_DIELECTRIC * 0.189 MM ? 4X_DIELECTRIC * 0.252 MM ? 5X_DIELECTRIC * 0.315 MM ? TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM 27P4_OHM_SE TOP,BOTTOM Y 0.310 MM 0.310 MM 27P4_OHM_SE * Y 0.222 MM 0.222 MM TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM =STANDARD =STANDARD =STANDARD TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM 70_OHM_DIFF * N =STANDARD =STANDARD =STANDARD =STANDARD 70_OHM_DIFF ISL3,ISL4,ISL9,ISL10 Y 0.151 MM 0.100 MM =STANDARD 0.224 MM =STANDARD 0.224 MM 70_OHM_DIFF TOP,BOTTOM Y 0.185 MM 0.100 MM 0.200 MM 0.200 MM PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 90_OHM_DIFF * N =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD 90_OHM_DIFF ISL3,ISL4,ISL9,ISL10 Y 0.095 MM 0.095 MM 0.234 MM 0.234 MM 90_OHM_DIFF TOP,BOTTOM Y 0.112 MM 0.112 MM 0.220 MM 0.220 MM PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 100_OHM_DIFF * N =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD 100_OHM_DIFF ISL3,ISL4,ISL9,ISL10 Y 0.075 MM 0.075 MM 0.244 MM 0.244 MM 100_OHM_DIFF TOP,BOTTOM Y 0.091 MM 0.091 MM 0.230 MM 0.230 MM PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 110_OHM_DIFF * N =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD 110_OHM_DIFF ISL3,ISL4,ISL9,ISL10 Y 0.075 MM 0.075 MM 0.330 MM 0.330 MM TABLE_PHYSICAL_RULE_ITEM C C TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD TABLE_PHYSICAL_RULE_ITEM B B TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM 110_OHM_DIFF TOP,BOTTOM Y 0.077 MM 0.077 MM PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH 1:1_DIFFPAIR * Y =STANDARD =STANDARD 0.330 MM 0.330 MM MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP =STANDARD 0.1 MM 0.1 MM TABLE_PHYSICAL_RULE_HEAD TABLE_PHYSICAL_RULE_ITEM A A SYNC_MASTER=M97_MLB PAGE TITLE K24 RULE DEFINITIONS DRAWING NUMBER Apple Inc 051-7898 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED D REVISION C.0.0 R NOTICE OF PROPRIETARY PROPERTY: SIZE BRANCH PAGE 109 OF 109 SHEET OF ... 73D3 13C6 BI 73D3 13B6 BI 73D3 13B6 BI 73D3 13B6 BI 73D3 13B6 BI 73D3 13B6 BI 73C3 13C6 BI 73C3 13C6 BI 73C3 13C6 BI 73C3 13C6 BI 73C3 13C6 BI 73C3 13C6 BI 73C3 13C6 BI 73C3 13C6 BI 73C3 13C6... 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