8 CK APPD ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5% ALL CAPACITANCE VALUES ARE IN MICROFARADS ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ K36 MLB SCHEMATIC REV ZONE ECN ENG APPD DESCRIPTION OF CHANGE DATE ? ? ? ? DATE ? REFERENCED FROM M70 8/9/2007 D (.csa) Page TABLE_TABLEOFCONTENTS_HEAD TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM C TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM B TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 Date Contents Sync 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 37 Ethernet (Yukon) Yukon Power Control ETHERNET CONNECTOR FIREWIRE CONTROLLER FIREWIRE PORT PATA CONNECTOR SATA CONNECTOR USB EXTERNAL CONNECTORS CONNECTOR MISC IR CONTROLLER & BT INTERFACE SMC SMC SUPPORT 38 39 40 43 44 45 46 47 48 49 50 Page 09/05/2006 Table of Contents System Block Diagram Power Block Diagram CONFIGURATION OPTIONS Revision History FUNC TEST OF Power Aliases SIGNAL ALIAS /RESET CPU FSB CPU Power & Ground CPU Decoupling & VID CPU ITP700FLEX DEBUG NB CPU Interface NB PEG / Video Interfaces NB Misc Interfaces NB DDR2 Interfaces NB Power NB Power NB Grounds NB Standard Decoupling NB Graphics Decoupling SB Enet, Disk, FSB, LPC SB PCI, PCIe, DMI, USB SB Pwr Mgt, GPIO, Clink SB Power & Ground SB Decoupling SB Misc Clock (CK505) Clock Termination DDR2 SO-DIMM Connector A DDR2 SO-DIMM Connector B Memory Active Termination (.csa) TABLE_TABLEOFCONTENTS_ITEM RX RX MK RX RX RX MK RX RX RX RX ES ES ES ES ES ES ES ES ES ES RX RX RX RX RX RX DK DK LD LD LD LT LT LT LT LT LT DK RX LT LT LT LD LD TABLE_TABLEOFCONTENTS_HEAD USB 05/11/2006 WFERRY-WF 06/30/2005 POWER 07/18/2005 SMC N/A N/A 07/25/2005 TP 06/15/2006 WFERRY 07/17/2006 GPU 11/12/2006 T9_MLB_NOME 11/12/2006 T9_MLB_NOME 04/26/2006 MSARWAR 5/23/05 MASTER 10/30/2006 T9_MLB 10/30/2006 T9_MLB 10/30/2006 T9_MLB 10/30/2006 T9_MLB 10/30/2006 T9_MLB 10/30/2006 T9_MLB 10/30/2006 T9_MLB 06/15/2006 WFERRY 06/15/2006 WFERRY 10/30/2006 T9_MLB 10/30/2006 T9_MLB 10/30/2006 T9_MLB 10/30/2006 T9_MLB 06/01/2006 WFERRY 07/26/2005 NB 06/06/2006 DSIMON 06/06/2006 DSIMON-WF 06/20/2005 MEMORY 06/20/2005 MEMORY 06/20/2005 MEMORY 08/19/2005 ENET 10/07/2006 USB 10/07/2006 USB 09/14/2006 USB 08/30/2005 ENET 07/17/2006 GPU 07/17/2006 GPU 07/17/2006 GPU 06/30/2006 USB 06/29/2006 USB 09/05/2006 USB 10/30/2006 T9_MLB 07/17/2006 GPU TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 51 52 53 55 56 59 61 62 66 67 68 69 70 71 72 73 75 76 77 78 79 90 92 94 100 101 102 103 104 105 106 LPC+ Debug Connector SMBUS CONNECTIONS CPU Current & Voltage Sense TEMPERATURE SENSE Fan SMS SPI ROMs AUDIO: CODEC AUDI0: SPEAKER AMP AUDIO: JACK AUDIO: JACK TRANSLATORS DC-In & Battery Connectors S0 FETS & Power Sequencing IMVP6 CPU VCore Regulator Render VCore Supplies 1.5V / 1.05V Supplies 1.8V/0.9V Supplies 5V/3.3V Supplies 3.42V/1.25V Switcher S3 FET & S3/S5 Control PBUS Supply/Battery Charger INVERTER,LVDS,TMDS EXTERNAL TMDS MINI-DVI CONNECTOR CPU/FSB Constraints NB Constraints Memory Constraints SB Constraints (1 of 2) SB Constraints (2 of 2) Clock Constraints FireWire & SMC Constraints TABLE_TABLEOFCONTENTS_ITEM D Date Contents Sync 06/01/2006 LD LD ES ES LD MK RX RX RX RX RX RX MK MK MK MK MK MK MK MK MK MK ES ES ES RX ES LD RX RX DK DVT BUILD A WFERRY 06/01/2006 WFERRY 07/17/2006 GPU 06/21/2006 GPU 11/10/2005 ENET 08/23/2005 SMC 04/26/2006 WFERRY 03/12/2007 M70AUDIO 03/12/2007 M70AUDIO 03/12/2007 M70AUDIO 03/12/2007 M70AUDIO 07/13/2005 POWER 05/31/2006 DSIMON-WF 07/13/2005 POWER 06/29/2006 GPU 07/13/2005 POWER 07/13/2005 POWER 07/13/2005 POWER 12/06/2005 ENET 06/12/2006 DSIMON-WF 08/19/2005 SMC 06/23/2006 GPU 06/06/2005 GRAPHIC 05/21/05 EUGENE 06/08/2006 WFERRY 06/12/2006 WFERRY 06/08/2006 WFERRY 06/12/2006 WFERRY 06/12/2006 WFERRY 06/12/2006 WFERRY 06/12/2006 WFERRY C K36 EE DRIS: RX-RAYMOND XU DK-DINESH KUMAR RC-RAY CHANG MK-MARC KLINGELHOFER LT-LAWRENCE TAN LD-LINDA DUNN MM-MARY(YUAN) MA B DIMENSIONS ARE IN MILLIMETERS APPLE INC METRIC XX X.XX DRAFTER Schematic / PCB #’s PART NUMBER THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING ENG APPD MFG APPD QA APPD DESIGNER RELEASE SCALE I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART ANGLES QTY DESCRIPTION REFERENCE DES CRITICAL 051-7455 SCHEM,MLB,K36 SCH CRITICAL 820-2279 PCBF,MLB,K36 PCB CRITICAL A NOTICE OF PROPRIETARY PROPERTY DESIGN CK X.XXX BOM OPTION TITLE DO NOT SCALE DRAWING SCHEM,MLB,K36 NONE SIZE THIRD ANGLE PROJECTION MATERIAL/FINISH NOTED AS APPLICABLE D DRAWING NUMBER 051-7455 REV SHT 1 01 OF 76 U1000 CPU U2900 CK 505 2.? GHz Core ~1.2V Pg 10 J1302 Pg Clocks TERMS Pg 28 Pg 29 ITP CONN PG 12 FSB D NB-GMCH Core 1.05 - 1.25V Pg 14 TV Out PG 68 RGB MUX PG 57 PG 57-67 DIMM DDR2 - Dual Channel Parallel Term Temp Sense Pg 32 1.8V - 64 Bits 533/667/800? MHz Pg 14 DMI CLnk Pg 15 Pg 15 U5520 PG 49 HEAT-PIPE/FIN U5500 PG 49 U5920 SUDDEN MOTION DETECT PG 51 POWER SENSE PG 69 J9001 PG 48 J5601 U6100/50 FAN CONN PG 50 SPI Boot ROM Int Disp Conn C CPU Pg30,31 Pg 15 Pg 17,18,19 LVDS DVI-I Power Supply Misc GPIO J9401 Pg 15/16 PCI-E SDVO TMDS DC/Batt Conn J3101 J3201 Main Memory Pg 13 U1400 U9200 D J6900/50 64-Bit 800/1066? MHz x4 DMI C PG 54 2.5 GHz PG 67 A B,0 BSA BSB ADC SMC Fan Ser Prt J5100 LPC Conn Pg 23 J4600 UATA SB-ICH8 Pg 24 GPIOs U4800 SATA-2 J4401 SPI Pg 24 SATA SATA-1 PG 40 CLnk U2300 Pg 22 SATA Conn DMI Pg 23 PG 46 PG 44 Pg 22 SATA-0 J4501 LPC U4900 J4850 IR CONTROLLER PG 44 Core 1.05V J4700 J4810 3G Geyser CONNECTOR PG 43 Trackpad/Keyboard PG 42 Bluetooth PG 43 J4601 USB Connectors PG 41 USB PCI-E CAMERA Ln5 Ln6 Core Pg 25 Pg 24 B SMB Pg 23 Ln1 Ln2 Ln3 Ln4 B Pg 23 UATA Pg 22 PG 39 Conn E-NET CLnk PCI AZALIA Pg 22 Pg 24 Pg 23 Pg 22 DIMM’s Clk Gen J3101 U2900 J3201 UC500 33 MHz 32-Bit U6200 U4000 Audio Codec FW32306 Pg 53 Pg 37 System Block Diagram U6600/10/20 JACK TRANSLATORS U3700 A NINEVEH PG 56 Speaker Amps SYNC_MASTER=WFERRY-WF SYNC_DATE=05/11/2006 NOTICE OF PROPRIETARY PROPERTY PG 54 E-NET THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING Pg 34 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT J3400 J4300 J3900 Mini PCI-E AirPort E-NET Conn FireWire Conn Pg 33 Pg 36 PG 38 J6701 INTERNAL MIC J6702/03 INTERNAL SPEAKER J6750/00 LINE IN/OUT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE Audio Conns D PG 55 APPLE INC DRAWING NUMBER SCALE SHT NONE REV 051-7455 OF 76 01 A K36 POWER SYSTEM ARCHITECTURE D6901 02 PPDCIN_G3H VIN D SMC_ENRGYSTR_LDO_EN MAX8719 U7950 SHGN* D7950 V 7A FUSE PPVBAT_G3H_CHGR_REG VOUT SMC PWRGD RN5VD30A-F U5000 (PAGE 45) ENABLE Q5350 PPBUS_G3H D CLOCK VIN 01 AC ADAPTER IN CHGR_EN (S5) U7970 6A FUSE A DCIN ENABLES VIN ENA1 17 1V5S0_RUNSS (S0) ENA2 PGOOD1 ISL6257HRZ U7900 (PAGE 66) U5300 01 02 VOUT ISL9504 3S2P IMVP_VR_ON PGOOD2 19 U7100 (PAGE 59) RC DELAY P3V3S3_EN_L (S3) 12 RESET* U6201 ENA PP4V5_AUDIO_ANALOG VOUT (PAGE 53) PP5V_S3 P25 LOGIC U4900 (PAGE 45) 17 CHGR_EN 02 Q7859 06 P60 07 Q7860 SMC_PM_G2_EN (S5) VIN 5VS5_RUNSS (S5) 3V3S5_RUNSS (S5) Q7859 ENA1 ENA2 07 5V VOUT1 PP1V2_ENET_REG MAX8516 PM_ENET_EN_L VIN PP5V_S5 (7.5A MAX CURRENT) 08 PP3V3_S5_REG VOUT ENA (PAGE 35) CRESTLINE P3V3S3_EN_L 12 18 16 MCH DPLL VIN P1V8S0_EN ENA TPS731125 U2265 (PAGE 21) 18 TPS3808-1.25V MR* U7200 RESET* SENSE (PAGE 58) ADAPTER IN RUNSS_GATE_D 15 S5 S3 VLDOIN 1.8V VOUT1 0.9V VOUT2 R7502 13 PP1V8_S3_REG (10.75A MAX CURRENT) PP0V9_S0_REG TPS51116 U7500 (PAGE 62) UVLO_A GATE A P5VS0_EN 15 PP5V_S0_FET UVLO_B GATE B P3V3S0_EN 15 PP3V3_S0_FET PP1V8_S0_FET 14 02 1V25S0_RUNSS 17 (S0) GFX_VR_EN PM_SLP_S3_L 20 GPU_VCORE U7200 PM_PWRBTN_L SMC_RESET_L SLP_S4_L(P94) SLP_S3_L(P93) U4900 (PAGE 44) Power Block Diagram SYNC_MASTER=POWER UVLO_C UVLO_D ENA* GATE C P1V8S0_EN 15 GATE D RUNSS_GATE_D THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING 15 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE PPVCORE_S0_NB_GFX_IMVP (7.7A MAX CURRENT) SYNC_DATE=06/30/2005 NOTICE OF PROPRIETARY PROPERTY ISL6130IRZA U7000 (PAGE 58) VIN ISL6263 ENA VOUT (PAGE 60) D 21 APPLE INC DRAWING NUMBER REV 051-7455 SCALE SHT NONE 23 RST* PGOOD_1V8S3 Q7006 SOFT START B PP1V8_S3_REG_R 18 14 1V05S0_RUNSS 17 (S0) IMVP_VR_ON(P16) RSMRST_IN(P13) PLT_RST* PWR_BUTTON(P90) P17(BTN_OUT) IMVP_VR_ON SLP_S5_L(P95) PGOOD_1V5S0 PGOOD_1V05S0 Q7007 SOFT START 99ms DLY PGOOD_SEQUENCER VIN 17 PWRGD(P12) 10-1 SLP_S4_L 19 12 Q7007 1V5S0_RUNSS (S0) : SLP_S3_L PM_SLP_S3_L A 05 04-1 1V8S3_RUNSS SOFT START 09 RSMRST_PWRGD SLP_S5_L PM3V3ENET_SS 02 Q7006 ALL_SYS_PWRGD PM_RSMRST_L RST* 16 PP1V5_S0_REG 15 RSMRST_OUT(P15) SMC_ONOFF_L PM_ENET_EN_L U7870 10 SMC 22 P1V25_S0_NB_DPLL WOL_EN SMC_ADAPTER_EN 30 FSB_CPURST_L U1400 (PAGE 13) BATTERY ONLY: VOUT 15 Q3802 16 P3V3S0_EN 15 Q3810 P3V3_ENET_FET 17 U3820 PP1V9_ENET_REG ENA VOUT (PAGE 35) PP1V25_S0_FET Q7001 HCPURST* 1.9V S3 TPS79501DRB VIN PP3V3_ENET_FET PP3V3_S0_FET P1V8_S0_FET PWROK 13 PP3V3_S3 Q7004 PP1V25_S0_REG PP3V3_S5 14 Q3801 15 VOUT (PAGE 64) Q7866 09 18 ENA VREG3 RSMRST_PWRGD 17-1 PP5V_S5_REG 1.25V S0 TPS62510 1V25S0_RUNSS 12 U7720 08 TPS51120 U7600 (PAGE 63) 1.2V YUKON VIN U3830 B P5VS3_EN_L 3.3V VOUT2 (5A MAX CURRENT) PGOOD1,2 PP3V3ENET_SS U1000 (PAGE 9) 17-1 VIN 13 SMC PM_S4_STATE_L PM_SLP_S4_L C PWRGOOD 16 4.5V AUDIO TPS79501 15 Q7865 PM_SLP_S3_L CPU Q7000 12 P5VS3_EN_L (S3) 28 U2300 (PAGE 22) 25 U2801 P5VS0_EN RC DELAY CPU_PWRGD PWROK CPUPWRGD(GPIO49) 24 29 RSMRST* 26 VR_PWRGOOD_DELAY PPBUS_G3H 11 Q7860 PLT_RST_L PM_SB_PWROK PP5V_S0_FET ICH 06-1 PWRBTN* VRMPWRGD 27 SMC_CPU_VSENSE VR_PWRGOOD_DELAY PGOOD CK_PWRGD PLTRST* 19 VR_ON 23 BATT_POS_F 18 VR_PWRGD_CK505_L CLKEN# SLG8LP537V U2900 (PAGE 28) U2803 VR_PWRGD_CK505 A SMC_CPU_ISENSE PPVCORE_CPU_S0 (36A MAX CURRENT) CPUVCORE VIN V PWRGD CLK_PWRGD PP1V05_S0_REG_R ICH8M PGOOD_1V5S0 PGOOD_1V05S0 A SMC_DCIN_ISENSE C 1.5VVOUT2 18 R7302 PP1V05_S0_REG (8A MAX CURRENT) PP1V5_S0_REG (4A MAX CURRENT) VOUT1 TPS51124 U7300 (PAGE 61) SMC_BATT_ISENSE PBUS CONVERTER/ BATTERY CHARGER BATTERY 1.05V 17 1V05S0_RUNSS (S0) U7975 VOUT 04 SMC_RESET_L 02 (PAGE 66) 03 3.425V G3HOT PP3V42_G3H_REG LT3470 U7790 (PAGE 64) PBUSB_VSENSE ENRGYSTR LDO OF 76 01 A PAGE_BORDER=TRUE Page Notes Power aliases required by this page: (NONE) Signal aliases required by this page: (NONE) BOM OPTION BOM options provided by this page: (NONE) BOMOPTION D K36 GOOD 630-9104 EVT IC,MDC,SR,E1,2.0G,800FSB,4M,BGA U1000 CRITICAL GOOD 337S3500 IC,MDC,SR,G0,2.2G,800FSB,4M,BGA U1000 CRITICAL BETTER 337S3500 IC,MDC,SR,G0,2.2G,800FSB,4M,BGA U1000 CRITICAL BEST TABLE_5_ITEM TABLE_5_ITEM BOM OPTION REMOVED BOM OPTION REMOVED - 0.031 - 0.031 BOM TABLE FOR HF POSCAPS 0.07 L7-L8 L8 BOM OPTION REMOVED BOM OPTION REMOVED REMOVED 0.076 POWER TABLE_5_ITEM 337S3463 REMOVED > L7 >> BOM OPTION >> L6-L7 CRITICAL - C > POWER > L6 0.014 0.07 > L5-L6 >>> 0.076 GND >> > L5 0.079 0.014 > L4-L5 >> Speed) Speed) SIGNAL >> REFERENCE DESIGNATOR(S) 0.156 L3-L4 L4 0.079 0.014 > DESCRIPTION SIGNAL >> QTY 0.076 >> L3 - 0.014 > L2-L3 TABLE_5_HEAD PART# 0.07 GROUND >> L2 0.1 D > L1-L2 0.018 0.047 >> CONFORMAL_COAT L1 SIGNAL(TOP) TRACE WIDTH (MM) BOM OPTION REMOVED > Speed) Speed) THICKNESS (MM) BOM OPTION REMOVED BOM OPTION REMOVED > MLB STACKUP LAYER BOM OPTION REMOVED REMOVED > SIGNAL GROUND SIGNAL(High SIGNAL(High GROUND POWER POWER GROUND SIGNAL(High SIGNAL(High GROUND SIGNAL REMOVED > C Top 10 11 BOTTOM M70 GOOD 630-7935 CONCEPT >> >> >> BOARD STACK-UP AND CONSTRUCTION K36 BEST 630-9106 EVT >> >> >> COMMON ALTERNATE ARB_ONLY K36 LPCPLUS INVERTER_BUF BOM OPTION INVERTER_UNBUF BOM OPTION ITP NO_REBOOT_MODE NBCFG_DMI_REVERSE NBCFG_DMI_X2 NBCFG_DYN_ODT_DISABLE NBCFG_PEG_REVERSE NBCFG_SDVO_AND_PCIE GOOD BETTER BEST K36_PGM YUKON_EC YUKON_ULTRA NORMAL FANCY STANDOFF ODD_PWR_CORE ODD_PWR_RESUME ISL6126 BOM OPTION BOM OPTION ISL6130 K36 BETTER 630-9105 EVT GROUND - 0.014 TABLE_5_HEAD PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION TABLE_5_ITEM L8-L9 B TABLE_5_HEAD PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION CRITICAL K36 TABLE_5_ITEM 343S0448 IC,CRESTLINE,GM965,667 U1400 L9 0.076 SIGNAL L9-L10 HF VERSION OF 128S0057 C4610,C4611,C6830,C6831 CRITICAL K36 128S0164 HF VERSION OF 128S0073 C2130,C2716,C7543 CRITICAL K36 128S0148 HF VERSION OF 128S0085 C6605 CRITICAL K36 128S0169 HF VERSION OF 128S0111 C7220,C7352,C7542 CRITICAL K36 128S0160 HF VERSION OF 128S0113 C2173,C2700 CRITICAL K36 128S0150 HF VERSION OF 128S0115 CRITICAL K36 128S0157 HF VERSION OF 128S0122 C2220 CRITICAL K36 128S0162 HF VERSION OF 128S0123 C2140 CRITICAL K36 128S0135 HF VERSION OF 128S0129 C6601,C6603 CRITICAL K36 TABLE_5_ITEM 0.156 TABLE_5_ITEM TABLE_5_ITEM 338S0434 IC,ICH8,BGA U2300 CRITICAL K36 TABLE_5_ITEM 516-0162 IN-LINE SODIMM CONNECTOR J3101,J3201 CRITICAL TABLE_5_ITEM L10 SIGNAL 0.1 0.014 TABLE_5_ITEM K36 L10-L11 L11 GROUND 0.076 TABLE_5_ITEM 0.1 0.014 C6204,C6205,C7651,C7652,C7691,C7692 TABLE_5_ITEM TABLE_5_HEAD PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION TABLE_5_ITEM 341S2196 IC,16MBIT 8PIN SPI SERIAL FLASH,SOIC8 U6100 CRITICAL K36_PGM 341S2060 IC,EEPROM,SERIAL IIC,8KBIT,SO8 U3780 CRITICAL K36_PGM TABLE_5_ITEM TABLE_5_ITEM 341S2198 IC,SMC,HS8/2116 U4900 CRITICAL K36_PGM 341S2093 IC,CYPRESS,CY7C63833,ENCORE_II,USB_CONTR U4800 CRITICAL K36_PGM B TABLE_5_ITEM 0.1 0.014 128S0147 TABLE_5_ITEM L11-L12 0.07 L12 SIGNAL(BOTTOM)0.047 0.018 CONFORMAL_COAT 0.1 TABLE_5_ITEM TOTAL LOCKED BOOTROM PN 341S2197 1.276 - TABLE_5_HEAD CRITICAL BOM OPTION 826-4393 PART# QTY DESCRIPTION LBL,P/N LABEL,PCB,28MMX6MM REFERENCE DESIGNATOR(S) EEE:Z55 CRITICAL GOOD 826-4393 LBL,P/N LABEL,PCB,28MMX6MM EEE:Z56 CRITICAL BETTER TABLE_5_ITEM CONFIGURATION OPTIONS TABLE_5_ITEM TABLE_5_ITEM A 826-4393 LBL,P/N LABEL,PCB,28MMX6MM EEE:Z57 CRITICAL SYNC_MASTER=SMC SYNC_DATE=07/18/2005 BEST NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE D APPLE INC DRAWING NUMBER SCALE SHT NONE REV 051-7455 OF 76 01 A Revision History - WAKE-ON-WIRELESS SUPPORT - RADAR: 4954357 - ADD ISOLATION BUFFER FOR ODD_RESET_L SIGNAL, ADD 100K PULL-DOWN TO ODD_PWR_EN_L, ADD ’DRAG’ CIRCUIT TO PROPERLY DISCHARGE ODD POWER WHEN IT’S TURNED OFF - RADAR: 4923903 - ADD 270K PULL-DOWN RESISTOR ON HTPLG - RADAR: 4888755 - LOWER RDS(ON) MOSFET (FDC606P - APN: 376S0552) FOR ODD AND LCD POWER - RADAR: TBD - HIGH-PRECISION 0.1% RESISTORS TO INCREASE OUTPUT VOLTAGE REGULATION (5V, 3.3V, PBUS_LDO) ACCURACY - RADAR:4972500 - FIX LINDA CARD POWER ALIAS (NEED TO CONNECT TO PP3V42_G3HOT INSTEAD OF PP3V3_S5) - RADAR: 4927858 - FIX MOJO-CARD SMC TX, RX REVERSAL - RADAR: 4910888 - NO STUFF 3G CONNECTOR CIRCUITRY - CHANGE BOM STUFFING TO SPEED UP PORT POWER SHUT-OFF RESPONSE TIME DURING ACTIVE LATE-VG EVENT (RADAR: 4985252) - CHANGE BOM STUFFING TO ENABLE ON-BOARD MICROPHONE CONNECTOR (M42/M42A SOLUTION) INSTEAD OF ROUTING MICROPHONE THROUGH LVDS CABLE - CHANGE LOAD CAP STUFFING OPTION FOR RTC AND ETHERNET CRYSTALS TO MEET 5XESR (-R) REQUIREMENT - CHANGE 10UF, 16V CPU VCORE CAPS TO 10UF, 6.3V CAPS - RADAR: 4952553 - MOVE SMC RESET BUTTON PAD TO TOP SIDE OF MLB - RADAR: 4920913 - MODIFY FIREWIRE CONNECTOR SYMBOL TO SUPPORT MINI-DVI CONNECTOR WITH TAB - TEST POINT MOVEMENTS REQUESTED BY ICT AND MAC-1 GROUPS - RADAR: 4924481 M70 EVT TO DVT CHANGES 3/8/2007 CSA PAGE 22: - 4986074 CHANGE L2205 TO R2205(100OHM,5%,1/10W,0603) CSA PAGE 25: - 4924443 CHANGE R2514 FROM 100K PULL-DOWN TO 10K PULL-UP TO 3.3V_S5 CSA PAGE 77: - 5048817 SYNC 1P25V REGULATOR CIRCUIT FROM M82, CHANGE R AND C TO 0402, CHANGE =PP3V3_S5_P1V25S0 TO =PP3V3_S5_1V25S0, C7723 FROM 2.2NF TO 10000PF, C7724 FROM 22PF TO 100PF, C7728 FROM 2.2NF TO 10000PF, AND REVERT REFERENCE DESIGNATORS (CHANGE FROM TPS62510 TO LTC3412A) 3/12/2007 CSA PAGE 25: - 4924443 CHANGE R2514 FROM 100K PULL-UP TO 47K PULL-UP CSA PAGE 45: - UPDATE SYMBOL FOR J4501 CSA PAGE 62,66,67,68: - SYNC FROM AUDIO TEAM CSA PAGE 94: - 4986074 CHANGE R9469 FOR CRT_TVO_IREF FROM 1.3K TO 1.21K C 7/17/2007 CSA PAGE 59: - UPDATE SYMBOL FOR U5930, VENDOR PART NUMBER CHANGES FROM SMB380 TO BMA150 6/29/2007 CSA PAGE 4: - CHANGE GOOD CPU FROM 337S3471(1.8G) TO 337S3463(2.0G) - CHANGE BETTER CPU FROM 337S3456(2.0G) TO 337S3464(2.2G) - CHANGE BEST CPU FROM 337S3457(2.2G) TO 337S3465(2.4G) - CHANGE NB FROM 338S0426(500M) TO 343S0448(667M) - CHANGE SB FROM 338S0427 TO 338S0434 CSA PAGE 16: - DISCONNECT GFX_VID TO GND - CONNECT GFX_VID TO GFX_VID0:3 ON NB - ADD R1600 (0OHM, 0402) TO CONNECT GFX_VID TO GND CSA PAGE 22: - 5282756 ADD C2207 (0.1UF, 0402) - SIZING DOWN R2205 FROM 0603 TO 0402 FOR PLACEMENT - CHANGE GFX_VID TO GFX_VID - CHANGE STRAPPING FROM 0010 ON GFX_VID TO 0001 ON GFX_VID CSA PAGE 39: - CHANGE J3900 FROM 514S0143 TO 514-0443 - EDIT BOM OPTION TABLE CSA PAGE 46: - CHANGE U4600 FROM 353S1245 TO 353S1728 - REMOVE MIN_NECK_WIDTH=0.3MM FROM PP5V_S3_USB2_EXTA/B - ADD NOSTUFF R4660 AND R4661 CSA PAGE 47: - CHANGE J4700 FROM 516S0251 TO 516S0588 CSA PAGE 69: - CHANGE J6900 FROM 518S0287 TO 518S0526 - REPLACE BATTERY INTERFACE CIRCUIT WITH THE ONE ON M42B ESTAR CSA PAGE 94: - 5040728 CHANGE L9404 FROM 155S0303 TO 155S0348 7/5/2006 CSA PAGE 4: - REPLACE ALL M70 WITH K36 (TEXT, BOM OPTIONS, 630 NUMBERS) CSA PAGE 21: - CHANGE C2173 FROM 128S0051 TO 128S0113 PER CE CSA PAGE 27: - CHANGE C2700 FROM 128S0051 TO 128S0113 PER CE CSA PAGE 28: - CHANGE J2800 FROM 518S0487 TO 518S0519 CSA PAGE 46: - REMOVE R4660 AND R4601 (U4675 BYPASS RESISTORS) CSA PAGE 48: - CHANGE J4810 FROM 518S0369 TO 518S0521 CSA PAGE 55: - CHANGE U5500 FROM M70 EMC1033 CIRCUIT TO M71 EMC1043 CIRCUIT - J5550 CHANGES FROM 2PIN TO 4PIN CSA PAGE 56: - CHANGE J5601 FROM 518S0369 TO 518S0521 CSA PAGE 67: - CHANGE J6702 FROM 518S0487 TO 518S0519 - CHANGE J6703 FROM 518S0369 TO 518S0521 CSA PAGE 90: - CHANGE J9000 FROM 518S0369 TO 518S0521 7/6/2006 CSA PAGE 8: - REMOVE NO_TEST=TRUE FOR 1V8S3_COMP, 1V8S3_FSET, 3V3S5_COMP, 3V3S5_FSET, 1V05S0_COMP, 1V05S0_FSET, IMVP6_RBIAS, IMVP6_COMP, 5VS5_RUNSS, 1V5S0_RUNSS - REMOVE NO_TEST=TRUE FOR CK505_PCI4_CLK_SPN, CK505_SRC1_N/P_SPN, CK505_SRC3_N/P_SPN, CK505_SRC7_N/P_SPN, CK505_SRC_CLKREQ1/3_L?SPN - ADD FUNC_TEST=TRUE FOR THRM_FINSTACK_P/N - ADD FUNC_TEST=TRUE FOR PP1V05_S0_R CSA PAGE 9: - REMOVE ALIASES FOR GND_CHASSIS_AUDIO_SPKRCONN,GND_CHASSIS_AUDIO_SHIELD1,GND_CHASSIS_AUDIO_SHIELD2,GND_CHASSIS_AUDIO_SHIELD3,MIC_SHIELD_LVDS_R,MIC_SHLD_CONN - REMOVE ALIAS FOR =FWPWR_PWRON - ADD SPN ALIASES FOR TP_CK505_SRC7_N/P - ADD SPN ALIASES FOR CK505_PCI2/4_CLK CSA PAGE 12: - REMOVE R1290 TO R1296 ON CPU_VID CSA PAGE 13: - DELETE TEXT NOTE AND WITH RESET BUTTON CSA PAGE 15: - RENAME LVDS_VREFH/L TO TP_LVDS_VREFH/L CSA PAGE 25: - ADD R2597 AND R2596 FOR 10K PU ON GPIO6 AND GPIO17(EXTGPU_RST_L) - CHANGE R2514 TO 100K CSA PAGE 29: - CHANGE L2902 AND L2903 FROM 155S0302 TO 0OHM R2906 AND R2907 - NOSTUFF C2907, C2910, C2916, C2911, C2914 - CHANGE R2900, R2901 FROM 2.2OHM TO 0OHM - CHANGE R2902 FROM 1OHM TO 0OHM CSA PAGE 44: - REMOVE TEXT NOTE WILL CHANGE TO 606P CSA PAGE 53: - RE-DRAW CPU VOLTAGE SENSE RC FILTERING CSA PAGE 62: - RE-CONNECTED /SHDN INPUT OF U6801 SO THAT IT’S CONTROLLED BY U6200 PORTA VREF - DISCONNECTED GPIO1 AND TERMINATED IT WITH A 10K PULL DOWN - ADDED A NO STUFF PULL-UP TO CODEC_DVDD AT GPIO1 - ADDED SMALL 15PF COMPENSATION CAP TO U6201 FEEDBACK NETWORK (C6224) CSA PAGE 67: - CHANGED ALL TRANSIENT SUPPRESSORS TO 6.8V/100PF DEVICES (WERE ORIGINALLY 8V/100PF DEVICES) - ADDED L6771 AND L6773 TO MIC INPUT EMI FILTER - REMOVED DZ6772 - ADDED R6740 NO STUFF CSA PAGE 68: - CONNECTED MIC_SHLD_CONN TO GND_CHASSIS_AUDIO_MIC THROUGH R6854 - ADDED R6856 NO STUFF CSA PAGE 71: - RENAME CPU_VID_R TO CPU_VID D 7/13/2007 CSA PAGE 4: - CHANGE BEST CPU FROM 337S3465(2.4GHZ) TO 337S3464(2.2GHZ) CSA PAGE 38: - CHANGE C3831 AND C3832 FROM 138S0582 TO 138S0554 (DON’T NEED LOW-PROFILE PARTS) M70 DVT TO K36 CHANGES A 7/12/2007 CSA PAGE 43: - CHANGE J4300 FROM 514-0289 TO 514-0456 (SAME JEDEC) - UPDATE BOM OPTION TABLE FOR J4300 - NORMAL CHANGES FROM 514-0359 TO 514-0456, FANCY CHANGES FROM 514-0316 TO 514-0476 CSA PAGE 46: - CHANGE J4600 AND J4601 FROM 514-0288 TO 514-0457 (DIFFERENT JEDEC, SAME LANDPATTERN) - UPDATE BOM OPTION TABLE FOR J4600 AND J4601 - NORMAL CHANGES FROM 514-0288 TO 514-0457, FANCY CHANGES FROM 514-0315 TO 514-0477 CSA PAGE 62: - ADD PAGE_TITLE AUDIO: CODEC CSA PAGE 67: - CHANGE J6700 FROM 514-0409 TO 514-0459 (DIFFERENT JEDEC, SAME LANDPATTERN) - UPDATE BOM OPTION TABLE FOR J6700 - NORMAL CHANGES FROM 514-0409 TO 514-0459, FANCY CHANGES FROM 514-0411 TO 514-0479 - CHANGE J6750 FROM 514-0408 TO 514-0458 (DIFFERENT JEDEC, SAME LANDPATTERN) - UPDATE BOM OPTION TABLE FOR J6750 - NORMAL CHANGES FROM 514-0408 TO 514-0458, FANCY CHANGES FROM 514-0410 TO 514-0478 CSA PAGE 79: - CHANGE L7900 FROM 152S0302 TO 152S0670 FOR CORRECT AVL CSA PAGE 94: - UPDATE BOM OPTION TABLE FOR J9401 - NORMAL CHANGES FROM 514-0375 TO 514-0480, FANCY CHANGES FROM 514-0376 TO 514-0481 3/14/2007 CSA PAGE 47: - ADD TEXT NOTE TO UPDATE J4700 FROM 516S0251 TO 516S0588 WHEN SYMBOL IS READY CSA PAGE 69: - ADD TEXT NOTE TO UPDATE J6900 FROM 518S0287 TO 518S0526 WHEN SYMBOL IS READY CSA PAGE 90: - DELETE LVDS_VREFH AND LVDS_VREFL TO GROUND TO FIX LVDS GLITCH CSA PAGE 94: - ADD TEXT NOTE TO CHANGE L9404 FROM 155S0303 TO 155S0348 WHEN SYMBOL IS READY B 7/11/2007 CSA PAGE 9: - CHANGE Z0901 AND Z0906 FROM 998-1178 TO 998-1186 (NON-PLATED) CSA PAGE 31: - STUFF C3110 AND C3111 CSA PAGE 32: - STUFF C3210 AND C3211 CSA PAGE 39: - UPDATE PN FOR FANCY RJ45 CONNECTOR, 514-0475 CSA PAGE 50: - REMOVE R5077 (BECOMES R5931) CSA PAGE 59: - ADD R5930, 10K PU ON SMC_SMS_INT - ADD R5931 (WAS R5077 BEFORE), 10K PD ON SMC_SMS_INIT - STUFF U5930 (DIGITAL ACCELEROMETER) CIRCUIT 3/5/2007 CSA PAGE 8: - 4954357 ADD =PP3V3_S3_AIRPORT_AUX BACK TO PP3V3_S3 ALIAS CSA PAGE 34: - 4954357 BREAK OUT =PP3V3_S3_AIRPORT_AUX(J3400,PIN 24) FROM PP3V3_S3_AP_AUX AGAIN - 4954357 MOVE C3409 AND C3410 FROM PP3V3_S3_AP_AUX RAIL TO =PP3V3_S3_AIRPORT_AUX RAIL CSA PAGE 49: - 5040728 STUFF C9421 FOR EMI CSA PAGE 62,66,67,68: - SYNC FROM AUDIO TEAM CSA PAGE 67: - 4999533 SWAP PIN AND PIN OF MIC CONNECTOR, BACK TO M42 PIN OUT CSA PAGE 79: - 5029811 CHANGE Q7940 FROM 376S0326 TO 376S0558 C 7/10/2007 CSA PAGE 4: - BOOTROM PART NUMBER CHANGES FROM 341S2085 TO 341S2196 - SMC PART NUMBER CHANGES FROM 341S2088 TO 341S2198 - UPDATE EEE CODES, Z55 FOR GOOD, Z56 FOR BETTER, Z57 FOR BEST CSA PAGE 8: - ADD ALIAS =PP3V3_S3_SMBUS_SMC_MGMT TO PP3V3_S3 CSA PAGE 29: - ADD CRITICAL TO U2900 CSA PAGE 44: - ADD CRITICAL TO U4401 CSA PAGE 46: - CHANGE U4675 FROM APN 353S1505 TO APN 353S1742 (SMALL PACKAGE) - ADD R4670 & R4671 (USB BYPASS ROUTING) CSA PAGE 49: - REMOVE ALIAS FOR =SMC_SMS_INT TO SMC_PG1 - SIGNAL SHOULD JUST BE CALLED SMC_SMS_INT CSA PAGE 50: - CHANGE R5077 FROM PULL-UP TO A PULL-DOWN RESISTOR AND NAME IT SMC_SMS_INT CSA PAGE 52: - ICH8-M ME SMBUS: - SMB_ME_CLK AND SMB_ME_DATA ON SOUTHBRIDGE DISCONNECTED FROM SMB_MGMT_CLK AND SMB_MGMT_DATA FROM SMC.B - THE 10K PULL-UP RESISTORS (R5230 AND R5231), AND STILL REMAIN CONNECTED TO PP3V3_S5_SMBUS_SB_ME AND STAY ON THE SB SIDE - SMC MANAGEMENT SMBUS CONNECTION: - ADD TWO NEW 10K PULL-UP RESISTOR (R5232 & R5233) TO =PP3V3_S3_SMBUS_SMC_MGMT.B - THE PULL-UP RESISTORS SHOULD BE CONNECTED BETWEEN SMB_MGMT_CLK AND SMB_MGMT_DATA TO =I2C_SMS_SCL AND =I2C_SMS_SDA OF THE NEW ACCELEROMETER CSA PAGE 59: -ADD 2ND SMS (U5930) CSA PAGE 62: - CHANGED C6210 FROM A CASE-R 10UF TANT CAP TO A SMA-LF 3.3UF TANT CAP - MADE NO_TEST ATTRIBUTE VISIBLE FOR NET NC_VRP CONNECTED TO PIN 37 OF U6200 CSA PAGE 67: - REMOVED NO STUFF RESISTORS R6730, R6731, AND R6732 ALSO REMOVED L6774 - STUFFED R6740 - MADE DZ6702, DZ6703, DZ6704, DZ6705, DZ6752, DZ6753, DZ6754, DZ6755, DZ6770, DZ6771B CRITICAL CSA PAGE 68: - NO STUFFED R6854 CSA PAGE 72: - CHANGE R7208 FROM 8.66K TO 15.8K M70 PROTO TO EVT CHANGES D 7/24/2007 CSA PAGE 4: - CHANGE BETTER AND BEST CPU TO G0 STEPPING PARTS (FROM 337S3464 TO 337S3500) CSA PAGE 22: - STUFF R2242 AND NOSTUFF R2247 CSA PAGE 92: - CHANGE R9201 AND R9202 FROM 5.23K TO 2.94K - CHANGE R9211 AND R9212 FROM 16.5K TO 9.09K M70 EVT TO DVT CHANGES 8/9/2007 PER CE, ALL SANYO POSCAPS HAVE NEW HF PART NUMBERS - ALL 128S0057 BECOME 128S0147 - ALL 128S0073 BECOME 128S0164 - ALL 128S0085 BECOME 128S0148 - ALL 128S0111 BECOME 128S0169 - ALL 128S0113 BECOME 128S0160 - ALL 128S0115 BECOME 128S0150 - ALL 128S0122 BECOME 128S0157 - ALL 128S0123 BECOME 128S0162 - ALL 128S0129 BECOME 128S0135 - ADD OMIT TO ALL ABOVE PARTS SO THE HF PARTS IN BOM TABLE TAKE OVER CSA PAGE 4: - ADD BOM OPTION TABLE FOR ALL SANYO POSCAP TO USE HF PARTS B Revision History SYNC_MASTER=N/A SYNC_DATE=N/A NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE D APPLE INC DRAWING NUMBER SCALE SHT NONE REV 051-7455 OF 76 01 A Functional Test Points Power Supply NO_TESTs Fan Connectors NO_TEST IMVP6_RBIAS IMVP6_COMP 5VS5_RUNSS 1V5S0_RUNSS I93 I94 I95 I96 59A4 59B7 59A4 59B7 I12 I15 63B5 65C5 I16 58B1 61B5 I157 D I158 I159 FUNC_TEST =PP5V_S0_FAN_RT TRUE FAN_RT_PWM TRUE FAN_RT_TACH TRUE =PP3V3_S0_FAN_RT TRUE SMC_FAN_1_CTL TRUE SMC_FAN_1_TACH TRUE Battery Digital Connector 7A7 50C4 I1 50B3 I3 50C3 I4 CLOCK NO_TESTS I111 I112 I113 I115 I114 I116 I117 I118 I119 I120 I122 NO_TEST TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE I19 I18 CK505_CPU0_N CK505_CPU0_P CK505_CPU1_N CK505_CPU1_P CK505_CPU2_ITP_SRC10_N CK505_CPU2_ITP_SRC10_P CK505_DOT96_27M_N CK505_DOT96_27M_P CK505_LVDS_N CK505_LVDS_P I17 28C4 29D6 75D3 I71 28C4 29D6 75D3 I72 28C4 29D6 75D3 I73 28C4 29D6 75D3 I74 28C4 29D6 75D3 I75 28C4 29D6 75D3 I76 28A4 29B6 75D3 I77 28A4 29B6 75D3 I78 28B4 29C6 75C3 I79 28B4 29C6 75D3 CK505_PCIF1_CLK I80 I81 28B6 29B6 75D3 I82 I83 C I125 I183 TRUE TRUE CK505_SRC2_N CK505_SRC2_P I84 28B4 29C6 75C3 I85 28B4 29C6 75C3 I86 I87 I186 I187 I188 I189 I190 I191 I194 I195 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE CK505_SRC4_N CK505_SRC4_P CK505_SRC5_N CK505_SRC5_P CK505_SRC6_N CK505_SRC6_P CK505_SRC8_N CK505_SRC8_P I88 28B4 29C6 75C3 I89 28B4 29C6 75C3 I91 28B4 29C6 75C3 I90 44A8 50B4 I177 44A8 50C4 I180 28B4 29C6 75C3 28A4 29B6 75C3 I201 B I202 I203 I204 I205 I206 I207 I208 FW_B_TPA_N_SPN FW_B_TPA_P_SPN FW_B_TPBIAS_SPN FW_B_TPB_N_SPN FW_B_TPB_P_SPN FW_C_TPA_N_SPN FW_C_TPA_P_SPN FW_C_TPBIAS_SPN FW_C_TPB_N_SPN FW_C_TPB_P_SPN I92 I152 8D1 I155 8D1 8D1 8D1 I153 8D1 I154 8D1 I156 8D1 8D1 8D1 I160 8D1 I161 LVDS NO_TESTS I209 I210 I211 I212 I213 I214 I215 NO_TEST TRUE TRUE TRUE TRUE TRUE TRUE TRUE I244 I162 I163 LVDS_B_CLK_N_SPN LVDS_B_CLK_P_SPN LVDS_B_DATA_N0_SPN LVDS_B_DATA_N1_SPN LVDS_B_DATA_N2_SPN LVDS_B_DATA_P1_SPN LVDS_B_DATA_P2_SPN I164 8D5 I169 8D5 I166 8D5 I167 8D5 I168 8D5 I174 8D5 I171 I173 I175 I176 I178 I181 I223 A I236 NO_TEST TRUE I11 7B1 46C6 7A7 46C6 22D4 44C8 46C6 22D4 44C8 46C6 22D4 44C8 46B6 24C8 37A5 44C5 46B6 23B5 46B6 I10 I21 I22 I24 I23 I25 I45 44B5 45C5 46B6 27D1 46B6 I29 44C1 46B6 I32 44B5 45C5 46B6 I31 44D1 46B6 I33 41A8 44B8 44C5 45D5 46B6 I36 46C5 I38 BATT_POS BATT_NEG TRUE TRUE 57A5 D 57B5 57A5 Audio FUNC_TEST =PP5V_S0_AUDIO_AMP TRUE =PP5V_S0_AUDIO TRUE GND_AUDIO_AMP TRUE GND_AUDIO_CODEC TRUE ACZ_SDATAIN TRUE ACZ_SDATAOUT TRUE ACZ_BITCLK TRUE ACZ_RST_L TRUE ACZ_SYNC TRUE Battery FUNC_TEST SMC_BATT_ISET TRUE SMC_BATT_CHG_EN TRUE SMC_BC_ACOK TRUE SMC_ADAPTER_EN TRUE SMC_BATT_TRICKLE_EN_L TRUE SYS_ONEWIRE TRUE 7A7 54B8 54C8 54D8 7A7 53A7 56C4 8A4 8B4 8A5 53C7 8A5 53C7 8A5 53C7 8A5 53B7 8A5 53C7 44B5 66A8 44C8 45B6 66A4 66A6 44C5 45B6 57C3 57C7 45B3 57C4 33C7 35C7 38C6 44D5 44C8 45B6 66A3 44B8 45D5 57C8 29B3 46C4 75C3 22D4 44C8 46C4 22D4 44C8 46C4 24C8 44C8 46B4 24D5 44C5 46B4 44B5 45C5 46B4 44B5 45C5 46B4 44C3 45D7 46B4 44C1 46B4 41A8 44B8 44C5 45D5 46B4 I44 I47 I46 I48 I224 I225 I240 I241 USB FUNC_TEST TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TP_USB_EXCARD_P TP_USB_EXCARD_N TP_USB_EXTC_P TP_USB_EXTC_N USB2_BT_F_P USB2_BT_F_N USB2_3G_F_N USB2_3G_F_P 8B2 8B2 C 8B2 8B2 43C2 43C2 43A4 43A4 24A7 24D5 46B4 FUNC_TEST =PP1V05_S0_REG TRUE I57 DC-JACK FUNC_TEST ACIN_ENABLE_GATE TRUE I58 Battery charger FUNC_TEST PPVBAT_G3H_CHGR_OUT TRUE 7D8 61B8 SMBus FUNC_TEST SMBUS_SMC_B_S0_SCL TRUE SMBUS_SMC_B_S0_SDA TRUE FIREWIRE FUNC_TEST PPFW_SWITCH TRUE SLEEP LED FUNC_TEST SYS_LED_ANODE TRUE SMC FUNC_TEST SMC_LID TRUE SMC_MANUAL_RST_L TRUE SMC_CPU_VSENSE TRUE Power Supply FUNC_TEST ALL_SYS_PWRGD TRUE PPVCORE_S0_CPU TRUE PP1V05_S0_R TRUE PP1V05_S0 TRUE PP1V5_S0 TRUE PP1V8_S0 TRUE PP3V3_S0 TRUE PP5V_S0 TRUE PP1V2_ENET_S0 TRUE PP1V8_S3 TRUE 47C5 76C3 47C5 76C3 I60 I59 I61 38D3 I63 40C5 45A3 I221 I220 42C3 44B5 45C5 57A8 I222 45D8 I238 44C5 48B1 I237 I239 27A5 44D8 58A3 7D7 7D7 I227 7D7 45D2 I226 7C7 I228 7B7 I230 7D4 45D1 I229 7A7 I231 TRUE TRUE TRUE TRUE TRUE TRUE PP3V3_S3 PP5V_S3 PP3V3_S5 PP5V_S5 PP3V42_G3H PPBUS_G3H TRUE TRUE TRUE TRUE PP18V5_G3H PP0V9_S0 PP3V3_S3_BT_F GND_BT_F INVERTER TRUE TRUE TRUE TRUE 57C3 66A6 66B5 66C2 CONNECTOR FUNC_TEST PPBUS_ALL_INV_CONN INV_GND PP5V_INV_F INV_BKLIGHT_PWM_L 67D3 67D2 67D3 67D2 MIC FUNC_TEST MIC_HI TRUE MIC_LO TRUE MIC_SHIELD TRUE MIC_HI_CONN TRUE MIC_LO_CONN TRUE MIC_SHLD_CONN TRUE 55B3 56A6 55B3 56A6 B 55B1 55D3 55B1 55D3 55A1 55D3 56A6 SPEAKER FUNC_TEST SPKRCONN_L_N_OUT TRUE SPKRCONN_L_P_OUT TRUE SPKRCONN_R_N_OUT TRUE SPKRCONN_R_P_OUT TRUE SPKRCONN_SUB_N_OUT TRUE SPKRCONN_SUB_P_OUT TRUE 54C1 55C2 54C1 55C2 54C1 55C2 54D1 55C2 54B1 55C2 54B1 55C2 7B5 7B4 8D5 I172 I219 I9 28A4 29B6 75C3 FIREWARE NO_TESTS I200 FUNC_TEST =PP3V42_G3H_LPCPLUS TRUE =PP5V_S0_LPCPLUS TRUE LPC_AD TRUE LPC_AD TRUE LPC_FRAME_L TRUE PM_CLKRUN_L TRUE BOOT_LPC_SPI_L TRUE SMC_TMS TRUE DEBUG_RESET_L TRUE SMC_TRST_L TRUE SMC_TDO TRUE SMC_MD1 TRUE SMC_TX_L TRUE FWH_INIT_L TRUE PCI_CLK33M_LPCPLUS TRUE LPC_AD TRUE LPC_AD TRUE INT_SERIRQ TRUE PM_SUS_STAT_L TRUE SMC_TDI TRUE SMC_TCK TRUE SMC_RESET_L TRUE SMC_NMI TRUE SMC_RX_L TRUE LINDACARD_GPIO TRUE Other Func Test Points 28B4 29B6 75C3 I151 I199 57A5 28B4 29C6 75C3 I182 NO_TEST TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE 44C5 45C5 57A2 7C4 50C4 LPC+ Debug Connector I20 FUNC_TEST SMC_BS_ALRT_L TRUE SMBUS_BATT_SCL_F TRUE SMBUS_BATT_SDA_F TRUE 7A4 I232 7A4 I233 7D1 I234 7C1 I235 7C1 I242 7B1 I243 THERMAL FUNC_TEST THRM_HEATPIPE_P TRUE THRM_HEATPIPE_N TRUE THRM_DIMM_DX_F_N TRUE THRM_DIMM_DX_F_P TRUE THRM_FINSTACK_P TRUE THRM_FINSTACK_N TRUE 7B1 49D6 49D6 49B6 49B6 49C6 49C6 FUNC TEST OF 7D7 43D2 A 43C2 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING SMC_FAN_3_TACH I TO MAINTAIN THE DOCUMENT IN CONFIDENCE 44A4 44A8 II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE D APPLE INC DRAWING NUMBER SCALE SHT NONE REV 051-7455 OF 76 01 "S0,S0M" RAILS 58D3 58C4 58C3 58B8 58B3 58A3 =PP3V3_S0_FET PP3V3_S0 =PPVORE_S0_CPU_REG (CPU VCOR PWRE) (REGULATOR OUTPUT CPU 0.90V PWR) D 62B8 =PP0V9_S0_REG (DDR2 TERMINATION 0.9V PWR) PPVCORE_S0_CPU =PPVCORE_S0_CPU PP0V9_S0 =PP1V05_S0_REG =PP3V3_S0_NB_VCCHV =PP3V3_S0_NB_FOLLOW =PP3V3_S0_SB_GPIO =PP3V3_S0_SB_VCCGLAN3_3 =PP3V3_S0_SB_VCC3_3_PCI =PP3V3_S0_SB_VCC3_3_IDE =PP3V3_S0_SB_VCC3_3_VCCPCORE =PP3V3_S0_SB_VCC3_3_SATA =PP3V3_S0_SB_VCC3_3_DMI =PP3V3_S0_SB =PP3V3_S0_SB_PM =PP3V3_S0_RSTBUF =PP3V3_S0_AIRPORT =PP3V3_S0_FW =PP3V3_S0_PATA 10B5 10D7 11D7 48B3 48B5 6A2 MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0.9V MAKE_BASE=TRUE =PP0V9_S3M_MEM_TERM 61B8 6B2 6B2 MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.3 MM VOLTAGE=0.9V MAKE_BASE=TRUE PP1V05_S0 32D4 6B2 45D2 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V MAKE_BASE=TRUE =PP1V05_S0_SB_CPU_IO =PPVCORE_S0_SB 61C7 =PP1V05_S0_REG_R PP1V05_S0_R 22D2 25C3 26C4 25D3 26D2 =PP3V3_S0_SMC_LS 6B2 =PP1V05_S0_CPU =PP1V05_S0_NB_PCIE =PPVCORE_S0_NB =PP1V25R1V05_S0_FSB_NB =PP1V25R1V05_S0_NB_VTT =PP1V05_S0M_NB_VCCAXM 64B2 =PP1V25_S0_REG 9B5 9B6 9C5 9D5 10C7 11A3 12B3 12C5 20D5 17D3 17D7 20B4 20D8 13B7 29B6 29C6 18D3 20C8 17B3 17C1 20D8 PP1V25_S0 =PP1V25_S0_NB_PLL =PP1V25_S0_NB_VCCDMI C =PP1V25_S0_SB_DMI =PP1V25_S0_NB_VCCAXF =PP1V25_S0_NB_PLL =PP1V25_S0_NB_VCC =PP1V25_S0_NB_VCCA =PP1V25_S0_FET 62C5 61B1 =PP1V5_S0_REG PP1V5_S0 18C3 20A8 6B2 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.5V MAKE_BASE=TRUE =PP1V5_S0_CPU 10B7 11B3 =PP1V5_S0_NB_TVDAC 21D8 =PP1V5_S0_SB 26A8 26C8 26D6 =PP1V5_S0_SB_VCC1_5_A_ARX 25B6 26D5 =PP1V5_S0_SB_VCC1_5_A_ATX 25B6 26C6 =PP1V5_S0_SB_VCC1_5_A 25B6 26C2 =PP1V5_S0_SB_VCCUSBPLL 25A6 26B6 =PP1V5_S0_SB_VCC1_5_A_USB_CORE 25B6 26C2 =PP1V5_S0_AIRPORT 33D2 =PP1V5_S0_NB_FOLLOW 21D5 35C1 =PP1V2_ENET_REG PP1V2_ENET_S0 6A2 35D1 35B2 25C3 26A6 26C6 25C3 26B8 25C3 26A8 26D8 39C8 27B6 27B8 27D4 35D4 =PP3V3_ENET_PHY PP3V3_ENET_FET MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V MAKE_BASE=TRUE 38C6 =PP3V3_S5_SMBUS_SB_ME =PP3V3_S5_ROM =PP3V3_S5_LCD =PP3V3_S5_SB_CLINK1 =PP3V3_S5_1V25S0 =PP3V3_S5_AIRPORT_AUX 39C2 63B8 =PP1V8_S0_FET PP1V8_S0 =PPVCORE_S0_NB_GFX_IMVP 21C5 =PP1V8_S3_REG 62B2 60C7 60C2 61C5 66C3 7C4 68B1 68B2 68B7 68C8 68D8 69B7 69C2 69C8 25A3 26B6 26D2 25B3 26B2 38A6 38A8 67C7 64B6 33C7 33D6 33D7 6A2 26D8 39D6 41C8 61C4 62C5 =PP5V_S5_PWRCTL =PP5V_S5_FET 48D2 65B6 58B3 58C6 58D5 65B5 66B3 C 25B3 26C4 23A3 18C6 20A6 "G3H" RAILS 30A7 31A3 31A7 25A6 26B2 25A3 26D3 24C1 64C4 =PP3V42_G3H_REG PP3V42_G3H 6A2 MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.42V MAKE_BASE=TRUE 28C8 28D3 28D8 29B2 29D2 18D6 21B5 69C8 =PP3V42_G3H_SMC 7C4 68B1 68B2 68B7 68C8 68D8 69B7 69C2 69C8 =PP1V9_ENET_REG PP1V9_ENET_S0 =PP1V8_S0_YUKON 34D6 36D8 =PP1V8R2V5_ENET_PHY 44D4 45C1 45D4 45D8 51B8 =PP3V42_G3H_SMCVREF =PP3V42_G3H_SMBUS_SMC_BSA =PP3V42_G3H_ACIN =PP3V42_G3H_LIDSWITCH =PP3V42_G3H_PWRCTL =PP3V42_G3H_SB_RTC =PP3V42_G3H_SMCUSBMUX =PP3V42_G3H_LPCPLUS MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=2.5V MAKE_BASE=TRUE 34C7 34D6 =PP18V5_G3H_INRUSH PP18V5_G3H 45C8 47C3 57C4 66A5 66A8 66B8 57A8 65C7 27D7 41A6 6D2 46C6 6A2 =PP18V5_G3H_CHGR MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=18.5V MAKE_BASE=TRUE 20A5 20A6 =PP1V8_S3_REG_R =PP3V3_S3_FET =PPBUSA_G3H PPBUS_G3H 6A2 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=18.5V MAKE_BASE=TRUE 35C3 PP1V8_S3_MEM_NB 66C2 =PPBUSB_G3H 43B5 6D2 46C6 48B8 6D2 50C4 6D1 53A7 56C4 6D1 54B8 54C8 54D8 6A2 67D4 62B3 63A6 63B6 63B3 61B3 61B5 45A6 33C2 37D5 37C5 43D3 51C7 47D3 62A2 62C2 Power Aliases 35D7 47C3 51B6 SYNC_MASTER=WFERRY SYNC_DATE=06/15/2006 35D3 59D8 NOTICE OF PROPRIETARY PROPERTY 60D2 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING 67D7 69D7 21D6 65B4 =PP5V_S3_FET PP5V_S3 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE 6A2 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5V MAKE_BASE=TRUE 39B7 II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART =PP5V_S3_SYSLED =PP5V_S3_GEYSER =PP5V_S3_IR =PP5V_S3_CAMERA 40B6 45A4 SIZE 42D6 D 43D8 APPLE INC 67A5 DRAWING NUMBER REV 051-7455 SCALE SHT NONE 60C2 =PPVIN_S5_1V8S30V9S0 =PPVIN_S5_5VS5 =PPVIN_S5_3V3S5 =PPVIN_S5_1V5S0 =PPVIN_S5_1V05S0 =PPVIN_S5_IMVP 20A4 =PP3V3_S3_AIRPORT_AUX =PP3V3_S3_FW =PP3V3_S3_PCI =PP3V3_S3_BT =PP3V3_S3_SMS =PP3V3_S3_SMBUS_SMC_A_S3 =PP3V3_S3_PDCISENS =PP3V3_S3_ENETPWRCTL =PP3V3_S3_SMBUS_SMC_MGMT =PP3V3_ENET_P3V3ENETFET 40C6 48D7 59C2 59D4 59D8 =PPBUS_S5_INV MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V MAKE_BASE=TRUE 26D8 38D5 =PPVIN_S5_CPU_IMVP =PPVIN_S5_NB_GFX_IMVP 15D2 17D7 20C8 30D2 31D2 PP3V3_S3 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5V MAKE_BASE=TRUE =PP5V_S0_LCD =PP5V_S0_TMDS =PP5V_S0_NB_TVDAC =PP5V_S0_IDE_RESET 66C2 30B2 30D4 30D6 31B2 31D4 31D6 =PPVIN_S0_NB_DPLL =PPBUS_S5_FWPWRSW 6A2 =PP5V_S0_CPU_IMVP =PP5V_S0_NB_GFX_IMVP B 64C6 58C5 17B7 17D5 21C5 48B3 65C3 65A4 =PP5V_S0_SB =PP5V_S0_SATA =PP5V_S0_3G =PP5V_S0_LPCPLUS =PP5V_S0_ISENSECAL =PP5V_S0_FAN_RT =PP5V_S0_AUDIO =PP5V_S0_AUDIO_AMP 66D8 PPDCIN_G3H =PPVIN_G3H_P3V42G3H =PP1V8_S3_FET =PP1V8_S3_MEMVREF =PP1V8_S3_MEM =PP1V8_ENET_P1V8ENETFET =PP1V8_S3M_MEM_NB =PP1V8_S3_NB_VCC PP5V_S0 =PPDCIN_G3H 6A2 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.4 mm VOLTAGE=1.8V MAKE_BASE=TRUE 25A3 26D2 24B1 =PP5V_S5_1V51V05S0 =PP5V_S5_1V8S30V9S0 67B5 67B7 67C6 PP1V8_S3 68D6 62C4 A 58C5 65A5 65C4 52C6 =PP5V_S5_SB =PP5V_S5_PATA =PP5V_S5_USB 59D8 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.8V MAKE_BASE=TRUE 21A7 PPVCORE_S0_NB_GFX =PPVCORE_S0_NB_GFX =PP5V_S0_FET 24A3 24A8 26D8 35C7 47A7 PP5V_S5 53A7 53D7 55D8 56B5 57D3 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=1.25V MAKE_BASE=TRUE 58D4 58C8 24D8 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5V MAKE_BASE=TRUE "S3" RAILS 6B2 =PP1V8_S0_NB_LVDS =PP1V8_S0_NB_DPLL =PP1V8_S0_TMDS 60C2 D 23C8 MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=18.5V MAKE_BASE=TRUE MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.8V MAKE_BASE=TRUE B =PP5V_S5_REG 8A4 57D1 58C4 58B8 27C5 33C6 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.2V MAKE_BASE=TRUE =PP1V2_ENET_PHY =PP3V3_S5_SB_PM =PP3V3_S5_SB_USB =PP3V3_S5_SB_GPIO =PP3V3_S5_SB =PP3V3_S5_FET =PP3V3_S5_SB_VCCSUS3_3_USB =PP3V3_S5_SB_VCCSUS3_3 =PP3V3_S5_SB_3V3_VCCSUSHDA =PP3V3_S5_FWLATEVG 25B3 26B4 25C3 26B4 6D2 50C4 =PP3V3_S0_SB_PCI 58A3 25A6 49C2 49D2 =PP3V3_S0_NB_VCCA_PEG_BG =PPSPD_S0_MEM =PP3V3_S0MWOL_SB_VCCCL3_3 =PP3V3_S0MWOL_SB_VCCLAN3_3 =PP3V3_S0MWOL_SB_CLINK0 =PP3V3_S0_CK505 =PP3V3_S0_NB_VCCSYNC =PP3V3_S0_NB =PP3V3_S0_TMDS 20B8 6A2 47C5 20D4 20A8 PP3V3_S5 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V MAKE_BASE=TRUE 47D5 25C3 26A6 7C7 20B4 20D3 =PP3V3_S5_REG 22D2 22D7 24B3 24D8 47D8 =PP3V3_S0_PDCISENS =PP3V3_S0_LCD =PP3V3_S0_TMDS =PP3V3_S0_CPUPOWER =PP3V3_S0_PBATTISENS =PP3V3R1V5_S0_SB_VCCHDA 7C7 20B4 20D3 63B1 20B2 46C4 =PP3V3_S0_IMVP =PP3V3_S0_NB_GFX_IMVP MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.25V MAKE_BASE=TRUE 15B7 15C7 18B3 20A8 21B7 45D4 =PP3V3_S0_LPCPLUS =PP3V3_S0_SMBUS_SB =PP3V3_S0_SMBUS_SMC_0_S0 =PP3V3_S0_SMBUS_SMC_B_S0 =PP3V3_S0_THRM_SNR =PP3V3_S0_FAN_RT =PP3V3_S0_ENET =PP3V3_S0_AUDIO MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V MAKE_BASE=TRUE "S5" RAILS 6A2 45D1 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V MAKE_BASE=TRUE (REGULATOR OUTPUT CPU VCORE PWR) 59D1 OF 76 01 A (EMI PAD FOR INVERTER GONNECTOR) LVDS ALIASES 67C2 INVT_CHGND ZS0920 EMI-SPRING VOLTAGE=0V MAKE_BASE=TRUE 43B5 43A5 LVDS_B_CLK_N LVDS_B_CLK_P LVDS_B_DATA_N LVDS_B_DATA_N LVDS_B_DATA_N 14C5 =GND_CHASSIS_3GPOWER 14C5 14C5 CHASSIS GND 14C5 BATTERY,AUDIO,DIP DIMM CONNECTOR CHASSIS GND 14C5 TP_LVDS_B_DATAN3 15C6 OMIT GND_CHASSIS_IO Z0906 5R2P3-7SQBNP D =GND_BATT_CHGND =GND_CHASSIS_AUDIO_JACK 57A6 55C3 30A5 LVDS_B_CLK_N_SPN 6A7 LVDS_B_CLK_P_SPNMAKE_BASE=TRUE 6A7 MAKE_BASE=TRUE LVDS_B_DATA_N0_SPN 6A7 MAKE_BASE=TRUE LVDS_B_DATA_N1_SPN 6A7 MAKE_BASE=TRUE LVDS_B_DATA_N2_SPN 6A7 MAKE_BASE=TRUE LVDS_B_DATA_N3_SPN 22B6 22B6 22B6 22B6 LVDS_B_DATA_P LVDS_B_DATA_P LVDS_B_DATA_P TP_LVDS_B_DATAP3 LVDS_B_DATA_P0_SPN MAKE_BASE=TRUE LVDS_B_DATA_P1_SPN 6A7 MAKE_BASE=TRUE LVDS_B_DATA_P2_SPN 6A7 MAKE_BASE=TRUE LVDS_B_DATA_P3_SPN TP_LVDS_A_DATAP3 TP_LVDS_A_DATAN3 LVDS_A_DATA_P3_SPN MAKE_BASE=TRUE LVDS_A_DATA_N3_SPN 14C5 14C5 15C6 22B6 22B6 22B6 15C6 SATA,LVDS CONNECTOR CHASSIS GND GND_CHASSIS_SATA OMIT Z0907 40C8 VOLTAGE=0V MAKE_BASE=TRUE =GND_CHASSIS_LVDS 6P5R2P6-7SQB 14D3 14D3 14D3 14D3 14D3 1 C0908 C0907 0.1UF 0.01UF 14D3 10% 10% 16V X5R 402 14D3 16V CERM 14D3 402 14D3 14C3 DCIN CONNECTOR CHASSIS GND OMIT GND_CHASSIS_DCIN Z0902 VOLTAGE=0V MAKE_BASE=TRUE 57C8 =GND_DCIN_CHGND 36B2 =GND_CHASSIS_RJ45 7X7R2P3-5B 14C3 14C3 14C3 14C3 14C3 C 69C4 69A4 C0930 14C3 0.1UF =GND_CHASSIS_TMDS_UPPER 14C3 10% 16V X5R 402 14C3 14C3 14C3 14C3 I/O CONNECTOR CHASSIS GND OMIT GND_CHASSIS_IO Z0908 8D7 VOLTAGE=0V MAKE_BASE=TRUE 5P0R2P3-7BLB 38B1 41C4 41C2 41A4 41A2 =GND_CHASSIS_FW_DOWN =GND_CHASSIS_USB 1 C0911 C0910 0.1UF 0.01UF 10% 16V X5R 402 14C3 14C3 14C3 14C3 14C3 14C3 10% 16V CERM 402 14C3 14C3 14C3 DIP DIMM CONNECTOR CHASSIS GND OMIT GND_CHASSIS_CENTER Z0910 VOLTAGE=0V 5R2P3-7SQB MAKE_BASE=TRUE 31A5 30D5 =GND_CHASSIS_DIPDIMM_CENTER C0916 C0917 0.01UF 10% 0.1UF 10% 16V CERM 16V X5R 402 402 14B3 14B3 14B3 14B3 14B3 14B3 14B3 14B3 14B3 DIP DIMM CONNECTOR CHASSIS GND 14B3 OMIT GND_CHASSIS_RIGHT Z0909 VOLTAGE=0V 5R2P3-7SQB MAKE_BASE=TRUE B 31D4 =GND_CHASSIS_DIPDIMM_RIGHT 1 14B3 14B3 0.01UF 10% 0.1UF 14B3 14B3 C0914 C0915 10% 16V X5R 402 14B3 14B3 16V CERM 14B3 402 14B3 14B3 OMIT OMIT Z0901 Z0911 5R2P3-7SQBNP 5R2P3-7B 1 GND_CHASSIS_CPU GND_CHASSIS_FANSCREW 14B3 14A3 14A3 14A3 14A3 1 C0913 C0912 0.1UF 0.01UF 10% 10% 16V X5R 402 C0918 0.1UF 10% 16V X5R 402 16V CERM 402 0.01UF 10% 73C3 22C8 402 73C3 22C8 73C3 22C8 CPU HEATSINK STANDOFF SCREW HOLE Z0903 NB_RIGHT_DOWN_SCREW R0912 A 1/16W MF-LF 2402 73B3 22B8 TP_PCIE_A_D2R_N 23D5 TP_PCIE_A_D2R_P 23D5 TP_PCIE_A_R2D_C_N 23D5 Z0904 HDA_BIT_CLK HDA_SYNC HDA_RST_L HDA_SDIN0 HDA_SDOUT STDOFF-4.2OD3.95H-5.52R3.37-7SQB 22C8 R0910 TP_HDA_SDIN3 15B6 OMIT Z0921 15B6 15B6 15B6 15B6 NB_CFG NB_CFG NB_CFG NB_CFG NB_CFG TP_NB_CFG TP_NB_CFG TP_NB_CFG TP_NB_CFG TP_NB_CFG R0921 R0911 28B4 28B4 28B4 28B4 75D3 28B6 75D3 28B6 34B8 28A4 USB_EXTA_P 23C2 73B3 USB_EXTA_N 23C2 73B3 USB_EXTA_OC_L 23C8 MAKE_BASE=TRUE USB PORT [1] = PCI-E Mini Card 33B3 =USB2_AIRPORT_P USB2_AIRPORT_P 33B3 =USB2_AIRPORT_N USB2_AIRPORT_N MAKE_BASE=TRUE 23C2 73B3 USB_MINI_N 23C2 73B3 USB PORT [2] = 3G USB =USB2_3G_P =USB2_3G_N 43A4 USB2_3G_P USB_EXTD_P 23C2 USB2_3G_N MAKE_BASE=TRUE USB_EXTD_N 23C2 43A4 MAKE_BASE=TRUE USB PORT [3] = CAMERA NO-CONNECT UNUSED CLOCK INTERFACE PORTS TP_CK505_SRC1_N CK505_SRC1_N_SPN CK505_SRC1_P_SPN MAKE_BASE=TRUE TP_CK505_SRC1_P MAKE_BASE=TRUE CK505_SRC3_N_SPN TP_CK505_SRC3_N TP_CK505_SRC3_P CK505_SRC3_P_SPN MAKE_BASE=TRUE TP_CK505_SRC7_N CK505_SRC7_N_SPN MAKE_BASE=TRUE MAKE_BASE=TRUE TP_CK505_SRC7_P CK505_SRC7_P_SPN MAKE_BASE=TRUE CK505_PCI2_CLK CK505_PCI2_CLK_SPN MAKE_BASE=TRUE CK505_PCI4_CLK CK505_PCI4_CLK_SPN MAKE_BASE=TRUE ENET_CLKREQ_L =ENET_CLKREQ_L 67B4 =USB2_CAMERA_P USB2_CAMERA_P 67A4 =USB2_CAMERA_N USB2_CAMERA_N MAKE_BASE=TRUE USB_CAMERA_P 23C2 73B3 USB_CAMERA_N 23C2 73B3 MAKE_BASE=TRUE C USB PORT [4] = IR CONTROLLER 73B3 23C2 8C1 =USB2_IR_P 43C4 =USB2_IR_N 43C4 USB_IR_P USB_IR_N USB_IR_P USB_IR_N MAKE_BASE=TRUE 8C2 23C2 73B3 8C2 23C2 73B3 MAKE_BASE=TRUE USB PORT [5] = Trackpad(Geyser) 42C7 =USB2_GEYSER_P USB2_GEYSER_P 42C7 =USB2_GEYSER_N USB2_GEYSER_N USB_TPAD_P USB_TPAD_N MAKE_BASE=TRUE MAKE_BASE=TRUE 23C2 73B3 23C2 73B3 MAKE_BASE=TRUE USB PORT [6] = BLUETOOTH 73B3 23C2 8C1 43C3 =USB2_BT_P SB ALIASES MAKE_BASE=TRUE USB_BT_N VR_PWRGD_CLKEN =SB_CLINK_MPWROK SB_SATA_CLKREQ_L EXTGPU_RST_L 24C3 24C5 24C5 24B5 8C2 23C2 73B3 8B2 23C2 73B3 MAKE_BASE=TRUE NO-CONNECT UNUSED CLOCK INTERFACE PORTS 24C5 USB_BT_P USB_BT_N USB_BT_P 43C3 =USB2_BT_N USB PORT [7] = External USB2.0 Port B VR_PWRGD_CK505 27A8 MAKE_BASE=TRUE CLINK_MPWROK 8B1 27A6 MAKE_BASE=TRUE SB_CLK100M_SATA_OE_L 28B4 MAKE_BASE=TRUE TP_SB_GPIO17 41B5 =USB2_EXTB_P USB2_EXTB_P 41B5 =USB2_EXTB_N USB2_EXTB_N MAKE_BASE=TRUE EXTBUSB_OC_L USB_EXTB_P 23C2 USB_EXTB_N 23C2 USB_EXTB_OC_L MAKE_BASE=TRUE 41C8 =EXTBUSB_OC_L 73B3 73B3 23C8 MAKE_BASE=TRUE MAKE_BASE=TRUE USB PORT [8] = Unused SO-DIMM ALIASES TP_USB_EXCARD_P 30C4 31C4 15C6 MEM_A_A MEM_B_A MAKE_BASE=TRUE TP_MEM_CLKN2 15C6 TP_MEM_CLKP5 15C6 TP_MEM_CLKN5 15C6 TP_USB_EXCARD_N 6C1 MEM_A_A15_SPN MEM_B_A15_SPN MAKE_BASE=TRUE MEM_CLK_P_2_SPNMAKE_BASE=TRUE MEM_CLK_N_2_SPNMAKE_BASE=TRUE MEM_CLK_P_5_SPNMAKE_BASE=TRUE MEM_CLK_N_5_SPNMAKE_BASE=TRUE TP_MEM_CLKP2 USB_EXCARD_P 23C2 73B3 USB_EXCARD_N 23C2 73B3 6C1 NO-CONNECT UNUSED ADDRESS INTERFACE PORTS MAKE_BASE=TRUE USB PORT [9] = Unused TP_USB_EXTC_P USB_EXTC_P 23C2 73B3 USB_EXTC_N 23C2 73B3 6C1 MAKE_BASE=TRUE TP_USB_EXTC_N 6C1 MAKE_BASE=TRUE B ANALOG SWITCH GPIO MAKE_BASE=TRUE 44B8 15B7 44B8 15B7 PM_EXTTS_L MAKE_BASE=TRUE PM_EXTTS_L DIMM_OVERTEMPA_L 30C4 DIMM_OVERTEMPB_L 31C4 MAKE_BASE=TRUE NB ALIASES 56A8 56A4 55B3 53D3 53B7 53A7 54C8 54B8 54A8 56C4 56B8 56B5 54B8 54A8 54A5 =GND_AUDIO_CODEC 6D1 GND_AUDIO_CODEC 6D1 GND_AUDIO_AMP NB_CLK96M_DOT_P NB_CLK96M_DOT_N NB_CLK100M_DPLLSS_P NB_CLK100M_DPLLSS_N 15C3 XW0802 SM MAKE_BASE=TRUE 60C6 CLINK_MPWROK 15A3 MAKE_BASE=TRUE =GND_AUDIO_AMP GFX_VR_EN =GFX_VR_EN =NB_CLINK_MPWROK =NB_CLK96M_DOT_P =NB_CLK96M_DOT_N 15C3 15C3 =NB_CLK100M_DPLLSS_P 15C3 =NB_CLK100M_DPLLSS_N 19D2 =NB_TDE_SENSE 15B3 XW0801 SM MAKE_BASE=TRUE 8B3 27A6 MAKE_BASE=TRUE 29B3 75B3 MAKE_BASE=TRUE 29B3 75B3 MAKE_BASE=TRUE 29C3 75B3 MAKE_BASE=TRUE 29C3 75B3 MAKE_BASE=TRUE 6C1 53C7 MAKE_BASE=TRUE 6C1 53C7 MAKE_BASE=TRUE Ethernet ALIASES 6C1 53B7 MAKE_BASE=TRUE TABLE_5_HEAD PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION 6D1 53C7 TABLE_5_ITEM MAKE_BASE=TRUE 6D1 53C7 860-0876 THERMAL STANDOFF Z0903,Z0904,Z0905,Z0921STANDOFF 860-0723 STANDOFF WIRELESS Z0912 STANDOFF 860-0749 STANDOFF W/THRU HOLES,WIRELESS Z0913 STANDOFF TABLE_5_ITEM 7C4 =PP3V3_S0_ENET =ENET_VMAIN_AVLBL 34C2 MAKE_BASE=TRUE MAKE_BASE=TRUE 34C7 =YUKON_EC_PP2V5_ENET TABLE_5_ITEM SIGNAL ALIAS /RESET SYNC_MASTER=GPU MAKE_BASE=TRUE 69A3 =GND_CHASSIS_TMDS_DOWN 38B1 =GND_CHASSIS_FW_UPPER VOLTAGE=0V MAKE_BASE=TRUE AIRPORT CARD STANDOFF SCREW HOLE THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE OMIT I TO MAINTAIN THE DOCUMENT IN CONFIDENCE OMIT Z0912 Z0913 II NOT TO REPRODUCE OR COPY IT STDOFF-4.2OD2.15H-1.2-3.2-TH STDOFF-4.2OD3.95H-5.52R3.37-6B NC NC SYNC_DATE=07/17/2006 NOTICE OF PROPRIETARY PROPERTY III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE D APPLE INC DRAWING NUMBER REV 051-7455 SCALE SHT NONE USB_MINI_P MAKE_BASE=TRUE CLOCK ALIASES 28B4 USB2_EXTA_N MAKE_BASE=TRUE EXTAUSB_OC_L MAKE_BASE=TRUE MAKE_BASE=TRUE 28B4 USB2_EXTA_P 41C8 =EXTAUSB_OC_L =NB_TDE_FORCE 19C2 =NB_TDB_FORCE 19C2 =NB_TDB_SENSE GND_CHASSIS_IO1 1/16W MF-LF 2402 1/16W MF-LF 2402 TP_PCIE_FW_D2R_N 23D5 TP_PCIE_FW_D2R_P 23D5 TP_PCIE_FW_R2D_C_N 23D5 TP_PCIE_FW_R2D_C_P 23D5 MAKE_BASE=TRUE 5% 5% TP_PCIE_EXCARD_R2D_C_N 23D5 TP_PCIE_EXCARD_R2D_C_P 23D5 USB PORT [0] = External USB2.0 Port A 41A8 =USB2_EXTA_P 41A8 =USB2_EXTA_N NB CFG ALIASES Z0905 STDOFF-4.5OD3.95H-1.1-3.2-TH STDOFF-4.5OD3.95H-1.1-3.2-TH CPU_THERMAL_SCREW_RIGHT MAKE_BASE=TRUE PCIE_A_D2R_N_SPN MAKE_BASE=TRUE PCIE_A_D2R_P_SPN MAKE_BASE=TRUE PCIE_A_R2D_C_N_SPN MAKE_BASE=TRUE PCIE_A_R2D_C_P_SPN PCIE_B_D2R_N_SPN MAKE_BASE=TRUE PCIE_B_D2R_P_SPN MAKE_BASE=TRUE MAKE_BASE=TRUE PCIE_B_R2D_C_N_SPN MAKE_BASE=TRUE PCIE_B_R2D_C_P_SPN PCIE_C_D2R_N_SPN MAKE_BASE=TRUE MAKE_BASE=TRUE PCIE_C_D2R_P_SPN MAKE_BASE=TRUE PCIE_C_R2D_C_N_SPN MAKE_BASE=TRUE PCIE_C_R2D_C_P_SPN MAKE_BASE=TRUE PCIE_D_D2R_N_SPN PCIE_D_D2R_P_SPN MAKE_BASE=TRUE MAKE_BASE=TRUE PCIE_D_R2D_C_N_SPN MAKE_BASE=TRUE PCIE_D_R2D_C_P_SPN MAKE_BASE=TRUE Z0903 USE SAME Z0913 NON SHAPE OF A HOOF SYMBOL 5% 1/16W FOR LAYOUT PLACEMENT MF-LF 402 BUT, NEED CHANGE TO HIGH STANDOFF SYMBOL CPU_THERMAL_SCREW_DOWN ACZ_BITCLK ACZ_SYNC ACZ_RST_L ACZ_SDATAIN ACZ_SDATAOUT HDN_SDIN1_SPN HDN_SPIN2_SPN HDN_SPIN3_SPN TP_HDA_SDIN1 22C8 TP_HDA_SDIN2 22C8 OMIT TP_PCIE_A_R2D_C_P TP_PCIE_B_D2R_N 23D5 TP_PCIE_B_D2R_P 23D5 TP_PCIE_B_R2D_C_N 23D5 TP_PCIE_B_R2D_C_P 23D5 TP_PCIE_EXCARD_D2R_N 23D5 TP_PCIE_EXCARD_D2R_P 23D5 23D5 D MAKE_BASE=TRUE CPU_THERMAL_SCREW_UP1 5% 73C3 22C8 OMIT STDOFF-4.2OD3.95H-5.52R3.37-6B SATA_C_D2R_N_SPN MAKE_BASE=TRUE SATA_C_D2R_P_SPN MAKE_BASE=TRUE SATA_C_R2D_C_N_SPN MAKE_BASE=TRUE SATA_C_R2D_C_P_SPN 19C2 16V CERM OMIT 37B3 PCI_EXP ALIASES MAKE_BASE=TRUE C0919 FW_B_TPBIAS_SPN 6B7 FW_B_TPA_P_SPNMAKE_BASE=TRUE 6B7 FW_B_TPA_N_SPNMAKE_BASE=TRUE 6B7 MAKE_BASE=TRUE FW_B_TPB_P_SPN 6B7 FW_B_TPB_N_SPNMAKE_BASE=TRUE 6B7 MAKE_BASE=TRUE FW_C_TPBIAS_SPN 6B7 FW_C_TPA_P_SPNMAKE_BASE=TRUE 6B7 MAKE_BASE=TRUE FW_C_TPA_N_SPN 6B7 FW_C_TPB_P_SPNMAKE_BASE=TRUE 6B7 FW_C_TPB_N_SPNMAKE_BASE=TRUE 6B7 FW_B_TPBIAS FW_B_TPA_P FW_B_TPA_N 37B3 FW_B_TPB_P 37B3 FW_B_TPB_N 37B3 FW_C_TPBIAS 37B3 FW_C_TPA_P 37B3 FW_C_TPA_N 37B3 FW_C_TPB_P 37B3 FW_C_TPB_N 37B3 37B3 NO-CONNECT UNUSED PCI_EXP INTERFACE PORTS PCI_EXPRESS GRAPHICS ALIASES NO-CONNECT UNUSED SDVO INTERFACE PORTS PEG_D2R_N PEG_D2R_N0_SPN PEG_D2R_N PEG_D2R_N2_SPN MAKE_BASE=TRUE PEG_D2R_N PEG_D2R_N3_SPN MAKE_BASE=TRUE PEG_D2R_N PEG_D2R_N4_SPN MAKE_BASE=TRUE PEG_D2R_N PEG_D2R_N5_SPN MAKE_BASE=TRUE PEG_D2R_N PEG_D2R_N6_SPN MAKE_BASE=TRUE PEG_D2R_N PEG_D2R_N7_SPN MAKE_BASE=TRUE MAKE_BASE=TRUE PEG_D2R_N PEG_D2R_N8_SPN MAKE_BASE=TRUE PEG_D2R_N PEG_D2R_N9_SPN PEG_D2R_N PEG_D2R_N10_SPN MAKE_BASE=TRUE PEG_D2R_N PEG_D2R_N11_SPN MAKE_BASE=TRUE PEG_D2R_N PEG_D2R_N12_SPN MAKE_BASE=TRUE PEG_D2R_N PEG_D2R_N13_SPN MAKE_BASE=TRUE PEG_D2R_N PEG_D2R_N14_SPN MAKE_BASE=TRUE PEG_D2R_N PEG_D2R_N15_SPN MAKE_BASE=TRUE PEG_D2R_P0_SPN MAKE_BASE=TRUE PEG_D2R_P PEG_D2R_P PEG_D2R_P2_SPN MAKE_BASE=TRUE PEG_D2R_P PEG_D2R_P3_SPN MAKE_BASE=TRUE MAKE_BASE=TRUE PEG_D2R_P PEG_D2R_P4_SPN MAKE_BASE=TRUE PEG_D2R_P PEG_D2R_P5_SPN PEG_D2R_P PEG_D2R_P6_SPN MAKE_BASE=TRUE PEG_D2R_P PEG_D2R_P7_SPN MAKE_BASE=TRUE PEG_D2R_P PEG_D2R_P8_SPN MAKE_BASE=TRUE PEG_D2R_P PEG_D2R_P9_SPN MAKE_BASE=TRUE PEG_D2R_P PEG_D2R_P10_SPN MAKE_BASE=TRUE PEG_D2R_P PEG_D2R_P11_SPN MAKE_BASE=TRUE PEG_D2R_P PEG_D2R_P12_SPN MAKE_BASE=TRUE PEG_D2R_P13_SPN MAKE_BASE=TRUE PEG_D2R_P PEG_D2R_P14_SPN MAKE_BASE=TRUE PEG_D2R_P PEG_D2R_P PEG_D2R_P15_SPN MAKE_BASE=TRUE MAKE_BASE=TRUE PEG_R2D_C_N PEG_R2D_C_N4_SPN PEG_R2D_C_N5_SPNMAKE_BASE=TRUE PEG_R2D_C_N MAKE_BASE=TRUE PEG_R2D_C_N PEG_R2D_C_N6_SPN PEG_R2D_C_N7_SPNMAKE_BASE=TRUE PEG_R2D_C_N PEG_R2D_C_N PEG_R2D_C_N8_SPNMAKE_BASE=TRUE PEG_R2D_C_N9_SPNMAKE_BASE=TRUE PEG_R2D_C_N MAKE_BASE=TRUE PEG_R2D_C_N PEG_R2D_C_N10_SPN MAKE_BASE=TRUE PEG_R2D_C_N PEG_R2D_C_N11_SPN MAKE_BASE=TRUE PEG_R2D_C_N PEG_R2D_C_N12_SPN MAKE_BASE=TRUE PEG_R2D_C_N PEG_R2D_C_N13_SPN MAKE_BASE=TRUE PEG_R2D_C_N14_SPN PEG_R2D_C_N MAKE_BASE=TRUE PEG_R2D_C_N15_SPN PEG_R2D_C_N PEG_R2D_C_P PEG_R2D_C_P4_SPNMAKE_BASE=TRUE PEG_R2D_C_P5_SPNMAKE_BASE=TRUE PEG_R2D_C_P PEG_R2D_C_P6_SPNMAKE_BASE=TRUE PEG_R2D_C_P PEG_R2D_C_P PEG_R2D_C_P7_SPNMAKE_BASE=TRUE PEG_R2D_C_P8_SPNMAKE_BASE=TRUE PEG_R2D_C_P PEG_R2D_C_P PEG_R2D_C_P9_SPNMAKE_BASE=TRUE MAKE_BASE=TRUE PEG_R2D_C_P PEG_R2D_C_P10_SPN MAKE_BASE=TRUE PEG_R2D_C_P11_SPN PEG_R2D_C_P MAKE_BASE=TRUE 56B4 56B1 PEG_R2D_C_P PEG_R2D_C_P12_SPN MAKE_BASE=TRUE PEG_R2D_C_P13_SPN PEG_R2D_C_P MAKE_BASE=TRUE PEG_R2D_C_P14_SPN PEG_R2D_C_P MAKE_BASE=TRUE PEG_R2D_C_P PEG_R2D_C_P15_SPN 54C8 NO-CONNECT UNUSED FIREWIRE INTERFACE PORTS MAKE_BASE=TRUE MAKE_BASE=TRUE 67B2 67A6 67A4 67A2 SATA_C_D2R_N SATA_C_D2R_P SATA_C_R2D_C_N SATA_C_R2D_C_P MAKE_BASE=TRUE 15C6 FIREWIRE ALIASES NO-CONNECT UNUSED SATA INTERFACE PORTS SATA_B_D2R_N_SPN SATA_B_D2R_N MAKE_BASE=TRUE SATA_B_D2R_P SATA_B_D2R_P_SPN MAKE_BASE=TRUE SATA_B_R2D_C_N SATA_B_R2D_C_N_SPN MAKE_BASE=TRUE SATA_B_R2D_C_P SATA_B_R2D_C_P_SPN MAKE_BASE=TRUE 22B6 MAKE_BASE=TRUE 14C5 =GND_CHASSIS_AUDIO_MIC =GND_CHASSIS_DIPDIMM_LEFT 56A4 SATA ALIASES NO-CONNECT UNUSED LVDS INTERFACE PORTS CLIP-SM-M42 OF 76 01 A OMIT 70C3 13D3 BI 70C3 13D3 BI 70C3 13D3 BI 70C3 13D3 BI 70C3 13D3 BI 70C3 13D3 BI 70C3 13D3 BI 70C3 13C3 BI 70C3 13C3 BI 70C3 13A3 BI 70C3 13A3 BI 70C3 13A3 BI 70C3 13A3 BI 70C3 13A3 BI 70C3 13C3 BI 70C3 13C3 BI 70C3 13C3 BI 70C3 13C3 BI 70C3 13C3 BI 70C3 13C3 BI 70C3 13C3 C BI 70C3 13C3 BI 70C3 13C3 BI 70C3 13C3 BI 70C3 13C3 BI 70C3 13C3 BI 70C3 13C3 BI 70C3 13C3 BI 70C3 13C3 BI 70C3 13C3 BI 70C3 13C3 BI 70C3 13C3 BI 70C3 13C3 BI 70C3 13C3 BI 70C3 22C4 70C3 22C2 70B3 22C4 IN IN 70C3 22C4 IN 70B3 22C4 K3 FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_ADSTB_L Y2 IN CPU_A20M_L OUT CPU_FERR_L 70B3 22C4 70C3 22C4 FSB_REQ_L FSB_REQ_L FSB_REQ_L FSB_REQ_L FSB_REQ_L IN IN J1 N3 P5 P2 L2 P4 P1 R1 M1 H2 K2 J3 L1 U5 R3 W6 U4 Y5 U1 R4 T5 T3 W2 W5 Y4 U2 V4 W3 AA4 AB2 AA3 V1 A6 A5 CPU_IGNNE_L C4 CPU_STPCLK_L CPU_INTR CPU_NMI CPU_SMI_L TP_CPU_RSVD0 TP_CPU_RSVD1 TP_CPU_RSVD2 TP_CPU_RSVD3 TP_CPU_RSVD4 TP_CPU_RSVD5 TP_CPU_RSVD6 TP_CPU_RSVD7 TP_CPU_RSVD8 TP_CPU_RSVD9 B N2 D5 C6 B4 A3 M4 N5 T2 V3 B2 C3 D2 D22 D3 F6 REQ0* REQ1* REQ2* REQ3* REQ4* A17* A18* A19* A20* A21* A22* A23* A24* A25* A26* A27* A28* A29* A30* A31* A32* A33* A34* A35* ADSTB1* DEFER* DRDY* DBSY* H5 E1 FSB_DEFER_L FSB_DRDY_L FSB_DBSY_L BR0* F1 FSB_BREQ0_L F21 BI 13C3 70D3 BI 13C3 70D3 BI 13C3 70D3 BI 13B3 70D3 BI 13B3 70D3 BI 13B3 70D3 BI 13B3 70D3 =PP1V05_S0_CPU IERR* INIT* D20 70C3 CPU_IERR_L B3 CPU_INIT_L IN LOCK* H4 FSB_LOCK_L BI RESET* RS0* RS1* RS2* TRDY* C1 FSB_CPURST_L FSB_RS_L FSB_RS_L FSB_RS_L FSB_TRDY_L HIT* HITM* BPM0* BPM1* BPM2* BPM3* PRDY* PREQ* TCK TDI TDO TMS TRST* DBR* F3 F4 G3 G2 E4 XDP_BPM_L XDP_BPM_L XDP_BPM_L XDP_BPM_L XDP_BPM_L XDP_BPM_L XDP_TCK XDP_TDI XDP_TDO XDP_TMS XDP_TRST_L XDP_DBRESET_L AD4 AD3 AD1 AC4 AC2 AC1 AC5 AA6 AB3 AB5 AB6 C20 R1002 54.9 1% 1/16W MF-LF 402 7C7 9B5 9B6 9C5 10C7 11A3 12B3 12C5 PLACE TESTPOINT ON FSB_IERR_L WITH A GND 0.1" AWAY D 22C4 46B2 70B3 13B3 70D3 IN 12B5 13A5 70D3 IN 13A3 70D3 IN 13A3 70D3 IN 13A3 70D3 IN 13B3 70D3 OMIT FSB_HIT_L FSB_HITM_L G6 BI 13B3 70D3 BI 13B3 70D3 BI 12B2 70A3 BI 12B2 70A3 BI 12B2 70A3 BI 12B3 70A3 BI 12B2 70A3 =PP1V05_S0_CPU 1% 1/16W MF-LF 402 XDP_TDI THERMTRIP* BI B25 CPU_PROCHOT_L CPU_THERMD_P CPU_THERMD_N C7 PM_THRMTRIP_L D21 A24 BCLK0 BCLK1 FSB_CLK_CPU_P FSB_CLK_CPU_N A22 A21 BI 70D3 13D5 BI OUT 9A7 12B5 70B3 70D3 13D5 BI IN 9B7 12B2 70B3 70D3 13D5 BI IN 9A7 12B3 70A3 70D3 13D5 BI OUT 12B4 27C6 70D3 13C5 R1004 OUT OUT 49C7 OUT 49B7 OUT 15A6 22C2 45B3 70B3 45B5 45C3 59C8 70C3 PM_THRMTRIP# SHOULD CONNECT TO ICH AND GMCH WITHOUT T (NO STUB) BI 70D3 13C5 BI 70D3 13C5 BI 70D3 13B3 BI 70D3 13B3 BI 70D3 13B3 BI 70C3 13C5 BI 70C3 13C5 BI 70C3 13C5 BI 70C3 13C5 BI 70C3 13C5 BI 70C3 13C5 BI BI IN 29D3 75C3 70C3 13C5 IN 29D3 75C3 70C3 13C5 BI 70C3 13C5 BI 70C3 13C5 BI 70C3 13C5 BI 70C3 13C5 BI 70C3 13C5 BI 70C3 13C5 BI =PP1V05_S0_CPU NC 1% 1/16W MF-LF 402 7C7 9B5 9C5 9D5 10C7 11A3 12B3 12C5 70C3 13C5 BI 70C3 13C5 BI 70C3 13B3 BI 70C3 13B3 BI 70C3 13B3 BI FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_DSTB_L_N FSB_DSTB_L_P FSB_DINV_L E22 F24 E26 G22 F23 G25 E25 E23 K24 G24 J24 J23 H22 F26 K22 H23 J26 H26 H25 FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_DSTB_L_N FSB_DSTB_L_P FSB_DINV_L N22 K25 P26 R23 L23 M24 L22 M23 P25 P23 P22 T24 R24 L25 T25 N25 L26 M26 N24 0.5" MAX LENGTH FOR CPU_GTLREF 70B3 CPU_GTLREF CPU_TEST1 CPU_TEST2 TP_CPU_TEST3 CPU_TEST4 TP_CPU_TEST5 NOSTUFF TP_CPU_TEST6 C1000 AD26 C23 D25 C24 AF26 AF1 A26 D0* D1* D2* D3* D4* D5* D6* D7* D8* D9* D10* D11* D12* D13* D14* D15* DSTBN0* DSTBP0* DINV0* D16* D17* D18* D19* D20* D21* D22* D23* D24* D25* D26* D27* D28* D29* D30* D31* DSTBN1* DATBP1* DINV1* GTLREF TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 U1000 MEROM FCBGA OF PLACE C1000 CLOSE TO CPU_TEST4 PIN MAKE SURE CPU_TEST4 IS REFERENCED TO GND 54.9 1% 1/16W MF-LF 402 10% 16V X5R 402 70B3 29C6 OUT 70B3 29B6 OUT 70B3 29A6 OUT CPU_BSEL CPU_BSEL CPU_BSEL B22 B23 C21 D32* D33* D34* D35* D36* D37* D38* D39* D40* D41* D42* D43* D44* D45* D46* D47* DSTBN2* DSTBP2* DINV2* D48* D49* D50* D51* D52* D53* D54* D55* D56* D57* D58* D59* D60* D61* D62* D63* DSTBN3* DSTBP3* DINV3* COMP0 COMP1 COMP2 COMP3 MISC DPRSTP* DPSLP* DPWR* PWRGOOD SLP* PSI* 0.1uF R1024 PLACEMENT_NOTE=Place R1024 near ITP connector (if present) BI 9B7 12B3 70B3 1% 1/16W MF-LF 402 BI 70D3 13D5 IN 1% 1/16W MF-LF 402 54.9 BI BI 1% 1/16W MF-LF 402 =PP1V05_S0_CPU 70D3 13D5 70D3 13D5 1K 54.9 BI 70D3 13D5 12B2 70A3 R1005 B1 BI 70D3 13D5 9A7 12B2 12B3 70B3 12C5 12B3 11A3 10C7 9D5 9C5 9B6 7C7 NC 70D3 13D5 IN H CLK R1021 70B3 12B5 9C6 70D3 13D5 5% 1/16W MF-LF 402 PROCHOT* THERMDA THERMDC RSVD0 RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 RSVD6 RSVD7 RSVD8 RSVD9 XDP_TDO BI 2.0K 70B3 12B3 9C6 70D3 13D5 54.9 THERMAL R1020 XDP_TMS BI R1003 R1006 70B3 12B2 9C6 7C7 9B5 9B6 9D5 10C7 11A3 12B3 12C5 70D3 13D5 68 A20M* FERR* IGNNE* STPCLK* LINT0 LINT1 SMI* G5 DATA GRP BI OF FSB_ADS_L FSB_BNR_L FSB_BPRI_L H1 E2 DATA GRP BI 70C3 13D3 M3 FCBGA DATA GRP 70C3 13D3 K5 ADS* BNR* BPRI* MEROM DATA GRP BI L4 CONTROL 70C3 13D3 L5 U1000 XDP/ITP SIGNALS BI A3* A4* A5* A6* A7* A8* A9* A10* A11* A12* A13* A14* A15* A16* ADSTB0* ADDR GROUP0 BI 70C3 13D3 J4 ADDR GROUP1 70C3 13D3 FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_ADSTB_L ICH BI RESERVED D 70C3 13D3 BSEL0 BSEL1 BSEL2 FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_DSTB_L_N FSB_DSTB_L_P FSB_DINV_L Y22 AB24 V24 V26 V23 T22 U25 U23 Y25 W22 Y23 W24 W25 AA23 AA24 AB25 Y26 AA26 U22 FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_DSTB_L_N FSB_DSTB_L_P FSB_DINV_L AE24 AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21 AC22 AD23 AF22 AC23 AE25 AF24 AC20 R26 U26 AA1 Y1 E5 B5 D24 D6 D7 AE6 BI 13C5 70C3 BI 13C5 70C3 BI 13C5 70C3 BI 13C5 70C3 BI 13C5 70C3 BI 13C5 70C3 BI 13C5 70C3 BI 13B5 70C3 BI 13B5 70C3 BI 13B5 70C3 BI 13B5 70C3 BI 13B5 70C3 BI 13B5 70C3 BI 13B5 70C3 BI 13B5 70C3 BI 13B5 70C3 BI 13B3 70C3 BI 13A3 70C3 BI 13B3 70C3 BI 13B5 70C3 BI 13B5 70C3 BI 13B5 70C3 BI 13B5 70C3 BI 13B5 70C3 BI 13B5 70C3 BI 13B5 70C3 BI 13B5 70C3 BI 13B5 70C3 BI 13B5 70C3 BI 13B5 70C3 BI 13B5 70C3 BI 13B5 70C3 BI 13B5 70C3 BI 13B5 70C3 BI 13B5 70C3 BI 13B3 70C3 BI 13A3 70C3 BI 13B3 70C3 C LAYOUT NOTE: COMP0,2 CONNECT WITH ZO=27.4OHM, MAKE TRACE LENGTH SHORTER THAN 0.5" COMP1,3 CONNECT WITH ZO=55OHM, MAKE TRACE LENGTH SHORTER THAN 0.5" R1016 27.4 R1017 54.9 CPU_COMP 70B3 CPU_COMP 70B3 CPU_COMP 70B3 CPU_COMP 1% 1/16W MF-LF 402 1% 1/16W MF-LF 402 R1018 R1019 1% 1/16W MF-LF 402 B 27.4 70B3 CPU_DPRSTP_L CPU_DPSLP_L FSB_DPWR_L CPU_PWRGD FSB_CPUSLP_L CPU_PSI_L 54.9 IN 15B6 22C4 59C7 70B3 IN 22C4 70B3 IN 13B3 70D3 IN 12B1 22C4 70C3 IN 13A5 70B3 OUT 1% 1/16W MF-LF 402 27B3 NOSTUFF R1030 R1022 70B3 12B3 12B2 9C6 54.9 XDP_TCK R1023 70A3 12B3 9C6 649 XDP_TRST_L NOSTUFF R1012 1% 1/16W MF-LF 402 5% 1/16W MF-LF 402 NOSTUFF 1K 5% 1/16W MF-LF 402 1% 1/16W MF-LF 402 R1007 1K 2 5% 1/16W MF-LF 402 CPU FSB A SYNC_MASTER=T9_MLB_NOME SYNC_DATE=11/12/2006 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE D APPLE INC DRAWING NUMBER SCALE SHT NONE REV 051-7455 OF 76 01 A A4 P6 A8 P21 (CPU CORE POWER) OMIT A11 =PPVCORE_S0_CPU D A14 7D7 10B5 11D7 48B3 48B5 Standard Voltage: Low Voltage: Ultra Low Voltage: 44.0 A (Design Target) 23.0 A (Design Target) 17.0 A (Design Target) 41.0 A (HFM) 30.4 A (LFM) 25.5 A (SuperLFM) 21.0 A (HFM) 18.7 A (LFM) TBD A (SuperLFM) TBD TBD OMIT A9 AB7 A10 U1000 AC7 A12 MEROM AC9 A13 FCBGA AC12 A15 OF AC13 A17 AC15 A18 AC17 A20 AC18 B7 AD9 B10 AD10 B12 AD12 B14 A16 B15 AD15 B17 AD17 A (HFM) A (LFM) R25 AF2 T1 B6 T4 D TBD TBD A (Auto-Halt/Stop-Grant HFM) A (Auto-Halt/Stop-Grant SuperLFM) TBD TBD A (Auto-Halt/Stop-Grant HFM) A (Auto-Halt/Stop-Grant LFM) 27.4 A (Sleep HFM) 16.8 A (Sleep SuperLFM) TBD TBD A (Sleep HFM) A (Sleep SuperLFM) TBD TBD A (Sleep HFM) A (Sleep LFM) B8 T23 B11 T26 B13 U3 B16 U6 B19 U21 B21 U24 B24 25.0 A (Deep Sleep HFM) 16.0 A (Deep Sleep SuperLFM) TBD TBD A (Deep Sleep HFM) A (Deep Sleep SuperLFM) TBD TBD A (Deep Sleep HFM) A (Deep Sleep LFM) V2 C5 V5 C8 11.5 A (Deeper Sleep) TBD A (Deeper Sleep) TBD A (Deeper Sleep) V22 C11 V25 C14 TBD A (Enhanced Deeper Sleep) TBD A (Enhanced Deeper Sleep) W1 C16 W4 C19 W23 C2 W26 AD18 B20 VCC AE10 C10 AE12 C12 C22 Y3 C25 Y6 AE9 C9 D1 Y21 D4 Y24 D8 AA2 D11 AA5 D13 AA8 D16 AA11 D19 AA14 D23 AA16 D26 AA19 E3 AA22 AE13 C13 AE15 C15 AE17 C17 AE18 C18 AE20 D9 AF9 C AF10 D10 AF12 D12 AF14 D14 VCC E6 AA25 E8 AB1 E11 AB4 AF15 AF17 D17 D18 AF18 E7 AF20 (CPU IO POWER 1.05V) E14 =PP1V05_S0_CPU E9 E10 VSS VSS AB8 E16 AB11 E19 AB13 E21 AB16 E24 AB19 F5 AB23 F8 AB26 7C7 9B5 9B6 9C5 9D5 11A3 12B3 12C5 G21 E12 V6 E13 J6 E15 K6 E17 4500 mA (before VCC stable) 2500 mA (after VCC stable) M6 E18 J21 E20 K21 VCCP F9 F11 AC3 F13 AC6 F16 AC8 F19 AC11 F2 AC14 F22 AC16 F25 AC19 G4 AC21 G1 AC24 M21 N21 F10 N6 F12 R21 F14 R6 F15 T21 F17 T6 F18 G23 AD2 G26 AD5 H3 AD8 V21 (CPU INTERNAL PLL POWER 1.5V) F20 W21 =PP1V5_S0_CPU AA7 7C7 11B3 H6 AD11 H21 AD13 H24 AD16 J2 AD19 J5 AD22 J22 AD25 J25 AE1 K1 AE4 K4 AE8 B26 AA9 AA10 R22 OF A23 AD14 B18 B R5 FCBGA A19 27.4 A (Auto-Halt/Stop-Grant HFM) 17.0 A (Auto-Halt/Stop-Grant SuperLFM) 9.4 A (Enhanced Deeper Sleep) F7 R2 MEROM AD7 B9 D15 P24 U1000 AB20 A7 C VCCA 130 mA B C26 AA12 AA13 AA15 AA17 AA18 AA20 AB9 AC10 VID0 VID1 VID2 VID3 VID4 VID5 VID6 AD6 AF5 AE5 AF4 AE3 AF3 AE2 CPU_VID CPU_VID CPU_VID CPU_VID CPU_VID CPU_VID CPU_VID OUT 59C7 70A3 OUT 59C7 70A3 OUT 59C7 70A3 OUT 59C7 70A3 OUT 59C7 70A3 OUT 59C7 70A3 OUT 59C7 70A3 =PPVCORE_S0_CPU R1100 100 AB10 AB12 AB14 7D7 10D7 11D7 48B3 48B5 1% 1/16W MF-LF 402 K23 AE11 K26 AE14 L3 AE16 L6 AE19 L21 AE23 L24 AE26 PLACEMENT_NOTE=Place within inch of CPU, no stub VCCSENSE AF7 CPU_VCCSENSE_P OUT 59A4 59A5 70A3 AB15 AB17 AB18 VSSSENSE AE7 CPU_VCCSENSE_N OUT M2 A2 M5 AF6 M22 AF8 M25 AF11 N1 AF13 N4 AF16 N23 AF19 N26 AF21 59A4 59A5 70A3 R1101 100 1% 1/16W MF-LF 402 PLACEMENT_NOTE=Place within inch of CPU, no stub P3 A25 AF25 CPU Power & Ground A SYNC_MASTER=T9_MLB_NOME SYNC_DATE=11/12/2006 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE D APPLE INC REV 051-7455 SCALE SHT NONE Current numbers from Merom for Santa Rosa EMTS, doc #22221 DRAWING NUMBER OF 10 76 01 A =PP5V_S0_LCD 7A7 PP5V_INV 100K 1% R9001 100K INV_PWREN_F_L Q9006 SSM3K15FV FERR-120-OHM-1.5A PPBUS_ALL_INV_CONN =PPBUS_S5_INV 6B1 1/16W MF-LF 402 D L9003 MIN_LINE_WIDTH=0.30 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=5V R9000 D INV_PWREN_L G VOLTAGE=12.6V MIN_LINE_WIDTH=0.30 MM MIN_NECK_WIDTH=0.20 MM 0402-LF NTK3142P SOT723-3 L9002 INVERTER CONNECTOR D FERR-120-OHM-1.5A 1% 1/16W MF-LF 402 D SOD-VESM 7B1 Q9005 S CRITICAL J9000 0402-LF 78171-0004 G 14D5 IN C9014 S 0.0022UF LVDS_BKLT_EN M-RT-SM L9000 120-OHM-0.3A-EMI 6B1 10% 50V CERM 402 PP5V_INV_F 6B1 INV_BKLIGHT_PWM_L VOLTAGE=5V MIN_LINE_WIDTH=0.30 MM MIN_NECK_WIDTH=0.20 MM 0402-LF 6B1 L9001 INV_GND 120-OHM-0.3A-EMI 67B7 67B5 7C4 =PP3V3_S0_LCD 518S0521 0402-LF 27D4 23A6 14D5 PLT_RST_L LVDS_BKLT_CTL SOT665 A U9053Y 100PF 5% 5% 50V CERM 402 TC7SZ08AFEF C90021 C90031 C9000 C9001 100PF 100PF 100PF CRITICAL 50V CERM 402 BKLIGHT_CTL 5% 5% 50V CERM 50V CERM 402 402 B C90591 0.1UF INVT_CHGND 10% 16V X5R 402 8D8 THIS GND CONECTS TO CHASSIS GND C C =PP3V3_S5_LCD CRITICAL Q9003 R9002 5% 1/16W MF-LF 402 Q9004 D SOD-VESM CONNECTOR PP3V3_LCDVDD_SW G LCDVDD_PWREN_L SSM3K15FV R9023 10K S 5% 1/16W MF-LF 402 LCD + CAMERA FDC606P SOT-6 100K D 7D1 C9011 0.1UF 0.001UF C9012 10UF 20% 6.3V X5R 603 10% 16V X5R 402 LCDVDD_PWREN_L_R C9009 VOLTAGE=3.3V MIN_LINE_WIDTH=0.30 MM MIN_NECK_WIDTH=0.20 MM CRITICAL J9001 S-050162B F-RT-SM 10% 50V CERM 402 25 C9013 0.0033UF 1 G 14D5 IN S 67A6 67A4 67A2 8C8 =PP3V3_S0_LCD 10% 50V CERM 402 LVDS_VDD_EN 5% 1/16W MF-LF 2402 1% 1/16W MF-LF 402 14D5 14D5 67C6 67B5 7C4 5% 1/16W MF-LF 2402 67C6 VOLTAGE=3.3VMIN_LINE_WIDTH=0.30 MIN_NECK_WIDTH=0.20 MM MM 0402-LF L9008 67B7 67B5 7C4 PP3V3_S0_LCD_F (LVDS DDC POWER) VOLTAGE=3.3V MIN_LINE_WIDTH=0.25 MIN_NECK_WIDTH=0.20 MM MM 120-OHM-0.3A-EMI =PP3V3_S0_LCD 0402-LF LVDS_DDC_CLK LVDS_DDC_DATA CRITICAL L9006 90-OHM-200MA SM =PP3V3_S0_LCD CRITICAL NOSTUFF 5% 1/16W MF-LF 402 SM 5% 1/16W MF-LF LVDS_CTRL_CLK 14D5 12B1 LVDS_CTRL_DATA 71D3 14C5 SYM_VER-1 8C2 2402 8C2 14D5 12B1 IO LVDS_A_CLK_N1 IO LVDS_A_CLK_P2 L9007 90-OHM-200MA R9015 R9016 10K 10K 71D3 14C5 IO 71D3 14C5 IO 71D3 14C5 IO 71D3 14C5 IO 71D3 14C5 IO 71D3 14C5 IO SYM_VER-1 71D3 14C5 NOSTUFF IO IO =USB2_CAMERA_P =USB2_CAMERA_N LVDS_A_DATA_N LVDS_A_DATA_P LVDS_A_DATA_N LVDS_A_DATA_P LVDS_A_DATA_N LVDS_A_DATA_P LVDS_A_CLK_F_N LVDS_A_CLK_F_P USB2_CAMERA_CONN_P USB2_CAMERA_CONN_N L9005 FERR-120-OHM-1.5A 7A4 =PP5V_S3_CAMERA PP5V_S3_CAMERA_F L9010 FERR-1000-OHM OUT MIC_LO_LVDS MIC_LO_LVDS_CONN 0402NOSTUFF OUT MIC_HI_LVDS C90161 MIC_HI_LVDS_CONN C9010 C90151 0.001UF 10% 50V 50V CERM 402 67A2 0.001UF 10% 50V CERM 402 CERM 402 67A4 =GND_CHASSIS_LVDS LVDS REFERENCE CURRENT,2.37K OHM PULL DOWN RESISTOR NEEDED MIC_SHIELD_LVDS1 OUT 71C3 14D5 LVDS_IBG R9013 2.37K =GND_CHASSIS_LVDS 0402 NOSTUFF NOSTUFF CRITICAL CRITICAL 2 1% 1/16W MF-LF 402 DZ9000 DZ9001 8V-100PF 8V-100PF 402-1 402-1 26 INVERTER,LVDS,TMDS NOTICE OF PROPRIETARY PROPERTY 0.001UF 10% 50V CERM 402 2 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT 67B2 67A4 67A2 8C8 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE =GND_CHASSIS_LVDS D APPLE INC DRAWING NUMBER REV 051-7455 SCALE SHT NONE CAMERA I/F SYNC_MASTER=GPU SYNC_DATE=06/23/2006 C90081 8C8 67A2 67A6 67B2 LCD I/F Plexi: 516S0212 *Enclosure: 518S0364 0402NOSTUFF L9012 FERR-1000-OHM MIC_LO_LVDS_CONN MIC_HI_LVDS_CONN B 24 67B2 67A6 67A4 8C8 0.001UF 10% L9011 FERR-1000-OHM 67A4 VOLTAGE=5V MIN_NECK_WIDTH=0.20 MM MIN_LINE_WIDTH=0.30 MM 0402-LF NOSTUFF A 10 11 12 13 14 15 16 17 18 19 20 21 22 PP3V3_LCDVDD_SW_F R9009 R9008 10K 10K R9014 100K 23 FERR-120-OHM-1.5A 7C4 67B5 67B7 67C6 1 B L9004 =GND_CHASSIS_LVDS OF 67 76 01 A L9206 L9201 FERR-120-OHM-1.5A 69C8 68D8 68C8 68B1 7C4 68B7 68B2 69C2 69B7 =PP3V3_S0_TMDS PP3V3_S0_ANALOG_TMDS_F VOLTAGE=3.3V MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.25MM 0402-LF C9236 0.001UF 10% 50V CERM 402 D 68B1 68B4 7B7 68D6 FERR-120-OHM-1.5A =PP1V8_S0_TMDS1 10% 50V CERM 402 0.1UF 10% 16V X5R 402 0.1UF C9207 0.1UF 10UF 10% 16V X5R 402 20% 6.3V X5R 603 10% 16V X5R 402 C9208 1C9209 0.001UF 10% 50V CERM 402 C9210 1C9211 0.001UF 10% 16V X5R 402 10% 50V CERM 402 0.1UF 10% 16V X5R 402 PP3V3_S0_ANALOG_SDVO_F 0.001UF 10% 50V CERM 402 68C4 68D6 7B7 =PP1V8_S0_TMDS C9230 C9231 0.001UF 0.1UF 10% 50V CERM 402 10% 16V X5R 402 R9207 R9237 1% 1/16W MF-LF 402 1% 1/16W MF-LF 402 TMDS_TX_P R9208 49.9 C9214 0.1UF C9200 0.001UF 10% 16V X5R 402 10% 50V CERM 402 C9201 0.001UF 10% 50V CERM 402 C9202 C9203 1 0.1UF 1% 1/16W MF-LF 402 68C4 C9204 6.3V X5R 603 R9209 R9239 1% 1/16W MF-LF 402 1% 1/16W MF-LF 402 49.92 TMDS_TX 149.92 TMDS_TX_P L9204 FERR-120-OHM-1.5A C9224 0.001UF PP3V3_S0_PVCC1_TMDS_F 10% 50V CERM 402 68C4 VOLTAGE=3.3V MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.25MM 0402-LF 68B2 69B2 1% 1/16W MF-LF 402 C9223 0.001UF ONE 0.1UF AND 1000PF FOR EACH PIN =PP3V3_S0_TMDS TMDS_TX_N D 10% 50V CERM 402 69B2 68B2 69C8 68D8 68C8 68B1 7C4 68B7 68B2 69C2 69B7 68B2 69B2 10UF 20% 0.1UF 10% 16V X5R 402 10% 16V X5R 402 TMDS_TX_N R9238 TMDS_TX 149.92 VOLTAGE=1.8V MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.25MM 68B2 69B2 10% 50V CERM 402 20% 6.3V X5R 603 PP1V8_S0_ANALOG_SDVO_F 0402-LF C9222 TMDS_TX_N 0.001UF 10UF 69B2 68B2 TMDS_TX_P 149.92 TMDS_TX 149.92 ONE 0.1UF AND 1000PF FOR EACH PIN VOLTAGE=3.3V MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.25MM 0402-LF 68B2 69B2 C9212 C9213 L9200 FERR-120-OHM-1.5A 1 0.1UF ONE 0.1UF AND 1000PF FOR EACH PIN =PP3V3_S0_TMDS 68B4 VOLTAGE=1.8V MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.25MM C9237 1C9238 1C9239 C9240 0.001UF PP1V8_S0_TMDS_F 0402-LF L9203 FERR-120-OHM-1.5A 69C8 68D8 68C8 68B1 7C4 68B7 68B2 69C2 69B7 C9232 C9233 0.001UF 0.1UF 10% 50V CERM 402 10% 16V X5R 402 C9206 R9210 0.1UF 10% 16V X5R 402 69A2 68B2 49.92 TMDS_TX_CLK_P R9240 49.92 TMDS_TX_CLK_N TMDS_TX_CLK 1% 1/16W MF-LF 402 68B2 69A2 1% 1/16W MF-LF 402 C9225 0.001UF 10% 50V CERM 402 L9205 FERR-120-OHM-1.5A 68C4 PLACE THE CAP NEAR THE NB SIDE IN 71D3 14B3 IN 71D3 14C3 IN 71D3 14B3 IN 71D3 14B3 IN 68D3 68C7 PEG_R2D_C_N PEG_R2D_C_P PEG_R2D_C_N PEG_R2D_C_P PEG_R2D_C_N 68C6 68D6 68B1 68D3 PP3V3_S0_ANALOG_SDVO_F PP1V8_S0_ANALOG_SDVO_F PP3V3_S0_PVCC2_TMDS_F PP3V3_S0_PVCC1_TMDS_F PP3V3_S0_ANALOG_TMDS_F PP1V8_S0_TMDS_F 0.1UF 10% 16V X5R 402 TMDS_SDR_P37 SDR_P =PP3V3_S0_TMDS 14C3 71D3 OUT R9201 2.94K PLACE R9200,U9201 CLOSE TO MINI DVI CONN J9401 CRITICAL R9200 5.5V 69C6 IN TMDS_HTPLG TOL INPUT 10K 2TMDS_HTPLG_R 5% 1/16W MF-LF 402 U9201 74LVC1G17DRL 1/16W MF-LF 402 1 2.94K 1% 1/16W MF-LF 402 OUT PEG_D2R_N 10% 16V X5R 402 TMDS_INT_P TMDS_INT_N 32 33 TMDS_EXT_RES 35 TMDS CHIP SDVO INPUT INTERRUPT SIGNAL TO MCH 27D1 IO 15A3 IO 15A3 SOT-553 TMDS_RST_L SDVO_CTRLCLK SDVO_CTRLDATA TMDS_HTPLG_BUF IF ADDRESS=0X70 NC HIGH, ADDRESS=0X72 29 3.3V ACTIVE OUTPUT NC R9200 INSURES ESD DIODE R9213 270K CURRENT IS SMALL 5% 1% 1/16W MF-LF 402 R9202 PEG_D2R_P 0.1UF R9211 R9212 9.09K 9.09K 1% 1/16W MF-LF 402 1% 1/16W MF-LF 402 DVI_HOTPLUG_DET R9203 23A6 68B8 1K 5% SDG_N SDB_P SDVO RCVR CORE SDB_N TXC_P TXC_N EXT_SWING 25 TX1_P TX1_N TX2_P DIFF SIG DATA TX2_N SDC_P SDC_N 10UF 20% 6.3V X5R 603 PP3V3_S0_ANALOG_TMDS_F 69B2 68D3 69B2 68D1 69B2 68D3 69B2 68D1 69B2 68C3 69B2 68C1 69A2 68C3 69A2 68C1 TMDS_TX_P OUT TMDS_TX_N OUT TMDS_TX_P OUT TMDS_TX_N OUT TMDS_TX_P OUT TMDS_TX_N OUT TMDS_TX_CLK_P OUT TMDS_TX_CLK_N OUT I2C MASTER INTER SCLDDC SDADDC EXT_RES RESET* SDSCL SDSDA 68B4 68D6 R9204 249 1% 1/16W MF-LF 2402 CONFIG/ PRGRM TEXT MODE =PP3V3_S0_TMDS B 7C4 68B2 68B7 68C8 68D8 69B7 69C2 69C8 R9205 R9206 10K 10K TMDS_EXT_SWING SDI_P SDI_N TMDS_I2C_SCL TMDS_I2C_SDA 5% 1/16W MF-LF 2402 5% 1/16W MF-LF 2402 TMDS_I2C_SCL AND TMDS_I2C_SDA DON’T NEED TO CONNECT TEST 30 A1 HTPLG SPGND 69C8 69C2 69B7 68D8 68C8 68B2 68B1 7C4 TMDS_SDC_P46 TMDS_SDC_N47 C9220 SDG_P SGND1 0.1UF 10% 16V X5R 402 402 17 16 20 19 23 22 14 13 C9219 0.1UF 10% 16V X5R TX0_P TX0_N LQFP SGND0 B U9200 SIL1362ACLU SDR_N 39 45 TMDS_SDR_N38 TMDS_SDG_P40 TMDS_SDG_N41 TMDS_SDB_P43 TMDS_SDB_N44 7C4 68B1 68B7 68C8 68D8 69B7 69C2 69C8 C92211 C9205 CRITICAL PGND2 0.1UF 0.1UF 10% 10% 16V 16V X5R X5R 402 402 27 0.1UF 0.1UF 10% 10% 16V 16V X5R X5R 402 402 AGND2 0.1UF 10% 16V X5R 402 VCC2 C92431 C92441 C9245 C92461 C92471 C9248 AGND0 AGND1 "Place R9250 near U2300.F12" 5% 1/16W MF-LF 2402 VCC0 C92411 C92421 0.1UF 0.1UF 10% 10% 16V 16V X5R X5R 402 402 12 18 24 100K GND0 GND1 R9250 VCC1 10 28 34 DVI_HOTPLUG_DET =PP3V3_S0_TMDS 71D3 14C3 68D6 48 IN PEG_R2D_C_P OVCC PEG_R2D_C_N SPVCC IN 71D3 14B3 36 42 0.1UF 10% 16V X5R 402 SVCC0 SVCC1 71D3 14C3 0.001UF 10% 50V CERM 402 11 26 PEG_R2D_C_P PVCC2 C9235 IN PVCC1 C9234 71D3 14B3 15 21 VOLTAGE=3.3V MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.25MM 0402-LF C MCH SDVO CHANNEL R,G,B,CLK SIGNAL TO TMDS CHIP PP3V3_S0_PVCC2_TMDS_F AVCC0 AVCC1 =PP3V3_S0_TMDS 69C2 69B7 68B2 68B1 7C4 68D8 68C8 68B7 69C8 31 C 1/16W MF-LF 2402 EXTERNAL TMDS SYNC_MASTER=GRAPHIC SYNC_DATE=06/06/2005 A NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE D APPLE INC DRAWING NUMBER SCALE SHT NONE REV 051-7455 OF 68 76 01 A NB VIDEO ALIASES CRT_TVO_IREF TV_A_DAC TV_B_DAC TV_C_DAC =CRT_TVO_IREF =TV_A_DAC =TV_B_DAC =TV_C_DAC 14A5 14C5 14B5 14B5 71C3 14B5 69D8 =CRT_BLUE CRT_BLUE =CRT_GREEN CRT_GREEN =CRT_RED CRT_RED =CRT_HSYNC_R =CRT_VSYNC_R CRT_HSYNC_R CRT_VSYNC_R 69B8 71C3 MAKE_BASE=TRUE MAKE_BASE=TRUE 69B8 71C3 MAKE_BASE=TRUE 14B5 69A8 71C3 MAKE_BASE=TRUE MAKE_BASE=TRUE 69A8 71C3 MAKE_BASE=TRUE 14B5 Video Connectors EXTERNAL VIDEO (VGA) INTERFACE 69A8 71C3 MAKE_BASE=TRUE 14B5 D 14A5 69C3 71C3 MAKE_BASE=TRUE D 69C3 71C3 MAKE_BASE=TRUE Isolation required for DVI power switch TMDS(MINI DVI) INTERFACE A 1.3K OHM 1% RESISTOR IS REQUIRED BETWEEN CRT_IREF AND GROUND 71C3 69D7 R9469 1.21K CRT_TVO_IREF 7A7 D9401 CRITICAL 1SS418 F9404 L9444 600-OHM-300MA SOD-723 0.5AMP-13.2V PP5V_S0_TMDS_FUSE 2 =PP5V_S0_TMDS VOLTAGE=5V MIN_LINE_WIDTH=0.30 MM MIN_NECK_WIDTH=0.20 MM 1% 1/16W MF-LF 402 PP5V_S0_DVIPORT VOLTAGE=5V MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.25 MM SM-LF 0402 =PP3V3_S0_TMDS 20% 10V CERM 402 =PP3V3_S0_NB PART NUMBER ALTERNATE FOR PART NUMBER BOM OPTION REF DES 740S0044 740S0028 ? F9404 CRITICAL 8C8 69A4 R9460 39 CRT_HSYNC_R1 71C3 69D5 R9466 R9467 2.2K 5% 1/16W MF-LF 2402 C 14B5 TV_DCONSEL 14B5 TV_DCONSEL 1/16W MF-LF 402 69C2 69B7 68D8 68C8 68B7 68B2 68B1 7C4 R9463 2.2K 5% 1/16W MF-LF 2402 125 Y R9470 CRT_HSYNC_LS 39 VGA_HSYNC 5% 1/16W MF-LF 402 GND R9461 39 71C3 69D5 CRT_VSYNC_R TMDS_HTPLG U9404 SN74LVC2G125DCU R9471 39 US 125 Y CRT_VSYNC_LS 1 Q9401 50V CERM C9410 402 GPU_CRT_DDC_CLK SSM6N15FE 5% 50V CERM 402 S OMIT CRITICAL PLACE R9450 R9451 CLOSE TO GMCH TV_A_DAC CRT_BLUE 50V CERM 402 14B5 14B5 1% 1/16W MF-LF 2402 NC NC 69C8 69C2 68B2 68B1 7C4 68D8 68C8 68B7 =PP3V3_S0_TMDS C9439 EXT_COMPVID_B 0.1UF 10% =TV_A_RTN 69C1 16V X5R 402 =CRT_BLUE_L CRITICAL 16 FL9400 210MHZ VGA_G 69C1 VGA_VSYNC MEA2010P-SM VGA_B VGA_HSYNC 26 18 27 19 28 20 29 30 22 31 VCC TV_B_DAC CRT_GREEN R9452 1R9453 75 1% 75 1% 1/16W MF-LF 2402 14B5 14B5 1/16W MF-LF 402 =TV_B_RTN S1A S1B S2B 11 10 S1C 14 13 S1D DA U9401 S2A S2C SOP DB 7 VGA_R EXT_Y_G 32 24 TMDS_TX_CONN_P S2D DC DD 12 IN EN_L 15 TMDS_TX_CONN_N 69D7 71C3 69D5 71C3 TMDS_TX_N 68B2 68D1 B CRITICAL TMDS_TX_CONN_P L9406 90-OHM-100MA 1210-4SM1 TMDS_TX_CONN_N TMDS_TX_P 68B2 68D3 TMDS_TX_N 68B2 68D1 TMDS_TX_CONN_CLK_P TMDS_TX_CONN_CLK_N SYM_VER-1 CRITICAL L9404 300-OHM-50MA 1210-4SM 514-0376 CRITICAL 69C4 8C8 =GND_CHASSIS_TMDS_UPPER 8A6 =GND_CHASSIS_TMDS_DOWN EXT_C_R TMDS_TX_CLK_P 68B2 68C3 TMDS_TX_CLK_N 68B2 68C1 SYM_VER-1 C9421 0.1UF 10% 16V X5R 402 MINI-DVI CONNECTOR SYNC_MASTER=EUGENESYNC_DATE=05/21/05 NOTICE OF PROPRIETARY PROPERTY TV_C_DAC THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING CRT_RED R9454 1R9455 75 1% 1/16W MF-LF 402 14B5 14B5 68B2 68D3 SYM_VER-1 PLACE R9454 R9455 CLOSE TO GMCH A TMDS_TX_P TMDS_TX_CONN_P GND =CRT_GREEN_L 68B2 68C1 L9407 90-OHM-100MA 1210-4SM1 TMDS_TX_CONN_N 33 34 35 36 69D7 71C3 69D5 71C3 TS3V330 PLACE R9452 R9453 CLOSE TO GMCH TMDS_TX_N CRITICAL 10 11 12 13 14 15 16 25 PP5V_S0_DVIPORT 17 68B2 68C3 SYM_VER-1 F-RT-TH 69D4 TMDS_TX_P MINI-DVI-M42-BLK 1% 1/16W MF-LF 2402 J9401 C9412 100PF 5% 69D7 71C3 71C3 69D5 R9450 R9451 75 75 L9405 90-OHM-100MA 1210-4SM1 GPU_CRT_DDC_DATA B CRITICAL 100PF SOT563 NOTE: CRT_DDC_* ARE NOT 5V COMPLIANT C9411 Q9401 D G SSM6N15FE SOT563 14B5 C9443 33PF 10% 50V CERM 402 G CRT_DDC_DATA 1/16W MF-LF 4022 D IO 2.2K 5% S IO CRT_DDC_CLK 69B4 NOSTUFF 0.001UF 14B5 VGA_VSYNC 5% 1/16W MF-LF 402 GND C 5% R94211 R94221 1/16W MF-LF 4022 C9442 33PF 5% VCC A CRT_VSYNC_LS_R 5% 1/16W MF-LF 402 =PP3V3_S0_TMDS 2.2K 5% 69B4 NOSTUFF 402 PLACE THE RESISTOR CLOSE TO GMCH AND THE CAP NEAR THE CONNECTOR CRITICAL 5% 1/16W MF-LF 4022 20% 10V CERM 402 50V CERM DVI power DIODE on page 95 (D9500) R9462 2.2K C9460 US VCC A CRT_HSYNC_LS_R 5% 1/16W MF-LF 402 PP5V_S0_DVIPORT_D 2.2K 5% 68A8 U9404 SN74LVC2G125DCU COMMENTS: TABLE_ALT_ITEM 7C4 68B1 68B2 68B7 68C8 68D8 69B7 69C8 0.1UF =GND_CHASSIS_TMDS_UPPER TABLE_ALT_HEAD 7C4 C9404 0.1UF PLACE THE RESISTOR CLOSE TO GMCH AND THE CAP NEAR CONNECTOR 69B4 VOLTAGE=5V MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.25 MM I TO MAINTAIN THE DOCUMENT IN CONFIDENCE 75 1% II NOT TO REPRODUCE OR COPY IT SB_CRT_TVOUT_MUX_L 1/16W MF-LF 2402 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART 24D2 TABLE_5_HEAD CRITICAL BOM OPTION 514-0480 PART# QTY DESCRIPTION CONN,REC,MINI-DVI,32P,RA,TABS,MG3 REFERENCE DESIGNATOR(S) J9401 CRITICAL NORMAL 514-0481 CONN,REC,MINI-DVI,32P,RA,TABS,BLK J9401 CRITICAL FANCY =TV_C_RTN SIZE D TABLE_5_ITEM =CRT_RED_L TABLE_5_ITEM APPLE INC DRAWING NUMBER SCALE SHT NONE REV 051-7455 OF 69 76 01 A FSB (Front-Side Bus) Constraints CPU / FSB Net Properties NET_TYPE TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP FSB_55S * Y =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING TABLE_PHYSICAL_RULE_ITEM FSB_COMMON FSB_55S FSB_COMMON FSB_COMMON FSB_55S FSB_COMMON TABLE_PHYSICAL_RULE_ITEM FSB_DSTB_55S * Y =55_OHM_SE =55_OHM_SE =55_OHM_SE =1:1_DIFFPAIR =1:1_DIFFPAIR TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING TABLE_SPACING_RULE_HEAD WEIGHT SPACING_RULE_SET LAYER LINE-TO-LINE SPACING * =3:1_SPACING FSB_DATA * =3:1_SPACING ? TABLE_SPACING_RULE_ITEM D * =2:1_SPACING ? FSB_ADSTB * =3:1_SPACING ? TABLE_SPACING_RULE_ITEM FSB_DATA2DATA * =2:1_SPACING ? FSB_DSTB * =3:1_SPACING ? TABLE_SPACING_RULE_ITEM * =3:1_SPACING FSB_COMMON FSB_COMMON FSB_55S FSB_COMMON FSB_COMMON FSB_55S FSB_COMMON FSB_COMMON FSB_55S FSB_COMMON FSB_COMMON FSB_55S FSB_COMMON FSB_COMMON FSB_55S FSB_COMMON FSB_COMMON FSB_55S FSB_COMMON FSB_COMMON FSB_55S FSB_COMMON FSB_COMMON FSB_55S FSB_COMMON FSB_COMMON FSB_55S FSB_COMMON FSB_CPURST_L FSB_55S FSB_COMMON FSB_DATA_GROUP0 FSB_55S FSB_DATA FSB_DATA_GROUP0 FSB_55S FSB_DATA FSB_DSTB0 FSB_DSTB_55S FSB_DSTB FSB_DSTB_55S FSB_DSTB FSB_DATA_GROUP1 FSB_55S FSB_DATA FSB_DATA_GROUP1 FSB_55S FSB_DATA FSB_DSTB1 FSB_DSTB_55S FSB_DSTB FSB_DSTB_55S FSB_DSTB TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM FSB_ADDR2ADSTB FSB_COMMON FSB_55S TABLE_SPACING_RULE_ITEM ? FSB_ADDR2ADDR FSB_55S WEIGHT TABLE_SPACING_RULE_ITEM FSB_ADDR FSB_COMMON FSB_COMMON TABLE_SPACING_RULE_ITEM ? FSB_DATA2DSTB * =3:1_SPACING ? TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM FSB_COMMON * =2:1_SPACING ? TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET FSB_ADDR FSB_ADDR * FSB_ADDR2ADDR TABLE_SPACING_ASSIGNMENT_ITEM FSB_ADS_L FSB_BNR_L FSB_BPRI_L FSB_BREQ0_L FSB_DBSY_L FSB_DEFER_L FSB_DPWR_L FSB_DRDY_L FSB_HIT_L FSB_HITM_L FSB_LOCK_L FSB_RS_L FSB_TRDY_L FSB_CPURST_L FSB_D_L FSB_DINV_L FSB_DSTB_L_P FSB_DSTB_L_N 9D6 13C3 9D6 13C3 9D6 13C3 9D6 13B3 9D6 13B3 9D6 13B3 9B2 13B3 9D6 13B3 D 9C6 13B3 9C6 13B3 9D6 13B3 9D6 13A3 9D6 13B3 9D6 12B5 13A5 9C4 13C5 13D5 9C4 13B3 9C4 13B3 9C4 13B3 TABLE_SPACING_ASSIGNMENT_ITEM FSB_ADDR FSB_ADSTB * FSB_ADDR2ADSTB FSB_DATA FSB_DATA * FSB_DATA2DATA FSB_DATA FSB_DSTB * FSB_DATA2DSTB TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM All FSB signals with impedance requirements are 55-ohm single-ended Worst-case spacing is 2:1 within Addr bus, with 3:1 spacing to the ADSTBs Worst-case spacing is 2:1 within Data bus, with 3:1 spacing to the DSTBs DSTB complementary pairs are spaced 1:1 and routed as differential pairs FSB_DATA_GROUP2 FSB_55S FSB_DATA FSB_DATA_GROUP2 FSB_55S FSB_DATA FSB_DSTB2 FSB_DSTB_55S FSB_DSTB FSB_DSTB_55S FSB_DSTB Design Guide recommends each strobe/signal group is routed on the same layer Design Guide recommends FSB signals be routed only on internal layers FSB_DATA_GROUP3 FSB_55S FSB_DATA FSB_DATA_GROUP3 FSB_55S FSB_DATA FSB_DSTB3 FSB_DSTB_55S FSB_DSTB FSB_DSTB_55S FSB_DSTB FSB_ADDR_GROUP0 FSB_55S FSB_ADDR FSB_ADDR_GROUP0 FSB_55S FSB_ADDR FSB_ADSTB0 FSB_55S FSB_ADSTB FSB_ADDR_GROUP1 FSB_55S FSB_ADDR FSB_ADSTB1 FSB_55S FSB_ADSTB CPU_IERR_L CPU_55S CPU_FERR_L CPU_55S CPU_PROCHOT_L CPU_55S CPU_PWRGD CPU_55S CPU_FROM_SB CPU_55S CPU_FROM_SB CPU_55S CPU_FROM_SB CPU_55S CPU_FROM_SB CPU_55S CPU_FROM_SB CPU_55S CPU_INIT_L CPU_55S CPU_FROM_SB CPU_55S CPU_FROM_SB CPU_55S PM_THRMTRIP_L CPU_55S FSB_CPUSLP_L CPU_55S PM_DPRSLPVR CPU_55S CPU_2TO1 (See above) CPU_55S CPU_2TO1 CPU_BSEL0 CPU_55S CPU_2TO1 (See above) CPU_55S CPU_2TO1 CPU_BSEL1 CPU_55S CPU_2TO1 (See above) CPU_55S CPU_2TO1 CPU_BSEL2 CPU_55S CPU_2TO1 (See above) CPU_55S CPU_2TO1 CPU_DPRSTP_L CPU_55S CPU_2TO1 CPU_GTLREF CPU_55S CPU_GTLREF CPU_COMP CPU_55S CPU_COMP NOTE: Design Guide does not indicate FSB spacing to other signals, assumed 3:1 NOTE: Design Guide allows closer spacing if signal lengths can be shortened SOURCE: Santa Rosa Platform DG, Rev 0.9 (#20517), Sections 4.2 & 4.3 C CPU Signal Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP CPU_27P4S * Y =27P4_OHM_SE =27P4_OHM_SE =27P4_OHM_SE MIL MIL CPU_55S * Y =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD SPACING_RULE_SET LAYER FSB_D_L FSB_DINV_L FSB_DSTB_L_P FSB_DSTB_L_N FSB_D_L FSB_DINV_L FSB_DSTB_L_P FSB_DSTB_L_N FSB_D_L FSB_DINV_L FSB_DSTB_L_P FSB_DSTB_L_N FSB_A_L FSB_REQ_L FSB_ADSTB_L FSB_A_L FSB_ADSTB_L 9B4 9C4 13C5 9B4 13B3 9B4 13B3 9B4 13B3 9C2 13B5 13C5 9C2 13B3 9C2 13A3 9C2 13B3 9B2 9C2 13B5 9B2 13B3 9B2 13A3 9B2 13B3 9D8 13C3 13D3 9C8 9D8 13A3 C 9D8 13C3 9C8 13C3 9C8 13C3 TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM NOTE: mil gap is for VCCSense pair, which Intel says to route with mil spacing without specifying a target differential impedance TABLE_SPACING_RULE_HEAD LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM CPU_2TO1 * =2:1_SPACING ? CPU_COMP * 25 MIL ? CPU_2TO1 TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM CPU_GTLREF * 25 MIL ? DG recommends at least 25 mils, >50 mils preferred TABLE_SPACING_RULE_ITEM CPU_ITP * =2:1_SPACING ? TABLE_SPACING_RULE_ITEM CPU_VCCSENSE * 25 MIL ? Most CPU signals with impedance requirements are 55-ohm single-ended Some signals require 27.4-ohm single-ended impedance SOURCE: Santa Rosa Platform DG, Rev 0.9 (#20517), Sections 4.4 & 5.8.2.4 B CPU_2TO1 CPU_COMP CPU_27P4S CPU_COMP CPU_COMP CPU_55S CPU_COMP CPU_COMP CPU_27P4S CPU_COMP XDP_TDI CPU_55S CPU_ITP XDP_TDO CPU_55S CPU_ITP XDP_TMS CPU_55S CPU_ITP XDP_TCK CPU_55S CPU_ITP XDP_TRST_L CPU_55S CPU_ITP XDP_BPM_L CPU_55S CPU_ITP XDP_BPM_L5 CPU_55S CPU_ITP CLK_FSB_100D CLK_FSB CLK_FSB_100D CLK_FSB CPU_55S CPU_ITP CPU_55S CPU_2TO1 CPU_55S CPU_2TO1 CPU_VCCSENSE CPU_27P4S CPU_VCCSENSE CPU_VCCSENSE CPU_27P4S CPU_VCCSENSE CPU_27P4S CPU_VCCSENSE CPU_27P4S CPU_VCCSENSE (FSB_CPURST_L) CPU_IERR_L CPU_FERR_L CPU_PROCHOT_L CPU_PWRGD CPU_INTR CPU_NMI CPU_A20M_L CPU_DPSLP_L CPU_IGNNE_L CPU_INIT_L CPU_SMI_L CPU_STPCLK_L PM_THRMTRIP_L FSB_CPUSLP_L PM_DPRSLPVR IMVP_DPRSLPVR CPU_BSEL NB_BSEL CPU_BSEL NB_BSEL CPU_BSEL NB_BSEL CPU_DPRSTP_L CPU_GTLREF CPU_COMP CPU_COMP CPU_COMP CPU_COMP XDP_TDI XDP_TDO XDP_TMS XDP_TCK XDP_TRST_L XDP_BPM_L XDP_BPM_L XDP_CLK_P XDP_CLK_N ITP_CPURST_L CPU_VID IMVP6_VID CPU_VCCSENSE_P CPU_VCCSENSE_N IMVP6_VSEN_P IMVP6_VSEN_N 9D6 9C8 22C2 9C5 45B5 45C3 59C8 9B2 12B1 22C4 9B8 22C4 9B8 22C4 9C8 22C4 9B2 22C4 9C8 22C4 9D6 22C4 46B2 9B8 22C4 9B8 22C4 9C6 15A6 22C2 45B3 9A2 13A5 15A6 24C3 59D8 59C7 9B4 29C6 15C6 29C8 9A4 29B6 15C6 29B8 9A4 29A6 15B6 29B8 B 9B2 15B6 22C4 59C7 9B4 9B3 9B3 9B3 9B3 9B7 9C6 12B3 9A7 9C6 12B5 9B7 9C6 12B2 9A7 9C6 12B2 12B3 9A7 9C6 12B3 9C6 12B2 12B3 9C5 12B2 75C3 75C3 10B7 59C7 10A6 59A4 59A5 10A6 59A4 59A5 CPU/FSB Constraints SYNC_MASTER=WFERRY A SYNC_DATE=06/08/2006 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE D APPLE INC DRAWING NUMBER SCALE SHT NONE REV 051-7455 OF 70 76 01 A PCI-Express / DMI Bus Constraints NET_TYPE TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP PCIE_100D * Y =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING TABLE_PHYSICAL_RULE_ITEM PEG_R2D DMI_100D * Y =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF PCIE PCIE_100D PCIE PCIE_100D PCIE PCIE_100D PCIE DMI_100D DMI DMI_100D DMI DMI_100D DMI DMI_100D DMI LVDS_A_CLK LVDS_100D LVDS LVDS_A_CLK LVDS_100D LVDS LVDS_A_DATA LVDS_100D LVDS LVDS_A_DATA LVDS_100D LVDS LVDS_A_DATA3 LVDS_100D LVDS LVDS_A_DATA3 LVDS_100D LVDS LVDS_A_CLK_P LVDS_A_CLK_N LVDS_A_DATA_P LVDS_A_DATA_N LVDS_A_DATA_P LVDS_A_DATA_N LVDS_IBG LVDS LVDS_IBG CRT_TVO_IREF CRT CRT_TVO_IREF CRT_RED CRT_GREEN CRT_BLUE CRT_HSYNC_R CRT_VSYNC_R TV_A_DAC TV_B_DAC TV_C_DAC =100_OHM_DIFF TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING PEG_D2R_N PEG_D2R_P PEG_R2D_C_P PEG_R2D_C_N PCIE_100D TABLE_PHYSICAL_RULE_ITEM 14D3 68B6 14C3 68B6 14B3 68B6 68C6 14B3 14C3 68B6 68C6 WEIGHT TABLE_SPACING_RULE_ITEM PCIE * 20 MIL ? DMI * 20 MIL ? TABLE_SPACING_RULE_ITEM D SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Sections 7.2, 9.2 & 10.5 DMI_N2S Video Signal Constraints DMI_S2N TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP LVDS_100D * Y =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF CRT_50S * Y =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM CRT_55S * Y =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD DMI_N2S_P DMI_N2S_N DMI_S2N_P DMI_S2N_N D 15B3 23D2 15B3 23D2 15B3 23D2 15B3 15C3 23D2 14C5 67B3 14C5 67B3 14C5 67B2 14C5 67B2 TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM LVDS * 20 MIL ? CRT * 25 MIL ? CRT_2CRT * 20 MIL ? CRT_SYNC * 25 MIL ? CRT_SYNC2SYNC * 20 MIL ? TVDAC * 25 MIL ? TABLE_SPACING_RULE_ITEM DG Says 40 mil spacing minimum TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM DG Says 30 mil spacing minimum 14D5 67A8 TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM DG Says 40 mil spacing minimum CRT_RED CRT_50S CRT CRT_GREEN CRT_50S CRT CRT_BLUE CRT_50S CRT CRT_SYNC CRT_55S CRT_SYNC CRT_SYNC CRT_55S CRT_SYNC TV_A_DAC CRT_50S TVDAC TV_B_DAC CRT_50S TVDAC TV_C_DAC CRT_50S TVDAC TABLE_SPACING_RULE_ITEM TVDAC_2TVDAC * 20 MIL ? TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET TABLE_SPACING_ASSIGNMENT_ITEM C CRT CRT * CRT_2CRT TABLE_SPACING_ASSIGNMENT_ITEM CRT_SYNC CRT_SYNC * CRT_SYNC2SYNC TVDAC TVDAC * TVDAC_2TVDAC 69D7 69D8 69A8 69D5 69A8 69D5 69B8 69D5 69C3 69D5 69C3 69D5 69B8 69D7 69A8 69D7 C 69A8 69D7 TABLE_SPACING_ASSIGNMENT_ITEM LVDS signals are 100-ohm +/- 20% differential impedence CRT & TVDAC signal single-ended impedence varies by location: - 37.5-ohm +/- 15% from GMCH to first termination resistor - 50-ohm +/- 15% from first to second termination resistor - 55-ohm +/- 15% from second termination resistor to connector CRT_HSYNC/CRT_VSYNC signals are 55-ohm +/- 15% single-ended impedence SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Sections 8.1 - 8.3 B B NB Constraints SYNC_MASTER=WFERRY A SYNC_DATE=06/12/2006 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE D APPLE INC DRAWING NUMBER SCALE SHT NONE REV 051-7455 OF 71 76 01 A DDR2 Memory Bus Constraints Memory Net Properties NET_TYPE TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP MEM_45S * Y =45_OHM_SE =45_OHM_SE =45_OHM_SE =STANDARD =STANDARD ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING TABLE_PHYSICAL_RULE_ITEM MEM_A_CLK MEM_70D MEM_CLK MEM_70D MEM_CLK MEM_A_CNTL MEM_45S MEM_CTRL MEM_A_CNTL MEM_45S MEM_CTRL MEM_A_CNTL MEM_45S MEM_CTRL MEM_A_CMD MEM_55S MEM_CMD TABLE_PHYSICAL_RULE_ITEM MEM_55S * Y =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD MEM_CLK_P MEM_CLK_N 15D3 30A4 30D4 15D3 30A4 30D4 TABLE_PHYSICAL_RULE_ITEM MEM_70D * Y =70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF MEM_85D * Y =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF SPACING_RULE_SET LAYER TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_HEAD D LINE-TO-LINE SPACING WEIGHT =4:1_SPACING ? TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET MEM_CLK MEM_CLK * MEM_CLK2MEM TABLE_SPACING_RULE_ITEM MEM_CLK2MEM * TABLE_SPACING_RULE_ITEM MEM_CTRL2CTRL * =2:1_SPACING TABLE_SPACING_ASSIGNMENT_ITEM ? MEM_CLK MEM_CTRL * MEM_CLK2MEM TABLE_SPACING_RULE_ITEM MEM_CTRL2MEM * =3:1_SPACING * =1.5:1_SPACING MEM_CLK MEM_CMD * MEM_CLK2MEM * =3:1_SPACING MEM_CMD MEM_55S MEM_CMD MEM_A_CMD MEM_55S MEM_CMD MEM_A_CMD MEM_55S MEM_CMD MEM_CLK MEM_DATA * MEM_CLK2MEM MEM_A_DQ_BYTE0 MEM_55S MEM_DATA MEM_A_DQ_BYTE1 MEM_55S MEM_DATA MEM_A_DQ_BYTE2 MEM_55S MEM_DATA MEM_A_DQ_BYTE3 MEM_55S MEM_DATA MEM_A_DQ_BYTE4 MEM_55S MEM_DATA MEM_A_DQ_BYTE5 MEM_55S MEM_DATA MEM_A_DQ_BYTE6 MEM_55S MEM_DATA MEM_A_DQ_BYTE7 MEM_55S MEM_DATA MEM_A_DM0 MEM_55S MEM_DATA MEM_A_DM1 MEM_55S MEM_DATA MEM_A_DM2 MEM_55S MEM_DATA MEM_A_DM3 MEM_55S MEM_DATA MEM_A_DM4 MEM_55S MEM_DATA MEM_A_DM5 MEM_55S MEM_DATA MEM_A_DM6 MEM_55S MEM_DATA MEM_A_DM7 MEM_55S MEM_DATA MEM_A_DQS0 MEM_85D MEM_DQS MEM_85D MEM_DQS MEM_85D MEM_DQS MEM_85D MEM_DQS MEM_85D MEM_DQS MEM_85D MEM_DQS MEM_85D MEM_DQS MEM_85D MEM_DQS MEM_85D MEM_DQS MEM_85D MEM_DQS MEM_85D MEM_DQS MEM_85D MEM_DQS MEM_85D MEM_DQS MEM_85D MEM_DQS MEM_85D MEM_DQS MEM_85D MEM_DQS MEM_70D MEM_CLK MEM_70D MEM_CLK MEM_B_CNTL MEM_45S MEM_CTRL MEM_B_CNTL MEM_45S MEM_CTRL MEM_B_CNTL MEM_45S MEM_CTRL MEM_B_CMD MEM_55S MEM_CMD MEM_B_CMD MEM_55S MEM_CMD MEM_B_CMD MEM_55S MEM_CMD MEM_B_CMD MEM_55S MEM_CMD MEM_B_CMD MEM_55S MEM_CMD MEM_B_DQ_BYTE0 MEM_55S MEM_DATA MEM_B_DQ_BYTE1 MEM_55S MEM_DATA MEM_B_DQ_BYTE2 MEM_55S MEM_DATA MEM_B_DQ_BYTE3 MEM_55S MEM_DATA MEM_B_DQ_BYTE4 MEM_55S MEM_DATA MEM_B_DQ_BYTE5 MEM_55S MEM_DATA MEM_B_DQ_BYTE6 MEM_55S MEM_DATA MEM_B_DQ_BYTE7 MEM_55S MEM_DATA MEM_B_DM0 MEM_55S MEM_DATA MEM_B_DM1 MEM_55S MEM_DATA MEM_B_DM2 MEM_55S MEM_DATA MEM_B_DM3 MEM_55S MEM_DATA MEM_B_DM4 MEM_55S MEM_DATA MEM_B_DM5 MEM_55S MEM_DATA MEM_B_DM6 MEM_55S MEM_DATA MEM_B_DM7 MEM_55S MEM_DATA MEM_B_DQS0 MEM_85D MEM_DQS MEM_85D MEM_DQS MEM_85D MEM_DQS MEM_85D MEM_DQS MEM_85D MEM_DQS MEM_85D MEM_DQS MEM_85D MEM_DQS MEM_85D MEM_DQS MEM_85D MEM_DQS MEM_85D MEM_DQS MEM_85D MEM_DQS MEM_85D MEM_DQS MEM_85D MEM_DQS MEM_85D MEM_DQS MEM_85D MEM_DQS MEM_85D MEM_DQS TABLE_SPACING_ASSIGNMENT_ITEM ? TABLE_SPACING_RULE_ITEM MEM_CMD2MEM MEM_55S MEM_A_CMD TABLE_SPACING_ASSIGNMENT_ITEM ? MEM_CLK MEM_DQS * MEM_CLK2MEM TABLE_SPACING_RULE_ITEM MEM_DATA2DATA * =1.5:1_SPACING ? TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 TABLE_SPACING_RULE_ITEM MEM_DATA2MEM * =3:1_SPACING ? NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET TABLE_SPACING_ASSIGNMENT_ITEM MEM_CMD TABLE_SPACING_RULE_ITEM MEM_DQS2MEM * =3:1_SPACING MEM_A_A MEM_A_BS MEM_A_RAS_L MEM_A_CAS_L MEM_A_WE_L 15D3 30C4 30C6 32D6 15D3 30B4 30B6 32D6 15C3 30B4 30B6 32D6 15C6 16B5 16C5 30B4 30B6 30C4 30C6 32C6 16D5 30B4 30B6 30C6 32C6 D 16B5 30B4 32B6 16D5 30B6 32B6 16B5 30B6 32B6 TABLE_SPACING_ASSIGNMENT_ITEM ? TABLE_SPACING_RULE_ITEM MEM_CMD2CMD MEM_A_CMD TABLE_SPACING_ASSIGNMENT_ITEM MEM_CKE MEM_CS_L MEM_ODT ? MEM_CLK * MEM_CMD2MEM MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ 16D8 30D4 30D6 16C8 30D4 30D6 16C8 30C4 30C6 16C8 30C4 30C6 30D4 30D6 16B8 16C8 30B4 30B6 16B8 30A4 30A6 30B4 30B6 16B8 30A4 30A6 16A8 16B8 30A4 30A6 TABLE_SPACING_ASSIGNMENT_ITEM MEM_CMD TABLE_SPACING_RULE_ITEM MEM_2OTHER * 25 MIL ? MEM_CTRL * MEM_CMD2MEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CMD MEM_CMD * MEM_CMD2CMD TABLE_SPACING_ASSIGNMENT_ITEM MEM_CMD MEM_DATA * MEM_CMD2MEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CMD MEM_DQS * MEM_CMD2MEM TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET MEM_CTRL MEM_CLK * MEM_CTRL2MEM MEM_A_DM MEM_A_DM MEM_A_DM MEM_A_DM MEM_A_DM MEM_A_DM MEM_A_DM MEM_A_DM 16D5 30D4 16D5 30D4 16C5 30C6 16C5 30C4 16C5 30B4 16C5 30B6 16C5 30A6 16C5 30A4 TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CTRL MEM_CTRL * MEM_CTRL2CTRL MEM_A_DQS1 TABLE_SPACING_ASSIGNMENT_ITEM MEM_CTRL MEM_CMD * MEM_CTRL2MEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CTRL MEM_DATA * MEM_CTRL2MEM MEM_A_DQS2 TABLE_SPACING_ASSIGNMENT_ITEM C MEM_CTRL MEM_DQS * MEM_CTRL2MEM MEM_A_DQS3 TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET MEM_DATA MEM_CLK * MEM_DATA2MEM MEM_DATA MEM_CTRL * MEM_DATA2MEM MEM_A_DQS4 TABLE_SPACING_ASSIGNMENT_ITEM MEM_A_DQS5 TABLE_SPACING_ASSIGNMENT_ITEM MEM_A_DQS6 TABLE_SPACING_ASSIGNMENT_ITEM MEM_DATA MEM_CMD * MEM_DATA2MEM MEM_DATA MEM_DATA * MEM_DATA2DATA TABLE_SPACING_ASSIGNMENT_ITEM MEM_A_DQS7 TABLE_SPACING_ASSIGNMENT_ITEM MEM_DATA MEM_DQS * MEM_DATA2MEM MEM_B_CLK TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE MEM_CLK * * MEM_2OTHER * * MEM_2OTHER TABLE_SPACING_ASSIGNMENT_ITEM MEM_DQS MEM_CLK * MEM_DQS2MEM MEM_DQS MEM_CTRL * MEM_DQS2MEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CMD * * MEM_2OTHER MEM_DATA * * MEM_2OTHER MEM_DQS * * MEM_2OTHER MEM_CLK_P MEM_CLK_N 16C5 30D6 16C5 30D6 16C5 30D6 16C5 30D6 16C5 30C4 16C5 30C4 C 16C5 30C6 16C5 30C6 16C5 30B6 16C5 30B6 16C5 30B4 16C5 30B4 16C5 30A4 16C5 30A4 16C5 30A6 16C5 30A6 15D3 31A4 31D4 15D3 31A4 31D4 SPACING_RULE_SET TABLE_SPACING_ASSIGNMENT_ITEM MEM_CTRL MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_CKE MEM_CS_L MEM_ODT 15D3 31C4 31C6 32D5 32D6 15C3 15D3 31B4 31B6 32D6 15C3 31B4 31B6 32D6 TABLE_SPACING_ASSIGNMENT_ITEM MEM_DQS MEM_CMD * MEM_DQS2MEM MEM_DQS MEM_DATA * MEM_DQS2MEM MEM_DQS MEM_DQS * MEM_DQS2MEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM Need to support MEM_*-style wildcards! SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Section 6.2 B MEM_B_DQS1 MEM_B_DQS2 MEM_B_DQS3 MEM_B_DQS4 MEM_B_DQS5 MEM_B_DQS6 A MEM_B_DQS7 MEM_B_A MEM_B_BS MEM_B_RAS_L MEM_B_CAS_L MEM_B_WE_L MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DM MEM_B_DM MEM_B_DM MEM_B_DM MEM_B_DM MEM_B_DM MEM_B_DM MEM_B_DM MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N 15C6 16B1 16C1 31B4 31B6 31C4 31C6 32A5 32B5 16D1 31B4 31B6 31C6 32A6 16B1 31B4 32A6 16D1 31B6 32A6 16B1 31B6 32A6 16D4 31D4 31D6 16C4 31D4 31D6 16C4 31C4 31C6 16C4 31C4 31C6 B 16B4 16C4 31B4 31B6 16B4 31A4 31A6 31B4 31B6 16B4 31A4 31A6 16A4 16B4 31A4 31A6 16D1 31D4 16D1 31D4 16C1 31C4 16C1 31C6 16C1 31B4 16C1 31A6 16C1 31A4 16C1 31A6 16C1 31D6 16C1 31D6 16C1 31D6 16C1 31D6 16C1 31C6 16C1 31C6 16C1 31C4 16C1 31C4 16C1 31B6 16C1 31B6 16C1 31A4 Memory Constraints 16C1 31B4 16C1 31A6 SYNC_MASTER=WFERRY SYNC_DATE=06/08/2006 16C1 31A6 NOTICE OF PROPRIETARY PROPERTY 16C1 31A4 16C1 31A4 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE D APPLE INC DRAWING NUMBER SCALE SHT NONE REV 051-7455 OF 72 76 01 A Disk Interface Constraints NET_TYPE TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP IDE_55S * Y =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING TABLE_PHYSICAL_RULE_ITEM IDE_PDD IDE_55S IDE IDE_PDA IDE_55S IDE IDE_PDCS IDE_55S IDE IDE_PDCS IDE_55S IDE IDE_CNTL IDE_55S IDE IDE_PDIOR_L IDE_55S IDE IDE_CNTL IDE_55S IDE IDE_CNTL IDE_55S IDE IDE_PDIORDY IDE_55S IDE IDE_IRQ14 IDE_55S IDE IDE_RST_L IDE_55S IDE SATA_A_R2D SATA_100D SATA SATA_100D SATA SATA_100D SATA SATA_100D SATA SATA_100D SATA SATA_100D SATA SATA_100D SATA SATA_100D SATA TABLE_PHYSICAL_RULE_ITEM SATA_55S * Y =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD TABLE_PHYSICAL_RULE_ITEM SATA_100D * Y =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM D IDE * =1.8:1_SPACING ? SATA * 20 MIL ? TABLE_SPACING_RULE_ITEM SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Sections 10.7 & 10.9 HD Audio Interface Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM HDA_55S * SPACING_RULE_SET LAYER Y =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD SATA_A_D2R TABLE_SPACING_RULE_HEAD LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM HDA * =1.8:1_SPACING ? IDE_PDD IDE_PDA IDE_PDCS1_L IDE_PDCS3_L IDE_PDIOW_L IDE_PDIOR_L IDE_PDDACK_L IDE_PDDREQ IDE_PDIORDY IDE_IRQ14 ODD_RST_5VTOL_L SATA_A_R2D_C_P SATA_A_R2D_C_N SATA_A_R2D_P SATA_A_R2D_N SATA_A_D2R_P SATA_A_D2R_N SATA_A_D2R_C_P SATA_A_D2R_C_N 22B4 22C4 39C3 39C5 22B4 39B3 39B5 22B4 39B5 22B4 39B3 22B4 39B5 22B4 39C3 22B4 39B3 22A4 39C3 D 22A4 39B5 22B4 39B5 23B6 39A8 22B6 40D4 22B6 40D4 40D7 40D7 22B6 40C4 22B6 40D4 40C7 40D7 SOURCE: Napa Platform DG, Rev 0.9 (#17978), Section 10.9.1 USB 2.0 Interface Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? USB_60S * Y =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD USB_90D * Y =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF SPACING_RULE_SET LAYER MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_HEAD LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM USB * 20 MIL ? USB_2CLK * 25 MIL ? TABLE_SPACING_RULE_ITEM C DG says minimum spacing 50 mils to clocks C SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Section 10.13.2 HDA_BIT_CLK Internal Interface Constraints HDA_SYNC TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP HDA_55S HDA HDA_55S HDA HDA_55S HDA HDA_55S HDA HDA_55S HDA HDA_55S HDA HDA_55S HDA DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM SMB_55S * Y =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD HDA_RST_L TABLE_PHYSICAL_RULE_ITEM SPI_55S * Y =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD HDA_SDIN0 HDA_BIT_CLK HDA_BIT_CLK_R HDA_SYNC HDA_SYNC_R HDA_RST_L HDA_RST_L_R HDA_SDIN0 8A6 22C8 22C6 8A6 22C8 22C6 8A6 22C8 22C6 8A6 22C8 TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT =3:1_SPACING ? HDA_SDOUT TABLE_SPACING_RULE_ITEM SMB * USB_EXTA TABLE_SPACING_RULE_ITEM SPI * =1.8:1_SPACING ? SOURCE: Santa Platform DG, Rev 1.0 (#21112), Section 10.17 USB_MINI USB_3G USB_CAMERA USB_BT USB_TPAD B USB_IR USB_EXTB USB_EXCARD USB_EXTC HDA_55S HDA HDA_55S HDA USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_RBIAS USB_60S SMB_SB_SCL SMB_55S SMB SMB_SB_SDA SMB_55S SMB SMB_SB_ME_SCL SMB_55S SMB SMB_SB_ME_SDA SMB_55S SMB SPI_SCLK SPI_55S SPI SPI_55S SPI SPI_55S SPI SPI_55S SPI SPI_55S SPI SPI_55S SPI SPI_55S SPI SPI_55S SPI SPI_55S SPI SPI_SI SPI_SO SPI_CE_L0 SPI_CE_L1 HDA_SDOUT HDA_SDOUT_R USB_EXTA_P USB_EXTA_N USB_EXTA_MUXED_P USB_EXTA_MUXED_N USB_MINI_P USB_MINI_N USB_3G_P USB_3G_N USB_CAMERA_P USB_CAMERA_N USB_BT_P USB_BT_N USB_TPAD_P USB_TPAD_N USB_IR_P USB_IR_N USB_EXTB_P USB_EXTB_N USB_EXCARD_P USB_EXCARD_N USB_EXTC_P USB_EXTC_N USB_RBIAS SMB_CLK SMB_DATA SMB_ME_CLK SMB_ME_DATA SPI_SCLK_R SPI_A_SCLK_R SPI_SI_R SPI_A_SI_R SPI_SO SPI_A_SO_R SPI_CE_R_L SPI_CE_L SPI_CE_R_L 8A6 22B8 22B6 8C1 23C2 8C1 23C2 8C1 23C2 8C1 23C2 8C1 23C2 8C1 23C2 8C1 8C2 23C2 8B1 8B2 23C2 8C1 23C2 B 8C1 23C2 8C1 8C2 23C2 8C1 8C2 23C2 8B1 23C2 8B1 23C2 8B1 23C2 8B1 23C2 8B1 23C2 8B1 23C2 23B3 24D5 47D8 24D5 47D8 24D5 47A8 24D5 47A8 23C5 52C7 52C5 23C5 52C3 52C4 23C5 52C3 52C4 23C5 52C7 52C6 SB Constraints (1 of 2) SYNC_MASTER=WFERRY A SYNC_DATE=06/12/2006 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE D APPLE INC DRAWING NUMBER SCALE SHT NONE REV 051-7455 OF 73 76 01 A PCI Bus Constraints NET_TYPE TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP PCI_55S * Y =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING TABLE_PHYSICAL_RULE_ITEM PCI_AD PCI_55S PCI PCI_AD19 PCI_55S PCI PCI_AD20 PCI_55S PCI PCI_AD PCI_55S PCI PCI_AD PCI_55S PCI PCI_C_BE_L PCI_55S PCI PCI_CNTL PCI_55S PCI PCI_CNTL PCI_55S PCI PCI_CNTL PCI_55S PCI PCI_LOCK_L PCI_55S PCI PCI_CNTL PCI_55S PCI PCI_CNTL PCI_55S PCI PCI_CNTL PCI_55S PCI PCI_CNTL PCI_55S PCI PCI_FW_REQ_L PCI_55S PCI PCI_FW_GNT_L PCI_55S PCI PCI_REQ1_L PCI_55S PCI PCI_GNT1_L PCI_55S PCI PCI_REQ2_L PCI_55S PCI PCI_GNT2_L PCI_55S PCI INT_PIRQA_L PCI_55S PCI INT_PIRQB_L PCI_55S PCI INT_PIRQC_L PCI_55S PCI INT_PIRQD_L PCI_55S PCI INT_PIRQE_L PCI_55S PCI INT_PIRQF_L PCI_55S PCI TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM PCI * =2:1_SPACING ? SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Sections 10.18.1 & 10.19 D Platform LAN (Nineveh) Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM LAN_55S * Y =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD ENET_100D * Y =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM GLAN_100D * Y =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM ENET_CLK * =2.5:1_SPACING ? ENET_GLAN * 20 MILS ? TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM ENET_LAN * =1.5:1_SPACING ? ENET_MDI * 25 MILS ? TABLE_SPACING_RULE_ITEM DG says 30 mils separation SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Sections 10.27.1.5-7, 10.29 & 10.30 Controller Link (AMT) Constraints PCI_AD PCI_AD PCI_AD PCI_AD PCI_PAR PCI_C_BE_L PCI_IRDY_L PCI_DEVSEL_L PCI_PERR_L PCI_LOCK_L PCI_SERR_L PCI_STOP_L PCI_TRDY_L PCI_FRAME_L PCI_FW_REQ_L PCI_FW_GNT_L PCI_REQ1_L PCI_GNT1_L PCI_REQ2_L PCI_GNT2_L INT_PIRQA_L INT_PIRQB_L INT_PIRQC_L INT_PIRQD_L INT_PIRQE_L INT_PIRQF_L 23A8 23B8 37B5 37C5 23A8 37B6 23A8 37B5 23A8 37B5 23A6 37B5 23B6 37B5 23A4 23A6 37A5 23A4 23A6 37A5 D 23A4 23A6 37A5 23A4 23A6 23A4 23A6 37A5 23A4 23A6 37A5 23A4 23A6 37A5 23A4 23A6 37A5 23A4 23B6 37A5 23B5 37A5 23A4 23B6 23A4 23B6 23A4 23A8 23A4 23A8 23A4 23A8 23A4 23A8 37A5 23A4 23A6 23A4 23A6 TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP CLINK_55S * Y =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD CLINK_12MIL * Y 12 MILS MILS 300 MILS =STANDARD =STANDARD SPACING_RULE_SET LAYER TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_HEAD C LINE-TO-LINE SPACING WEIGHT C TABLE_SPACING_RULE_ITEM CLINK * =1.8:1_SPACING ? CLINK_VREF * 12 MILS ? TABLE_SPACING_RULE_ITEM SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Sections 10.27.1.5-7, 10.29 & 10.30 PCIE_E_R2D PCIE_E_D2R PCIE_100D PCIE PCIE_100D PCIE PCIE_100D PCIE PCIE_100D PCIE GLAN_COMP GLAN_COMP B PCIE_E_R2D_C_P PCIE_E_R2D_C_N PCIE_E_D2R_P PCIE_E_D2R_N ENET_LAN LAN_55S ENET_LAN LAN_55S ENET_LAN ENET_LAN LAN_55S ENET_LAN ENET_GLAN_CLK LAN_55S ENET_CLK LAN_55S ENET_CLK ENET_100D ENET_MDI ENET_MDI0 ENET_LAN ENET_100D ENET_MDI ENET_MDI1 ENET_100D ENET_MDI ENET_100D ENET_MDI ENET_MDI2 ENET_100D ENET_MDI ENET_100D ENET_MDI ENET_100D ENET_MDI ENET_100D ENET_MDI CLINK_NB CLINK_55S CLINK CLINK_NB CLINK_55S CLINK CLINK_NB_RESET_L CLINK_55S CLINK CLINK_WLAN CLINK_55S CLINK CLINK_WLAN CLINK_55S CLINK CLINK_WLAN_RESET_L CLINK_55S CLINK NB_CLINK_VREF CLINK_12MIL CLINK_VREF SB_CLINK_VREF0 CLINK_12MIL CLINK_VREF SB_CLINK_VREF1 CLINK_12MIL CLINK_VREF ENET_MDI3 LAN_RSTSYNC LAN_R2D LAN_D2R ENET_GLAN_CLK_R ENET_GLAN_CLK ENET_MDI_P ENET_MDI_N ENET_MDI_P ENET_MDI_N ENET_MDI_P ENET_MDI_N ENET_MDI_P ENET_MDI_N CLINK_NB_CLK CLINK_NB_DATA CLINK_NB_RESET_L CLINK_WLAN_CLK CLINK_WLAN_DATA CLINK_WLAN_RESET_L NB_CLINK_VREF SB_CLINK_VREF0 SB_CLINK_VREF1 33B5 33B6 33B5 33B6 33B5 33B5 33C5 22C6 B 34B8 36B7 34B8 36B7 34B8 36C7 34B8 36C7 34B8 36B7 34B8 36C7 34B8 36C7 34B8 36C7 15A3 24C3 15A3 24C3 15A3 24C3 24C3 24C3 24D5 15A4 24C3 24C3 SB Constraints (2 of 2) SYNC_MASTER=WFERRY A SYNC_DATE=06/12/2006 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE D APPLE INC DRAWING NUMBER SCALE SHT NONE REV 051-7455 OF 74 76 01 A Clock Signal Constraints Clock Net Properties NET_TYPE TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP CLK_FSB_100D * Y =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING TABLE_PHYSICAL_RULE_ITEM CK505_CPU CLK_FSB_100D CLK_FSB CK505_CPU CLK_FSB_100D CLK_FSB CK505_NB CLK_FSB_100D CLK_FSB CK505_NB CLK_FSB_100D CLK_FSB CK505_ITP CLK_FSB_100D CLK_FSB CK505_ITP CLK_FSB_100D CLK_FSB CK505_PCIF0 CLK_MED_55S CLK_MED CK505_PCIF1 CLK_MED_55S CLK_MED CK505_PCI1 CLK_MED_55S CLK_MED CK505_PCI2 CLK_MED_55S CLK_MED CK505_PCI3 CLK_MED_55S CLK_MED CK505_PCI4 CLK_MED_55S CLK_MED CK505_PCI5 CLK_MED_55S CLK_MED (CPU_BSEL0) (CPU_BSEL2) CLK_MED_55S CLK_MED CLK_MED_55S CLK_MED CK505_DOT96 CLK_PCIE_100D CLK_PCIE CLK_PCIE_100D CLK_PCIE CLK_PCIE_100D CLK_PCIE CLK_PCIE_100D CLK_PCIE CLK_PCIE_100D CLK_PCIE CLK_PCIE_100D CLK_PCIE CLK_PCIE_100D CLK_PCIE CLK_PCIE_100D CLK_PCIE CLK_PCIE_100D CLK_PCIE CLK_PCIE_100D CLK_PCIE CLK_PCIE_100D CLK_PCIE CLK_PCIE_100D CLK_PCIE CLK_PCIE_100D CLK_PCIE CLK_PCIE_100D CLK_PCIE CLK_PCIE_100D CLK_PCIE CLK_PCIE_100D CLK_PCIE CLK_PCIE_100D CLK_PCIE CLK_PCIE_100D CLK_PCIE CLK_PCIE_100D CLK_PCIE CLK_PCIE_100D CLK_PCIE (CK505_CPU) (CK505_CPU) (CK505_NB) (CK505_NB) (CK505_ITP) (CK505_ITP) CLK_FSB_100D CLK_FSB CLK_FSB_100D CLK_FSB CLK_FSB_100D CLK_FSB CLK_FSB_100D CLK_FSB CLK_FSB_100D CLK_FSB CLK_FSB_100D CLK_FSB (CK505_PCIF0) (CK505_PCIF1) (CK505_PCI1) (CK505_PCI2) (CK505_PCI3) CLK_MED_55S CLK_MED CLK_MED_55S CLK_MED CLK_MED_55S CLK_MED CLK_MED_55S CLK_MED CLK_MED_55S CLK_MED (CPU_BSEL0) (CPU_BSEL2) CLK_MED_55S CLK_MED CLK_MED_55S CLK_MED (CPU_BSEL0) (CPU_BSEL2) CLK_MED_55S CLK_MED CLK_MED_55S CLK_MED (CK505_DOT96) (CK505_DOT96) (CK505_LVDS) (CK505_LVDS) (CK505_SRC1) (CK505_SRC1) (CK505_SRC2) (CK505_SRC2) (CK505_SRC3) (CK505_SRC3) (CK505_SRC4) (CK505_SRC4) (CK505_SRC5) (CK505_SRC5) (CK505_SRC6) (CK505_SRC6) CLK_PCIE_100D CLK_PCIE CLK_PCIE_100D CLK_PCIE CLK_PCIE_100D CLK_PCIE CLK_PCIE_100D CLK_PCIE CLK_PCIE_100D CLK_PCIE CLK_PCIE_100D CLK_PCIE CLK_PCIE_100D CLK_PCIE CLK_PCIE_100D CLK_PCIE CLK_PCIE_100D CLK_PCIE CLK_PCIE_100D CLK_PCIE CLK_PCIE_100D CLK_PCIE CLK_PCIE_100D CLK_PCIE CLK_PCIE_100D CLK_PCIE CLK_PCIE_100D CLK_PCIE CLK_PCIE_100D CLK_PCIE CLK_PCIE_100D CLK_PCIE TABLE_PHYSICAL_RULE_ITEM CLK_PCIE_100D * Y =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF TABLE_PHYSICAL_RULE_ITEM CLK_MED_55S * Y =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD CLK_SLOW_55S * Y =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD TABLE_PHYSICAL_RULE_ITEM CK505_CPU0_P CK505_CPU0_N CK505_CPU1_P CK505_CPU1_N CK505_CPU2_ITP_SRC10_P CK505_CPU2_ITP_SRC10_N 6C7 28C4 29D6 6C7 28C4 29D6 6C7 28C4 29D6 6C7 28C4 29D6 6C7 28C4 29D6 6C7 28C4 29D6 TABLE_SPACING_RULE_HEAD SPACING_RULE_SET D LAYER LINE-TO-LINE SPACING WEIGHT 25 MIL ? TABLE_SPACING_RULE_ITEM CLK_FSB * TABLE_SPACING_RULE_ITEM CLK_PCIE * 20 MIL ? CLK_MED * 20 MIL ? TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM CLK_SLOW * 10 MIL ? SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Sections 14.1 - 14.6 CK505_LVDS CK505_SRC1 CK505_SRC2 CK505_SRC3 CK505_SRC4 CK505_SRC5 CK505_SRC6 CK505_SRC7 C CK505_SRC8 B CK505_PCIF0_CLK CK505_PCIF1_CLK CK505_PCI1_CLK CK505_PCI2_CLK CK505_PCI3_CLK CK505_PCI4_CLK CK505_PCI5_FCTSEL1 CK505_USB48_FSA CK505_CLK14P3M_TIMER CK505_DOT96_27M_P CK505_DOT96_27M_N CK505_LVDS_P CK505_LVDS_N CK505_SRC1_P CK505_SRC1_N CK505_SRC2_P CK505_SRC2_N CK505_SRC3_P CK505_SRC3_N CK505_SRC4_P CK505_SRC4_N CK505_SRC5_P CK505_SRC5_N CK505_SRC6_P CK505_SRC6_N CK505_SRC7_P CK505_SRC7_N CK505_SRC8_P CK505_SRC8_N FSB_CLK_CPU_P FSB_CLK_CPU_N FSB_CLK_NB_P FSB_CLK_NB_N XDP_CLK_P XDP_CLK_N 28B8 29B6 D 6C7 28B6 29B6 28B6 29B6 8C4 28B6 28B6 29A6 8C4 28B6 28B6 29B2 28A4 29D8 28A4 29D8 6C7 28A4 29B6 6C7 28A4 29B6 6C7 28B4 29C6 6C7 28B4 29C6 6C7 28B4 29C6 6C7 28B4 29C6 6C7 28B4 29C6 6C7 28B4 29C6 6C7 28B4 29C6 6C7 28B4 29C6 6C7 28B4 29C6 6C7 28B4 29B6 C 6B7 28A4 29B6 6B7 28A4 29B6 9B6 29D3 9B6 29D3 13B3 29D3 13B3 29D3 70A3 70A3 PCI_CLK33M_LPCPLUS 6C2 29B3 46C4 PCI_CLK33M_SB 23A6 29A5 29B3 PCI_CLK33M_FW 29A5 29B3 37A5 PCI_CLK33M_TPM PCI_CLK33M_SMC 29A3 29A5 44C8 CK505 PCI4 is project-specific CK505 PCI5 is project-specific SB_CLK48M_USBCTLR SB_CLK14P3M_TIMER CK505_FSA CK505_FSC NB_CLK96M_DOT_P NB_CLK96M_DOT_N NB_CLK100M_DPLLSS_P NB_CLK100M_DPLLSS_N PEG_CLK100M_P PEG_CLK100M_N SB_CLK100M_DMI_P SB_CLK100M_DMI_N PCIE_CLK100M_EXCARD_P PCIE_CLK100M_EXCARD_N SB_CLK100M_SATA_P SB_CLK100M_SATA_N NB_CLK100M_PCIE_P NB_CLK100M_PCIE_N PCIE_CLK100M_MINI_P PCIE_CLK100M_MINI_N 24D3 29A5 29D6 24D3 29A5 29D6 29C8 29D6 29A8 29D6 8B1 29B3 8B1 29B3 8B1 29C3 8A1 29C3 B 23C2 29C3 23D2 29C3 22B6 29C3 22B6 29C3 15C3 29C3 15C3 29C3 29C3 33C5 29B3 33C5 CK505 SRC7 is project-specific CK505 SRC8 is project-specific Clock Constraints SYNC_MASTER=WFERRY A SYNC_DATE=06/12/2006 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE D APPLE INC DRAWING NUMBER SCALE SHT NONE REV 051-7455 OF 75 76 01 A FireWire Interface Constraints FireWire Net Properties NET_TYPE TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP FW_55S * Y =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD ELECTRICAL_CONSTRAINT_SET SPACING PHYSICAL TABLE_PHYSICAL_RULE_ITEM FW_D_CTL FW_55S FW FW_D_CTL FW_55S FW FW_LCLK CLK_MED_55S CLK_MED TABLE_PHYSICAL_RULE_ITEM FW_110D * SPACING_RULE_SET LAYER Y =110_OHM_DIFF =110_OHM_DIFF =110_OHM_DIFF =110_OHM_DIFF =110_OHM_DIFF CLK_MED_55S CLK_MED CLK_MED_55S CLK_MED CLK_MED_55S CLK_MED FW_55S FW FW_55S FW FW_LPS FW_55S FW FW_LREQ FW_55S FW FW_PINT FW_55S FW FWPHY_CLK98P304M_XI CLK_MED_55S CLK_MED CLK_MED_55S CLK_MED FW_0_TPA FW_110D FW_TP FW_0_TPA FW_110D FW_TP FW_0_TPB FW_110D FW_TP TABLE_SPACING_RULE_HEAD LINE-TO-LINE SPACING WEIGHT FW_PCLK TABLE_SPACING_RULE_ITEM FW * =2:1_SPACING ? FW_TP * =3:1_SPACING ? FW_LKON TABLE_SPACING_RULE_ITEM D FW_110D FW_TP FW_1_TPA FW_110D FW_TP FW_1_TPA FW_110D FW_TP FW_1_TPB FW_110D FW_TP FW_110D FW_TP FW_LINK FW_CTL CLKFW_LINK_LCLK CLKFW_PHY_LCLK CLKFW_LINK_PCLK CLKFW_PHY_PCLK FW_LKON FW_LKON_R FW_LPS FW_LREQ FW_PINT D CLK98P304M_FW_XI_R CLK98P304M_FW_XI FW_0_TPA_P FW_0_TPA_N FW_0_TPB_P FW_0_TPB_N FW_1_TPA_P FW_1_TPA_N FW_1_TPB_P FW_1_TPB_N Port Not Used SMC SMBus Net Properties NET_TYPE ELECTRICAL_CONSTRAINT_SET C PHYSICAL SPACING SMBUS_SMC_A_S3_SCL SMB_55S SMB SMBUS_SMC_A_S3_SDA SMB_55S SMB SMBUS_SMC_B_S0_SCL SMB_55S SMB SMBUS_SMC_B_S0_SDA SMB_55S SMB SMBUS_SMC_0_S0_SCL SMB_55S SMB SMBUS_SMC_0_S0_SDA SMB_55S SMB SMBUS_SMC_BSA_SCL SMB_55S SMB SMBUS_SMC_BSA_SDA SMB_55S SMB SMBUS_SMC_MGMT_SCL SMB_55S SMB SMBUS_SMC_MGMT_SDA SMB_55S SMB SMBUS_SMC_A_S3_SCL SMBUS_SMC_A_S3_SDA SMBUS_SMC_B_S0_SCL SMBUS_SMC_B_S0_SDA SMBUS_SMC_0_S0_SCL SMBUS_SMC_0_S0_SDA SMBUS_SMC_BSA_SCL SMBUS_SMC_BSA_SDA SMBUS_SMC_MGMT_SCL SMBUS_SMC_MGMT_SDA 47D2 47D2 6B2 47C5 C 6B2 47C5 47D5 47D5 47C2 47C2 47B2 47B2 B B FireWire & SMC Constraints SYNC_MASTER=WFERRY A SYNC_DATE=06/12/2006 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE D APPLE INC DRAWING NUMBER SCALE SHT NONE REV 051-7455 OF 76 76 01 A ... C2130,C2716,C7543 CRITICAL K36 128S0148 HF VERSION OF 128S0085 C6605 CRITICAL K36 128S0169 HF VERSION OF 128S0111 C7220,C7352,C7542 CRITICAL K36 128S0160 HF VERSION OF 128S0113 C2173,C2700 CRITICAL K36 128S0150... 128S0115 CRITICAL K36 128S0157 HF VERSION OF 128S0122 C2220 CRITICAL K36 128S0162 HF VERSION OF 128S0123 C2140 CRITICAL K36 128S0135 HF VERSION OF 128S0129 C6601,C6603 CRITICAL K36 TABLE_5_ITEM... FLASH,SOIC8 U6100 CRITICAL K36_ PGM 341S2060 IC,EEPROM,SERIAL IIC,8KBIT,SO8 U3780 CRITICAL K36_ PGM TABLE_5_ITEM TABLE_5_ITEM 341S2198 IC,SMC,HS8/2116 U4900 CRITICAL K36_ PGM 341S2093 IC,CYPRESS,CY7C63833,ENCORE_II,USB_CONTR