apple macbook a1181 k36c mlb

8 CK APPD ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5% ALL CAPACITANCE VALUES ARE IN MICROFARADS ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ REV ZONE ECN ENG APPD DESCRIPTION OF CHANGE DATE K36C MLB SCHEMATIC 02 691395 ENGINEERING RELEASED DATE 04/09/09 ? D APR/10/2009 D (.csa) (.csa) Date Page Contents TABLE_TABLEOFCONTENTS_HEAD TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM C TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM B TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 08/22/2007 Table of Contents K36BH_MLB TABLE_TABLEOFCONTENTS_ITEM 08/17/2008 System Block Diagram K36B_MLB Power Block Diagram K36B_MLB CONFIGURATION OPTIONS K36B_MLB Revision History K36B_MLB JTAG Scan Chain K36B_MLB TABLE_TABLEOFCONTENTS_ITEM 08/17/2008 TABLE_TABLEOFCONTENTS_ITEM 08/17/2008 TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM 08/17//2008 TABLE_TABLEOFCONTENTS_ITEM 08/17/2008 FUNC TEST K36B_MLB Power Aliases K36B_MLB SIGNAL ALIAS K36B_MLB TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM 10 TABLE_TABLEOFCONTENTS_ITEM 08/18/2008 CPU FSB K36B_MLB CPU Power & Ground K36B_MLB 11 TABLE_TABLEOFCONTENTS_ITEM 08/17/2008 12 TABLE_TABLEOFCONTENTS_ITEM 08/17/2008 CPU Decoupling K36B_MLB eXtended Debug Port(MiniXDP) M99_MLB 13 TABLE_TABLEOFCONTENTS_ITEM 01/08/2008 14 TABLE_TABLEOFCONTENTS_ITEM 08/17/2008 MCP CPU Interface K36B_MLB MCP Memory Interface K36B_MLB 15 TABLE_TABLEOFCONTENTS_ITEM 08/17/2008 16 TABLE_TABLEOFCONTENTS_ITEM 08/17/2008 MCP Memory Misc K36B_MLB 17 TABLE_TABLEOFCONTENTS_ITEM 08/17/2008 MCP PCIe Interfaces K36B_MLB MCP Ethernet & Graphics K36B_MLB 18 TABLE_TABLEOFCONTENTS_ITEM 08/17/2008 19 TABLE_TABLEOFCONTENTS_ITEM 08/17/2008 MCP PCI & LPC K36B_MLB MCP SATA & USB K36B_MLB 20 TABLE_TABLEOFCONTENTS_ITEM 08/17/2008 21 TABLE_TABLEOFCONTENTS_ITEM 08/17/2008 MCP HDA & MISC K36B_MLB MCP Power & Ground K36B_MLB 22 TABLE_TABLEOFCONTENTS_ITEM 08/17/2008 24 TABLE_TABLEOFCONTENTS_ITEM 08/17/2008 MCP79 A01 Silicon Support K36B_MLB 25 TABLE_TABLEOFCONTENTS_ITEM 08/17/2008 MCP Standard Decoupling K36B_MLB MCP Graphics Support K36B_MLB 26 TABLE_TABLEOFCONTENTS_ITEM 08/17/2008 28 TABLE_TABLEOFCONTENTS_ITEM 08/17/2008 SB Misc K36B_MLB FSB/DDR2 VREF MARGINING K36B_MLB 29 TABLE_TABLEOFCONTENTS_ITEM 08/17/2008 31 TABLE_TABLEOFCONTENTS_ITEM 08/17/2008 DDR2 SO-DIMM Connector A K36B_MLB DDR2 SO-DIMM Connector B K36B_MLB 32 TABLE_TABLEOFCONTENTS_ITEM 08/17/2008 33 TABLE_TABLEOFCONTENTS_ITEM 08/17/2008 Memory Active Termination K36B_MLB 34 TABLE_TABLEOFCONTENTS_ITEM 08/17/2008 Right Clutch Connector K36B_MLB 37 TABLE_TABLEOFCONTENTS_ITEM 03/20/2008 Ethernet PHY (RTL8211CL) SUMA Ethernet & AirPort Support SUMA ETHERNET CONNECTOR SUMA 38 TABLE_TABLEOFCONTENTS_ITEM 04/04/2008 39 TABLE_TABLEOFCONTENTS_ITEM 04/04/2008 41 TABLE_TABLEOFCONTENTS_ITEM 08/17/2008 FireWire LLC/PHY(FW643E) K36B_MLB 42 TABLE_TABLEOFCONTENTS_ITEM 08/17/2008 FireWire Port Power K36B_MLB FireWire Ports K36B_MLB 43 Date Page TABLE_TABLEOFCONTENTS_HEAD TABLE_TABLEOFCONTENTS_ITEM (MASTER) TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM Contents 45 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 08/17/2008 SATA Connectors K36B_MLB External USB Connectors K36B_MLB Front Flex Support K36B_MLB SMC K36B_MLB SMC Support K36B_MLB LPC+SPI Debug Connector K36B_MLB SMBUS CONNECTIONS K36B_MLB VOLTAGE SENSING K36B_MLB Current Sensing K36B_MLB Thermal Sensors K36B_MLB Fan K36B_MLB GEYSER K36B_MLB SMS K36B_MLB SPI ROM K36B_MLB 46 08/17/2008 48 07/17/2008 49 08/17/2008 50 08/17/2008 51 08/17/2008 52 08/17/2008 53 08/17/2008 54 08/17/2008 55 08/17/2008 56 08/17/2008 58 08/17/2008 59 08/17/2008 61 C 081/17/2008 62 08/29/2008 AUDIO: CODEC K36A_MLB AUDI0: SPEAKER AMP K36A_MLB AUDIO: JACK K36A_MLB AUDIO: JACK TRANSLATORS K36A_MLB DC-In & Battery Connectors RAYMOND PBUS Supply/Battery Charger K36B_MLB 5V/3.3V SUPPLY K36B_MLB 1.8V/0.9V DDR2 SUPPLY K36B_MLB IMVP6 CPU VCore Regulator K36B_MLB MCP VCORE REGULATOR K36B_MLB CPU VTT(1.05V) SUPPLY K36B_MLB MISC POWER SUPPLIES K36B_MLB POWER SEQUENCING K36B_MLB POWER FETS K36B_MLB INVERTER,LVDS K36B_MLB TMDS ALIASES K36B_MLB MINI-DVI CONNECTOR K36B_MLB CPU/FSB Constraints K36B_MLB Memory Constraints K36B_MLB MCP Constraints K36B_MLB MCP Constraints K36B_MLB Ethernet Constraints K36B_MLB FireWire Constraints K36B_MLB SMC Constraints K36B_MLB K36B RULE DEFINITIONS K36B_MLB 66 08/29/2008 67 08/29/2008 68 08/29/2008 69 08/17/2008 70 08/17/2008 72 08/17/2008 73 08/17/2008 74 08/17/2008 75 08/17/2008 76 08/17/2008 77 08/17/2008 78 08/17/2008 79 08/17/2008 90 08/17/2008 93 08/17/2008 94 B 08/17/2008 100 08/17/2008 101 08/17/2008 102 08/17/2008 103 08/17/2008 104 08/17/2008 105 08/17/2008 106 08/17/2008 109 08/17/2008 TABLE_TABLEOFCONTENTS_ITEM DIMENSIONS ARE IN MILLIMETERS A APPLE INC METRIC XX X.XX DRAFTER Schematic / PCB #’s PART NUMBER THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING ENG APPD MFG APPD QA APPD DESIGNER RELEASE SCALE I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART ANGLES QTY DESCRIPTION REFERENCE DES CRITICAL 051-8089 SCHEM,MLB,K36C SCH CRITICAL 820-2496 PCBF,MLB,K36B PCB CRITICAL A NOTICE OF PROPRIETARY PROPERTY DESIGN CK X.XXX TITLE DO NOT SCALE DRAWING BOM OPTION SCHEM,MLB,K36C NONE SIZE THIRD ANGLE PROJECTION MATERIAL/FINISH NOTED AS APPLICABLE D DRAWING NUMBER REV 051-8089 02 SHT 1 OF 109 U1000 J1300 INTEL CPU XDP CONN 2.X OR 3.X GHZ PG 12 PENRYN PG FSB D D J6950 64-Bit 800/1067/1333 MHz DC/BATT POWER SUPPLY PG 13 PG 60 J3100,3200 MAIN FSB INTERFACE GPIOs MEMORY UDIMMs DDR2-800MHZ DIMM PG 14 J5520 PG 25,26 TEMP SENSOR PG 41 Misc CLK PG 24 U6100 SYNTH POWER SENSE PG 45 SPI Boot ROM J4501 J5601 FAN CONN AND CONTROL SPI SATA PG 52 Conn 3GHZ PG 48,49 PG 20 PG 38 HD NVIDIA J4500 U4900 B,0 SATA Conn PG 38 C ADC BSB Fan Ser J5100 MCP79 SATA 3GHZ Prt SMC LPC Conn LPC PG 19 ODD Port80,serial PG 41 C PG 43 PG 18 U1400 J9001 PWR LVDS CONN CTRL LVDS OUT PG 71 RGB OUT J4810 DP OUT J5800 J4501 J9001 TRACKPAD/ KEYBOARD Bluetooth J9401 IR J4600,4601 CAMERA HDMI OUT PG 40 PG 40 PG 16 PCI-E UP TO 20 LANES3 B PG 17 USB TMDS OUT PG 19 PG 71 PG 40 PG 39 DVI OUT (UP TO 12 DEVICES) MINI DVI CONN EXTERNAL USB Connectors PG 40 B SMB SMB PG 20 CONN RGMII HDA PCI PG 44 DIMM’s (UP TO FOUR PORTS) PG 17 PG 18 PG 20 U6200 Audio U4100 Codec PCI-E FIREWIRE PG 53 FW643E PG 35 J4300 U6801 U6801 System Block Diagram U6610,6620,6630 U3700 A FW PORT GB Conn E-NET HEADPHONE Line Out Speaker Amp Amp Amps PG 55 PG 56 PG 57 SYNC_MASTER=K36B_MLB SYNC_DATE=08/17/2008 NOTICE OF PROPRIETARY PROPERTY 88E1116 PG 37 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING PG 31 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE J3400 II NOT TO REPRODUCE OR COPY IT J3900 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART MINI PCI-E J6800,6801,6802,6803 E-NET AirPort Conn PG 28 Audio SIZE Conns D PG 33 PG 59 APPLE INC DRAWING NUMBER SCALE SHT NONE REV 051-8089 02 OF 109 A K36B POWER SYSTEM ARCHITECTURE D6905 02 PPVIN_G3H_P3V42G3H D6905 D V 7A FUSE PPVBAT_G3H_CHGR_REG 01 03 SHDN* 3.425V G3HOT VIN LT3470 VOUT U6990 PBUS_VSENSE PP3V42_G3H_REG D 02 22 VIN AC DCIN(16.5V) ADAPTER IN CPUVTTS0_EN (S0) VIN VOUT SMC_BATT_ISENSE 01 02 A VOUT ISL9504B CHGR_BGATE P3V3S3_EN U4900 RC DELAY U1400 DDRREG_EN P60 04-1 ENTRIP1 PP1V05_S5_REG P1V05_S5_PGOOD VIN EN1 SMC_PM_G2_EN 5V (RT) VOUT1 (S5) ENTRIP2 3.3V 11-2 P5VLTS3_EN PGOOD RESET* 08 32 09 PP5VRT_S0_REG PP5VLT_S3_REG 17 PP3V3_S5 06 (4A MAX CURRENT) Q7910 TPS51125 U7200 05 PP4V6_AUDIO_ANALOG OVT (4A MAX CURRENT) VOUT2 EN2 C PWRGOOD U1000 PP3V3_S5_REG RC DELAY RC DELAY U6201 EN VOUT PG 02 Q7800 PCI_RESET0# 31 1.05V (S5) P1V05_S5_EN RC DELAY 4.6V AUDIO IN MAX8902A TPS62510 PVIN U7750 SMC P16 11-3 CPU_RESET# U1400 U2850 CPU 07 15 29 26 U7400 EN 11-1 MCP_PS_PWRGD PS_PWRGD PPBUS_G3H PM_SLP_S4_L CPU_PWRGD 28 VR_PWRGOOD_DELAY PGOOD 25 11 30 PPVCORE_S0_CPU_REG (44A MAX CURRENT) SMC_CPU_ISENSE VR_ON PPVBAT_G3H_CHGR_OUT 29-1 RSMRST* SMC_CPU_VSENSE V CPU VCORE IMVP_VR_ON Q7050 BATT_POS_F LPC_RESET_L LPC_RESET0* CPUPWRGD VIN C MCP79 CPUVTTS0_PGOOD J6950 3S2P PP1V05_S0_FET PGOOD A ISL6258A U7000 SLP_S3# 09-1 PWRBTN* R7955 TPS51117 U7600 U5403 SMC_DCIN_ISENSE MCP79 PPCPUVTT_S0_REG (8A MAX CURRENT) VOUT CPUVTT ENABLES A PBUS SUPPLY/ BATTERY CHARGER (9 TO 12.6V) EN_PSV (1.05V) 6A FUSE SMC_RESET_L Q5315 PPBUS_G3H CHGR_EN (S5) 04 SMC PWRGD RN5VD30A-F U5000 PP3V3_S3_FET VREG3 13 11-1 P3V3S3_EN P5V3V3_PGOOD Q7930 B 18 PP3V3_S0_FET 15 PM_SLP_S3_L RSMRST_OUT(P15) PWRGD(P12) 09-1 RSMRST_PWRGD Q3805 P3V3S0_EN Q3810 P3V3_ENET_FET 1.5V (S0) PM_WLAN_EN_L PVIN 16 19-1 PP1V5_S0_FET TPS62510 16-3 P1V5S0_EN EN U7740 SMC_ONOFF_L 99ms DLY IMVP_VR_ON(P16) RSMRST_IN(P13) SMC_LRESET_L PWR_BUTTON(P90) P17(BTN_OUT) VOUT P3V3ENET_EN_L P5V3V3_PGOOD AP_PWR_EN P1V5_S0_PGOOD PP1V8_S0_FET SMC_ADAPTER_EN 02 VIN =DDRREG_EN =DDRVTT_EN A P1V5S0_EN RC DELAY MCPDDR_EN RC DELAY CPUVTTS0_EN RC DELAY 16-3 P1V05S0_EN (S0) P3V3S0_EN (S0) 16-3 PBUSVSENS_EN (S0) 16-2 P5VRTS0_EN_L (S0) 16-1 16-4 S3 14 1.8V VOUT1 0.9V VOUT2 PP1V5_S0_FET R5490 PP1V5_S0 MCPCORES0_EN 11-2 P5VLTS3_EN VOUT2 EN2 5V (LT) EN1 SLP_S4_L SLP_S3_L P5V_LT_S3_PGOOD SMC_RESET_L SLP_S4_L(P94) SLP_S3_L(P93) U4900 21 PPVCORE_S0_MCP_REG_R R5490 PPVCORE_S0_MCP PP3V3_S0 SEL PP1V8_S0 ADJ1 PP1V05_S0 ADJ2 LTC2909 20 Power Block Diagram SYNC_MASTER=K36B_MLB THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING (23A MAX CURRENT) PP5VLT_S3_REG PP5VLT_S3 SYNC_DATE=08/17/2008 NOTICE OF PROPRIETARY PROPERTY U7870 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE 12 II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART VOUT1 SIZE PP5V_LT_S3_PGOOD PGOOD1 U7500 DRAWING NUMBER D SN0802043 02 PM_PWRBTN_L SLP_S5_L(P95) (4.5A MAX CURRENT) VIN B 25 RST* PP0V9_S0_REG (1A MAX CURRENT) MCP_CORE IMVP_VR_ON (Q7901 & Q7971) PP1V8_S3_REG (12A MAX CURRENT) TPS51116 U7300 16-2 16-2 MCPCORES0_EN 16-2 S5 SLP_S5_L S0PGOOD_PWROK S3 TO S0 FETS RC DELAY 21 PP1V8_S0_REG FL7700 04-1 PM_SLP_S3_L 1.8V S0 MCPCORES0_PGOOD CPUVTTS0_PGOOD PM_RSMRST_L RST* P1V5_S0_PGOOD Q3805 10 SMC 24 ALL_SYS_PWRGD MCPCORES0_PGOOD APPLE INC PGOOD2 SCALE SHT NONE REV 051-8089 02 OF 109 A PAGE_BORDER=TRUE Page Notes Power aliases required by this page: (NONE) Signal aliases required by this page: (NONE) BOM options provided by this page: (NONE) D D ALTERNATES OPTION BOM OPTION TABLE_5_HEAD PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION TABLE_ALT_HEAD PART NUMBER ALTERNATE FOR PART NUMBER REF DES COMMENTS: 128S0093 128S0218 ALL ALTERNATE PER CYNDI 152S0694 152S0138 ALL ALTERNATE PER CYNDI 152S0847 152S0586 ALL ALTERNATE PER CYNDI 152S0874 152S0516 ALL ALTERNATE PER CYNDI 152S0796 152S0685 ALL ALTERNATE PER CYNDI 152S0778 152S0693 ALL ALTERNATE PER CYNDI 157S0058 157S0055 ALL ALTERNATE PER CYNDI TABLE_5_ITEM 341S2420 IC,SMC,HS8/2117,9X9MM,TLP,HF,BLANK U4900 CRITICAL SMC_PROG 341S2418 IC,FLASH,SPI,32MBIT,3.3V,86MHZ,8-SOP U6100 CRITICAL BOOTROM_PROG BOM OPTION TABLE_ALT_ITEM TABLE_5_ITEM TABLE_ALT_ITEM TABLE_5_ITEM 341S2093 IC, CYPRESS, CY7C63833 U4800 CRITICAL 338S0654 IC,FW643E,1394B PHY/OHCI LINK/PCI-E,127 U4100 CRITICAL TABLE_ALT_ITEM TABLE_5_ITEM TABLE_ALT_ITEM TABLE_ALT_ITEM TABLE_5_HEAD C PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL TABLE_ALT_ITEM BOM OPTION TABLE_5_ITEM 826-4393 [EEE:3TN] LBL,P/N LABEL,PCB,28MMX6MM C TABLE_ALT_ITEM CRITICAL TABLE_5_HEAD PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION TABLE_5_ITEM TABLE_5_HEAD 337S3769 U1000 PDC,SLGVT,2.26,25W,1066,R0,3M,BGA,P7750 CRITICAL PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION TABLE_5_ITEM 514-0665 CONN,RCPT,MINI-DVI,32P,R/A J9401 CRITICAL 514-0666 CONN,RCPT,3.5MM AUDIO IN,R/A J6750 CRITICAL 514-0667 CONN,RCPT,3.5MM AUDIO OUT,R/A J6700 CRITICAL 514-0668 CONN,RCPT,RJ45,NO FILTER,8P J3900 CRITICAL 514-0669 CONN,RCPT,USB,4P,MIDPLANE J4600 CRITICAL 514-0669 CONN,RCPT,USB,4P,MIDPLANE J4601 CRITICAL TABLE_5_ITEM TABLE_5_HEAD PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION TABLE_5_ITEM TABLE_5_ITEM 338S0702 U1400 IC,GMCP,MCP79,35X35MM,BGA1437,B03 CRITICAL TABLE_5_ITEM TABLE_5_ITEM TABLE_5_HEAD TABLE_5_ITEM PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION TABLE_5_ITEM 338S0694 B IC,RTL8251CA-VB-GR,GIGE TRANSCEIVER,48P U3700 CRITICAL B BOARD STACK-UP AND CONSTRUCTION Top 10 11 BOTTOM A SIGNAL GROUND SIGNAL(High SIGNAL(High GROUND POWER POWER GROUND SIGNAL(High SIGNAL(High GROUND SIGNAL Speed) Speed) CONFIGURATION OPTIONS Speed) Speed) SYNC_MASTER=K36B_MLB THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC REV 051-8089 SCALE SHT NONE SYNC_DATE=08/17/2008 NOTICE OF PROPRIETARY PROPERTY 02 OF 109 A Revision History D C B A *****2008/08/21***** PAGE 61: - U7500 PIN V5DRV1 LINK TO PP5V_S0_MCPREG_VCC - U7500 PIN TONSEL LINK TO GND DIRECTLY PAGE 64: - R7859 CHANGE TO 100 OHM - R7879 CHANGE TO 100K OHM PAGE 65: - DELETE 1.05V S0 FET CIRCUIT PAGE 57: - R7011 CHANGE TO 9.31K OHM, 1% *****2008/08/22***** PAGE 7: - ADD SMC_EXCARD_PWR_EN TEST_POINT PAGE 8: - ADD =PP3V42_G3H_RTC_D LINK TO =PP3V42_G3H_REG PAGE 14: - R1410 CHANGE TO 49.9 OHM - CHANGE R1440 TO 150_5% AND NO STUFF PAGE 26: - R2872 CHANGE TO 0OHM - RTC FOLLOW M97 DESIGN AND USE SUPERCAP SOLUTION - MCP S0 PWRGD FOLLOW M97 DESIGN PAGE 29: - PULL R3240 DOWN TO GND PULL R3241 HIGH PAGE 32,33,34 - FOLLOW M97 DESIGN PAGE 39: - D4600/D4601/PIN-6 CONNECT TO USB VBUS (FOLLOW M97D) PAGE 44: - R5270/R5271 = 1K (FOLLOW M97D) - R5280/R5281 = 1K (FOLLOW M97D) PAGE 68: - CHANGE C9411, C9412 TO 220PF - CHANGE R9462, R9463 TO 2.7KOHM - ADD C9480 0.1UF_16V_0402 FROM GND_CHASSIS_TMDS_DOWN TO GND - CHANGE R9460,R9461 TO 0OHM, - CHANG C9442 AND C9443 TO 47PF *****2008/08/23***** MODIFY ALL NOSTUFF TO NO STUFF PAGE 6: - REMOVE ETHERNET CIRCUIT PAGE 8: - ADD =PP3V3_S5_P3V3ENETFET LINK TO PP3V3_S5 - ADD =PP1V05_ENET_PHY LINK TO PP1V2R1V05_ENET PAGE 9: - ADD =RTL8211_ENSWRE LINK TO GND - ADD =PP3V3_ENET_PHY_VDDREG LINK TO TP_PP3V3_ENET_PHY_VDDREG - ADD =RTL8211_REGOUT LINK TO NC_RTL8211_REGOUT - =P3V3ENET_EN_L LINK TO PM_SLP_RMGT_L - =P1V05ENET_EN LINK TO PM_SLP_RMGT_L PAGE 10: - CHANGE XDP_TDO_CONN TO XDP_TDO PAGE 13: - XDP FOLLOW M98 DESIGN CONNECTOR FROM 516S0625 CHANGE TO 998-1571 PLAGE 23: - DELETE R2400~R2413 FOR MCP A01 VERSION PAGE 31: - REMOVE R3400, R3401 - L3401 FROM NO STUFF CHANGE TO STUFF PAGE 39 - DELETE R4699 - R4690 FROM NO STUFF CHANGE TO STUFF PAGE 41: - SMC_NB_DDR_ISENSE CHANGE TO SMC_MCP_DDR_ISENSE - SMC_NB_CORE_ISENSE CHANGE TO SMC_MCP_CORE_ISENSE PAGE 46: - SMC_NB_DDR_ISENSE CHANGE TO SMC_MCP_DDR_ISENSE - SMC_NB_CORE_ISENSE CHANGE TO SMC_MCP_CORE_ISENSE - R5417 ADD BOM OPTION FOR NO STUFF - R5416 ADD BOM OPTION FOR NO STUFF PAGE 50: - ADD C5926 (10UF,20%.0603) TO =PP3V3_S3_SMS PAGE 63: - REMOVE USB_PWR_EN_S3 PAGE 66: - REMOVE R9010, R9011 *****2008/08/24***** PAGE 6: - R0602 BOMOPTION FROM JTAG_1DEV CHANGE TO NO STUFF PAGE 13: - XDP FOLLOW M97 DESIGN CONNECTOR FROM 998-1571 CHANGE TO 516S0625 PAGE 18: - R1860 AND R1861 CHANGE TO PAGE 68 PAGE 25: - C2504-C2507 FROM 138S0578(402) CHANGE TO 138S0614(402-1) - C2516-C2517 FROM 138S0578(402) CHANGE TO 138S0614(402-1) PAG3 35: - R4150 FROM 118S0343 (0201) CHANGE TO 116S0056(0402) PAGE 58: - C7281, C7241, C7272 FROM 138S0555(603) CHANGE TO 138S0615(603-1) - C7280, C7240 FROM 128S0092(POLY) CHANGE TO 128S0128(POLY-TANT) - C7291, C7292, C7252, C7251 FROM 128S0115(POLY,CASE-B2) CHANGE TO 128S0222(POLY,CASE-B2-SM) - Q7260, Q7261 FROM 376S0512 CHANGE TO 376S0652 (H-F) PAGE 59: - Q7320 FROM 376S0512 CHANGE TO 376S0652 (H-F) - Q7321 FROM 376S0511 CHANGE TO 376S0651 (H-F) - C7321 FROM 128S0111(POLY) CHANGE TO 128S0218 (POLY,CASE-D2E-SM) - C7343 FROM 128S0073 CHANGE TO 128S0233 PAGE 60: - XW7400 ADD BOMOPTION OMIT - Q7400, Q7402 FROM 376S0472 CHANGE TO 376S0617 PAGE 61: - L7500 FROM 152S0869 CHANGE TO 152S0685 - Q7500 FROM 376S0512 CHANGE TO 376S0652 - C7560 FROM 128S0092 CHANGE TO 128S0218 PAGE 62: - Q7620 FROM 376S0512 CHANGE TO 376S0652 - C7601 FROM 138S0578 CHANGE TO 138S0614 *****2008/08/25***** CHANGE CSA BASE ON WILL’S SUGGESTION PAGE 9: - ADD GMUX_JTAG_TMS AND GMUX_JTAG_TDI IN MISC NC MCP79 ALIASES PAGE 18: - NETNAME ENET_INTR_L CHANGE TO TP_ENET_INTR_L - ENET_PWRDWN_L CHANGE TO TP_ENET_PWRDWN_L PAGE 19: - DELETE R1987,R1988,R1995,R1970,R1971,R1972,R1973,R1996,R1997,R1998,R1999,R1978,R1979 (FOLLOW M97 DESIGN) - NET DPMUX_LOWPWR_L SYNC M97 NETNAME AUD_IPHS_SWITCH_EN - NET LVDSMUX_SEL_IG_L SYNC M97 NETNAME - NET DPMUX_SEL_IG_L SYNC M97 NETNAME PAGE 28: - REMOVE NET DIMM_OVERTEMPA_L PAGE 29: - REMOVE NET DIMM_OVERTEMPA_L PAGE 42: - ADD SMC_EXCARD_PWR_EN TO TP_SMC_EXCARD_PWR_EN - ADD SMC_RSTGATE_L TO TP_SMC_RSTGATE_L - ADD ALS_GAIN TO NC_ALS_GAIN - ADD ESTARLDO_EN TO NC_ESTARLDO_EN - ADD SMC_ANALOG_ID TO NC_SMC_ANALOG_ID - ADD SMC_SYS_KBDLED TO NC_SMC_SYS_KBDLED - ADD R5054 10KOHM LINK SMC_GPU_ISENSE PULL DOWN TO GND - ADD R5055 10KOHM LINK SMC_NB_MISC_ISENSE PULL DOWN TO GND PAGE 43: - R5142 CHANGE TO NO STUFF PAGE 46: - R5416 CHANGE TO 4.53K AND DELETE BOM OPTION - R5417 CHANGE TO 4.53K AND DELETE BOM OPTION - R5418 CHANGE TO 4.53K AND DELETE BOM OPTION PAGE 57: - NETNAME FROM CHGR LOWCURRENT REF CHANGE TO CHGR_LOWCURRENT_REF - NETNAME FROM CHGR LOWCURRENT GATE CHANGE TO CHGR_LOWCURRENT_GATE PAGE : - REMOVE R7884 AND C7884 PAGE 66: - REMOVE J9001 PIN 20 AND PIN21 NET *****2008/09/02***** PAGE 45: - CHANGE ODD CONNECTOR FROM 516S0720 TO 516S0719 *****2008/09/27***** PAGE 9: - ADD STANDOFF 860-0964 X - ADD STANDOFF 860-0723 X - ADD STANDOFF 860-0749 X PAGE 29: - REMOVE BOMOPTION TABLE OF R2903/R2905/R2909/R2911 PAGE 66: - C6601/C6603 CHANGE TO APN 128S0135, and REMOVE BOMOPTION OMIT - C6605 CHANGE TO APN 128s0148, HF APN 128s0221, and REMOVE BOMOPTION OMIT PAGE 68: - C6830/C6831 CHANGE TO APN 128S0220, and REMOVE BOMOPTION OMIT PAGE 72: - R7272 CHANGE FROM 57.6K 1%(114s0389) TO 75K 1%(114s0399) *****2008/10/31***** PAGE 41: - U4100 CHANGE FROM 338S0523 TO 338S0654 *****2008/11/01***** PAGE 4: - BOM change U1400 CHANGE FROM 338S0678 TO 338S0702 *****2008/11/05***** PAGE 62: - C6210 CHANGE FROM 127S0062 TO 127S0108 PAGE 68: - C6832, C6833 CHANGE FROM 127S0062 TO 127S0108 PAGE 45: - DELETE L4502, NET SATA_HDD_D2R_UF_P / SATA_HDD_D2R_UF_N - L4501 / Fl4520 / FL4525 CHANGE FROM 155S0303 TO 155S0371 PAGE 102: - DELETE PHYSICAL/SPACING SETTING OF SATA_HDD_D2R_UF_P / SATA_HDD_D2R_UF_N D *****2008/11/06***** - U5413 CHANGE FROM 353S1432 TO 353S2220 - R7417 CHANGE FROM 5.36K(114S0289) TO 4.42K(114S0280) *****2008/11/12***** - U1000 CHANGE FROM 373S3646 TO 373S3702 *****2008/11/19***** - J6950 CHANGE FROM 516S0620 TO 516S0735 - J9401 CHANGE FROM 514-0517 TO 514-0665 - J6750 CHANGE FROM 514-0519 TO 514-0666 - J6700 CHANGE FROM 514-0521 TO 514-0667 - J3900 CHANGE FROM 514-0523 TO 514-0668 - J4600, J4601 CHANGE FROM 514-0527 TO 514-0669 - U3700 CHANGE FROM 338S0570 TO 338S0694 *****2008/11/26***** - PAGE 61 NOTE : CORRECT REFERENCE TO R5164 AND R5144 - J3400 CHANGE TO 516S0729 *****2008/12/12***** - R5144 and R5164 changed to 10K 5% 0402 (116S0090) C *****2008/12/17***** - U4900 symbol update *****2008/12/20***** - R5156, R5157, R5158 change from to 33 ohm, 5%, 0402(116s0030) *****2008/10/20***** PAGE 29: - ADD R2903/R2905 BOMOTION AND CHANGE VALUE TO 200 OHM PAGE 50: - REMOVE ALT TABLE PAGE 74: - REMOVE ALT TABLE PAGE 94: - REMOVE K36 BOM OPTION TABLE AND ALT TABLE *****2008/10/22***** PAGE 12: - C1200 ~ C1219 CHANGE TO 138S0580 PAGE 28: - C2870 CHANGE TO 138S0614 PAGE 37: - ADD R3731 (116s0026 22 ohm 5% 0402) FOR EMI 125MHZ NOISE - TP_RTL8211_CLK125 CHANGE TO RTL8211_CLK125 PAGE 48: - C4803 CHANGE TO 138S0614 PAGE 66: - C6605 CHANGE TO HF APN 128S0221 PAGE 70: - C7040/C7041/C7047 CHANGE TO 138S0614 PAGE 90: - L9002 CHANGE TO 116S0004(0ohm,5%,0402) - C9003 CHANGE TO 116S0004(0ohm,5%,0402) B *****2008/10/24***** PAGE 19: - R1950/R1951/R1952/1953 CHANGE TO 116s0004 (0 OHM,5%,0402) PAGE 28: - R2825/R2826 CHANGE TO 116s0004 (0 OHM,5%,0402) PAGE 34: - J3400 516S0635 CHANGE TO HF APN 516S0729 PAGE 52: - ADD C5250/C5251/C5270/C5271/C5260/C5261/C5280/C5281 131S1104 (22pF,5%,0402) NO STUFF - TEXT "ALS" CHANGE TO "MINI-PCIE" - I2C_ALS_SCL CHANGE TO I2C_MINI_PCIE_SCL - I2C_ALS_SDA CHANGE TO I2C_MINI_PCIE_SDA PAGE 67: - J6700 514-0604 CHANGE TO HF APN 514-0521 - J6750 514-0603 CHANGE TO HF APN 514-0519 PAGE 69: - J6950 516S0620 CHANGE TO HF APN 516S0735 02 SYNC_MASTER=K36B_MLB *****2008/10/25***** PAGE 52: - STUFF C5250/C5251/C5270/C5271/C5260/C5261/C5280/C5281 *****2008/10/28***** PAGE 34: - J3400 516S0729 CHANGE TO 516S0635 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT *****2008/10/30***** PAGE 69: - J6950 516S0735 CHANGE TO 516S0620 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC NOTE: All page numbers are csa, not PDF REV 051-8089 SCALE SHT NONE See page for csa -> PDF mapping A NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING 02 OF 109 D D 1.05V TO 3.3V LEVEL TRANSLATOR (K36B: ON ICT FIXTURE) =PP3V3_S0_XDP 13 To XDP connector and/or level translator =PP1V05_S0_CPU 13 12 11 10 U1000 CPU From XDP connector JTAG_ALLDEV C0601 JTAG_ALLDEV 0.1UF C0602 0.1UF 20% 10V CERM 402 20% 10V CERM 402 69 13 10 IN 69 13 10 IN 69 13 10 IN 69 13 10 IN XDP_TCK XDP_TDI XDP_TMS XDP_TRST_L XDP R0603 69 10 XDP_TDO XDP_TDO_CONN 5% 1/16W MF-LF 402 JTAG_ALLDEV OUT 13 XDP connector R06011 11 10K 5% 1/16W MF-LF 402 From XDP connector or via level translator VCCA VCCB U0600 C U1400 MCP NLSV4T244 69 13 10 XDP_TCK NO STUFF R06021 5% 1/16W MF-LF 402 69 13 10 69 13 10 XDP_TMS XDP_TRST_L UQFN A1 A2 A3 JTAG_ALLDEV A4 B1 B2 B3 B4 JTAG_MCP_TCK MAKE_BASE=TRUE JTAG_MCP_TDI MAKE_BASE=TRUE JTAG_MCP_TMS MAKE_BASE=TRUE JTAG_MCP_TRST_L 10 C 13 21 XDP 13 21 R0604 13 21 13 21 21 JTAG_MCP_TDO MAKE_BASE=TRUE JTAG_LVL_TRANS_EN_L 12 JTAG_MCP_TDO_CONN 5% 1/16W MF-LF 402 OE* 13 XDP connector GND OUT B B JTAG Scan Chain A SYNC_MASTER=K36B_MLB SYNC_DATE=08/17//2008 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC SCALE SHT NONE REV 051-8089 02 OF 109 A Functional Test Points # J4501 SATA HD System LED and IR #J5601 Fan Connectors D TRUE TRUE TRUE TRUE I12 I15 I16 I157 PP5VRT_S0 FAN_RT_PWM FAN_RT_TACH I284 48 I283 I282 48 GND I281 I280 #J6950 Battery/Lid Connector I279 I290 TRUE TRUE TRUE TRUE TRUE TRUE TRUE I292 TRUE I285 I286 I288 I287 I289 I291 SMC_BS_ALRT_L_F SMBUS_BATT_SCL_F SMBUS_BATT_SDA_F PPVBAT_G3H_CONN_F SMC_LID_F GND_SMC_LID_F 56 I278 56 I277 56 I276 56 TRUE TRUE TRUE I274 I275 56 I273 I272 I293 I295 I296 I298 I299 I269 56 I270 56 Need TP I267 #J9000 INVERTER Connector I268 TRUE TRUE TRUE TRUE I297 Need TP I271 I266 PPBUS_ALL_INV_CONN Need TP 66 INV_GND 66 PP5V_INV_F 66 INV_BKLIGHT_PWM_L Need TP 66 I264 I265 I263 I262 I261 #J9001 LCD + CAMERA CONNECTOR C TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE I300 I301 I303 I302 I305 I304 I306 I307 I308 I309 I310 I311 I313 I312 I315 I314 PP3V3_LCDVDD_SW_F PP3V3_S0_LCD_F LVDS_IG_DDC_CLK I259 I260 66 66 I316 I317 I318 I320 B LVDS_IG_DDC_DATA LVDS_IG_A_DATA_N LVDS_IG_A_DATA_P LVDS_IG_A_DATA_N LVDS_IG_A_DATA_P LVDS_IG_A_DATA_N LVDS_IG_A_DATA_P LVDS_IG_A_CLK_F_N LVDS_IG_A_CLK_F_P USB2_CAMERA_CONN_P USB2_CAMERA_CONN_N PP5V_S3_CAMERA_F GND 18 66 I258 18 66 71 I256 18 66 71 I257 18 66 71 I255 18 66 71 I254 18 66 71 I253 18 66 71 I252 66 I251 66 I250 66 72 I248 66 72 I249 I246 66 I247 MIC_LO_CONN MIC_HI_CONN MIC_SHLD_CONN I245 I244 54 I243 54 I242 54 55 I240 I241 SPKRCONN_L_P_OUT SPKRCONN_L_N_OUT I239 53 54 I237 53 54 I235 #J6703 Right SUB SPEAKER CONNECTOR TRUE TRUE TRUE TRUE I321 I322 I323 I324 SPKRCONN_SUB_P_OUT SPKRCONN_SUB_N_OUT SPKRCONN_R_P_OUT SPKRCONN_R_N_OUT I236 53 54 I234 53 54 I233 53 54 I232 53 54 I230 I231 # J5800 GEYSER AND DIMM0 REMOTE TEMP SENSORS I326 I325 I328 I327 I329 I330 TRUE TRUE TRUE TRUE TRUE TRUE I198 TPAD_GND_F CONN_TPAD_ONOFF_FLTR_L CONN_TPAD_USB_P CONN_TPAD_USB_N SMC_LID_LC PP5V_S3_TPAD_F I196 71 I197 38 I195 I193 40 I194 I192 I191 I190 I188 PCIE_WAKE_L 17 31 I189 MINI_CLKREQ_L PCIE_CLK100M_MINI_N PCIE_CLK100M_MINI_P PCIE_MINI_D2R_N 17 31 17 31 71 I186 I187 17 31 71 I185 17 31 71 I183 PCIE_MINI_D2R_P PCIE_MINI_R2D_N 17 31 71 31 71 PCIE_MINI_R2D_P 31 PP3V3_WLAN Need TP 31 PP1V5_S0_R Need TP MINI_RESET 31 PP3V3_S3_AIRPORT_CONN 31 I2C_MINI_PCIE_SCL 31 I2C_MINI_PCIE_SDA 31 USB2_AIRPORT_N 31 USB2_AIRPORT_P 31 Need TP GND 71 I184 I182 I181 I180 I178 I179 I177 44 I175 44 I176 72 I173 72 I174 I172 I171 I170 I238 TRUE TRUE 71 71 18 66 #J6702 Left SPEAKER CONNECTOR I319 I199 # Other Func Test Points # J6701 MIC CONNECTOR TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE #J1300 71 #J3400 Airport 56 PP3V42_G3H_LIDSWITCH_F Need TP GND PP18V5_DCIN_FUSE ADAPTER_SENSE GND SATA_HDD_R2D_P 38 SATA_HDD_R2D_N 38 SATA_HDD_D2R_C_N 38 SATA_HDD_D2R_C_P 38 PP5V_S0_HDD_FLT Need TP SYS_LED_ANODE_L 38 IR_RX_OUT 38 PP5V_S3_IR_CONN 38 Need TP GND 56 #J6900 MagSafe DC Power Jack I294 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE I229 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE ALL_SYS_PWRGD PPVCORE_S0_CPU PPCPUVTT_S0 PPVCORE_S0_MCP_R PPVCORE_S0_MCP PP0V9_S0 PP1V05_S0 PP1V5_S0_R PP1V8_S0 PP1V8_S0_R PP1V05_S0_MCP_PEX_AVDD PP1V05_S0 PP1V05_S0_MCP_SATA_AVDD PP1V05_S0 PP5VRT_S0 PP3V3_S0 PP1V0_FW PP1V8_S3 PP3V3_S3 PP5VLT_S3 PPVTT_S3_DDR_BUF PP1V05_S5_REG PP3V3_S5 PP3V42_G3H PP18V5_G3H PPBUS_G3H PPBUS_G3H_CPU_ISNS PP3V3_ENET_PHY PP1V2R1V05_ENET PPVP_FW 26 41 64 I169 I168 I167 I165 I166 I163 I164 I162 I161 I160 24 I159 I158 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE # J5100 LPC+SPI Connector XDP XDP_BPM_L XDP_BPM_L XDP_BPM_L XDP_BPM_L XDP_BPM_L XDP_BPM_L TP_XDP_OBSFN_B0 TP_XDP_OBSFN_B1 TP_XDP_OBSDATA_B0 TP_XDP_OBSDATA_B1 TP_XDP_OBSDATA_B2 TP_XDP_OBSDATA_B3 XDP_PWRGD XDP_OBS20 PM_LATRIGGER_L JTAG_MCP_TCK SMBUS_MCP_0_DATA SMBUS_MCP_0_CLK XDP_TCK PPCPUVTT_S0 PP3V3_S0 JTAG_MCP_TDO_CONN JTAG_MCP_TRST_L MCP_DEBUG MCP_DEBUG MCP_DEBUG MCP_DEBUG JTAG_MCP_TDI JTAG_MCP_TMS MCP_DEBUG MCP_DEBUG MCP_DEBUG MCP_DEBUG FSB_CLK_ITP_P FSB_CLK_ITP_N XDP_CPURST_L I227 10 13 69 I228 10 13 69 I226 10 13 69 I225 10 13 69 I224 10 13 69 I223 13 I222 13 I221 13 I219 13 I220 13 I217 13 I218 13 I216 13 I215 13 19 I214 13 21 I213 13 21 44 72 I212 13 21 44 72 I211 10 13 69 I209 I210 I207 13 I208 13 21 I206 13 19 72 I203 13 19 72 I204 13 19 72 I205 13 19 72 I202 13 21 I201 13 21 I200 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE PP3V42_G3H PP5VRT_S0 LPC_AD LPC_AD SPI_ALT_MOSI SPI_ALT_MISO LPC_FRAME_L PM_CLKRUN_L SMC_TMS DEBUG_RESET_L D 8 19 41 43 72 19 41 43 72 43 43 19 41 43 72 19 41 43 41 42 43 26 43 SMC_TDO 41 42 43 SMC_TRST_L SMC_MD1 SMC_TX_L LPC_CLK33M_LPCPLUS LPC_AD LPC_AD 41 43 41 43 39 41 42 43 26 43 72 19 41 43 72 19 41 43 72 SPIROM_USE_MLB SPI_ALT_CLK SPI_ALT_CS_L 43 43 43 LPC_SERIRQ LPC_PWRDWN_L SMC_TDI 19 41 43 19 41 43 41 42 43 SMC_TCK SMC_RESET_L SMC_NMI SMC_RX_L 41 42 43 41 42 43 41 43 39 41 42 43 LPCPLUS_GPIO C 18 43 Need TP GND 13 19 72 13 19 72 13 19 72 13 19 72 13 14 69 13 14 69 13 69 XDP_DBRESET_L XDP_TDO_CONN XDP_TRST_L XDP_TDI XDP_TMS GND 10 13 69 10 13 26 13 10 13 69 10 13 69 10 13 69 Need TP 24 8 8 8 8 8 B 8 8 8 49 49 49 72 49 72 49 49 #J5520 CPU/MCP Thermal Sensor I331 I332 I334 I333 TRUE TRUE TRUE TRUE CPUTHMSNS_D2_P CPUTHMSNS_D2_N MCPTHMSNS_D2_P 47 47 47 MCPTHMSNS_D2_N 47 #J4810 BLUETOOTH I335 I336 I337 I338 A TRUE TRUE TRUE TRUE PP3V3_S3_BT_F_CONN USB2_BT_F_N_CONN 40 40 72 USB2_BT_F_P_CONN GND_BT_F_CONN 40 72 FUNC TEST 40 #J4500 SATA ODD I340 I339 I342 I341 I343 I345 I344 TRUE TRUE TRUE TRUE TRUE TRUE TRUE THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC REV 051-8089 SCALE SHT NONE A NOTICE OF PROPRIETARY PROPERTY SATA_ODD_R2D_UF_P 38 71 SATA_ODD_R2D_UF_N 38 71 SATA_ODD_D2R_C_N 38 71 SATA_ODD_D2R_C_P 38 71 PP3V3_S0 Need TP SMC_ODD_DETECT 38 41 GND Need TP 02 OF 109 "S0,S0M" RAILS "G3H" RAILS "S3" RAILS 56 =PPVCORE_S0_CPU_REG 60 (CPU VCORE PWR) PPVCORE_S0_CPU 58 =PP5VRT_S0_REG 45 43 48 PPCPUVTT_S0 =PP5V_S0_ODD =PP5V_S0_TMDS =PP5V_S0_LCD =PP5V_S0_CPUVTTS0 =PP5V_S0_AUDIO =PP5V_S0_AUDIO_AMP MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V MAKE_BASE=TRUE =PP1V05_S0_CPU =PP1V05_S0_MCP_FSB =PP1V05_S0_SMC_LS 10 11 12 13 14 22 24 =PP1V8_S3_P1V8S0FET 65 =PP1V8_S3_MEM 28 29 60 38 65 21 =PP3V3_S3_FET PP3V3_S3 62 =PP3V3_S3_SMBUS_SMC_A_S3 =PP3V3_S3_PDCISENS =PP3V3_S3_SMBUS_SMC_MGMT =PP3V3_S3_VREFMRGN =PP3V3_S3_WLAN =PP3V3_S3_AIRPORT_AUX =PP3V3_S3_BT =PP3V3_S3_SMS 52 55 53 42 61 =PPMCPCORE_S0_REG =PPVCORE_S0_MCP_REG_R (MCP VCORE REG OUTPUT) (MCP VCORE AFTER SENSE RES) C 59 =PP0V9_S0_REG PPVCORE_S0_MCP_R =PP3V3_S0_FET PP3V3_S0 44 56 =PP3V3_S0_XDP =PP3V3_S0_MCP =PP3V3_S0_MCP_DAC_UF =PP3V3_S0_MCP_VPLL_UF =PP3V3_S0_ODD =PP3V3_S0_LPCPLUS =PP3V3_S0_SMBUS_SMC_0_S0 =PP3V3_S0_SMBUS_SMC_B_S0 =PP3V3_S0_SMBUS_MCP_0 =PP3V3_S0_FAN_RT =PP3V3_S0_AUDIO MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0.9V MAKE_BASE=TRUE 65 =PP1V05_S0_FET 65 30 PP1V05_S0 MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V MAKE_BASE=TRUE =PP1V05_S0_MCP_PEX_DVDD =PP1V05_S0_MCP_AVDD_UF =PP1V05_S0_MCP_PLL_UF =PP1V05_S0_MCP_SATA_DVDD =PP1V05_S0_MCP_HDMI_VDD =PP1V05_S0_VMON 63 =PP1V5_S0_FET PP1V5_S0_R =PP1V5_S0_CPU =PP1V5_S0_AIRPORT =PP1V8_S0 (DDR PWR AFTER SENSE RES.) 46 PP1V8_S0 MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.2MM VOLTAGE=1.8V MAKE_BASE=TRUE =PP1V8R1V5_S0_MCP_MEM =PP1V8_S0_FET (DDR PWR REG OUTPUT) 65 PP1V8_S0_R MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.2MM VOLTAGE=1.8V MAKE_BASE=TRUE =PP1V8_S0_VMON =PP1V8_S0_FET_R =PP3V3R1V8_S0_MCP_IFP_VDD =PP3V3R1V5_S0_MCP_HDA =PP3V3_S0_SMC =PP3V3_S0_MCPTHMSNS =PP3V3_S0_CPUTHMSNS =PP5VR3V3_S0_MCPCOREISNS =PPSPD_S0_MEM =PP3V3_S0_PWRCTL =PP3V3_S0_VMON =PP3V3_S0_MCPDDRISNS =PP3V3_S0_CPUVTTISNS =PP3V3_FW_P1V0FW =PP3V3_FW_PHY =PP3V3_FW_FWPHY 24 18 25 64 11 12 31 31 44 44 44 48 52 54 55 50 A PP1V05_S0_MCP_SATA_AVDD MAKE_BASE=TRUE =PP1V05_S0_MCP_SATA_DVDD 127 mA (A01) 57 PPBUS_G3H =PP1V05_S0_MCP_PEX_AVDD0 =PP1V05_S0_MCP_PEX_AVDD1 =PP1V05_S0_MCP_PEX_DVDD0 =PP1V05_S0_MCP_PEX_DVDD1 61 61 59 58 58 61 45 66 36 46 C 66 65 46 PPBUS_G3H_CPU_ISNS =PPBUS_G3H_CPU_ISNS MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.3MM VOLTAGE=12.6V MAKE_BASE=TRUE 65 42 =PPVIN_S0_CPUVTTS0 =PPVIN_S5_CPU_IMVP 49 59 62 60 "ENET" RAILS 25 24 33 =PP3V3_ENET_FET PP3V3_ENET_PHY MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V MAKE_BASE=TRUE 21 24 42 =PP3V3_ENET_MCP_RMGT 47 47 59 27 =PPVTT_S3_DDR_BUF PPVTT_S3_DDR_BUF 28 29 =PP3V3_ENET_PHY MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=0.9V MAKE_BASE=TRUE 46 33 =PP1V05_ENET_FET "S5" RAILS 46 =PP1V05_ENET_MCP_PLL_MAC =PP1V05_ENET_MCP_RMGT =PP1V05_ENET_PHY 32 63 37 35 37 =PP1V05_S5_REG 16 24 MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V MAKE_BASE=TRUE 64 46 18 24 32 PP1V2R1V05_ENET 64 PP1V05_S5_REG 24 18 24 B =PP1V05_S5_MCP_VDD_AUXC =PP1V05_ENET_P1V05ENETFET 36 PPVP_FW =PPBUS_S5_FW_FET VOLTAGE=12.6V MAKE_BASE=TRUE 22 24 MIN_NECK_WIDTH=0.2 MM MIN_LINK_WIDTH=0.4 MM =PPVP_FW_PHY_CPS_FET 33 =PPVP_FW_PORT1 37 37 64 46 58 =PP3V3_S5_REG =PP1V0_FW_REG PP1V0_FW =PP1V0_FW_FWPHY PP3V3_S5 MIN_LINE_WIDTH=1.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=3.3V MAKE_BASE=TRUE 18 25 =PP3V3_S5_MCP_GPIO =PP3V3_S5_ROM =PP3V3_S5_LCD =PP3V3_S5_MCP =PP3V3_S5_MCPPWRGD =PP3V3_S5_AIRPORT_AUX =PP3V3_S5_P3V3ENETFET =PP3V3_S5_PWRCTL =PP3V3_S5_P1V05ENETFET =PP3V3_S5_P3V3S3FET =PP3V3_S5_P3V3S0FET =PP3V3_S5_P1V05S5 =PP3V3_FW_LATEVG 35 17 206 mA (A01) 17 17 57 mA (A01) 17 18 20 43 51 66 22 24 26 33 64 33 65 65 Power Aliases 63 36 37 SYNC_MASTER=K36B_MLB A NOTICE OF PROPRIETARY PROPERTY =PP1V05_S0_MCP_SATA_AVDD0 =PP1V05_S0_MCP_SATA_AVDD1 20 =PP1V05_S0_MCP_SATA_DVDD0 =PP1V05_S0_MCP_SATA_DVDD1 20 20 127 mA (A01) THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING 127 mA (A01) 24 =PP18V5_G3H_CHGR 38 40 206 mA (A01) 24 7 39 18 19 21 MAKE_BASE=TRUE =PP1V05_S0_MCP_PEX_DVDD 26 =PPVIN_S0_MCPCORES0 =PPVIN_S0_MCPREG_VIN =PPVIN_S5_1V8S3_0V9S0 =PPVIN_S5_3V3S5 =PPVIN_S0_5VRTS0 =PPVIN_S3_5VLTS3 =PPBUS_G3HRS5 =PPBUS_S5_INV =PPBUS_S5_FWPWRSW =PPBUS_G3H_CPU_ISNS_R MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V MAKE_BASE=TRUE PEX & SATA AVDD/DVDD aliases 24 =PPBUS_G3H 66 MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.2MM VOLTAGE=1.0V MAKE_BASE=TRUE 206 mA (A01) 41 42 50 43 40 =PP5V_S3_EXTUSB =PP5V_S3_IR =PP5V_S3_CAMERA =PP5V_S3_VTTCLAMP =PP5V_S3_MCPDDRFET =PP5V_S3_SYSLED =PP5V_S3_TPAD =PP5V_S3_1V8S3_0V9S0 =PP5V_S3_AUDIO =PP5V_S3_AUDIO_AMP 63 63 PP1V05_S0_MCP_PEX_AVDD 46 PP18V5_G3H 25 68 =PP3V3_S0_MCP_PLL_UF PP5VLT_S3 38 "FW" RAILS 24 56 MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.3 MM VOLTAGE=18.5V MAKE_BASE=TRUE 31 MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=5V MAKE_BASE=TRUE 25 =PP3V3_S0_TMDS 24 =PP5VLT_S3_REG 21 22 24 60 =PP3V3_S0_LCD =PP3V3_S0_MCP_GPIO =PP3V3_S0_HDCPROM 24 61 13 =PP3V3_S0_IMVP 24 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.5V MAKE_BASE=TRUE B =PP18V5_DCIN_CONN 27 MIN_LINE_WIDTH=0.30MM MIN_NECK_WIDTH=0.20MM VOLTAGE=3.3V MAKE_BASE=TRUE =PP0V9_S3M_MEM_TERM D 39 59 45 PPVCORE_S0_MCP =PPVTT_S0_VTTCLAMP 57 MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V MAKE_BASE=TRUE PP0V9_S0 64 44 MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V MAKE_BASE=TRUE 65 63 =PPVCORE_S0_MCP 44 MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.25MM VOLTAGE=12.6V MAKE_BASE=TRUE =PPVCORE_S0_MCP_VSENSE 24 22 61 46 42 =PP3V3_S5_SMC =PP3V3_S5_LPCPLUS =PP3V42_G3H_RTC_D MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V MAKE_BASE=TRUE 68 66 =PPVIN_S5_SMCVREF =PP3V42_G3H_SMBUS_SMC_BSA =PP3V42_G3H_PWRCTL =PP3V42_G3H_CHGR =PP3V42_G3H_SMCUSBMUX =PP3V42_G3H_LIDSWITCH =PP3V42_G3H_BMON_ISNS 57 46 PP3V42_G3H MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM VOLTAGE=3.42V MAKE_BASE=TRUE 38 =PP5V_S0_CPU_IMVP =PPCPUVTT_S0_REG 59 PP1V8_S3 =PP3V42_G3H_REG MIN_LINE_WIDTH=1.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=1.8V MAKE_BASE=TRUE =PP5V_S0_HDD =PP5V_S0_LPCPLUS =PP5V_S0_FAN_RT 11 12 D 65 62 =PP1V8_S3_REG MIN_LINE_WIDTH=0.30 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=5V MAKE_BASE=TRUE MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.3 MM VOLTAGE=0.9V MAKE_BASE=TRUE =PPVCORE_S0_CPU =PPVCORE_S0_CPU_VSENSE PP5VRT_S0 20 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE 43 mA (A01) II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC SCALE SHT NONE REV 051-8089 02 OF 109 LVDS ALIASES PCI-E ALIASES 17 UNUSED GPU LANES =PEG_D2R_N NC_PEG_D2R_N NO_TEST=TRUE =PEG_D2R_P NC_PEG_D2R_P 17 =PEG_R2D_C_N NC_PEG_R2D_C_N NO_TEST=TRUE 71 18 LVDS_IG_A_DATA_N NC_LVDS_IG_A_DATA_N3 LVDS_IG_B_CLK_P NC_LVDS_IG_B_CLKP NO_TEST=TRUE NC_PEG_R2D_C_P 17 PEG_PRSNT_L TP_PEG_PRSNT_L 17 PEG_CLKREQ_L NC_LVDS_IG_B_CLKN 71 18 LVDS_IG_B_DATA_P NC_LVDS_IG_B_DATA_P 71 18 LVDS_IG_B_DATA_N 71 17 PEG_CLK100M_P PCIE_EXCARD_D2R_N 17 PCIE_EXCARD_R2D_C_P PCIE_EXCARD_R2D_C_N PCIE_EXCARD_PRSNT_L 17 EXCARD_CLKREQ_L MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NC_LVDS_IG_B_DATA_N NO_TEST=TRUE MAKE_BASE=TRUE 71 17 71 17 NO_TEST=TRUE TP_PEG_CLKREQ_L PCIE_EXCARD_D2R_P 71 17 LVDS_IG_B_CLK_N MAKE_BASE=TRUE 71 17 MAKE_BASE=TRUE 71 18 MAKE_BASE=TRUE D MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE =PEG_R2D_C_P MAKE_BASE=TRUE 71 18 MAKE_BASE=TRUE 17 NO_TEST=TRUE NO_TEST=TRUE MAKE_BASE=TRUE TP_PEG_CLK100MP 71 17 PCIE_CLK100M_EXCARD_P 71 17 PCIE_CLK100M_EXCARD_N PEG_CLK100M_N EXTGPU_PWR_EN TP_EXTGPU_PWR_EN EXTGPU_RESET_L TP_EXTGPU_RESET_L MAKE_BASE=TRUE 14 CPU_PECI_MCP 19 GMUX_JTAG_TDI TP_GMUX_JTAG_TDI 19 GMUX_JTAG_TMS TP_GMUX_JTAG_TMS ETHERNET ALIASES 33 33 32 MCP_MEM_RESET_L =PP3V3_ENET_PHY_VDDREG =RTL8211_REGOUT 21 72 20 72 20 72 20 UNUSED ADDRESS PINS 28 29 MEM_A_A MEM_B_A 72 20 TP_MEM_A_A15 TP_MEM_B_A15 MAKE_BASE=TRUE 266 133 200 (166) 333 100 (400) (RSVD) HDA PULL-DOWN AUD_IPHS_SWITCH_EN 19 R0977 20K TP_USB_EXTCP TP_USB_EXTCN TP_USB_EXTDP TP_USB_EXTDN TP_USB_EXCARDP TP_USB_EXCARDN 31 =USB_MINI_P USB_MINI_P 31 =USB_MINI_N USB_MINI_N 5% 1/16W MF-LF MAKE_BASE=TRUE 402 MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE LAN ALIASES MAKE_BASE=TRUE MAKE_BASE=TRUE MCP_MII_RXER MCP_MII_COL MCP_MII_CRS 18 20 72 MAKE_BASE=TRUE 18 20 72 MAKE_BASE=TRUE 18 R0930 47K R0932 47K 5% 49 =USB2_TPAD_P USB_TPAD_P 49 =USB2_TPAD_N USB_TPAD_N 1/16W MF-LF 402 5% 1/16W MF-LF 402 1/16W MF-LF 402 TRACKPAD(WELLSPRING) 5% R0931 47K =RTL8211_ENSWREG 20 72 MAKE_BASE=TRUE 20 72 MAKE_BASE=TRUE DP HOTPLUG PULL-DOWN BLUETOOTH C FSB MHZ 1 1 D MAKE_BASE=TRUE MAKE_BASE=TRUE 32 TP_MCP_MEM_RESET_L SO-DIMM ALIASES PP3V3_ENET_PHY_VDDREG MAKE_BASE=TRUE NC_RTL8211_REGOUT 32 72 20 MAKE_BASE=TRUE MAKE_BASE=TRUE 14 OUT 0 1 0 1 MAKE_BASE=TRUE USB_EXTC_P USB_EXTC_N USB_EXTD_P USB_EXTD_N USB_EXCARD_P USB_EXCARD_N 72 20 MAKE_BASE=TRUE 16 =MCP_BSEL UNUSED USB PORTS MAKE_BASE=TRUE PM_SLP_RMGT_L CPU_BSEL MAKE_BASE=TRUE 0 0 1 1 TP_PCIE_CLK100M_EXCARDP MAKE_BASE=TRUE TP_PCIE_CLK100M_EXCARDN USB ALIASES TP_CPU_PECI_MCP MAKE_BASE=TRUE MAKE_BASE=TRUE =P3V3ENET_EN =P1V05ENET_EN IN MISC NC MCP79 ALIASES MAKE_BASE=TRUE 17 69 10 MAKE_BASE=TRUE TP_PEG_CLK100MN 17 BSEL TP_PCIE_EXCARD_D2RP MAKE_BASE=TRUE TP_PCIE_EXCARD_D2RN MAKE_BASE=TRUE TP_PCIE_EXCARD_R2D_CP MAKE_BASE=TRUE TP_PCIE_EXCARD_R2D_CN MAKE_BASE=TRUE TP_PCIE_EXCARD_PRSNT_L MAKE_BASE=TRUE TP_EXCARD_CLKREQ_L MAKE_BASE=TRUE 71 17 CPU FSB FREQUENCY STRAPS UNUSED EXPRESS CARD LANE UNUSED LVDS SIGNALS LVDS_IG_A_DATA_P NC_LVDS_IG_A_DATA_P3 MAKE_BASE=TRUE 17 NO_TEST=TRUE 71 18 40 =USB2_BT_P USB_BT_P 40 =USB2_BT_N USB_BT_N DP_HOTPLUG_DET 18 C 20 72 MAKE_BASE=TRUE R0940 20K 20 72 MAKE_BASE=TRUE 5% 1/16W MF-LF 402 FW PULL-DOWN CPU HEATSINK STANDOFF SCREW HOLE Screw Holes OMIT OMIT Z0903 17 Z0904 STDOFF-4.2OD3.95H-5.52R3.37-6B PCIE_FW_PRSNT_L STDOFF-4.2OD3.95H-5.52R3.37-7SQB 1 R0955 BATTERY,AUDIO,DIP DIMM CONNECTOR CHASSIS GND Z0906 OMIT 5R2P3-7SQBNP 56 SATA,LVDS CONNECTOR CHASSIS GND =GND_CHASSIS_AUDIO_JACK 28 =GND_CHASSIS_DIPDIMM_LEFT 55 =GND_CHASSIS_AUDIO_MIC 66 =GND_CHASSIS_LVDS 28 =GND_CHASSIS_DIPDIMM_CENTER 29 =GND_CHASSIS_DIPDIMM_RIGHT 34 =GND_CHASSIS_RJ45 68 =GND_CHASSIS_TMDS_UPPER 37 =GND_CHASSIS_FW_UPPER 68 =GND_CHASSIS_TMDS_DOWN 37 =GND_CHASSIS_FW_DOWN OMIT 6P5R2P6-7SQB 29 DIP DIMM CONNECTOR CHASSIS GND OMIT Z0910 5R2P3-7SQB OMIT OMIT =GND_BATT_CHGND 54 Z0907 B 5% 1/16W MF-LF 402 Z0903 USE SAME Z0913 NON SHAPE OF A HOOF SYMBOL FOR LAYOUT PLACEMENT BUT, NEED CHANGE TO HIGH STANDOFF SYMBOL STDOFF-4.5OD3.95H-1.1-3.2-TH STDOFF-4.5OD3.95H-1.1-3.2-TH R0920 1 MCP_SPKR 21 SMC_MCP_SAFE_MODE IN 41 5% 1/16W MF-LF 402 MCP_TV_DAC_RSET MCP_TV_DAC_VREF R09411 124 OMIT 5R2P3-7SQBNP 1% 1/16W MF-LF 402 OMIT Z0901 MCP_SAFE_MODE SIGNAL TO SUPPORT ROM FAILURE OVERRIDE Z0921 Z0905 Z0912 18 71 B C0940 0.01UF 10% 16V CERM 402 STDOFF-4.2OD2.15H-1.2-3.2-TH DIP DIMM CONNECTOR CHASSIS GND 18 71 OMIT Z0909 5R2P3-7SQB 55 54 53 52 DCIN CONNECTOR CHASSIS GND OMIT Z0911 5R2P3-7B OMIT Z0902 7X7R2P3-5B GND_AUDIO_CODEC MAKE_BASE=TRUE XW0901 SM Z0913 STDOFF-4.2OD3.95H-5.52R3.37-6B 1 =GND_AUDIO_CODEC OMIT 53 =GND_AUDIO_AMP GND_AUDIO_AMP MAKE_BASE=TRUE XW0902 SM I/O CONNECTOR CHASSIS GND OMIT Z0908 5P0R2P3-7BLB SIGNAL ALIAS (EMI PAD FOR INVERTER GONNECTOR) A SYNC_MASTER=K36B_MLB QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION 66 INVT_CHGND TABLE_5_ITEM 860-0964 THERMAL STANDOFF Z0903,Z0904,Z0905,Z0921 ? STANDOFF 860-0723 STANDOFF WIRELESS Z0912 ? STANDOFF 860-0749 STANDOFF W/THRU HOLES,WIRELESS Z0913 ? STANDOFF A NOTICE OF PROPRIETARY PROPERTY TABLE_5_HEAD PART# ZS0920 EMI-SPRING THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING CLIP-SM-M42 TABLE_5_ITEM I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT TABLE_5_ITEM III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC SCALE SHT NONE REV 051-8089 02 OF 109 OMIT 69 14 BI 69 14 BI 69 14 BI 69 14 BI 69 14 BI 69 14 BI 69 14 BI 69 14 BI 69 14 BI 69 14 BI 69 14 BI 69 14 BI 69 14 BI 69 14 BI 69 14 BI 69 14 BI 69 14 BI 69 14 BI 69 14 69 14 BI BI 69 14 BI 69 14 BI 69 14 C BI 69 14 BI 69 14 BI 69 14 BI 69 14 BI 69 14 BI 69 14 BI 69 14 BI 69 14 BI 69 14 BI 69 14 BI 69 14 69 14 69 14 K3 FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_ADSTB_L Y2 IN CPU_A20M_L OUT CPU_FERR_L IN CPU_IGNNE_L 69 14 IN 69 14 IN 69 14 IN 69 14 FSB_REQ_L FSB_REQ_L FSB_REQ_L FSB_REQ_L FSB_REQ_L IN CPU_STPCLK_L CPU_INTR CPU_NMI CPU_SMI_L TP_CPU_RSVD_M4 TP_CPU_RSVD_N5 TP_CPU_RSVD_T2 TP_CPU_RSVD_V3 TP_CPU_RSVD_B2 TP_CPU_RSVD_F6 TP_CPU_RSVD_D2 TP_CPU_RSVD_D22 TP_CPU_RSVD_D3 N2 J1 N3 P5 P2 L2 P4 P1 R1 M1 H2 K2 J3 L1 U5 R3 W6 U4 Y5 U1 R4 T5 T3 W2 W5 Y4 U2 V4 W3 AA4 AB2 AA3 V1 A6 A5 C4 D5 C6 B4 A3 M4 N5 T2 V3 B2 F6 D2 D22 D3 DEFER* DRDY* DBSY* BR0* REQ0* REQ1* REQ2* REQ3* REQ4* A17* A18* A19* A20* A21* A22* A23* A24* A25* A26* A27* A28* A29* A30* A31* A32* A33* A34* A35* ADSTB1* FSB_DEFER_L FSB_DRDY_L FSB_DBSY_L H5 F21 E1 FSB_BREQ0_L F1 BI 14 69 BI 14 69 BI 14 69 BI 14 69 BI 14 69 BI 14 69 BI IN LOCK* H4 FSB_LOCK_L BI RESET* RS0* RS1* RS2* TRDY* C1 FSB_CPURST_L FSB_RS_L FSB_RS_L FSB_RS_L FSB_TRDY_L D20 F3 F4 G3 G2 HIT* HITM* G6 BPM0* BPM1* BPM2* BPM3* PRDY* PREQ* TCK TDI TDO TMS TRST* DBR* AD4 E4 AD3 AD1 AC4 AC2 AC1 AC5 AA6 AB3 AB5 AB6 C20 69 R1000 11 12 13 54.9 1% 1/16W MF-LF 402 14 69 D B3 CPU_IERR_L CPU_INIT_L IERR* INIT* =PP1V05_S0_CPU FSB_HIT_L FSB_HITM_L XDP_BPM_L XDP_BPM_L XDP_BPM_L XDP_BPM_L XDP_BPM_L XDP_BPM_L XDP_TCK XDP_TDI XDP_TDO XDP_TMS XDP_TRST_L XDP_DBRESET_L 14 69 14 69 IN 13 14 69 IN 14 69 IN 14 69 IN 14 69 IN 14 69 BI 14 69 BI 14 69 BI 13 69 OMIT BI 13 69 BI 13 69 BI 13 69 BI R1001 1% 1/16W MF-LF 402 13 69 THERMTRIP* RSVD0 RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 RSVD6 RSVD7 RSVD8 BI BI BI 10 69 69 14 IN 10 13 69 69 14 BI IN 10 13 69 69 14 BI 69 14 BI OUT 13 26 R1002 B25 OUT 47 C7 PM_THRMTRIP_L OUT 14 42 69 69 14 OUT 14 42 60 69 IN IN 14 69 BI BI 69 14 BI 69 14 BI 69 14 BI 69 14 BI 69 14 BI 69 14 BI 69 14 BI 69 14 BI 69 14 BI 1K CPU JTAG Support B R1090 XDP_TMS BI 69 14 BI 69 13 10 69 10 XDP_TDI BI 69 14 BI 69 14 BI XDP_TDO R1092 54.9 PLACEMENT_NOTE=Place R1092 near ITP connector (if present) 1% 1/16W MF-LF 402 C1014 R1094 XDP_TRST_L 649 BI 69 14 BI 69 14 BI 54.9 1% 1/16W MF-LF 402 10% 16V X5R 402 R1010 5% 1/16W MF-LF 402 R1011 1K NO STUFF 69 69 69 FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_DSTB_L_N FSB_DSTB_L_P FSB_DINV_L E22 FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_DSTB_L_N FSB_DSTB_L_P FSB_DINV_L N22 CPU_GTLREF CPU_TEST1 CPU_TEST2 TP_CPU_TEST3 CPU_TEST4 TP_CPU_TEST5 TP_CPU_TEST6 TP_CPU_TEST7 OUT CPU_BSEL OUT CPU_BSEL OUT CPU_BSEL F24 E26 G22 F23 G25 E25 E23 K24 G24 J24 J23 H22 F26 K22 H23 J26 H26 H25 K25 P26 R23 L23 M24 L22 M23 P25 P23 P22 T24 R24 L25 T25 N25 L26 M26 N24 AD26 C23 D25 C24 AF26 AF1 A26 C3 B22 B23 C21 D0* D1* D2* D3* D4* D5* D6* D7* D8* D9* D10* D11* D12* D13* D14* D15* DSTBN0* DSTBP0* DINV0* D16* D17* D18* D19* D20* D21* D22* D23* D24* D25* D26* D27* D28* D29* D30* D31* DSTBN1* DSTBP1* DINV1* GTLREF TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 TEST7 BSEL0 BSEL1 BSEL2 U1000 PENRYN FCBGA OF D32* D33* D34* D35* D36* D37* D38* D39* D40* D41* D42* D43* D44* D45* D46* D47* DSTBN2* DSTBP2* DINV2* Y22 D48* D49* D50* D51* D52* D53* D54* D55* D56* D57* D58* D59* D60* D61* D62* D63* DSTBN3* DSTBP3* DINV3* AE24 COMP0 COMP1 COMP2 COMP3 MISC DPRSTP* DPSLP* DPWR* PWRGOOD SLP* PSI* FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_DSTB_L_N FSB_DSTB_L_P FSB_DINV_L AB24 V24 V26 V23 T22 U25 U23 Y25 W22 Y23 W24 W25 AA23 AA24 AB25 Y26 AA26 U22 FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_DSTB_L_N FSB_DSTB_L_P FSB_DINV_L AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21 AC22 AD23 AF22 AC23 AE25 AF24 AC20 R26 69 U26 69 AA1 69 Y1 69 E5 B5 D24 D6 D7 AE6 BI 14 69 BI 14 69 BI 14 69 BI 14 69 BI 14 69 BI 14 69 BI 14 69 BI 14 69 BI 14 69 BI 14 69 BI 14 69 BI 14 69 BI 14 69 BI 14 69 BI 14 69 BI 14 69 BI 14 69 BI 14 69 BI 14 69 BI 14 69 BI 14 69 BI 14 69 BI 14 69 BI 14 69 BI 14 69 BI 14 69 BI 14 69 BI 14 69 BI 14 69 BI 14 69 BI 14 69 BI 14 69 BI 14 69 BI 14 69 BI 14 69 BI 14 69 BI 14 69 BI 14 69 C B CPU_COMP CPU_COMP CPU_COMP CPU_COMP CPU_DPRSTP_L CPU_DPSLP_L FSB_DPWR_L CPU_PWRGD FSB_CPUSLP_L CPU_PSI_L IN 14 60 69 IN 14 69 IN 14 69 IN 13 14 69 IN 14 69 OUT R1023 R1021 54.9 1% 1/16W MF-LF 402 54.9 1% 1/16W MF-LF 402 60 5% 1/16W MF-LF 402 R1022 R1020 27.4 R1012 1K 5% 1/16W MF-LF 402 0.1uF NO STUFF 1% 1/16W MF-LF 402 NO STUFF 69 13 10 69 14 NO STUFF R1093 XDP_TCK BI R1006 69 13 10 BI 69 14 2.0K BI 69 14 69 27 1% 1/16W MF-LF 402 1% 1/16W MF-LF 402 BI 69 14 1% 1/16W MF-LF 402 R1091 54.9 54.9 R1005 BI 69 14 69 14 BI 69 14 69 14 14 69 BI 69 14 69 14 69 13 10 BI 69 14 OUT FSB_CLK_CPU_P FSB_CLK_CPU_N 69 14 10 13 69 47 A21 BI IN OUT A22 BI 69 14 IN H CLK BCLK0 BCLK1 BI 69 14 69 14 CPU_PROCHOT_L CPU_THERMD_P CPU_THERMD_N A24 BI 69 14 13 69 BI 5% 1/16W MF-LF 402 D21 BI 69 14 10 13 69 THERMAL PROCHOT* THERMDA THERMDC 69 14 69 14 54.9 68 A20M* FERR* IGNNE* STPCLK* LINT0 LINT1 SMI* G5 DATA GRP BI OF FSB_ADS_L FSB_BNR_L FSB_BPRI_L H1 E2 DATA GRP BI 69 14 FCBGA DATA GRP 69 14 M3 ADS* BNR* BPRI* PENRYN DATA GRP BI K5 U1000 CONTROL 69 14 L4 A3* A4* A5* A6* A7* A8* A9* A10* A11* A12* A13* A14* A15* A16* ADSTB0* XDP/ITP SIGNALS BI L5 ADDR GROUP0 BI 69 14 J4 ADDR GROUP1 D BI 69 14 FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_ADSTB_L ICH 69 14 BI RESERVED 69 14 PLACEMENT_NOTE=Place C1014 within 12.7mm of CPU PLACEMENT_NOTE=Place R1005 within 12.7mm of CPU PLACEMENT_NOTE=Place R1006 within 12.7mm of CPU 2 27.4 1% 1/16W MF-LF 402 1% 1/16W MF-LF 402 PLACEMENT_NOTE (all resistors): 1% 1/16W MF-LF 402 Place within 12.7mm of CPU CPU FSB A SYNC_MASTER=K36B_MLB SYNC_DATE=08/18/2008 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING SYNC FROM T18 CHANGE CPU FROM SOCKET TO BGA SYMBOL I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC SCALE SHT NONE REV 051-8089 02 OF 10 109 A CPUVTT POWER SUPPLY D D =PPVIN_S0_CPUVTTS0 CRITICAL C7630 1 20% 16V POLY-TANT CASED2E-SM C7695 1UF 33UF 2 10% 25V X5R 603-1 C7696 0.001UF 20% 50V CERM 402 C D CRITICAL C Q7620 SI7110DN G PWRPK-1212-8-HF S =PP5V_S0_CPUVTTS0 L7620 R7601 PP5V_S0_CPUVTTS0_V5FILT MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5V R7603 C7601 1UF 10% 10V X5R 402-1 10 1% 1/16W MF-LF 402 301 V5FILT 187K C7604 1% 1/16W MF-LF 402 4.7UF V5DRV CRITICAL 10% 6.3V X5R-CERM 603 64 IN =CPUVTTS0_EN 64 OUT CPUVTTS0_PGOOD PGOOD (=PPCPUVTT_S0_REG) VOUT VFB VBST CPUVTTS0_TON 14 CPUVTTS0_VBST DRVH 13 LL 12 CPUVTTS0_DRVH GATE_NODE=TRUE CPUVTTS0_VFB CPUVTTS0_LL SWITCH_NODE=TRUE CPUVTTS0_TRIP 11 TRIP DRVL CPUVTTS0_DRVL GATE_NODE=TRUE THRM_PAD 10% 50V X7R 603-1 2.2 5% 1/16W MF-LF SI7108DN G PWRPK-1212-8-HF XW7665 402 CPUVTTS0_LL_SNUBBER 1 2 EMI request NO STUFF C7690 100PF 5% 50V CERM MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM 402 MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM CPUVTTS0_VSNS MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM NO STUFF R7670 C7670 8.45K R7604 XW7600 5% 50V CERM 402 SM 1 100PF 1% 1/16W MF-LF 402 6.65K 1% 1/16W MF-LF 402 SM S 0.1UF MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM R7690 CRITICAL Q7621 B PGND D 15 GND C7603 SM-IHLP-1 U7600 TPS51117RGY_QFN14 SYM QFN (2 OF 2) EN_PSV TON EMI request NO STUFF (GND) ROUTING NOTE: R7671 1% 1/16W MF-LF 402 20% 6.3V X5R 603 CRITICAL C7660 C7661 0.001UF 20% 50V CERM 402 330UF 20% 2.5V POLY-TANT CASE-C2-SM B XW7601 ROUTING NOTE: GND_CPUVTTS0_SGND C7665 10UF 20.0K Place XW7600 between Pin and Pin 15 of U7600 65 Vout = 1.052V 8A max output F = 400 KHZ SM PLACEMENT_NOTE=Place XW7665 next to L7620 =PPCPUVTT_S0_REG 1.0UH-13A-5.6M-OHM CRITICAL Place XW7601 by C7660 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0V Vout = 0.75V * (1 + Ra / Rb) (CPUVTTS0_VFB) CPUVTT_VOUT (=PPCPUVTT_S0_REG) CPU VTT(1.05V) SUPPLY SYNC_MASTER=K36B_MLB A SYNC_DATE=08/17/2008 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC SCALE SHT NONE REV 051-8089 02 OF 76 109 A FireWire 1.0V (Core) Supply CRITICAL L7710 4.7UH-0.8A P1V0FW_SW D CRITICAL MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm SWITCH_NODE=TRUE U7780 C7712 =PP3V3_FW_P1V0FW 52.3K 22pF 5% 50V CERM 402 SC70 VIN SW RUN VFB R7713 4.7UF 20% 6.3V X5R-CERM 402 200K 2 C7715 4.7UF 1 f = 2.25 MHz P1V0FW_VFB GND C7710 (Switcher limit) 1% 1/16W MF-LF 402 D Vout = 1.001V 300mA max output LTC3410ESC6 =PP1V0_FW_REG R7712 PCAA031B-SM 1% 1/16W MF-LF 402 20% 6.3V X5R-CERM 402 Vout = 0.8V * (1 + Ra / Rb) C C MCP 1.05V_S5 AUXC SUPPLY 1.5V S0 SWITCH =PP3V3_S5_P1V05S5 CRITICAL CRITICAL C7781 CRITICAL SW OVT U7750 FB TPS62510 PG BQA 1V05S5_SW 1V05S5_FB =PP1V05_S5_REG C7782 402 P1V05_S5_PGOOD OUT 64 =P1V5S0_EN C7783 FREQ = 1MHZ C7741 22UF R7781 392K 20% 6.3V CERM 805 0.1UF 10% MF-LF 402 1V05S5_SGND VOUT = 0.6V * (1 + Ra / Rb) CRITICAL L7740 2.2UH-3.25A EN IHLP1616BZ-SM OVT CRITICAL SW 1V5S0_SW U7740 FB 1V5S0_FB TPS62510 MODE PG BQA C7742 R7740 22PF 301K 16V X5R 402 5% 50V CERM 402 1% 1/16W MF-LF 402 R7741 200K P1V5_S0_PGOOD OUT 64 MODE_GND XW7700 SM =PP1V5_S0_FET 1 AGND PGND THRM_PAD 1% 1/16W 64 MAX Current = 1.5A CRITICAL 1% 1/16W MF-LF 402 11 2 16V X5R 402 0.1UF 10% Vout = 1.05V 301K 5% 50V CERM R7780 22PF 20% 6.3V CERM 805 AVINPVIN C7740 22UF 1V5S0_AVIN AGND PGND THRM_PAD IHLP1616BZ-SM EN MODE L7720 10 2.2UH-3.25A AVINPVIN =P1V05_S5_EN 64 R7742 5% 1/16W MF-LF 402 6.3V CERM 805 10 5% 1/16W MF-LF 402 1V05S5_AVIN B =PP3V3_S0_FET 22UF 20% 65 C7720 11 1 R7722 VOUT = 0.6V * (1 + Ra / Rb) VOUT = 1.5V MAX CURRENT = 1.5A C7743 22UF B FREQ = 1MHZ 20% 6.3V CERM 805 1% 1/16W MF-LF 402 XW7740 SM MISC POWER SUPPLIES SYNC_MASTER=K36B_MLB A SYNC_DATE=08/17/2008 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC SCALE SHT NONE REV 051-8089 02 OF 77 109 A 3.3V 1.05V S5 ENABLE Power Control Signals R7802 64 100K =PP3V42_G3H_PWRCTL PM_G2_P3V3S5_EN_L =P3V3S5_EN_L OUT 58 MAKE_BASE=TRUE 5% 1/16W MF-LF 402 0.068UF Q7800 D SSM3K15FV D 10% 10V R7813 SMC_PM_G2_EN IN D CERM 402 SOD-VESM-HF 41 5VLT_S0, 3.3V_S0, 1.8V_S0 ENABLE MCPDDR, CPUVTT,MCPCORES0 ENABLE 1.5V S0 AND 1.05V S0 ENABLE NO STUFF C7802 64 =PP3V42_G3H_PWRCTL 68K PM_SLP_S3_L_INVERT =P5VRTS0_EN_L OUT MAKE_BASE=TRUE 5% R7800 100K 5% 1/16W MF-LF 402 G 1/16W MF-LF 402 S SSM3K15FV SOD-VESM-HF NO STUFF R7801 2 5.1K PM_G2_P1V05S5_EN OUT 63 1 G S (PM_SLP_S3_L) C7801 0.47UF C7813 0.068UF =P1V05_S5_EN MAKE_BASE=TRUE 5% 1/16W MF-LF 402 58 Q7813 D 41 36 33 21 10% 6.3V CERM-X5R 402 IN 10% 10V CERM 402 PM_SLP_S3_L R7879 NO STUFF C7858 64 =PP3V3_S5_PWRCTL 0.1UF 100K 5% 1/16W MF-LF 402 PM_SLP_S3_L_BUF =P3V3S0_EN =PBUSVSENS_EN 20% 10V CERM 402 OUT MAKE_BASE=TRUE 65 OUT 45 NO STUFF TC7SZ08AFEAPE SOT665 A U7859 Y (PM_SLP_S3_L) B (PM_SLP_S3_L_BUF) R78811 R7880 22K 5% S3 ENABLE 1/16W MF-LF 402 R78821 R78831 33K 5.1K 5% 1/16W MF-LF 402 5% 1/16W MF-LF 402 5% 1/16W MF-LF 402 2 P1V8S0_EN C 42 41 21 IN (PM_S4_STATE_L) PM_SLP_S4_L OUT MCPDDR_EN CPUVTTS0_EN R7859 5% 1/16W MF-LF 402 10% 6.3V CERM-X5R 402 2 DDRREG_EN =DDRREG_EN OUT MAKE_BASE=TRUE NO STUFF C7812 R7812 =USB_PWR_EN OUT 100 65 =CPUVTTS0_EN OUT 62 =MCPCORES0_EN OUT 61 MAKE_BASE=TRUE MCPCORES0_EN MAKE_BASE=TRUE 5% 1/16W MF-LF 402 59 C NO STUFF 39 0.47UF 63 OUT MAKE_BASE=TRUE 0.47UF 5.1K 100K 5% 1/16W MF-LF 402 R7811 OUT =MCPDDR_EN 65 C7810 R7810 =P1V5S0_EN MAKE_BASE=TRUE =P3V3S3_EN MAKE_BASE=TRUE C7880 1 0.47UF 10% 6.3V 10% 6.3V 10% 6.3V CERM-X5R CERM-X5R 402 C7882 0.47UF 402 C7881 0.47UF C7883 0.47UF 10% 6.3V CERM-X5R CERM-X5R 402 402 5% 1/16W MF-LF 402 10% 6.3V CERM-X5R 402 P5VLTS3_EN =P5VLTS3_EN MAKE_BASE=TRUE OUT 61 64 =PP3V42_G3H_PWRCTL OTHER S0 RAILS PGOOD C7840 1 0.1uF B 20% 10V CERM 402 =PP3V3_S5_PWRCTL 64 100K R7820 63 0.1uF 20% 10V CERM 402 58 IN IN U7840 RSMRST_PWRGD 41 P1V05_S5_PGOOD 63 TPS3808G33DBVRG4 CT CT SOT23-6 MR* TPS3808 MR* HAS INTERNAL PULLUP GND C7841 P1V5_S0_PGOOD NEED TO CHANGE SIMBOL 0.001UF 20% 50V CERM 402 P5V3V3_PGOOD VCC RESET* 5% 1/16W MF-LF 402 5% 1/16W MF-LF 402 =PP3V3_S0_VMON C7870 SENSE 10K LAYOUT_NOTE: ADD XW IF NEEDS TO SAVE SPACE FOR PIN2,10,1,9 VDD 5.0V (RIGHT AND LEFT), 3.3V AND 1.5V S0 RAILS MONITOR CIRCUIT B R7840 =PP3V3_S0_PWRCTL 61 IN MCPCORES0_PGOOD 62 IN CPUVTTS0_PGOOD U7870 LTC2909 =PP1V8_S0_VMON NC =PP1V05_S0_VMON SEL ADJ1 ADJ2 REF DFN RST* TIE TMR TO GND TRST = 200MS 61 IN P5V_LT_S3_PGOOD ALL_SYS_PWRGD OUT 26 41 MAKE_BASE=TRUE GND A TMR S0PGOOD_PWROK (S0PGOOD_PWROK) POWER SEQUENCING THRM_PAD SYNC_MASTER=K36B_MLB SYNC_DATE=08/17/2008 Unused PGOOD signal NOTICE OF PROPRIETARY PROPERTY LTC2901 THRESHOLD IS 95% (4.75V, 3.136V) 1.5V 1.05V COMPARED TO 0.5V TP_ENETLV_PGOOD THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING ENETLV_PGOOD MAKE_BASE=TRUE I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC SCALE SHT NONE REV 051-8089 02 OF 78 109 A 3.3V S3 FET 1.8V S0 FET CRITICAL Q7910 (1.8V S0 FET FOR DDR2 MEM) FDC638P_G SM 3.3V S3 FET =PP3V3_S3_FET =PP1V8_S3_P1V8S0FET 8 21 1.8V S0 FET D =PP3V3_S5_P3V3S3FET R7912 MOSFET FDC638P CHANNEL P-TYPE C7911 10K RDS(ON) 0.033UF 5% X5R 402 C7910 20% 10V CERM 402 0.182 A (EDP) P3V3S3_SS =PP5V_S3_MCPDDRFET 10% SSM3K15FV MF-LF 16V 402 CERM R7903 402 D 10K 5% 1/16W MF-LF 402 64 IN N-TYPE D CRITICAL RDS(ON) 15 MOHM @4.5V VGS LOADING 5A (EDP) FDM6296G G CKT FROM T18 S D SSM6N15FEAPE =PP1V8_S0_FET SOT563 S MCPDDR_EN_L 47K G S 1 D 5% 1/16W MF-LF 402 C7903 0.068UF 2 =P3V3S3_EN Q7971 FDM6296G CHANNEL MICROFET3X3 Q7971 R7971 G MCPDDR_SS 100K SOD-VESM-HF D Q7901 1% 1/16W MF-LF 402 5% 1/16W Q7903 R7901 0.01UF 47K P3V3S3_EN_L 48 mOhm @4.5V LOADING 402 R7910 0.1UF 10% 16V 1/16W MF-LF C7902 MOSFET 10% 10V CERM 402 MCPDDR_EN_L_RC SSM6N15FEAPE SOT563 3.3V S0 FET 64 IN G S =MCPDDR_EN CRITICAL Q7930 C C FDC606P_G 100K C7931 5% MF-LF 402 D FDC606P CHANNEL P-TYPE 10% 16V R7930 P3V3S0_EN_L X5R 47K 26 MOHM @4.5V 1.431 A (EDP) 0.01UF P3V3S0_SS LOADING C7930 402 RDS(ON) 0.033UF 1/16W 3.3V S0 FET 63 MOSFET G R7932 S =PP3V3_S5_P3V3S0FET =PP3V3_S0_FET SOT-6 5% 10% 1/16W Q7905 SSM3K15FV 16V MF-LF CERM 402 402 D SOD-VESM-HF MCP79 DDRVTT FET 64 IN G S =P3V3S0_EN MCP79 DDR PAD LEAKAGE IS HIGH ENOUGH THAT NVIDIA RECOMMENDS UNPOWERING DURING SLEEP IN ORDER TO SUPPORT UNPOWERING RAIL, HARDWARE MUST GUARANTEE MEM_CKE SIGNALS ARE LOW BEFORE RAIL IS TURNED OFF, AND REMAINS LOW UNTIL AFTER RAIL TURNS BACK ON OR DIMMS WILL EXIT SELF-REFRESH PREMATURELY MEM_VTT_EN OUTPUT FROM MCP79 USED TO ENABLE CLAMP ON VTT RAIL, WHICH PULLS ALL CKE SIGNALS LOW THROUGH VTT TERMINATION RESISTORS B B R7975 =PPVTT_S0_VTTCLAMP R79551 VTTCLAMP_L 90mA max load @ 0.9V 81mW max power CKT FROM T18 =PP5V_S3_VTTCLAMP Q7975 5% 1/8W MF-LF 805 62 10 5% 1/10W MF-LF 603 =PP1V05_S0_FET S SOT563 100K 5% 1/16W MF-LF 402 SSM6N15FEAPE R7976 =PPCPUVTT_S0_REG D 2 G VTTCLAMP_EN Q7975 D NO STUFF C7976 SSM6N15FEAPE 20% 50V CERM 402 A 59 26 IN G 0.001UF SOT563 S POWER FETS SYNC_MASTER=K36B_MLB SYNC_DATE=08/17/2008 NOTICE OF PROPRIETARY PROPERTY =DDRVTT_EN THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC SCALE SHT NONE REV 051-8089 02 OF 79 109 A 8 =PP5V_S0_LCD PP5V_INV MIN_LINE_WIDTH=0.30 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=5V R9000 100K 1% 1/16W MF-LF 402 INV_PWREN_F_L D R9001 100K Q9006 SSM3K15FV D PPBUS_ALL_INV_CONN VOLTAGE=12.6V MIN_LINE_WIDTH=0.30 MM MIN_NECK_WIDTH=0.20 MM 0402-LF NTK3142PXXH D INV_PWREN_L Q9005 SOT723-3-HF G S CRITICAL J9000 5% 1/16W MF-LF 402 78171-0004 M-RT-SM L9000 G 66 18 IN S 120-OHM-0.3A-EMI C9014 0.0022UF LVDS_IG_BKL_ON PP5V_INV_F VOLTAGE=5V MIN_LINE_WIDTH=0.30 MM MIN_NECK_WIDTH=0.20 MM 0402-LF 10% 50V CERM 402 7 INV_BKLIGHT_PWM_L INV_GND L9001 120-OHM-0.3A-EMI 66 =PP3V3_S0_LCD 518S0521 0402-LF C9001 CRITICAL 100PF 26 BKLT_PLT_RST_L TC7SZ08AFEAPE LVDS_IG_BKL_PWM 66 18 SOT665 A U9053Y C9002 C9003 5% 5% 1/16W MF-LF 402 50V CERM 402 BKLIGHT_CTL C9000 100PF 5% 50V CERM 100PF 5% 50V CERM 402 1 402 B C90591 0.1UF INVT_CHGND 10% 16V X5R 402 C D INVERTER CONNECTOR L9002 1% 1/16W MF-LF 402 SOD-VESM-HF L9003 FERR-120-OHM-1.5A =PPBUS_S5_INV THIS GND CONECTS TO CHASSIS GND C CRITICAL Q9003 =PP3V3_S5_LCD PP3V3_LCDVDD_SW VOLTAGE=3.3V MIN_NECK_WIDTH=0.20 MM MIN_LINE_WIDTH=0.30 MM G R9002 D S FDC606P_G SOT-6 100K 5% 1/16W MF-LF 402 LCDVDD_PWREN_L D 10K 5% 1/16W MF-LF 402 C9011 0.1UF R9023 Q9004 SSM3K15FV LCD + CAMERA CONNECTOR C9012 10UF 20% 6.3V X5R 603 10% 16V X5R 402 LCDVDD_PWREN_L_R CRITICAL J9001 S-050162B F-RT-SM SOD-VESM-HF 25 C9013 0.0033UF 1 G 66 18 IN S 66 L9004 FERR-120-OHM-1.5A 10% 50V CERM 402 LVDS_IG_PANEL_PWR 66 =PP3V3_S0_LCD PP3V3_LCDVDD_SW_F VOLTAGE=3.3VMIN_LINE_WIDTH=0.30 MIN_NECK_WIDTH=0.20 MM MM 0402-LF PP3V3_S0_LCD_F (LVDS DDC POWER) VOLTAGE=3.3V MIN_LINE_WIDTH=0.25 MIN_NECK_WIDTH=0.20 MM MM L9008 120-OHM-0.3A-EMI B IT IS CO-LAY FUNCTION 0402-LF 66 18 66 18 66 71 18 CRITICAL LVDS_IG_DDC_CLK LVDS_IG_DDC_DATA 71 18 L9006 90-OHM-200MA 71 18 AMC2012-SM =PP3V3_S0_LCD 71 18 SYM_VER-1 71 18 LVDS_IG_A_CLK_N 71 18 71 18 1 R9015 R9016 2.7K 5% 1/16W MF-LF 402 CRITICAL L9007 2.7K 5% 71 18 LVDS_IG_A_CLK_P 66 18 1/16W MF-LF 2402 USB_CAMERA_P 72 20 USB_CAMERA_N 72 20 LVDS_IG_DDC_CLK L9005 FERR-120-OHM-1.5A LVDS_IG_DDC_DATA =PP5V_S3_CAMERA 1 72 66 18 66 18 AMC2012-SM 66 18 LVDS_IG_BKL_PWM LVDS_IG_BKL_ON LVDS_IG_PANEL_PWR 1K 5% 1/16W MF-LF 402 C9016 0.001UF 10% 50V CERM 402 R90191 R90181 1K 5% 1/16W MF-LF 402 USB2_CAMERA_CONN_P USB2_CAMERA_CONN_N SYM_VER-1 PP5V_S3_CAMERA_F 0402-LF A LVDS_IG_A_DATA_N LVDS_IG_A_DATA_P LVDS_IG_A_DATA_N LVDS_IG_A_DATA_P LVDS_IG_A_DATA_N LVDS_IG_A_DATA_P LVDS_IG_A_CLK_F_N LVDS_IG_A_CLK_F_P 90-OHM-200MA 72 66 18 23 =GND_CHASSIS_LVDS C9015 0.001UF 10% 50V CERM 402 C9010 NC NC VOLTAGE=5V MIN_NECK_WIDTH=0.20 MM MIN_LINE_WIDTH=0.30 MM 10 11 12 13 14 15 16 17 18 19 20 21 22 B LCD I/F CAMERA I/F 24 0.001UF 66 10% 50V CERM 402 =GND_CHASSIS_LVDS 26 Plexi: 516S0212 *Enclosure: 518S0364 R90121 INVERTER,LVDS 1K 5% 1/16W MF-LF 402 SYNC_MASTER=K36B_MLB SYNC_DATE=08/17/2008 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT LVDS: Power +VDD_IFPx at 1.8V Dual-channel TMDS: Power +VDD_IFPx at 3.3V III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC SCALE SHT NONE REV 051-8089 02 OF 90 109 A 18 =MCP_HDMI_DDC_CLK DP_IG_DDC_CLK DP_IG_DDC_DATA 18 68 D9301, D9302, D9303, D9304 PLACE CLOSE TO J9401 MAKE_BASE=TRUE =MCP_HDMI_DDC_DATA 68 MAKE_BASE=TRUE CRITICAL CRITICAL CRITICAL CRITICAL D9301 D9301 D9303 D9303 RCLAMP0524P RCLAMP0524P RCLAMP0524P RCLAMP0524P SLP2510P8 SLP2510P8 SLP2510P8 SLP2510P8 D D IO IO NC MCP_HDMI_TXC_N IO NC 10 GND GND NC GND NC IO 3 C9302 0.1UF 20% 10V CERM 18 MCP_HDMI_TXC_P 18 402 IO NC 402 0.1UF 20% NC IO C9301 10V CERM IO NC 10 GND NC IO TMDS_TX_CLK_P 68 TMDS_TX_CLK_N 68 TMDS_TX_P 68 TMDS_TX_N 68 TMDS_TX_P 68 TMDS_TX_N 68 C9303 MCP_HDMI_TXD_N C9304 0.1UF 20% 10V CERM 18 402 MCP_HDMI_TXD_P 18 402 0.1UF 20% 10V CERM C9305 MCP_HDMI_TXD_N C9306 0.1UF 20% 10V CERM 18 402 MCP_HDMI_TXD_P 18 C 402 0.1UF 20% 10V CERM C C9307 C9308 0.1UF 20% 402 68 TMDS_TX_N 68 R9305 R9307 1% 1/16W MF-LF 402 2 R9308 499 499 499 1% 1/16W MF-LF 402 1% 1/16W MF-LF 402 1% 1/16W MF-LF 402 499 1% 1/16W MF-LF 402 R9303 TMDS_TX_P R9306 499 1% 1/16W MF-LF 402 1% 1/16W MF-LF 402 1% 1/16W MF-LF 402 R9304 499 R9302 499 R9301 499 10V CERM MCP_HDMI_TXD_N MCP_HDMI_TXD_P 18 18 402 0.1UF 20% 10V CERM B B 18 1.00K2 MCP_HDMI_HPD 600-OHM-300MA HDMI_HPD_R 18 1M C9321 5% 1/16W MF-LF 402 180PF 100K A DP_IG_CA_DET 68 R93701 C9320 R9322 100PF 5% 50V CERM 402 TMDS_HTPLG 0402 0.1% 1/16W MF 402 Interface Mode Setting L9320 R9321 5% 50V CERM 402 1% 1/16W MF-LF 402 TMDS ALIASES SYNC_MASTER=K36B_MLB SYNC_DATE=08/17/2008 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE R9322, C9320 PLEASE PLACE CLOSE TO MCP79 R9321, L9320, C9321 PLEASE PLACE CLOSE TO J9401 II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC SCALE SHT NONE REV 051-8089 02 OF 93 109 A Video Connectors EXTERNAL VIDEO (VGA) INTERFACE D D Isolation required for DVI power switch TMDS(MINI DVI) INTERFACE NEED CHANGE SYMBOL CRITICAL F9404 VOLTAGE=5V MIN_LINE_WIDTH=0.30 MM MIN_NECK_WIDTH=0.20 MM 600-OHM-300MA 1SS418 PP5V_S0_TMDS_FUSE L9444 D9401 0.5AMP-13.2V =PP5V_S0_TMDS 1 PP5V_S0_DVIPORT VOLTAGE=5V MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.25 MM SOD-723-HF SM-HF 0402 1 C9408 0.047UF 10% 16V X7R 402 C9409 0.047UF 10% 16V X7R 402 C9404 0.1UF PLACE THE RESISTOR CLOSE TO MCP79 AND THE CAP NEAR J9401 68 VOLTAGE=5V MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.25 MM =PP3V3_S0_TMDS 20% 10V CERM 402 C9409 PLACE CLOSE TO Z0912 68 C9460 0.1UF =GND_CHASSIS_TMDS_UPPER 20% 10V CERM 402 CRITICAL 68 U9404 CRT_IG_HSYNC 71 18 C9408 PLACE CLOSE TO F9404 R9460 SN74LVC2G125DCU 5% 1/16W MF-LF 402 PP5V_S0_DVIPORT_D R9470 US VCC A CRT_HSYNC_LS_R 125 Y CRT_HSYNC_LS 39 VGA_HSYNC 5% 1/16W MF-LF 402 GND 68 NO STUFF C9442 47PF 5% DVI power DIODE on page 95 (D9500) 50V CERM R9462 2.7K C R9463 2.7K 5% 1/16W MF-LF 4022 67 5% 1/16W MF-LF 2402 71 18 CRT_IG_VSYNC R9461 U9404 SN74LVC2G125DCU TMDS_HTPLG R9471 39 US VCC A CRT_VSYNC_LS_R 5% 1/16W MF-LF 402 125 Y CRT_VSYNC_LS 1 R94221 1/16W MF-LF 4022 1/16W MF-LF 402 2 50V CERM C9410 402 G NOTE: CRT_DDC_* ARE NOT 5V COMPLIANT C9411 Q9401 SSM6N15FEAPE 5% 25V CERM 402 CRITICAL 220PF SOT563 S 67 GPU_CRT_DDC_CLK SOT563 D DP_IG_DDC_DATA SSM6N15FEAPE G BI 2.7K 5% D BI DP_IG_DDC_CLK L9405 90-OHM-100MA 1210-4SM1 OMIT GPU_CRT_DDC_DATA J9401 C9412 220PF NC NC B CRITICAL D9400 SC70-6-1 68 VGA_B VGA_HSYNC 26 18 27 19 28 20 29 RCLAMP0504F 68 VGA_G VGA_VSYNC VG signal trace, we need follow NV’s recommendation So we need change the segment impedance base on NV design guide A segment: 37.5 ohm from MCP to 150 ohm PD res: Top/bottom layer width is 0.18 mm B segment: 50 ohm B/W 150 PF res inner layer width is 0.09 mm top/bottom layer width is 0.115 mm C segment: 75 ohm from FL to connector, top/bottom layer width is 0.076 mm VGA_R 30 22 31 32 24 TMDS_TX_CONN_P 67 L9407 90-OHM-100MA 1210-4SM1 TMDS_TX_CONN_N TMDS_TX_CONN_P TMDS_TX_CONN_N 67 TMDS_TX_N 67 B SYM_VER-1 CRITICAL TMDS_TX_CONN_P TMDS_TX_CONN_N TMDS_TX_P L9406 90-OHM-100MA 1210-4SM1 TMDS_TX_P 67 TMDS_TX_N 67 TMDS_TX_CONN_CLK_P TMDS_TX_CONN_CLK_N SYM_VER-1 CRITICAL L9404 33 34 35 36 300-OHM-100MA 1210-4SM 68 FL9400 210MHZ =GND_CHASSIS_TMDS_UPPER =GND_CHASSIS_TMDS_DOWN TMDS_TX_CLK_P 67 TMDS_TX_CLK_N 67 SYM_VER-1 MEA2010P-SM MINI-DVI CONNECTOR 71 18 CRT_IG_B_COMP_PB SYNC_MASTER=K36B_MLB SYNC_DATE=08/17/2008 R9491 150 1% 1/16W MF-LF 402 R9492 150 1% 1/16W MF-LF 402 NOTICE OF PROPRIETARY PROPERTY CRITICAL THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE R9490 150 1% 1/16W MF-LF 402 1% 1/16W MF-LF 402 1 R9495 150 R9494 150 1% 1/16W MF-LF 402 1% 1/16W MF-LF 402 R9493 150 71 18 CRT_IG_G_Y_Y 2 CRT_IG_R_C_PR 71 18 A TMDS_TX_N CRITICAL 10 11 12 13 14 15 16 25 PP5V_S0_DVIPORT 17 67 SYM_VER-1 F-RT-TH-HF 68 TMDS_TX_P MINI-DVI-M42-MG3 5% 25V CERM 402 CRITICAL for for for for C9443 47PF 10% 50V CERM 402 Q9401 S 67 68 NO STUFF 0.001UF R94211 2.7K 5% VGA_VSYNC 5% 1/16W MF-LF 402 GND C 5% =PP3V3_S0_TMDS 68 402 PLACE THE RESISTOR CLOSE TO MCP79 AND THE CAP NEAR THE CONNECTOR CRITICAL II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE R9493, R9494, R9495 PLACE CLOSE TO U1400 DRAWING NUMBER D R9490, R9491, R9492 PLACE CLOSE TO FL9400 APPLE INC SCALE SHT NONE REV 051-8089 02 OF 94 109 A FSB (Front-Side Bus) Constraints CPU / FSB Net Properties TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP FSB_50S * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD NET_TYPE ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING TABLE_PHYSICAL_RULE_ITEM FSB_DATA_GROUP0 FSB_50S FSB_DATA FSB_DATA_GROUP0 FSB_50S FSB_DATA FSB_DSTB0 FSB_DSTB_50S FSB_DSTB FSB_DSTB0 FSB_DSTB_50S FSB_DSTB FSB_DATA_GROUP1 FSB_50S FSB_DATA FSB_DATA_GROUP1 FSB_50S FSB_DATA FSB_DSTB1 FSB_DSTB_50S FSB_DSTB FSB_DSTB1 FSB_DSTB_50S FSB_DSTB FSB_DATA_GROUP2 FSB_50S FSB_DATA FSB_DATA_GROUP2 FSB_50S FSB_DATA FSB_DSTB2 FSB_DSTB_50S FSB_DSTB FSB_DSTB2 FSB_DSTB_50S FSB_DSTB FSB_DATA_GROUP3 FSB_50S FSB_DATA FSB_DATA_GROUP3 FSB_50S FSB_DATA FSB_DSTB3 FSB_DSTB_50S FSB_DSTB FSB_DSTB3 FSB_DSTB_50S FSB_DSTB FSB_ADDR_GROUP0 FSB_50S FSB_ADDR FSB_ADDR_GROUP0 FSB_50S FSB_ADDR FSB_ADSTB0 FSB_50S FSB_ADSTB FSB_ADDR_GROUP1 FSB_50S FSB_ADDR FSB_ADSTB1 FSB_50S FSB_ADSTB FSB_1X FSB_50S FSB_1X FSB_BREQ0_L FSB_50S FSB_1X FSB_BREQ1_L FSB_50S FSB_1X FSB_1X FSB_50S FSB_1X FSB_1X FSB_50S FSB_1X FSB_1X FSB_50S FSB_1X FSB_1X FSB_50S FSB_1X FSB_1X FSB_50S FSB_1X FSB_1X FSB_50S FSB_1X FSB_1X FSB_50S FSB_1X FSB_1X FSB_50S FSB_1X FSB_CPURST_L FSB_50S FSB_1X FSB_1X FSB_50S FSB_1X FSB_1X FSB_50S FSB_1X CPU_ASYNC CPU_50S CPU_AGTL CPU_BSEL CPU_50S CPU_AGTL CPU_FERR_L CPU_50S CPU_8MIL CPU_ASYNC CPU_50S CPU_AGTL CPU_INIT_L CPU_50S CPU_AGTL CPU_ASYNC_R CPU_50S CPU_AGTL CPU_ASYNC_R CPU_50S CPU_AGTL CPU_PROCHOT_L CPU_50S CPU_AGTL CPU_PWRGD CPU_50S CPU_AGTL CPU_ASYNC CPU_50S CPU_AGTL CPU_ASYNC CPU_50S CPU_AGTL PM_THRMTRIP_L CPU_50S CPU_8MIL FSB_CPUSLP_L CPU_50S CPU_AGTL CPU_FROM_SB CPU_50S CPU_AGTL CPU_DPRSTP_L CPU_50S CPU_AGTL CPU_ASYNC CPU_50S CPU_AGTL MCP_CPU_COMP MCP_50S MCP_FSB_COMP TABLE_PHYSICAL_RULE_ITEM * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =1:1_DIFFPAIR =1:1_DIFFPAIR TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LINE-TO-LINE SPACING WEIGHT FSB_DATA LAYER * =2x_DIELECTRIC ? FSB_DSTB * =3x_DIELECTRIC ? FSB_ADDR * =STANDARD ? TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LINE-TO-LINE SPACING WEIGHT FSB_DATA TOP,BOTTOM LAYER =4x_DIELECTRIC ? FSB_DSTB TOP,BOTTOM =5x_DIELECTRIC ? FSB_ADDR TOP,BOTTOM =3x_DIELECTRIC ? TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM D TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM FSB_ADSTB * =2x_DIELECTRIC TABLE_SPACING_RULE_ITEM ? FSB_ADSTB TOP,BOTTOM =4x_DIELECTRIC ? TABLE_SPACING_RULE_ITEM FSB_1X * =STANDARD FSB 4X Signal Groups FSB_DSTB_50S TABLE_SPACING_RULE_ITEM ? FSB_1X TOP,BOTTOM =3x_DIELECTRIC ? All 4x/2x/1x FSB signals with impedance requirements are 50-ohm single-ended FSB 2X Signals FSB 4X signals / groups shown in signal table on right Signals within each 4x group should be matched within ps of strobe DSTB# complementary pairs should be matched within ps of each other, all DSTB#s matched to +/- 300 ps Spacing is 2x dielectric between DATA#, DINV# signals, with 3x dielectric spacing to the DSTB#s DSTB# complementary pairs are spaced normally and are NOT routed as differential pairs FSB 2X signals / groups shown in signal table on right Signals within each 2x group should be matched within 20 ps ADTSB#s should be matched +/- 300 ps Spacing is 1x dielectric between ADDR#, REQ# signals, with 2x dielectric spacing to ADSTB# FSB 1X signals shown in signal table on right Signals within each 1x group should be matched to CPU clock, +0/-1000 mils FSB 1X Signals Design Guide recommends each strobe/signal group is routed on the same layer Intel Design Guide recommends FSB signals be routed only on internal layers NOTE: Intel Design Guide allows closer spacing if signal lengths can be shortened SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2 SOURCE: Santa Rosa Platform DG, Rev 1.5 (#22294), Sections 4.2 & 4.3 CPU Signal Constraints TABLE_PHYSICAL_RULE_HEAD C PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM CPU_50S * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD TABLE_PHYSICAL_RULE_ITEM CPU_27P4S * =27P4_OHM_SE =27P4_OHM_SE =27P4_OHM_SE =27P4_OHM_SE MIL MIL NOTE: mil gap is for VCCSense pair, which Intel says to route with mil spacing without specifying a target impedance TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT =STANDARD ? TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT =2x_DIELECTRIC ? TABLE_SPACING_RULE_ITEM CPU_AGTL * TABLE_SPACING_RULE_ITEM CPU_AGTL TOP,BOTTOM TABLE_SPACING_RULE_ITEM CPU_8MIL * MIL ? TABLE_SPACING_RULE_ITEM CPU_COMP * 25 MIL ? TABLE_SPACING_RULE_ITEM CPU_GTLREF * 25 MIL SR DG recommends at least 25 mils, >50 mils preferred ? TABLE_SPACING_RULE_ITEM CPU_ITP * =2:1_SPACING ? CPU_VCCSENSE * 25 MIL ? TABLE_SPACING_RULE_ITEM Most CPU signals with impedance requirements are 55-ohm single-ended Some signals require 27.4-ohm single-ended impedance SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2 SOURCE: Santa Rosa Platform DG, Rev 0.9 (#20517), Sections 4.4 & 5.8.2.4 MCP FSB COMP Signal Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MCP_50S * =50_OHM_SE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD TABLE_PHYSICAL_RULE_ITEM B MCP_CPU_COMP MCP_50S MCP_FSB_COMP MCP_CPU_COMP MCP_50S MCP_FSB_COMP MCP_CPU_COMP MCP_50S MCP_FSB_COMP FSB_CLK_CPU CLK_FSB_100D CLK_FSB FSB_CLK_CPU CLK_FSB_100D CLK_FSB FSB_CLK_ITP CLK_FSB_100D CLK_FSB FSB_CLK_ITP CLK_FSB_100D CLK_FSB FSB_CLK_MCP CLK_FSB_100D CLK_FSB FSB_CLK_MCP CLK_FSB_100D CLK_FSB CPU_IERR_L CPU_50S PM_DPRSLPVR CPU_50S CPU_AGTL (See above) CPU_50S CPU_AGTL CPU_GTLREF CPU_50S CPU_GTLREF TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM MCP_FSB_COMP * MIL ? SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2.4 FSB Clock Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF LAYER LINE-TO-LINE SPACING WEIGHT LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM CLK_FSB * =3x_DIELECTRIC CPU_COMP CPU_50S CPU_COMP CPU_COMP CPU_27P4S CPU_COMP CPU_COMP CPU_50S CPU_COMP CPU_COMP CPU_27P4S CPU_COMP XDP_TDI CPU_50S CPU_ITP XDP_TDO1 CPU_50S CPU_ITP XDP_TMS CPU_50S CPU_ITP XDP_TCK CPU_50S CPU_ITP XDP_TRST_L CPU_50S CPU_ITP XDP_BPM_L CPU_50S CPU_ITP XDP_BPM_L5 CPU_50S CPU_ITP (FSB_CPURST_L) CPU_50S CPU_ITP CPU_50S CPU_8MIL CPU_50S CPU_8MIL CPU_27P4S CPU_VCCSENSE TABLE_SPACING_RULE_HEAD SPACING_RULE_SET TABLE_SPACING_RULE_ITEM ? CLK_FSB TOP,BOTTOM =4x_DIELECTRIC FSB_D_L FSB_DINV_L FSB_DSTB_L_P FSB_DSTB_L_N FSB_D_L FSB_DINV_L FSB_DSTB_L_P FSB_DSTB_L_N FSB_A_L FSB_REQ_L FSB_ADSTB_L FSB_A_L FSB_ADSTB_L FSB_ADS_L FSB_BREQ0_L FSB_BREQ1_L FSB_BNR_L FSB_BPRI_L FSB_DBSY_L FSB_DEFER_L FSB_DRDY_L FSB_HIT_L FSB_HITM_L FSB_LOCK_L FSB_CPURST_L FSB_RS_L FSB_TRDY_L CPU_A20M_L CPU_BSEL CPU_FERR_L CPU_IGNNE_L CPU_INIT_L CPU_INTR CPU_NMI CPU_PROCHOT_L CPU_PWRGD CPU_SMI_L CPU_STPCLK_L PM_THRMTRIP_L FSB_CPUSLP_L CPU_DPSLP_L CPU_DPRSTP_L FSB_DPWR_L MCP_BCLK_VML_COMP_VDD MCP_BCLK_VML_COMP_GND MCP_CPU_COMP_VCC MCP_CPU_COMP_GND FSB_CLK_CPU_P FSB_CLK_CPU_N FSB_CLK_ITP_P FSB_CLK_ITP_N FSB_CLK_MCP_P FSB_CLK_MCP_N CPU_IERR_L =100_OHM_DIFF TABLE_SPACING_RULE_HEAD SPACING_RULE_SET FSB_D_L FSB_DINV_L FSB_DSTB_L_P FSB_DSTB_L_N 10 14 10 14 10 14 10 14 10 14 10 14 10 14 D 10 14 10 14 10 14 10 14 10 14 10 14 10 14 10 14 10 14 10 14 10 14 10 14 10 14 10 14 10 14 10 14 14 10 14 10 14 10 14 10 14 10 14 10 14 10 14 C 10 14 10 13 14 10 14 10 14 10 14 10 10 14 10 14 10 14 10 14 10 14 10 14 42 60 10 13 14 10 14 10 14 10 14 42 10 14 10 14 10 14 60 10 14 14 14 14 14 10 14 10 14 B 13 14 13 14 14 14 10 PM_DPRSLPVR IMVP_DPRSLPVR 21 60 60 DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM CLK_FSB_100D FSB_D_L FSB_DINV_L FSB_DSTB_L_P FSB_DSTB_L_N CPU_GTLREF CPU_COMP CPU_COMP CPU_COMP CPU_COMP 10 27 10 10 10 10 ? SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2.5 CPU_VCCSENSE A CPU_VCCSENSE CPU_27P4S CPU_VCCSENSE (CPU_VCCSENSE) (CPU_VCCSENSE) CPU_27P4S CPU_VCCSENSE CPU_27P4S CPU_VCCSENSE XDP_TDI XDP_TDO XDP_TMS XDP_TCK XDP_TRST_L XDP_BPM_L XDP_BPM_L XDP_CPURST_L CPU_VID IMVP6_VID CPU_VCCSENSE_P CPU_VCCSENSE_N IMVP6_VSEN_P IMVP6_VSEN_N 10 13 10 10 13 10 13 10 13 10 13 10 13 13 11 60 CPU/FSB Constraints 11 60 SYNC_MASTER=K36B_MLB SYNC_DATE=08/17/2008 11 60 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC SCALE SHT NONE REV 051-8089 02 OF 100 109 A Memory Bus Constraints Memory Net Properties TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP MEM_40S * =40_OHM_SE =40_OHM_SE =40_OHM_SE =40_OHM_SE =STANDARD =STANDARD NET_TYPE ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING TABLE_PHYSICAL_RULE_ITEM MEM_A_CLK MEM_70D_VDD MEM_CLK MEM_A_CLK MEM_70D_VDD MEM_CLK MEM_A_CNTL MEM_40S_VDD MEM_CTRL MEM_A_CNTL MEM_40S_VDD MEM_CTRL MEM_A_CNTL MEM_40S_VDD MEM_CTRL MEM_A_CMD MEM_40S_VDD MEM_CMD MEM_A_CMD MEM_40S_VDD MEM_CMD MEM_A_CMD MEM_40S_VDD MEM_CMD MEM_A_CMD MEM_40S_VDD MEM_CMD MEM_A_CMD MEM_40S_VDD MEM_CMD MEM_A_DQ_BYTE0 MEM_40S MEM_DATA MEM_A_DQ_BYTE1 MEM_40S MEM_DATA MEM_A_DQ_BYTE2 MEM_40S MEM_DATA MEM_A_DQ_BYTE3 MEM_40S MEM_DATA MEM_A_DQ_BYTE4 MEM_40S MEM_DATA MEM_A_DQ_BYTE5 MEM_40S MEM_DATA MEM_A_DQ_BYTE6 MEM_40S MEM_DATA MEM_A_DQ_BYTE7 MEM_40S MEM_DATA MEM_A_DQ_BYTE0 MEM_40S MEM_DATA MEM_A_DQ_BYTE1 MEM_40S MEM_DATA MEM_A_DQ_BYTE2 MEM_40S MEM_DATA MEM_A_DQ_BYTE3 MEM_40S MEM_DATA MEM_A_DQ_BYTE4 MEM_40S MEM_DATA MEM_A_DQ_BYTE5 MEM_40S MEM_DATA MEM_A_DQ_BYTE6 MEM_40S MEM_DATA MEM_A_DQ_BYTE7 MEM_40S MEM_DATA MEM_A_DQS0 MEM_70D MEM_DQS MEM_A_DQS0 MEM_70D MEM_DQS MEM_A_DQS1 MEM_70D MEM_DQS MEM_A_DQS1 MEM_70D MEM_DQS MEM_A_DQS2 MEM_70D MEM_DQS MEM_A_DQS2 MEM_70D MEM_DQS MEM_A_DQS3 MEM_70D MEM_DQS MEM_A_DQS3 MEM_70D MEM_DQS MEM_A_DQS4 MEM_70D MEM_DQS MEM_A_DQS4 MEM_70D MEM_DQS MEM_A_DQS5 MEM_70D MEM_DQS MEM_A_DQS5 MEM_70D MEM_DQS MEM_A_DQS6 MEM_70D MEM_DQS MEM_A_DQS6 MEM_70D MEM_DQS MEM_A_DQS7 MEM_70D MEM_DQS MEM_A_DQS7 MEM_70D MEM_DQS MEM_B_CLK MEM_70D_VDD MEM_CLK MEM_B_CLK MEM_70D_VDD MEM_CLK MEM_B_CNTL MEM_40S_VDD MEM_CTRL MEM_B_CNTL MEM_40S_VDD MEM_CTRL MEM_B_CNTL MEM_40S_VDD MEM_CTRL MEM_B_CMD MEM_40S_VDD MEM_CMD MEM_B_CMD MEM_40S_VDD MEM_CMD MEM_B_CMD MEM_40S_VDD MEM_CMD MEM_B_CMD MEM_40S_VDD MEM_CMD MEM_B_CMD MEM_40S_VDD MEM_CMD MEM_B_DQ_BYTE0 MEM_40S MEM_DATA MEM_B_DQ_BYTE1 MEM_40S MEM_DATA MEM_B_DQ_BYTE2 MEM_40S MEM_DATA MEM_B_DQ_BYTE3 MEM_40S MEM_DATA MEM_B_DQ_BYTE4 MEM_40S MEM_DATA MEM_B_DQ_BYTE5 MEM_40S MEM_DATA MEM_B_DQ_BYTE6 MEM_40S MEM_DATA DQ signals should be matched within ps of associated DQS pair DQS intra-pair matching should be within ps, inter-pair matching shoulw be within 180 ps No DQS to clock matching requirement CLK intra-pair matching should be within ps, inter-pair matching should be within ps A/BA/cmd signals should be matched within ps of CLK pairs All memory signals maximum length is 1.005 ps CLK minimum length is 594 ps (lengths include substrate) DQ/A/BA/cmd signal spacing is 3x dielectric, DQS/CLK is 4x dielectric MEM_B_DQ_BYTE7 MEM_40S MEM_DATA MEM_B_DQ_BYTE0 MEM_40S MEM_DATA MEM_B_DQ_BYTE1 MEM_40S MEM_DATA MEM_B_DQ_BYTE2 MEM_40S MEM_DATA MEM_B_DQ_BYTE3 MEM_40S MEM_DATA MEM_B_DQ_BYTE4 MEM_40S MEM_DATA MEM_B_DQ_BYTE5 MEM_40S MEM_DATA SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.3 SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Section 6.2 MEM_B_DQ_BYTE6 MEM_40S MEM_DATA MEM_B_DQ_BYTE7 MEM_40S MEM_DATA MCP MEM COMP Signal Constraints MEM_B_DQS0 MEM_70D MEM_DQS MEM_B_DQS0 MEM_70D MEM_DQS MEM_B_DQS1 MEM_70D MEM_DQS MEM_B_DQS1 MEM_70D MEM_DQS MEM_B_DQS2 MEM_70D MEM_DQS MEM_B_DQS2 MEM_70D MEM_DQS MEM_B_DQS3 MEM_70D MEM_DQS MEM_B_DQS3 MEM_70D MEM_DQS MEM_B_DQS4 MEM_70D MEM_DQS MEM_B_DQS4 MEM_70D MEM_DQS MEM_B_DQS5 MEM_70D MEM_DQS MEM_B_DQS5 MEM_70D MEM_DQS MEM_B_DQS6 MEM_70D MEM_DQS TABLE_PHYSICAL_RULE_ITEM MEM_40S_VDD * =40_OHM_SE =40_OHM_SE =40_OHM_SE =40_OHM_SE =STANDARD =STANDARD MEM_A_CLK_P MEM_A_CLK_N 15 28 15 28 TABLE_PHYSICAL_RULE_ITEM MEM_70D * =70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF MEM_70D_VDD * =70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_HEAD SPACING_RULE_SET D LAYER LINE-TO-LINE SPACING WEIGHT =4:1_SPACING ? TABLE_SPACING_RULE_ITEM MEM_CLK2MEM * TABLE_SPACING_RULE_ITEM MEM_CTRL2CTRL * =2:1_SPACING ? MEM_A_CKE MEM_A_CS_L MEM_A_ODT MEM_A_A MEM_A_BA MEM_A_RAS_L MEM_A_CAS_L MEM_A_WE_L 15 28 30 15 28 30 15 28 30 15 28 30 15 28 30 D 15 28 30 15 28 30 15 28 30 TABLE_SPACING_RULE_ITEM MEM_CTRL2MEM * =2.5:1_SPACING ? MEM_CMD2CMD * =1.5:1_SPACING ? TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM MEM_CMD2MEM * =3:1_SPACING ? TABLE_SPACING_RULE_ITEM MEM_DATA2DATA * =1.5:1_SPACING ? TABLE_SPACING_RULE_ITEM MEM_DATA2MEM * =3:1_SPACING ? TABLE_SPACING_RULE_ITEM MEM_DQS2MEM * ? =3:1_SPACING MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ 15 28 15 28 15 28 15 28 15 28 15 28 15 28 15 28 TABLE_SPACING_RULE_ITEM MEM_2OTHER * 25 MIL ? Memory Bus Spacing Group Assignments TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET TABLE_SPACING_ASSIGNMENT_ITEM MEM_CLK MEM_CLK * MEM_CLK2MEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CMD MEM_CLK * MEM_CMD2MEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CLK MEM_CTRL * MEM_CLK2MEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CMD MEM_CTRL * MEM_CMD2MEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CLK MEM_CMD * MEM_CLK2MEM MEM_CLK MEM_DATA * MEM_CLK2MEM MEM_CLK MEM_DQS * MEM_CLK2MEM MEM_CMD MEM_CMD * MEM_CMD2CMD MEM_CMD MEM_DATA * MEM_CMD2MEM MEM_CMD MEM_DQS * MEM_CMD2MEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_HEAD C NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET MEM_CTRL MEM_CLK * MEM_CTRL2MEM TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET MEM_DATA MEM_CLK * MEM_DATA2MEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CTRL MEM_CTRL * MEM_CTRL2CTRL MEM_CTRL MEM_CMD * MEM_CTRL2MEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_DATA MEM_CTRL * MEM_DATA2MEM MEM_DATA MEM_CMD * MEM_DATA2MEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CTRL MEM_DATA * MEM_CTRL2MEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_DATA MEM_DATA * MEM_DATA2DATA TABLE_SPACING_ASSIGNMENT_ITEM MEM_CTRL MEM_DQS * MEM_CTRL2MEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_DATA MEM_DQS * MEM_DATA2MEM TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET MEM_DQS MEM_CLK * MEM_DQS2MEM MEM_DQS MEM_CTRL * MEM_DQS2MEM TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET MEM_CLK * * MEM_2OTHER MEM_CTRL * * MEM_2OTHER TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CMD * MEM_DQS2MEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CMD * * MEM_2OTHER TABLE_SPACING_ASSIGNMENT_ITEM MEM_DQS MEM_DATA * MEM_DQS2MEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_DATA * * MEM_DQS * MEM_DQS2MEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_DQS * * MEM_2OTHER Need to support MEM_*-style wildcards! DDR2: B DQ signals should be matched within 20 ps of associated DQS pair DQS intra-pair matching should be within ps, no inter-pair matching requirement All DQS pairs should be matched within 100 ps of clocks CLK intra-pair matching should be within ps, inter-pair matching should be within 140 ps A/BA/cmd signals should be matched within 75 ps, no CLK matching requirement All memory signals maximum length is 1.005 ps CLK minimum length is 594 ps (lengths include substrate) DQ/A/BA/cmd signal spacing is 3x dielectric, DQS/CLK is 4x dielectric DDR3: TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM MCP_MEM_COMP * Y MIL MIL =STANDARD =STANDARD =STANDARD TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM MCP_MEM_COMP * MIL 15 28 15 28 15 28 15 28 15 28 15 28 MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_B_CLK_P MEM_B_CLK_N 15 28 15 28 15 28 15 28 15 28 15 28 C 15 28 15 28 15 28 15 28 15 28 15 28 15 28 15 28 15 28 15 28 15 29 MEM_B_CKE MEM_B_CS_L MEM_B_ODT 15 29 15 29 30 15 29 30 15 29 30 MEM_2OTHER TABLE_SPACING_ASSIGNMENT_ITEM MEM_DQS 15 28 TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_DQS 15 28 TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM NET_SPACING_TYPE1 MEM_A_DM MEM_A_DM MEM_A_DM MEM_A_DM MEM_A_DM MEM_A_DM MEM_A_DM MEM_A_DM ? SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.3.4 A MEM_B_DQS6 MEM_70D MEM_DQS MEM_B_DQS7 MEM_70D MEM_DQS MEM_B_DQS7 MEM_70D MEM_DQS MCP_MEM_COMP MCP_MEM_COMP MCP_MEM_COMP MCP_MEM_COMP MCP_MEM_COMP MCP_MEM_COMP MEM_B_A MEM_B_BA MEM_B_RAS_L MEM_B_CAS_L MEM_B_WE_L MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DM MEM_B_DM MEM_B_DM MEM_B_DM MEM_B_DM MEM_B_DM MEM_B_DM MEM_B_DM 15 29 30 15 29 30 15 29 30 15 29 30 15 29 30 15 29 15 29 15 29 15 29 B 15 29 15 29 15 29 15 29 15 29 15 29 15 29 15 29 15 29 15 29 15 29 15 29 MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MCP_MEM_COMP_VDD MCP_MEM_COMP_GND 15 29 15 29 15 29 15 29 15 29 15 29 15 29 15 29 15 29 15 29 15 29 Memory Constraints 15 29 15 29 SYNC_MASTER=K36B_MLB SYNC_DATE=08/17/2008 15 29 NOTICE OF PROPRIETARY PROPERTY 15 29 15 29 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING 16 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE 16 II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC SCALE SHT NONE REV 051-8089 02 OF 101 109 A PCI-Express TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP PCIE_90D * =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF NET_TYPE ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING TABLE_PHYSICAL_RULE_ITEM PCIE_90D PCIE PCIE_90D PCIE PEG_R2D PCIE_90D PCIE PEG_R2D PCIE_90D PCIE PEG_D2R PCIE_90D PCIE PCIE_90D PCIE PCIE_90D PCIE PCIE_90D PCIE PCIE_90D PCIE PCIE_90D PCIE PCIE_90D PCIE PCIE_90D PCIE PCIE_90D PCIE PCIE_90D PCIE PCIE_90D PCIE PCIE_90D PCIE PCIE_90D PCIE PCIE_90D PCIE PCIE_90D PCIE PCIE_90D PCIE PCIE_90D PCIE PCIE_90D PCIE PCIE_90D PCIE PCIE_90D PCIE PCIE_90D PCIE PCIE_90D PCIE PCIE_90D PCIE PCIE_90D PCIE CLK_PCIE_100D CLK_PCIE CLK_PCIE_100D CLK_PCIE CLK_PCIE_100D CLK_PCIE CLK_PCIE_100D CLK_PCIE CLK_PCIE_100D CLK_PCIE CLK_PCIE_100D CLK_PCIE CLK_PCIE_100D CLK_PCIE CLK_PCIE_100D CLK_PCIE TABLE_PHYSICAL_RULE_ITEM CLK_PCIE_100D * SPACING_RULE_SET LAYER =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF TABLE_SPACING_RULE_HEAD LINE-TO-LINE SPACING TABLE_SPACING_RULE_HEAD WEIGHT SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM PCIE * =3X_DIELECTRIC TABLE_SPACING_RULE_ITEM ? PCIE TOP,BOTTOM =4X_DIELECTRIC ? TABLE_SPACING_RULE_ITEM CLK_PCIE D * 20 MIL ? PEG_R2D_P PEG_R2D_N PEG_R2D_C_P PEG_R2D_C_N PEG_D2R_P PEG_D2R_N PEG_D2R_C_P PEG_D2R_C_N D TABLE_SPACING_RULE_ITEM MCP_PEX_COMP * MIL ? SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.4 PCIE_MINI_R2D Analog Video Signal Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP CRT_50S * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD PCIE_MINI_D2R PCIE_MINI_R2D_P PCIE_MINI_R2D_N PCIE_MINI_R2D_C_P PCIE_MINI_R2D_C_N PCIE_MINI_D2R_P PCIE_MINI_D2R_N 31 31 17 31 17 31 17 31 17 31 TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING TABLE_SPACING_ASSIGNMENT_HEAD WEIGHT NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET TABLE_SPACING_RULE_ITEM CRT * =4:1_SPACING PCIE_FW_R2D TABLE_SPACING_ASSIGNMENT_ITEM ? CRT CRT * CRT_2CRT PCIE_FW_D2R TABLE_SPACING_RULE_ITEM * CRT_2CRT =STANDARD ? TABLE_SPACING_RULE_ITEM CRT_2CLK * 50 MIL ? PCIE_FW_R2D_P PCIE_FW_R2D_N PCIE_FW_R2D_C_P PCIE_FW_R2D_C_N PCIE_FW_D2R_P PCIE_FW_D2R_N PCIE_FW_D2R_C_P PCIE_FW_D2R_C_N 35 35 17 35 17 35 17 35 17 35 35 35 TABLE_SPACING_RULE_ITEM CRT_2SWITCHER * 250 MIL ? TABLE_SPACING_RULE_ITEM CRT_SYNC * 16 MIL ? MCP_DAC_COMP * =2:1_SPACING ? TABLE_SPACING_RULE_ITEM PCIE_EXCARD_R2D CRT signal single-ended impedence varies by location: - 37.5-ohm from MCP to first termination resistor - 50-ohm from first to second termination resistor - 75-ohm from output of three-pole filter to connector (if possible) R/G/B signals should be matched as close as possible and < 10 inches SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Sections 2.5.1 & 2.5.2 C PCIE_EXCARD_D2R MCP_PE0_REFCLK MCP_PE1_REFCLK MCP_PE2_REFCLK Digital Video Signal Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP MCP_PE3_REFCLK TABLE_PHYSICAL_RULE_ITEM DP_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF LVDS_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF MCP_DV_COMP * Y 20 MIL 20 MIL =STANDARD =STANDARD =STANDARD MCP_PEX_CLK_COMP MCP_PEX_COMP PCIE_EXCARD_R2D_P PCIE_EXCARD_R2D_N PCIE_EXCARD_R2D_C_P PCIE_EXCARD_R2D_C_N PCIE_EXCARD_D2R_P PCIE_EXCARD_D2R_N PEG_CLK100M_P PEG_CLK100M_N PCIE_CLK100M_MINI_P PCIE_CLK100M_MINI_N PCIE_CLK100M_FW_P PCIE_CLK100M_FW_N PCIE_CLK100M_EXCARD_P PCIE_CLK100M_EXCARD_N MCP_PEX_CLK_COMP 17 17 17 17 17 17 17 31 17 31 C 17 35 17 35 17 17 17 TABLE_PHYSICAL_RULE_ITEM CRT_RED CRT_MCP_P CRT CRT_GREEN CRT_MCP_P CRT CRT_BLUE CRT_MCP_P CRT CRT_SYNC CRT_50S CRT_SYNC CRT_SYNC CRT_50S TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT =3x_DIELECTRIC ? TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT =4x_DIELECTRIC ? TABLE_SPACING_RULE_ITEM DISPLAYPORT * TOP,BOTTOM TABLE_SPACING_RULE_ITEM LVDS * =3x_DIELECTRIC CRT_SYNC TABLE_SPACING_RULE_ITEM DISPLAYPORT TABLE_SPACING_RULE_ITEM ? LVDS TOP,BOTTOM =4x_DIELECTRIC MCP_DAC_RSET MCP_DAC_COMP MCP_DAC_VREF MCP_DAC_COMP CRT_IG_R_C_PR CRT_IG_G_Y_Y CRT_IG_B_COMP_PB CRT_IG_HSYNC CRT_IG_VSYNC MCP_TV_DAC_RSET MCP_TV_DAC_VREF 18 68 18 68 18 68 18 68 18 68 18 18 ? LVDS intra-pair matching should be mils Pairs should be within 100 mils of clock length DisplayPort/TMDS intra-pair matching should be ps Inter-pair matching should be within 150 ps DIsplayPort AUX CH intra-pair matching should be ps No relationship to other signals Max length of LVDS/DisplayPort/TMDS traces: 12 inches SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Sections 2.5.3 & 2.5.4 SATA Interface Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP SATA_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF TABLE_PHYSICAL_RULE_ITEM TMDS_IG_TXC DP_100D DISPLAYPORT TMDS_IG_TXC DP_100D DISPLAYPORT TMDS_IG_TXD DP_100D DISPLAYPORT TMDS_IG_TXD DP_100D DISPLAYPORT DP_ML DP_100D DISPLAYPORT DP_ML DP_100D DISPLAYPORT DP_AUX_CH DP_100D DISPLAYPORT DP_AUX_CH DP_100D DISPLAYPORT MCP_HDMI_RSET MCP_DV_COMP MCP_HDMI_VPROBE MCP_DV_COMP LVDS_IG_A_CLK LVDS_100D LVDS LVDS_IG_A_CLK LVDS_100D LVDS LVDS_IG_A_DATA LVDS_100D LVDS LVDS_IG_A_DATA LVDS_100D LVDS LVDS_IG_A_DATA3 LVDS_100D LVDS LVDS_IG_A_DATA3 LVDS_100D LVDS LVDS_IG_B_CLK LVDS_100D LVDS LVDS_IG_B_CLK LVDS_100D LVDS LVDS_IG_B_DATA LVDS_100D LVDS LVDS_IG_B_DATA LVDS_100D LVDS LVDS_IG_B_DATA3 LVDS_100D LVDS LVDS_IG_B_DATA3 LVDS_100D LVDS MCP_IFPAB_RSET MCP_DV_COMP TMDS_IG_TXC_P TMDS_IG_TXC_N TMDS_IG_TXD_P TMDS_IG_TXD_N DP_IG_ML_P DP_IG_ML_N TP_DP_IG_AUX_CH_P TP_DP_IG_AUX_CH_N MCP_HDMI_RSET MCP_HDMI_VPROBE 18 25 18 25 TABLE_PHYSICAL_RULE_ITEM SATA_100D_HDD * =100_OHM_DIFF_HDD =100_OHM_DIFF_HDD =100_OHM_DIFF_HDD =100_OHM_DIFF_HDD =100_OHM_DIFF_HDD =100_OHM_DIFF_HDD TABLE_SPACING_RULE_HEAD B SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT =4x_DIELECTRIC ? TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT =3x_DIELECTRIC ? TABLE_SPACING_RULE_ITEM SATA * TABLE_SPACING_RULE_ITEM SATA TOP,BOTTOM TABLE_SPACING_RULE_ITEM SATA_TERMP * MIL ? SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.7.1 MCP_IFPAB_RSET MCP_IFPAB_VPROBE MCP_IFPAB_VPROBE SATA_HDD_R2D SATA_HDD_D2R LVDS_IG_A_CLK_P LVDS_IG_A_CLK_N LVDS_IG_A_DATA_P LVDS_IG_A_DATA_N LVDS_IG_A_DATA_P LVDS_IG_A_DATA_N LVDS_IG_B_CLK_P LVDS_IG_B_CLK_N LVDS_IG_B_DATA_P LVDS_IG_B_DATA_N LVDS_IG_B_DATA_P LVDS_IG_B_DATA_N SATA_100D_HDD SATA SATA_100D_HDD SATA SATA_100D_HDD SATA SATA_100D_HDD SATA SATA_100D_HDD SATA SATA_100D_HDD SATA SATA_100D_HDD SATA SATA_100D_HDD SATA SATA_100D_HDD SATA SATA_100D_HDD SATA SATA_100D SATA SATA_HDD_R2D_C_P SATA_HDD_R2D_C_N SATA_HDD_R2D_P SATA_HDD_R2D_N SATA_HDD_R2D_UF_P SATA_HDD_R2D_UF_N SATA_HDD_D2R_P SATA_HDD_D2R_N SATA_HDD_D2R_C_P SATA_HDD_D2R_C_N 18 66 18 66 B 18 66 18 66 18 18 18 18 18 18 18 18 18 25 18 25 20 38 20 38 38 38 38 38 20 38 20 38 38 38 MCP Constraints SATA_ODD_R2D A SATA_ODD_D2R SATA_100D SATA SATA_100D SATA SATA_100D SATA SATA_100D SATA SATA_ODD_R2D_C_P SATA_ODD_R2D_C_N SATA_ODD_R2D_P SATA_ODD_R2D_N SATA_ODD_R2D_UF_P SATA_ODD_R2D_UF_N SATA_ODD_D2R_P SATA_ODD_D2R_N SATA_ODD_D2R_C_P SATA_ODD_D2R_C_N SATA_ODD_D2R_UF_P SATA_ODD_D2R_UF_N SATA_TERMP MCP_SATA_TERMP SATA_100D SATA SATA_100D SATA SATA_100D SATA SATA_100D SATA SATA_100D SATA SATA_100D SATA SATA_100D SATA 20 38 SYNC_MASTER=K36B_MLB NOTICE OF PROPRIETARY PROPERTY 38 38 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING 38 38 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE 20 38 II NOT TO REPRODUCE OR COPY IT 20 38 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART 38 SIZE 38 DRAWING NUMBER D 38 38 APPLE INC MCP_SATA_TERMP SYNC_DATE=08/17/2008 20 38 SCALE SHT 20 NONE REV 051-8089 02 OF 102 109 A PCI Bus Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP PCI_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD NET_TYPE ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING TABLE_PHYSICAL_RULE_ITEM MCP_DEBUG PCI_55S PCI PCI_AD PCI_55S PCI PCI_AD24 PCI_55S PCI PCI_AD PCI_55S PCI PCI_AD PCI_55S PCI PCI_C_BE_L PCI_55S PCI PCI_CNTL PCI_55S PCI PCI_CNTL PCI_55S PCI PCI_CNTL PCI_55S PCI PCI_CNTL PCI_55S PCI PCI_CNTL PCI_55S PCI PCI_CNTL PCI_55S PCI PCI_CNTL PCI_55S PCI PCI_REQ0_L PCI_55S PCI PCI_GNT0_L PCI_55S PCI PCI_REQ1_L PCI_55S PCI PCI_GNT1_L PCI_55S PCI PCI_INTW_L PCI_55S PCI PCI_INTX_L PCI_55S PCI PCI_INTY_L PCI_55S PCI PCI_INTZ_L PCI_55S PCI MCP_PCI_CLK2 CLK_PCI_55S CLK_PCI CLK_PCI_55S CLK_PCI LPC_AD LPC_55S LPC LPC_FRAME_L0 LPC_55S LPC LPC_RESET_L LPC_55S LPC MCP_LPC_CLK CLK_LPC_55S CLK_LPC MCP_LPC_CLK CLK_LPC_55S CLK_LPC MCP_LPC_CLK CLK_LPC_55S CLK_LPC USB_EXTA USB_90D USB USB_EXTA USB_EXTA USB_EXTA USB_EXTA USB_EXTA USB_90D USB USB_90D USB TABLE_PHYSICAL_RULE_ITEM CLK_PCI_55S * SPACING_RULE_SET LAYER =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD TABLE_SPACING_RULE_HEAD LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM PCI * =STANDARD ? TABLE_SPACING_RULE_ITEM CLK_PCI D * MIL ? SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.8 LPC Bus Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM LPC_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD TABLE_PHYSICAL_RULE_ITEM CLK_LPC_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT MIL ? TABLE_SPACING_RULE_ITEM LPC * TABLE_SPACING_RULE_ITEM CLK_LPC * MIL USB 2.0 Interface Constraints TABLE_PHYSICAL_RULE_HEAD LAYER ALLOW ROUTE ON LAYER? 13 19 D 19 19 ? SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.9.1 PHYSICAL_RULE_SET MCP_DEBUG PCI_AD PCI_AD PCI_AD PCI_PAR PCI_C_BE_L PCI_IRDY_L PCI_DEVSEL_L PCI_PERR_L PCI_SERR_L PCI_STOP_L PCI_TRDY_L PCI_FRAME_L PCI_REQ0_L PCI_GNT0_L PCI_REQ1_L PCI_GNT1_L PCI_INTW_L PCI_INTX_L PCI_INTY_L PCI_INTZ_L MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP PCI_CLK33M_MCP_R PCI_CLK33M_MCP LPC_AD LPC_FRAME_L LPC_RESET_L 19 19 19 41 43 19 41 43 19 26 TABLE_PHYSICAL_RULE_ITEM MCP_USB_RBIAS * =STANDARD MIL MIL =STANDARD =STANDARD =STANDARD USB_90D * =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING TABLE_SPACING_RULE_HEAD WEIGHT SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM USB C * =2x_DIELECTRIC TABLE_SPACING_RULE_ITEM ? USB TOP,BOTTOM =4x_DIELECTRIC ? SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.10.1 I188 I185 SMBus Interface Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP SMB_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD I190 TABLE_PHYSICAL_RULE_ITEM I189 USB_MINI USB_90D USB USB_90D USB USB_90D USB_90D USB USB USB_90D USB USB_90D USB USB_CAMERA USB_90D USB USB_CAMERA USB_90D USB USB_CAMERA USB_90D USB USB_CAMERA USB_90D USB USB_IR USB_90D USB USB_IR USB_90D USB USB_EXTD LAYER LINE-TO-LINE SPACING USB USB USB USB_MINI USB_MINI USB_MINI TABLE_SPACING_RULE_HEAD SPACING_RULE_SET USB_90D USB_90D USB_90D WEIGHT TABLE_SPACING_RULE_ITEM SMB * =2x_DIELECTRIC ? SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.11.1 I183 HD Audio Interface Constraints LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP HDA_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD USB_90D USB USB_TPAD USB_TPAD USB_90D USB_90D USB USB CONN_TPAD_USB_P CONN_TPAD_USB_N USB_BT USB_90D USB USB_BT USB_90D USB USB_BT_P USB_BT_N USB_BT USB_BT USB_90D USB_90D USB USB USB2_BT_F_P_CONN USB2_BT_F_N_CONN USB_EXTB USB_90D USB USB_90D USB USB_90D USB_90D USB USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_TPAD I186 USB_MINI_P USB_MINI_N USB2_AIRPORT_P USB2_AIRPORT_N USB_EXTD_P USB_EXTD_N USB_CAMERA_P USB_CAMERA_N USB2_CAMERA_CONN_P USB2_CAMERA_CONN_N USB_TPAD USB_90D TABLE_PHYSICAL_RULE_ITEM I187 USB_EXTA_P USB_EXTA_N USB2_EXTA_MUXED_P USB2_EXTA_MUXED_N USB2_EXTA_F_P USB2_EXTA_F_N USB_IR_P USB_IR_N USB_TPAD_P USB_TPAD_N TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LPC_CLK33M_SMC_R LPC_CLK33M_SMC LPC_CLK33M_LPCPLUS USB 19 26 26 41 26 43 20 39 20 39 39 C 39 39 39 20 20 31 31 20 20 20 66 20 66 66 66 20 40 20 40 20 20 49 49 TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM HDA * =2x_DIELECTRIC ? MCP_HDA_COMP * MIL ? I194 TABLE_SPACING_RULE_ITEM I193 SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.12.1 B SIO Signal Constraints I192 TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP I191 USB_EXTB USB_EXTB USB_EXTB 20 20 USB_EXTB_P USB_EXTB_N USB2_EXTB_F_P USB2_EXTB_F_N 40 40 20 39 20 39 B 39 39 TABLE_PHYSICAL_RULE_ITEM CLK_SLOW_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD USB_EXCARD USB_EXCARD_P USB_EXCARD_N 20 20 TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT USB_EXTC TABLE_SPACING_RULE_ITEM CLK_SLOW * MIL I184 USB_EXTC_P USB_EXTC_N 20 20 ? MCP_USB_RBIAS_GND MCP_USB_RBIAS MCP_USB_RBIAS SMBUS_MCP_0_CLK SMB_55S SMB SMBUS_MCP_0_DATA SMB_55S SMB SMBUS_MCP_1_CLK SMB_55S SMB SMBUS_MCP_1_DATA SMB_55S SMB HDA_BIT_CLK HDA_55S HDA HDA_55S HDA HDA_55S HDA HDA_55S HDA HDA_55S HDA HDA_55S HDA HDA_55S HDA HDA_55S HDA HDA_55S HDA HDA_55S HDA 20 SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.13 SPI Interface Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP SPI_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING HDA_SYNC WEIGHT TABLE_SPACING_RULE_ITEM SPI * MIL ? HDA_RST_L SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.14 HDA_SDIN0 HDA_SDOUT MCP_HDA_PULLDN_COMP A MCP_HDA_COMP MCP_SUS_CLK SPI_CLK SPI_MOSI SPI_MISO SPI_CS0 CLK_SLOW_55S CLK_SLOW CLK_SLOW_55S CLK_SLOW SPI_55S SPI SPI_55S SPI SPI_55S SPI SPI_55S SPI SPI_55S SPI SPI_55S SPI SPI_55S SPI SPI_55S SPI SMBUS_MCP_0_CLK SMBUS_MCP_0_DATA SMBUS_MCP_1_CLK SMBUS_MCP_1_DATA HDA_BIT_CLK HDA_BIT_CLK_R HDA_SYNC HDA_SYNC_R HDA_RST_R_L HDA_RST_L HDA_SDIN0 HDA_SDIN_CODEC HDA_SDOUT HDA_SDOUT_R MCP_HDA_PULLDN_COMP PM_CLK32K_SUSCLK_R PM_CLK32K_SUSCLK SPI_CLK_R SPI_CLK_MUX SPI_MOSI_R SPI_MOSI_MUX SPI_MISO_MUX SPI_MISO_R SPI_CS0_R_L SPI_CS0_L 13 21 44 13 21 44 21 44 21 44 21 52 21 21 52 21 21 21 52 21 52 21 52 21 MCP Constraints 21 SYNC_MASTER=K36B_MLB SYNC_DATE=08/17/2008 21 26 NOTICE OF PROPRIETARY PROPERTY 26 41 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING 21 43 43 51 21 43 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT 43 51 43 51 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART 51 SIZE DRAWING NUMBER D APPLE INC 051-8089 SCALE SHT NONE REV 21 43 02 OF 103 109 A MCP RGMII (Ethernet) Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP MCP_MII_COMP * =STANDARD 7.5 MIL 7.5 MIL =STANDARD =STANDARD =STANDARD NET_TYPE ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING TABLE_PHYSICAL_RULE_ITEM MCP_MII_COMP_VDD MCP_MII_COMP_GND MCP_MII_COMP MCP_MII_COMP MCP_MII_COMP MCP_MII_COMP MCP_CLK25M_BUF0 ENET_MII_55S MCP_BUF0_CLK ENET_MII_55S MCP_BUF0_CLK ENET_INTR_L ENET_MII_55S ENET_MII ENET_MDIO ENET_MII_55S ENET_MII ENET_MDC ENET_MII_55S ENET_MII ENET_PWRDWN_L ENET_MII_55S ENET_MII ENET_RXCLK ENET_MII_55S ENET_MII TABLE_PHYSICAL_RULE_ITEM ENET_MII_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT MCP_CLK25M_BUF0_R MCP_CLK25M_BUF0 18 18 18 33 TABLE_SPACING_RULE_ITEM MCP_BUF0_CLK * =3:1_SPACING ? ENET_MII * 12 MIL ? TABLE_SPACING_RULE_ITEM D SOURCE: MCP73 Interface DG (DG-02974-001_v01), Sections 2.7.2 & 2.7.4 88E1116R (Ethernet PHY) Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP ENET_MDI_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF ENET_MII_55S ENET_MII ENET_RXD_STRAP ENET_MII_55S ENET_MII ENET_RXD ENET_MII_55S ENET_MII ENET_TXCLK ENET_MII_55S ENET_MII ENET_MII_55S ENET_MII ENET_INTR_L ENET_MDIO ENET_MDC ENET_PWRDWN_L ENET_CLK125M_RXCLK ENET_CLK125M_RXCLK_R ENET_RXD ENET_RX_CTRL 18 32 18 32 D 18 32 32 18 32 18 32 TABLE_PHYSICAL_RULE_ITEM ENET_TXD0 ENET_MII_55S ENET_MII ENET_TXD ENET_MII_55S ENET_MII ENET_TXD ENET_MII_55S ENET_MII ENET_CLK125M_TXCLK ENET_CLK125M_TXCLK_R ENET_TXD ENET_TXD ENET_TX_CTRL ENET_MII_55S ENET_MII ENET_RESET_L ENET_MDI_100D ENET_MDI ENET_MDI_100D ENET_MDI ENET_MDI_P ENET_MDI_N TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM ENET_MDI * 25 MIL ? SOURCE: MCP73 Interface DG (DG-02974-001_v01), Section 2.7.4 ENET_MDI 18 32 32 18 32 18 32 18 32 18 32 32 34 32 34 C C B B Ethernet Constraints A SYNC_MASTER=K36B_MLB SYNC_DATE=08/17/2008 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC SCALE SHT NONE REV 051-8089 02 OF 104 109 A FireWire Interface Constraints FireWire Net Properties TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP FW_110D * =110_OHM_DIFF =110_OHM_DIFF =110_OHM_DIFF =110_OHM_DIFF =110_OHM_DIFF =110_OHM_DIFF NET_TYPE ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING TABLE_PHYSICAL_RULE_ITEM FW_P0_TPA FW_110D FW_TP FW_P0_TPA FW_110D FW_TP FW_P0_TPB FW_110D FW_TP FW_P0_TPB FW_110D FW_TP FW_P1_TPA FW_110D FW_TP FW_P1_TPA FW_110D FW_TP FW_P1_TPB FW_110D FW_TP FW_P1_TPB FW_110D FW_TP FW_P1_TPA FW_110D FW_TP FW_P1_TPA FW_110D FW_TP FW_P1_TPB FW_110D FW_TP FW_P1_TPB FW_110D FW_TP TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM FW_TP * =3:1_SPACING ? D FW_P0_TPA_P FW_P0_TPA_N FW_P0_TPB_P FW_P0_TPB_N FW_P1_TPA_P FW_P1_TPA_N FW_P1_TPB_P FW_P1_TPB_N FW_PORT_A_P FW_PORT_A_N FW_PORT_B_P FW_PORT_B_N 35 37 35 37 35 37 35 37 35 37 35 37 35 37 35 37 D 37 37 37 37 Port Not Used C C B B FireWire Constraints A SYNC_MASTER=K36B_MLB SYNC_DATE=08/17/2008 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC SCALE SHT NONE REV 051-8089 02 OF 105 109 A SMC SMBus Net Properties TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 1TO1_DIFFPAIR * =STANDARD =STANDARD =STANDARD =STANDARD 0.1 MM 0.1 MM NET_TYPE ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING TABLE_PHYSICAL_RULE_ITEM D SMBUS_SMC_A_S3_SCL SMB_55S SMB SMBUS_SMC_A_S3_SDA SMB_55S SMB SMBUS_SMC_B_S0_SCL SMB_55S SMB SMBUS_SMC_B_S0_SDA SMB_55S SMB SMBUS_SMC_0_S0_SCL SMB_55S SMB SMBUS_SMC_0_S0_SDA SMB_55S SMB SMBUS_SMC_BSA_SCL SMB_55S SMB SMBUS_SMC_BSA_SDA SMB_55S SMB SMBUS_SMC_MGMT_SCL SMB_55S SMB SMBUS_SMC_MGMT_SDA SMB_55S SMB SMBUS_SMC_A_S3_SCL SMBUS_SMC_A_S3_SDA SMBUS_SMC_B_S0_SCL SMBUS_SMC_B_S0_SDA SMBUS_SMC_0_S0_SCL SMBUS_SMC_0_S0_SDA SMBUS_SMC_BSA_SCL SMBUS_SMC_BSA_SDA SMBUS_SMC_MGMT_SCL SMBUS_SMC_MGMT_SDA 44 44 44 44 44 44 44 44 D 44 44 SMBus Charger Net Properties NET_TYPE ELECTRICAL_CONSTRAINT_SET PHYSICAL CHGR_CSI 1TO1_DIFFPAIR 1TO1_DIFFPAIR CHGR_CSO 1TO1_DIFFPAIR 1TO1_DIFFPAIR SPACING CHGR_CSI_P CHGR_CSI_N CHGR_CSO_P CHGR_CSO_N C C B B SMC Constraints A SYNC_MASTER=K36B_MLB SYNC_DATE=08/17/2008 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC SCALE SHT NONE REV 051-8089 02 OF 106 109 A K36B BOARD-SPECIFIC SPACING & PHYSICAL CONSTRAINTS TABLE_BOARD_INFO BOARD LAYERS BOARD AREAS BOARD UNITS (MIL or MM) ALLEGRO VERSION TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM NO_TYPE,BGA_P1MM MM 15.5.1 TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE TABLE_SPACING_RULE_ITEM DEFAULT * 0.1 MM ? PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP STANDARD * =DEFAULT ? TABLE_PHYSICAL_RULE_ITEM BGA_P1MM * =DEFAULT ? TABLE_PHYSICAL_RULE_ITEM BGA_P2MM * =DEFAULT ? * * BGA_P1MM * Y =50_OHM_SE =50_OHM_SE 30 MM MM MM * Y =DEFAULT =DEFAULT 12.7 MM =DEFAULT =DEFAULT * BGA_P1MM BGA_P2MM CLK_FSB * BGA_P1MM BGA_P2MM CLK_LPC * BGA_P1MM BGA_P2MM BGA_P3MM MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP * =DEFAULT ? LINE-TO-LINE SPACING WEIGHT TOP,BOTTOM Y MEM_40S_VDD BGA_P1MM STANDARD TABLE_PHYSICAL_ASSIGNMENT_ITEM CLK_PCI * BGA_P1MM BGA_P2MM CLK_PCIE * BGA_P1MM BGA_P2MM CLK_SLOW * BGA_P1MM BGA_P2MM TABLE_PHYSICAL_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM DIFFPAIR NECK GAP D TABLE_SPACING_RULE_HEAD SPACING_RULE_SET TABLE_PHYSICAL_RULE_ITEM 55_OHM_SE STANDARD TABLE_SPACING_ASSIGNMENT_ITEM TABLE_PHYSICAL_RULE_HEAD MINIMUM LINE WIDTH BGA_P1MM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_RULE_ITEM ALLOW ROUTE ON LAYER? MEM_40S BGA_P1MM MEM_CLK TABLE_SPACING_RULE_ITEM DEFAULT LAYER PHYSICAL_RULE_SET DIFFPAIR NECK GAP STANDARD PHYSICAL_RULE_SET AREA_TYPE TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_RULE_ITEM D TABLE_PHYSICAL_ASSIGNMENT_HEAD NET_PHYSICAL_TYPE TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD SPACING_RULE_SET 0.090 MM LAYER 0.090 MM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM 55_OHM_SE * Y 0.076 MM 0.076 MM =STANDARD =STANDARD 1.5:1_SPACING * 0.15 MM ? 2:1_SPACING * 0.2 MM ? TABLE_SPACING_ASSIGNMENT_ITEM =STANDARD FSB_DSTB FSB_DSTB BGA_P1MM BGA_P3MM TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH 50_OHM_SE TOP,BOTTOM Y 0.115 MM 0.115 MM MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP TABLE_SPACING_RULE_ITEM DIFFPAIR NECK GAP 2.5:1_SPACING * 0.25 MM ? 3:1_SPACING * 0.3 MM ? 4:1_SPACING * 0.4 MM ? LINE-TO-LINE SPACING WEIGHT TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM 50_OHM_SE * Y 0.090 MM 0.090 MM =STANDARD =STANDARD =STANDARD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER TABLE_PHYSICAL_RULE_ITEM 40_OHM_SE TOP,BOTTOM Y 0.165 MM TABLE_SPACING_RULE_ITEM 0.165 MM 2X_DIELECTRIC TOP,BOTTOM 0.140 MM ? 3X_DIELECTRIC TOP,BOTTOM 0.210 MM ? 4X_DIELECTRIC TOP,BOTTOM 0.280 MM ? 5X_DIELECTRIC TOP,BOTTOM 0.350 MM ? 2X_DIELECTRIC * 0.152 MM ? 3X_DIELECTRIC * 0.228 MM ? 4X_DIELECTRIC * 0.304 MM ? 5X_DIELECTRIC * 0.380 MM ? TABLE_PHYSICAL_RULE_ITEM 40_OHM_SE * Y 0.145 MM 0.145 MM =STANDARD =STANDARD =STANDARD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM 27P4_OHM_SE TOP,BOTTOM Y 0.310 MM 0.310 MM 27P4_OHM_SE * Y 0.275 MM 0.275 MM TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM =STANDARD =STANDARD =STANDARD TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 70_OHM_DIFF * N =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD 70_OHM_DIFF ISL3,ISL4,ISL9,ISL10 Y 0.175 MM 0.175 MM 0.200 MM 0.200 MM 70_OHM_DIFF TOP,BOTTOM Y 0.185 MM 0.185 MM 0.200 MM 0.200 MM PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 90_OHM_DIFF * N =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD 90_OHM_DIFF ISL3,ISL4,ISL9,ISL10 Y 0.109 MM 0.109 MM 0.220 MM 0.220 MM 90_OHM_DIFF TOP,BOTTOM Y 0.112 MM 0.112 MM 0.220 MM 0.220 MM PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 100_OHM_DIFF * N =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD 100_OHM_DIFF ISL3,ISL4,ISL9,ISL10 Y 0.089 MM 0.089 MM 0.230 MM 0.230 MM 100_OHM_DIFF TOP,BOTTOM Y 0.091 MM 0.091 MM 0.230 MM 0.230 MM PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 100_OHM_DIFF_HDD * N =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD 100_OHM_DIFF_HDD ISL3,ISL4,ISL9,ISL10 Y 0.095 MM 0.095 MM 0.400 MM 0.400 MM 100_OHM_DIFF_HDD TOP,BOTTOM Y 0.095 MM 0.095 MM 0.400 MM 0.400 MM PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 110_OHM_DIFF * N =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD 110_OHM_DIFF ISL3,ISL4,ISL9,ISL10 Y 0.075 MM 0.075 MM 0.330 MM 0.330 MM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM C C TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD TABLE_PHYSICAL_RULE_ITEM B B TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM 110_OHM_DIFF TOP,BOTTOM Y 0.077 MM 0.077 MM PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH 1:1_DIFFPAIR * Y =STANDARD =STANDARD 0.330 MM 0.330 MM MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP =STANDARD 0.1 MM 0.1 MM TABLE_PHYSICAL_RULE_HEAD TABLE_PHYSICAL_RULE_ITEM K36B RULE DEFINITIONS A SYNC_MASTER=K36B_MLB SYNC_DATE=08/17/2008 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC SCALE SHT NONE REV 051-8089 02 OF 109 109 A ... TQFN 10K 5% 1/16W MF-LF 402 43 SPIROM_USE _MLB 10 SEL D+ D- C =PP3V3_S5_LPCPLUS R5140 100K 5% 1/16W MF-LF 402 OE* GND 43 SPIROM_USE _MLB =SPI_CS1_R_L_USE _MLB BI 21 MAKE_BASE=TRUE 43 =PP3V3_S5_LPCPLUS... PP1V05_S0 ADJ2 LTC2909 20 Power Block Diagram SYNC_MASTER=K36B _MLB THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING (23A... Speed) Speed) CONFIGURATION OPTIONS Speed) Speed) SYNC_MASTER=K36B _MLB THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO