apple macbook k78 mlb 051 8871 r250

8 ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5% ALL CAPACITANCE VALUES ARE IN MICROFARADS ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ REV ECN DESCRIPTION OF REVISION CK APPD DATE 2011-04-08 K78 MLB SCHEMATIC 04/08/11 D (.csa) Date Page TABLE_TABLEOFCONTENTS_HEAD Contents 1 MASTER Table of Contents TABLE_TABLEOFCONTENTS_ITEM System Block Diagram 11/16/2010 K78 BOM Variants 10 TABLE_TABLEOFCONTENTS_ITEM CPU CLOCK/MISC/JTAG K21_MLB CPU DDR3 INTERFACES K21_MLB TABLE_TABLEOFCONTENTS_ITEM 12 12/13/2010 CPU POWER 13 14 CPU DECOUPLING-I TABLE_TABLEOFCONTENTS_ITEM K21_MLB PBus Supply & Battery Charger K21_MLB System Agent Supply K21_MLB 5V / 3.3V Power Supply K21_MLB 1.5V DDR3 Supply K21_MLB CPU IMVP7 & AXG VCore Regulator K21_MLB CPU IMVP7 & AXG VCore Output K21_MLB CPU VCCIO (1.05V) Power Supply K21_MLB Misc Power Supplies K21_MLB Power FETs K21_MLB Power Control 1/ENABLE K21_MLB Internal DisplayPort Connector K21_MLB DisplayPort/T29 A MUXing K21_MLB DisplayPort/T29 A Connector K21_MLB LCD Backlight Driver K21_MLB CPU Constraints CONSTRAINTS Memory Constraints CONSTRAINTS PCH Constraints CONSTRAINTS PCH Constraints CONSTRAINTS Ethernet/FW Constraints CONSTRAINTS T29 Constraints CONSTRAINTS SMC Constraints CONSTRAINTS Project Specific Constraints CONSTRAINTS PCB Rule Definitions CONSTRAINTS 11/11/2010 11/30/2010 12/13/2010 11/30/2010 12/13/2010 12/13/2010 12/13/2010 76 TABLE_TABLEOFCONTENTS_ITEM 12/13/2010 77 59 K21_MLB DC-In & Battery Connectors 12/13/2010 75 58 12/13/2010 TABLE_TABLEOFCONTENTS_ITEM 12/13/2010 TABLE_TABLEOFCONTENTS_ITEM 17 15 12/13/2010 CPU DECOUPLING-II 78 60 K21_MLB TABLE_TABLEOFCONTENTS_ITEM 12/13/2010 TABLE_TABLEOFCONTENTS_ITEM 18 16 12/13/2010 PCH SATA/PCIE/CLK/LPC/SPI 79 61 K21_MLB TABLE_TABLEOFCONTENTS_ITEM 12/13/2010 C TABLE_TABLEOFCONTENTS_ITEM 19 17 TABLE_TABLEOFCONTENTS_ITEM 12/13/2010 PCH DMI/FDI/GRAPHICS K21_MLB PCH PCI/FLASHCACHE/USB K21_MLB TABLE_TABLEOFCONTENTS_ITEM PCH MISC K21_MLB 12/13/2010 12/13/2010 20 12/13/2010 PCH POWER 21 22 PCH DECOUPLING TABLE_TABLEOFCONTENTS_ITEM 23 24 TABLE_TABLEOFCONTENTS_ITEM USB HUBS K21_MLB Clock (CK505) and Chipset Support K21_MLB TABLE_TABLEOFCONTENTS_ITEM 26 12/13/2010 CPU Memory S3 Support 27 28 29 30 TABLE_TABLEOFCONTENTS_ITEM DDR3 DRAM CHANNEL B (32-63) K21_MLB FSB/DDR3/FRAMEBUF Vref Margining TABLE_TABLEOFCONTENTS_ITEM K21_MLB DDR3 DRAM Channel B (32-63) K21_MLB TABLE_TABLEOFCONTENTS_ITEM 33 T29 Host (1 of 2) K21_MLB 34 T29 Host (2 of 2) K21_MLB T29 Power Support K21_MLB 35 X21 WIRELESS CONNECTOR K21_MLB SATA CONNECTOR K21_MLB External USB Connectors K21_MLB LIO CONNECTORS N/A SMC K21_MLB SMC Support K21_MLB LPC+SPI Debug Connector K21_MLB SMBus Connections K21_MLB Voltage & Load Side Current Sensing K21_MLB High Side Current Sensing K21_MLB 12/13/2010 40 36 B 12/13/2010 38 TABLE_TABLEOFCONTENTS_ITEM 04/06/2011 TABLE_TABLEOFCONTENTS_ITEM 12/13/2010 37 TABLE_TABLEOFCONTENTS_ITEM 04/06/2011 109 12/13/2010 36 TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM 12/13/2010 34 32 04/06/2011 108 74 12/13/2010 33 31 TABLE_TABLEOFCONTENTS_ITEM K21_MLB 32 04/06/2011 106 73 12/13/2010 DDR3 DRAM CHANNEL B (0-31) TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM K21_MLB 31 04/06/2011 105 72 12/13/2010 DDR3 DRAM CHANNEL A (32-63) TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM K21_MLB 30 04/06/2011 104 71 12/13/2010 DDR3 DRAM CHANNEL A (0-31) TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM K21_MLB 29 04/06/2011 103 70 28 TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM 69 11/30/2010 04/06/2011 102 68 12/13/2010 27 25 TABLE_TABLEOFCONTENTS_ITEM K21_MLB 26 04/06/2011 101 67 12/13/2010 CPU & PCH XDP TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM K21_MLB 25 12/13/2010 100 66 12/13/2010 12/13/2010 97 TABLE_TABLEOFCONTENTS_ITEM K21_MLB 24 12/13/2010 94 TABLE_TABLEOFCONTENTS_ITEM 65 12/13/2010 PCH GROUNDS TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM K21_MLB 23 12/13/2010 93 64 22 TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM 63 21 19 TABLE_TABLEOFCONTENTS_ITEM 90 62 20 18 B TABLE_TABLEOFCONTENTS_ITEM K21_MLB 16 K21_MLB 74 57 12/13/2010 CPU GROUNDS TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM K21_MLB 14 AUDI0: SPEAKER AMP 12/13/2010 73 56 13 TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM 55 12/13/2010 K21_MLB 72 54 12/13/2010 12 11 TABLE_TABLEOFCONTENTS_ITEM K21_MLB 11 SPI ROM 12/13/2010 71 53 12/13/2010 CPU DMI/PEG/FDI/RSVD TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM K91_MLB 10 K21_MLB 70 52 05/15/2010 Signal Aliases TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM K91_MLB IPD / KBD Backlight 12/13/2010 69 51 05/15/2010 Power Aliases TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM (K99_MLB) K21_MLB 62 50 (02/16/2010) Functional Test / No Test TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM K21_MLB Fan 61 49 11/16/2010 BOM Configuration TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM K21_MLB K21_MLB 57 48 TABLE_TABLEOFCONTENTS_ITEM C TABLE_TABLEOFCONTENTS_ITEM Power Block Diagram TABLE_TABLEOFCONTENTS_ITEM 12/13/2010 Thermal Sensors 56 47 19/01/2011 Sync 55 TABLE_TABLEOFCONTENTS_ITEM K6_MLB 3 TABLE_TABLEOFCONTENTS_HEAD Contents 46 12/11/2009 D Date Page MASTER TABLE_TABLEOFCONTENTS_ITEM (.csa) Sync 12/13/2010 TABLE_TABLEOFCONTENTS_ITEM 45 37 12/13/2010 TABLE_TABLEOFCONTENTS_ITEM 46 38 12/13/2010 TABLE_TABLEOFCONTENTS_ITEM 47 39 TABLE_TABLEOFCONTENTS_ITEM N/A 49 40 TABLE_TABLEOFCONTENTS_ITEM 12/13/2010 50 41 TABLE_TABLEOFCONTENTS_ITEM 12/13/2010 51 42 TABLE_TABLEOFCONTENTS_ITEM 12/13/2010 52 43 TABLE_TABLEOFCONTENTS_ITEM 12/13/2010 53 44 TABLE_TABLEOFCONTENTS_ITEM 12/13/2010 54 45 12/13/2010 TABLE_TABLEOFCONTENTS_ITEM A A DRAWING TITLE SCHEM,MLB,K78 DRAWING NUMBER Schematic / PCB #’s PART NUMBER QTY Apple Inc DESCRIPTION REFERENCE DES CRITICAL 051-8871 SCHEM,MLB,K78 SCH CRITICAL 820-3024 PCBF,MLB,K78 PCB CRITICAL BOM OPTION PRODUCT SAFETY REQUIREMENTS: PCB, UL RECOGNIZED, MIN 130-C TEMP RATING AND V-0 FLAME RATING PER UL 796 & UL 94 PCB TO BE SILK-SCREENED WITH UL/CUL RECOGNITION MARK, MANUFACTURER’S UL FILE NUMBER, UL PCB MATERIAL DESIGNATION, 130-C TEMP RATING AND V-0 FLAME RATING DRAWING TITLE=MLB ABBREV=DRAWING LAST_MODIFIED=Fri Apr 10:21:51 2011 051-8871 REVISION R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED 2.5.0 BRANCH PAGE OF 109 SHEET OF 74 SIZE D 1G/2GB J2500 CPU XDP CONN JTAG U2900,U3030 PG 10 MEMORY U1000 PG 23 D DDR3-1066/1333MHZ D A 64-Bit INTEL CPU PG 27,38 1G/2GB J9000 INTERNAL DISPLAY CONN EDP PG 62 PG MEMORY SANDYBRIDGE SFF U7000 U3100,3230 1.6 GHZ MEMORY CHARGER DDR3-1066/1333MHZ B POWER CIRCUITRY 64-Bit PCIE FDI PG 52 DMI PG PG PG 52-60 PG 29,30 PG PG 11 TEMP SENSOR PG 46 RTC FDI DMI PG 16 PG 17 PG 17 VOLTAGE/CURRENT SENSOR GPIO U2700 PG 45 SYSTEM CLOCK U6100 PG 15 J5600 BOOTROM SPI CLOCK BUFFER PG 25 FAN CONN PG 16 PG 49 PG 47 PG16 MISC J4501 U4900 SSD CONN C SMB_BSA SATA SMB_B/0 ADC FAN0 PG 19 C J5100 PG 37 LPC+SPI CONN LPC PG 16 U1800 SERIAL PORT SMC PG 16 PG 42 EDP OUT PWR CTRL INTEL PCH PM_SLP S3/S4 HDMI OUT PG 40 SMB_A U2600 COUGAR POINT DVI OUT USB HUB-1 PCIE U3600 LID PG 17 RGB OUT TMDS OUT LVDS OUT T29 ROUTER PG 24 J6955 HALL EFFECT PG 34,35 J5700 PG 64 DP OUT USB PG 17 USB HUB-2 PG 48 PG 63 J4600 RIGHT EXT USB CONN PG 24 10 11 JTAG J4610 PG 16 PG 18 PCIE J4001 PCI PCIE X21 WIRELESS CONN PG 36 13 PG 23 B PG 38 12 PCH XDP CONN PG 51 IPD FLEX CONN U2650 DP MUX DISPLAY PORT+ T29 CONN U9390 J9400 PG 16 SMB PG 18 HDA PG 16 B PG 16 USB U6210 J4700 USB CAM HDA USB EXT SPEAKER AMP SPK LEFT I/O CONN PG 50 J6903 RIGHT SPEAKER CONN PG 51 I2C PG 39 J4702 U6201 AUDIO CODEC J4610 CAMERA+ALS CONN LEFT EXT USB CONN PG PG PG LIO BOARD U6620 A SPEAKER AMP LINE IN FILTER HEADPHONE FILTER PG PG 11 PG SYNC_MASTER=K6_MLB SYNC_DATE=12/11/2009 PAGE TITLE System Block Diagram DRAWING NUMBER J6702 Apple Inc J6700 LEFT SPEAKER CONN HEADPHONE/ LINE IN JACK PG 10 PG 10 R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED 051-8871 REVISION 2.5.0 BRANCH PAGE OF 109 SHEET OF 74 SIZE D A D6905 PPDCIN_G3H_OR_PBUS ENABLE 3.425V G3HOT PPVIN_G3H_P3V42G3H R6905 PP3V42_G3H_REG LT3470A (PAGE 52) J6900 D AC DCIN(14.5V) A ADAPTER U7000 EN 21 PPVBAT_G3H VIN (PAGE 59) PBUS SUPPLY/ BATTERY CHARGER R7050 R5320 SMC_CPU_VSENSE V VIN A 24 SMC_RESET_L SMC_BATT_ISENSE PP1V05_T29_FET V U7400 VR_ON R5330 SMC_GFX_VSENSE PPVCORE_S0_AXG_REG VOUT Q7055 PPVBAT_G3H_CHGR_R (PAGE 57) CPUIMVP_AXG_PGOOD PGOODG VIN S5 0.75V TPS51916 U7300 SMC RSMRST# PM_RSMRST_L PPDDR_S3_REG 16 27 RC P60 P3V3S5_EN U2850 (PAGE 17~21) 30 P1V5CPU_EN PP1V5_S3RS0_FET DELAY SMC_PM_G2_EN PP5V_S0_VCCSA 22 PVCCSA_EN VCC ISL95870A U7100 EN (PAGE 54) CPU_VCCSA_VID VID1 R7140 VOUT PPVCCSA_S0_REG SM_DRAMPWROK A PGOOD 23 CPU U1000 PM_SLP_S5_L PG 17 11 PM_SLP_SUS_L SLP_SUS# U7940 P5V_3V3_SUS_EN RC P3V3S3_EN PG62 DELAY RC DDRREG_EN PG62 10-1 P5VS3_EN 13-1 PG61 EN1 14 VIN 5V VOUT1 (R/H) 15 B 13-2 14-1 PP3V3_SUS_FET Q9706 PM_SLP_S4_L PG 17 13 SLP_S3#(F4) ALL_SYS_PWRGD (PAGE 60) Q7820 R7962 PP3V3_S3_FET 14-1 SMC_ONOFF_L PWR_BUTTON(P90) IMVP_VR_ON(P16) ISL88042IRTEZ V3MON P3V3S3_EN PP1V05_S0_VMON SYSRST(PA2) P17(BTN_OUT) VOUT PP5V_SUS_FET (PAGE 66) 26 CPUIMVP_VR_ON PM_SYSRST_L 6-1 V4MON PPVOUT_SW_LCDBKLT EN B PM_RSMRST_L 99ms DLY U7960 V2MON 10 12 RSMRST_IN(P13) RSMRST_OUT(P15) VDD PP5V_S0_VMON PP1V5_S3RS0_VMON U9701 S5_PWRGD PM_DSW_PWRGD PWRGD(P12) Q7810 VIN LP8550 P15 25 PP3V3_S0_VMON LCD_BKLT_EN PPBUS_SW_LCDBKLT_PWR PM_PWRBTN_L (PAGE 62) 10-2 PM_SLP_S5_L SLP_S5_L(P95) SMC_RESET_L PM_SLP_S4_L Q7840 R7978 SMC PVCCSA_PGOOD P5V_3V3_SUS_EN 14 (PAGE 17~21) 10-4 TPS720105 U7740 && BKLT_PLT_RST_L PM_SLP_S3_L PG 17 CPUVCCIOS0_PGOOD PP1V05_SUS_LDO F9700 P3V3S5_PGOOD SLP_S4#(H4) P3V3S5_PGOOD 10-3 P5VS3_PGOOD PG62 P1V8S0_PGOOD P5VS3_PGOOD P5VS0_EN TPS51980 U7201 (PAGE 55) PGOOD RESET* CPUIMVP_AXG_PGOOD 15 PP3V3_S5 VOUT2 EN2 (PAGE 9~15) 23-1 PP5V_S0_FET PP3V3_S5_REG 3.3V P3V3S5_EN 13 U1800 PVCCSA_PGOOD Q7860 PP5V_S3_REG (L/H) DELAY P5VS3_EN UNCOREPWRGOOD PPVIN_S5_P5VP3V3 SLP_S5#(E4) (PCH) C PM_MEM_PWRGD DRAMPWROK U7801 DDRREG_PGOOD (PAGE 41) COUGAR-POINT 28 PROCPWRGD (PAGE 56) U4900 29 PLTRST# CPU_PWRGD 16-1 PGOOD PM_DSW_PWRGD PLT_RERST_L PM_PCH_PWRGD PPVTT_S0_DDR_LDO VOUT2 C PM_SYSRST_L U1800 DPWROK A VOUT1 S3 PM_PWRBTN_L SYS_RERST# R7350 VLDOIN 1.5V DDRVTT_EN COUGAR-POINT (PCH) PWRBTN# 26-1 CHGR_BGATE DDRREG_EN 26 25-1 CPUIMVP_PGOOD PGOOD K78/K21 POWER SYSTEM ARCHITECTURE T29_PWR_EN CPU VCORE MAX15092GTL (PAGE 53) PPVBATT_G3H_CONN 25 PPVCORE_S0_CPU_REG VOUT CPUIMVP_VR_ON 2S3P U3816/U3815 EN SMC_DCIN_ISENSE (6 TO 8.4V) TPS22924 22-1 CPUVCCIOS0_PGOOD PGOOD (PAGE 36) ISL6259HRTZ J6950 D SMC_CPU_FSB_ISENSE VOUT IN CPUVCCIOS0_EN ISL95870 U7600 22 PPCPUVCCIO_S0_REG A 1.05VVOUT VCC A R7020 SMC_RESET_L R7640 VIN PP5V_S0_CPUVCCIOS0 PPBUS_G3H F6905 6A FUSE 15 R5400 F7040 SMC POWER SN0903048 U5010 (PAGE 42) U6990 R6920 RES* SLP_S4_L(P94) PG62 PM_SLP_S3_L P5V_3V3_SUS_EN 16 PP3V3_S0 Q5300 SLP_S3_L(P93) P1V8S0_PGOOD U4900 (PAGE 41) SMC_PBUS_VSENSE PM_SLP_S3_R_L ISL8014A P1V8_S0_EN EN 17 PBUSVSENS_EN RC A CPUVCCIOS0_EN DELAY RC PVCCSA_EN 21 21 22 P1V5S0_EN 19 DELAY RC P1V8S0_EN DELAY SYNC_DATE=19/01/2011 18 19 TPS720105 1V05_S0_LDO_EN EN P5VS0_EN P3V3S0_EN DELAY RC PP1V8_S0_REG Q3880 14-1 U7770 T29_A_HV_EN PBUSVSENS_EN 14-1 17 PP1V05_S0_LDO U7780 (PAGE 60) 14-1 T29BST_EN_UVLO TPS72015 EN/UVLO 1V05_S0_LDO_EN U7720 (PAGE 60) VIN LT3957 Q7830 TPS22924 T29_PWR_EN U3890 EN VOUT PP15V_T29_REG (PAGE 36) P3V3S0_EN PP1V5_S0_REG A PAGE TITLE Power Block Diagram (PAGE 60) EN U3810 DRAWING NUMBER Apple Inc PP3V3_T29_FET R (PAGE 36) 14 PP1V5S0_EN NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED 051-8871 REVISION 2.5.0 BRANCH PAGE OF 109 SHEET OF 74 SIZE D BOM Variants Bar Code Labels / EEEE #’s TABLE_BOMGROUP_HEAD BOM NUMBER BOM NAME BOM OPTIONS 639-1808 PCBA,MLB,K78 K78_CMNPTS,CPU:1.6GHZ,EEEE:DK9L,DDR3:HYNIX_2GB 639-1989 PCBA,MLB,1.6GHZ,HY 4GB,K78 K78_CMNPTS,CPU:1.6GHZ,EEEE:DLCR,DDR3:HYNIX_4GB PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION TABLE_BOMGROUP_ITEM 825-7563 LABEL,LIO,K99 [EEEE_DK9L] CRITICAL EEEE:DK9L 825-7563 LABEL,LIO,K99 [EEEE_DLCL] CRITICAL EEEE:DLCL 825-7563 LABEL,LIO,K99 [EEEE_DLCM] CRITICAL EEEE:DLCM 825-7563 LABEL,LIO,K99 [EEEE_DLCN] CRITICAL EEEE:DLCN 825-7563 LABEL,LIO,K99 [EEEE_DLCP] CRITICAL EEEE:DLCP 825-7563 LABEL,LIO,K99 [EEEE_DLCQ] CRITICAL EEEE:DLCQ 825-7563 LABEL,LIO,K99 [EEEE_DLCR] CRITICAL EEEE:DLCR 825-7563 LABEL,LIO,K99 [EEEE_DLCT] CRITICAL EEEE:DLCT 825-7563 LABEL,LIO,K99 [EEEE_DLCV] CRITICAL EEEE:DLCV 825-7563 LABEL,LIO,K99 [EEEE_DLCW] CRITICAL EEEE:DLCW 825-7563 LABEL,LIO,K99 [EEEE_DLCY] CRITICAL EEEE:DLCY 825-7563 LABEL,LIO,K99 [EEEE_DLD0] CRITICAL EEEE:DLD0 825-7563 LABEL,LIO,K99 [EEEE_DLD1] CRITICAL EEEE:DLD1 825-7563 LABEL,LIO,K99 [EEEE_DLD2] CRITICAL EEEE:DLD2 825-7563 LABEL,LIO,K99 [EEEE_DLD3] CRITICAL EEEE:DLD3 825-7563 LABEL,LIO,K99 [EEEE_DLD4] CRITICAL EEEE:DLD4 825-7563 LABEL,LIO,K99 [EEEE_DLD5] CRITICAL EEEE:DLD5 825-7563 LABEL,LIO,K99 [EEEE_DLD6] CRITICAL EEEE:DLD6 TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM 639-1990 PCBA,MLB,1.6GHZ,SA 2GB,K78 K78_CMNPTS,CPU:1.6GHZ,EEEE:DLCT,DDR3:SAMSUNG_2GB 639-1999 PCBA,MLB,1.6GHZ,SA 4GB,K78 K78_CMNPTS,CPU:1.6GHZ,EEEE:DLD6,DDR3:SAMSUNG_4GB 639-1987 PCBA,MLB,1.6GHZ,MI 2GB,K78 K78_CMNPTS,CPU:1.6GHZ,EEEE:DLCP,DDR3:MICRON_2GB 639-1995 PCBA,MLB,1.6GHZ,EL 4GB,K78 K78_CMNPTS,CPU:1.6GHZ,EEEE:DLD1,DDR3:ELPIDA_4GB 639-1998 PCBA,MLB,1.5GHZ,HY 2GB,K78 K78_CMNPTS,CPU:1.5GHZ,EEEE:DLD4,DDR3:HYNIX_2GB 639-1991 PCBA,MLB,1.5GHZ,HY 4GB,K78 K78_CMNPTS,CPU:1.5GHZ,EEEE:DLCV,DDR3:HYNIX_4GB 639-1986 PCBA,MLB,1.5GHZ,SA 2GB,K78 K78_CMNPTS,CPU:1.5GHZ,EEEE:DLCN,DDR3:SAMSUNG_2GB TABLE_BOMGROUP_ITEM D D TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM 639-1985 PCBA,MLB,1.5GHZ,SA 4GB,K78 K78_CMNPTS,CPU:1.5GHZ,EEEE:DLCM,DDR3:SAMSUNG_4GB 639-1992 PCBA,MLB,1.5GHZ,MI 2GB,K78 K78_CMNPTS,CPU:1.5GHZ,EEEE:DLCW,DDR3:MICRON_2GB 639-1993 PCBA,MLB,1.5GHZ,EL 4GB,K78 K78_CMNPTS,CPU:1.5GHZ,EEEE:DLCY,DDR3:ELPIDA_4GB 639-1994 PCBA,MLB,1.4GHZ,HY 2GB,K78 K78_CMNPTS,CPU:1.4GHZ,EEEE:DLD0,DDR3:HYNIX_2GB 639-1988 PCBA,MLB,1.4GHZ,HY 4GB,K78 K78_CMNPTS,CPU:1.4GHZ,EEEE:DLCQ,DDR3:HYNIX_4GB TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM 639-1997 PCBA,MLB,1.4GHZ,SA 2GB,K78 K78_CMNPTS,CPU:1.4GHZ,EEEE:DLD3,DDR3:SAMSUNG_2GB 639-1984 PCBA,MLB,1.4GHZ,SA 4GB,K78 K78_CMNPTS,CPU:1.4GHZ,EEEE:DLCL,DDR3:SAMSUNG_4GB 639-2000 PCBA,MLB,1.4GHZ,MI 2GB,K78 K78_CMNPTS,CPU:1.4GHZ,EEEE:DLD5,DDR3:MICRON_2GB 639-1996 PCBA,MLB,1.4GHZ,EL 4GB,K78 K78_CMNPTS,CPU:1.4GHZ,EEEE:DLD2,DDR3:ELPIDA_4GB 085-2714 K78 MLB DEVELOPMENT BOM K78_DEVEL:ENG 607-8084 CMN PTS,PCBA,MLB,K78 K78_COMMON TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM C C B B A SYNC_MASTER=K21_MLB SYNC_DATE=11/16/2010 PAGE TITLE K78 BOM Variants Sub-BOMs PART NUMBER 085-2714 QTY DESCRIPTION REFERENCE DES K78 MLB DEVELOPMENT BOM DEVEL CRITICAL CRITICAL DRAWING NUMBER BOM OPTION Apple Inc DEVEL_BOM 051-8871 REVISION R 607-8084 CMNPTS CMN PTS,PCBA,MLB,K78 CRITICAL K78_CMNPTS NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED 2.5.0 BRANCH PAGE OF 109 SHEET OF 74 SIZE D A Module Parts K78 BOM GROUPS TABLE_BOMGROUP_HEAD PART NUMBER BOM GROUP BOM OPTIONS K78_COMMON ALTERNATE,COMMON,K78_MISC,K78_DEBUG:ENG,K78_PROGPARTS,USBHUB_2513B,T29BST:Y,EDP DESCRIPTION REFERENCE DES 337S4101 QTY SNB,QAM1,QS,J1,1.6,17W,2+2,1.1,4M,BGA U1000 CRITICAL CRITICAL BOM OPTION CPU:1.6GHZ 337S4100 SNB,QAM2,QS,J1,1.5,17W,2+2,1.1,4M,BGA U1000 CRITICAL CPU:1.5GHZ 337S4099 SNB,QAM3,QS,J1,1.4,17W,2+2,1.05,3M,BGA U1000 CRITICAL CPU:1.4GHZ 337S4098 SNB,QALV,QS,J1,1.3,17W,2+2,1.05,3M,BGA U1000 CRITICAL CPU:1.3GHZ 337S4080 COUGAR POINT,SLHAG,PRQ,BD82QS67 U1800 CRITICAL PCH:B2 337S4091 COUGAR POINT,B3,SLJ4K,PRQ,BD82QS67 U1800 CRITICAL PCH:B3 338S0976 IC,T29, FCBGA,PRQ 8x9MM U3600 CRITICAL T29:YES 333S0585 IC,SDRAM,1GBIT,DDR3-1333,78P FBGA,T-DIE,HYNIX U2900,U2910,U2920,U2930 CRITICAL DRAM_TYPE:HYNIX_2GB 333S0585 IC,SDRAM,1GBIT,DDR3-1333,78P FBGA,T-DIE,HYNIX U3000,U3010,U3020,U3030 CRITICAL DRAM_TYPE:HYNIX_2GB 333S0585 IC,SDRAM,1GBIT,DDR3-1333,78P FGBA,T-DIE,HYNIX U3100,U3110,U3120,U3130 CRITICAL DRAM_TYPE:HYNIX_2GB 333S0585 IC,SDRAM,1GBIT,DDR3-1333,78P FBGA,T-DIE,HYNIX U3200,U3210,U3220,U3230 CRITICAL DRAM_TYPE:HYNIX_2GB 333S0586 IC,SDRAM,2GBIT,DDR3-1333,78P FBGA,B-DIE,HYNIX U2900,U2910,U2920,U2930 CRITICAL DRAM_TYPE:HYNIX_4GB 333S0586 IC,SDRAM,2GBIT,DDR3-1333,78P FBGA,B-DIE,HYNIX U3000,U3010,U3020,U3030 CRITICAL DRAM_TYPE:HYNIX_4GB 333S0586 IC,SDRAM,2GBIT,DDR3-1333,78P FGBA,B-DIE,HYNIX U3100,U3110,U3120,U3130 CRITICAL DRAM_TYPE:HYNIX_4GB 333S0586 IC,SDRAM,2GBIT,DDR3-1333,78P FBGA,B-DIE,HYNIX U3200,U3210,U3220,U3230 CRITICAL DRAM_TYPE:HYNIX_4GB 333S0587 IC,SDRAM,1GBIT,DDR3-1333,78P FBGA,G-DIE,SAMSUNG U2900,U2910,U2920,U2930 CRITICAL DRAM_TYPE:SAMSUNG_2GB TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM K78_MISC PCH:B3,CPUMEM_S0,HUB1_2NONREM,HUB2_2NONREM,T29:YES,SDRVI2C:MCU,SDRV_PD,KB_BL K78_PROGPARTS BOOTROM_PROG,SMC_PROG,T29ROM:PROG,T29MCU:PROG TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM K78_DEVEL:ENG BKLT:ENG,BMON:ENG,XDP_CONN,XDP_CPU:BPM,XDP_PCH,LPCPLUS,VREFMRGN,S0PGOOD_ISL,S3_S0_LED,VCCIOISNS_ENG,AIRPORTISNS_ENG,HDDISNS_ENG,LCDBKLTISNS_ENG K78_DEVEL:PVT LPCPLUS,XDP_CONN,XDP_PCH TABLE_BOMGROUP_ITEM D TABLE_BOMGROUP_ITEM D K78_DEBUG:ENG DEVEL_BOM,SMC_DEBUG_YES,XDP K78_DEBUG:PVT DEVEL_BOM,BKLT:PROD,BMON:PROD,SMC_DEBUG_YES,XDP,VREFMRGN_NOT TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM K78_DEBUG:PROD BKLT:PROD,BMON:PROD,SMC_DEBUG_YES,XDP,VREFMRGN_NOT,LPCPLUS,VCCIOISNS_PROD,AIRPORTISNS_PROD,HDDISNS_PROD,LCDBKLTISNS_PROD DDR3:HYNIX_2GB DRAM_CFG0:L,DRAM_CFG1:L,DRAM_CFG2:L,DRAM_CFG3:L,DRAM_TYPE:HYNIX_2GB DDR3:HYNIX_4GB DRAM_CFG0:L,DRAM_CFG1:L,DRAM_CFG2:H,DRAM_CFG3:L,DRAM_TYPE:HYNIX_4GB DDR3:SAMSUNG_2GB DRAM_CFG0:L,DRAM_CFG1:H,DRAM_CFG2:L,DRAM_CFG3:L,DRAM_TYPE:SAMSUNG_2GB DDR3:SAMSUNG_4GB DRAM_CFG0:L,DRAM_CFG1:H,DRAM_CFG2:H,DRAM_CFG3:L,DRAM_TYPE:SAMSUNG_4GB DDR3:MICRON_2GB DRAM_CFG0:H,DRAM_CFG1:L,DRAM_CFG2:L,DRAM_CFG3:L,DRAM_TYPE:MICRON_2GB DDR3:ELPIDA_4GB DRAM_CFG0:H,DRAM_CFG1:H,DRAM_CFG2:H,DRAM_CFG3:L,DRAM_TYPE:ELPIDA_4GB TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM Programmable Parts 333S0587 IC,SDRAM,1GBIT,DDR3-1333,78P FBGA,G-DIE,SAMSUNG U3000,U3010,U3020,U3030 CRITICAL DRAM_TYPE:SAMSUNG_2GB 335S0550 EEPROM,32KBIT,2X3QFN U3690 CRITICAL T29ROM:BLANK 333S0587 IC,SDRAM,1GBIT,DDR3-1333,78P FGBA,G-DIE,SAMSUNG U3100,U3110,U3120,U3130 CRITICAL DRAM_TYPE:SAMSUNG_2GB 341T0354 IC,T29-ROM,K78 U3690 CRITICAL T29ROM:PROG 333S0587 IC,SDRAM,1GBIT,DDR3-1333,78P FBGA,G-DIE,SAMSUNG U3200,U3210,U3220,U3230 CRITICAL DRAM_TYPE:SAMSUNG_2GB 337S3997 IC,MCU,32B,LPC1112A,16KB/2KB,HVQFN25 U9330 CRITICAL T29MCU:BLANK 333S0588 IC,SDRAM,2GBIT,DDR3-1333,78P FBGA,D-DIE,SAMSUNG U2900,U2910,U2920,U2930 CRITICAL DRAM_TYPE:SAMSUNG_4GB 341T0355 IC,T29-MCU,K78 U9330 CRITICAL T29MCU:PROG 333S0588 IC,SDRAM,2GBIT,DDR3-1333,78P FBGA,D-DIE,SAMSUNG U3000,U3010,U3020,U3030 CRITICAL DRAM_TYPE:SAMSUNG_4GB 338S0895 IC,SMC,RENESAS,H8S/2117RP,9MM,TLP,HF U4900 CRITICAL SMC_BLANK 333S0588 IC,SDRAM,2GBIT,DDR3-1333,78P FGBA,D-DIE,SAMSUNG U3100,U3110,U3120,U3130 CRITICAL DRAM_TYPE:SAMSUNG_4GB 341T0350 IC,SMC,K78 U4900 CRITICAL SMC_PROG 333S0588 IC,SDRAM,2GBIT,DDR3-1333,78P FBGA,D-DIE,SAMSUNG U3200,U3210,U3220,U3230 CRITICAL DRAM_TYPE:SAMSUNG_4GB 335S0809 64 MBIT SPI SERIAL DUAL I/O FLASH,8X6X0.8 U6100 CRITICAL BOOTROM_BLANK 333S0590 IC,SDRAM,1GBIT,DDR3-1333,78P FBGA,V68A-D,MICRON U2900,U2910,U2920,U2930 CRITICAL DRAM_TYPE:MICRON_2GB 335S0803 64 MBIT SPI SERIAL DUAL I/O FLASH,8X6X0.8 U6100 CRITICAL BOOTROM_BLANK 333S0590 IC,SDRAM,1GBIT,DDR3-1333,78P FBGA,V68A-D,MICRON U3000,U3010,U3020,U3030 CRITICAL DRAM_TYPE:MICRON_2GB 341T0349 IC,EFI ROM,K21 K78 U6100 CRITICAL BOOTROM_PROG 333S0590 IC,SDRAM,1GBIT,DDR3-1333,78P FGBA,V68A-D,MICRON U3100,U3110,U3120,U3130 CRITICAL DRAM_TYPE:MICRON_2GB 333S0590 IC,SDRAM,1GBIT,DDR3-1333,78P FBGA,V68A-D,MICRON U3200,U3210,U3220,U3230 CRITICAL DRAM_TYPE:MICRON_2GB 333S0589 IC,SDRAM,2GBIT,DDR3-1333,78P FBGA,C-DIE,ELPIDA U2900,U2910,U2920,U2930 CRITICAL DRAM_TYPE:ELPIDA_4GB 333S0589 IC,SDRAM,2GBIT,DDR3-1333,78P FBGA,C-DIE,ELPIDA U3000,U3010,U3020,U3030 CRITICAL DRAM_TYPE:ELPIDA_4GB 333S0589 IC,SDRAM,2GBIT,DDR3-1333,78P FGBA,C-DIE,ELPIDA U3100,U3110,U3120,U3130 CRITICAL DRAM_TYPE:ELPIDA_4GB 333S0589 IC,SDRAM,2GBIT,DDR3-1333,78P FBGA,C-DIE,ELPIDA U3200,U3210,U3220,U3230 CRITICAL DRAM_TYPE:ELPIDA_4GB 607-6811 ASSEMBLY,SUBASSY,PCBA,HALL EFFECT,K99 J6955 CRITICAL 353S2929 IC,ISL6259,BATCHARGER,3%,4C4MM,QFN28 U7000 CRITICAL PART NUMBER C QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION Alternate Parts TABLE_ALT_HEAD PART NUMBER ALTERNATE FOR PART NUMBER BOM OPTION REF DES C COMMENTS: TABLE_ALT_ITEM 376S0855 376S0613 ALL Diodes alt to Toshiba 376S0977 376S0859 ALL Diodes alt to Toshiba 376S0972 376S0612 ALL Rohm alt to Toshiba 377S0107 377S0066 ALL ONsemi alt to Semtech 138S0676 138S0691 ALL Murata alt to Samsung 371S0679 371S0652 ALL NXP alt to NXP 138S0671 138S0673 ALL Taiyo alt to Murata TABLE_ALT_ITEM TABLE_ALT_ITEM TABLE_ALT_ITEM TABLE_ALT_ITEM TABLE_ALT_ITEM B B TABLE_ALT_ITEM TABLE_ALT_ITEM 138S0679 138S0678 ALL Murata/Samsung alt to Taiyo 353S3312 353S3055 ALL NXP ALT TO PERICOM 104S0035 104S0011 ALL Panasonic alt to Cyntec 152S1085 152S1307 ALL Toko alt to Cyntec 152S1462 152S1295 ALL Toko alt to NEC inductor 128S0333 128S0294 ALL Sanyo alt to Sanyo/Frederick TABLE_ALT_ITEM TABLE_ALT_ITEM TABLE_ALT_ITEM TABLE_ALT_ITEM TABLE_ALT_ITEM TABLE_ALT_ITEM 337S4092 337S4100 ALL EARLY 1.5GHZ CPU SAMPLES 337S4093 337S4101 ALL EARLY 1.4GHZ CPU SAMPLES 376S0874 376S0895 ALL FDMC0202S alt to RJK03E0DNS 376S1018 376S0617 ALL FDMS0349 alt to RJK0305DPB 376S0826 376S0917 ALL RJK0332DPB alt to FDMS0355 514-0744 998-3941 ALL mDP connector alt DRAM CFG CHART TABLE_ALT_ITEM TABLE_ALT_ITEM VENDOR TABLE_ALT_ITEM CFG CFG TABLE_ALT_ITEM HYNIX 0 MICRON ELPIDA 1 TABLE_ALT_ITEM SAMSUNG A SYNC_MASTER=K21_MLB SIZE CFG DIE REV SYNC_DATE=11/16/2010 PAGE TITLE CFG BOM Configuration DRAWING NUMBER 2GB A Apple Inc 4GB B 051-8871 REVISION R 2.5.0 NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED BRANCH PAGE OF 109 SHEET OF 74 SIZE D A Functional Test Points J4001: AirPort / BT Connector FUNC_TEST PP3V3_WLAN_F (Need TPs) WIFI_EVENT_L PCIE_AP_R2D_N PCIE_AP_R2D_P PCIE_CLK100M_AP_N PCIE_CLK100M_AP_P USB_BT_P USB_BT_N PCIE_AP_D2R_P PCIE_AP_D2R_N PCIE_WAKE_L AP_RESET_CONN_L AP_CLKREQ_Q_L =PP3V3_S3_BT TRUE TRUE TRUE TRUE TRUE TRUE D NC_EDP_TXP MAKE_BASE=TRUE NC_EDP_TXN MAKE_BASE=TRUE NC_EDP_AUXP MAKE_BASE=TRUE NC_EDP_AUXN J5600: Fan Connector FUNC_TEST TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE 36 TRUE 36 40 TRUE 36 69 TRUE =PP5V_S0_FAN FAN_RT_TACH FAN_RT_PWM TRUE TRUE TRUE TRUE TRUE TP_EDP_AUX_P TRUE TP_EDP_AUX_N TRUE NC_CPU_THERMDC TP_CPU_THERMDA TP_CPU_THERMDC TRUE NC_CPU_RSVD TRUE TP_CPU_RSVD TRUE TP_CPU_RSVD MAKE_BASE=TRUE 24 36 68 FUNC_TEST TRUE 24 36 68 TRUE 16 36 69 TRUE 16 36 69 TRUE 17 36 TRUE 36 TRUE 36 TRUE TRUE 36 TRUE TRUE (Need TPs) PP3V3_S0_HDD_R 37 SATA_HDD_D2R_C_P 37 SATA_HDD_D2R_C_N 37 SATA_HDD_R2D_N 37 SATA_HDD_R2D_P 37 SMC_HDD_OOB_TEMP_CONN 37 SMC_HDD_TEMP_CTL_CONN 37 TRUE TP_EDP_TX_N MAKE_BASE=TRUE J5700: IPD Flex Connector J4501: SATA SSD Connector TRUE TP_EDP_TX_P TRUE MAKE_BASE=TRUE NC_CPU_THERMDA 47 16 36 69 TRUE TRUE TRUE MAKE_BASE=TRUE 16 36 69 (Need to add GND TPs) FUNC_TEST 47 47 (Need to add GND TP) 36 69 SMC_PME_S4_WAKE_L PP5V_TPAD_FILT =PP3V42_G3H_TPAD PP3V3_TPAD_CONN USB_TPAD_CONN_P USB_TPAD_CONN_N =I2C_TPAD_SDA =I2C_TPAD_SCL SMC_ONOFF_L SMC_LID SMC_TPAD_RST_L NC_CPU_RSVD 40 41 48 48 TRUE NC_PEG_R2D_CP 48 =PEG_R2D_C_P =PEG_R2D_C_N TRUE =PEG_D2R_P TRUE =PEG_D2R_N MAKE_BASE=TRUE 48 73 TRUE NC_PEG_R2D_CN MAKE_BASE=TRUE 48 73 NC_PEG_D2RP 43 48 MAKE_BASE=TRUE 43 48 NC_PEG_D2RN MAKE_BASE=TRUE 40 41 48 40 41 48 51 41 48 (Need to add GND TPs) J6900: DC-In Connector 68 68 FUNC_TEST 68 TRUE 68 TRUE =PP18V5_DCIN_CONN =PP5V_S3_LIO_CONN (Need TPs) (Need TPs) 51 51 NO_TEST Nets TP_PCIE_CLK100M_PE4N TP_PCIE_CLK100M_PE4P (Need to add GND TPs) J6903: Speaker Connector (Need to add GND TPs) 16 TP_PCIE_CLK100M_PE5N 16 TP_PCIE_CLK100M_PE5P 16 TP_PCIE_CLK100M_PE6N 16 TP_PCIE_CLK100M_PE6P 16 TP_PCIE_CLK100M_PE7N 16 TP_PCIE_CLK100M_PE7P FUNC_TEST J4700: LIO Connector TRUE FUNC_TEST TRUE TRUE TRUE C TRUE TRUE TRUE TRUE =PP3V42_G3H_ONEWIRE =PP3V3_S0_AUDIO =PP3V3R1V5_S0_AUDIO SYS_ONEWIRE SMC_BC_ACOK =USB_PWR_EN TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE 50 51 73 NO_TEST 39 J6950: Battery Connector 39 TP_CRT_IG_GREEN TP_CRT_IG_RED 17 TRUE 39 40 41 TRUE 38 39 61 TRUE 39 43 PPVBAT_G3H_CONN =SMBUS_BATT_SCL =SMBUS_BATT_SDA SYS_DETECT_L 51 52 (Need TPs) 39 43 TP_CRT_IG_DDC_CLK 17 43 51 TP_PSOC_P1_3 NC_CRT_IG_GREEN 16 TP_SATA_B_D2RN 16 TP_SATA_B_D2RP 16 TP_SATA_B_R2D_CN 16 TP_SATA_B_R2D_CP 16 TP_SATA_D_D2RN 16 TP_SATA_D_D2RP 16 TP_SATA_D_R2D_CN 16 TP_SATA_D_R2D_CP 16 TP_SATA_E_D2RN 16 TP_SATA_E_D2RP 16 TP_SATA_E_R2D_CN 16 TP_SATA_E_R2D_CP NC_CRT_IG_RED 51 17 TP_CRT_IG_HSYNC 17 TP_CRT_IG_VSYNC J9000: Internal DP Connector FUNC_TEST 18 39 TRUE 39 50 TRUE TRUE 39 50 73 39 50 73 TRUE 24 39 68 TRUE 24 39 68 TRUE 18 39 68 TRUE 18 39 68 TRUE TP_PCH_LVDS_VBG 62 65 62 NC_CRT_IG_VSYNC NC_LVDS_IG_CTRL_CLK TRUE MAKE_BASE=TRUE NC_LVDS_IG_CTRL_DATA TRUE MAKE_BASE=TRUE NC_PCH_LVDS_VBG TRUE MAKE_BASE=TRUE TP_LVDS_IG_CTRL_DATA PPVOUT_SW_LCDBKLT PP3V3_SW_LCD I2C_TCON_SDA_R LED_RETURN_6 LED_RETURN_5 LED_RETURN_4 LED_RETURN_3 LED_RETURN_2 LED_RETURN_1 DP_INT_HPD_CONN DP_INT_AUX_CH_C_N DP_INT_AUX_CH_C_P DP_INT_ML_F_P DP_INT_ML_F_N DP_INT_ML_F_P DP_INT_ML_F_N I2C_TCON_SCL_R NC_CRT_IG_HSYNC TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TP_LVDS_IG_CTRL_CLK 18 39 NC_CRT_IG_DDC_DATA 43 51 39 43 19 39 NC_CRT_IG_DDC_CLK TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TP_CRT_IG_DDC_DATA 17 (Need to add GND TPs near J6950 and for shield) 39 43 (Need TPs) (Need TPs) 16 TP_HDA_SDIN1 16 TP_HDA_SDIN2 16 TP_HDA_SDIN3 TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE 62 62 65 62 65 16 TP_SATA_F_D2RN NC_HDA_SDIN1 16 TP_SATA_F_D2RP NC_HDA_SDIN2 16 TP_SATA_F_R2D_CN NC_HDA_SDIN3 16 TP_SATA_F_R2D_CP TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE A TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE 62 65 18 TP_PCI_PME_L 62 65 18 TP_PCI_CLK33M_OUT3 NC_PSOC_P1_3 NC_SATA_B_D2RN NC_SATA_B_D2RP NC_SATA_B_R2D_CP NC_SATA_D_D2RP NC_SATA_D_R2D_CN NC_SATA_D_R2D_CP NC_SATA_E_D2RN NC_SATA_E_D2RP NC_SATA_E_R2D_CN NC_SATA_E_R2D_CP NC_SATA_F_D2RP NC_SATA_F_R2D_CN NC_SATA_F_R2D_CP NC_PCI_CLK33M_OUT3 NC_PCH_TP16 TP_PCH_TP15 TRUE MAKE_BASE=TRUE NC_PCH_TP15 TP_PCH_TP14 TRUE MAKE_BASE=TRUE NC_PCH_TP14 TP_PCH_TP13 TRUE MAKE_BASE=TRUE NC_PCH_TP13 TP_PCH_TP12 TRUE MAKE_BASE=TRUE NC_PCH_TP12 TP_PCH_TP10 TRUE MAKE_BASE=TRUE NC_PCH_TP10 TP_PCH_TP9 TRUE MAKE_BASE=TRUE NC_PCH_TP9 48 TP_PCH_TP8 TRUE MAKE_BASE=TRUE NC_PCH_TP8 48 TP_PCH_TP7 TRUE MAKE_BASE=TRUE NC_PCH_TP7 TP_PCH_TP6 TRUE MAKE_BASE=TRUE NC_PCH_TP6 TP_PCH_TP5 TRUE MAKE_BASE=TRUE NC_PCH_TP5 51 TP_PCH_TP4 TRUE MAKE_BASE=TRUE NC_PCH_TP4 35 TP_PCH_TP3 TRUE MAKE_BASE=TRUE NC_PCH_TP3 TP_PCH_TP2 TRUE MAKE_BASE=TRUE NC_PCH_TP2 TP_PCH_TP1 TRUE MAKE_BASE=TRUE TRUE 24 39 TRUE TRUE TRUE TRUE J5715: KB BKLT Connector 62 65 62 69 16 TP_CLINK_CLK 62 69 16 TP_CLINK_DATA 62 69 TP_CLINK_RESET_L 16 NC_CLINK_CLK TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE NC_CLINK_DATA NC_CLINK_RESET_L 62 69 16 TP_PCIE_CLK100M_PEBN 16 TP_PCIE_CLK100M_PEBP 62 69 62 69 NC_PCIE_CLK100M_PEBN TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE NC_PCIE_CLK100M_PEBP 62 (Need to add GND TPs) Misc Voltages & Control Signals TRUE J6955: HALL EFFECT Connector TRUE SMC_LID_R =PP3V42_G3H_HALL 51 TRUE 51 TRUE TRUE 42 TRUE 42 TRUE 16 40 42 69 TRUE 42 TRUE 42 TRUE 16 40 42 69 TRUE 17 40 42 TRUE 40 41 42 TRUE 25 42 TRUE 40 41 42 TRUE 40 42 TRUE 40 42 TRUE 38 40 41 42 TRUE 25 42 69 TRUE 19 42 49 TRUE 42 TRUE 42 TRUE 16 40 42 TRUE 17 40 42 TRUE 40 41 42 TRUE 40 41 42 TRUE 40 41 42 52 TRUE PPBUS_G3H PPVIN_SW_T29BST PPBUS_S5_HS_COMPUTING_ISNS PPDCIN_G3H PP3V42_G3H PPVRTC_G3H PP5V_S5 PP5V_SUS PP3V3_S5 PP3V3_SUS PP3V3_S3 PP1V8_S0 PP3V3_S0 PP1V5_S3 PP1V5_S3RS0 PP1V5_S0 PP1V05_S0 PPVTTDDR_S3 PP0V75_S0_DDRVTT PPVCCSA_S0_CPU PP1V05_SUS PP15V_T29 PP3V3_T29 PP1V05_T29 PP1V05_S0_PCH_VCCADPLL PPVCORE_S0_CPU PPVCORE_S0_AXG PP1V5_S3_CPU_VCCDQ PP1V05_S0_CPU_VCCPQE PP1V8_S0_CPU_VCCPLL_R 7 PCH_VSS_NCTF 69 NC_PCH_TP1 I567 TRUE PCH_VSS_NCTF 69 TRUE PCH_VSS_NCTF I500 TRUE PCH_VSS_NCTF 69 I499 TRUE PCH_VSS_NCTF 69 I501 TRUE PCH_VSS_NCTF 69 I502 TRUE PCH_VSS_NCTF 69 I503 TRUE PCH_VSS_NCTF 69 I504 TRUE PCH_VSS_NCTF 69 I505 TRUE PCH_VSS_NCTF 69 TRUE PCH_VSS_NCTF 69 69 73 I570 TRUE PCH_VSS_NCTF 69 I571 TRUE PCH_VSS_NCTF 69 I569 TRUE PCH_VSS_NCTF 69 I506 73 17 TP_SDVO_TVCLKINN 67 17 TP_SDVO_TVCLKINP 67 17 TP_SDVO_STALLN 17 TP_SDVO_STALLP TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE NC_SDVO_TVCLKINN TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE NC_SDVO_STALLN NC_SDVO_TVCLKINP TP_LVDS_IG_B_CLKN TP_LVDS_IG_B_CLKP TRUE MAKE_BASE=TRUE TRUE NC_SDVO_STALLP 17 TP_SDVO_INTN 17 TP_SDVO_INTP NC_SDVO_INTN TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TP_LVDS_IG_BKL_PWM NC_SDVO_INTP SMC_BS_ALRT_L (Need to add 27 GND TPs) 23 TP_XDP_PCH_OBSFN_A 23 TP_XDP_PCH_OBSFN_B 35 23 TP_XDPPCH_HOOK2 23 TP_XDPPCH_HOOK3 23 TP_XDP_PCH_OBSFN_D 23 TP_XDP_PCH_HOOK4 7 23 TP_XDP_PCH_HOOK5 TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE NC_TP_XDP_PCH_OBSFN_A TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE NC_PCH_GPIO64_CLKOUTFLEX0 NC_TP_XDP_PCH_OBSFN_B TP_PCH_GPIO64_CLKOUTFLEX0 16 TP_PCH_GPIO65_CLKOUTFLEX1 16 TP_PCH_GPIO66_CLKOUTFLEX2 16 TP_PCH_GPIO67_CLKOUTFLEX3 NC_LVDS_IG_B_CLKP NC_LVDS_IG_BKL_PWM NC_SMC_BS_ALRT_L SYNC_MASTER=(K99_MLB) Functional Test / No Test NC_TP_XDPPCH_HOOK3 DRAWING NUMBER NC_TP_XDP_PCH_OBSFN_D Apple Inc NC_TP_XDP_PCH_HOOK4 NC_TP_XDP_PCH_HOOK5 NC_PCH_GPIO65_CLKOUTFLEX1 NC_PCH_GPIO66_CLKOUTFLEX2 NC_PCH_GPIO67_CLKOUTFLEX3 SYNC_DATE=(02/16/2010) PAGE TITLE NC_TP_XDPPCH_HOOK2 7 NC_LVDS_IG_B_CLKN TRUE MAKE_BASE=TRUE 16 I566 TRUE I568 19 42 TRUE B 38 40 41 42 40 42 C NC_SATA_B_R2D_CN NC_PCH_TP17 16 39 69 TRUE NC_PCIE_CLK100M_PE7P NC_PCI_PME_L TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE 62 (Need to add GND TPs) NC_PCIE_CLK100M_PE7N NC_PCH_TP18 FUNC_TEST TRUE NC_PCIE_CLK100M_PE6P TRUE MAKE_BASE=TRUE TRUE TRUE NC_SATA_F_D2RN NC_PCIE_CLK100M_PE6N TRUE MAKE_BASE=TRUE J5100: LPC+SPI Connector TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE NC_PCIE_CLK100M_PE5P TRUE MAKE_BASE=TRUE 16 39 69 =PP3V3_S5_LPCPLUS =PP5V_S0_LPCPLUS LPC_AD SPI_ALT_MOSI SPI_ALT_MISO LPC_FRAME_L PM_CLKRUN_L SMC_TMS LPCPLUS_RESET_L SMC_TDO SMC_TRST_L SMC_MD1 SMC_TX_L LPC_CLK33M_LPCPLUS SPIROM_USE_MLB SPI_ALT_CLK SPI_ALT_CS_L LPC_SERIRQ LPC_PWRDWN_L SMC_TDI SMC_TCK SMC_RESET_L SMC_NMI SMC_RX_L LPCPLUS_GPIO NC_SATA_D_D2RN NC_PCIE_CLK100M_PE5N TP_PCH_TP16 TRUE TRUE TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE NC_PCIE_CLK100M_PE4P 62 65 FUNC_TEST TRUE NC_PCIE_CLK100M_PE4N TP_PCH_TP17 TRUE 16 39 69 (Need to add GND TPs) FUNC_TEST TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TP_PCH_TP18 16 39 69 16 39 69 KBDLED_FB KBDLED_ANODE NC_CRT_IG_BLUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE FUNC_TEST 39 40 =I2C_LIO_SDA =I2C_LIO_SCL =I2C_MIKEY_SCL =I2C_MIKEY_SDA AUD_IPHS_SWITCH_EN AUD_IP_PERIPHERAL_DET AUD_I2C_INT_L AUD_GPIO_3 SPKRAMP_INR_N SPKRAMP_INR_P USB_EXTD_N USB_EXTD_P USB_CAMERA_N USB_CAMERA_P HDA_SDOUT HDA_BIT_CLK HDA_SDIN0 USB_EXTD_OC_L HDA_RST_L HDA_SYNC TP_CRT_IG_BLUE 17 TRUE FUNC_TEST 50 51 73 17 (Need to add GND TPs) B SPKRAMP_R_P_OUT SPKRAMP_R_N_OUT (Need to add GND TPs) 39 TRUE TRUE D MAKE_BASE=TRUE 48 051-8871 REVISION R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED 2.5.0 BRANCH PAGE OF 109 SHEET OF 74 SIZE D A "G3Hot" (Always-Present) Rails 52 =PPBUS_G3H PPBUS_G3H 51 54 =PP3V3_S5_REG MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.8V MAKE_BASE=TRUE 35 PPVIN_SW_T29BST VOLTAGE=12.8V =PPBUS_S0_LCDBKLT =PPBUS_S0_VSENSE =PPVIN_SW_T29BST =PPVIN_S5_HS_COMPUTING_ISNS_R =PPVIN_S5_P5VP3V3 PP3V3_S5 MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM 44 35 45 54 D =PPVIN_S5_HS_COMPUTING_ISNS PPBUS_S5_HS_COMPUTING_ISNS MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.8V MAKE_BASE=TRUE =PPVIN_S0_CPUIMVP =PPVIN_S3_DDRREG =PPVIN_S0_CPUVCCIOS0 =PPVIN_S0_VCCSAS0 =PPVIN_S0_CPUAXG 51 =PP18V5_DCIN_CONN PPDCIN_G3H 56 57 55 58 53 57 MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM VOLTAGE=18.5V MAKE_BASE=TRUE =PPDCIN_S5_CHGR =PPDCIN_S5_VSENSE 51 =PP3V42_G3H_REG PP3V42_G3H 60 =PP3V3_SUS_FET 44 59 60 MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.42V MAKE_BASE=TRUE =PP3V3_S5_LPCPLUS =PP3V3_S5_SMC =PP3V42_G3H_HALL =PP3V42_G3H_CHGR =PP3V42_G3H_PWRCTL =PP3V42_G3H_SMBUS_SMC_BSA =PP3V42_G3H_SMCUSBMUX =PP3V42_G3H_TPAD =PPVIN_S5_SMCVREF =PPVBAT_G3_SYSCLK =PP3V42_G3H_ONEWIRE C 42 40 41 51 =PPVRTC_G3_OUT PPVRTC_G3H 26 =PP5V_S5_LDO PP5V_S5 17 19 25 41 25 55 =PP5V_SUS_FET 61 20 22 48 64 60 =PP3V3_S3_FET PP3V3_S3 MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM 60 =PP5V_S0_FET 60 =PP3V3_S0_FET 50 55 26 60 38 51 =PP5V_S0_LPCPLUS =PP5V_S0_VCCSA =PP5V_S0_PCH =PP5V_S0_VMON =PP5V_S0_KBDLED 65 56 58 47 42 53 22 PP1V05_T29 35 29 30 32 =PP1V05_T29_RTR 16 19 34 55 1V05 S0 LDO 67 59 PP1V05_S0_PCH_VCCADPLL =PP1V05_S0_LDO 22 MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V MAKE_BASE=TRUE 10 12 15 26 61 =PP1V05_S0_PCH_VCCADPLL 20 59 41 =PP1V5_S0_REG PP1V5_S0 Chipset "VCore" Rails 57 =PPVCORE_S0_CPU_REG PPVCORE_S0_CPU 55 31 =PPVTT_S3_DDR_BUF PPVTTDDR_S3 16 20 22 57 =PPVCORE_S0_AXG_REG 55 =PPVTT_S0_DDR_LDO PP0V75_S0_DDRVTT MIN_LINE_WIDTH=2 mm MIN_NECK_WIDTH=0.17 mm VOLTAGE=0.75V MAKE_BASE=TRUE 45 32 PPVCCSA_S0_CPU 51 73 59 =PP1V05_SUS_LDO VOLTAGE=3.3V MAKE_BASE=TRUE 39 44 12 15 PP1V05_SUS =PP1V5_S3_CPU_VCCDQ PP1V5_S3_CPU_VCCDQ =PP1V05_S0_CPU_VCCPQE PP1V05_S0_CPU_VCCPQE 23 PP1V05_S0 6 MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V MAKE_BASE=TRUE 14 12 =PP1V05_SUS_PCH_JTAG MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.5V MAKE_BASE=TRUE 14 12 =PPVCCSA_S0_CPU MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V MAKE_BASE=TRUE 44 12 15 26 MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=0.9V MAKE_BASE=TRUE 45 32 15 12 =PPVCCSA_S0_REG PPVCORE_S0_AXG =PP1V8_S0_CPU_VCCPLL_R PP1V8_S0_CPU_VCCPLL_R MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.8V MAKE_BASE=TRUE 65 45 =PPCPUVCCIO_S0_REG MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V MAKE_BASE=TRUE ? mA 46 =PP1V05_S0_PCH_VCCIO_PLLPCIE =PP1V05_S0_CPU_VCCIO =PP1V05_S0_PCH =PP1V05_S0_PCH_VCCIO =PP1V05_S0_PCH_VCCIO_PCIE =PP1V05_S0_PCH_VCCIO_SATA =PP1V05_S0_PCH_VCCASW =PP1V05_S0_PCH_VCCIO_USB =PP1V05_S0_PCH_VCC_CORE =PP1V05_S0_VMON =PP1V05_S0_PCH_VCCIO_CLK =PPVCCIO_S0_CPUIMVP =PP1V05_S0_PCH_VCCDIFFCLK =PP1V05_S0_PCH_VCCSSC =PP1V05_S0_PCH_V_PROC_IO =PP1V05_S0_PCH_VCCIO_PLLUSB =PP1V05_S0_PCH_VCC_DMI =PP1V05_S0_PCH_VCCIO_PLLFDI =PP1V05_S0_PCH_VCCDMI_FDI =PPVCCIO_S0_XDP =PPVCCIO_S0_SMC =PP1V05_S0_P1V05T29FET 12 47 35 59 16 19 22 18 22 20 22 20 22 20 22 20 22 22 16 17 19 61 25 25 43 43 43 41 37 B 20 10 12 14 16 22 20 22 17 16 20 22 20 22 20 22 20 22 61 20 22 56 16 20 22 20 22 20 22 20 20 22 20 20 23 40 35 45 61 59 35 SYNC_MASTER=K91_MLB 63 SYNC_DATE=05/15/2010 PAGE TITLE 59 Power Aliases 44 DRAWING NUMBER 23 43 Apple Inc 45 051-8871 REVISION R 2.5.0 25 61 NOTICE OF PROPRIETARY PROPERTY: BRANCH 48 C 12 14 =PPVCORE_S0_CPU_VCCAXG =PPGFXVCORE_S0_VSENSE =PP0V75_S0_MEM_VTT_A =PP0V75_S0_MEM_VTT_B =PPVTT_S0_VTTCLAMP 45 18 19 44 MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V MAKE_BASE=TRUE 43 43 =PPVCORE_S0_CPU =PPCPUVCORE_S0_VSENSE MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=0.75V MAKE_BASE=TRUE 26 MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM VOLTAGE=1.25V MAKE_BASE=TRUE 39 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED 25 61 36 =PP3V3_S0_HDD =PP3V3_S0_HDDISNS =PP3V3_S0_VMON =PP3V3_S0_P1V5S0 =PP3V3_S0_T29PWRCTL =PP3V3_S0_DPSDRVA =PP3V3_S0_P1V05S0LDO =PP3V3_S0_IMVPISNS =PP3V3_S0_XDP =PP3V3_S0_T29I2C =PP3V3_S0_BKLTISNS =PP3V3_S0_SYSCLKGEN PP5V_S0 =PP5V_S0_BKL =PP5V_S0_CPUIMVP =PP5V_S0_CPUVCCIOS0 =PP5V_S0_FAN PP1V5_S3RS0 =PP1V5_S3_CPU_VCCDDR =PP1V5_S3RS0_VMON 31 =PP3V3_S0_HS_COMPUTING_ISNS =PP3V3_S0_CPUTHMSNS =PP3V3_S0_CPU_VCCIO_SEL =PP3V3_S0_DP_DDC =PP3V3_S0_FAN =PP3V3_S0_P3V3T29FET =PP3V3_S0_P1V8S0 =PP3V3_S0_PCH =PP3V3_S0_PCH_GPIO =PP3V3_S0_PCH_VCC3_3_CLK =PP3V3_S0_PCH_VCC3_3_GPIO =PP3V3_S0_PCH_VCC3_3_HVCMOS =PP3V3_S0_PCH_VCC3_3_PCI =PP3V3_S0_PCH_VCC3_3_SATA =PP3V3_S0_PCH_VCCADAC =PP3V3_S0_PCH_STRAPS =PP3V3_S0_PWRCTL =PP3V3_S0_RSTBUF =PP3V3_S0_SB_PM =PP3V3_S0_SMBUS_PCH =PP3V3_S0_SMBUS_SMC_0_S0 =PP3V3_S0_SMBUS_SMC_B_S0 =PP3V3_S0_SMC PP5V_S3 33 34 35 27 28 32 20 16 17 18 19 24 =PP3V3_S0_CPUVCCIOISNS =PP3V3_S0_AUDIO =PP3V3_S0_BKL_VDDIO 22 D =PPVDDIO_T29_CLK =PP3V3_T29_RTR =PP3V3_T29_PCH_GPIO 60 MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.5V MAKE_BASE=TRUE 20 22 24 PP3V3_S0 MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.20MM MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V MAKE_BASE=TRUE 48 MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=5V MAKE_BASE=TRUE A =PP1V5_S3RS0_FET 20 22 36 =PP3V3_S3_1V5S3ISNS =PP3V3_S3_DBGLEDS 60 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5V MAKE_BASE=TRUE 60 =PP1V05_T29_FET 26 =PP3V3_S3_USB_HUB =PP3V3_S3_USB_RESET =PP3V3_S3_VREFMRGN =PP3V3_S3_WLAN =PP3V3_S3_WLANISNS =PP3V3_S3_BMON_ISNS =PP3V3_S3_PCH_GPIO 16 17 20 PP3V3_T29 MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V MAKE_BASE=TRUE VOLTAGE=3.3V MAKE_BASE=TRUE =PP3V3_S3_MEMRESET =PP3V3_S3_SMBUS_SMC_A_S3 =PP3V3_S3_SMBUS_SMC_MGMT 60 =PP5V_S3_MEMRESET =PP5V_S3_P5VS0FET =PP5V_S3_RTUSB =PP5V_S3_LIO_CONN =PP3V3_T29_FET 59 39 =PP5V_S3_AUDIO_AMP =PP5V_S3_DDRREG 35 25 35 =PP3V3R1V5_S0_AUDIO =PP3V3R1V5_S0_PCH_VCCSUSHDA B =PP5V_S3_REG 20 VOLTAGE=3.3V MAKE_BASE=TRUE 48 25 64 67 =PP1V5_S3_MEMRESET =PP1V5_S3_MEM_A =PP1V5_S3_MEM_B =PP1V5_S3_P1V5S3RS0_FET =PPVIN_S0_DDRREG_LDO 60 58 54 PP1V5_S3 =PPHV_SW_DPAPWRSW 59 MIN_LINE_WIDTH=0.8 MM MIN_NECK_WIDTH=0.1 MM VOLTAGE=1.5V MAKE_BASE=TRUE 38 MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM VOLTAGE=3.3V MAKE_BASE=TRUE =PP5V_SUS_PCH 14 18 20 22 MIN_LINE_WIDTH=2 mm MIN_NECK_WIDTH=0.17 mm VOLTAGE=1.5V MAKE_BASE=TRUE PP5V_SUS =PPDDR_S3_REG 61 MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=17.8V MAKE_BASE=TRUE 24 59 41 PP15V_T29 =PP15V_T29_REG 20 22 53 60 35 49 43 MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=5V MAKE_BASE=TRUE =PP5V_S5_P1V5DDRFET =PP5V_S5_P5VSUSFET =PP5V_S5_TPAD =PP1V8_S0_CPU_VCCPLL =PP1V8_S0_PCH_VCC_DFTERM =PP1V8_S0_P1V05S0LDO =PP1V8R1V5_S0_PCH_VCCVRM =PPVDDIO_S0_SBCLK =PP1V8_S0_P1V5S0 62 61 5V Rails 54 2A max supply 52 MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3V MAKE_BASE=TRUE =PPVRTC_G3_PCH PP1V8_S0 MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.8V MAKE_BASE=TRUE 41 =PP3V3_S3_BT 25 =PP1V8_S0_REG 60 =PP3V3_SUS_PCH_VCCSUS_USB =PP3V3_SUS_PCH_VCCSUS_GPIO =PP3V3_SUS_PCH_VCCSUS =PP3V3_SUS_GPIO =PP3V3_SUS_PCH =PP3V3_SUS_PWRCTL =PP3V3_SUS_P1V05SUSLDO =PP3V3_SUS_SMC T29 Rails (off when no cable) 23 PP3V3_SUS MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM 52 73 =PP3V3_S5_ROM =PP3V3_S5_USB_RESET =PP3V3_S5_PCH_VCCDSW =PP3V3_S5_SYSCLK =PP3V3_S5_VMON =PP3V3_S5_PWRCTL =PP3V3_S5_PCH_VCC_SPI =PP3V3_S5_P3V3SUSFET =PP3V3_S5_TPAD =PP3V3_S4_DPAPWRSW VOLTAGE=3.3V MAKE_BASE=TRUE =PP3V3_S5_XDP =PP3V3_S0_P3V3S0FET =PP3V3_S3_P3V3S3FET =PP3V3_S5_CPU_VCCDDR =PP3V3_S4_SMC =PP3V3_S5_LCD =PP3V3_S5_PCH =PP3V3_S5_PCHPWRGD 65 1.8V/1.5V/1.2V/1.05V Rails =PP3V3_S5_SMCBATLOW 45 3.3V Rails PAGE OF 109 SHEET OF 74 SIZE D A T29 DP Ports 9 9 =PEG_R2D_C_P =PEG_R2D_C_N =PEG_D2R_P =PEG_D2R_N PEG_R2D_C_P PEG_R2D_C_N PEG_D2R_P PEG_D2R_N 66 66 66 66 PCIE_T29_R2D_C_P PCIE_T29_R2D_C_N PCIE_T29_D2R_P MAKE_BASE=TRUE PCIE_T29_D2R_N 33 69 17 33 69 17 33 69 17 MAKE_BASE=TRUE MAKE_BASE=TRUE 33 69 17 MAKE_BASE=TRUE 17 TP_DP_IG_C_HPD TP_DP_IG_C_MLP TP_DP_IG_C_MLN TP_DP_IG_C_AUXP TP_DP_IG_C_AUXN DP_T29SNK0_HPD DP_T29SNK0_ML_C_P DP_T29SNK0_ML_C_N MAKE_BASE=TRUE DP_T29SNK0_AUXCH_C_P MAKE_BASE=TRUE DP_T29SNK0_AUXCH_C_N 33 MAKE_BASE=TRUE 33 71 MAKE_BASE=TRUE 33 71 33 71 33 71 MAKE_BASE=TRUE CPU signals MEMVTT_EN 26 =DDRVTT_EN 69 63 DP_EXTA_ML_C_P 68 DP_IG_ML_P TP_DP_IG_B_MLP 17 68 DP_IG_ML_N TP_DP_IG_B_MLN 17 68 DP_IG_AUX_CH_P DP_IG_B_AUX_P 17 68 DP_IG_AUX_CH_N DP_IG_B_AUX_N MAKE_BASE=TRUE CPU Heat Sink Mounting Bosses 69 63 DP_EXTA_ML_C_N MAKE_BASE=TRUE 69 63 Z0913 Z0910 STDOFF-4.5OD1.8H-SM STDOFF-4.5OD1.8H-SM DP_EXTA_AUXCH_C_P 17 MAKE_BASE=TRUE 69 63 17 DP_EXTA_AUXCH_C_N 17 17 MAKE_BASE=TRUE TP_DP_IG_D_HPD 17 TP_DP_IG_C_CTRL_CLK TP_DP_IG_C_CTRL_DATA TP_DP_IG_D_CTRL_CLK TP_DP_IG_D_CTRL_DATA 2.2K 2.2K 2.2K 2.2K R09091 5% 1/20W MF 201 5% 1/20W MF 201 5% 1/20W MF 201 5% 1/20W MF 201 2 100K 5% 1/20W MF 201 DP_IG_C_CTRL_CLK DP_IG_C_CTRL_DATA DP_IG_D_CTRL_CLK MAKE_BASE=TRUE DP_IG_D_CTRL_DATA MAKE_BASE=TRUE MAKE_BASE=TRUE LVDS Aliases Z0912 16 STDOFF-4.5OD1.8H-SM 16 Z0911 STDOFF-4.5OD1.8H-SM 16 1 16 4x 860-1327 69 16 69 16 NC_PCIE_EXCARD_D2RN NC_PCIE_EXCARD_D2RP NC_PCIE_EXCARD_R2D_CN NC_PCIE_EXCARD_R2D_CP NC_PCIE_CLK100M_EXCARDN NC_PCIE_CLK100M_EXCARDP TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE R09241 R09251 DP_EXTA_DDC_CLK 2.2K 2.2K 5% 1/20W MF 201 5% 1/20W MF 201 NC_LVDS_IG_B_DATAP MAKE_BASE=TRUE MAKE_BASE=TRUE 63 Z0914 Z0915 STDOFF-4.5OD1.9H-SM STDOFF-4.5OD1.9H-SM MAKE_BASE=TRUE DP_IG_B_DDC_CLK 17 DP_IG_B_DDC_DATA 17 MAKE_BASE=TRUE 69 16 1 860-1327 860-1327 860-1327 C TP_PCH_CLKOUT_DPN DPLL_REF_CLK_N MAKE_BASE=TRUE DPLL_REF_CLKN 10 66 TP_PCH_CLKOUT_DPP DPLL_REF_CLK_P MAKE_BASE=TRUE DPLL_REF_CLKP 10 66 USB/SD Card Pogo CRITICAL 67 11 67 11 ZS0905 ZS0906 POGO-2.0OD-3.6H-K86-K87 POGO-2.0OD-3.6H-K86-K87 SM SM 67 11 67 11 67 11 1 67 11 870-1938 870-1938 DP_EXTA_HPD DP_IG_B_HPD 17 62 67 11 67 11 MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE LCD_IG_PWR_EN LCD_BKLT_EN 0.5% 1W MF 0612-1 65 PPBUS_SW_LCDBKLT_PWR MAKE_BASE=TRUE 73 45 OUT ISNS_LCDBKLT_P 73 45 OUT ISNS_LCDBKLT_N PPBUS_SW_BKL MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.375 MM VOLTAGE=12.6V MAKE_BASE=TRUE =PPBUS_SW_BKL NC_USB_HUB1_OCS4 65 =USB_HUB1_OCS4 24 =USB_HUB2_OCS4 24 MAKE_BASE=TRUE NC_USB_HUB2_OCS4 MAKE_BASE=TRUE 68 16 IN SATA_ODD_R2D_C_P 68 16 IN SATA_ODD_R2D_C_N ZS0907 POGO-2.0OD-2.95H-K86-K87 1.4DIA-SHORT-SILVER-K99 SM 68 16 OUT SATA_ODD_D2R_P 68 16 OUT SATA_ODD_D2R_N T29_A_BIAS_R 51 1 =PPVIN_SW_T29BST 64 63 =PP15V_T29_REG 35 UNUSED SDCARD USB Aliases =PP3V3_S3_USB_HUB 5% 1/20W MF 201 C0960 B T29 Can Slots SL0901 TH-NSP R0902 10K 5% 1/20W MF 201 10% 10V X5R 201 68 24 OUT USB_SDCARD_N 68 24 OUT USB_SDCARD_P SIGNAL_MODEL=EMPTY R0927 64 T29_A_BIAS_R 51 T29_A_BIAS_D2RN1 5% 1/20W MF 201 1 64 C0907 0.01UF 10% 10V X5R 201 2 SL0902 TH-NSP 64 0.01UF 0.01UF 10% 10V X5R 201 SIGNAL_MODEL=EMPTY 5% 1/8W MF-LF 805 T29_A_BIAS NO_TEST=TRUE C0906 35 NO_TEST=TRUE NC_SATA_ODD_D2RN MAKE_BASE=TRUE R09011 T29_A_BIAS_D2RP1 T29BST:N R0960 870-2015 870-1940 C NO_TEST=TRUE NC_SATA_ODD_D2RP 10K 5% 1/20W MF 201 NO_TEST=TRUE NC_SATA_ODD_R2DCN MAKE_BASE=TRUE T29_A_BIAS caps 64 NC_SATA_ODD_R2DCP MAKE_BASE=TRUE 24 SM 17 MAKE_BASE=TRUE R0926 CRITICAL 17 LVDS_IG_BKL_ON SATA Aliases SIGNAL_MODEL=EMPTY ZS0904 17 LVDS_IG_PANEL_PWR Unused SATA ODD Signals R0910 MAKE_BASE=TRUE CRITICAL 68 LVDS_IG_BKL_PWM NO_TEST=TRUE LCD_BKLT_PWM CRITICAL 0.01 MAKE_BASE=TRUE 68 LVDS_IG_A_DATA_N MAKE_BASE=TRUE 5% 1/20W MF 201 TP_MEM_A_CLKP TP_MEM_A_CLKN NC_MEM_A_CKE NC_MEM_A_CS_L NC_MEM_A_ODT TP_MEM_B_CLKP TP_MEM_B_CLKN NC_MEM_B_CKE NC_MEM_B_CS_L NC_MEM_B_ODT TP_MEM_A_A TP_MEM_B_A MAKE_BASE=TRUE 68 LVDS_IG_A_DATA_P MAKE_BASE=TRUE 65 100K 16 67 11 CRITICAL 65 R09081 16 MEM_A_CLK_P MEM_A_CLK_N MEM_A_CKE MEM_A_CS_L MEM_A_ODT MEM_B_CLK_P MEM_B_CLK_N MEM_B_CKE MEM_B_CS_L MEM_B_ODT MEM_A_A MEM_B_A 68 LVDS_IG_B_DATA_N MAKE_BASE=TRUE MAKE_BASE=TRUE EMI I/O Pogo Pins DisplayPort Pogo DP_EXTA_DDC_DATA NC_PEG_CLK100MP NC_PEG_CLK100MN MAKE_BASE=TRUE 68 LVDS_IG_B_DATA_P NO_TEST=TRUE NC_LVDS_IG_A_DATAN MAKE_BASE=TRUE PEG_CLK100M_P PEG_CLK100M_N 69 16 68 LVDS_IG_B_CLK_N NO_TEST=TRUE NC_LVDS_IG_A_DATAP MAKE_BASE=TRUE SSD Boss Z0905 LVDS_IG_B_CLK_P NO_TEST=TRUE NC_LVDS_IG_B_DATAN MAKE_BASE=TRUE STDOFF-4.5OD1.8H-SM TP_LVDS_IG_B_CLKN MAKE_BASE=TRUE 63 X21 Boss TP_LVDS_IG_B_CLKP MAKE_BASE=TRUE =PP3V3_S0_DP_DDC 63 Fan Boss D 2 MAKE_BASE=TRUE PCIE_EXCARD_D2R_N PCIE_EXCARD_D2R_P PCIE_EXCARD_R2D_C_N PCIE_EXCARD_R2D_C_P PCIE_CLK100M_EXCARD_N PCIE_CLK100M_EXCARD_P DP_IG_D_HPD MAKE_BASE=TRUE R09201 R09211 R09221 R09231 26 55 MAKE_BASE=TRUE D 17 =PP3V3_S0_DP_DDC SIGNAL_=EMPTY B T29_A_BIAS caps SL-1.1X0.4-1.4x0.7 SIGNAL_MODEL=EMPTY R0931 SL-1.1X0.4-1.4x0.7 998-2691 998-2691 64 51 T29_A_BIAS_R DP_A_BIAS caps T29_A_BIAS_R2DP0 5% 1/20W MF 201 63 C0901 63 DP_A_BIAS_P_2 10% 10V SIGNAL_MODEL=EMPTY X5R 201 C0962 SIGNAL_MODEL=EMPTY DisplayPort PCB Stiffener (Provides PCB support for small finger above J9400) R0932 64 T29_A_BIAS_R 51 T29_A_BIAS_R2DN0 5% 1/20W MF 201 NO STUFF MT0900 C0964 0.01UF 0.01UF 10% 10V X5R 201 10% 10V X5R 201 TP_P1V5S3RS0_RAMP_DONE TP_DDRREG_PGOOD R0990 63 DP_A_BIAS_N_2 63 DP_A_BIAS_N_0 23 19 SIGNAL_MODEL=EMPTY SIGNAL_MODEL=EMPTY C0905 0.01UF 806-1176 SIGNAL_MODEL=EMPTY R0933 51 2 T29_A_BIAS_R2DP1 5% 1/20W MF 201 GND 2 5% 1/20W MF 201 10% 10V SIGNAL_MODEL=EMPTY X5R 201 OUT JTAG_ISP_TDI JTAG_T29_TDI MAKE_BASE=TRUE JTAG_T29_TCK OUT JTAG_ISP_TDO JTAG_T29_TDO 5% 1/20W MF 201 MAKE_BASE=TRUE SYNC_MASTER=K91_MLB 33 OUT 33 IN 33 Signal Aliases =PP3V3_S3_USB_HUB DRAWING NUMBER 10K T29_A_BIAS_R2DN1 63 NO STUFF C0904 0.01UF 10% 10V X5R 201 68 63 SIGNAL_MODEL=EMPTY 68 63 T29_A_RSVD_N T29_A_RSVD_P R0917 201 R09181/20W 201 1/20W SYNC_DATE=05/15/2010 PAGE TITLE Unused USB ports 0 1 5% 1/20W MF 201 R0916 MF 5% MF 051-8871 REVISION R 5% 1/20W MF 201 USB_T29A_N USB_T29A_P 5% Apple Inc 10K NO STUFF 19 T29 Aliases R09151 10% 10V X5R 201 JTAG_T29_TCK_R 63 24 51 IN JTAG_ISP_TCK MAKE_BASE=TRUE C0903 R0934 19 0.01UF 10% 10V X5R 201 SIGNAL_MODEL=EMPTY T29_A_BIAS_R C0908 IN 0.01UF VOLTAGE=0V MIN_NECK_WIDTH=0.075MM MIN_LINE_WIDTH=0.6MM 64 55 T29 JTAG 10% 10V X5R SIGNAL_MODEL=EMPTY 201 SM-SP T29_A_BIAS_R 60 IN 63 64 IN DDRREG_PGOOD MAKE_BASE=TRUE C0902 Digital Ground P1V5S3RS0_RAMP_DONE MAKE_BASE=TRUE 0.01UF STIFFENER-K16-K99 A Unused PGOOD signal DP_A_BIAS_P_0 63 0.01UF NOTICE OF PROPRIETARY PROPERTY: 24 68 24 68 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED 2.5.0 BRANCH PAGE OF 109 SHEET OF 74 SIZE D A OMIT_TABLE NOTE: CRITICAL IN 66 17 IN 66 17 IN 66 17 IN 66 17 IN 66 17 OUT 66 17 OUT 66 17 OUT 66 17 OUT 66 17 OUT 66 17 OUT 66 17 OUT 66 17 OUT 66 17 OUT 66 17 OUT 66 17 OUT 66 17 OUT 66 17 OUT 66 17 OUT 66 17 OUT 66 17 C 14 12 10 OUT 66 17 OUT 66 17 OUT 24.9 1% 1/20W MF 201 DMI_N2S_N DMI_N2S_N DMI_N2S_N DMI_N2S_N K1 M8 N4 R2 FDI_DATA_N FDI_DATA_N FDI_DATA_N FDI_DATA_N FDI_DATA_P FDI_DATA_P FDI_DATA_P FDI_DATA_P U6 W10 W3 AA7 FDI0_TX_0 FDI0_TX_1 FDI0_TX_2 FDI0_TX_3 FDI_DATA_P FDI_DATA_P FDI_DATA_P FDI_DATA_P W7 T4 AA3 AC8 FDI1_TX_0 FDI1_TX_1 FDI1_TX_2 FDI1_TX_3 OUT 66 17 OUT 66 17 OUT 66 17 OUT 66 17 IN 66 17 IN FDI_FSYNC FDI_FSYNC 66 17 IN FDI_INT 66 17 IN 66 AA11 AC12 U11 FDI_LSYNC FDI_LSYNC EDP_COMP AA10 AG8 AD2 AF3 PLACE_NEAR=U1000.AF3:12.7MM 69 62 69 62 69 62 69 62 6 69 62 69 62 B DMI_TX_0 DMI_TX_1 DMI_TX_2 DMI_TX_3 W6 V4 Y2 AC9 OUT IN DMI_TX_0* DMI_TX_1* DMI_TX_2* DMI_TX_3* U7 W11 W1 AA6 66 17 66 17 K3 M7 P4 T3 EDP_HPD_L AG11 DP_INT_AUX_CH_N DP_INT_AUX_CH_P AG4 AF4 BGA (1 OF 9) FDI0_TX_0* FDI0_TX_1* FDI0_TX_2* FDI0_TX_3* FDI1_TX_0* FDI1_TX_1* FDI1_TX_2* FDI1_TX_3* FDI0_FSYNC FDI1_FSYNC FDI_INT FDI0_LSYNC FDI1_LSYNC EDP_ICOMPO EDP_COMPIO FIXME: Pin should be EDP_HPD* EDP_HPD EDP_AUX* EDP_AUX DP_INT_ML_N DP_INT_ML_N TP_EDP_TX_N TP_EDP_TX_N AC3 AC4 AE11 AE7 EDP_TX_0* EDP_TX_1* EDP_TX_2* EDP_TX_3* DP_INT_ML_P DP_INT_ML_P TP_EDP_TX_P TP_EDP_TX_P AC1 AA4 AE10 AE6 EDP_TX_0 EDP_TX_1 EDP_TX_2 EDP_TX_3 Intel Doc 438297 Huron River SFF DG rev1.0 section 2.2.1 recommendation NOTE: eDP_COMPIO and eDP_ICOMPO can not be left floating even if internal Graphics is disabled since they are shared with other interfaces NOTE: The EDP_HPD processor input is a low voltage active low signal Therefore, an inverting level shifter is required on the motherboard to convert the active high signal from Embedded DisplayPort sink device to low voltage signals for the processor (refer to latest Processor EDS for DC specifications) If HPD is disabled while eDP interface is still enabled, connect it to CPU VCCIo via a 10-kOhm pull-up resistor on the motherboard This signal can be left as no-connect if entire eDP interface is disabled 66 23 66 23 66 23 66 23 66 23 23 CPU_CFG CPU_CFG CPU_CFG CPU_CFG CPU_CFG NOSTUFF A CPU_CFG CPU_CFG CPU_CFG H22 J21 B22 D21 A19 D17 B14 D13 A11 B10 G8 A8 B6 H8 E5 K7 PEG_RX_0 PEG_RX_1 PEG_RX_2 PEG_RX_3 PEG_RX_4 PEG_RX_5 PEG_RX_6 PEG_RX_7 PEG_RX_8 PEG_RX_9 PEG_RX_10 PEG_RX_11 PEG_RX_12 PEG_RX_13 PEG_RX_14 PEG_RX_15 K22 K19 C21 D19 C19 D16 C13 D12 C11 C9 F8 C8 C5 H6 F6 K6 =PEG_D2R_P =PEG_D2R_P =PEG_D2R_P =PEG_D2R_P =PEG_D2R_P =PEG_D2R_P =PEG_D2R_P =PEG_D2R_P =PEG_D2R_P =PEG_D2R_P =PEG_D2R_P =PEG_D2R_P =PEG_D2R_P =PEG_D2R_P =PEG_D2R_P =PEG_D2R_P PEG_TX_0* PEG_TX_1* PEG_TX_2* PEG_TX_3* PEG_TX_4* PEG_TX_5* PEG_TX_6* PEG_TX_7* PEG_TX_8* PEG_TX_9* PEG_TX_10* PEG_TX_11* PEG_TX_12* PEG_TX_13* PEG_TX_14* PEG_TX_15* G22 C23 D23 F21 H19 C17 K15 F17 F14 A15 J14 H13 M10 F10 D9 J4 =PEG_R2D_C_N =PEG_R2D_C_N =PEG_R2D_C_N =PEG_R2D_C_N =PEG_R2D_C_N =PEG_R2D_C_N =PEG_R2D_C_N =PEG_R2D_C_N =PEG_R2D_C_N =PEG_R2D_C_N =PEG_R2D_C_N =PEG_R2D_C_N =PEG_R2D_C_N =PEG_R2D_C_N =PEG_R2D_C_N =PEG_R2D_C_N PEG_TX_0 PEG_TX_1 PEG_TX_2 PEG_TX_3 PEG_TX_4 PEG_TX_5 PEG_TX_6 PEG_TX_7 PEG_TX_8 PEG_TX_9 PEG_TX_10 PEG_TX_11 PEG_TX_12 PEG_TX_13 PEG_TX_14 PEG_TX_15 F22 A23 D24 E21 G19 B18 K17 G17 E14 C15 K13 G13 K10 G10 D8 K4 =PEG_R2D_C_P =PEG_R2D_C_P =PEG_R2D_C_P =PEG_R2D_C_P =PEG_R2D_C_P =PEG_R2D_C_P =PEG_R2D_C_P =PEG_R2D_C_P =PEG_R2D_C_P =PEG_R2D_C_P =PEG_R2D_C_P =PEG_R2D_C_P =PEG_R2D_C_P =PEG_R2D_C_P =PEG_R2D_C_P =PEG_R2D_C_P NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF R1045 R1046 R1047 R1040 R1041 R1043 R1049 1K 1K 1K 1K 1K 1K 1K 5% 5% 5% 5% 5% 5% 5% 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W MF-LF MF-LF MF-LF MF-LF MF-LF MF-LF MF-LF MF-LF MF-LF 402 402 402 402 66 23 IN 66 23 IN 66 23 IN 66 23 IN 66 23 IN 66 23 IN 66 23 IN 66 23 IN 66 23 IN 66 23 IN 66 23 IN 66 23 IN 66 23 IN 66 23 IN 23 IN 23 IN IN IN IN IN IN IN IN IN IN IN R1064 IN 49.9 49.9 IN IN 1% 1/20W MF 201 1% 1/20W MF 201 IN IN IN IN IN Note VOLTAGE=1.05V IN Note VOLTAGE=0V IN IN IN IN IN IN IN IN IN IN IN IN OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT =PPVCORE_S0_CPU 12 14 =PPVCORE_S0_CPU_VCCAXG NOSTUFF NOSTUFF 12 15 R1070 PLACE_NEAR=U1000.H45:50.8MM PLACE_SIDE=BOTTOM Note VOLTAGE=1.25V Note VOLTAGE=0V NOSTUFF CPU_CFG CPU_CFG CPU_CFG CPU_CFG CPU_CFG CPU_CFG CPU_CFG CPU_CFG CPU_CFG CPU_CFG CPU_CFG CPU_CFG CPU_CFG CPU_CFG CPU_CFG CPU_CFG CPU_CFG CPU_CFG B50 C51 B54 D53 A51 C53 C55 H49 A55 H51 K49 K53 F53 G53 L51 F51 D52 L53 RSVD_28 BE7 RSVD_29 BG7 NC U1000 CFG_0 CFG_1 CFG_2 CFG_3 CFG_4 CFG_5 CFG_6 CFG_7 CFG_8 CFG_9 CFG_10 CFG_11 CFG_12 CFG_13 CFG_14 CFG_15 CFG_16 CFG_17 BGA (5 OF 9) RESERVED RSVD_30 RSVD_31 RSVD_32 RSVD_33 N42 NC L42 NC L45 NC L47 RSVD_34 RSVD_35 RSVD_36 RSVD_37 RSVD_38 M13 NC M14 NC U14 NC W14 NC P13 CPU_MEM_VREFDQ_A D NC NC RSVD_39 AT49NC RSVD_40 K24 NC RSVD_41 RSVD_42 RSVD_43 RSVD_44 CPU_VCC_VALSENSE_P CPU_VCC_VALSENSE_N H43 VCC_VAL_SENSE K43 VSS_VAL_SENSE CPU_AXG_VALSENSE_P CPU_AXG_VALSENSE_N H45 VAXG_VAL_SENSE K45 VSSAXG_VAL_SENSE TP_CPU_VCC_DIE_SENSE F48 VCC_DIE_SENSE AH2 NC AG13 NC AM14NC AM15 NC RSVD_45 N50 NC NOSTUFF R1065 R1071 49.9 49.9 1% 1/20W MF 201 1% 1/20W MF 201 2 73 46 OUT 73 46 OUT DC_TEST_A4 DC_TEST_C4 DC_TEST_D3 DC_TEST_D1 DC_TEST_A58 DC_TEST_A59 DC_TEST_C59 DC_TEST_A61 DC_TEST_C61 DC_TEST_D61 DC_TEST_BD61 DC_TEST_BE61 DC_TEST_BE59 DC_TEST_BG61 DC_TEST_BG59 DC_TEST_BG58 DC_TEST_BG4 DC_TEST_BG3 DC_TEST_BE3 DC_TEST_BG1 DC_TEST_BE1 DC_TEST_BD1 H48 RSVD_6 K48 RSVD_7 CPU_THERMD_P CPU_THERMD_N BA19 RSVD_8 RSVD_9 RSVD_10 RSVD_11 RSVD_12 RSVD_13 RSVD_14 RSVD_15 RSVD_16 RSVD_17 RSVD_18 RSVD_19 RSVD_20 RSVD_21 RSVD_22 RSVD_23 RSVD_24 RSVD_25 RSVD_26 RSVD_27 NC AV19 NC AT21 NC BB21 NC BB19 NC AY21 NC BA22 NC AY22 NC AU19 NC AU21 NC BD21 NC BD22 NC BD25 NC BD26 NC BG22 NC BE22 NC BG26 NC BE26 NC BF23 NC BE24 NC PLACE_NEAR=U1000.K45:50.8MM PLACE_SIDE=BOTTOM PLACE_NEAR=U1000.K43:50.8MM PLACE_SIDE=BOTTOM NOTE: Intel validation sense lines per doc 439028 rev1.0 HR_PPDG sections 6.2.1 and 6.3.1 A4 TP_CPU_DC_TEST_A4 C4 CPU_DC_TEST_C4_D3 D3 D1 TP_CPU_DC_TEST_D1 A58 TP_CPU_DC_TEST_A58 A59 CPU_DC_TEST_C59_A59 C59 A61 CPU_DC_TEST_C61_A61 C61 D61 TP_CPU_DC_TEST_D61 BD61 TP_CPU_DC_TEST_BD61 BE61 CPU_DC_TEST_BE59_BE61 BE59 BG61 CPU_DC_TEST_BG59_BG61 BG59 BG58 TP_CPU_DC_TEST_BG58 BG4 TP_CPU_DC_TEST_BG4 BG3 CPU_DC_TEST_C4_BE3_BG3 BE3 BG1 CPU_DC_TEST_C4_BE1_BG1 BE1 BD1 TP_CPU_DC_TEST_BD1 C NOTE: Intel is investigating future processor VREF_DQ generation to replace M1 and M2 This would require routing processor signal balls BE7 and BG7 for Sandy Bridge 2-core to SO-DIMM connectors directly FETs are needed in order to avoid potential leakage while system is in S3 state NOSTUFF R1021 67 31 30 29 28 27 PP0V75_S3_MEM_VREFDQ_A 5% 1/20W MF 201 CPU_MEM_VREFDQ_A B 1NOSTUFF R1020 1K 1% 1/20W MF 201 =PP1V05_S0_CPU_VCCIO 1K 5% IN R1031 1K IN 66 23 PLACE_NEAR=U1000.AG11:12.7MM R1044 IN 66 23 5% =PEG_D2R_N =PEG_D2R_N =PEG_D2R_N =PEG_D2R_N =PEG_D2R_N =PEG_D2R_N =PEG_D2R_N =PEG_D2R_N =PEG_D2R_N =PEG_D2R_N =PEG_D2R_N =PEG_D2R_N =PEG_D2R_N =PEG_D2R_N =PEG_D2R_N =PEG_D2R_N PEG_RX_0* PEG_RX_1* PEG_RX_2* PEG_RX_3* PEG_RX_4* PEG_RX_5* PEG_RX_6* PEG_RX_7* PEG_RX_8* PEG_RX_9* PEG_RX_10* PEG_RX_11* PEG_RX_12* PEG_RX_13* PEG_RX_14* PEG_RX_15* 14 12 10 1K 402 EDP CRITICAL 10 12 14 1% 1/20W MF 201 66 23 R1042 =PP1V05_S0_CPU_VCCIO CPU_CFG 66 23 66 23 PLACE_NEAR=U1000.G3:12.7MM PEG_ICOMPI G3 PEG_ICOMPO G1 PEG_RCOMPO G4 SANDY-BRIDGE MOBILE-2C-35W DMI_RX_0 DMI_RX_1 DMI_RX_2 DMI_RX_3 FDI_DATA_N FDI_DATA_N FDI_DATA_N FDI_DATA_N 66 17 =PP1V05_S0_CPU_VCCIO R1030 N3 P7 P3 P11 DMI_N2S_P DMI_N2S_P DMI_N2S_P DMI_N2S_P OUT 66 17 DMI_S2N_P DMI_S2N_P DMI_S2N_P DMI_S2N_P U1000 DMI_RX_0* DMI_RX_1* DMI_RX_2* DMI_RX_3* PCI EXPRESS BASED INTERFACE SIGNALS IN 66 17 M2 P6 P1 P10 DMI 66 17 DMI_S2N_N DMI_S2N_N DMI_S2N_N DMI_S2N_N INTEL FLEXIBLE DISPLAY INTERFACE SIGNALS IN EMBEDDED DISPLAY PORT D IN 66 17 OMIT_TABLE 24.9 CPU_PEG_COMP Intel provides an internal pull-up OF 5-15k to VCCIO on all CFG signals R1010 66 66 17 SANDY-BRIDGE MOBILE-2C-35W 402 402 402 5% 1/20W MF 201 402 EDP_HPD_L Q1031 SSM3K15FV D A SOD-VESM-HF PAGE TITLE CPU DMI/PEG/FDI/RSVD G These can be Placed close to J2500 and Only for debug access 62 S DRAWING NUMBER Apple Inc DP_INT_HPD FOR SANDYBRIDGE PROCESSOR CFG [7] :PEG DEFER TRAINING R = (DEFAULT) IMMEDIATELY AFTER xxRESETB CFG [6:5] :PCIE BIFURCATION 11 = X16 (DEFAULT) CFG [4] :eDP ENABLE/DISABLE = DISABLED CFG [3] :PCIE x4 LANE REVERSAL = NORMAL OPERATION = LANES REVERSED CFG [2] :PCIE x16 LANE REVERSAL = NORMAL OPERATION = LANES REVERSED 051-8871 10 = X8 NOTICE OF PROPRIETARY PROPERTY: = WAIT FOR BIOS 01 = RSVD 00 = X8, X4, X4 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED = ENABLED SIZE D REVISION 2.5.0 BRANCH PAGE 10 OF 109 SHEET OF 74 D D 14 12 10 OMIT_TABLE =PP1V05_S0_CPU_VCCIO CRITICAL U1000 NOSTUFF NOSTUFF R11001 62 5% 1/20W MF 201 C 66 66 40 19 R1103 26 15 12 BI CPU_PROCHOT_L 56 CPU_PECI BI 66 19 OUT DPLL_REF_CLK AG3 DPLL_REF_CLK* AG1 BCLK_ITP N59 BCLK_ITP* N58 A48 PECI C45 PROCHOT* PM_THRMTRIP_L D45 THERMTRIP* PM_MEM_PWRGD 130 PM_SYNC C48 PM_SYNC IN CPU_PWRGD B46 UNCOREPWRGOOD PM_MEM_PWRGD_R 1% 1/20W MF 201 BE45 SM_DRAMPWROK PLT_RESET_LS1V1_L 26 OUT D44 RESET* =MEM_RESET_L AT30 SM_DRAMRST* CPU_SM_RCOMP CPU_SM_RCOMP CPU_SM_RCOMP 66 66 66 14 12 10 BF44 SM_RCOMP_0 BE43 SM_RCOMP_1 BG43 SM_RCOMP_2 =PP1V05_S0_CPU_VCCIO JTAG & BPM IN R1121 IN PWR MGMT 66 26 17 66 17 66 23 19 DDR3 MISC 1% 1/20W MF 201 IN IN 16 66 DPLL_REF_CLKP DPLL_REF_CLKN IN 66 IN 66 ITPCPU_CLK100M_P ITPCPU_CLK100M_N IN 16 66 (IPU) (IPU) PRDY* N53 PREQ* N55 XDP_CPU_PRDY_L XDP_CPU_PREQ_L (IPU) (IPU) (IPU) TCK L56 TMS L55 TRST* J58 XDP_CPU_TCK XDP_CPU_TMS XDP_CPU_TRST_L (IPU) TDI M60 TDO L59 R1120 200 DMI_CLK100M_CPU_P DMI_CLK100M_CPU_N 16 66 IN 16 66 OUT 23 66 IN 23 66 IN 23 66 IN 23 66 IN 23 66 C C49 CATERR* CPU_PROCHOT_R_L 5% 1/20W MF 201 =PP1V5_S3_CPU_VCCDDR F49 PROC_SELECT* CPU_CATERR_L OUT CLOCKS CPU_PROC_SEL_L OUT BCLK J3 BCLK* H2 BGA (2 OF 9) 5% 1/20W MF 201 C57 PROC_DETECT* NC 18 66 56 41 1K 5% 1/20W MF 201 THERMAL 51 5% 1/20W MF 201 R1101 SANDY-BRIDGE MOBILE-2C-35W R1104 1R1102 1K NOSTUFF DBR* K58 (IPU) (IPU) (IPU) (IPU) (IPU) (IPU) (IPU) (IPU) BPM_0* BPM_1* BPM_2* BPM_3* BPM_4* BPM_5* BPM_6* BPM_7* XDP_CPU_TDI XDP_CPU_TDO IN 23 66 OUT 23 66 XDP_DBRESET_L OUT 23 25 66 XDP_BPM_L XDP_BPM_L XDP_BPM_L XDP_BPM_L XDP_BPM_L XDP_BPM_L XDP_BPM_L XDP_BPM_L G58 E55 E59 G55 G59 H60 J59 J61 BI 23 66 BI 23 66 BI 23 66 BI 23 66 BI 23 66 BI 23 66 BI 23 66 BI 23 66 NOSTUFF R1115 R1112 1R1113 1R1114 B R1126 140 25.5 200 1% 1/20W MF 201 1% 1/20W MF 201 1% 1/20W MF 201 75 1% 1/20W MF 201 25 23 IN CPU_RESET_L 2 4.99K 1% 1/20W MF 201 R1111 10K B 5% 1/20W MF 201 R1125 43.2 1% 1/20W MF 201 A A PAGE TITLE CPU CLOCK/MISC/JTAG DRAWING NUMBER Apple Inc 051-8871 R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED SIZE D REVISION 2.5.0 BRANCH PAGE 11 OF 109 SHEET 10 OF 74 3.3V S0 FET CRITICAL Q7830 SIA427DJ SC70-6L =PP3V3_S0_FET D S =PP3V3_S0_P3V3S0FET 3.3V S0 FET C7831 R7832 Q7812 0.033UF 10K 10% 16V X5R 402 5% 1/20W MF 201 SSM6N37FEAPE SOT563 61 IN G 91K S D MOSFET SiA427 CHANNEL P-TYPE 8V/5V C7830 R7830 P3V3S0_EN_L =P3V3S0_EN D G D RDS(ON) 0.01UF P3V3S0_SS 26 mOhm @1.8V LOADING 5% 1/20W MF 201 3.2 A (EDP) 10% 10V X5R 201 3.3V_SUS FET Q7820 CRITICAL SIA427DJ SC70-6L D C7821 SOT563 CRITICAL Q7810 G SIA427DJ 61 60 =P3V3S3_EN 5V_SUS FET 3.3V S3 FET C7810 0.01UF P3V3S3_SS 26 mOhm @1.8V LOADING 100? mA (EDP) C CRITICAL Q7840 5% 1/20W MF 201 MOSFET SiA427 CHANNEL P-TYPE 8V/5V RDS(ON) 10% 10V X5R 201 SC70-6L =PP5V_S5_P5VSUSFET =PP5V_SUS_FET 47K P-TYPE 8V/5V SIA413DJ R7810 P3V3S3_EN_L S SiA427 MOSFET CHANNEL RDS(ON) 10% 10V X5R 201 S 10% 16V X5R 402 31 mOhm @1.8V C7841 LOADING 1.608 A (EDP) Q7822 R7842 D 61 60 IN =P5V_3V3_SUS_EN 10% 16V X5R 402 5% 1/20W MF 201 SOT563 G 0.033UF 220K SSM6N37FEAPE P5VSUS_EN_L S R7840 3.3K 5V SUS FET G IN 5% 1/20W MF 201 SOT563 61 C7811 0.033UF 5% 1/20W MF 2201 D SSM6N37FEAPE G =P5V_3V3_SUS_EN 0.01UF P3V3SUS_SS Q7812 =PP3V3_S3_FET G R7812 100K C D S =PP3V3_S3_P3V3S3FET IN 3.3V SUS FET C7820 R7820 P3V3SUS_EN_L 12K S SC70-6L 10% 16V X5R 402 D 3.3V S3 FET 0.033UF 5% 1/20W MF 201 Q7822 SSM6N37FEAPE =PP3V3_SUS_FET G R7822 100K D S =PP3V3_S5_P3V3SUSFET MOSFET C7840 0.01UF P5VSUS_SS 5% 1/20W MF 201 10% 16V CERM 402 SiA427 CHANNEL RDS(ON) P-TYPE 12V/8V 29 mOhm @4.5V LOADING 100? mA (EDP) 1.5V S3/S0 FET 5.0V S0 FET =PP1V5_S3_P1V5S3RS0_FET =PP5V_S0_FET B TDFN ON CRITICAL G S 10% 6.3V X5R-CERM 603 PG SHDN* 4.7UF R7862 220K R7801 P1V5S0FET_GATE 5% P1V5S0FET_GATE_R 1/16W MF-LF 402 CRITICAL 5% 1/20W MF 2201 Q7801 IRLHS6242TRPBF G PQFN2X2 S CRITICAL P5V0S0_EN_L R7850 PP1V5_S3RS0_FET_R THRM PAD C7861 5.0V S0 FET D =PP5V_S3_P5VS0FET APN 376S0981 0.033UF 10% 16V X5R R7860 10K B MOSFET TPCP8102 CHANNEL P-TYPE RDS(ON) 18 MOHM @4.5V LOADING 1.678 A (EDP) C7860 402 0.01UF P5V0S0_SS 5% =PP1V5_S3RS0_FET 5% 1/4W MF-LF 1206 GND D D NO STUFF C7802 SLG5AP020 P1V5CPU_EN 5 S VCC U7801 G 20% 10V CERM 402 23V1K-SM 0.1UF IN Q7860 TPCP8102 C7801 26 CRITICAL =PP5V_S5_P1V5DDRFET 1/20W 10% MF 16V 201 CERM 402 Q7802 D SSM6N37FEAPE SOT563 P1V5S3RS0_RAMP_DONE OUT G 61 IN =P5VS0_EN S 1.5V S3/S0 FET MOSFET PQFN2X2 CHANNEL N-TYPE RDS(ON) 9.4 mOhm @4.5V LOADING A (EDP) A SYNC_MASTER=K21_MLB SYNC_DATE=12/13/2010 PAGE TITLE Power FETs DRAWING NUMBER Apple Inc 051-8871 R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED SIZE D REVISION 2.5.0 BRANCH PAGE 78 OF 109 SHEET 60 OF 74 A S5 Rail Enables & PGOOD 3.3V,5V S3 ENABLE =PP3V42_G3H_PWRCTL Internal pull-ups 100K +/- 20% 61 State C7940 0.1UF 10% VDD 6.3V X5R 201 IN U7941 IN_A =PP3V3_S5_PWRCTL Threshold: ?? DLY > 10 ms S5PGOOD_DLY 343S0497 OUT_A* (IPD) (OD,IPU) IN_B (OD,IPU) OUT_A Sleep (S3) =P3V3S5_ENOUT 0.033UF Deep Sleep (S4) 54 10% 16V X5R 402 PM_SLP_S5_L Deep Sleep (S5) NO STUFF Battery Off (G3Hot) PM_SLP_S4_L 1 1 0 0 0 0 S5_PWRGD S0 ENABLE Delete R when pull-down added to PCH page 56 OUT PLACE_NEAR=U7400.1:5mm 5% 1/20W MF 201 100 PM_PECI_PWRGD OUT 15K ALL_SYS_PWRGD Q1 Q2 VMON_Q3_BASE NC IN 1/20W MF 201 =PP3V3_S5_PWRCTL R79571 100 S4_PGOOD_CT CT NO STUFF R7968 54 =PP5V_S0_VMON IN IN 100 CPUIMVP_AXG_PGOOD 5% 1/20W MF 201 P1V8S0_PGOOD IN =PP1V5_S3RS0_VMON C7960 =PP1V05_S0_VMON 0.1UF 61 10K 1% 1/20W MF 2012 S0PGOOD_ISL R79731 15K P5VS3_PGOOD V3MON S0PGOOD_ISL V4MON RST* GND 1% 1/20W MF 2012 61 58 IN 10% 6.3V X5R 201 PVCCSA_EN =PVCCSA_EN 53 OUT MAKE_BASE=TRUE C 59 52 PLACE_NEAR=U7720.5:6mm PLACE_NEAR=U7100.15:6mm PLACE_NEAR=U7600.3:6mm S C7987 C7981 PLACE_NEAR=U7770.3:6mm 0.47UF 0.47UF 0.47UF 10% 6.3V CERM-X5R 402 10% 6.3V CERM-X5R 402 10% 6.3V CERM-X5R 402 2 C7988 C7986 0.47UF 10% 6.3V CERM-X5R 402 60 53 IN PVCCSA_PGOOD 100 5% 1/20W MF 201 100 5% 1/20W MF 201 U7930 RESET* SOT23-6 MR* PM_RSMRST_L (90K IPU) OUT 17 PM_RSMRST_L goes to U1800.C21 NC C7931 WLAN Enable Generation 1000PF 10% 16V X7R 201 "WLAN" = ("S3" && "AP_PWR_EN" && ("AC" || "S0")) NOTE: S3 term is guaranteed by S3 pull-up on open-drain AP_PWR_EN signal NO STUFF R7966 100 PM_WLAN_EN_L Q7925 IN AP_PWR_EN SOT-363 DP S4 Power Enable (AC_EN_L) IN SMC_S4_WAKESRC_EN =DPAPWRSW_EN MAKE_BASE=TRUE SOT-363 OUT 64 SYNC_MASTER=K21_MLB NO STUFF PSOC USB Power Enable IN G S THRM_PAD 5% 1/20W MF 201 S0PGOOD_ISL R7962 330 ALL_SYS_PWRGD OUT 61 40 26 17 IN S DRAWING NUMBER 2N7002DW-X-G G SOT-363 Apple Inc PM_SLP_S3_L 051-8871 (PM_SLP_S3_L) NOTICE OF PROPRIETARY PROPERTY: SIZE D REVISION R THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED 23 25 40 51 61 5% 1/20W MF 201 Power Control 1/ENABLE Q7920 D SMC_ADAPTER_EN SYNC_DATE=12/13/2010 PAGE TITLE R79291 D 41 40 17 S NC AC_EN_L Q7920 2N7002DW-X-G 41 40 G R7964 S 5% 1/20W MF 201 Unused fet SOT-363 NC G D 2N7002DW-X-G D 2N7002DW-X-G 36 18 100 Q7925 NC 36 OUT 5% 1/20W MF 201 ALL_SYS_PWRGD_R 353S2310 B 5% 1/20W MF 201 R7901 CPUVCCIOS0_PGOOD 58 100K 5% 1/20W MF 201 R7963 NC 2 U7960 1% 1/20W MF 2012 R7971 IN 5% 1/20W MF 201 VDD 15K 54 100 P3V3S5_PGOOD S0PGOOD_ISL P1V5_DIV_VMON R79611S0PGOOD_ISL P1V05_DIV_VMON 59 GND R79671 R7965 P5V_DIV_VMON OUT =1V05_S0_LDO_ENOUT =CPUVCCIOS0_EN OUT VDD SENSE =PP3V3_SUS_PWRCTL =PP3V3_S0_PWRCTL =PP3V3_S0_VMON ISL88042IRTEZ TDFN (IPU) V2MON CRITICAL MR* =P1V5S0_EN R79331 0.1UF CRITICAL 5% 1/20W MF 201 59 1% 1/20W MF 201 59 =PP3V3_SUS_PWRCTL C7930 No stuff C7931, 12ms Min delay time U7930 Sense input threhold is 3.07V Worst-Case Thresholds: 6.04K OUT PLACE_NEAR=U7930.6:2.3mm S0PGD_BJT_GND_R 10% 6.3V X5R 201 =P1V8S0_EN 3.3V SUS Detect 61 56 S0PGOOD_ISL PLACE_NEAR=U7720.5:6mm 353S2809 P1V5S0_PGOOD from U7710 R79721 44 Q4 10K 10K OUT R7917 CRITICAL (ISL Version in development) 1% 1/20W MF 201 60 =PBUSVSENS_EN VFRQ Low: Fix Frequency VFRQ High: Variable Frequency 5% 1/20W MF 201 1/20W MF 2012 PLACE_NEAR=U7770.3:6mm 60 OUT NO STUFF S0 Rail PGOOD Circuitry A OUT =P3V3S0_EN CHGR VFRQ Generation TPS3808G33DBVRG4 S0PGOOD_ISL 5% 1/20W MF 201 MAKE_BASE=TRUE 100K 5% pull-down added to PCH page Delete R when 61 61 5.1K 5% 1/20W MF 201 CPUVCCIOS0_EN GND R7918 ASMCC0179 Q2: 0.XXXV Q3: 0.640V 3.3V w/Divider: 2.345V Q4: 0.660V R79601S0PGOOD_ISL 6.04K R79701 1% 39K 5% 1/20W MF 201 =P5VS0_EN C Q3 VMON_Q4_BASE 5% 1/20W MF 201 D G =P5V_3V3_SUS_EN OUT PM_SUS_EN MAKE_BASE=TRUE R7955 S0PGOOD_ISL R7988 20K R7986 MAKE_BASE=TRUE SOD-VESM-HF PM_SLP_SUS_L DFN2015H4-8 NC 5% 1/20W MF 201 SSM3K15FV B PLACE_NEAR=U1800.A15:5mm Q7950 U7940 Y VMON_Q2_BASE R7981 R7931 CHGR_VFRQOUT Q7931 74AUP1G3208 SOT891 A 23 25 40 51 61 17 R7954 61 38 39 =PP3V42_G3H_PWRCTL Thresholds: VDD: 2.734V-3.010V V2MON: 2.815V-3.099V V3MON: 0.572V-0.630V V4MON: 0.572V-0.630V 5% 1/20W MF 201 P1V5S0_EN VCC SMC_BATLOW_L:100K pull up on SMC page SMC_BATLOW_L 41 40 IN 5% 1/20W MF 201 5% 1/20W MF 201 OUT PM_SLP_S3_R_L 33K 10% 6.3V X5R 201 R7953 1K 55 =USB_PWR_EN 10% 6.3V CERM-X5R 402 10K 0.1UF S0PGD_C =PP1V05_S0_VMON R7987 =PP3V3_S5_PWRCTL R7951 60 OUT 0.47UF MAKE_BASE=TRUE 3.3V/5.0V Sus ENABLE 40 61 1% 1/20W MF 201 1K OUT =DDRREG_EN C7912 2 CPUVCCIOS0_PGOOD 150K 61 P1V8S0_EN R7956 7.15K =P3V3S3_EN MAKE_BASE=TRUE 61 B (PM_SLP_S3_R_L) PLACE_NEAR=U7600.3:6mm =PP3V3_S5_VMON R7952 D PLACE_NEAR=U7100.15:6mm =PP3V3_S0_VMON PP1V5_S3RS0 PLACE_NEAR=Q7812.2:6mm 10% 6.3V CERM-X5R 402 5% 1/20W MF 201 PLACE_NEAR=U1800.D4:5mm 5% 1/20W MF 201 10% 10V CERM 402 R7978 IN 100K CPUIMVP_VR_ON 61 58 =PP1V5_S3RS0_VMON 5% 1/20W MF 201 NO STUFF 1K 0.068UF 9.1K PLACE_NEAR=U7400.1:5mm VMON_3V3_DIV 1 C7913 R7912 C7910 R7915 C7943 61 5% 1/20W MF 201 54 OUT NO STUFF 5.1K 0.47UF R7975 1% 1/20W MF 201 R7911 CPUVCORE ENABLE 1% 1/20W MF 201 S0 Rail PGOOD (BJT Version) PLACE_NEAR=U7300.16:6mm 5% 1/20W MF 201 =P5VS3_EN MAKE_BASE=TRUE 100K PLACE_NEAR=U7300.16:6mm PLACE_NEAR=U7940.5:2.3mm 61 P5VS3_EN P3V3S3_EN R7979 5% 1/20W MF 201 C R7910 PM_SLP_S5_L IN S5_PWRGD (old name RSMRST_PWRGD) >SMC SMC >PM_DSW_PWRGD R7976 DDRREG_EN 40 17 PLACE_NEAR=U7400.1:5mm 5% 1/20W MF 201 MAKE_BASE=TRUE PM_SLP_S3_L 5% 1/20W MF 201 MAKE_BASE=TRUE 40 61 40 26 17 0 PM_SLP_S4_L PLACE_NEAR=Q7812.2:6mm IN MAKE_BASE=TRUE OUT MAKE_BASE=TRUE (OD,IPU) GND R7974 48 40 26 17 54 100K 5% pull-down added to PCH page Delete R when 1/20W ALL_SYS_PWRGD R7913 Delete R when pull-down added to PCH page 1 MF 201 61 51 40 25 23 PM_SLP_S3_L 3.3V S4 ENABLE OUT_B DLY THRM PAD 220PF C7942 =P5V3V3_REG_EN OUT DLY_1C 10% 25V X7R-CERM 201 SMC_PM_G2_ENABLE Run (S0) P3V3S5_EN MAKE_BASE=TRUE NC P5V3V3_REG_EN MAKE_BASE=TRUE 2:1 + 1.3V - C7941 100 5% 1/20W MF 201 SLG4AP012 TDFN SMC_PM_G2_EN MAKE_BASE=TRUE 61 R7941 D CRITICAL 40 2.5.0 BRANCH PAGE 79 OF 109 SHEET 61 OF 74 A D D LCD Connector Internal DP Connector: 518S0787 CRITICAL J9000 CABLINE-CA F-RT-SM Pull-ups on panel side, 4.7 kOhm to 3.3V R9061 43 BI =I2C_TCON_SDA 31 65 PPVOUT_SW_LCDBKLT I2C_TCON_SDA_R 5% 1/20W MF 201 NC NC R9062 43 C IN =I2C_TCON_SCL I2C_TCON_SCL_R 5% 1/20W MF 201 CHECK IF LVDS_IG_PANEL_PWR GLITCHES ON POWER UP 65 OUT 65 OUT 65 OUT 65 OUT 65 OUT 65 OUT U9000 =PP3V3_S5_LCD OUT DP_INT_HPD FPF1009 IN LCD_IG_PWR_EN ON VIN_1 VOUT_1 PP3V3_SW_LCD_UF VIN_2 VOUT_2 MIN_LINE_WIDTH=0.30 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=3.3V FERR-120-OHM-1.5A 1K 5% 1/20W MF 201 C9009 0.1UF 2 10% 6.3V X5R 201 11 NC C9015 10% 16V X7R 201 0.1UF C9011 0.1UF 10% 6.3V X5R 201 C9012 69 BI DP_INT_AUX_CH_N 1 1000PF C9024 (DP_INT_AUX_CH_C_N) DP_INT_HPD_CONN 15 16 2 2 10% 16V X5R-CERM 0201 69 BI DP_INT_AUX_CH_P 69 69 69 IN DP_INT_ML_P IN DP_INT_ML_N C9025 B 21 22 69 DP_INT_ML_F_P DP_INT_ML_F_N 24 25 0.1UF 26 (DP_INT_AUX_CH_C_P) 10% 16V X5R-CERM 0201 10% 16V X5R-CERM 0201 69 20 23 69 0.1UF 19 DP_INT_AUX_CH_C_N DP_INT_AUX_CH_C_P 69 C9020 18 MIN_LINE_WIDTH=0.30 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=3.3V 5% 1/20W MF 201 CRITICAL 69 DP_INT_ML_C_P 27 28 29 12-OHM-100MA-8.5GHZ TCM0806-4SM SYM_VER-2 PLACE_NEAR=J9000.24:1mm PLACE_NEAR=J9000.25:1mm R9018 C9021 0.1UF DP_INT_ML_F_P DP_INT_ML_F_N FL9000 69 DisplayPort I/F 17 PP3V3_SW_LCD 10UF 20% 6.3V X5R 603 14 R9070 100K 12 13 6 0402-LF THRM PAD C LED Backlight I/F 10 5% 1/20W MF 201 L9004 MFET-2X2-8IN GND R9014 LED_RETURN_6 LED_RETURN_5 LED_RETURN_4 LED_RETURN_3 LED_RETURN_2 LED_RETURN_1 R9060 CRITICAL 2 69 DP_INT_ML_C_N 1M 1M 5% 1/20W MF 201 5% 1/20W MF 201 30 R9017 33 34 35 B 36 C9022 0.1UF 69 IN DP_INT_ML_P 10% 16V X5R-CERM 0201 CRITICAL 37 FL9001 69 DP_INT_ML_C_P 38 12-OHM-100MA-8.5GHZ TCM0806-4SM SYM_VER-2 39 40 10% 16V X5R-CERM 0201 69 IN DP_INT_ML_N C9023 41 0.1UF 2 69 DP_INT_ML_C_N 32 10% 16V X5R-CERM 0201 R9050 1 R9080 PLACE_NEAR=J9000.3:2mm 100K 100K C9017 5% 1/20W MF 201 5% 1/20W MF 201 1000PF A 2 5% 50V C0G-CERM 603 SYNC_MASTER=K21_MLB SYNC_DATE=12/13/2010 PAGE TITLE Internal DisplayPort Connector DRAWING NUMBER Apple Inc 051-8871 R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED SIZE D REVISION 2.5.0 BRANCH PAGE 90 OF 109 SHEET 62 OF 74 A 69 C9300 DP_EXTA_ML_C_P IN 69 C9301 DP_EXTA_ML_C_N IN 10% 16V X5R-CERM 63 69 0201 DP_EXTA_ML_N 10% 16V X5R-CERM 0.1UF GND_VOID=TRUE DP_EXTA_ML_P 0.1UF 63 69 71 33 OUT 71 33 OUT 0201 C9370 (C9370/C9371) T29_D2R_N T29_D2R_P C9302 DP_EXTA_ML_C_P IN 1 10% 16V X5R-CERM 69 C9303 DP_EXTA_ML_C_N IN 69 D C9304 DP_EXTA_ML_C_P IN C9305 DP_EXTA_ML_C_N IN DP_EXTA_ML_N 10% 16V X5R-CERM 71 33 63 69 IN T29_R2D_C_N T29_R2D_C_P C9372 DP_EXTA_ML_P C9373 0201 10% 16V X5R-CERM 71 63 69 0201 caps to improve layout D9372 1/20W 201 10% 16V X5R-CERM 0.1UF 69 C9307 DP_EXTA_ML_C_N IN DP_EXTA_ML_P 0201 DP_EXTA_ML_N 10% 16V X5R-CERM 0.1UF 63 69 63 69 C9308 DP_EXTA_AUXCH_C_P BI R9309 10% 16V X5R-CERM 0.1UF 69 C9309 DP_EXTA_AUXCH_C_N BI OUT 5% MF 1/20W 201 DP_EXTA_AUXCH_N 10% 16V X5R-CERM (C9382.2) 71 33 IN 71 33 IN T29_R2D_C_N T29_R2D_C_P T29 Path Biasing R9308/R9309 maintain bias on C9308/C9309 5% MF R9354 to prevent spikes when U9310 AUXDDC_OFF 1/20W 201 5% MF 30 5% 1/20W MF 201 DP A Super-Driver =PP3V3_S0_DPSDRVA R9355 5% C9311 5% MF 69 63 69 63 69 63 69 63 69 63 1K 5% 1/20W MF 201 69 63 5% 1/20W MF 201 IN BI 69 63 69 63 R9312 1K OUT 5% 1/20W MF 201 B 43 IN 43 BI DP_EXTA_ML_P DP_EXTA_ML_N DP_EXTA_ML_P DP_EXTA_ML_N DP_EXTA_DDC_CLK DP_EXTA_DDC_DATA DP_EXTA_AUXCH_P DP_EXTA_AUXCH_N DP_EXTA_HPD 10 13 16 15 26 DPSDRVA_I2C_ADDR0 DPSDRVA_I2C_ADDR1 36 =I2C_DPSDRVA_SCL =I2C_DPSDRVA_SDA DP_AUXCH_ISOL_R 14 DPSDRVA_I2C_CTL_EN DPSDRVA_REXT R9390 DP_AUXCH_ISOL IN_D0P IN_D0N C9361 R9352 63 OUT_D0P OUT_D0N OUT_D1P OUT_D1N 30 71 29 71 28 71 27 71 OUT_D2P OUT_D2N 25 71 24 71 IN_D3P IN_D3N OUT_D3P OUT_D3N 23 71 22 71 IN_SCL IN_SDA AC_AUXP AC_AUXN 20 71 19 71 IN_D2P IN_D2N 5% 1/20W MF 201 35 38 37 12 39 34 I2C_ADDR0 I2C_ADDR1 DP_SDRVA_ML_C_P DP_SDRVA_ML_C_N DP_SDRVA_ML_C_P DP_SDRVA_ML_C_N R9319 4.99K 5% 1/20W MF 201 C9367 DP_SDRVA_ML_C_P DP_SDRVA_ML_C_N 1 C9369 71 CA_DET DP_A_CA_DET CEXT 11 DPSDRVA_CEXT IN 63 C9368 0.1UF C9319 63 AUXDDC_OFF 51 1.5K 1.5K R9366 DP_A_BIAS_P_2 2 201 1/20W 201 5% MF 1/20W 201 DP_A_BIAS_N_0 1/20W MF PLACE_NEAR=C9361.1:2mm 5% 1/20W R9363 PLACE_NEAR=C9361.1:2mm 51 C VOLTAGE=3.3V 51 MF 5% VOLTAGE=3.3V 5% MF 201 5% MF MF 5% 1/20W 1/20W 201 R9367 PLACE_NEAR=C9361.1:2mm 1/20W 201 DP_A_BIAS_P_0 51 MF 5% 1/20W PP3V3_SW_DPAPWR 71 31 30 DP_SDRVA_ML_N DP_SDRVA_ML_P 0201 71 71 10% 16V X5R-CERM D0+A D0-A 27 26 D1+A D1-A DP_SDRVA_AUXCH_P DP_SDRVA_AUXCH_N 19 18 AUX+A AUX-A DP_SDRVA_HPD 17 HPD_A T29_A_RSVD_N T29_A_RSVD_P 25 24 D0+B D0-B R9393 51 2 5% 1/20W MF 201 TQFN R9396 D0+ D0- 1K PP3V3_SW_DPAPWR 5% 1/20W MF 201 Must be 3.3V DP A port power C9331 R9338 0.1UF 5% 1/20W MF 201 T29_D2R1_BIASP T29_D2R1_BIASN 15 14 AUX+B AUX-B 13 HPD_B 64 63 DP_A_PWRDWN T29_A_BIAS CBTL04DP081 (353S3151) and PI3vEDP212 (353S3055) are footprint-compatible parts with similar pinouts NXP uses pin 10 for ML and HPD, Pericom uses pin 10 for ML and pin 11 for HPD 10K 10% 16V X5R-CERM 0201 63 10 32 11 C9391 0.1UF T29DPA_ML_N T29DPA_ML_P 10% 16V X5R-CERM 0201 OUT 64 71 64 71 BI T29: Unused CRITICAL D1+ D1- T29DPA_ML_N T29DPA_ML_P AUX+ AUX- 23 22 R9397 1K 5% 1/20W MF 201 R9399 64 71 BI OUT 64 71 B T29: LSX_A_R2P/P2R (P/N) (T29_A_LSX_P2R) (T29_A_LSX_R2P) NC 5% 1/20W MF 201 0201 1 10% 16V X5R-CERM 0201 100K VDD U9390 PI3VEDP212 DP_SDRVA_ML_N DP_SDRVA_ML_P C9390 0.1UF Port A MCU 1/20W 201 R9362 0201 5% 1/20W MF 201 1.5K 64 63 51 10% 16V X5R-CERM 0201 1/20W 201 Must be 3.3V DP A port power R9392 5% MF DP_A_BIAS_N_2 201 0201 THMPAD OMIT_TABLE VOLTAGE=3.3V (IPD) VDD DP/T29 A Low-Speed MUX IC supports input high while Vcc = 0V 68 U9330 64 71 DP_A_BIAS (IPD) CRITICAL 64 71 OUT 0201 68 0.1UF OUT SC70 2 C9330 201 5% MF 1 1.5K 5% MF U9359 71 1.5K GND_VOID=TRUE R9385 DP_A_PWRDWN 64 71 GND_VOID=TRUE R9384 CRITICAL 2.2UF REXT 1.5K R9364 71 20% 6.3V CERM 402-LF 64 63 10% 16V X5R-CERM 0.1UF 32 GND_VOID=TRUE DP Path Biasing R9360 64 71 IN VOLTAGE=3.3V R9361 IN TSLP-2-7 (D9382/D9383) 6.3V 0201 71 SIGNAL_MODEL=T29PIN DP_SDRVA_ML_P DP_SDRVA_ML_N AUXCH Snoop Port, used by PS8301 during training (DP_SDRVA_HPD) PLACE_NEAR=C9361.1:2mm 20% X5R 1/20W 201 (D9382/D9383) (D9361.2) 74LVC1G04DBDCK 10% 16V X5R-CERM 0.1UF TSLP-2-7 (D9360/D9361) 71 6.3V 0201 C9359 10% 16V X5R-CERM 0.1UF C9366 DP_SDRVA_AUXCH_C_P DP_SDRVA_AUXCH_C_N SCL_CTL SDA_CTL PD 20% X5R 5% MF T29: TX_1 T29DPA_ML_C_P T29DPA_ML_C_N TSLP-2-7 CRITICAL (All D’s) =PP3V3_S0_DPSDRVA 0201 1/20W 201 TSLP-2-7 BAR90-02LRH R9365 10% 16V X5R-CERM 0.1UF D9361 1/20W 201 DP_SDRVA_ML_P DP_SDRVA_ML_N PLACE_NEAR=U9310.11:2 mm PS8301 has internal ~150K pull-down on PD pin Okay to drive this pin even when VCC=0V per Parade (pin is 5V-tolerant) 2 1% 1/20W MF 201 31 1 5% MF (D9360.2) GND_VOID=TRUE 5% 1/20W MF 201 10% 16V X5R-CERM 0.1UF C9362 (DP_SDRVA_AUXCH_P) (DP_SDRVA_AUXCH_N) 17 1.5K SIGNAL_MODEL=EMPTY 10% 6.3V X5R 201 (IPD) R9318 OUT_HPD (IPD) DP_A_PWRDWN_R 18 (IPU) GND SDRV_PD OUT_AUXP_SCL OUT_AUXN_SDA (IPD) I2C_CTL_EN 5% MF 64 71 D GND_VOID=TRUE GND_VOID=TRUE 6.3V 0201 DP_SDRVA_ML_C_P DP_SDRVA_ML_C_N C9363 BAR90-02LRH 0.1UF IN_D1P IN_D1N IN_HPD 71 20% X5R 0.22UF 270 CRITICAL IN_AUXP IN_AUXN 71 0.22UF R9310 1K 2 D9383 R9383 6.3V 0201 DP_EXTA_ML_P DP_EXTA_ML_N 1 BAR90-02LRH SIGNAL_MODEL=EMPTY 20% X5R C9360 DP_SDRVA_ML_R_P DP_SDRVA_ML_R_N 1/20W 201 VDD 22 R9311 DP_EXTA_ML_P DP_EXTA_ML_N 1.5K BAR90-02LRH D9382 201 71 30 T29_R2D_P T29_R2D_N 0.22UF MF 71 R9351 C9365 R9375 1.5K 29 20 16 12 69 63 69 63 IN 10% 16V X5R-CERM 0201 QFN NO STUFF 23 16 1/20W 201 PS8301TQFN40GTR-A2 Note: Other Parade devices use 96/B6, so only 94/B4 are used for this part D9360 1/20W 201 64 71 OUT GND_VOID=TRUE R9374 SIGNAL_MODEL=EMPTY GND_VOID=TRUE 20% 4V CERM-X5R-1 201 0.22UF U9310 Addr (W/R) 0x96/0x97 0xB6/0xB7 0x94/0x95 0xB4/0xB5 0.1UF 30 71 C9364 DP_SDRVA_ML_R_P DP_SDRVA_ML_R_N 41 A0 1 2 71 C9312 10% 16V X5R-CERM 0201 33 A1 0 1 0.1UF 40 21 2.2UF 1/20W R9350 5% MF 30 71 T29_A_BIAS_R2DN1 IN GND_VOID=TRUE D9364/D9365: 270 20% 6.3V CERM 402-LF 1 5% MF OUT TSLP-2-7 SIGNAL_MODEL=T29PIN SIGNAL_MODEL=EMPTY 71 20% 4V CERM-X5R-1 201 1/20W 201 transitions from high to low R9353 C C9383 (C9383.2) R9382 1.5K 0.47UF R9308 C9310 0.47UF GND_VOID=TRUE D9372/D9373: GND_VOID=TRUE 64 71 (D9372/D9373) (D9365.2) T29_D2R_C_P T29_D2R_C_N 20% 4V CERM-X5R-1 201 63 69 1M PS8301 I2C Addresses: C9382 0201 If GPU uses common pins for AUX_CH and DDC, alias nets together at GPU 63 GND_VOID=TRUE 63 69 CRITICAL (All D’s) 20% 4V CERM-X5R-1 201 0.47UF C9381 TSLP-2-7 63 0201 0.1UF 71 33 T29_D2R_N T29_D2R_P DP_EXTA_AUXCH_P OUT 0.47UF 1M 69 =PP3V3_S0_DPSDRVA 0201 71 33 C9380 (C9380/C9381) BAR90-02LRH 1 D9365 C9306 DP_EXTA_ML_C_P IN T29: TX_0 T29DPA_ML_C_P T29DPA_ML_C_N TSLP-2-7 GND_VOID=TRUE 5% MF 64 71 IN (D9364.2) GND_VOID=TRUE BAR90-02LRH SIGNAL_MODEL=EMPTY IN TSLP-2-7 D9373 GND_VOID=TRUE 69 BAR90-02LRH R9373 BAR90-02LRH T29_R2D_P T29_R2D_N 1.5K 20% 4V CERM-X5R-1 201 T29_A_BIAS_R2DP1 IN 1/20W 201 GND_VOID=TRUE P/N-swapped after AC DP_EXTA_ML_N 71 T29_A_BIAS_R2DN0 IN 5% MF SIGNAL_MODEL=EMPTY 20% 4V CERM-X5R-1 201 R9372 1.5K 0.47UF T29 signals are 63 69 0.47UF GND_VOID=TRUE (C9373.2) 10% 16V X5R-CERM 0.1UF IN 0201 0.1UF 69 71 33 0.1UF (C9372.2) 63 69 0201 D9364 GND_VOID=TRUE 20% 4V CERM-X5R-1 201 GND_VOID=TRUE DP_EXTA_ML_P 0.1UF T29_D2R_C_P T29_D2R_C_N 20% 4V CERM-X5R-1 201 0.47UF C9371 0.47UF 69 T29 A High-Speed Signals T29_A_BIAS_R2DP0 IN D1+B D1-B DP_A_EXT_AUXCH_P DP_A_EXT_AUXCH_N BI 64 71 BI 64 71 T29: RX_1 Bias Sink HPD DP_A_EXT_HPD SEL AUX_SEL HPD_SEL IN 41 63 R9398 100K LO=Port A HI=Port B 5% 1/20W MF 201 THMPAD GND 28 21 33 LPC1112A =T29_WAKE_L: 33 IN 43 IN 17 33 OUT 33 OUT =I2C_T29AMCU_SCL =I2C_T29AMCU_SDA T29DPA_HPD T29_A_BIAS T29_LSOE T29_LSOE OUT T29_MCU_INT_L 43 BI 64 IN 64 63 Desktops use PCIe WAKE# Mobiles use S4 WAKE# T29_LSEO OUT =T29_WAKE_L OUT 10 11 12 13 14 OMIT R9330 18 SWCLK 15 HVQFN25 RESET#/PIO0_0 PIO0_1/CLKOUT PIO0_2/SSEL/CT16B0_CAP0 5% 1/20W MF 201 63 R/PIO1_0/AD1 R/PIO1_1/AD2 R/PIO1_2/AD3 (IPU) SWDIO/PIO1_3/AD4 PIO1_4/AD5/WAKEUP PIO0_4/SCL (OD) PIO0_5/SDA (OD) PIO0_6/SCK PIO1_6/RXD PIO0_7/CTS# PIO1_7/TXD PIO0_8/MISO/CT16B0_MAT0 PIO1_8/CT16B1_CAP0 PIO0_9/MOSI/CT16B0_MAT1 SWCLK/PIO0_10/SCK/CT16B0_MAT2 (OD) R/PIO0_11/AD0 (OD) THRM XTALIN VSS PAD A DP_A_PWRDWN T29DPA_CONFIG1_RC T29DPA_CONFIG2_RC T29_A_HV_EN_R T29_A_UC_ADDR DP_A_EXT_HPD 16 17 18 19 20 T29_A_LSX_P2R T29_A_LSX_R2P T29_LSEO 23 24 IN 64 R9334 10K T29_A_HV_EN R9335 1K 5% 1/20W MF 201 41 63 35 64 P2R = Plug to Receptacle R2P = Receptacle to Plug IN DRAWING NUMBER 1M R9336 5% 1/20W MF 201 Apple Inc 5% 1/20W MF 201 NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED 051-8871 SIZE D REVISION R R9330 provides pads for programming/debug of MCU, please make accessible If project has space for 10-pin programming header it should be used SYNC_DATE=12/13/2010 PAGE TITLE R9339 SWDIO SYNC_MASTER=K21_MLB DisplayPort/T29 A MUXing T29_A_UC_ADDR Note: U9390 ML/HPD defaults to T29 mode so that DP/T29 Display can detect host T29 support using I2C pull-ups on ML U9390 AUX defaults to DP mode because 100-ohm pull-downs would defeat DP Sink’s detection of DP Source 33 10K OUT 5% 1/20W MF 201 63 2 IN 64 I2C Addr: 0x26/0x27 (Wr/Rd) 25 63 DP_A_CA_DET 21 63 2.5.0 BRANCH PAGE 93 OF 109 SHEET 63 OF 74 A 3.3V/HV Power MUX SI8409DB: Vds(max): Vgs(max): Vgs(th): Rds(on): Id(max): 20V Max R9416 C9410 470K 5% 1/20W MF 201 0.1UF 10% 50V X7R 603-1 VIN VOUT PPHV_SW_DPAPWR QFN DPAPWRSW_HVEN_L_R 10% 50V X7R 603-1 ILIM GND 1% 1/20W MF 201 STPS2L30AF TP_DPAPWRSW_FLT_L 13 14 5% 1/20W MF 201 5% 1/20W MF 201 100K 1% 1/20W MF 201 1% 1/20W MF 201 OUT FB PGND DPAPWR_BLDR_E PLACE_NEAR=C9490.1:2mm 71 63 OUT 5% 1/20W MF 201 OUT VOLTAGE=3.3V B 8 IN IN T29_A_BIAS_D2RP1 71 63 BI 71 63 BI T29_A_BIAS_D2RN1 2 D 2.2K 2.2K 5% 1/20W MF 201 5% 1/20W MF 201 GND_VOID=TRUE 71 63 71 63 OUT OUT R9499 2 C9400 MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=15V OUT T29DPA_HPD 63 OUT T29DPA_CONFIG1_RC 63 OUT T29DPA_CONFIG2_RC R9452 10% 50V X7R 402 1M 5% 1/20W MF 201 2 5% 1/20W MF 201 10K 2 5% 1/20W MF 201 T29_A_HV_EN 2 DP Dir CRITICAL DP Dir 0.1UF GND_VOID=TRUE C9470 T29 Dir 71 GND_VOID=TRUE GND_VOID=TRUE 13 10 12 14 16 18 20 GND_DPACONN_8 MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=0V C9471 HOT_PLUG_DETECT GND CONFIG1 ML_LANE0P CONFIG2 ML_LANE0N GND GND ML_LANE3P ML_LANE1P ML_LANE3N ML_LANE1N GND GND AUX_CHP ML_LANE2P AUX_CHN ML_LANE2N DP_PWR RETURN 11 15 17 19 GND_DPACONN_7 R9406 0.1UF 12 GND_DPA7_R MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=0V 5% 1/20W MF 201 10% 6.3V X5R 201 2 10% 16V X7R 201 330PF 2 10% 16V X7R 201 IN 63 71 T29DPA_ML_C_P T29DPA_ML_C_N IN 63 71 IN 63 71 5% 1/20W MF 201 C9402 0.01UF 10% 50V X7R 402 L9408 GND_DPACONN_19 R9401 C9401 12 1 5% 1/20W MF 201 R9472 GND_VOID=TRUE 0603 5% 1/20W MF 201 R9473 470K 5% 1/20W MF 201 R9408 12 5% 1/20W MF 201 10% 50V X7R 402 470k R’s for ESD protection on AC-coupled signals SYNC_MASTER=K21_MLB DisplayPort/T29 A Connector 5% 1/20W MF 201 DRAWING NUMBER Apple Inc Sink HPD range: High: 2.0 - 5.0V Low: - 0.8V SYNC_DATE=12/13/2010 PAGE TITLE R9441 100K B 63 71 20% 4V CERM-X5R-1 201 470K MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=0V 0.01UF 2 051-8871 NOTICE OF PROPRIETARY PROPERTY: SIZE D REVISION R THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED BI 20% 4V CERM-X5R-1 201 0.47UF GND_VOID=TRUE MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=15V C9473 FERR-120-OHM-3A 5% 1/20W MF 201 GND_VOID=TRUE 0.47UF T29DPA_ML_P T29DPA_ML_N T29DPA_HPD_R C9499 C9495 T29DPA_ML_P T29DPA_ML_N R9471 470K 5% 1/20W MF 201 T29: TX_1 12 1 5% 50V CERM 402 63 71 (Both C’s) R9402 30PF 63 71 IN GND_VOID=TRUE R9470 C9472 71 DPACONN_20_RC IN 20% 4V CERM-X5R-1 201 470K T29DPA_ML_C_P T29DPA_ML_C_N T29: LSX_R2P/P2R (P/N) 71 SIGNAL_MODEL=EMPTY 330PF GND_VOID=TRUE L9499 C9494 20% 4V CERM-X5R-1 201 0.47UF SHIELD PINS 650NH-5%-0.430MA-0.052OHM 1 0.47UF T29DPA_ML_P T29DPA_ML_N GND_VOID=TRUE SIGNAL_MODEL=EMPTY T29DPA_D2R1_AUXCH_P T29DPA_D2R1_AUXCH_N 2 (Both C’s) 10% 6.3V X5R 201 71 CRITICAL C Circuit threshold range: 2.877-2.941V (2.903V nominal) GND_DPACONN_1 5% 1/20W MF 201 71 DPAPWR_FB_DIV PP3V3RHV_SW_DPAPWR MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=15V 0603 0603 35 63 64 24.9K MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=0V SIGNAL_MODEL=EMPTY DP Source must pull down HPD input with greater than or equal to 100K (DPv1.1a) 1M 1% 1/20W MF 201 R9432 12 TSLP-2-7 R9451 NO STUFF C9405 DP_A_EXT_AUXCH_P DP_A_EXT_AUXCH_N 1 GND_VOID=TRUE 30PF 63 C9406 5% 50V CERM 402 R9436 GND_VOID=TRUE R9403 C9498 A DPAPWRSW_HV_DET 0.01UF 0603 BI R9437 DisplayPort/T29 A Connector L9400 5% 1/20W MF 201 71 2 T29: TX_0 (Both L’s) 71 63 G 5% 1/20W MF 201 FERR-120-OHM-3A CRITICAL BI 1K 5% 1/20W MF 201 R9495 GND_VOID=TRUE SIGNAL_MODEL=T29PIN 71 63 S F-RT-TH TSLP-2-7 D9499 S MF GND 201 S SIGNAL_MODEL=T29PIN BAR90-02LRH 1% 1/20W L9498 SOT353 FB PGND 100K 650NH-5%-0.430MA-0.052OHM D9498 G 220 T29DPA_ML_P T29DPA_ML_N BAR90-02LRH SOT563 Q9419 GND_VOID=TRUE 10% 10V X5R 402 10% 16V X5R-CERM 0201 ZXRE060A 1UF Q9430 C9435 0.1UF R9435 R9433 G SIGNAL_MODEL=EMPTY T29_D2R_C_P T29_D2R_C_N D SSM6N37FEAPE 28 27 26 25 24 23 22 21 SIGNAL_MODEL=EMPTY 1 IN OUT DPAPWRSW_NPN_E CRITICAL 5% 1/20W MF 201 10% 16V X5R-CERM 0201 T29: Unused R9498 C9429 1K SIGNAL_MODEL=EMPTY 82 GND_VOID=TRUE 1K T29_A_BIAS_R SOT363 0.1UF DMB53D0UV R9494 T29_A_BIAS MIN_LINE_WIDTH=0.20 MM MIN_NECK_WIDTH=0.20 MM GND_VOID=TRUE MMDT3946XG 5% 1/20W MF 201 MDP-K21-K78 5% 1/20W MF 201 D DPAPWRSW_ON_C J9400 51 Q9426 T29_D2R_C_P T29_D2R_C_N R9490 20% 6.3V POLY-TANT CASE-B2-SM NO STUFF T29 Dir OUT D SSM6N37FEAPE R9418 10% 6.3V X5R 201 71 63 R9429 DPAPWR_BLDR_B Note: Bleeder active when DPAPWRSW_HV_DET is HIGH and T29_A_HV_EN is LOW 0.1UF 20% 6.3V X5R-CERM-1 603 CRITICAL Q9430 ZXRE060A REF range: 0.595-0.605V (0.600V nominal) Circuit threshold range: 3.363-3.439V (3.395V nominal) C9490 100UF 2 T29_A_HV_EN T29_A_BIAS 10% 16V X5R-CERM 0201 C9487 U9435 SOT-563 61 IN CRITICAL 22UF GND PP3V3RHV_SW_DPAPWR_UF IN C9480 DPAPWRSW_HV_DET_L SOT353 SOT-563 64 63 64 63 Bleeder Resistor R9419 IN 10% 16V X5R-CERM 0201 CERM-X5R 10% 6.3V DMB53D0UV 2.5V / 249 ohm = 10mA P = ~27mW 64 63 35 0.1UF DPAPWRSW_P3V3_ON 4.7K CRITICAL Q9419 5% 1/20W MF 201 1 0.1UF 10% 16V X5R-CERM 0201 249 4.7K 5% 1/20W MF 201 C9481 0.1UF SOT563 C9426 1% 1/20W MF 201 C9485 C9436 ZXRE060A = CCT * 1000000 R9430 1K DPAPWRSW_HV_DET_R_L IN TFLT = CCT * 38900 0.47UF 402 21.5K R9411 210K 5% 1/20W MF 201 2 R9428 R9410 ILIM = 201k / RLIM = 957mA S 1 R9426 G C C9424 DPAPWRSW_VREF TSD DPAPWRSW_P3V3_ON_L DPAPWR_ON_L_C IFLT = 200k / RFLT = 2A SOD-VESM-HF 20% 6.3V X5R 603 3.3V Always U9426 D =DPAPWRSW_EN DPAPWRSW_IFLT Q9415 EN 4.7K 22 100K 5% 1/16W MF-LF 402 SSM3K15FV CRITICAL C9486 OC* =PP3V3_S4_DPAPWRSW IN GND R9412 R9424 R9427 DPAPWRSW_ILIM IFLT THRM PAD Blocking FET, off when Source >3.4V or HV_EN high R9425 SM 17 CT T29_A_HV_EN 10UF (IPU-Weak!) DPAPWRSW_CT 64 63 35 SI8409DB 3.3V/HV MUXed D9410 C9411 FLT* 15 RTRY* Q9425 OUT 0.1UF SN1010017 16 EN* BGA CRITICAL MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=15V U9410 TPS2051B SOT23 DFLS1100 CRITICAL (*) U9410 tolerance unknown 10 11 12 DP_PWR must be S4/S5 to support wake from T29 devices U9480 G -30V +/-12V -1.4V 65mOhm @ 2.5V Vgs 3.7A @ 70C D =PPHV_SW_DPAPWRSW Max 894mA (*) 1A (*) 26.7ms 724ms S IFLT ILIM TFLT TSD Min 876mA 925mA 13.4ms 235ms CRITICAL POWERDI-123 Nominal 885mA 935mA 18.3ms 470ms Port A 3.3V Power Switch D9425 Port A HV Power Switch CRITICAL PP3V3_SW_DPAPWR MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=3.3V D 63 2.5.0 BRANCH PAGE 94 OF 109 SHEET 64 OF 74 A PPBUS S0 LCDBkLT FET MOSFET FDC638APZ CHANNEL P-TYPE RDS(ON) 43 mOhm @4.5V LOADING 0.65 A (EDP) CRITICAL Q9706 FDC638APZ_SBMS001 SSOT6-HF BOTTOM C9782 R9788 PPBUS_S0_LCDBKLT_FUSED MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.6V 603-HF AND PPBUS_SW_BKL =PPBUS_S0_LCDBKLT PPBUS_SW_LCDBKLT_PWR ON THE SENSOR PAGE 10% 16V 1% 1/20W X5R MF *LCD_BKLT_PWM SHOULD BE AWAY FROM BOOST CIRCUIT =PP5V_S0_BKL PLACE_NEAR=L9701.2:3mm CRITICAL 2 D9701 15UH-2.8A LCDBKLT_EN_DIV =PPBUS_SW_BKL C9712 R9789 PIMB053T-SM 1 10UF 10% 25V X5R 805 1% 1/20W MF SOD-123 CRITICAL 147K CRITICAL L9701 402 201 D *C9797 AND C9799 SHOULD BE PLACED IN T-BONE FOR ACOUSTICS *PPBUS_SW_LCDBKLT_PWR_SW SHOULD BE KEPT AS SHORT AS POSSIBLE 0.1UF 301K THERE IS A SENSE RESISTOR BETWEEN D 65 MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.6V F9700 3AMP-32V-467 PPBUS_SW_LCDBKLT_PWR C9713 0.1UF 2 10% 25V X5R 402 PPBUS_SW_LCDBKLT_PWR_SW MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.375 MM VOLTAGE=50V SWITCH_NODE=TRUE DIDT=TRUE PPVOUT_SW_LCDBKLT CRITICAL RB160M-60G C9796 220PF 201 PLACE_NEAR=L9701.1:3mm PLACE_NEAR=U9701.A5:3mm PLACE_NEAR=L9701.1:3mm CRITICAL C9797 10UF 10% 50V X7R-CERM 402 C9799 62 MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.375 MM VOLTAGE=50V 10UF 10% 50V X5R 1210-1 10% 50V X5R 1210-1 PLACE_NEAR=D9701.2:5mm LCDBKLT_EN_L PLACE_NEAR=D9701.2:3mm PLACE_NEAR=U9701.D1:5mm Q9707 D IN G 1 2 10V X5R C9714 1UF 10% 25V X5R 603-1 SOT563 PLACE_NEAR=U9701.D1:3mm C9710 SSM6N15FEAPE S 0.01UF 10% XW9720 SM 201 PPVOUT_SW_LCDBKLT_FB VOLTAGE=50V MIN_LINE_WIDTH=0.1 MM MIN_NECK_WIDTH=0.1 MM =PP3V3_S0_BKL_VDDIO LCD_BKLT_EN PLACE_NEAR=U9701.C4:4mm LCDBKLT_DISABLE Q9707 C9711 D PLACE_NEAR=C9797.1:5mm 0.1UF 10% 6.3V X5R 201 SSM6N15FEAPE SOT563 C C C1 BKLT_PLT_RST_L D1 IN S C4 25 G VIN VDDIO VLDO U9701 25-BUMP-MICRO 5% 1/20W MF 201 5% 1/20W MF 201 PPBUS_SW_LCDBKLT_PWR 65 200K B 1% 1/20W MF 201 R9704 IN LCD_BKLT_PWM 33 5% 1/20W MF 201 BKL_SCL BKL_SDA D3 BKL_PWM BKL_EN A4 PWM A3 EN R9715 D4 C3 TP_BKL_FAULT A5 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm SCLK SDA FAULT PLACE_SIDE=BOTTOM 100K 2 R9717 FB PLACE_NEAR=U9701.E5:10mm 1% 1/20W MF 201 Fpwm=9.62kHz see spec for others C9704 33PF 5% 25V OUT1 E5 OUT2 OUT3 D5 C5 BKL_ISEN1 BKL_ISEN2 BKL_ISEN3 OUT4 OUT5 E3 BKL_ISEN4 OUT6 E1 E2 R9755 201 10K 5% 1/20W MF 201 R97161 90.9K 1% 1/20W MF 201 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm OUT 62 OUT 62 OUT 62 OUT 62 OUT 62 OUT 62 R9718 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm BKL_ISEN5 BKL_ISEN6 LED_RETURN_2 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm 5% 1/16W MF-LF 402 BOTTOM BKLT:PROD B R9719 PLACE_NEAR=U9701.C5:10mm MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm LED_RETURN_3 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm 5% 1/16W MF-LF 402 BOTTOM BKLT:PROD R9714 R9720 18.2K LED_RETURN_1 BKLT:PROD PLACE_NEAR=U9701.D5:10mm I_LED=20.3mA NP0-C0G 5% 1/16W MF-LF 402 BOTTOM R9731 BKLT:PROD B2 GND_SW GND_SW Addr: 0x58(Wr)/0x59(Rd) FSET B1 A2 B4 ISET GND_L =I2C_BKL_1_SDA BKL_FSET B3 SW_0 SW_1 E4 BI R9757 43 FILTER BKL_ISET 5% 1/20W MF 201 C2 GND_S IN BKL_FLTR B5 43 VSYNC A1 R9753 =I2C_BKL_1_SCL 10K D2 LP8550 R9741 BKL_VSYNC_R PLACE_NEAR=U9701.E3:10mm 1% 1/20W MF 201 XW9710 SM GND_BKL_SGND 1 PLACEMENT_NOTE=Keep away from noise nodes(E4, A1, A2, B1, B2 pins) MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm LED_RETURN_4 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm 5% 1/16W MF-LF 402 BOTTOM BKLT:PROD MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=0V R9721 PLACE_NEAR=U9701.E2:10mm I_LED=369/Riset (EEPROM should set EN_I_RES=1) MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm LED_RETURN_5 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm 5% 1/16W MF-LF 402 BOTTOM BKLT:PROD R9722 PLACE_NEAR=U9701.E1:10mm MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm BOTTOM A PART NUMBER 103S0198 103S0198 QTY 3 DESCRIPTION RES,THIN FLIM,1/16W,10.2 OHM,0.1,0402,SM RES,THIN FLIM,1/16W,10.2 OHM,0.1,0402,SM REFERENCE DES CRITICAL BOM OPTION BKLT:ENG R9717,R9718,R9719 BKLT:ENG R9720,R9721,R9722 LED_RETURN_6 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm 5% 1/16W MF-LF 402 SYNC_MASTER=K21_MLB 10.2 ohm resistors for current SYNC_DATE=12/13/2010 PAGE TITLE LCD Backlight Driver measurement on LED strings DRAWING NUMBER Apple Inc 051-8871 R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED SIZE D REVISION 2.5.0 BRANCH PAGE 97 OF 109 SHEET 65 OF 74 A CPU Signal Constraints CPU Net Properties TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP CPU_50S * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD NET_TYPE ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM CPU_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD TABLE_PHYSICAL_RULE_ITEM CPU_27P4S * =27P4_OHM_SE =27P4_OHM_SE =27P4_OHM_SE =27P4_OHM_SE MIL MIL CPU_XDP_BPM TOP,BOTTOM 100 MIL 100 MIL 100 MIL 100 MIL =STANDARD =STANDARD DMI_S2N DMI_S2N DMI_N2S DMI_N2S PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE PCIE PCIE PCIE DMI_S2N_P DMI_S2N_N DMI_N2S_P DMI_N2S_N FDI_DATA FDI_DATA PCIE_85D PCIE_85D CPU_50S CPU_50S PCIE PCIE CPU_AGTL CPU_AGTL FDI_DATA_P FDI_DATA_N FDI_FSYNC FDI_LSYNC CPU_50S CPU_AGTL FDI_INT 17 CPU_PECI CPU_50S PCIE CPU_PECI 10 19 40 PM_SYNC PM_MEM_PWRGD CPU_50S CPU_50S CPU_AGTL CPU_AGTL PM_SYNC PM_MEM_PWRGD CPU_50S CPU_ITP XDP_DBRESET_L 10 23 25 CPU_50S CPU_50S CPU_ITP CPU_ITP XDP_CPU_PRDY_L XDP_CPU_PREQ_L 10 23 CPU_50S CPU_50S CPU_27P4S CPU_27P4S CPU_27P4S CPU_50S CPU_50S CPU_50S CPU_AGTL CPU_AGTL CPU_COMP CPU_COMP CPU_COMP CPU_ITP CPU_AGTL CPU_AGTL PM_EXT_TS_L PM_EXT_TS_L CPU_SM_RCOMP CPU_SM_RCOMP CPU_SM_RCOMP CPU_CFG CPU_CATERR_L CPU_VCCIO_SEL CPU_PROCHOT_L CPU_PWRGD CPU_50S CPU_50S CPU_AGTL CPU_AGTL CPU_PROCHOT_L CPU_PWRGD PM_THRMTRIP_L CPU_50S CPU_8MIL PM_THRMTRIP_L DMI_CLK100M DMI_CLK100M DPLL_REF_CLK120M DPLL_REF_CLK120M ITPCPU_CLK100M ITPCPU_CLK100M ITPCPU_CLK100M ITPCPU_CLK100M ITPCPU_CLK100M ITPCPU_CLK100M CLK_PCIE_90D CLK_PCIE_90D CLK_PCIE_90D CLK_PCIE_90D CLK_PCIE_90D CLK_PCIE_90D CLK_PCIE_90D CLK_PCIE_90D CLK_PCIE_90D CLK_PCIE_90D CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE DMI_CLK100M_CPU_P DMI_CLK100M_CPU_N DPLL_REF_CLKP DPLL_REF_CLKN ITPCPU_CLK100M_P ITPCPU_CLK100M_N ITPXDP_CLK100M_P ITPXDP_CLK100M_N XDP_CPU_CLK100M_P XDP_CPU_CLK100M_N CPU_27P4S CPU_27P4S CPU_COMP CPU_COMP EDP_COMP CPU_PEG_COMP (FSB_CPURST_L) CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_XDP_BPM CPU_50S CPU_50S CPU_ITP CPU_ITP CPU_ITP CPU_ITP CPU_ITP CPU_ITP CPU_ITP CPU_ITP XDP_CPU_TDI XDP_CPU_TDO XDP_CPU_TMS XDP_CPU_TCK XDP_CPU_TRST_L XDP_BPM_L CPU_CFG XDP_CPURST_L CPU_VCCAXG_SENSE CPU_VCCAXG_SENSE CPU_VCCSENSE CPU_VCCSENSE CPU_27P4S CPU_27P4S CPU_27P4S CPU_27P4S CPU_VCCSENSE CPU_VCCSENSE CPU_VCCSENSE CPU_VCCSENSE CPU_VCCSENSE_P CPU_VCCSENSE_N CPU_VCCIOSENSE_P CPU_VCCIOSENSE_N CPU_VCCAXG_SENSE CPU_VCCAXG_SENSE CPU_27P4S CPU_27P4S CPU_VCCSENSE CPU_VCCSENSE CPU_AXG_SENSE_P CPU_AXG_SENSE_N CPU_VALSENSE CPU_VALSENSE CPU_VALSENSE CPU_VALSENSE CPU_VALSENSE CPU_VALSENSE CPU_27P4S CPU_27P4S CPU_27P4S CPU_27P4S CPU_27P4S CPU_27P4S CPU_VCCSENSE CPU_VCCSENSE CPU_VCCSENSE CPU_VCCSENSE CPU_VCCSENSE CPU_VCCSENSE CPU_VDDQ_SENSE_P CPU_VDDQ_SENSE_N CPU_AXG_VALSENSE_P CPU_AXG_VALSENSE_N CPU_VCC_VALSENSE_P CPU_VCC_VALSENSE_N CPU_SVIDALERT_L CPU_SVIDSCLK CPU_SVIDSOUT CPU_50S CPU_50S CPU_50S CPU_COMP CPU_COMP CPU_COMP CPU_VIDALERT_L CPU_VIDSCLK CPU_VIDSOUT 17 17 17 17 TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM CPU_XDP_BPM * =CPU_50S =CPU_50S =CPU_50S =CPU_50S =CPU_50S =CPU_50S NOTE: CPU_XDP_BPM physical constraint is to prevent routing on outer layers D 17 17 17 D 17 NOTE: mil gap is for VCCSense pair, which Intel says to route with mil spacing without specifying a target impedance TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT =STANDARD ? TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT =2x_DIELECTRIC ? TABLE_SPACING_RULE_ITEM CPU_AGTL * TABLE_SPACING_RULE_ITEM CPU_AGTL TOP,BOTTOM TABLE_SPACING_RULE_ITEM CPU_8MIL * MIL ? CPU_COMP * 20 MIL ? 10 17 10 17 26 TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM CPU_ITP * =2:1_SPACING ? CPU_VCCSENSE * 25 MIL ? TABLE_SPACING_RULE_ITEM Most CPU signals with impedance requirements are 50-ohm single-ended 10 23 Some signals require 27.4-ohm single-ended impedance SOURCE: Huron River SFF DG (DG-438297_v1.0), Section 4.18 and Huron River Platform Power Delivery DG v1.0 Section 2.7 CPU_SM_RCOMP CPU_SM_RCOMP CPU_SM_RCOMP PCI-Express TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM PCIE_85D * =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF CLK_PCIE_90D * =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF CPU_CATERR_L TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LINE-TO-LINE SPACING WEIGHT PCIE LAYER * =3X_DIELECTRIC ? CLK_PCIE * 20 MIL ? TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT =4X_DIELECTRIC ? TABLE_SPACING_RULE_ITEM 10 10 10 23 10 12 10 41 56 10 19 23 TABLE_SPACING_RULE_ITEM PCIE TOP,BOTTOM 10 19 TABLE_SPACING_RULE_ITEM C SOURCE: Huron River SFF DG (DG-438297_v1.0), Section 4.18 and Huron River Platform Power Delivery DG v1.0 Section 2.7 XDP_TDI XDP_TDO XDP_TMS XDP_TCK XDP_TRST_L XDP_BPM_L XDP_BPM_R_L B C 10 16 10 16 10 10 10 16 10 16 16 23 16 23 23 23 9 10 23 10 23 10 23 10 23 10 23 10 23 23 23 12 56 CPU_VCCSA_VID CPU_VCCSA_VID B 12 56 12 58 12 58 12 56 12 56 12 12 9 9 12 56 12 56 12 56 A SYNC_MASTER=CONSTRAINTS SYNC_DATE=04/06/2011 PAGE TITLE PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PEG_R2D_P PEG_R2D_N PEG_R2D_C_P PEG_R2D_C_N PEG_D2R_P PEG_D2R_N PEG_D2R_C_P PEG_D2R_C_N CPU Constraints DRAWING NUMBER Apple Inc 8 051-8871 R NOTICE OF PROPRIETARY PROPERTY: SIZE D REVISION 2.5.0 BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED PAGE 100 OF 109 SHEET 66 OF 74 A Memory Bus Constraints Memory Net Properties TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP MEM_37S * =37_OHM_SE =37_OHM_SE =37_OHM_SE =37_OHM_SE =STANDARD =STANDARD NET_TYPE ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM MEM_40S * =40_OHM_SE =40_OHM_SE =40_OHM_SE =40_OHM_SE =STANDARD =STANDARD MEM_A_CLK MEM_A_CLK MEM_72D MEM_72D MEM_CLK MEM_CLK MEM_A_CLK_P MEM_A_CLK_N MEM_A_CTRL MEM_A_CTRL MEM_A_CTRL MEM_55S MEM_55S MEM_55S MEM_CTRL MEM_CTRL MEM_CTRL MEM_A_CKE MEM_A_CS_L MEM_A_ODT MEM_A_CMD MEM_A_CMD MEM_A_CMD MEM_A_CMD MEM_A_CMD MEM_55S MEM_55S MEM_55S MEM_55S MEM_55S MEM_CMD MEM_CMD MEM_CMD MEM_CMD MEM_CMD MEM_A_A MEM_A_BA MEM_A_RAS_L MEM_A_CAS_L MEM_A_WE_L MEM_A_DQ_BYTE0 MEM_A_DQ_BYTE1 MEM_A_DQ_BYTE2 MEM_A_DQ_BYTE3 MEM_A_DQ_BYTE4 MEM_A_DQ_BYTE5 MEM_A_DQ_BYTE6 MEM_A_DQ_BYTE7 MEM_50S MEM_50S MEM_50S MEM_50S MEM_50S MEM_50S MEM_50S MEM_50S MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQS0 MEM_A_DQS0 MEM_A_DQS1 MEM_A_DQS1 MEM_A_DQS2 MEM_A_DQS2 MEM_A_DQS3 MEM_A_DQS3 MEM_A_DQS4 MEM_A_DQS4 MEM_A_DQS5 MEM_A_DQS5 MEM_A_DQS6 MEM_A_DQS6 MEM_A_DQS7 MEM_A_DQS7 MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_B_CLK MEM_B_CLK MEM_72D MEM_72D MEM_CLK MEM_CLK MEM_B_CLK_P MEM_B_CLK_N MEM_B_CTRL MEM_B_CTRL MEM_B_CTRL MEM_55S MEM_55S MEM_55S MEM_CTRL MEM_CTRL MEM_CTRL MEM_B_CKE MEM_B_CS_L MEM_B_ODT MEM_B_CMD MEM_B_CMD MEM_B_CMD MEM_B_CMD MEM_B_CMD MEM_55S MEM_55S MEM_55S MEM_55S MEM_55S MEM_CMD MEM_CMD MEM_CMD MEM_CMD MEM_CMD MEM_B_A MEM_B_BA MEM_B_RAS_L MEM_B_CAS_L MEM_B_WE_L MEM_B_DQ_BYTE0 MEM_B_DQ_BYTE1 MEM_B_DQ_BYTE2 MEM_B_DQ_BYTE3 MEM_B_DQ_BYTE4 MEM_B_DQ_BYTE5 MEM_B_DQ_BYTE6 MEM_B_DQ_BYTE7 MEM_50S MEM_50S MEM_50S MEM_50S MEM_50S MEM_50S MEM_50S MEM_50S MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQS0 MEM_B_DQS0 MEM_B_DQS1 MEM_B_DQS1 MEM_B_DQS2 MEM_B_DQS2 MEM_B_DQS3 MEM_B_DQS3 MEM_B_DQS4 MEM_B_DQS4 MEM_B_DQS5 MEM_B_DQS5 MEM_B_DQS6 MEM_B_DQS6 MEM_B_DQS7 MEM_B_DQS7 MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_PWR MEM_PWR MEM_PWR MEM_PWR PP1V5_S3RS0 PP1V5_S3 PP0V75_S3_MEM_VREFCA_A PP0V75_S3_MEM_VREFDQ_A 11 27 28 32 11 27 28 32 TABLE_PHYSICAL_RULE_ITEM MEM_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD MEM_72D * =72_OHM_DIFF =72_OHM_DIFF =72_OHM_DIFF =72_OHM_DIFF =72_OHM_DIFF =72_OHM_DIFF TABLE_PHYSICAL_RULE_ITEM 11 27 28 32 11 27 28 32 11 27 28 32 TABLE_PHYSICAL_RULE_ITEM MEM_50S TOP,BOTTOM Y =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD TABLE_PHYSICAL_RULE_ITEM MEM_85D D TOP,BOTTOM Y =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF TABLE_PHYSICAL_RULE_ITEM MEM_50S ISL3,ISL4,ISL9,ISL10 Y =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD MEM_85D ISL3,ISL4,ISL9,ISL10 Y =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF TABLE_PHYSICAL_RULE_ITEM Memory to Power Spacing TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 C NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET TABLE_SPACING_ASSIGNMENT_ITEM MEM_CLK MEM_PWR * MEM_2PWR MEM_CTRL MEM_PWR * MEM_2PWR 11 27 28 32 11 27 28 32 D 11 27 28 32 11 27 28 32 11 27 28 32 11 27 11 27 11 27 11 27 11 28 11 28 11 28 11 28 11 27 11 27 11 27 11 27 11 27 11 27 11 27 11 27 11 28 11 28 11 28 11 28 11 28 11 28 C 11 28 11 28 TABLE_SPACING_ASSIGNMENT_ITEM Spacing Rule Sets TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT 0.6 MM ? TABLE_SPACING_ASSIGNMENT_ITEM MEM_CMD MEM_PWR * MEM_2PWR MEM_DATA MEM_PWR * MEM_2PWR TABLE_SPACING_RULE_ITEM MEM_CLK2CLK * TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_RULE_ITEM MEM_CTRL2CTRL * 0.2 MM ? MEM_CMD2CTRL * 0.2 MM ? TABLE_SPACING_ASSIGNMENT_ITEM MEM_DQS MEM_PWR * MEM_2PWR TABLE_SPACING_RULE_ITEM 11 29 30 32 11 29 30 32 11 29 30 32 11 29 30 32 11 29 30 32 TABLE_SPACING_RULE_ITEM MEM_CMD2CMD * 0.2 MM ? MEM_DATA2DATA * 0.14 MM ? MEM_DQS2DQS * 0.4 MM ? Memory to GND Spacing TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET MEM_CLK GND * MEM_2GND TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_RULE_ITEM MEM_MEM2OTHERMEM * 0.4 MM ? MEM_2PWR * =PWR_P2MM ? TABLE_SPACING_ASSIGNMENT_ITEM MEM_CTRL GND * MEM_2GND MEM_CMD GND * MEM_2GND TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_RULE_ITEM MEM_2GND * =GND_P2MM TABLE_SPACING_ASSIGNMENT_ITEM MEM_DATA ? GND * MEM_2GND TABLE_SPACING_RULE_ITEM MEM_2OTHER * ? 0.6 MM TABLE_SPACING_ASSIGNMENT_ITEM MEM_DQS GND * MEM_2GND Memory Bus Spacing Group Assignments TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE TABLE_SPACING_ASSIGNMENT_ITEM MEM_CLK MEM_CLK * MEM_CLK2CLK MEM_CLK MEM_CTRL * MEM_MEM2OTHERMEM MEM_CMD MEM_CLK * MEM_MEM2OTHERMEM MEM_CMD MEM_CTRL * MEM_CMD2CTRL B TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CLK MEM_CMD * MEM_MEM2OTHERMEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CMD MEM_CMD * TABLE_SPACING_ASSIGNMENT_ITEM MEM_CLK MEM_DATA * MEM_MEM2OTHERMEM MEM_CLK MEM_DQS * MEM_MEM2OTHERMEM MEM_CMD MEM_DATA * MEM_MEM2OTHERMEM MEM_CMD MEM_DQS * MEM_MEM2OTHERMEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET MEM_CTRL MEM_CLK * MEM_MEM2OTHERMEM TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET MEM_DATA MEM_CLK * MEM_MEM2OTHERMEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CTRL MEM_CTRL * MEM_CTRL2CTRL MEM_CTRL MEM_CMD * MEM_CMD2CTRL TABLE_SPACING_ASSIGNMENT_ITEM MEM_DATA MEM_CTRL * MEM_MEM2OTHERMEM MEM_DATA MEM_CMD * MEM_MEM2OTHERMEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CTRL MEM_DATA * MEM_MEM2OTHERMEM MEM_CTRL MEM_DQS * MEM_MEM2OTHERMEM NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET TABLE_SPACING_ASSIGNMENT_ITEM MEM_DATA MEM_DATA * MEM_DATA2DATA MEM_DATA MEM_DQS * MEM_MEM2OTHERMEM NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_HEAD TABLE_SPACING_ASSIGNMENT_ITEM MEM_CLK * MEM_MEM2OTHERMEM MEM_DQS MEM_CTRL * MEM_MEM2OTHERMEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CLK * * MEM_2OTHER MEM_CTRL * * MEM_2OTHER TABLE_SPACING_ASSIGNMENT_ITEM MEM_CMD * MEM_MEM2OTHERMEM MEM_DQS MEM_DATA * MEM_MEM2OTHERMEM MEM_CMD * * MEM_2OTHER MEM_DATA * * MEM_2OTHER A * MEM_DQS2DQS 11 29 11 29 11 29 11 30 11 30 11 30 11 30 11 29 11 29 11 29 B 11 29 11 29 11 29 11 29 11 29 11 30 11 30 11 30 11 30 11 30 11 30 11 30 11 30 7 27 28 29 30 31 27 28 29 30 31 MEM_DQS * * MEM_2OTHER TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_DQS 11 29 TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_DQS 11 29 30 32 11 29 30 32 TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_DQS 11 29 30 32 TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_HEAD MEM_DQS MEM_CMD2CMD TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM 11 29 30 32 SPACING_RULE_SET TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM 11 29 30 32 TABLE_SPACING_ASSIGNMENT_ITEM Need to support MEM_*-style wildcards! DDR3: Sandybridge SFF 2C when routed on Type-3 (Through hole) should follow rPGA guidelines SYNC_MASTER=CONSTRAINTS per Huron River SFF DG rev1.0 (#438297) SYNC_DATE=04/06/2011 PAGE TITLE DQS intra-pair matching should be within 0.127mm, no inter-pair matching requirement Memory Constraints DQ to DQS matching per byte lane should be within 0.127mm DRAWING NUMBER DQS to clock matching should be within [CLK-63.5mm] and [CLK+38.1mm] Apple Inc CLK intra-pair matching should be within 0.127mm, inter-pair matching should be within 0.0508mm CONTROL signals should be matched within [CLK-2.54mm] to [CLK+0.0mm] of CLK pairs 051-8871 R A/BA/CMD signals should be matched within [CLK-12.7mm] to [CLK+12.7mm] of CLK pairs A/BA/CMD signals to each other should match within 5.08mm NOTICE OF PROPRIETARY PROPERTY: SIZE D REVISION 2.5.0 BRANCH DQ/DQS/A/BA/cmd signal spacing is 4x dielectric, CLK is 5x dielectric THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED Maximum length of any signal from die pad to SODIMM pad is 119.83mm, from procesor ball to SODIMM pad is 88.9mm SOURCE: Huron River Platform DG, Rev 1.01 (#436735), Section 2.5 PAGE 101 OF 109 SHEET 67 OF 74 A Digital Video Signal Constraints PCH Net Properties TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP NET_TYPE ELECTRICAL_CONSTRAINT_SET TABLE_PHYSICAL_RULE_ITEM DP_85D * =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF LVDS_90D * =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF SPACING_RULE_SET LAYER TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_HEAD LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM DISPLAYPORT * =3x_DIELECTRIC ? LVDS * =3x_DIELECTRIC ? LVDS intra-pair matching should be mils DISPLAYPORT TOP,BOTTOM =4x_DIELECTRIC ? LVDS TOP,BOTTOM =4x_DIELECTRIC ? TABLE_SPACING_RULE_ITEM Pairs should be within 100 mils of clock length DisplayPort/TMDS intra-pair matching should be ps DP_85D DP_85D DP_85D DP_85D DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DP_IG_ML_P DP_IG_ML_N DP_IG_AUX_CH_P DP_IG_AUX_CH_N LVDS_IG_A_CLK LVDS_IG_A_CLK LVDS_IG_A_DATA LVDS_IG_A_DATA LVDS_90D LVDS_90D LVDS_90D LVDS_90D LVDS_90D LVDS_90D LVDS_90D LVDS_90D LVDS_90D LVDS_90D LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS_IG_A_CLK_P LVDS_IG_A_CLK_N LVDS_IG_A_DATA_P LVDS_IG_A_DATA_N LVDS_IG_A_DATA_P LVDS_IG_A_DATA_N LVDS_IG_B_DATA_P LVDS_IG_B_DATA_N LVDS_IG_B_CLK_P LVDS_IG_B_CLK_N SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA_HDD_R2D_C_P SATA_HDD_R2D_C_N SATA_HDD_R2D_P SATA_HDD_R2D_N SATA_HDD_D2R_P SATA_HDD_D2R_N SATA_HDD_D2R_C_P SATA_HDD_D2R_C_N SATA_ODD_R2D_C_P SATA_ODD_R2D_C_N SATA_ODD_R2D_P SATA_ODD_R2D_N SATA_ODD_D2R_P SATA_ODD_D2R_N SATA_HDD_R2D_RC_P SATA_HDD_R2D_RC_N SATA_HDD_D2R_RC_P SATA_HDD_D2R_RC_N USB_85D USB_85D USB_85D USB_85D USB_85D USB_85D USB_85D USB_85D USB_85D USB_85D USB_85D USB_85D USB_85D USB_85D USB_85D USB_85D USB_85D USB_85D USB_85D USB_85D USB_85D USB_85D USB_85D USB_85D USB_85D USB_85D USB_85D USB_85D USB_85D USB_85D SATA_ICOMP USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB PCH_SATAICOMP USB_HUB1_UP_P USB_HUB1_UP_N USB_HUB2_UP_P USB_HUB2_UP_N USB_EXTA_P USB_EXTA_N USB_EXTB_P USB_EXTB_N USB_EXTC_P USB_EXTC_N USB_EXTD_P USB_EXTD_N USB_T29A_P USB_T29A_N T29_A_RSVD_P T29_A_RSVD_N USB_CAMERA_P USB_CAMERA_N USB_CAMERA_CONN_P USB_CAMERA_CONN_N USB_BT_P USB_BT_N USB_TPAD_P USB_TPAD_N USB_IR_P USB_IR_N USB_SDCARD_P USB_SDCARD_N USB_BRCRYPT_P USB_BRCRYPT_N CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE PCIE_CLK100M_PCH_P PCIE_CLK100M_PCH_N FSB_CLK133M_PCH_P FSB_CLK133M_PCH_N PCH_CLK96M_DOT_P PCH_CLK96M_DOT_N PCH_CLK100M_SATA_P PCH_CLK100M_SATA_N PCH_CLK14P3M_REFCLK PCH_CLK33M_PCIIN GFX_CLK120M_DPLLSS_P GFX_CLK120M_DPLLSS_N Inter-pair matching should be within 150 ps DIsplayPort AUX CH intra-pair matching should be ps SPACING DP_ML DP_ML DP_EXTA_AUXCH DP_EXTA_AUXCH 8 8 TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM D PHYSICAL No relationship to other signals Max length of LVDS/DisplayPort/TMDS traces: 12 inches SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Sections 2.5.3 & 2.5.4 SATA Interface Constraints D 8 8 8 TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP SATA_90D * =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING SATA * =4x_DIELECTRIC SATA_HDD_R2D SATA_HDD_R2D SATA_HDD_D2R SATA_HDD_D2R WEIGHT TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM ? SATA TOP,BOTTOM =3x_DIELECTRIC ? TABLE_SPACING_RULE_ITEM SATA_ICOMP * MIL ? SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.7.1 USB 2.0 Interface Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP SATA_ODD_R2D SATA_ODD_R2D SATA_ODD_D2R SATA_ODD_D2R DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM PCH_USB_RBIAS * =STANDARD MIL MIL =STANDARD =STANDARD =STANDARD USB_85D * =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT =2x_DIELECTRIC ? TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT =4x_DIELECTRIC ? TABLE_SPACING_RULE_ITEM C USB * TABLE_SPACING_RULE_ITEM USB TOP,BOTTOM 16 37 16 37 37 37 16 37 16 37 37 37 16 16 16 16 C SOURCE: Calpella Platform Design Guide for Ibex Peak M (DG-398905-398905_v1.5), Section 3.8 PCH_SATA_ICOMP USB_HUB1_UP USB_HUB2_UP USB_EXTA USB_EXTA USB_EXTB USB_EXTC USB_EXTD USB_EXTD USB_CAMERA USB_CAMERA B USB_BT USB_BT USB_TPAD USB_IR USB_SDCARD USB_BRCRYPT PCH_USB_RBIAS PCH_USB_RBIAS PCH_DIFFCLK_UNUSED_ PCH_DIFFCLK_UNUSED_ CLK_PCIE_90D CLK_PCIE_90D CLK_PCIE_90D CLK_PCIE_90D CLK_PCIE_90D CLK_PCIE_90D CLK_PCIE_90D CLK_PCIE_90D CPU_50S CPU_50S CLK_PCIE_90D CLK_PCIE_90D PCH_DIFFCLK_UNUSED_ PCH_DIFFCLK_UNUSED_ PCH_DIFFCLK_UNUSED_ PCH_DIFFCLK_UNUSED_ LPC_CLK33M GFX_CLK_DPLLSS GFX_CLK_DPLLSS PCH_USB_RBIAS A 16 18 24 18 24 18 24 18 24 24 38 24 38 24 39 24 39 24 24 63 63 18 39 18 39 B 24 36 24 36 48 48 24 24 18 16 25 16 25 16 25 16 25 16 25 16 25 16 25 16 25 SYNC_MASTER=CONSTRAINTS SYNC_DATE=04/06/2011 PAGE TITLE PCH Constraints DRAWING NUMBER Apple Inc 051-8871 R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED SIZE D REVISION 2.5.0 BRANCH PAGE 102 OF 109 SHEET 68 OF 74 A LPC Bus Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER PCH Net Properties ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP Chipset Net Properties NET_TYPE DIFFPAIR NECK GAP ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING NET_TYPE TABLE_PHYSICAL_RULE_ITEM LPC_50S * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD ELECTRICAL_CONSTRAINT_SET =STANDARD TABLE_PHYSICAL_RULE_ITEM CLK_LPC_50S * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD LPC_AD LPC_FRAME_L LPC_RESET_L LPC_50S LPC_50S LPC_50S LPC LPC LPC LPC_AD LPC_FRAME_L LPC_RESET_L LPC_CLK33M LPC_CLK33M LPC_CLK33M CLK_LPC_50S CLK_LPC_50S CLK_LPC_50S CLK_LPC CLK_LPC CLK_LPC LPC_CLK33M_SMC_R LPC_CLK33M_SMC LPC_CLK33M_LPCPLUS SMBUS_PCH_CLK SMBUS_PCH_DATA SMBUS_PCH_0_CLK SMBUS_PCH_0_DATA SMBUS_PCH_1_CLK SMBUS_PCH_1_DATA SMB_50S SMB_50S SMB_50S SMB_50S SMB_50S SMB_50S SMB SMB SMB SMB SMB SMB SMBUS_PCH_CLK SMBUS_PCH_DATA SML_PCH_0_CLK SML_PCH_0_DATA SML_PCH_1_CLK SML_PCH_1_DATA HDA_BIT_CLK HDA_50S HDA_50S HDA_50S HDA_50S HDA_50S HDA_50S HDA_50S HDA_50S HDA_50S HDA_50S HDA HDA HDA HDA HDA HDA HDA HDA HDA HDA HDA_BIT_CLK HDA_BIT_CLK_R HDA_SYNC HDA_SYNC_R HDA_RST_R_L HDA_RST_L HDA_SDIN0 AUD_SDI_R HDA_SDOUT HDA_SDOUT_R PM_SUS_CLK CLK_SLOW_55S CLK_SLOW PM_CLK32K_SUSCLK SPI_CLK SPI_55S SPI_55S SPI_55S SPI_55S SPI_55S SPI_55S SPI_55S SPI_55S SPI_55S SPI_55S SPI_55S SPI SPI SPI SPI SPI SPI SPI SPI SPI SPI SPI SPI_CLK_R SPI_CLK SPI_MOSI_R SPI_MOSI SPI_MISO SPI_CS0_R_L SPI_CS0_L SPI_MLB_CLK SPI_MLB_MOSI SPI_MLB_MISO SPI_MLB_CS_L 16 40 42 16 40 42 DP_EXTA_ML DP_EXTA_ML 25 TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM LPC * MIL ? TABLE_SPACING_RULE_ITEM CLK_LPC D * MIL SMBus Interface Constraints TABLE_PHYSICAL_RULE_HEAD LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM SMB_50S * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD LAYER LINE-TO-LINE SPACING WEIGHT HDA_SYNC TABLE_SPACING_RULE_ITEM SMB * 25 42 =2x_DIELECTRIC ? HDA_RST_L HDA_SDIN0 HD Audio Interface Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP HDA_50S * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD HDA_SDOUT TABLE_PHYSICAL_RULE_ITEM 16 43 16 43 16 43 LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM HDA * =2x_DIELECTRIC ? SPI_MOSI SOURCE: Calpella Platform Design Guide for Ibex Peak M (DG-398905-398905_v1.5), Section 3.15 SPI_MISO SPI_CS0 SIO Signal Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM C CLK_SLOW_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING 16 43 16 43 16 39 16 16 39 * MIL ? PCIE_ENET_R2D SPI Interface Constraints PCIE_ENET_D2R TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP SPI_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT PCIE_AP_R2D TABLE_SPACING_RULE_ITEM SPI * MIL ? PCIE_AP_D2R PCIE_FW_R2D PCIE_FW_D2R DisplayPort Signal Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP DP_85D * =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF SPACING_RULE_SET LAYER TABLE_PHYSICAL_RULE_ITEM B PCIE_AP_D2R TABLE_SPACING_RULE_HEAD LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM * DISPLAYPORT =3x_DIELECTRIC PCIE_AP_R2D TABLE_SPACING_RULE_ITEM ? DISPLAYPORT TOP,BOTTOM =4x_DIELECTRIC ? PCI-Express Signal Constraints PCIE_CLK100M_ENET TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP PCIE_85D * =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF CLK_PCIE_90D * =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF TABLE_PHYSICAL_RULE_ITEM MCP_PE1_REFCLK TABLE_PHYSICAL_RULE_ITEM MCP_PE2_REFCLK TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT =3X_DIELECTRIC ? TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT =4X_DIELECTRIC ? TABLE_SPACING_RULE_ITEM PCIE * TABLE_SPACING_RULE_ITEM PCIE TOP,BOTTOM TABLE_SPACING_RULE_ITEM CLK_PCIE * 20 MIL ? System Clock Signal Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP CLK_SLOW_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM CLK_25M_55S * SPACING_RULE_SET LAYER =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD TABLE_SPACING_RULE_HEAD A LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM CLK_SLOW * =2x_DIELECTRIC ? CLK_25M * =5x_DIELECTRIC ? TABLE_SPACING_RULE_ITEM NOTE: 25MHz system clocks very sensitive to noise PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE_ENET_R2D_P PCIE_ENET_R2D_N PCIE_ENET_R2D_C_P PCIE_ENET_R2D_C_N PCIE_ENET_D2R_P PCIE_ENET_D2R_N PCIE_ENET_D2R_C_P PCIE_ENET_D2R_C_N PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE PCIE PCIE PCIE PCIE PCIE PCIE_AP_R2D_P PCIE_AP_R2D_N PCIE_AP_R2D_C_P PCIE_AP_R2D_C_N PCIE_AP_D2R_P PCIE_AP_D2R_N PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE_FW_R2D_P PCIE_FW_R2D_N PCIE_FW_R2D_C_P PCIE_FW_R2D_C_N PCIE_FW_D2R_P PCIE_FW_D2R_N PCIE_FW_D2R_C_P PCIE_FW_D2R_C_N PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE PCIE PCIE PCIE CONN_PCIE_AP_D2R_P CONN_PCIE_AP_D2R_N CONN_PCIE_AP_R2D_P CONN_PCIE_AP_R2D_N CLK_PCIE_90D CLK_PCIE_90D CLK_PCIE_90D CLK_PCIE_90D CLK_PCIE_90D CLK_PCIE_90D CLK_PCIE_90D CLK_PCIE_90D CLK_PCIE_90D CLK_PCIE_90D CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE PEG_CLK100M_P PEG_CLK100M_N PCIE_CLK100M_ENET_P PCIE_CLK100M_ENET_N PCIE_CLK100M_AP_P PCIE_CLK100M_AP_N PCIE_CLK100M_FW_P PCIE_CLK100M_FW_N PCIE_CLK100M_EXCARD_P PCIE_CLK100M_EXCARD_N CPU_27P4S CPU_27P4S CPU_27P4S CPU_27P4S CPU_27P4S CPU_27P4S CPU_27P4S CPU_27P4S CPU_27P4S CPU_27P4S CPU_27P4S CPU_27P4S CPU_27P4S CPU_27P4S CPU_27P4S CPU_27P4S CPU_COMP CPU_COMP CPU_COMP CPU_COMP CPU_COMP CPU_COMP CPU_COMP CPU_COMP CPU_COMP CPU_COMP CPU_COMP CPU_COMP CPU_COMP CPU_COMP CPU_COMP CPU_COMP PCH_VSS_NCTF PCH_VSS_NCTF PCH_VSS_NCTF TP_PCH_VSS_NCTF PCH_VSS_NCTF PCH_VSS_NCTF PCH_VSS_NCTF PCH_VSS_NCTF PCH_VSS_NCTF PCH_VSS_NCTF PCH_VSS_NCTF PCH_VSS_NCTF PCH_VSS_NCTF PCH_VSS_NCTF PCH_VSS_NCTF PCH_VSS_NCTF DP_INT_AUXCH DP_INT_AUXCH 16 16 SPACING DP_85D DP_85D DP_85D DP_85D DP_85D DP_85D DP_85D DP_85D DP_85D DP_85D DP_85D DP_85D DP_85D DP_85D DP_85D DP_85D DP_85D DP_85D DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DP_EXTA_ML_C_P DP_EXTA_ML_C_N DP_EXTA_ML_P DP_EXTA_ML_N DP_EXTA_AUXCH_C_P DP_EXTA_AUXCH_C_N DP_EXTA_AUXCH_P DP_EXTA_AUXCH_N DP_INT_ML_C_P DP_INT_ML_C_N DP_INT_ML_P DP_INT_ML_N DP_INT_ML_F_P DP_INT_ML_F_N DP_INT_AUX_CH_C_P DP_INT_AUX_CH_C_N DP_INT_AUX_CH_P DP_INT_AUX_CH_N PCIE_85D PCIE_85D PCIE PCIE PCIE_T29_R2D_C_P PCIE_T29_R2D_C_N PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE_T29_D2R_P PCIE_T29_D2R_P PCIE_T29_D2R_P PCIE_T29_D2R_P PCIE_T29_D2R_N PCIE_T29_D2R_N PCIE_T29_D2R_N PCIE_T29_D2R_N PCIE_T29_R2D_P PCIE_T29_R2D_P PCIE_T29_R2D_P PCIE_T29_R2D_P PCIE_T29_R2D_N PCIE_T29_R2D_N PCIE_T29_R2D_N PCIE_T29_R2D_N PCIE_85D PCIE_85D PCIE PCIE PCIE_T29_D2R_C_P PCIE_T29_D2R_C_N CLK_PCIE_90D CLK_PCIE_90D CLK_PCIE CLK_PCIE PCIE_CLK100M_T29_P PCIE_CLK100M_T29_N 16 33 16 25 16 39 16 39 16 39 16 16 42 42 16 42 42 16 42 16 42 42 42 49 42 49 42 49 42 49 WEIGHT TABLE_SPACING_RULE_ITEM CLK_SLOW DP_INT_ML DP_INT_ML 16 43 TABLE_SPACING_RULE_HEAD SPACING_RULE_SET DP_EXTA_AUXCH DP_EXTA_AUXCH =STANDARD TABLE_SPACING_RULE_HEAD SPACING_RULE_SET 25 40 ? SOURCE: Calpella Platform Design Guide for Ibex Peak M (DG-398905-398905_v1.5), Section 3.15 PHYSICAL_RULE_SET 18 25 PHYSICAL PCIE_PEG_D2R_LANE3 PCIE_PEG_D2R_LANE2 PCIE_PEG_D2R_LANE1 PCIE_PEG_D2R_LANE0 PCIE_PEG_D2R_LANE3 PCIE_PEG_D2R_LANE2 PCIE_PEG_D2R_LANE1 PCIE_PEG_D2R_LANE0 PCIE_PEG_R2D_LANE3 PCIE_PEG_R2D_LANE2 PCIE_PEG_R2D_LANE1 PCIE_PEG_R2D_LANE0 PCIE_PEG_R2D_LANE3 PCIE_PEG_R2D_LANE2 PCIE_PEG_R2D_LANE1 PCIE_PEG_R2D_LANE0 PCIE_CLK100M_T29 PCIE_CLK100M_T29 PHYSICAL 16 36 63 63 D 63 62 62 62 62 62 62 62 62 62 62 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 C 33 33 33 33 33 16 33 SPACING SYSCLK_CLK32K_RTC CLK_SLOW_55S CLK_SLOW SYSCLK_CLK32K_RTC SYSCLK_CLK25M_SB CLK_25M_55S CLK_25M_55S CLK_25M_55S CLK_25M_55S CLK_25M_55S CLK_25M_55S CLK_25M CLK_25M CLK_25M CLK_25M CLK_25M CLK_25M SYSCLK_CLK25M_SB SYSCLK_CLK25M_SB_R SYSCLK_CLK25M_ENET SYSCLK_CLK25M_ENET_R SYSCLK_CLK25M_T29 SYSCLK_CLK25M_T29_R 16 36 16 36 16 36 SYSCLK_CLK25M_T29 16 25 16 25 33 33 B 16 16 16 36 16 36 16 16 6 6 69 69 6 6 6 SYNC_MASTER=CONSTRAINTS SYNC_DATE=04/06/2011 PAGE TITLE PCH Constraints DRAWING NUMBER THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED 63 NET_TYPE ELECTRICAL_CONSTRAINT_SET NOTICE OF PROPRIETARY PROPERTY: 63 63 36 051-8871 SIZE D REVISION R 63 Clock Net Properties 36 Apple Inc 8 63 2.5.0 BRANCH PAGE 103 OF 109 SHEET 69 OF 74 A CAESAR IV (Ethernet) Constraints Ethernet Net Properties TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP ENET_50S * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD NET_TYPE ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING TABLE_PHYSICAL_RULE_ITEM ENET_50S ENET_50S ENET_50S ENET_3X ENET_3X ENET_3X BCM5764_CLK25M_XTALI BCM5764_CLK25M_XTALO ENET_RESET_L ENET_MDI ENET_100D ENET_100D ENET_MDI ENET_MDI ENET_MDI_P ENET_MDI_N CR_DATA CR_DATA CR_CLK CR_DATA CR_DATA CR_CLK ENET_50S ENET_50S ENET_50S ENET_50S ENET_50S ENET_50S ENET_CR_DATA ENET_CR_DATA ENET_CR_DATA ENET_CR_DATA ENET_CR_DATA ENET_CR_DATA ENET_CR_DATA ENET_CR_CMD ENET_CR_CLK SDCONN_DATA SDCONN_CMD SDCONN_CLK TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT =3:1_SPACING ? LINE-TO-LINE SPACING WEIGHT 8MIL ? TABLE_SPACING_RULE_ITEM ENET_3X * SOURCE: Broadcom 5764-DS04-RDS Page 38 I166 TABLE_SPACING_RULE_HEAD SPACING_RULE_SET D LAYER I167 TABLE_SPACING_RULE_ITEM I168 ENET_CR_DATA * I169 I170 CAESAR IV (Ethernet PHY) Constraints I171 D TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? ENET_100D * =100_OHM_DIFF SPACING_RULE_SET LAYER MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_HEAD LINE-TO-LINE SPACING WEIGHT 0.6 MM ? TABLE_SPACING_RULE_ITEM ENET_MDI * SOURCE: Broadcom 5764-DS04-RDS Page 38 C FireWire Interface Constraints C FireWire Net Properties TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP FW_110D * =110_OHM_DIFF =110_OHM_DIFF =110_OHM_DIFF =110_OHM_DIFF =110_OHM_DIFF =110_OHM_DIFF NET_TYPE ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING TABLE_PHYSICAL_RULE_ITEM I158 I159 TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT =3:1_SPACING ? I160 TABLE_SPACING_RULE_ITEM I161 FW_TP * I162 I163 I164 I165 FW_P0_TPA FW_P0_TPA FW_P0_TPB FW_P0_TPB FW_P1_TPA FW_P1_TPA FW_P1_TPB FW_P1_TPB FW_110D FW_110D FW_110D FW_110D FW_110D FW_110D FW_110D FW_110D FW_TP FW_TP FW_TP FW_TP FW_TP FW_TP FW_TP FW_TP FW_P0_TPA_P FW_P0_TPA_N FW_P0_TPB_P FW_P0_TPB_N FW_P1_TPA_P FW_P1_TPA_N FW_P1_TPB_P FW_P1_TPB_N Port Not Used B B A SYNC_MASTER=CONSTRAINTS SYNC_DATE=04/06/2011 PAGE TITLE Ethernet/FW Constraints DRAWING NUMBER Apple Inc 051-8871 R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED SIZE D REVISION 2.5.0 BRANCH PAGE 104 OF 109 SHEET 70 OF 74 A DisplayPort Signal Constraints T29 Net Properties NOTE: DisplayPort Physical/Spacing Constraints provided by Chipset or GPU page NET_TYPE ELECTRICAL_CONSTRAINT_SET T29 I2C Signal Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP I263 DIFFPAIR NECK GAP I262 TABLE_PHYSICAL_RULE_ITEM * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD I264 T29 IC Net Properties T29_I2C_55S TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM T29_I2C D * =2x_DIELECTRIC ? T29 SPI Signal Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP T29_SPI_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD SPACING_RULE_SET LAYER TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_HEAD LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM T29_SPI * =2x_DIELECTRIC ? DP/T29 Connector Signal Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM T29DP_80D * =80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF TABLE_PHYSICAL_RULE_ITEM T29DP_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT =5x_DIELECTRIC ? TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT =7x_DIELECTRIC ? TABLE_SPACING_RULE_ITEM T29DP * TABLE_SPACING_RULE_ITEM T29DP TOP,BOTTOM I265 DP_T29SNK0_ML DP_T29SNK0_ML I266 I267 I268 I269 DP_T29SNK0_AUXCH DP_T29SNK0_AUXCH I270 I271 I272 I273 DP_T29SNK1_ML DP_T29SNK1_ML I274 I275 I276 I277 DP_T29SNK1_AUXCH DP_T29SNK1_AUXCH I282 I283 I284 I285 I286 I287 T29_SPI_CLK T29_SPI_MOSI T29_SPI_MISO T29_SPI_CS_L I288 SOURCE: Bill Cornelius’s T29 Routing Notes I289 I290 I291 C I292 I293 I294 I295 T29_R2D0 T29_R2D0 T29_R2D1 T29_R2D1 I322 I323 I296 I298 I297 I299 T29_D2R0 T29_D2R0 T29_D2R1 T29_D2R1 I300 I301 I302 I303 T29/DP Net Properties I320 B I321 I304 I305 I306 I308 I307 I309 I310 I311 I312 I313 DP_SDRVA_ML_EVEN DP_SDRVA_ML_EVEN DP_SDRVA_ML_ODD DP_SDRVA_ML_ODD DP_SDRVA_ML_EVEN DP_SDRVA_ML_EVEN DP_SDRVA_ML_ODD DP_SDRVA_ML_ODD DP_SDRVA_AUXCH DP_SDRVA_AUXCH I314 I315 I326 I327 I328 I329 I317 I324 I325 I319 SPACING DP_85D DP_85D DP_85D DP_85D DP_85D DP_85D DP_85D DP_85D DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DP_T29SNK0_ML_C_P DP_T29SNK0_ML_C_N DP_T29SNK0_ML_P DP_T29SNK0_ML_N DP_T29SNK0_AUXCH_C_P DP_T29SNK0_AUXCH_C_N DP_T29SNK0_AUXCH_P DP_T29SNK0_AUXCH_N DP_85D DP_85D DP_85D DP_85D DP_85D DP_85D DP_85D DP_85D DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DP_T29SNK1_ML_C_P DP_T29SNK1_ML_C_N DP_T29SNK1_ML_P DP_T29SNK1_ML_N DP_T29SNK1_AUXCH_C_P DP_T29SNK1_AUXCH_C_N DP_T29SNK1_AUXCH_P DP_T29SNK1_AUXCH_N T29_I2C_55S T29_I2C_55S T29_I2C T29_I2C I2C_T29_SCL I2C_T29_SDA T29_SPI_55S T29_SPI_55S T29_SPI_55S T29_SPI_55S T29_SPI T29_SPI T29_SPI T29_SPI T29_SPI_CLK T29_SPI_MOSI T29_SPI_MISO T29_SPI_CS_L T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP T29DP T29DP T29DP T29_R2D_C_P T29_R2D_C_N T29_D2R_P T29_D2R_N T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP T29DP T29DP T29DP T29DP T29DP T29DP T29DP T29DP T29DP T29DP T29DP T29_R2D_P T29_R2D_N T29_R2D_P T29_R2D_N T29_R2D_C_F_P T29_R2D_C_F_N T29_D2R_C_P T29_D2R_C_N T29_D2R_C_P T29_D2R_C_N T29DPA_D2R1_AUXCH_P T29DPA_D2R1_AUXCH_N T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP T29DP T29DP T29DP DP_SDRVA_ML_C_P DP_SDRVA_ML_C_N DP_SDRVA_ML_R_P DP_SDRVA_ML_R_N T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP T29DP T29DP T29DP T29DP T29DP T29DP T29DP T29DP T29DP T29DP T29DP DP_SDRVA_ML_P DP_SDRVA_ML_N DP_SDRVA_ML_P DP_SDRVA_ML_N DP_SDRVA_ML_P DP_SDRVA_ML_N DP_SDRVA_ML_P DP_SDRVA_ML_N DP_SDRVA_AUXCH_P DP_SDRVA_AUXCH_N DP_SDRVA_AUXCH_C_P DP_SDRVA_AUXCH_C_N T29DPA_ML_P T29DPA_ML_N T29DPA_ML_P T29DPA_ML_N T29DPA_ML_ODD T29DPA_ML_ODD T29DPA_ML_ODD T29DPA_ML_ODD I316 I318 PHYSICAL DP_A_EXT_AUXCH DP_A_EXT_AUXCH T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP T29DP T29DP T29DP T29DP T29DP T29DPA_ML_P T29DPA_ML_N T29DPA_ML_C_P T29DPA_ML_C_N DP_A_EXT_AUXCH_P DP_A_EXT_AUXCH_N A 33 33 33 33 33 33 33 D 33 33 43 33 43 33 33 33 33 33 63 33 63 33 63 33 63 C 63 63 63 63 63 64 63 64 63 64 63 64 64 64 63 63 63 63 63 63 63 63 63 63 63 B 63 63 63 63 63 63 64 71 63 64 71 63 64 71 63 64 71 63 64 71 63 64 71 63 64 63 64 63 64 63 64 SYNC_MASTER=CONSTRAINTS SYNC_DATE=04/06/2011 PAGE TITLE T29 Constraints DRAWING NUMBER Apple Inc 051-8871 R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED SIZE D REVISION 2.5.0 BRANCH PAGE 105 OF 109 SHEET 71 OF 74 A SMC SMBus Net Properties TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 1TO1_DIFFPAIR * =STANDARD =STANDARD =STANDARD =STANDARD 0.1 MM 0.1 MM NET_TYPE ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING TABLE_PHYSICAL_RULE_ITEM SMBUS_SMC_A_S3_SCL SMBUS_SMC_A_S3_SDA SMBUS_SMC_B_S0_SCL SMBUS_SMC_B_S0_SDA SMBUS_SMC_0_S0_SCL SMBUS_SMC_0_S0_SDA SMBUS_SMC_BSA_SCL SMBUS_SMC_BSA_SDA SMBUS_SMC_MGMT_SCL SMBUS_SMC_MGMT_SDA D SMB_50S SMB_50S SMB_50S SMB_50S SMB_50S SMB_50S SMB_50S SMB_50S SMB_50S SMB_50S SMB SMB SMB SMB SMB SMB SMB SMB SMB SMB SMBUS_SMC_A_S3_SCL SMBUS_SMC_A_S3_SDA SMBUS_SMC_B_S0_SCL SMBUS_SMC_B_S0_SDA SMBUS_SMC_0_S0_SCL SMBUS_SMC_0_S0_SDA SMBUS_SMC_BSA_SCL SMBUS_SMC_BSA_SDA SMBUS_SMC_MGMT_SCL SMBUS_SMC_MGMT_SDA 43 43 43 43 43 43 43 43 D 43 43 SMBus Charger Net Properties NET_TYPE ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING CHGR_CSI 1TO1_DIFFPAIR 1TO1_DIFFPAIR CHGR_CSI_P CHGR_CSI_N CHGR_CSO 1TO1_DIFFPAIR 1TO1_DIFFPAIR CHGR_CSO_P CHGR_CSO_N 52 52 52 52 C C B B A SYNC_MASTER=CONSTRAINTS SYNC_DATE=04/06/2011 PAGE TITLE SMC Constraints DRAWING NUMBER Apple Inc 051-8871 R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED SIZE D REVISION 2.5.0 BRANCH PAGE 106 OF 109 SHEET 72 OF 74 A TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET ALLOW ROUTE ON LAYER? LAYER MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP K21/K78 Specific Net Properties K21/K78 Specific Net Properties NET_TYPE NET_TYPE TABLE_PHYSICAL_RULE_ITEM SENSE_1TO1_55S * =1:1_DIFFPAIR =55_OHM_SE =55_OHM_SE =55_OHM_SE =1:1_DIFFPAIR ELECTRICAL_CONSTRAINT_SET =1:1_DIFFPAIR THERM_1TO1_55S * =1:1_DIFFPAIR =55_OHM_SE =55_OHM_SE =55_OHM_SE =1:1_DIFFPAIR =1:1_DIFFPAIR TABLE_PHYSICAL_RULE_ITEM DIFFPAIR * =1:1_DIFFPAIR SPACING_RULE_SET LAYER =1:1_DIFFPAIR =1:1_DIFFPAIR =1:1_DIFFPAIR TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 TABLE_SPACING_RULE_HEAD LINE-TO-LINE SPACING NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET WEIGHT TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_RULE_ITEM D SENSE * =2:1_SPACING CPU_COMP GND * GND_P2MM ? TABLE_SPACING_ASSIGNMENT_ITEM I295 TABLE_SPACING_RULE_ITEM THERM * =2:1_SPACING CPU_VCCSENSE GND * GND_P2MM ? I298 TABLE_SPACING_RULE_ITEM I297 AUDIO * =2:1_SPACING PHYSICAL ? I296 ELECTRICAL_CONSTRAINT_SET SPACING ENET_100D ENET_100D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D TABLE_PHYSICAL_RULE_ITEM ENETCONN ENETCONN SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA ENETCONN_P ENETCONN_N SATA_ODD_D2R_UF_P SATA_ODD_D2R_UF_N SATA_HDD_D2R_RDRVR_OUT_P SATA_HDD_D2R_RDRVR_OUT_N SATA_HDD_R2D_RDRVR_IN_P SATA_HDD_R2D_RDRVR_IN_N SATA_HDD_D2R_RDRVR_IN_P SATA_HDD_D2R_RDRVR_IN_N SATA_HDD_R2D_RDRVR_OUT_P SATA_HDD_R2D_RDRVR_OUT_N PCIE_CLK100M_AP (USB_EXTA) (USB_EXTA) SENSE_DIFFPAIR TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT I287 TABLE_SPACING_ASSIGNMENT_HEAD TABLE_SPACING_RULE_ITEM ENETCONN * 25 MILS NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET ENET_MDI GND * GND_P2MM CPU_THERMD I288 ? SENSE_DIFFPAIR TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING SENSE_DIFFPAIR WEIGHT TABLE_SPACING_RULE_ITEM GND * =STANDARD TABLE_SPACING_ASSIGNMENT_HEAD ? NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET CLK_PCIE GND * GND_P2MM PCIE GND * GND_P2MM SATA GND * GND_P2MM USB GND * GND_P2MM THERM_1TO1_55S THERM_1TO1_55S THERM_1TO1_55S THERM_1TO1_55S THERM_1TO1_55S THERM_1TO1_55S THERM_1TO1_55S THERM_1TO1_55S THERM THERM THERM THERM THERM THERM THERM THERM CPUTHMSNS_D2_P CPUTHMSNS_D2_N CPU_THERMD_P CPU_THERMD_N T29_THERMD_P T29_THERMD_N T29_MLBBOT_THMSNS_P T29_MLBBOT_THMSNS_N SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE SENSE SENSE SENSE SENSE SENSE ISNS_HS_COMPUTING_N ISNS_HS_COMPUTING_P ISNS_HS_OTHER_N ISNS_HS_OTHER_P CPUVCCIOS0_CS_N CPUVCCIOS0_CS_P SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S LVDS_90D LVDS_90D SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE LVDS LVDS CPUIMVP_ISNS1_P CPUIMVP_ISNS1_N CPUIMVP_ISNS2_P CPUIMVP_ISNS2_N CPUIMVP_ISNS1G_P CPUIMVP_ISNS1G_N CPUIMVP_ISUM_R_P CPUIMVP_ISUM_R_N CPUIMVP_ISUMG_R_P CPUIMVP_ISUMG_R_N CPUIMVP_ISNS_P CPUIMVP_ISNS_N VCCSAS0_CS_P VCCSAS0_CS_N CPUIMVP_ISUMG_P CPUIMVP_ISUMG_N ISNS_CPU_N ISNS_CPU_P ISNS_HDD_N ISNS_HDD_P ISNS_HDD_R_N ISNS_HDD_R_P ISNS_LCDBKLT_N ISNS_LCDBKLT_P ISNS_ODD_N ISNS_ODD_P ISNS_ODD_R_N ISNS_ODD_R_P ISNS_1V5_S3_N ISNS_1V5_S3_P ISNS_P1V8GPU_R_N ISNS_P1V8GPU_R_P ISNS_AIRPORT_N ISNS_AIRPORT_P LVDS_CONN_A_CLK_F_N LVDS_CONN_A_CLK_F_P 46 (USB_EXTA) 46 (USB_EXTA) SENSE_DIFFPAIR TABLE_SPACING_ASSIGNMENT_ITEM SPACING_RULE_SET LAYER LINE-TO-LINE SPACING SENSE_DIFFPAIR WEIGHT TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_RULE_ITEM GND_P2MM * 0.20 MM 1000 PWR_P2MM * 0.20 MM 1000 SENSE_DIFFPAIR TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_RULE_ITEM CLK_PCIE SB_POWER * PWR_P2MM SATA SB_POWER * PWR_P2MM SENSE_DIFFPAIR TABLE_SPACING_ASSIGNMENT_ITEM NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET SENSE_DIFFPAIR TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CLK GND * GND_P2MM MEM_CMD GND * GND_P2MM MEM_CTRL GND * GND_P2MM USB SB_POWER * PWR_P2MM SENSE_DIFFPAIR TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM C SENSE_DIFFPAIR TABLE_SPACING_ASSIGNMENT_ITEM MEM_DATA GND * TABLE_SPACING_ASSIGNMENT_HEAD GND_P2MM NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SENSE_DIFFPAIR SPACING_RULE_SET TABLE_SPACING_ASSIGNMENT_ITEM MEM_DQS GND * TABLE_SPACING_ASSIGNMENT_ITEM GND_P2MM LVDS GND * GND_P2MM SENSE_DIFFPAIR TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM MEM_40S * OVERRIDE OVERRIDE OVERRIDE OVERRIDE 0.09 MM 400 MIL OVERRIDE OVERRIDE OVERRIDE MEM_72D * OVERRIDE OVERRIDE OVERRIDE 0.09 MM 400 MIL OVERRIDE OVERRIDE * OVERRIDE OVERRIDE OVERRIDE OVERRIDE 0.09 MM 400 MIL OVERRIDE OVERRIDE OVERRIDE * OVERRIDE OVERRIDE 0.09 MM 400 MIL * OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE 0.076 MM 10 mm OVERRIDE OVERRIDE OVERRIDE OVERRIDE USB_85D TOP 0.1 MM 500 MIL OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE TOP OVERRIDE OVERRIDE OVERRIDE OVERRIDE 0.09 MM 400 MIL OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE SENSE_DIFFPAIR I284 I285 OVERRIDE SENSE_DIFFPAIR I282 I283 TABLE_PHYSICAL_RULE_ITEM CPU_27P4S I255 I281 TABLE_PHYSICAL_RULE_ITEM OVERRIDE SENSE_DIFFPAIR OVERRIDE TABLE_PHYSICAL_RULE_ITEM PCIE_85D OVERRIDE SENSE_DIFFPAIR I254 I256 TABLE_PHYSICAL_RULE_ITEM MEM_85D I251 OVERRIDE TABLE_PHYSICAL_RULE_ITEM MEM_37S SENSE_DIFFPAIR OVERRIDE I253 OVERRIDE SENSE_DIFFPAIR I250 I252 TABLE_PHYSICAL_RULE_ITEM OVERRIDE I249 SENSE_DIFFPAIR I286 SENSE_DIFFPAIR TABLE_PHYSICAL_RULE_ITEM CLK_PCIE_90D TOP OVERRIDE OVERRIDE 0.09 MM OVERRIDE OVERRIDE OVERRIDE SENSE_DIFFPAIR 400 MIL OVERRIDE OVERRIDE OVERRIDE I292 SENSE_DIFFPAIR I291 B I335 SENSE_DIFFPAIR I336 I293 I294 46 45 45 I331 SPKRAMP_INR I332 I334 MAX98300_R I333 DIFFPAIR DIFFPAIR 44 58 44 56 57 44 57 I299 44 57 I300 44 57 I302 44 I301 44 I304 44 I303 44 I305 I307 I306 53 I310 53 I308 56 57 I309 56 57 I311 I312 I313 37 45 I314 37 45 I315 I316 SPK_OUT SPK_OUT SPK_OUT SPK_OUT SPK_OUT SPK_OUT AUD_DIFF AUD_DIFF AUD_DIFF AUD_DIFF AUD_DIFF AUD_DIFF AUD_DIFF AUD_DIFF AUD_DIFF AUD_DIFF AUD_DIFF AUD_DIFF AUD_DIFF AUD_DIFF SPKRAMP_INR AUD_DIFF AUD_DIFF AUD_DIFF DIFFPAIR DIFFPAIR AUDIO AUDIO MAX98300_R_P MAX98300_R_N 45 D 52 45 52 45 52 38 38 38 38 DP_IG_AUX_CH_C_P DP_IG_AUX_CH_C_N SPKRAMP_L_P_OUT SPKRAMP_L_N_OUT SPKRAMP_SUB_P_OUT SPKRAMP_SUB_N_OUT SPKRAMP_R_P_OUT SPKRAMP_R_N_OUT SSM2315_SUB_N SSM2315_SUB_P SSM2315_L_N SSM2315_L_P SSM2315_R_N SSM2315_R_P AUD_LO2_N_R AUD_LO2_P_R AUD_LO1_N_R AUD_LO1_P_R AUD_LO2_N_L AUD_LO2_P_L SPKRAMP_INL_P SPKRAMP_INL_N SPKRAMP_INR_P SPKRAMP_INR_N SPKRAMP_INSUB_P SPKRAMP_INSUB_N DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR 1TO1_DIFFPAIR 1TO1_DIFFPAIR 1TO1_DIFFPAIR 1TO1_DIFFPAIR 1TO1_DIFFPAIR 1TO1_DIFFPAIR 1TO1_DIFFPAIR 1TO1_DIFFPAIR 1TO1_DIFFPAIR 1TO1_DIFFPAIR 1TO1_DIFFPAIR 1TO1_DIFFPAIR 1TO1_DIFFPAIR 1TO1_DIFFPAIR DIFFPAIR DIFFPAIR 1TO1_DIFFPAIR 1TO1_DIFFPAIR AUDIO AUDIO AUDIO AUDIO AUDIO AUDIO AUDIO AUDIO AUDIO AUDIO AUDIO AUDIO AUDIO AUDIO AUDIO AUDIO AUDIO AUDIO AUDIO AUDIO AUDIO AUDIO AUDIO AUDIO USB_85D USB_85D USB USB USB_TPAD_R_P USB_TPAD_R_N SB_POWER SB_POWER PP3V3_S5 PP3V3_S0 45 55 GND 50 51 50 51 C 39 50 73 39 50 73 7 GND 45 55 36 45 B 36 45 Misc Net Properties NET_TYPE PHYSICAL SPACING (USB_TPAD) USB_85D USB_85D USB_85D USB_85D USB_85D USB_85D USB USB USB USB USB USB USB_EXTA_MUXED_P USB_EXTA_MUXED_N USB_LT1_P USB_LT1_N USB_TPAD_CONN_P USB_TPAD_CONN_N SMBUS_SMC_MGMT_SDA SMBUS_SMC_MGMT_SCL SMB_55S SMB_55S SMB SMB I2C_SMC_SMS_SDA_R I2C_SMC_SMS_SCL_R SMB_55S SMB_55S SMB_55S SMB_55S SMB SMB SMB SMB I2C_TCON_SCL I2C_TCON_SDA I2C_TCON_SCL_CONN I2C_TCON_SDA_CONN I317 (USB_EXTA) I318 (USB_EXTA) I319 (USB_EXTA) I320 (USB_EXTA) I322 (USB_TPAD) I324 39 50 73 48 48 39 50 73 I326 50 I325 50 I328 I327 I330 I329 A DISPLAYPORT DISPLAYPORT 45 SPACING AUDIO AUDIO CONN_USB2_BT_P CONN_USB2_BT_N USB_LT2_P USB_LT2_N USB USB USB USB DP_85D DP_85D 44 58 NET_TYPE SPKRAMP_INR_P SPKRAMP_INR_N USB_85D USB_85D USB_85D USB_85D 52 46 Audio Net Properties PHYSICAL PCIE_CLK100M_AP_CONN_P PCIE_CLK100M_AP_CONN_N CHGR_CSI_R_P CHGR_CSI_R_N CHGR_CSO_R_P CHGR_CSO_R_N USB2_EXTA_MUXED_P USB2_EXTA_MUXED_N USB2_LT1_P USB2_LT1_N 46 46 ELECTRICAL_CONSTRAINT_SET ELECTRICAL_CONSTRAINT_SET CLK_PCIE_90D CLK_PCIE CLK_PCIE_90D CLK_PCIE 1TO1_DIFFPAIR 1TO1_DIFFPAIR 1TO1_DIFFPAIR 1TO1_DIFFPAIR USB_85D USB USB_85D USB USB_85D USB USB_85D USB 46 TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 SPACING 46 TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_RULE_HEAD PHYSICAL Memory Constraint Relaxations SYNC_MASTER=CONSTRAINTS SYNC_DATE=04/06/2011 PAGE TITLE Allow 0.127 mm necks for >0.127 mm lines for ARD fanout Project Specific Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER MEM_72D BOTTOM ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH 0.127 MM 6.35 MM DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP DRAWING NUMBER TABLE_PHYSICAL_RULE_ITEM Apple Inc TABLE_PHYSICAL_RULE_ITEM MEM_85D TOP 0.1 MM R THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED SIZE D 2.5.0 6.35 MM NOTICE OF PROPRIETARY PROPERTY: 051-8871 REVISION BRANCH PAGE 108 OF 109 SHEET 73 OF 74 A K90i Board-Specific Spacing & Physical Constraints TABLE_BOARD_INFO BOARD LAYERS BOARD AREAS BOARD UNITS (MIL or MM) ALLEGRO VERSION TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM NO_TYPE,BGA MM 15.5.1 TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_PHYSICAL_RULE_ITEM DEFAULT * Y =50_OHM_SE =50_OHM_SE 10 MM MM MM DEFAULT * 0.1 MM * Y =DEFAULT =DEFAULT 10 MM =DEFAULT =DEFAULT NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET * * BGA BGA_P1MM TABLE_SPACING_ASSIGNMENT_ITEM ? TABLE_PHYSICAL_RULE_ITEM STANDARD TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM STANDARD * =DEFAULT ? BGA_P1MM * =DEFAULT ? TABLE_SPACING_ASSIGNMENT_ITEM MEM_CLK * BGA BGA_P2MM CLK_PCIE * BGA BGA_P2MM CLK_SLOW * BGA BGA_P2MM TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_PHYSICAL_RULE_HEAD D PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH 50_OHM_SE TOP,BOTTOM Y 0.110 MM 0.090 MM MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_SPACING_RULE_ITEM BGA_P2MM * =DEFAULT D TABLE_SPACING_ASSIGNMENT_ITEM ? TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM 50_OHM_SE * Y LAYER ALLOW ROUTE ON LAYER? 0.090 MM 0.090 MM =STANDARD =STANDARD =STANDARD TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LINE-TO-LINE SPACING WEIGHT 1.5:1_SPACING LAYER * 0.15 MM ? 2:1_SPACING * 0.2 MM ? TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LINE-TO-LINE SPACING WEIGHT 2X_DIELECTRIC LAYER * 0.140 MM ? 3X_DIELECTRIC * 0.210 MM ? 4X_DIELECTRIC * 0.280 MM ? TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM 40_OHM_SE TOP,BOTTOM Y TABLE_SPACING_RULE_ITEM DIFFPAIR NECK GAP 0.170 MM 0.170 MM TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM 40_OHM_SE ISL3,ISL4,ISL9,ISL10 Y 0.140 MM 0.140 MM =STANDARD =STANDARD =STANDARD 2.5:1_SPACING * 0.25 MM ? TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM 40_OHM_SE * Y =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD 3:1_SPACING * 0.3 MM ? TABLE_SPACING_RULE_ITEM 5X_DIELECTRIC * 0.350 MM ? 7X_DIELECTRIC * 0.490 MM ? TABLE_SPACING_RULE_ITEM 4:1_SPACING * 0.4 MM ? TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH 37_OHM_SE TOP,BOTTOM Y 0.195 MM 0.1 MM 37_OHM_SE ISL3,ISL4,ISL9,ISL10 Y 0.160 MM 0.1 MM =STANDARD =STANDARD =STANDARD 37_OHM_SE * Y =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 27P4_OHM_SE TOP,BOTTOM Y 0.310 MM 0.2 MM 27P4_OHM_SE * Y 0.250 MM 0.2 MM =STANDARD =STANDARD =STANDARD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 55_OHM_SE TOP,BOTTOM Y 0.090 MM 0.090 MM 55_OHM_SE * Y 0.076 MM 0.076 MM =STANDARD =STANDARD =STANDARD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD C C TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 1:1_DIFFPAIR * Y =STANDARD =STANDARD =STANDARD 0.1 MM 0.1 MM TABLE_PHYSICAL_RULE_ITEM 72_OHM_DIFF * Y =STANDARD =STANDARD =STANDARD =STANDARD 72_OHM_DIFF ISL3,ISL10 Y 0.135 MM 0.135 MM =STANDARD 0.130 MM 0.130 MM 72_OHM_DIFF ISL4,ISL9 Y 0.155MM 0.155 MM 0.130 MM 0.130 MM 72_OHM_DIFF TOP,BOTTOM Y 0.165 MM 0.165 MM 0.130 MM 0.130 MM PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD MAXIMUM NECK LENGTH TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 85_DIFF_BGA * =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF 85_DIFF_BGA ISL3,ISL4 Y 0.075 MM 0.075 MM 0.125 MM 0.125 MM 85_DIFF_BGA ISL9,ISL10 Y 0.075 MM 0.075 MM 0.125 MM 0.125 MM TABLE_PHYSICAL_RULE_ITEM 85_OHM_DIFF * Y =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM 85_OHM_DIFF ISL3,ISL10 Y 0.095 MM 0.1 MM 0.170 MM 0.170 MM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM 85_OHM_DIFF ISL4,ISL9 Y 0.115 MM 0.115 MM 0.170 MM 0.170 MM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM 85_OHM_DIFF TOP,BOTTOM Y 0.130 MM 0.130 MM 0.195 MM 0.195 MM NOTE: 85_DIFF_BGA is 85-ohms differential impedance on outer layers and 80-ohms on inner layers TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 90_DIFF_BGA * =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF 90_DIFF_BGA ISL3,ISL4 Y 0.075 MM 0.075 MM 0.125 MM 0.125 MM 90_DIFF_BGA ISL9,ISL10 Y 0.075 MM 0.075 MM 0.125 MM 0.125 MM TABLE_PHYSICAL_RULE_ITEM 90_OHM_DIFF * Y =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM B 90_OHM_DIFF ISL3,ISL10 Y 0.089 MM 0.089 MM 0.210 MM 0.210 MM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM 90_OHM_DIFF ISL4,ISL9 Y 0.105 MM 0.105 MM 0.210 MM 0.210 MM B TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM 90_OHM_DIFF TOP,BOTTOM Y 0.115 MM 0.115 MM PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH 0.210 MM 0.210 MM NOTE: 90_DIFF_BGA is 90-ohms differential impedance on outer layers and 85-ohms on inner layers DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_HEAD MAXIMUM NECK LENGTH TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 100_DIFF_BGA * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF 100_DIFF_BGA ISL3,ISL4 Y 0.075 MM 0.075 MM 0.125 MM 0.125 MM 100_DIFF_BGA ISL9,ISL10 Y 0.075 MM 0.075 MM 0.125 MM 0.125 MM TABLE_PHYSICAL_RULE_ITEM 100_OHM_DIFF * Y =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM 100_OHM_DIFF ISL3,ISL10 Y 0.074 MM 0.074 MM 0.250 MM 0.250 MM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM 100_OHM_DIFF ISL4,ISL9 Y 0.085 MM 0.085 MM 0.250 MM 0.250 MM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM 100_OHM_DIFF TOP,BOTTOM Y 0.091 MM 0.091 MM 0.200 MM 0.200 MM NOTE: 100_DIFF_BGA is 100-ohms differential impedance on outer layers and 95-ohms on inner layers NOTE: 110_DIFF is 110-ohms differential impedance on outer layers and 105-ohms on inner layers TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 110_OHM_DIFF * Y =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD 110_OHM_DIFF ISL3,ISL10 N 0.070 MM 0.070 MM 0.330 MM 0.330 MM 110_OHM_DIFF ISL4,ISL9 Y 0.071 MM 0.071 MM 0.300 MM 0.300 MM 110_OHM_DIFF TOP,BOTTOM Y 0.077 MM 0.077 MM 0.280 MM 0.280 MM DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM NOTE: These are Intel recommended impedances for PEG, unused on K90i TABLE_PHYSICAL_RULE_HEAD A PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH 48_OHM_SE TOP,BOTTOM Y 0.120 MM 0.165 MM 48_OHM_SE * Y 0.097 MM 0.090 MM =STANDARD =STANDARD =STANDARD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP MAXIMUM NECK LENGTH TABLE_PHYSICAL_RULE_ITEM SYNC_MASTER=CONSTRAINTS SYNC_DATE=04/06/2011 PAGE TITLE TABLE_PHYSICAL_RULE_ITEM PCB Rule Definitions DRAWING NUMBER TABLE_PHYSICAL_RULE_HEAD Apple Inc TABLE_PHYSICAL_RULE_ITEM 80_OHM_DIFF * Y =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD 051-8871 R ISL3,ISL10 Y 0.110 MM 0.110 MM 0.170 MM 0.170 MM ISL4,ISL9 Y 0.129 MM 0.129 MM 0.170 MM 0.170 MM 80_OHM_DIFF TOP,BOTTOM Y 0.145 MM 0.145 MM 0.180 MM 0.180 MM NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM D 2.5.0 TABLE_PHYSICAL_RULE_ITEM 80_OHM_DIFF 80_OHM_DIFF SIZE REVISION BRANCH PAGE 109 OF 109 SHEET 74 OF 74 A ... PCBA ,MLB, 1.6GHZ,SA 2GB ,K78 K78_CMNPTS,CPU:1.6GHZ,EEEE:DLCT,DDR3:SAMSUNG_2GB 639-1999 PCBA ,MLB, 1.6GHZ,SA 4GB ,K78 K78_CMNPTS,CPU:1.6GHZ,EEEE:DLD6,DDR3:SAMSUNG_4GB 639-1987 PCBA ,MLB, 1.6GHZ,MI 2GB ,K78. .. PCBA ,MLB, 1.5GHZ,SA 4GB ,K78 K78_CMNPTS,CPU:1.5GHZ,EEEE:DLCM,DDR3:SAMSUNG_4GB 639-1992 PCBA ,MLB, 1.5GHZ,MI 2GB ,K78 K78_CMNPTS,CPU:1.5GHZ,EEEE:DLCW,DDR3:MICRON_2GB 639-1993 PCBA ,MLB, 1.5GHZ,EL 4GB ,K78. .. PCBA ,MLB, 1.4GHZ,SA 2GB ,K78 K78_CMNPTS,CPU:1.4GHZ,EEEE:DLD3,DDR3:SAMSUNG_2GB 639-1984 PCBA ,MLB, 1.4GHZ,SA 4GB ,K78 K78_CMNPTS,CPU:1.4GHZ,EEEE:DLCL,DDR3:SAMSUNG_4GB 639-2000 PCBA ,MLB, 1.4GHZ,MI 2GB,K78