87cd6 macbook air a1304 m96 MLB 051 7631 230

8 CK APPD ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5% ALL CAPACITANCE VALUES ARE IN MICROFARADS ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ REV ZONE ECN ENG APPD DESCRIPTION OF CHANGE SCHEM,MLB,M96 EVT 08/01/2008 DATE DATE D D (.csa) Date Page Contents TABLE_TABLEOFCONTENTS_HEAD TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM C TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM B TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM Sync 1 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 (.csa) Page TABLE_TABLEOFCONTENTS_HEAD N/A Table of Contents N/A System Block Diagram WFERRY-WF Power Block Diagram POWER CONFIGURATION OPTIONS 05/11/2006 TABLE_TABLEOFCONTENTS_ITEM 06/30/2005 TABLE_TABLEOFCONTENTS_ITEM (N/A) TABLE_TABLEOFCONTENTS_ITEM N/A TABLE_TABLEOFCONTENTS_ITEM (MASTER) TABLE_TABLEOFCONTENTS_ITEM (N/A) Acoustic Cap BOM Config Tables N/A Functional Test and No-Tests (MASTER) 06/15/2006 Power Aliases WFERRY SIGNAL ALIAS /RESET (MASTER) (MASTER) 10 02/04/2008 CPU FSB TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM M97 11 CPU Power & Ground (MASTER) TABLE_TABLEOFCONTENTS_ITEM 04/26/2006 TABLE_TABLEOFCONTENTS_ITEM 02/04/2008 TABLE_TABLEOFCONTENTS_ITEM 02/04/2008 TABLE_TABLEOFCONTENTS_ITEM 02/04/2008 TABLE_TABLEOFCONTENTS_ITEM 02/04/2008 TABLE_TABLEOFCONTENTS_ITEM (MASTER) 12 CPU Decoupling & VID MSARWAR eXtended Debug Port (XDP) M97 13 14 MCP CPU Interface M97 15 MCP Memory Interface M97 MCP Memory Misc M97 16 17 MCP PCIe Interfaces 02/04/2008 TABLE_TABLEOFCONTENTS_ITEM 02/04/2008 TABLE_TABLEOFCONTENTS_ITEM 02/04/2008 TABLE_TABLEOFCONTENTS_ITEM 02/04/2008 TABLE_TABLEOFCONTENTS_ITEM 02/04/2008 TABLE_TABLEOFCONTENTS_ITEM 02/04/2008 TABLE_TABLEOFCONTENTS_ITEM 02/04/2008 TABLE_TABLEOFCONTENTS_ITEM M97 18 MCP Ethernet & Graphics M97 19 MCP PCI & LPC M97 20 MCP SATA & USB M97 21 MCP HDA & MISC M97 22 MCP Power & Ground M97 MCP Standard Decoupling M97 25 26 MCP Graphics Support M97 SB Misc M97 28 29 FSB/DDR3 Vref Margining 02/04/2008 TABLE_TABLEOFCONTENTS_ITEM 02/04/2008 TABLE_TABLEOFCONTENTS_ITEM 01/15/2008 TABLE_TABLEOFCONTENTS_ITEM 01/30/2008 TABLE_TABLEOFCONTENTS_ITEM (MASTER) TABLE_TABLEOFCONTENTS_ITEM BEN 30 DDR3 Support T18_MLB 31 DDR3 DRAM Channel A (0-31) (MASTER) TABLE_TABLEOFCONTENTS_ITEM 32 DDR3 DRAM Channel A (32-63) 33 (MASTER) DDR3 DRAM Channel B (0-31) TABLE_TABLEOFCONTENTS_ITEM (MASTER) TABLE_TABLEOFCONTENTS_ITEM 34 DDR3 DRAM Channel B (32-63) 35 06/20/2005 DDR BYPASSING MEMORY DDR BYPASSING MEMORY Memory Active Termination M70 Wireless M93 Connector M70 36 Date 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 Contents Sync 52 02/04/2008 M97 SMBUS CONNECTIONS BEN Voltage Sensors M70 Current Sensing YUNWU TEMPERATURE SENSORS M70 Fan M70 Sudden Motion Sensor (SMS) M76_MLB SPI ROM CHANGZHANG DC-In & Battery Connectors M70 IMVP6 CPU VCore Regulator POWER MCP CORE REGULATOR MINGJING 53 01/09/2007 54 02/04/2008 55 01/09/2007 56 01/09/2007 59 01/12/2007 61 02/15/2008 69 01/09/2007 71 07/13/2005 72 06/24/2008 73 1.8V LDO Supply 74 05/21/2008 1V05 S5 Power Supply RXU_K20 1.5V/0.75V Supplies M70 5V / 3.3V Power Supply RXU_K20 POWER SEQUENCING YUAN.MA POWER FETS YUAN.MA PBUS Supply/Battery Charger M70 LVDS,Camera Conn and ALS Conn GPU DISPLAYPORT SUPPORT NMARTIN DisplayPort Connector M98_MLB LED Backlight Driver (MASTER) LCD Backlight Support M97 75 01/09/2007 76 05/21/2008 77 02/04/2008 78 C 02/04/2008 79 01/09/2007 90 06/23/2006 93 12/18/2007 94 01/17/2008 97 (MASTER) 98 02/04/2008 99 Additional CPU/GPU Decoupling 100 02/04/2008 CPU/FSB Constraints M97 Memory Constraints M97 MCP Constraints M97 MCP Constraints M97 SMC Constraints M97 M96 Power and Ground Nets (MASTER) M96 RULE DEFINITIONS M97 101 02/04/2008 102 02/04/2008 103 02/04/2008 106 02/04/2008 108 (MASTER) 109 02/04/2008 TABLE_TABLEOFCONTENTS_ITEM 06/20/2005 37 01/09/2007 41 B 01/09/2007 42 (MASTER) Hatch and Audio Connectors (MASTER) SATA Connectors CHANGZHANG USB EXTERNAL CONNECTORS M70 45 02/05/2008 46 01/09/2007 48 IPD Connector 49 02/21/2008 SMC M97 SMC SUPPORT M70 LPC+SPI Debug Connector CHANGZHANG 50 01/09/2007 51 01/24/2008 TABLE_TABLEOFCONTENTS_ITEM DIMENSIONS ARE IN MILLIMETERS A APPLE INC METRIC XX X.XX DRAFTER Schematic / PCB #’s PART NUMBER THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING QTY ENG APPD MFG APPD QA APPD DESIGNER RELEASE SCALE I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART ANGLES DESCRIPTION REFERENCE DES 051-7631 SCHEM,MLB,M96 SCH CRITICAL CRITICAL 820-2375 PCBF,MLB,M96 PCB CRITICAL A NOTICE OF PROPRIETARY PROPERTY DESIGN CK X.XXX BOM OPTION TITLE DO NOT SCALE DRAWING DRAWING SIZE TITLE=M96_MLB ABBREV=DRAWING LAST_MODIFIED=Fri Aug SCHEM,MLB,M96 NONE THIRD ANGLE PROJECTION 09:54:13 2008 MATERIAL/FINISH NOTED AS APPLICABLE D DRAWING NUMBER REV 051-7631 2.3.0 SHT 1 OF 71 D D U1000 CPU 1.6/1.8 GHz J6900/80 Pg 10 J1300 Pg 11 DC/Batt Power Conn Supplies PG 51 PG 52-59 MINI XDP CONN PG 12 FSB 64-Bit J9000 TOP ALS J4100 M93 PG 60 800 MHz MEM Active Parallel FSB J4200 Pg 14 HDMI J9000 Pg 15/16 FLAT PANEL PG 37 U3100 U3110 U3120 U3130 U3210 U3220 U3230 U3240 U1400 Main Memory Display Port Term J4800 Pg 35 IPD DDR3 - Dual Channel 0.75V - 64 Bits DDR3 RAM 1066 MHz LVDS Pg 18 C CPU/MCP T-Diode Thermal Sensor U5515 PG 47 Local TEMP near power supplies U5550 PG 47 Local TEMP near Air Vent U5560 PG 47 Local TEMP near Front Edge U5570 PG 47 PG 40 Pg29/30 LVDS Int Disp Conn PG 36 Misc C Pg 21 Camera MCP79U SUDDEN MOTION DETECT U5900 PG 60 PG 49 U3300 U3310 U3320 U3330 U3410 U3420 U3430 U3440 USB Ln0 Pg 20 Core VOLTAGE SENSORS PCI-E Pg31/32 SMB Pg 17 A BSA MGMT ADC Fan Ser J5100 LPC Pg 19 Prt FrankCard Conn U4900 PG 43 PG 41 U9500 NAND Flash Flash Controller PG 64 B SMC Ln3 NAND PG 48 DDR3 RAM Pg 24 Ln2 U9600 U9601 J5600 Ln1 FAN CONN PG 45 SATA DACS LAN PCI HDA Pg20 Pg18 Pg18 Pg 19 Pg 21 SPI Pg 21 PG 63 J4500 B B HDD SATA U6100 Conn Well Spring SPI J4200 J4800 Trackpad/Keyboard PG 38 Boot ROM PG 40 External USB PG 50 PG 37 J9050 DIGITAL MIC J4100 CONNECTOR M93 AirPort/BT PG 60 Pg 36 J4260 Audio Connector Pg 37 System Block Diagram A SYNC_MASTER=WFERRY-WF SYNC_DATE=05/11/2006 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC SCALE SHT NONE REV 051-7631 2.3.0 OF 71 A DC-JACK M96 POWER SYSTEM ARCHITECTURE 01 6A FUSE PP18V5_DCIN D6901 PPDCIN_G3H_R PP18V5_G3H_CHGR 02 PPDCIN_G3H PPVBATT_G3H_R J6980 PPBUSB_G3H D6901 PPVIN_G3H_DCIN 04 SMC_RESET_L 03 3.425V G3HOT LTC3470A VIN U6900 (PAGE 51) SMBUS_SMC_BSA_SDA 7A FUSE R7980 PPVBAT_G3H_CHGR_REG SMC PWRGD RN5VD30A-F U5000 (PAGE 42) ENABLE SMBUS_SMC_BSA_SCL ENABLES PP3V42_G3H_SMC D6901 F6900 D PPBUSB_G3H PP3V42_G3H_REG DEBUG_RESET_L LPC_RESET* Q7853 SMC_LRESET_L FC_RESET_L PP1V05_S0_FET PBUSA_G3H VOUT 2S2P BATTERY A ISL6258 U7900 PCA9557D_RESET_L VIN (0.002) V R7930 Q7950 42 AIRPORT_RST_L 02 P1V05S0_EN 26 (PAGE 59) CHGR_BGATE U1400 1.05V 10 P1V05_S5_EN (S5) ENA1 33 MCPCORES0_EN (S0) ENA2 BKLT_PLT_RST_L MCP79U 11 Q5315 VIN 01 D 27 PCIE_RESET* PBUS Supply/ BATTERY CHARGER 43 (200 mA MAX CURRENT) PP1V05_S5_REG (7 A MAX CURRENT) VOUT1 MCPCORE 40 PPMCPCORE_S0_REG VOUT2 MCP_PS_PWRGD 34 PS_PWRGD PWRBTN* (25 A MAX CURRENT) RSMRST* ISL6236 PG1 U7200 (PAGE 53) BATT_POS_F P1V05_S5_PGOOD PG2 FSB_CPURST_L 12 MCPCORES0_PGOOD CPU_RESET* CPU_PWRGD 35 CPU_PWRGD 41 38 02 PPVCORE_S0_CPU_REG CPUVCORE PPVCORE_S0_CPU VOUT VIN (30 A MAX CURRENT) PP3V3_S5_PWRCTI IMVP_VR_ON R-100K C-NoStuff C MCP79U R-1K C-0.47uF 39 VR_PWRGOOD_DELAY ISL6261CRZ PGOOD U7100 (PAGE 52) 37 16 P5VS3_EN_L DELAY 15 VR_ON DELAY Q7710 VR_PWRGOOD_DELAY MCPCORES0_PGOOD 26 22 =PPBUSB_G3H 25 04 SMC_ADAPTER_PRESENT PP1V5_S0_VMON IMVP_VR_ON DDRREG_EN SMC SLP_S3* C PWRGOOD 19 DELAY R-5.1K C-0.47uF CPU PPBUSA_G3H P3V3S3_EN PM_SLP_S4_L SLP_S5* U2850 26 03 PP3V42_G3H_PWRCTL U7770 LTC2909 ADJ1 FSB_CPURST_L 35 RESET* P5V3V3_PGOOD PP1V05_S0_VMON U1000 (PAGE 10) 44 S0PGOOD_PWROK ADJ2 RST* ALL_SYS_PWRGD (PAGE 57) U4900 (PAGE 41) DELAY Q7700 P60 SMC_PM_G2_EN PM_G2_P3V3S5_EN_L PP3V3S5_EN_L R-100K C-NoStuff WOW_EN (S5) 08 PCI_RESET0* DELAY 07 29 P1V05_S5_EN SMC_PM_G2_EN R-5.1K C-0.47uF 26 10 PM_WLAN_EN_L PP3V3_S5_PWRCTL PM_SLP_S3_L 09 P3V3S0_EN Q7840 PP5V_S0_FET P5VS0_EN 28 26 PBUSVSENS_EN 02 P5VS0_EN_L 27 DELAY R-0 C-0.47uF B P1V05S0_EN (S0) 16 26 Q7621 P5VS3_EN_L DELAY R-5.1k C-0.47uF P1V8S0_EN (S0) VIN 3.3V VO2 (S3) 08 26 09 DELAY CPUVTTS0_EN (S0) SENSE (? A MAX CURRENT) 13 PP3V3_S3 RSMRST_IN(P13) RESET 20 P3V3S3_EN_L P1V8_S0_EN EN PPVIN_S0_P1V8S0 1.8V S0 TPS19918 U7360 VIN 33 VOUT (PAGE 54) SMC_LRESET_L SMC_RESET_L PP1V8_S0_REG (200 mA MAX) RST* 32 15 15 28 Q7830 PM_PWRBTN_L P17(BTN_OUT) 05 PLT_RST* 31 06 PWR_BUTTON(P90) 21 BATTERY ONLY: 18 37 (PAGE 57) PGOOD1,2 36 IMVP_VR_ON RSMRST_PWRGD RSMRST_PWRGD MR 99ms DLY IMVP_VR_ON(P16) SMC_ONOFF_L DELAY MCPCORES0_EN (S0) PWRGD(P12) B PM_RSMRST_L RSMRST_OUT(P15) U7740 TPS19918 PP1V5_S5_PGOOD 12 Q7810 P5V3V3_PGOOD R-22k C-0,47uF P3V3_S5_PWRCTL PP3V3_S5 TPS51120 U7600 (PAGE 60) SMC ALL_SYS_PWRGD (S5) MCPDDR_EN (S0) 14 22 PP5V_S3 09 PP3V3_S5_REG PP3V3S5_EN_L EN2 R-33k C-0.47uF VO1 31 DELAY R-0 C-0.47uF 5V EN1 17 PP5V_S3_REG (? A MAX CURRENT) PM_SLP_S5_L SLP_S5_L(P95) PM_SLP_S4_L SLP_S4_L(P94) PM_SLP_S3_L SLP_S3_L(P93) 24 PP3V3_S0_FET U4900 (PAGE 41) P3V3S0_EN_L 27 Q7801 A Power Block Diagram 27 =PP1V5_S0_FET PP1V5_S3_P1V5S0FET SYNC_MASTER=POWER PP0V75_S3_VTTREF SYNC_DATE=06/30/2005 NOTICE OF PROPRIETARY PROPERTY MCPDDR_EN 22 26 VIN VLDOIN 1.5V DDRREG_EN S5 MEM_VTT_EN_R R2870 DDRVTT_EN THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING S3 VOUT1 23 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE PP1V5_S3_REG (11 A MAX CURRENT) II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART 0.75V VOUT2 PP0V75_S0_REG 30 29 TPS51116 U7500 (PAGE 55) SIZE DRAWING NUMBER D DDRREG_PGOOD APPLE INC 24 SCALE SHT NONE REV 051-7631 2.3.0 OF 71 A PAGE_BORDER=TRUE BOMs BOMOPTION Groups TABLE_BOMGROUP_HEAD BOM NUMBER BOM NAME BOM OPTIONS TABLE_BOMGROUP_HEAD BOM GROUP BOM OPTIONS M96_COMMON ALTERNATE,COMMON,M96_COMMON1,M96_COMMON2,M96_COMMON3 M96_COMMON1 MCP_B02,BOOTROM_DEVEL,SMC_PRGRM,BOOT_MODE_USER,JTAG_ALLDEV,MEMRESET_HW,MEMRESET_MCP,VREFMRGN M96_COMMON2 LPCPLUS,XDP,XDP_CONN M96_COMMON3 MCP_CS1_NO M96_HYNIX DRAM_HYNIX M96_MICRON DRAM_MICRON,DRAM_SPD_2 TABLE_BOMGROUP_ITEM 630-9734 PCBA,MLB,1.6GHZ,HY 2GB,SS CAP,M96 EEE_4DA,M96_COMMON,M96_HYNIX,M96_SS_CAP,CPU_1_6GHZ TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM 630-9735 PCBA,MLB,1.6GHZ,HY 2GB,MU CAP,M96 EEE_4DB,M96_COMMON,M96_HYNIX,M96_MU_CAP,CPU_1_6GHZ TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM 630-9514 PCBA,MLB,1.6GHZ,HY 2GB,TY CAP,M96 EEE_2AL,M96_COMMON,M96_HYNIX,M96_TY_CAP,CPU_1_6GHZ TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM 630-9738 PCBA,MLB,1.8GHZ,HY 2GB,SS CAP,M96 EEE_4DC,M96_COMMON,M96_HYNIX,M96_SS_CAP,CPU_1_8GHZ 630-9516 PCBA,MLB,1.8GHZ,HY 2GB,MU CAP,M96 EEE_2AN,M96_COMMON,M96_HYNIX,M96_MU_CAP,CPU_1_8GHZ TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM D TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM 630-9517 PCBA,MLB,1.8GHZ,HY 2GB,TY CAP,M96 EEE_2AP,M96_COMMON,M96_HYNIX,M96_TY_CAP,CPU_1_8GHZ D TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM M96_SS_CAP SS_CAP_2_2UF,SS_CAP_10UF,SS_CAP_1UF M96_MU_CAP MU_CAP_2_2UF,MU_CAP_10UF,MU_CAP_1UF M96_TY_CAP TY_CAP_2_2UF,TY_CAP_10UF,TY_CAP_1UF TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM Module Parts PART NUMBER Bar Code Label / EEE #’s PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION 826-4393 LBL,P/N LABEL,PCB,28MM X MM [EEE:4DA] CRITICAL EEE_4DA 826-4393 LBL,P/N LABEL,PCB,28MM X MM [EEE:4DB] CRITICAL EEE_4DB 826-4393 LBL,P/N LABEL,PCB,28MM X MM [EEE:2AL] CRITICAL EEE_2AL 826-4393 LBL,P/N LABEL,PCB,28MM X MM [EEE:4DC] CRITICAL EEE_4DC 826-4393 LBL,P/N LABEL,PCB,28MM X MM [EEE:2AN] CRITICAL EEE_2AN 826-4393 LBL,P/N LABEL,PCB,28MM X MM [EEE:2AP] CRITICAL EEE_2AP C QTY DESCRIPTION REFERENCE DES CRITICAL 337S3658 IC,PDC,QS,1.60GHZ,17W,1066,6M U1000 CRITICAL BOM OPTION CPU_1_6GHZ 337S3659 IC,PDC,QS,1.80GHZ,17W,1066,6M U1000 CRITICAL CPU_1_8GHZ 338S0604 IC,GMCP,MCP79U-A01Q,27MMX27MM,BGA1588 U1400 CRITICAL MCP_A01Q 338S0601 IC,GMCP,MCP79U-B01,27MMX27MM,BGA1588 U1400 CRITICAL MCP_B01 338S0637 IC,GMCP,MCP79U-B02,27MMX27MM,BGA1588 U1400 CRITICAL MCP_B02 335S0615 IC, 32MBIT 8-PIN SERIAL FLASH, WSON8 U6100 CRITICAL BOOTROM_BLANK_4MB 341S2382 IC,EFI,BOOTROM DEVELOPMENT (UNLOCKED),M96 U6100 CRITICAL BOOTROM_DEVEL 341S2326 IC,EFI,BOOTROM FINAL (LOCKED),M96 U6100 CRITICAL BOOTROM_FINAL 338S0563 IC,SMC,HS8/2117 U4900 CRITICAL SMC_BLANK 341S2327 IC,PRGRM,SMC (NEW),M96 U4900 CRITICAL SMC_PRGRM 333S0476 HYNIX,DDR3,128M16,9x11.5 U3100,U3110,U3120,U3130 CRITICAL DRAM_HYNIX 333S0476 HYNIX,DDR3,128M16,9x11.5 U3200,U3210,U3220,U3230 CRITICAL DRAM_HYNIX 333S0476 HYNIX,DDR3,128M16,9x11.5 U3300,U3310,U3320,U3330 CRITICAL DRAM_HYNIX 333S0476 HYNIX,DDR3,128M16,9x11.5 U3400,U3410,U3420,U3430 CRITICAL DRAM_HYNIX 333S0475 MICRON,DDR3,128M16,9x11.5 U3100,U3110,U3120,U3130 CRITICAL DRAM_MICRON 333S0475 MICRON,DDR3,128M16,9x11.5 U3200,U3210,U3220,U3230 CRITICAL DRAM_MICRON 333S0475 MICRON,DDR3,128M16,9x11.5 U3300,U3310,U3320,U3330 CRITICAL DRAM_MICRON 333S0475 MICRON,DDR3,128M16,9x11.5 U3400,U3410,U3420,U3430 CRITICAL DRAM_MICRON 353S1938 IC,ISL6258,REV2,BAT CHGR, 28P QFN U7900 CRITICAL C B B Alternate Parts 128S0093 ALTERNATE FOR PART NUMBER 128S0092 376S0466 740S0067 PART NUMBER A REFERENCE DESIGNATOR(S) DESCRIPTION ALL 33UF 20% 16V DCASE 376S0410 ALL Si4413 for Si4405 740S0028 ALL 0.5A OC FUSE 104S0023 104S0018 ALL 1206 1/4W 002 OHM 152S0684 152S0421 ALL 1.0UH,22A,10MOHM 376S0627 376S0723 ALL POWER NFET, 30V, 18A 152S0905 152S0861 ALL IND,IHLP4040CZ,0.68uH,18A BOM OPTION CONFIGURATION OPTIONS SYNC_MASTER=(N/A) SYNC_DATE=(N/A) NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC SCALE SHT NONE REV 051-7631 2.3.0 OF 71 A 1UF 0402 CAPACITOR VENDOR TABLES FOR ACOUSTICS SAMSUNG PART NUMBER D MURATA QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION 138S0629 CAP, 1UF, 6.3V, 10%, 0402 C7947,C7360,C2504,C2505 CRITICAL SS_CAP_1UF 138S0629 CAP, 1UF, 6.3V, 10%, 0402 C2506,C2507,C2516,C2517,C7100,C7101,C7103 CRITICAL 138S0629 CAP, 1UF, 6.3V, 10%, 0402 C2860,C7296,C7297,C7492,C7500,C7940,C7941,C9760,C7603 CRITICAL PART NUMBER TAIYO YUDEN QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION QTY DESCRIPTION 138S0628 CAP, 1UF, 6.3V, 10%, 0402 C7947,C7360,C2504,C2505 CRITICAL MU_CAP_1UF PART NUMBER 138S0630 CAP, 1UF, 6.3V, 10%, 0402 REFERENCE DES C7947,C7360,C2504,C2505 CRITICAL CRITICAL BOM OPTION TY_CAP_1UF SS_CAP_1UF 138S0628 CAP, 1UF, 6.3V, 10%, 0402 C2506,C2507,C2516,C2517,C7100,C7101,C7103 CRITICAL MU_CAP_1UF 138S0630 CAP, 1UF, 6.3V, 10%, 0402 C2506,C2507,C2516,C2517,C7100,C7101,C7103 CRITICAL TY_CAP_1UF SS_CAP_1UF 138S0628 CAP, 1UF, 6.3V, 10%, 0402 C2860,C7296,C7297,C7492,C7500,C7940,C7941,C9760,C7603 CRITICAL MU_CAP_1UF 138S0630 CAP, 1UF, 6.3V, 10%, 0402 C2860,C7296,C7297,C7492,C7500,C7940,C7941,C9760,C7603 CRITICAL TY_CAP_1UF D 2.2UF 0402 CAPACITOR VENDOR TABLES FOR ACOUSTICS SAMSUNG PART NUMBER C B MURATA QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION 138S0632 10 CAP, 2.2UF, 6.3V, 20%, 0402 C1240,C1241,C1242,C1243,C1244,C1245,C1246,C1247,C1248,C1249 CRITICAL SS_CAP_2_2UF 138S0632 10 CAP, 2.2UF, 6.3V, 20%, 0402 C1250,C1251,C1252,C1253,C1254,C1255,C1256,C1257,C1258,C1259 CRITICAL 138S0632 CAP, 2.2UF, 6.3V, 20%, 0402 C1260,C1261,C1262,C1263,C1264,C1265,C1266,C1267 CRITICAL 138S0632 10 CAP, 2.2UF, 6.3V, 20%, 0402 C9900,C9901,C9902,C9903,C9904,C9905,C9906,C9907,C9908,C9909 138S0632 10 CAP, 2.2UF, 6.3V, 20%, 0402 138S0632 10 CAP, 2.2UF, 6.3V, 20%, 0402 138S0632 10 138S0632 PART NUMBER TAIYO YUDEN QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION QTY DESCRIPTION 138S0633 10 CAP, 2.2UF, 6.3V, 20%, 0402 C1240,C1241,C1242,C1243,C1244,C1245,C1246,C1247,C1248,C1249 CRITICAL MU_CAP_2_2UF PART NUMBER 138S0634 10 CAP, 2.2UF, 6.3V, 20%, 0402 C1240,C1241,C1242,C1243,C1244,C1245,C1246,C1247,C1248,C1249 REFERENCE DES CRITICAL CRITICAL TY_CAP_2_2UF BOM OPTION SS_CAP_2_2UF 138S0633 10 CAP, 2.2UF, 6.3V, 20%, 0402 C1250,C1251,C1252,C1253,C1254,C1255,C1256,C1257,C1258,C1259 CRITICAL MU_CAP_2_2UF 138S0634 10 CAP, 2.2UF, 6.3V, 20%, 0402 C1250,C1251,C1252,C1253,C1254,C1255,C1256,C1257,C1258,C1259 CRITICAL TY_CAP_2_2UF SS_CAP_2_2UF 138S0633 CAP, 2.2UF, 6.3V, 20%, 0402 C1260,C1261,C1262,C1263,C1264,C1265,C1266,C1267 CRITICAL MU_CAP_2_2UF 138S0634 CAP, 2.2UF, 6.3V, 20%, 0402 C1260,C1261,C1262,C1263,C1264,C1265,C1266,C1267 CRITICAL TY_CAP_2_2UF CRITICAL SS_CAP_2_2UF 138S0633 10 CAP, 2.2UF, 6.3V, 20%, 0402 C9900,C9901,C9902,C9903,C9904,C9905,C9906,C9907,C9908,C9909 CRITICAL MU_CAP_2_2UF 138S0634 10 CAP, 2.2UF, 6.3V, 20%, 0402 C9900,C9901,C9902,C9903,C9904,C9905,C9906,C9907,C9908,C9909 CRITICAL TY_CAP_2_2UF C9910,C9911,C9912,C9913,C9914,C9915,C9916,C9917,C9918,C9919 CRITICAL SS_CAP_2_2UF 138S0633 10 CAP, 2.2UF, 6.3V, 20%, 0402 C9910,C9911,C9912,C9913,C9914,C9915,C9916,C9917,C9918,C9919 CRITICAL MU_CAP_2_2UF 138S0634 10 CAP, 2.2UF, 6.3V, 20%, 0402 C9910,C9911,C9912,C9913,C9914,C9915,C9916,C9917,C9918,C9919 CRITICAL TY_CAP_2_2UF C9920,C9921,C9922,C9923,C9924,C9925,C9926,C9927,C9928,C9929 CRITICAL SS_CAP_2_2UF 138S0633 10 CAP, 2.2UF, 6.3V, 20%, 0402 C9920,C9921,C9922,C9923,C9924,C9925,C9926,C9927,C9928,C9929 CRITICAL MU_CAP_2_2UF 138S0634 10 CAP, 2.2UF, 6.3V, 20%, 0402 C9920,C9921,C9922,C9923,C9924,C9925,C9926,C9927,C9928,C9929 CRITICAL TY_CAP_2_2UF CAP, 2.2UF, 6.3V, 20%, 0402 C9930,C9931,C9932,C9933,C9934,C9935,C9936,C9937,C9938,C9939 CRITICAL SS_CAP_2_2UF 138S0633 10 CAP, 2.2UF, 6.3V, 20%, 0402 C9930,C9931,C9932,C9933,C9934,C9935,C9936,C9937,C9938,C9939 CRITICAL MU_CAP_2_2UF 138S0634 10 CAP, 2.2UF, 6.3V, 20%, 0402 C9930,C9931,C9932,C9933,C9934,C9935,C9936,C9937,C9938,C9939 CRITICAL TY_CAP_2_2UF 12 CAP, 2.2UF, 6.3V, 20%, 0402 C1283,C1284,C1285,C1286,C1287,C1288,C1291,C1292,C1293,C1294,C1295,C1296 CRITICAL SS_CAP_2_2UF 138S0633 12 CAP, 2.2UF, 6.3V, 20%, 0402 C1283,C1284,C1285,C1286,C1287,C1288,C1291,C1292,C1293,C1294,C1295,C1296 CRITICAL MU_CAP_2_2UF 138S0634 12 CAP, 2.2UF, 6.3V, 20%, 0402 C1283,C1284,C1285,C1286,C1287,C1288,C1291,C1292,C1293,C1294,C1295,C1296 CRITICAL TY_CAP_2_2UF 138S0632 10 CAP, 2.2UF, 6.3V, 20%, 0402 C3500,C3501,C3504,C3505,C3510,C3511,C3512,C3514,C3515,C3516 CRITICAL SS_CAP_2_2UF 138S0633 10 CAP, 2.2UF, 6.3V, 20%, 0402 C3500,C3501,C3504,C3505,C3510,C3511,C3512,C3514,C3515,C3516 CRITICAL MU_CAP_2_2UF 138S0634 10 CAP, 2.2UF, 6.3V, 20%, 0402 C3500,C3501,C3504,C3505,C3510,C3511,C3512,C3514,C3515,C3516 CRITICAL TY_CAP_2_2UF 138S0632 10 CAP, 2.2UF, 6.3V, 20%, 0402 C3520,C3521,C3524,C3525,C3530,C3531,C3534,C3535,C3540,C3541 CRITICAL SS_CAP_2_2UF 138S0633 10 CAP, 2.2UF, 6.3V, 20%, 0402 C3520,C3521,C3524,C3525,C3530,C3531,C3534,C3535,C3540,C3541 CRITICAL MU_CAP_2_2UF 138S0634 10 CAP, 2.2UF, 6.3V, 20%, 0402 C3520,C3521,C3524,C3525,C3530,C3531,C3534,C3535,C3540,C3541 CRITICAL TY_CAP_2_2UF 138S0632 CAP, 2.2UF, 6.3V, 20%, 0402 C3542,C3544,C3545,C3546,C3550,C3551,C3554,C3555 CRITICAL SS_CAP_2_2UF 138S0633 CAP, 2.2UF, 6.3V, 20%, 0402 C3542,C3544,C3545,C3546,C3550,C3551,C3554,C3555 CRITICAL MU_CAP_2_2UF 138S0634 CAP, 2.2UF, 6.3V, 20%, 0402 C3542,C3544,C3545,C3546,C3550,C3551,C3554,C3555 CRITICAL TY_CAP_2_2UF 138S0632 10 CAP, 2.2UF, 6.3V, 20%, 0402 C3600,C3601,C3604,C3605,C3610,C3611,C3612,C3614,C3615,C3616 CRITICAL SS_CAP_2_2UF 138S0633 10 CAP, 2.2UF, 6.3V, 20%, 0402 C3600,C3601,C3604,C3605,C3610,C3611,C3612,C3614,C3615,C3616 CRITICAL MU_CAP_2_2UF 138S0634 10 CAP, 2.2UF, 6.3V, 20%, 0402 C3600,C3601,C3604,C3605,C3610,C3611,C3612,C3614,C3615,C3616 CRITICAL TY_CAP_2_2UF 138S0632 10 CAP, 2.2UF, 6.3V, 20%, 0402 C3620,C3621,C3624,C3625,C3630,C3631,C3634,C3635,C3640,C3641 CRITICAL SS_CAP_2_2UF 138S0633 10 CAP, 2.2UF, 6.3V, 20%, 0402 C3620,C3621,C3624,C3625,C3630,C3631,C3634,C3635,C3640,C3641 CRITICAL MU_CAP_2_2UF 138S0634 10 CAP, 2.2UF, 6.3V, 20%, 0402 C3620,C3621,C3624,C3625,C3630,C3631,C3634,C3635,C3640,C3641 CRITICAL TY_CAP_2_2UF 138S0632 CAP, 2.2UF, 6.3V, 20%, 0402 C3642,C3644,C3645,C3646,C3650,C3651,C3654,C3655 CRITICAL SS_CAP_2_2UF 138S0633 CAP, 2.2UF, 6.3V, 20%, 0402 C3642,C3644,C3645,C3646,C3650,C3651,C3654,C3655 CRITICAL MU_CAP_2_2UF 138S0634 CAP, 2.2UF, 6.3V, 20%, 0402 C3642,C3644,C3645,C3646,C3650,C3651,C3654,C3655 CRITICAL TY_CAP_2_2UF 138S0632 CAP, 2.2UF, 6.3V, 20%, 0402 C2530,C2531,C2532,C2533,C2534,C2535,C2536 CRITICAL SS_CAP_2_2UF 138S0633 CAP, 2.2UF, 6.3V, 20%, 0402 C2530,C2531,C2532,C2533,C2534,C2535,C2536 CRITICAL MU_CAP_2_2UF 138S0634 CAP, 2.2UF, 6.3V, 20%, 0402 C2530,C2531,C2532,C2533,C2534,C2535,C2536 CRITICAL TY_CAP_2_2UF 138S0632 CAP, 2.2UF, 6.3V, 20%, 0402 C2550,C2551,C2552,C2553,C2555,C2560,C2562,C2564 CRITICAL SS_CAP_2_2UF 138S0633 CAP, 2.2UF, 6.3V, 20%, 0402 C2550,C2551,C2552,C2553,C2555,C2560,C2562,C2564 CRITICAL MU_CAP_2_2UF 138S0634 CAP, 2.2UF, 6.3V, 20%, 0402 C2550,C2551,C2552,C2553,C2555,C2560,C2562,C2564 CRITICAL TY_CAP_2_2UF 138S0632 CAP, 2.2UF, 6.3V, 20%, 0402 C2570,C2571,C2572,C2573,C2574,C2575,C2576,C2610 CRITICAL SS_CAP_2_2UF 138S0633 CAP, 2.2UF, 6.3V, 20%, 0402 C2570,C2571,C2572,C2573,C2574,C2575,C2576,C2610 CRITICAL MU_CAP_2_2UF 138S0634 CAP, 2.2UF, 6.3V, 20%, 0402 C2570,C2571,C2572,C2573,C2574,C2575,C2576,C2610 CRITICAL TY_CAP_2_2UF 138S0632 CAP, 2.2UF, 6.3V, 20%, 0402 C4800,C7362,C7511 CRITICAL SS_CAP_2_2UF 138S0633 CAP, 2.2UF, 6.3V, 20%, 0402 C4800,C7362,C7511 CRITICAL MU_CAP_2_2UF 138S0634 CAP, 2.2UF, 6.3V, 20%, 0402 C4800,C7362,C7511 CRITICAL TY_CAP_2_2UF 10UF 0603 CAPACITOR VENDOR TABLES FOR ACOUSTICS SAMSUNG PART NUMBER B MURATA REFERENCE DES CRITICAL BOM OPTION PART NUMBER C TAIYO YUDEN QTY DESCRIPTION QTY DESCRIPTION QTY DESCRIPTION 138S0626 10 CAP, 10UF, 6.3V, 20%, 0603 C1200,C1201,C1202,C1203,C1204,C1205,C1206,C1207,C1208,C1209 CRITICAL SS_CAP_10UF 138S0625 10 CAP, 10UF, 6.3V, 20%, 0603 C1200,C1201,C1202,C1203,C1204,C1205,C1206,C1207,C1208,C1209 REFERENCE DES CRITICAL CRITICAL BOM OPTION MU_CAP_10UF PART NUMBER 138S0627 10 CAP, 10UF, 6.3V, 20%, 0603 C1200,C1201,C1202,C1203,C1204,C1205,C1206,C1207,C1208,C1209 REFERENCE DES CRITICAL CRITICAL BOM OPTION TY_CAP_10UF 138S0626 10 CAP, 10UF, 6.3V, 20%, 0603 C1210,C1211,C1212,C1213,C1214,C1215,C1216,C1217,C1218,C1219 CRITICAL SS_CAP_10UF 138S0625 10 CAP, 10UF, 6.3V, 20%, 0603 C1210,C1211,C1212,C1213,C1214,C1215,C1216,C1217,C1218,C1219 CRITICAL MU_CAP_10UF 138S0627 10 CAP, 10UF, 6.3V, 20%, 0603 C1210,C1211,C1212,C1213,C1214,C1215,C1216,C1217,C1218,C1219 CRITICAL TY_CAP_10UF 138S0626 10 CAP, 10UF, 6.3V, 20%, 0603 C1220,C1221,C1222,C1223,C1224,C1225,C1226,C1227,C1228,C1229 CRITICAL SS_CAP_10UF 138S0625 10 CAP, 10UF, 6.3V, 20%, 0603 C1220,C1221,C1222,C1223,C1224,C1225,C1226,C1227,C1228,C1229 CRITICAL MU_CAP_10UF 138S0627 10 CAP, 10UF, 6.3V, 20%, 0603 C1220,C1221,C1222,C1223,C1224,C1225,C1226,C1227,C1228,C1229 CRITICAL TY_CAP_10UF 138S0626 CAP, 10UF, 6.3V, 20%, 0603 C1230,C1231,C1280 CRITICAL SS_CAP_10UF 138S0625 CAP, 10UF, 6.3V, 20%, 0603 C1230,C1231,C1280 CRITICAL MU_CAP_10UF 138S0627 CAP, 10UF, 6.3V, 20%, 0603 C1230,C1231,C1280 CRITICAL TY_CAP_10UF 138S0626 CAP, 10UF, 6.3V, 20%, 0603 C4109,C4613,C5066,C7502,C7541,C7650,C7690,C9012 CRITICAL SS_CAP_10UF 138S0625 CAP, 10UF, 6.3V, 20%, 0603 C4109,C4613,C5066,C7502,C7541,C7650,C7690,C9012 CRITICAL MU_CAP_10UF 138S0627 CAP, 10UF, 6.3V, 20%, 0603 C4109,C4613,C5066,C7502,C7541,C7650,C7690,C9012 CRITICAL TY_CAP_10UF 138S0626 CAP, 10UF, 6.3V, 20%, 0603 C7266,C7267,C7269,C7401,C7605 CRITICAL SS_CAP_10UF 138S0625 CAP, 10UF, 6.3V, 20%, 0603 C7266,C7267,C7269,C7401,C7605 CRITICAL MU_CAP_10UF 138S0627 CAP, 10UF, 6.3V, 20%, 0603 C7266,C7267,C7269,C7401,C7605 CRITICAL TY_CAP_10UF Acoustic Cap BOM Config Tables A SYNC_MASTER=N/A SYNC_DATE=N/A NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC SCALE SHT NONE REV 051-7631 2.3.0 OF 71 A Functional Test Points NB NO_TESTS These are normally testpoints but become NC FUNC TEST - XDP/ITP CONNECTOR NO_TEST x2 x2 I647 I649 I638 I640 D I639 FUNC TEST - M93 WIRELESS CONNECTOR FUNC TEST - BATTERY CONNECTOR BATT_POS TRUE GND TRUE SMC_BS_ALRT_L TRUE SMBUS_SMC_BSA_SCL TRUE SMBUS_SMC_BSA_SDA TRUE I470 I475 39 40 49 I479 42 69 I478 42 69 I476 I480 I648 I650 x6 I706 I668 I667 I669 I714 FUNC TEST - Power Supplies I595 49 I477 x6 FUNC TEST - DC-IN CONNECTOR PP18V5_DCIN TRUE ADAPTER_SENSE TRUE GND TRUE I483 49 70 I484 49 I482 I499 I500 FUNC TEST - FAN CONNECTOR =PP5V_S0_FAN TRUE FAN_RT_PWM TRUE FAN_RT_TACH TRUE GND TRUE I501 46 I502 46 I503 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE AIRPORT_RST_L PCIE_WAKE_L CK505_SRC_CLKREQ6_L PCIE_CLK100M_MINI_N_F PCIE_CLK100M_MINI_P_F PCIE_E_D2R_N_F PCIE_E_D2R_P_F PCIE_E_R2D_C_N_F PCIE_E_R2D_C_P_F AIRPORT_RST_L =SMB_AIRPORT_DATA =SMB_AIRPORT_CLK PCIE_E_R2D_C_N_F PCIE_E_R2D_C_P_F PP3V3_S3_AP_AUX 24 34 I92 16 34 I454 I455 34 I457 34 I460 34 I459 34 I458 34 I461 34 I466 24 34 I463 34 42 I462 34 42 I467 34 I469 34 I474 34 70 I473 PPVCORE_S0_CPU PP0V75_S0 PP1V05_S0 PP1V5_S0 PP1V5_S3 PP1V05_S5 PPMCPCORE_S0 PP5V_S0 PP3V3_S0 PP3V3_S3 PP5V_S3 PP3V3_S5 PP3V42_G3H PP18V5_G3H PPDCIN_G3H PPBUS_G3H PPBUS_R_G3H PP1V8_S0 46 I472 I471 I741 I742 I743 I744 I745 I746 FUNC TEST - AIRPORT CK505_SRC_CLKREQ6_L TRUE PCIE_WAKE_L TRUE AIRPORT_RST_L TRUE =SMB_AIRPORT_CLK TRUE =SMB_AIRPORT_DATA TRUE GND TRUE I757 I748 I749 I750 C 16 34 24 34 I751 34 42 I752 34 42 I753 I755 FUNC TEST - MIC PP3V3_S0_MIC_F TRUE AUD_MIC_DATA_F TRUE AUD_MIC_CLK_F TRUE GND_MIC_F TRUE I756 I646 I735 I736 I737 I738 I740 I739 70 I681 70 I683 70 I682 70 I684 70 I685 70 I687 70 I686 70 I688 70 I689 70 I691 70 I690 70 I692 70 I694 70 I695 70 I696 70 I697 70 I698 FUNC TEST - SATA HDD PP3V3_S0_HDD_F TRUE SATA_HDD_R2D_N TRUE SATA_HDD_R2D_P TRUE SATA_HDD_D2R_C_N TRUE SATA_HDD_D2R_C_P TRUE GND TRUE I701 I700 36 70 I702 36 67 I703 36 67 I704 36 67 I705 59 59 I716 59 I717 I718 HDA_SYNC HDA_BIT_CLK AUD_MIC_DATA HDA_SDOUT =PPVIN_S0_AUDIO HDA_SDIN0 AUD_MIC_CLK PM_SLP_S3_L 20 35 68 I720 20 35 68 I721 35 59 I722 20 35 68 I723 35 I725 20 35 68 I726 35 59 I727 20 34 35 39 56 I728 FUNC TEST - RIO HATCH CONNECTOR DP_ML_C_N TRUE DP_ML_C_P TRUE DP_AUX_CH_C_N TRUE DP_AUX_CH_C_P TRUE DP_CA_DET_Q TRUE HDMI_CEC TRUE DP_HPD_Q TRUE PP3V3_S0_DPPWR TRUE USB2_EXTA_F_P TRUE USB2_EXTA_F_N TRUE PP5V_S3_USB2_EXTA_F TRUE GND TRUE 61 67 35 60 61 67 x2 I654 35 60 61 67 I655 35 61 I656 35 61 I657 35 61 I658 35 61 70 I659 35 37 I660 35 37 I661 35 37 70 I662 I663 I665 I508 I509 I510 I512 I511 I513 Power Supply NO_TESTs I514 I515 NO_TEST I517 I516 B I518 I520 I519 I521 I676 I734 12 65 12 12 12 12 12 D 12 12 12 12 20 42 68 12 20 42 68 12 65 12 12 20 12 18 68 12 20 12 20 12 13 65 12 13 65 12 65 12 24 12 12 65 12 65 12 65 12 10 11 12 61 67 x2 I506 XDP_BPM_L TP_XDP_OBSFN_B0 TP_XDP_OBSFN_B1 TP_XDP_OBSDATA_B0 TP_XDP_OBSDATA_B1 TP_XDP_OBSDATA_B2 TP_XDP_OBSDATA_B3 XDP_PWRGD XDP_OBS20 SMBUS_MCP_0_DATA SMBUS_MCP_0_CLK XDP_TCK JTAG_MCP_TDO_CONN JTAG_MCP_TRST_L MCP_DEBUG JTAG_MCP_TDI JTAG_MCP_TMS FSB_CLK_ITP_P FSB_CLK_ITP_N XDP_CPURST_L XDP_DBRESET_L XDP_TDO_CONN XDP_TRST_L XDP_TDI XDP_TMS =PP3V3_S0_XDP =PP1V05_S0_CPU 36 67 I664 I507 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE 59 70 I719 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE I680 I699 FUNC TEST - AUDIO CONNECTOR I645 70 I754 I747 I593 I666 I711 FUNC TEST - IPD CONNECTOR SMC_LID TRUE PP3V42_G3H_IPD_F TRUE SMC_SYS_KBDLED TRUE SMC_SYS_LED TRUE =USB2_TPAD_N TRUE =USB2_TPAD_P TRUE SMC_ONOFF_L TRUE =USB2_IR_N TRUE =USB2_IR_P TRUE PP5V_S0_KBDLED_F TRUE PP5V_S3_TOPCASE_F TRUE =I2C_TPAD_SCL TRUE =I2C_TPAD_SDA TRUE SMC_ONOFF_L TRUE =USB2_IR_N TRUE =USB2_IR_P TRUE PP5V_S0_KBDLED_F TRUE LSOC_PRESS_H_R TRUE I712 38 39 40 x10I713 FUNC TEST - CAMERA USB, LVDS, ALS PP5V_S3_CAMERA_F TRUE USB2_CAMERA_F_P TRUE USB2_CAMERA_F_N TRUE LCDBKLT_RTN TRUE LVDS_IG_A_DATA_N TRUE LVDS_IG_A_DATA_P TRUE PPVOUT_S0_LCDBKLT TRUE LVDS_IG_A_CLK_F_N TRUE LVDS_IG_A_CLK_F_P TRUE LVDS_IG_DDC_CLK TRUE LVDS_IG_DDC_DATA TRUE PP3V3_S0_LCD_F TRUE PP3V3_LCDVDD_SW_F TRUE =I2C_ALS_SDA TRUE =I2C_ALS_SCL TRUE GND TRUE 59 70 59 C 59 59 62 17 59 67 17 59 67 59 62 70 59 67 59 67 17 59 17 59 59 70 59 70 42 59 42 59 38 70 38 39 38 39 38 38 38 39 40 38 38 38 70 38 70 38 42 B 38 42 38 39 40 38 38 38 70 38 CLOCK NO_TESTS NO_TEST x13I522 REQUIRED NETS LVDS NO_TESTS TRUE GND NICE2HAVE NETS NO_TEST Functional Test and No-Tests A A NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC SCALE SHT NONE REV 051-7631 2.3.0 OF 71 "S0" RAILS 50 =PPVCORE_S0_CPU_REG 27 A PPVCORE_S0_CPU =PPVCORE_S0_CPU D 51 =PPMCPCORE_S0_REG 11.551 A PPMCPCORE_S0 MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=0.9V MAKE_BASE=TRUE =PPVCORE_S0_MCP =PPVCORE_S0_MCP_VSENSE 54 =PP0V75_S0_REG 1.075 A PP0V75_S0 MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0.75V MAKE_BASE=TRUE =PPVTT_S0_VTTCLAMP =PP0V75_S0_MEM_VTT_A =PP0V75_S0_MEM_VTT_B 57 =PP1V05_S0_FET 7.047 A PP1V05_S0 70 54 =PP0V75_S3_VTTREF =PPVTT_S3_DDR_BUF 10 11 64 70 54 =PP1V5_S3_REG PP1V5_S3 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.8V MAKE_BASE=TRUE 12.984 A 21 22 =PP1V5_S3_MEM_A =PP1V5_S3_MEM_B =PP1V5_S3_P1V5S0FET =PP1V5_S3_MEMRESET 43 70 57 =PP3V3_S3_FET PP3V3_S3 MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V MAKE_BASE=TRUE 57 315 mA 33 70 MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V MAKE_BASE=TRUE =PP5V_S3_REG 5.027 A PP1V5_S0 MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.5V MAKE_BASE=TRUE MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5V MAKE_BASE=TRUE 52 =PP1V8_S0_REG 19 mA PP1V8_S0 11 15 22 66 =PP3V3_S0_FET PP3V3_S0 MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V MAKE_BASE=TRUE 2.046 A B 49 24 =PP3V42_G3H_REG PP3V42_G3H =PP1V05_S5_MCP_VDD_AUXC 21 22 =PP1V05_S5_P1V05S0FET 57 =PP1V05_RMGT_P1V05RMGTFET 57 25 =PP3V42_G3H_SMC =PP3V42_G3H_SMCVREF =PP3V42_G3H_SMBUS_SMC_BSA =PP3V42_G3H_IPD =PP3V42_G3H_SMCUSBMUX =PP3V42_G3H_CHGR =PP3V42_G3H_LPCPLUS 70 55 =PP3V3_S5_REG PP3V3_S5 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V MAKE_BASE=TRUE 27 28 31 33 29 30 32 33 4.011 A 57 70 =PP3V3_S5_AIRPORT_AUX 34 =PP3V3_S5_LCD 59 =PP3V3_S5_MCP 21 22 =PP3V3_S5_MCPPWRGD 24 =PP3V3_S5_MCP_GPIO 17 19 20 =PP3V3_S5_P1V05FET 57 =PP3V3_S5_P3V3S0FET 57 =PP3V3_S5_P3V3S3FET 57 =PP3V3_S5_PWRCTL 56 =PP3V3_S5_ROM 41 48 =PP3V3_S5_SMBUS_MCP_1 42 =PP3V3_S5_MEMRESET 26 =PP3V3_S5_P3V3RMGTFET 57 =PP3V3_S5_P1V05RMGTFET 57 26 70 42 42 58 49 =PP18V5_G3H_CHGR =PP3V3_S0_DPCONN 61 =PP3V3_S0_FAN 46 =PP3V3_S0_IMVP 50 =PP3V3_S0_LCD 59 =PP3V3_S0_LCDBKLT 62 =PP3V3_S0_MCP 20 21 22 =PP3V3_S0_MCP_GPIO 17 18 20 =PP3V3_S0_MCP_PLL_UF 22 =PP3V3_S0_MCP_VPLL_UF 23 =PP3V3_S0_PWRCTL 24 56 =PP3V3_S0_SMBUS_SMC_0_S0 =PP3V3_S0_THRM_SNR 45 =PP3V3_S0_VMON 56 =PP3V3_S0_XDP 12 =PPVIN_S0_P1V8S0 52 =PP3V3_S0_LPCPLUS 41 =PP3V3_S0_HDD 36 =PP3V3_S0_SMBUS_SMC_B_S0 =PP3V3_S0_SMBUS_MCP_0 42 =PP3V3R1V5_S0_MCP_HDA 20 22 =PP3V3_S0_SMC_LS 40 =PP3V3_S0_MIC 59 39 40 40 D 42 38 37 58 41 PP18V5_G3H 70 MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=18.5V MAKE_BASE=TRUE 49 =PPDCIN_G3H PPDCIN_G3H 70 MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.25MM VOLTAGE=18.5V MAKE_BASE=TRUE =PPVIN_G3H_P3V42G3H 58 44 =PPBUSA_G3H 49 PPBUS_R_G3H 70 MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.25MM VOLTAGE=12.6V MAKE_BASE=TRUE 50 54 51 53 70 C 58 44 =PPBUSB_G3H PPBUS_G3H 70 MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.6V MAKE_BASE=TRUE 6.207 A =PPVIN_S3_5VS3 =PPVIN_S5_3V3S5 =PPVIN_S0_AUDIO =PPVIN_G3H_DCIN =PPBUS_S0_LCDBKLT =PPBUS_G3HRS5 70 70 70 MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.42V MAKE_BASE=TRUE 165 mA MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.8V MAKE_BASE=TRUE =PP3V3R1V8_S0_MCP_IFP_VDD 57 70 =PP5V_S3_CAMERA 59 =PP5V_S3_MCPDDRFET 57 =PP5V_S3_P1V05S0FET 57 =PP5V_S3_TOPCASE 38 =PP5V_S3_VTTCLAMP 57 =PP5V_S3_1V5S30V75S0 54 =PP5V_S3_EXTUSB 37 =PP5V_S3_P5VS0FET 57 =PP5V_S3_MCPREG 51 70 =PP1V5_S0_CPU 10 =PP1V5_S0_VMON 56 =PP1V8R1V5_S0_MCP_MEM PP1V05_S5 MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V MAKE_BASE=TRUE 7.368 A =PPVIN_S5_CPU_IMVP =PPVIN_S5_1V5S30V75S0 =PPVIN_S0_MCPCORES0 =PPVIN_S5_1V05 PP5V_S3 3.134 A =PP1V5_S0_FET =PP1V05_S5_REG 13 A 55 C 53 70 =PP3V3_S3_BT 34 =PP3V3_S3_SMBUS_SMC_A_S3 =PP3V3_S3_SMC 40 =PP3V3_S3_SMS 47 =PP3V3_S3_VREFMRGN 25 =PP3V3_S3_SMBUS_SMC_MGMT =PP3V3_S3_DDRREG 54 =PP3V3_S3_MCPREG 51 =PP3V3_S3_MCP_GPIO 20 33 =PP1V05_S0_CPU 10 11 12 =PP1V05_S0_MCP_AVDD_UF 22 =PP1V05_S0_MCP_FSB 13 21 22 =PP1V05_S0_MCP_HDMI_VDD 17 23 =PP1V05_S0_MCP_PEX_DVDD 22 =PP1V05_S0_MCP_PLL_UF 22 =PP1V05_S0_MCP_SATA_DVDD 19 22 =PP1V05_S0_SMC_LS 40 =PP1V05_S0_VMON 56 57 PP0V75_S3 MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0.75V MAKE_BASE=TRUE 1.075 A "G3H" RAILS "S5" RAILS "S3" RAILS MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=0.9V MAKE_BASE=TRUE 55 55 35 49 63 43 "RMGT" RAILS 17 23 PP3V3_RMGT 57 =PP3V3_RMGT_FET 57 =PP1V05_RMGT_FET MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V MAKE_BASE=TRUE =PP3V3_ENET_MCP_RMGT PP1V05_RMGT 70 17 22 70 MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V MAKE_BASE=TRUE =PP1V05_ENET_MCP_RMGT 17 22 =PP1V05_ENET_MCP_PLL_MAC B 22 42 42 PEX & SATA AVDD/DVDD aliases A 70 22 57 =PP5V_S0_FET 562 mA =PP1V05_S0_MCP_PEX_AVDD0 =PP1V05_S0_MCP_PEX_AVDD1 PP1V05_S0_MCP_PEX_AVDD Power Aliases 16 206 mA (A01) 16 SYNC_MASTER=WFERRY MAKE_BASE=TRUE PP5V_S0 MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5V MAKE_BASE=TRUE =PP5V_S0_CPU_IMVP =PP5V_S0_DP_AUX_MUX =PP5V_S0_FAN =PP5V_S0_KBDLED =PP5V_S0_LPCPLUS 70 206 mA (A01) 22 50 =PP1V05_S0_MCP_PEX_DVDD0 =PP1V05_S0_MCP_PEX_DVDD1 =PP1V05_S0_MCP_PEX_DVDD SYNC_DATE=06/15/2006 NOTICE OF PROPRIETARY PROPERTY 16 57 mA (A01) 16 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING 57 mA (A01) 60 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE 46 II NOT TO REPRODUCE OR COPY IT 38 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART 41 SIZE DRAWING NUMBER D APPLE INC SCALE SHT NONE REV 051-7631 2.3.0 OF 71 A PCI-E ALIASES EMI SPRING CLIPS 16 =PEG_D2R_N CRITICAL =PEG_D2R_P NC_PEG_D2R_P 16 =PEG_R2D_C_N NC_PEG_R2D_C_N NO_TEST=TRUE 16 D Z0900 4.5OD2.0H-M1.6X0.35 Z0910 MAKE_BASE=TRUE NO_TEST=TRUE TP_PEG_PRSNT_L PEG_CLKREQ_L TP_PEG_CLKREQ_L PEG_CLK100M_P TP_PEG_CLK100M_P NC_MCP_CLK27M_XTALIN TP_PEG_CLK100M_N 16 EXTGPU_PWR_EN TP_EXTGPU_PWR_EN MAKE_BASE=TRUE CRT_IG_G_Y_Y NC_CRT_IG_G_Y_Y 17 CRT_IG_B_COMP_PB NC_CRT_IG_B_COMP_PB MAKE_BASE=TRUE 17 CRT_IG_HSYNC NC_CRT_IG_HSYNC 17 CRT_IG_VSYNC NC_CRT_IG_VSYNC 22 21 13 MAKE_BASE=TRUE NO STUFF LVDS ALIASES STDOFF-4.0OD2.4H-0.5-THNP HDA PULL-DOWN Z0912 LVDS_IG_A_DATA_P NC_LVDS_IG_A_DATA_P3 67 17 LVDS_IG_A_DATA_N NC_LVDS_IG_A_DATA_N3 18 NO_TEST=TRUE AUD_I2C_INT_L IS PU ON MCP PAGE 67 17 LVDS_IG_B_CLK_N NC_LVDS_IG_B_CLK_N 67 17 LVDS_IG_B_DATA_P NC_LVDS_IG_B_DATA_P NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE LVDS_IG_B_DATA_N MAKE_BASE=TRUE NC_LVDS_IG_B_DATA_N MAKE_BASE=TRUE 13 18 CPU_PECI_MCP FW_PME_L ODD_PWR_EN_L TP_CPU_PECI_MCP MAKE_BASE=TRUE TP_FW_PME_L MAKE_BASE=TRUE TP_ODD_PWR_EN_L 15 15 15 =DVI_HPD_GMUX_INT 15 20K 39 39 39 B 39 39 39 39 39 39 39 39 39 15 SATA ALIASES 5% 1/20W MF 201 NO_TEST 39 15 R0940 NO-CONNECT UNUSED SMC INTERFACE PORTS 39 15 UNUSED SATA ODD SIGNALS 19 19 19 19 SATA_ODD_R2D_C_P SATA_ODD_R2D_C_N SATA_ODD_D2R_P SATA_ODD_D2R_N 15 15 TP_SATA_ODD_R2D_C_P TP_SATA_ODD_R2D_C_N TP_SATA_ODD_D2R_P TP_SATA_ODD_D2R_N MAKE_BASE=TRUE 15 MAKE_BASE=TRUE 15 MAKE_BASE=TRUE 15 MAKE_BASE=TRUE 15 15 LAN ALIASES 15 15 UNUSED ETHERNET RG/MII INTERFACE 15 17 ENET_RXD 17 ENET_MDIO 17 ENET_CLK125M_RXCLK 17 ENET_RXD 17 ENET_RX_CTRL 17 ENET_INTR_L 17 ENET_RXD 17 ENET_CLK125M_TXCLK 17 ENET_RXD 17 MCP_MII_VREF 15 OUT 65 13 OUT 65 13 12 OUT 65 13 OUT 65 13 OUT 5% 1/20W MF 201 CPU_DPRSTP_L FSB_BREQ0_L FSB_CPURST_L CPU_INTR CPU_NMI NO_TEST TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE C UNUSED USB PORTS 68 68 RP0930 RP0931 RP0932 68 19 10K 10K 10K 68 19 5% 1/32W 4X0201-HF NC_MEM_A_CLK4P NC_MEM_A_CLK4N NC_MEM_A_CLK3P NC_MEM_A_CLK3N NC_MEM_A_CS_L NC_MEM_A_CS_L NC_MEM_A_CKE NC_MEM_A_CKE NC_MEM_B_CLK4P NC_MEM_B_CLK4N NC_MEM_B_CLK3P NC_MEM_B_CLK3N NC_MEM_B_CS_L NC_MEM_B_CS_L NC_MEM_B_ODT NC_MEM_B_ODT NC_MEM_B_CKE NC_MEM_B_CKE TP_MEM_A_CLK4P TP_MEM_A_CLK4N TP_MEM_A_CLK3P TP_MEM_A_CLK3N TP_MEM_A_CS_L TP_MEM_A_CS_L TP_MEM_A_CKE TP_MEM_A_CKE TP_MEM_B_CLK4P TP_MEM_B_CLK4N TP_MEM_B_CLK3P TP_MEM_B_CLK3N TP_MEM_B_CS_L TP_MEM_B_CS_L TP_MEM_B_ODT TP_MEM_B_ODT TP_MEM_B_CKE TP_MEM_B_CKE MAKE_BASE=TRUE 68 19 5% 1/32W 4X0201-HF 5% 1/32W 4X0201-HF 68 68 150 USB ALIASES 68 19 R0998 MEM ALIASES NC_SMC_PA0 TRUE MAKE_BASE=TRUE NC_SMC_PA1 TRUE MAKE_BASE=TRUE NC_ESTARLDO_EN TRUE MAKE_BASE=TRUE NC_SMC_P26 TRUE MAKE_BASE=TRUE NC_SMC_P41 TRUE MAKE_BASE=TRUE NC_SMC_P67 TRUE MAKE_BASE=TRUE NC_SMC_GFX_OVERTEMP_L TRUE MAKE_BASE=TRUE NC_EXCARD_OC_L TRUE MAKE_BASE=TRUE NC_SMC_P24 TRUE MAKE_BASE=TRUE NC_SMC_EXCARD_CP TRUE MAKE_BASE=TRUE NC_ALS_RIGHT TRUE MAKE_BASE=TRUE NC_ALS_GAIN TRUE MAKE_BASE=TRUE NC_SMC_FAN_1_CTL TRUE MAKE_BASE=TRUE NC_SMC_FAN_2_CTL TRUE MAKE_BASE=TRUE NC_SMC_FAN_3_CTL TRUE MAKE_BASE=TRUE NC_SMC_FAN_1_TACH TRUE MAKE_BASE=TRUE NC_SMC_FAN_2_TACH TRUE MAKE_BASE=TRUE NC_SMC_FAN_3_TACH TRUE MAKE_BASE=TRUE NC_SMC_RSTGATE_L TRUE MAKE_BASE=TRUE NC_ISENSE_CAL_EN TRUE MAKE_BASE=TRUE NC_SMC_FWE TRUE MAKE_BASE=TRUE NC_SMC_ANALOG_ID TRUE MAKE_BASE=TRUE NC_ALS_LEFT TRUE NC_SMC_NB_DDR_ISENSEMAKE_BASE=TRUE TRUE MAKE_BASE=TRUE NC_SMC_P10 TRUE MAKE_BASE=TRUE NC_SMC_PA5 TRUE MAKE_BASE=TRUE NC_SMC_GPU_ISENSE TRUE 65 50 13 MISC NC MCP79 ALIASES DP HOTPLUG PULL-DOWN 17 R0996 R0920 5% 1/20W MF 201 HPLUG_DET2 39 NO STUFF 5% 1/20W MF 201 MAKE_BASE=TRUE 39 SMC ALIASES 39 MAKE_BASE=TRUE MAKE_BASE=TRUE 39 5% 1/20W MF 201 NC_LVDS_IG_B_CLK_P NO_TEST=TRUE 20 39 5% 1/20W MF 201 62 67 17 100K 39 150 5% 1/20W MF 201 MAKE_BASE=TRUE AUD_IPHS_SWITCH_EN 4.5OD2.0H-M1.6X0.35 39 R0999 200 MAKE_BASE=TRUE NO_TEST=TRUE NO_TEST=TRUE Z0904 39 NO STUFF R0997 220 NO STUFF LVDS_IG_B_CLK_P 67 17 UNUSED IPHS SIGNAL(FOR IPHONE JACK) 39 NO STUFF R0995 MAKE_BASE=TRUE 67 17 Z0911 4.5OD2.0H-M1.6X0.35 39 D =PP1V05_S0_MCP_FSB UNUSED LVDS SIGNALS STDOFF-4.0OD2.4H-0.5-THNP 39 266 133 200 (166) 333 100 (400) (RSVD) Exist in MRB but not Intel designs Here for CYA If found to be necessary, will move to page14.csa MAKE_BASE=TRUE NO_TEST=TRUE 39 FSB MHZ 1 1 Extra FSB Pull-ups MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE SMC_PA0 SMC_PA1 ESTARLDO_EN SMC_P26 SMC_P41 SMC_BIL_BUTTON_L SMC_GFX_OVERTEMP_L SMC_EXCARD_OC_L SMC_P24 SMC_EXCARD_CP ALS_RIGHT ALS_GAIN SMC_FAN_1_CTL SMC_FAN_2_CTL SMC_FAN_3_CTL SMC_FAN_1_TACH SMC_FAN_2_TACH SMC_FAN_3_TACH SMC_EXCARD_PWR_EN ISENSE_CAL_EN SMC_FWE SMC_ANALOG_ID ALS_LEFT SMC_NB_DDR_ISENSE SMC_P10 SMC_PA5 SMC_GPU_ISENSE 13 0 1 0 1 NC_CRT_IG_R_C_PR 17 Z0902 39 =MCP_BSEL OUT MAKE_BASE=TRUE MAKE_BASE=TRUE 4.5OD2.0H-M1.6X0.35 C CRT_IG_R_C_PR TP_EXTGPU_RESET_L PCIE_FC_PRSNT_L Z0903 CPU_BSEL MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE IN NC_MCP_CLK27M_XTALOUT NO_TEST=TRUE MAKE_BASE=TRUE EXTGPU_RESET_L MCP_CLK27M_XTALOUT 65 0 0 1 1 MAKE_BASE=TRUE NO_TEST=TRUE PCIE_MINI_PRSNT_L Z0901 NO_TEST=TRUE AIRPORT CARD AND TURBOMEM PRESENT SIGNAL 1 NC_MCP_TV_DAC_VREF MCP_CLK27M_XTALIN 17 MAKE_BASE=TRUE STDOFF-4.0OD2.4H-0.5-THNP 4.5OD2.0H-M1.6X0.35 MCP_TV_DAC_VREF 17 NO_TEST=TRUE MAKE_BASE=TRUE PEG_CLK100M_N 16 17 17 MAKE_BASE=TRUE 67 16 MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE PEG_PRSNT_L NC_MCP_TV_DAC_RSET NO_TEST=TRUE NC_PEG_R2D_C_P 16 BOSSES STANDOFFS =PEG_R2D_C_P MCP_TV_DAC_RSET 17 MAKE_BASE=TRUE NO_TEST=TRUE 16 67 16 MAKE_BASE=TRUE 16 SC0900 EMI-SPRING PS-25N BSEL UNUSED CRT & TV-OUT INTERFACE NC_PEG_D2R_N NO_TEST=TRUE CPU FSB FREQUENCY STRAPS DACS ALIASES UNUSED GPU LANES PLACE CLIPS PER MCO ON TOPSIDE NEAR BATTERY CONNECTOR J6900 4 68 19 68 19 TP_USB_EXTB_P TP_USB_EXTB_N TP_USB_EXTC_P TP_USB_EXTC_N TP_USB_EXTD_P TP_USB_EXTD_N TP_USB_EXCARD_P TP_USB_EXCARD_N TP_USB_MINI_P TP_USB_MINI_N USB_EXTB_P USB_EXTB_N USB_EXTC_P USB_EXTC_N USB_EXTD_P USB_EXTD_N USB_EXCARD_P USB_EXCARD_N USB_MINI_P USB_MINI_N MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE B MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE EXTERNAL PORT A MAKE_BASE=TRUE 37 =USB2_EXTA_P USB_EXTA_P 37 =USB2_EXTA_N USB_EXTA_N 37 19 68 MAKE_BASE=TRUE 19 68 MAKE_BASE=TRUE =EXTAUSB_OC_L USB_EXTA_OC_L 19 MAKE_BASE=TRUE CAMERA 17 17 17 17 17 17 ENET_RESET_L MCP_CLK25M_BUF0_R ENET_PWRDWN_L ENET_MDC ENET_TX_CTRL ENET_TXD NC_ENET_RESET_L MAKE_BASE=TRUE NC_MCP_CLK25M_BUF0_R MAKE_BASE=TRUE NC_ENET_PWRDWN_L MAKE_BASE=TRUE NC_ENET_MDC MAKE_BASE=TRUE NC_ENEX_TX_CTRL MAKE_BASE=TRUE NC_ENET_TXD MAKE_BASE=TRUE 59 =USB2_CAMERA_P USB_CAMERA_P 59 =USB2_CAMERA_N USB_CAMERA_N 19 68 MAKE_BASE=TRUE 19 68 MAKE_BASE=TRUE TRACKPAD(WELLSPRING) 38 =USB2_TPAD_P USB_TPAD_P 38 =USB2_TPAD_N USB_TPAD_N 19 68 MAKE_BASE=TRUE 19 68 MAKE_BASE=TRUE IR 38 =USB2_IR_P USB_IR_P 38 =USB2_IR_N USB_IR_N 19 68 MAKE_BASE=TRUE 19 68 MAKE_BASE=TRUE BT (M93) 34 34 =USB2_BT_P =USB2_BT_N USB_BT_P MAKE_BASE=TRUE USB_BT_N 19 68 19 68 MAKE_BASE=TRUE SIGNAL ALIAS /RESET A SYNC_MASTER=(MASTER) SYNC_DATE=(MASTER) NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART 20 SMC_IG_THROTTLE_L SMC_GFX_THROTTLE_L GND VOLTAGE=0V MIN_NECK_WIDTH=0.20 MM MIN_LINE_WIDTH=0.30 MM 39 MAKE_BASE=TRUE SMC_SMS_INT_L 40 =SMC_SMS_INT SIZE MAKE_BASE=TRUE APPLE INC SMC_ADAPTER_EN 40 39 20 SMC_ADAPTER_PRESENT SCALE SHT NONE REV 051-7631 34 MAKE_BASE=TRUE DRAWING NUMBER D 39 2.3.0 OF 71 A OMIT BI 65 13 BI 65 13 BI 65 13 BI 65 13 BI 65 13 BI 65 13 BI 65 13 BI 65 13 BI 65 13 BI 65 13 BI 65 13 BI 65 13 BI 65 13 BI 65 13 BI 65 13 BI 65 13 BI 65 13 BI 65 13 BI 65 13 BI 65 13 BI 65 13 BI 65 13 BI 65 13 BI 65 13 BI 65 13 BI 65 13 BI 65 13 BI 65 13 BI 65 13 BI 65 13 BI 65 13 BI 65 13 BI 65 13 65 13 65 13 FSB_REQ_L FSB_REQ_L FSB_REQ_L FSB_REQ_L FSB_REQ_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_ADSTB_L IN CPU_A20M_L OUT CPU_FERR_L IN CPU_IGNNE_L R1 R5 U1 P4 W5 AN1 AK4 AG1 AT4 AK2 AT2 AH2 AF4 AJ5 AH4 AM4 AP4 AR5 AJ1 AL1 AM2 AU5 AP2 AR1 AN5 C7 D4 F10 REQ0* REQ1* REQ2* REQ3* REQ4* A17* A18* A19* A20* A21* A22* A23* A24* A25* A26* A27* A28* A29* A30* A31* A32* A33* A34* A35* ADSTB1* BR0* FSB_BREQ0_L M2 13 65 BI 13 65 BI 13 65 BI 13 65 BI 13 65 BI IN N1 FSB_LOCK_L BI RESET* RS0* RS1* RS2* TRDY* G5 K2 H4 K4 L1 FSB_CPURST_L FSB_RS_L FSB_RS_L FSB_RS_L FSB_TRDY_L HIT* HITM* H2 F2 FSB_HIT_L FSB_HITM_L B40 D8 LOCK* BPM0* BPM1* BPM2* BPM3* PRDY* PREQ* TCK TDI TDO TMS TRST* 65 AY8 BA7 BA5 AY2 AV10 AV2 AV4 AW7 AU1 AW5 AV8 XDP_BPM_L XDP_BPM_L XDP_BPM_L XDP_BPM_L XDP_BPM_L XDP_BPM_L XDP_TCK XDP_TDI XDP_TDO XDP_TMS XDP_TRST_L R1000 10 11 12 54.9 1% 1/20W MF 201 13 65 D CPU_IERR_L CPU_INIT_L IERR* INIT* =PP1V05_S0_CPU 13 65 13 65 IN 12 13 65 IN 13 65 IN 13 65 IN 13 65 IN 13 65 BI 13 65 BI 13 65 OMIT BI 12 65 BI 12 65 BI 12 65 BI 12 65 BI R1001 54.9 1% 1/20W MF 201 12 65 12 65 IN 65 13 IN 65 13 IN 65 13 IN 24 12 OUT CPU_STPCLK_L CPU_INTR CPU_NMI CPU_SMI_L XDP_DBRESET_L CPU_TEST1 CPU_TEST2 TP_CPU_TEST3 CPU_TEST4 TP_CPU_TEST5 TP_CPU_TEST6 F8 C9 C5 E5 J7 E37 D40 C43 AE41 AY10 AC43 65 13 BI BI 65 13 BI 12 65 65 13 BI IN 12 65 65 13 BI IN 12 65 65 13 BI 65 13 BI 65 13 BI 65 13 BI 65 13 BI 65 13 BI 65 13 BI 65 13 BI 65 13 BI 65 13 BI 65 13 BI 65 13 BI 65 13 BI OUT CPU_PROCHOT_L CPU_THERMD_P CPU_THERMD_N OUT 45 OUT 45 B10 PM_THRMTRIP_L OUT 13 40 65 FSB_CLK_CPU_P FSB_CLK_CPU_N BI 12 65 D38 BB34 BD34 A35 C35 BI 65 13 IN OUT 13 40 50 65 H CLK BCLK0 BCLK1 BI 65 13 IN THERMAL STPCLK* LINT0 LINT1 SMI* 65 13 BI ICH 65 13 BI 65 13 5% 1/20W MF 201 THERMTRIP* 65 13 65 13 BI 68 A20M* FERR* IGNNE* BI 12 65 R1002 PROCHOT* THRMDA THRMDC 65 13 IN 13 65 65 13 BI IN 13 65 65 13 BI 65 13 BI 65 13 BI 65 13 BI NC_CPU_RSVD_J9 65 13 BI NC_CPU_RSVD_F4 NC_CPU_RSVD_H8 NC_CPU_RSVD_V2 NC_CPU_RSVD_Y2 NC_CPU_RSVD_AG5 NC_CPU_RSVD_AL5 65 13 BI 65 13 BI 65 13 BI 65 13 BI 65 13 BI 65 13 BI 65 13 BI 65 13 BI DBR* RSVD7 RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14 TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 J9 F4 H8 V2 Y2 AG5 AL5 B 1K CPU JTAG Support 65 12 XDP_TMS R1090 65 12 XDP_TDI 54.9 1% 1/20W MF 201 65 25 R1092 54.9 PLACEMENT_NOTE=Place R1092 near ITP connector (if present) 1% 1/20W MF 201 CPU_TEST4 C1014 R1094 XDP_TRST_L 649 CPU_GTLREF GTLREF 54.9 1% 1/20W MF 201 10% 16V X5R 402 MISC R1010 5% 1/20W MF 201 R1011 1K NO STUFF D48* D49* D50* D51* D52* D53* D54* D55* D56* D57* D58* D59* D60* D61* D62* D63* DSTBN3* DSTBP3* DINV3* FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_DSTB_L_N FSB_DSTB_L_P FSB_DINV_L 65 65 65 65 BI 13 65 BI 13 65 BI 13 65 BI 13 65 BI 13 65 BI 13 65 BI 13 65 BI 13 65 BI 13 65 BI 13 65 BI 13 65 BI 13 65 BI 13 65 BI 13 65 BI 13 65 BI 13 65 BI 13 65 BI 13 65 BI 13 65 BI 13 65 BI 13 65 BI 13 65 BI 13 65 BI 13 65 BI 13 65 BI 13 65 BI 13 65 BI 13 65 BI 13 65 BI 13 65 BI 13 65 BI 13 65 BI 13 65 BI 13 65 BI 13 65 BI 13 65 BI 13 65 BI 13 65 C B CPU_COMP CPU_COMP CPU_COMP CPU_COMP DPRSTP* DPSLP* DPWR* PWRGOOD SLP* PSI* 65 65 65 OUT CPU_BSEL OUT CPU_BSEL OUT CPU_BSEL BSEL0 BSEL1 BSEL2 CPU_DPRSTP_L CPU_DPSLP_L FSB_DPWR_L CPU_PWRGD FSB_CPUSLP_L TP_CPU_PSI_L IN 13 50 65 IN 13 65 IN 13 65 IN 12 13 65 IN 13 65 R1023 R1021 54.9 1% 1/20W MF 201 54.9 1% 1/20W MF 201 5% 1/20W MF 201 R1022 R1020 27.4 R1012 1K 5% 1/20W MF 201 FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_DSTB_L_N FSB_DSTB_L_P FSB_DINV_L D32* D33* D34* D35* D36* D37* D38* D39* D40* D41* D42* D43* D44* D45* D46* D47* DSTBN2* DSTBP2* DINV2* COMP0 COMP1 COMP2 COMP3 0.1uF NO STUFF 1% 1/20W MF 201 NO STUFF 65 12 D16* D17* D18* D19* D20* D21* D22* D23* D24* D25* D26* D27* D28* D29* D30* D31* DSTBN1* DSTBP1* DINV1* NO STUFF R1093 XDP_TCK FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_DSTB_L_N FSB_DSTB_L_P FSB_DINV_L CPU_TEST1 CPU_TEST2 R1006 65 12 D0* D1* BGA D2* (2 OF 8) D3* D4* D5* D6* D7* D8* D9* D10* D11* D12* D13* D14* D15* DSTBN0* DSTBP0* DINV0* 2K 1% 1/20W MF 201 XDP_TDO 54.9 1% 1/20W MF 201 R1091 65 12 R1005 U1000 FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_DSTB_L_N FSB_DSTB_L_P FSB_DINV_L DATA GRP BI 65 13 FSB_DEFER_L FSB_DRDY_L FSB_DBSY_L 13 65 BI PENRYN-SFF BI 65 13 N5 F38 J1 BI PDC-Q9YM-ES1-1.86-17W-1066-CO-6M 65 13 DEFER* DRDY* DBSY* FSB_ADS_L FSB_BNR_L FSB_BPRI_L DATA GRP BI M4 J5 L5 DATA GRP 65 13 ADS* BNR* BPRI* BGA (1 OF 8) PENRYN-SFF BI U1000 PDC-Q9YM-ES1-1.86-17W-1066-CO-6M CONTROL BI 65 13 A3* A4* A5* A6* A7* A8* A9* A10* A11* A12* A13* A14* A15* A16* ADSTB0* ADDR GROUP0 BI 65 13 P2 V4 W1 T4 AA1 AB4 T2 AC5 AD2 AD4 AA5 AE5 AB2 AC1 Y4 XDP/ITP SIGNALS 65 13 FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_ADSTB_L DATA GRP1 C BI ADDR GROUP1 D 65 13 PLACEMENT_NOTE=Place C1014 within 12.7mm of CPU PLACEMENT_NOTE=Place R1005 within 12.7mm of CPU PLACEMENT_NOTE=Place R1006 within 12.7mm of CPU 2 27.4 1% 1/20W MF 201 1% 1/20W MF 201 PLACEMENT_NOTE (all resistors): 1% 1/20W MF 201 Place within 12.7mm of CPU CPU FSB A SYNC_MASTER=M97 SYNC_DATE=02/04/2008 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING SYNC FROM M97 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC SCALE SHT NONE REV 051-7631 2.3.0 OF 71 A C B (3 OF 8) VCC VCC 27A AD28 AD30 AB28 AB30 Y28 Y30 AK26 AH26 AF26 AK28 AK30 AH28 AH30 AF28 AF30 AP26 AM26 AP28 AP30 AM28 AM30 AY26 AV26 AT26 AY28 AY30 AV28 AV30 AT28 AT30 BD26 BB26 BD28 (CPU IO POWER 1.05V) 2.5A VCCP N37 L37 K38 J37 W37 V38 U37 R37 P38 AC37 AB38 AA37 AK38 AJ37 AG37 AF38 =PP1V05_S0_CPU 10 11 12 (CPU INTERNAL PLL POWER 1.5V) 0.130A VCCA VID VCCSENSE VSSSENSE =PP1V5_S0_CPU B34 D34 BD8 BC7 BB10 BB8 BC5 BB4 AY4 CPU_VID OUT 11 50 65 CPU_VID OUT 11 50 65 CPU_VID OUT 11 50 65 CPU_VID OUT 11 50 65 CPU_VID OUT 11 50 65 CPU_VID OUT 11 50 65 CPU_VID OUT 11 50 65 VCCA=1.5 ONLY 11 =PPVCORE_S0_CPU OMIT U1000 BGA (7 OF 8) VCC VCC K20 M16 M18 K16 K18 V20 T20 P20 V16 V18 T16 T18 P16 P18 AD20 AB20 Y20 AD16 AD18 AB16 AB18 Y16 Y18 AK20 AK16 AK18 AH20 AF20 AH16 AH18 AF16 AF18 AP20 AM20 AP16 AP18 AM16 AM18 AY20 AV20 AT20 AY16 AY18 AV16 AV18 AT16 AT18 BD20 BB20 BD16 BD18 BB16 BB18 AP14 AM14 AY14 AV14 AT14 BD14 BB14 10 11 64 R1100 100 BD12 1% 1/20W MF AE37 AP38 AN37 AL37 C33 B32 H36 F36 G35 F34 E33 E35 D32 K36 N35 L35 J35 W35 V36 P36 U35 R35 AB36 AC35 AA35 AK36 AF36 AJ35 AG35 AE35 AP36 AN35 AL35 C13 B14 B12 H12 H14 G11 G13 F12 F14 E11 E13 D14 D12 K10 N11 N13 M14 L11 L13 K12 K14 J11 J13 V10 P10 W11 W13 V12 V14 U11 U13 T14 R11 OMIT U1000 BGA (8 OF 8) VCCP VCCP R13 P12 P14 AB10 AD14 AC11 AC13 AB12 AB14 AA11 AA13 Y14 AK10 AF10 AK12 AK14 AJ11 AJ13 AH14 AG11 AG13 AF12 AF14 AE11 AE13 AP10 AR11 AR13 AP12 AN11 AN13 AL11 AL13 AU11 AU13 N7 N9 L7 L9 W7 W9 U7 U9 R7 R9 AC7 AC9 AA7 AA9 AJ7 AJ9 AG7 AG9 AE7 AE9 AR7 AR9 AN7 AN9 AL7 AL9 A33 A13 10 11 12 Y6 Y8 AK6 AK8 AH6 AH8 AF6 AF8 AP6 AP8 AM6 AM8 AY6 AW9 AU7 AV6 AU9 AT6 AT8 BD6 BC9 BB6 BA9 C3 B4 G3 E3 D2 N3 L3 J3 W3 U3 R3 AC3 AA3 OMIT U1000 BGA (6 OF 8) VSS 201 BC13 CPU_VCCSENSE_P CPU_VCCSENSE_N OUT OUT 50 65 50 65 R1101 LAYOUT NOTE: 100 PLACE R1100 AND R1101 1% 1/20W MF 201 WITHIN INCH OF CPU W/ NO STUB LAYOUT NOTE: CPU_VCCSENSE_P/CPU_VCCSENSE_N USE ZO=27.4 OHM DIFFERENTIAL TRACE ROUTING VSS AJ3 AG3 AE3 AR3 AN3 AL3 AW3 AU3 BD4 BC3 BB2 BA3 G1 E1 AW1 BA1 A39 A41 A31 A27 A29 A21 A23 A25 A17 A19 A15 A11 A9 A5 A7 B42 H42 F42 D42 D44 F44 M42 K42 V42 T42 P42 AD42 AB42 Y42 AK42 AH42 AF42 AP42 AM42 AY42 AV42 AT42 AV44 AY44 BB42 BA43 C39 H38 G37 E39 N39 M38 L39 J39 W39 U39 T38 R39 AD38 AC39 AA39 Y38 AJ39 AH38 AG39 AE39 AR37 AR39 AN39 AM38 AL39 AW37 AW39 AU37 AU39 AT38 BD38 BD40 BC41 BA39 B36 D36 H34 M36 M34 K34 T36 V34 T34 P34 AD36 Y36 AD34 AB34 Y34 AK34 AH36 AH34 AF34 AR35 AM36 OMIT U1000 BGA (4 OF 8) VSS VSS E21 E23 E25 N21 N23 N25 L21 L23 L25 J21 J23 J25 W21 W23 W25 U21 U23 U25 R21 R23 R25 AC21 AC23 AC25 AA21 AA23 AA25 AJ21 AJ23 AJ25 AG21 AG23 AG25 AE21 AE23 AE25 AR21 AR23 AR25 AN21 AN23 AN25 AL21 AL23 AL25 AW21 AW23 AW25 AU21 AU23 AU25 BC21 BC23 BC25 BA21 BA23 BA25 C19 C17 G17 G19 E17 E19 N17 N19 L17 L19 J17 J19 W17 W19 U17 U19 R17 R19 AC17 AC19 AA17 AA19 AJ17 AJ19 AG17 AG19 AP34 AM34 AV36 AT36 AY34 AW33 AW35 AV34 AU35 BD36 BB36 BC33 BA33 C31 C29 C27 G31 E31 G27 G29 E27 E29 N31 L31 J31 N27 N29 L27 L29 J27 J29 W31 W27 W29 U31 R31 U27 U29 R27 R29 AC31 AA31 AC27 AC29 AA27 AA29 AJ31 AG31 AE31 AJ27 AJ29 AG27 AG29 AE27 AE29 AR31 AR27 AR29 AN31 AL31 AN27 AN29 AL27 AL29 AW31 AU31 AW27 AW29 AU27 AU29 BC31 BA31 BC27 BC29 BA27 BA29 C25 C23 C21 G21 G23 G25 LAYOUT NOTE: OMIT U1000 BGA (5 OF 8) PENRYN-SFF PDC-Q9YM-ES1-1.86-17W-1066-CO-6M BGA PENRYN-SFF PDC-Q9YM-ES1-1.86-17W-1066-CO-6M D OMIT U1000 BD30 BB28 BB30 B24 B22 H22 H24 F22 F24 D24 D22 M22 M24 K22 K24 V22 V24 T22 T24 P22 P24 AD22 AD24 AB22 AB24 Y22 Y24 AK22 AK24 AH22 AH24 AF22 AF24 AP22 AP24 AM22 AM24 AY22 AY24 AV22 AV24 AT22 AT24 BD22 BD24 BB22 BB24 B20 B18 B16 H20 F20 D20 H16 H18 F16 F18 D18 D16 M20 10 11 64 (CPU CORE POWER) H32 G33 F32 N33 M32 L33 K32 J33 W33 V32 U33 T32 R33 P32 AD32 AC33 AB32 AA33 Y32 AK32 AJ33 AH32 AG33 AF32 AE33 AR33 AP32 AN33 AM32 AL33 AY32 AV32 AU33 AT32 AT34 BD32 BB32 B26 B30 B28 H26 F26 D26 H28 H30 F28 F30 D30 D28 M26 K26 M28 M30 K28 K30 V26 T26 P26 V28 V30 T28 T30 P28 P30 AD26 AB26 Y26 =PP1V05_S0_CPU PENRYN-SFF PDC-Q9YM-ES1-1.86-17W-1066-CO-6M =PPVCORE_S0_CPU =PPVCORE_S0_CPU PENRYN-SFF PDC-Q9YM-ES1-1.86-17W-1066-CO-6M 64 11 10 PENRYN-SFF PDC-Q9YM-ES1-1.86-17W-1066-CO-6M PENRYN-SFF PDC-Q9YM-ES1-1.86-17W-1066-CO-6M VSS VSS AE17 AE19 AR17 AR19 AN17 AN19 AL17 AL19 AW17 AW19 AU17 AU19 BC17 BC19 BA17 BA19 C15 C11 H10 G15 E15 M10 N15 L15 J15 M12 T10 W15 U15 R15 T12 AD10 Y10 AC15 AA15 AD12 Y12 AH10 AJ15 AG15 AE15 AH12 AM10 AR15 AN15 AL15 AM12 AT10 AW15 AU15 AY12 AW11 AW13 AV12 AT12 BC15 BA15 BC11 BB12 BA11 BA13 B6 H6 G9 F6 E9 D6 M6 M8 K6 K8 U5 V6 V8 T6 T8 P6 P8 AD6 AD8 AB6 AB8 D C B PROVIDE A TEST POINT (WITH NO STUB) TO CONNECT A DIFFERENTIAL PROBE BETWEEN VCCSENSE AND VSSSENSE CPU Power & Ground A SYNC_MASTER=(MASTER) SYNC_DATE=(MASTER) NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC SCALE SHT NONE REV 051-7631 2.3.0 OF 10 71 A 1.5V S0 FET (1.5V S0 FET FOR DDR3 MEM, MCP79 AND CPU) =PP1V5_S3_P1V5S0FET CRITICAL 3.3V S3 FET Q7810 C7802 FDC638P_G SM =PP3V3_S5_P3V3S3FET =PP3V3_S3_FET MOSFET FDC638P CHANNEL P-TYPE C7811 33000PF 10K D RDS(ON) 10% 6.3V 5% 1/20W 10K 201 P3V3S3_SS 2 Q7803 10% MF 10V SSM3K15FV PWRPK-1212-8-HF Q7871 D =PP1V5_S0_FET R7871 G S 1 C7803 10% 10V CERM 402 5% 1/20W MF 201 D 56 56 G S =MCPDDR_EN IN 3.3V RMGT FET FDC606P_G 5V S0 FET C7841 D MOSFET FDC606P CHANNEL P-TYPE G LOADING X5R MF 201 C =PP3V3_RMGT_FET P5VS0_SS D 5% 1/20W MF 201 10V 201 X5R C7821 G 0.033UF 10K 10% MF R7820 5% 1/20W Q7845 S 0.562 A (EDP) 0.01UF 33K SOT-23-HF 26 MOHM @4.5V C7840 R7840 P5VS0_EN_L Q7820 NTR4101P =PP3V3_S5_P3V3RMGTFET RDS(ON) CRITICAL 10% 6.3V 5% 1/20W @ 2.5V Vgs: Rds(on) = 90mOhm max I(max) = 1.7A (85C) 33000PF 100K 201 =PP5V_S0_FET S =PP5V_S3_P5VS0FET 5.027A (EDP) Q7840 SOT-6 R7842 MOHM @3.5V VGS CRITICAL 5V S0 FET N-TYPE LOADING S =P3V3S3_EN IN SI7108DNS CHANNEL RDS(ON) SOT563 G MOSFET MCPDDR_EN_L_RC SSM6N15FEAPE 1.5V S0 FET 0.068UF 47K Q7871 SOT563 MCPDDR_EN_L SOD-VESM-HF D SSM6N15FEAPE 201 D SI7108DN G X5R 201 Q7801 S 5% 1/20W 100K 5% 1/20W MF 201 CRITICAL D MCPDDR_SS 5% 1/20W MF 201 R7803 0.315 A (EDP) 0.01UF 47K LOADING C7810 R7810 P3V3S3_EN_L 48 mOhm @4.5V X5R MF 201 10% 6.3V X5R 201 R7801 =PP5V_S3_MCPDDRFET 1 R7812 0.1UF 3.3V S3 FET R7821 100K P3V3RMGT_EN_L 10% 16V X5R 402 C C7820 0.01UF P3V3RMGT_SS 201 SSM3K15FV D 5% 1/20W MF 201 SOD-VESM-HF Q7821 D S 10% 16V CERM 402 SSM6N15FEAPE SOT563 56 G S =P5VS0_EN IN G CRITICAL Q7830 3.3V S0 FET SOT-6 D FDC606P CHANNEL P-TYPE RDS(ON) X5R C7830 1 P3V3S0_SS =PP3V3_S5_P1V05RMGTFET 10K 26 MOHM @4.5V 2.046 A (EDP) R7864 1% 1/20W MF 201 10V MF X5R 201 SI2312BDS G SOT23 S Q7861 D =PP1V05_RMGT_FET SSM6N15FEAPE R7861 P1V05RMGT_EN_L G S 1 56 G S 1.05V S0 FET =P3V3S0_EN IN 7 P1V05S0_SS 5% 1/20W MF 201 NO STUFF C7852 R7854 0.1UF =PP3V3_S5_P1V05FET P1V05S0_RC N-TYPE Q7853 RDS(ON) 6.1 MOHM @4.5V VGS SI7108DN LOADING 8.25A (EDP) D =PPVTT_S0_VTTCLAMP =PP1V05_S0_FET R7851 P1V05_EN_L A G S 1 5% 1/20W MF 201 5% 1/20W MF 201 IN 90mA max load @ 0.9V 81mW max power C7853 10% 10V CERM 402 D S SSM6N15FEAPE SOT563 2 G POWER FETS SYNC_MASTER=YUAN.MA VTTCLAMP_EN D Q7875 NO STUFF C7876 SSM6N15FEAPE 54 24 IN THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING 1000PF 10% 16V X7R 201 P1V05S0_EN G S I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART =DDRVTT_EN SIZE DRAWING NUMBER D APPLE INC SCALE REV 051-7631 SHT NONE SYNC_DATE=02/04/2008 NOTICE OF PROPRIETARY PROPERTY SOT563 56 G PM_SLP_RMGT_L CKT FROM T18 R7876 SOT563 S VTTCLAMP_L Q7875 P1V05_EN_L_RC SSM6N15FEAPE G =PP5V_S3_VTTCLAMP 0.068UF 100K 2 10 100K IN 5% 1/10W MF-LF 603 SOT563 57 20 R7875 PWRPK-1212-8-HF SSM6N15FEAPE 10K D SI7108DN CHANNEL MCP79 DDR PAD LEAKAGE IS HIGH ENOUGH THAT NVIDIA RECOMMENDS UNPOWERING DURING SLEEP IN ORDER TO SUPPORT UNPOWERING RAIL, HARDWARE MUST GUARANTEE MEM_CKE SIGNALS ARE LOW BEFORE RAIL IS TURNED OFF, AND REMAINS LOW UNTIL AFTER RAIL TURNS BACK ON OR DIMMS WILL EXIT SELF-REFRESH PREMATURELY MEM_VTT_EN OUTPUT FROM MCP79 USED TO ENABLE CLAMP ON VTT RAIL, WHICH PULLS ALL CKE SIGNALS LOW THROUGH VTT TERMINATION RESISTORS S Q7851 R7853 Q7851 G 5% 1/20W MF 201 10% 6.3V X5R 201 5% 1/20W MF 201 510 MOSFET CRITICAL D NO STUFF S B P1V05RMGT_EN_L_RC SOT563 =PP1V05_S5_P1V05S0FET 1.05V S0 FET 220K 10% 10V CERM 402 SSM6N15FEAPE R7852 =PP5V_S3_P1V05S0FET Q7861 D 1% 1/20W MF 201 C7861 0.068UF 15K MCP79 DDRVTT FET SOT563 201 D @ 1.8V Vgs: Rds(on) = 47mOhm max I(max) = 3.1A (70C) CRITICAL Q7860 1% 1/20W MF 201 SOD-VESM-HF B D P1V05RMGT_SS 69.8K 10% 1/20W Q7805 20% 10V CERM 402 R7860 5% SSM3K15FV 0.1UF 0.01UF 47K P3V3S0_EN_L LOADING 201 R7830 10% 6.3V MF C7860 33000PF 1/20W =PP1V05_RMGT_P1V05RMGTFET MOSFET G C7831 5% 201 =PP3V3_S0_FET 100K 3.3V S0 FET S =PP3V3_S5_P3V3S0FET R7832 1.05V RMGT FET PM_SLP_RMGT_L IN FDC606P_G 57 20 2.3.0 OF 57 71 A PBUS SUPPLY / BATTERY CHARGER CRITICAL CRITICAL Q7900 Q7901 HAT1127H HAT1127H 0.1UF 10% 25V X5R 402 58 S =PP3V42_G3H_CHGR R7962 CHGR_AMON CRITICAL 0.1UF 10% 25V X5R 402 U7960 TL331 1.82K CHGR_LOWCURRENT_GATE GND R79611 1% 1/20W MF 201 SOT23-5 R7923 R7901 CHGR_SGATE MIN_NECK_WIDTH=0.2 MM MIN_LINE_WIDTH=0.2 MM R7910 30.1K OMIT R7940 4.7 C7941 =PP3V42_G3H_CHGR C7947 (CHGR_ACIN) 10% 10V X5R 402-1 VDD 58 58 12 VHST 11 SCL 10 SDA CHGR_SCL CHGR_SDA NC CHGR_ACIN R7945 C7944 0.01UF 10% 10V 201 X5R 29 THRM_PAD C7943 56.2K 0.1UF 1% 1/16W MF-LF 402 2 10% 16V X5R 402 CHGR_VCOMP_R C7945 AGATE 28 CSIN 27 CHGR_AGATE CHGR_CSIP CHGR_CSIN 16 58 BGATE DCIN CHGR_BGATE CHGR_DCIN 58 BOOT 25 UGATE 24 PHASE 23 CHGR_BOOT CHGR_UGATE CHGR_PHASE LGATE 21 CHGR_LGATE 10% 25V X5R 402 AMON BMON 15 ACOK 14 R7920 0.02 XW7921 SM PPVDCIN_G3H_PRE_R MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM MIN_NECK_WIDTH=0.2 MM MIN_LINE_WIDTH=0.3 MM 10% 25V X5R 402 C7920 20% 25V POLY-TANT CASE-D2-SM C7921 20% 25V POLY-TANT CASE-D2-SM GND_CHGR_SGND C7922 1 1UF 10% 25V X5R 603-1 CRITICAL FDMC8296 POWER33 CHGR_VNEG_R 4.7UH-7.5A IHLP4040CZ-SM 10% 50V CERM 402 58 42 =SMBUS_CHGR_SDA CHGR_SDA 58 CHGR_ACOK 58 R7930 0.01 0.5% 1W MF 0612 MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM 70 PPVBAT_G3H_CHGR_REG MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM PPVBAT_G3H_CHGR_OUT CRITICAL CRITICAL CRITICAL C7930 47UF 20% 10V POLY-TANT CASE-B2-SM FDMC8296 POWER33 10% 25V X5R 603-1 47UF 20% 10V POLY-TANT CASE-B2-SM XW7930 SM C7926 XW7931 1000PF PWM FREQ = 400 kHz MAX CURRENT = 5.35A?? 10% 16V X7R 201 58 70 C7935 1UF C7931 (CHGR_CSOP) B SM PPVBAT_G3H_CHRGR_REG_0 70 MIN_LINE_WIDTH=0.2MM R79311 10 5% 1/20W MF 201 (AC adapter limited?) GND_CHGR_SGND 58 470PF CHGR_SCL CRITICAL 7AMP-24V C7946 =SMBUS_CHGR_SCL =PPBUSB_G3H 1206 L7900 Q7921 3.01K 1% 1/16W MF-LF 402 TO SYSTEM F7900 CRITICAL MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM 44 S D XW7900 SM R79461 =PPBUSA_G3H 1% 1/4W MF-LF 1206 S B 42 0.0022 CRITICAL Q7920 CHGR_AMON 58 CHGR_BMON 58 CHGR_ACOK 58 R7980 G 0.1UF 10% 25V X5R 402 CRITICAL 10% 25V X5R 603-1 58 D C7925 C7923 1UF 22UF 22UF G C KELVIN CONNECTION TO CURRENT SENSOR U5480 70 PP18V5_S5_CHGR_SW_R CRITICAL CRITICAL 0.1UF 10% 50V CERM 402 GND_CHGR_SGND 0.5% 1W MF 0612 0.001UF 58 CRITICAL C7996 NC TRKL* 13 26 AGND ICOMP VCOMP VNEG CSOP CSON MIN_NECK_WIDTH=0.2MM 20 QFN SM MIN_LINE_WIDTH=0.2MM C7995 U7900 CSIP VREF ACIN CHGR_ICOMP CHGR_VCOMP CHGR_VNEG CHGR_CSOP 18 CHGR_CSON 17 33000PF 10% 6.3V X5R 201 VDDP OMIT 1UF PGND pullups offpage 5% 1/20W MF 201 10% 10V X5R 402-1 CRITICAL XW7920 R7921 10 C7940 0.1UF 1% 1/20W MF 201 C7942 ISL6258 9.76K OMIT 10% 16V CERM 402 PPVDCIN_G3H_PRE_0 5% MIN_LINE_WIDTH=0.2MM 1/20W MIN_NECK_WIDTH=0.2MM MF 201 0.047UF OMIT 1UF 10% 6.3V X5R 402-1 R79111 C7924 5% 1/20W MF 201 CHGR_VDDP 5% 1/16W MF-LF 402 1UF 10 70 22 C 58 2CHGR_VDD 19 1% 1/20W MF 201 62K 44 58 1 5% 1/20W MF 201 VCC CHGR_LOWCURRENT_REF CHGR_DCIN 100K 5% 1/20W MF 201 10% 25V X5R 402 1% 1/20W MF 201 2 MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.2 MM 62K C7960 0.1UF 57.6K C7910 R7999 CHGR_SGATE_DIV 5% 1/20W MF 201 2 100K R79601 58 D 5 D R79001 D C7900 PPVDCIN_G3H_PRE MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM B0530WS-X-G 70 43 G G D7910 SOD-323 MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.2 MM D PPVDCIN_G3H_PRE2 70 CRITICAL LFPAK-SM S 49 =PP18V5_G3H_CHGR LFPAK-SM MIN_NECK_WIDTH=0.2MM 70 PPVBAT_G3H_CHRGR_REG_R MIN_LINE_WIDTH=0.2MM MIN_NECK_WIDTH=0.2MM R79471 10 5% 1/20W MF 201 (CHGR_CSOP) (CHGR_CSON) ACOK pullup/down on SMC page 49 40 39 SMC_BC_ACOK AMON PULLDOWN LOGIC MAKE_BASE=TRUE CHGR_AMON BATTERY CHARGING 58 CRITICAL PLACE RC CLOSE TO SMC CHGR_BMON 58 SMC_BATT_ISENSE Q7950 39 R7971 58 5% 1/16W MF-LF 402 R7974 10% 6.3V 58 CHGR_AMON 39 40 43 44 58 SMC_DCIN_ISENSE R7970 5% 1/16W MF-LF 402 39 C7971 Q7970 R79731SSM6N15FEAPE 10% 6.3V CERM 402 GND_SMC_AVSS 70 58 100K C7950 G 10% 10V X5R 201 S 1 BATT_POS_F 49 PBUS Supply/Battery Charger C7951 SYNC_MASTER=M70 0.1UF 10% 16V X5R 402 SYNC_DATE=01/09/2007 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING D CHGR_VDD_L I TO MAINTAIN THE DOCUMENT IN CONFIDENCE SOT563 5% 1/20W MF 201 39 40 43 44 58 PPVBAT_G3H_CHGR_OUT 0.01UF 58 CHGR_VDD 0.68UF MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM 5% 1/20W MF 201 PLACE RC CLOSE TO SMC Q7970 D 1MSSM6N15FEAPE SOT563 402 5% 1/20W MF 201 TO BATTERY SO-8 1M CERM GND_SMC_AVSS FDS6681Z R7975 C7972 0.68UF A 1NO STUFF =PP3V42_G3H_CHGR II NOT TO REPRODUCE OR COPY IT CHGR_BGATE 58 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART G S SIZE CHGR_VDD_R DRAWING NUMBER D APPLE INC SCALE SHT NONE REV 051-7631 2.3.0 OF 58 71 A R9002 FDC638P_G =PP3V3_S5_LCD CRITICAL 100K 10% 6.3V X5R 201 SSM3K15FV D 70 CRITICAL OMIT C9011 10% 6.3V X5R 201 LCDVDD_PWREN_L_R SOD-VESM-HF PP3V3_LCDVDD_SW VOLTAGE=3.3V MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM 0.1UF 5% 1/20W MF 201 Q9004 0.1UF 10K 2 R9023 LCDVDD_PWREN_L LCD + CAMERA CONNECTOR SM 5% 1/20W MF 201 C9040 90-OHM-100MA 10UF 1210-4SM1 SYM_VER-1 20% 6.3V X5R 603 3300PF 1 G IN S =USB2_CAMERA_N BI =USB2_CAMERA_P CRITICAL BI L9052 42 =I2C_ALS_SDA 240-OHM-0.2A-0.8-OHM I2C_ALS_SDA_F =I2C_ALS_SCL 240-OHM-0.2A-0.8-OHM I2C_ALS_SCL_F 0201 L9051 L9005 10% 10V X5R 201 LVDS_IG_PANEL_PWR D L9007 C9012 C9013 17 Q9003 D FERR-120-OHM-1.5A =PP5V_S3_CAMERA 42 0201 0402-LF R9014 C9016 100K 1 2 NPO 1000PF 5% 1/20W MF 201 10% 16V X7R 201 CRITICAL L9004 C9052 10PF C9051 5% J9000 20347-130E-11 5% 25V NPO 201 201 FERR-120-OHM-1.5A CRITICAL 10PF 25V F-RT-SM 38 2 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 0402-LF C9015 10% 16V X7R 201 1000PF PLACE FILTERS AND CAPS NEAR PINS ON CONNECTOR VOLTAGE=5V C 70 6 120-OHM-0.3A-EMI =PP3V3_S0_LCD MIN_NECK_WIDTH=0.2MM L9008 MIN_LINE_WIDTH=0.3MM (LVDS DDC POWER) PP5V_S3_CAMERA_F USB2_CAMERA_F_P USB2_CAMERA_F_N VOLTAGE=3.3V MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM 70 PP3V3_LCDVDD_SW_F VOLTAGE=3.3V MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM 70 PP3V3_S0_LCD_F 0402-LF C9010 LVDS_IG_A_DATA_F_N 67 LVDS_IG_A_DATA_F_P 67 LVDS_IG_A_DATA_F_N 67 LVDS_IG_A_DATA_F_P 67 LVDS_IG_A_DATA_F_N 67 LVDS_IG_A_DATA_F_P 67 LVDS_IG_A_CLK_F_N 67 LVDS_IG_A_CLK_F_P 67 1000PF 10% 16V X7R 201 62 R9008 R9009 10K 62 10K 17 BI 17 BI LVDS_IG_DDC_CLK LVDS_IG_DDC_DATA 62 5% 1/20W MF 201 5% 1/20W MF 201 62 62 62 62 70 LCDBKLT_RTN LCDBKLT_RTN LCDBKLT_RTN LCDBKLT_RTN LCDBKLT_RTN LCDBKLT_RTN PPVOUT_S0_LCDBKLT BI 67 17 BI LVDS_IG_A_DATA_N LVDS_IG_A_DATA_P B L9010 SYM_VER-2 1210-4SM1 90-OHM-100MA BI 67 17 BI LVDS_IG_A_DATA_N LVDS_IG_A_DATA_P L9011 MIC CONNECTOR MIN_LINE_WIDTH=0.20MM MIN_NECK_WIDTH=0.20MM VOLTAGE=3.3V PP3V3_S0_MIC_F NC NC 67 17 BI L9012 SYM_VER-2 1210-4SM1 90-OHM-100MA CRITICAL L9006 600-OHM-300MA AUD_MIC_DATA 0402 CRITICAL AUD_MIC_DATA_F AUD_MIC_CLK_F 35 67 17 BI 67 17 BI LVDS_IG_A_CLK_N LVDS_IG_A_CLK_P 600-OHM-300MA AUD_MIC_CLK CRITICAL L9053 90-OHM-100MA 1210-4SM1 SYM_VER-2 LVDS,Camera Conn and ALS Conn SYNC_MASTER=GPU 35 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING 0402 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE 0.01UF 10% 16V CERM 402 APN:518S0536 SYNC_DATE=06/23/2006 0402 600-OHM-300MA MIN_LINE_WIDTH=0.20MM MIN_NECK_WIDTH=0.20MM L9031 GND_MIC_F C9050 0402 A L9050 LVDS_IG_A_DATA_N LVDS_IG_A_DATA_P L9030 BI CRITICAL CRITICAL 67 17 600-OHM-300MA =PP3V3_S0_MIC J9050 GS03067-11131-7F CRITICAL CRITICAL F-RT-SM NO STUFF C9030 C9053 10PF 0.01UF 10% 16V CERM 402 5% 25V NPO 201 II NOT TO REPRODUCE OR COPY IT NO STUFF C9031 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART 10PF 5% 25V SIZE 201 D NPO APPLE INC DRAWING NUMBER REV 051-7631 SCALE SHT NONE B 518S0433 SYM_VER-2 1210-4SM1 90-OHM-100MA C 39 CRITICAL 67 17 LCD I/F 31 32 33 34 35 36 37 CRITICAL 67 17 CAMERA I/F 2.3.0 OF 59 71 A 17 17 17 17 17 17 17 17 17 D 17 17 =MCP_HDMI_TXC_P =MCP_HDMI_TXC_N =MCP_HDMI_TXD_P =MCP_HDMI_TXD_N =MCP_HDMI_TXD_P =MCP_HDMI_TXD_N =MCP_HDMI_TXD_P =MCP_HDMI_TXD_N =MCP_HDMI_HPD =MCP_HDMI_DDC_CLK =MCP_HDMI_DDC_DATA DP_ML_P DP_ML_N DP_ML_P DP_ML_N DP_ML_P DP_ML_N DP_ML_P DP_ML_N DP_HPD 61 67 MAKE_BASE=TRUE 61 67 MAKE_BASE=TRUE 61 67 MAKE_BASE=TRUE 61 67 MAKE_BASE=TRUE 61 67 MAKE_BASE=TRUE 61 67 MAKE_BASE=TRUE 61 67 MAKE_BASE=TRUE 61 67 MAKE_BASE=TRUE 61 D MAKE_BASE=TRUE DP_IG_DDC_CLK DP_IG_DDC_DATA 60 MAKE_BASE=TRUE 60 MAKE_BASE=TRUE DP_AUX_CH_C_N R9300 60 BI DP_IG_DDC_DATA 33 5% 1/20W MF 201 BI 33 5% 1/20W MF 201 35 61 67 BI 35 61 67 C9300 0.1UF 67 DP_AUX_CH_SW_N 10% 6.3V X5R 201 R9301 DP_IG_DDC_CLK 60 BI DP_AUX_CH_C_P C9301 0.1UF 67 DP_AUX_CH_SW_P 10% 6.3V X5R 201 C Q9300 D SSM6N15FEAPE SOT563 S Q9300 C D SSM6N15FEAPE SOT563 G G S DP_IG_AUX_CH_P 67 17 BI 67 17 BI DP_IG_AUX_CH_N =PP5V_S0_DP_AUX_MUX R9306 1K 5% 1/20W MF 201 R9302 100K 5% 1/20W MF 201 DDC_CA_DET_LS5V_L B B Q9301 D SSM3K15FV SOD-VESM-HF S G DP_CA_DET 61 IN DP_IG_CA_DET OUT 17 DISPLAYPORT SUPPORT SYNC_MASTER=NMARTIN A SYNC_DATE=12/18/2007 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC SCALE SHT NONE REV 051-7631 2.3.0 OF 60 71 A 61 CRITICAL =PP3V3_S0_DPCONN U9450 C9451 TPS2051 MSOP 0.1UF 10% 6.3V X5R 201 D IN OUT IN OUT 56 IN =DPPWR_EN EN GND D OUT OC* THRML L9400 NC FERR-120-OHM-3A PAD 70 NO STUFF1 C9450 0603 DP_ESD CRITICAL 22UF 20% 6.3V X5R-CERM 603 70 35 PP3V3_S0_DPFUSE MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=3.3V PP3V3_S0_DPPWR MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=3.3V 0.01UF D9411 C9400 RCLAMP0524P 10% 10V X5R 201 DP_ESD CRITICAL SLP2510P8 D9410 IO IO NC R9420 SLP2510P8 GND NC RCLAMP0524P IO NC IO NC 5% 1/20W MF 201 67 60 IN DP_ML_P IN DP_ML_N C9410 0.1uF 67 60 C9411 0.1uF DP_ML_C_P 67 10% 6.3V X5R DP_ML_C_N 10% 6.3V X5R TCM1210-4SM SYM_VER-2 GND 100K FL9400 12-OHM-100MA FL9410 201 12-OHM-100MA TCM1210-4SM SYM_VER-2 FL9420 12-OHM-100MA C9414 DP_ML_P IN 10% DP_ML_C_P 10% DP_ML_C_N 0.1uF 67 60 C9415 DP_ML_N IN 0.1uF 6.3V X5R X5R TCM1210-4SM SYM_VER-2 DP_ML_F_P DP_ML_F_N BI 67 60 35 BI 35 67 201 DP_ML_F_P DP_ML_F_N 67 35 67 35 DP_ML_F_P 35 DP_ML_F_N 35 DP_CA_DET_Q DP_AUX_CH_C_P DP_AUX_CH_C_N DP_ML_C_N C9413 12-OHM-100MA TCM1210-4SM SYM_VER-2 67 DP_ML_C_P DP_ML_P 10% 6.3V DP_ML_N 10% 6.3V 10% DP_ML_P DP_ML_N 10% 6.3V C9416 67 67 35 DP_ML_F_P DP_ML_F_N HDMI_CEC 35 DP_HPD_Q 67 35 201 35 0.1uF 67 DP_ML_C_N C9417 0.1uF X5R X5R 201 201 IN 60 67 IN 60 67 IN 60 67 IN 60 67 C 6.3V X5R X5R 201 201 R9425 1M These nets connect to RIO connector @ J4200 R9440 R9421 100K 100K 5% 1/20W MF 201 5% 1/20W MF 201 R9441 DP_CA_DET DP_ESD CRITICAL DP_ESD CRITICAL D9410 D9411 RCLAMP0524P RCLAMP0524P SLP2510P8 SLP2510P8 5% 1/20W MF 201 100K Q9440 5% 1/20W MF 201 D 2N7002DW-X-G Q9440 must have Drain to Gate leakage of 5MOhm B GND OUT RCLAMP0504F (DP_CA_DET_Q) SC70-6-1 B R9422 1M 5% 1/20W MF 201 61 FL9430 =PP3V3_S0_DPCONN 60 0.1uF 35 67 67 35 67 60 35 C9412 GND 61 6.3V DP_ML_C_P 0.1uF C 67 60 201 2 DP to DVI/HDMI Cable Adapter (CA) has 100k pullup to DP_PWR =PP3V3_S0_DPCONN R94451 10K 5% 1/20W MF 201 60 OUT R94441 DP_HPD 10K 5% 1/20W MF 201 R94461 100K 1% 1/20W MF 201 Q9441 D 2N7002DW-X-G SOT-363 S A MCP requires pull down HPD input with 100K if DP_HPD is used G 2DP_HPD_DET_L DisplayPort Connector D Q9441 S SOT-363 SYNC_MASTER=M98_MLB 2N7002DW-X-G G (DP_HPD_Q) R94231 100K 1% 1/20W MF 201 SYNC_DATE=01/17/2008 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING DP Source must pull down HPD input with greater than or equal to 100K (DPv1.1a) I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC SCALE SHT NONE REV 051-7631 2.3.0 OF 61 71 A LED Backlight Driver D D CRITICAL CRITICAL L9750 70 63 D9750 22UH-1.7A PPBUS_S0_LCDBKLT_PWR =PP3V3_S0_LCDBKLT 63 17 24 IN LVDS_IG_BKL_ON IN BKLT_PLT_RST_L C9740 U9740Y 63 LCDBKLT_ENA NO STUFF R9740 1 10K C9741 1 0.1UF 100K C9751 1UF 10% 16V X5R 402 5% 1/20W MF 201 10% 6.3V X5R 201 C9750 10UF 10% 25V X5R 603-1 10% 25V X5R 1206-1 U9750 C LCDBKLT_ENA_RC f=500KHz C9756 C9757 4.7UF 4.7UF 4.7UF 10% 50V X7R-CERM 1206 10% 50V X7R-CERM 1206 10% 50V X7R-CERM 1206 2 C9758 4.7UF 10% 50V X7R-CERM 1206 QFN ENA R97551 1M 1% 1/20W MF 201 SW 18 >2V = ON, 50 mils preferred ? TABLE_SPACING_RULE_ITEM CPU_ITP * =2:1_SPACING ? CPU_VCCSENSE * 25 MIL ? TABLE_SPACING_RULE_ITEM Most CPU signals with impedance requirements are 55-ohm single-ended Some signals require 27.4-ohm single-ended impedance SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2 SOURCE: Santa Rosa Platform DG, Rev 0.9 (#20517), Sections 4.4 & 5.8.2.4 MCP FSB COMP Signal Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MCP_50S * =50_OHM_SE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD TABLE_PHYSICAL_RULE_ITEM B TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM MCP_FSB_COMP * MIL ? SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2.4 FSB Clock Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM CLK_FSB * =3x_DIELECTRIC TABLE_SPACING_RULE_ITEM ? CLK_FSB TOP,BOTTOM =4x_DIELECTRIC FSB_D_L FSB_DINV_L FSB_DSTB_L_P FSB_DSTB_L_N FSB_D_L FSB_DINV_L FSB_DSTB_L_P FSB_DSTB_L_N FSB_A_L FSB_REQ_L FSB_ADSTB_L FSB_A_L FSB_ADSTB_L FSB_ADS_L FSB_BREQ0_L FSB_BREQ1_L FSB_BNR_L FSB_BPRI_L FSB_DBSY_L FSB_DEFER_L FSB_DRDY_L FSB_HIT_L FSB_HITM_L FSB_LOCK_L FSB_CPURST_L FSB_RS_L FSB_TRDY_L CPU_A20M_L CPU_BSEL CPU_FERR_L CPU_IGNNE_L CPU_INIT_L CPU_INTR CPU_NMI CPU_PROCHOT_L CPU_PWRGD CPU_SMI_L CPU_STPCLK_L PM_THRMTRIP_L FSB_CPUSLP_L CPU_DPSLP_L CPU_DPRSTP_L FSB_DPWR_L MCP_BCLK_VML_COMP_VDD MCP_BCLK_VML_COMP_GND MCP_CPU_COMP_VCC MCP_CPU_COMP_GND FSB_CLK_CPU_P FSB_CLK_CPU_N FSB_CLK_ITP_P FSB_CLK_ITP_N FSB_CLK_MCP_P FSB_CLK_MCP_N CPU_IERR_L =100_OHM_DIFF TABLE_SPACING_RULE_HEAD SPACING_RULE_SET FSB_D_L FSB_DINV_L FSB_DSTB_L_P FSB_DSTB_L_N 13 13 13 13 13 13 13 D 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 C 13 12 13 13 13 13 9 13 13 13 13 13 13 40 50 12 13 13 13 13 40 13 13 13 50 13 13 13 13 13 13 13 B 12 13 12 13 13 13 PM_DPRSLPVR IMVP_DPRSLPVR 20 50 50 DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM CLK_FSB_100D FSB_D_L FSB_DINV_L FSB_DSTB_L_P FSB_DSTB_L_N CPU_GTLREF CPU_COMP CPU_COMP CPU_COMP CPU_COMP 25 9 9 ? SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2.5 CPU_VCCSENSE A CPU_VCCSENSE CPU_27P4S CPU_VCCSENSE (CPU_VCCSENSE) (CPU_VCCSENSE) CPU_27P4S CPU_VCCSENSE CPU_27P4S CPU_VCCSENSE XDP_TDI XDP_TDO XDP_TMS XDP_TCK XDP_TRST_L XDP_BPM_L XDP_BPM_L XDP_CPURST_L CPU_VID IMVP6_VID CPU_VCCSENSE_P CPU_VCCSENSE_N IMVP6_VSEN_P IMVP6_VSEN_N 12 12 12 12 12 12 12 12 10 11 50 CPU/FSB Constraints 11 10 50 SYNC_MASTER=M97 SYNC_DATE=02/04/2008 10 50 NOTICE OF PROPRIETARY PROPERTY 50 50 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC SCALE SHT NONE REV 051-7631 2.3.0 OF 65 71 A Memory Bus Constraints Memory Net Properties TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP MEM_50S * =50_OHM_SE =50_OHM_SE 0.110 MM =50_OHM_SE =STANDARD =STANDARD NET_TYPE TABLE_PHYSICAL_RULE_ITEM ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING TABLE_PHYSICAL_RULE_ITEM MEM_50S_VDD * =50_OHM_SE =50_OHM_SE 0.110 MM =50_OHM_SE =STANDARD =STANDARD MEM_90D * =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF MEM_90D_VDD * =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM MEM_A_CLK MEM_90D MEM_CLK MEM_A_CLK MEM_90D MEM_CLK MEM_A_CNTL MEM_50S MEM_CTRL MEM_A_CNTL MEM_50S MEM_CTRL MEM_A_CNTL MEM_50S MEM_CTRL MEM_A_CMD MEM_50S MEM_CMD MEM_A_CMD MEM_50S MEM_CMD MEM_A_CMD MEM_50S MEM_CMD MEM_A_CMD MEM_50S MEM_CMD MEM_A_CMD MEM_50S MEM_CMD MEM_A_DQ_BYTE0 MEM_50S MEM_DATA MEM_A_CLK_P MEM_A_CLK_N 14 27 28 33 14 27 28 33 MEM_A_CKE MEM_A_CS_L MEM_A_ODT 14 27 28 33 14 27 28 33 14 27 28 33 TABLE_SPACING_RULE_HEAD SPACING_RULE_SET D LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM MEM_CLK2MEM * =2.28:1_SPACING ? TABLE_SPACING_RULE_ITEM MEM_CTRL2CTRL * =1.1:1_SPACING ? TABLE_SPACING_RULE_ITEM MEM_CTRL2MEM * =2.28:1_SPACING ? MEM_CMD2CMD * =1.1:1_SPACING ? MEM_CMD2MEM * =2.28:1_SPACING ? MEM_A_A MEM_A_BA MEM_A_RAS_L MEM_A_CAS_L MEM_A_WE_L 14 27 28 33 D 14 27 28 33 14 27 28 33 14 27 28 33 14 27 28 33 TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM MEM_A_DQ_BYTE1 MEM_50S MEM_DATA MEM_A_DQ_BYTE2 MEM_50S MEM_DATA MEM_A_DQ_BYTE3 MEM_50S MEM_DATA MEM_A_DQ_BYTE4 MEM_50S MEM_DATA MEM_A_DQ_BYTE5 MEM_50S MEM_DATA MEM_A_DQ_BYTE6 MEM_50S MEM_DATA MEM_A_DQ_BYTE7 MEM_50S MEM_DATA MEM_A_DQ_BYTE0 MEM_50S MEM_DATA MEM_A_DQ_BYTE1 MEM_50S MEM_DATA MEM_A_DQ_BYTE2 MEM_50S MEM_DATA MEM_A_DQ_BYTE3 MEM_50S MEM_DATA MEM_A_DQ_BYTE4 MEM_50S MEM_DATA MEM_A_DQ_BYTE5 MEM_50S MEM_DATA MEM_A_DQ_BYTE6 MEM_50S MEM_DATA MEM_A_DQ_BYTE7 MEM_50S MEM_DATA MEM_A_DQS0 MEM_90D MEM_DQS MEM_A_DQS0 MEM_90D MEM_DQS MEM_A_DQS1 MEM_90D MEM_DQS MEM_A_DQS1 MEM_90D MEM_DQS MEM_A_DQS2 MEM_90D MEM_DQS MEM_A_DQS2 MEM_90D MEM_DQS MEM_A_DQS3 MEM_90D MEM_DQS MEM_A_DQS3 MEM_90D MEM_DQS MEM_A_DQS4 MEM_90D MEM_DQS MEM_A_DQS4 MEM_90D MEM_DQS MEM_A_DQS5 MEM_90D MEM_DQS MEM_A_DQS5 MEM_90D MEM_DQS MEM_A_DQS6 MEM_90D MEM_DQS MEM_A_DQS6 MEM_90D MEM_DQS MEM_A_DQS7 MEM_90D MEM_DQS MEM_A_DQS7 MEM_90D MEM_DQS MEM_B_CLK MEM_90D MEM_CLK MEM_B_CLK MEM_90D MEM_CLK MEM_B_CNTL MEM_50S MEM_CTRL MEM_B_CNTL MEM_50S MEM_CTRL MEM_B_CNTL MEM_50S MEM_CTRL MEM_B_CMD MEM_50S MEM_CMD MEM_B_CMD MEM_50S MEM_CMD MEM_B_CMD MEM_50S MEM_CMD MEM_B_CMD MEM_50S MEM_CMD MEM_B_CMD MEM_50S MEM_CMD MEM_B_DQ_BYTE0 MEM_50S MEM_DATA MEM_B_DQ_BYTE1 MEM_50S MEM_DATA MEM_B_DQ_BYTE2 MEM_50S MEM_DATA MEM_B_DQ_BYTE3 MEM_50S MEM_DATA MEM_B_DQ_BYTE4 MEM_50S MEM_DATA MEM_B_DQ_BYTE5 MEM_50S MEM_DATA MEM_B_DQ_BYTE6 MEM_50S MEM_DATA MEM_B_DQ_BYTE7 MEM_50S MEM_DATA MEM_B_DQ_BYTE0 MEM_50S MEM_DATA MEM_B_DQ_BYTE1 MEM_50S MEM_DATA MEM_B_DQ_BYTE2 MEM_50S MEM_DATA MEM_B_DQ_BYTE3 MEM_50S MEM_DATA MEM_B_DQ_BYTE4 MEM_50S MEM_DATA MEM_B_DQ_BYTE5 MEM_50S MEM_DATA MEM_B_DQ_BYTE6 MEM_50S MEM_DATA MEM_B_DQ_BYTE7 MEM_50S MEM_DATA MEM_B_DQS0 MEM_90D MEM_DQS MEM_B_DQS0 MEM_90D MEM_DQS TABLE_SPACING_RULE_ITEM MEM_DATA2DATA * =1.1:1_SPACING ? TABLE_SPACING_RULE_ITEM MEM_DATA2MEM * =2.28:1_SPACING ? TABLE_SPACING_RULE_ITEM MEM_DQS2MEM * =2.28:1_SPACING ? TABLE_SPACING_RULE_ITEM MEM_2OTHER * 25 MIL TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE2 AREA_TYPE TABLE_SPACING_ASSIGNMENT_HEAD SPACING_RULE_SET NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET TABLE_SPACING_ASSIGNMENT_ITEM MEM_CLK MEM_CLK * TABLE_SPACING_ASSIGNMENT_ITEM MEM_CLK2MEM MEM_CMD MEM_CLK * MEM_CMD2MEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CLK MEM_CTRL * TABLE_SPACING_ASSIGNMENT_ITEM MEM_CLK2MEM MEM_CMD MEM_CTRL * MEM_CMD2MEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CLK MEM_CMD * TABLE_SPACING_ASSIGNMENT_ITEM MEM_CLK2MEM MEM_CMD MEM_CMD * MEM_CLK MEM_DATA * MEM_CLK2MEM MEM_CLK MEM_DQS * MEM_CLK2MEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CMD MEM_DATA * MEM_CMD2MEM MEM_CMD MEM_DQS * MEM_CMD2MEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET MEM_CTRL MEM_CLK * MEM_CTRL2MEM TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET MEM_DATA MEM_CLK * MEM_DATA2MEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CTRL MEM_CTRL * MEM_CTRL2CTRL MEM_CTRL MEM_CMD * MEM_CTRL2MEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_DATA MEM_CTRL * MEM_DATA2MEM MEM_DATA MEM_CMD * MEM_DATA2MEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CTRL MEM_DATA * TABLE_SPACING_ASSIGNMENT_ITEM MEM_CTRL2MEM MEM_DATA MEM_DATA * MEM_DATA2DATA TABLE_SPACING_ASSIGNMENT_ITEM MEM_CTRL MEM_DQS * TABLE_SPACING_ASSIGNMENT_ITEM MEM_CTRL2MEM MEM_DATA MEM_DQS * MEM_DATA2MEM TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET MEM_DQS MEM_CLK * MEM_DQS2MEM TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET MEM_CLK * * MEM_2OTHER TABLE_SPACING_ASSIGNMENT_ITEM MEM_CTRL * TABLE_SPACING_ASSIGNMENT_ITEM MEM_DQS2MEM MEM_CTRL * * MEM_2OTHER TABLE_SPACING_ASSIGNMENT_ITEM MEM_DQS MEM_CMD * MEM_DQS2MEM MEM_DQS MEM_DATA * MEM_DQS2MEM MEM_CMD * * MEM_2OTHER MEM_DATA * * MEM_2OTHER TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_DQS * NET_SPACING_TYPE2 MEM_DQS2MEM AREA_TYPE MEM_DQS * * MEM_2OTHER TABLE_SPACING_ASSIGNMENT_HEAD SPACING_RULE_SET NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET TABLE_SPACING_ASSIGNMENT_ITEM MEM_CLK GND * TABLE_SPACING_ASSIGNMENT_ITEM GND_P2MM MEM_CLK PWR * BUS2PWR_GND TABLE_SPACING_ASSIGNMENT_ITEM MEM_CMD GND * GND MEM_CLK GND * BUS2PWR_GND * TABLE_SPACING_ASSIGNMENT_ITEM GND_P2MM MEM_CTRL PWR * BUS2PWR_GND TABLE_SPACING_ASSIGNMENT_ITEM B MEM_DATA GND * TABLE_SPACING_ASSIGNMENT_ITEM GND_P2MM MEM_CTRL GND * BUS2PWR_GND TABLE_SPACING_ASSIGNMENT_ITEM MEM_DQS GND * TABLE_SPACING_ASSIGNMENT_ITEM GND_P2MM MEM_CMD PWR * BUS2PWR_GND TABLE_SPACING_ASSIGNMENT_ITEM MEM_CLK PP1V5_MEM * PWR_P2MM MEM_CTRL PP1V5_MEM * PWR_P2MM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CMD GND * BUS2PWR_GND MEM_DATA PWR * BUS2PWR_GND TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_DATA PP1V5_MEM * PWR_P2MM MEM_DQS PP1V5_MEM * PWR_P2MM MEM_DATA GND * BUS2PWR_GND MEM_DQS PWR * BUS2PWR_GND TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM PP1V5_MEM * TABLE_SPACING_ASSIGNMENT_ITEM PWR_P2MM MEM_DQS GND * BUS2PWR_GND DDR3: MEM_B_DQS1 MEM_90D MEM_DQS MEM_B_DQS1 MEM_90D MEM_DQS MEM_B_DQS2 MEM_90D MEM_DQS MEM_B_DQS2 MEM_90D MEM_DQS MEM_B_DQS3 MEM_90D MEM_DQS MEM_B_DQS3 MEM_90D MEM_DQS MEM_B_DQS4 MEM_90D MEM_DQS MEM_B_DQS4 MEM_90D MEM_DQS MEM_B_DQS5 MEM_90D MEM_DQS MEM_B_DQS5 MEM_90D MEM_DQS DQ signals should be matched within ps of associated DQS pair DQS intra-pair matching should be within ps, inter-pair matching shoulw be within 180 ps No DQS to clock matching requirement CLK intra-pair matching should be within ps, inter-pair matching should be within ps A/BA/cmd signals should be matched within ps of CLK pairs All memory signals maximum length is 1.005 ps CLK minimum length is 594 ps (lengths include substrate) DQ/A/BA/cmd signal spacing is 3x dielectric, DQS/CLK is 4x dielectric A 14 28 14 28 MEM_A_DM MEM_A_DM MEM_A_DM MEM_A_DM MEM_A_DM MEM_A_DM MEM_A_DM MEM_A_DM 14 27 14 27 14 27 14 27 14 28 14 28 14 28 14 28 MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N 14 27 14 27 14 27 14 27 14 27 C 14 27 14 27 14 27 14 28 14 28 14 28 14 28 14 28 14 28 14 28 14 28 MEM_B_CLK_P MEM_B_CLK_N 14 29 30 33 14 29 30 33 MEM_B_CKE MEM_B_CS_L MEM_B_ODT 14 29 30 33 14 29 30 33 14 29 30 33 MEM_B_A MEM_B_BA MEM_B_RAS_L MEM_B_CAS_L MEM_B_WE_L 14 29 30 33 14 29 30 33 14 29 30 33 14 29 30 33 14 29 30 33 MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ 14 29 14 29 14 29 B 14 29 14 30 14 30 14 30 14 30 TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CMD 14 28 TABLE_SPACING_ASSIGNMENT_ITEM GND_P2MM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CTRL 14 28 TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 14 27 TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_DQS 14 27 TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_DQS 14 27 MEM_CMD2CMD TABLE_SPACING_ASSIGNMENT_ITEM C 14 27 ? Memory Bus Spacing Group Assignments NET_SPACING_TYPE1 MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.3 MEM_B_DQS6 MEM_90D MEM_DQS SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Section 6.2 MEM_B_DQS6 MEM_90D MEM_DQS MEM_B_DQS7 MEM_90D MEM_DQS MCP MEM COMP Signal Constraints MEM_B_DQS7 MEM_90D MEM_DQS MCP_MEM_COMP MCP_MEM_COMP MCP_MEM_COMP MEM_B_DM MEM_B_DM MEM_B_DM MEM_B_DM MEM_B_DM MEM_B_DM MEM_B_DM MEM_B_DM 14 29 14 29 14 29 14 29 14 30 14 30 14 30 14 30 MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N 14 29 14 29 14 29 14 29 14 29 14 29 14 29 14 29 14 30 14 30 Memory Constraints 14 30 14 30 SYNC_MASTER=M97 SYNC_DATE=02/04/2008 14 30 NOTICE OF PROPRIETARY PROPERTY 14 30 14 30 14 30 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH Y MIL MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM MCP_MEM_COMP * MIL =STANDARD =STANDARD MCP_MEM_COMP MCP_MEM_COMP MCP_MEM_COMP MCP_MEM_COMP_VDD MCP_MEM_COMP_GND =STANDARD 15 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE VOLTAGE=0V 15 II NOT TO REPRODUCE OR COPY IT VOLTAGE=1.5V MEM_CLK MEM_RESET_L 30 26 27 28 29 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT MIL ? =PP1V8R1V5_S0_MCP_MEM NET_SPACING_TYPE=PP1V5_MEM GND NET_SPACING_TYPE=GND 22 15 * DRAWING NUMBER D TABLE_SPACING_RULE_ITEM MCP_MEM_COMP APPLE INC SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.3.4 SCALE SHT NONE REV 051-7631 2.3.0 OF 66 71 A NET_TYPE PCI-Express ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP PCIE_90D * =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF PCIE_90D PCIE PCIE_90D PCIE PCIE_90D PCIE PCIE_90D PCIE PCIE_90D PCIE PCIE_90D PCIE PCIE_90D PCIE PCIE_90D PCIE PCIE_90D PCIE PCIE_90D PCIE PCIE_90D PCIE PCIE_90D PCIE PCIE_90D PCIE PCIE_90D PCIE PCIE_90D PCIE PCIE_90D PCIE PCIE_90D PCIE PCIE_90D PCIE PCIE_90D PCIE PCIE_90D PCIE PCIE_90D PCIE PCIE_90D PCIE PCIE_90D PCIE PCIE_90D PCIE PCIE_90D PCIE PCIE_90D PCIE PCIE_90D PCIE PCIE_90D PCIE PCIE_90D PCIE PCIE_90D PCIE PCIE_90D PCIE PCIE_90D PCIE PCIE_FC_D2R PCIE_90D PCIE PCIE_90D PCIE MCP_PE0_REFCLK CLK_PCIE_100D CLK_PCIE CLK_PCIE_100D CLK_PCIE CLK_PCIE_100D CLK_PCIE CLK_PCIE_100D CLK_PCIE CLK_PCIE_100D CLK_PCIE CLK_PCIE_100D CLK_PCIE CLK_PCIE_100D CLK_PCIE CLK_PCIE_100D CLK_PCIE CLK_PCIE_100D CLK_PCIE TABLE_PHYSICAL_RULE_ITEM PEG_R2D TABLE_PHYSICAL_RULE_ITEM CLK_PCIE_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF PEG_D2R TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING TABLE_SPACING_RULE_HEAD WEIGHT SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM PCIE * =3X_DIELECTRIC TABLE_SPACING_RULE_ITEM ? PCIE TOP,BOTTOM =4X_DIELECTRIC ? TABLE_SPACING_RULE_ITEM CLK_PCIE D * 20 MIL ? TABLE_SPACING_RULE_ITEM MCP_PEX_COMP * MIL ? PCIE_MINI_R2D SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.4 PCIE_MINI_D2R Analog Video Signal Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? CRT_50S * =50_OHM_SE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD TABLE_PHYSICAL_RULE_ITEM PCIE_FW_R2D PCIE_FW_D2R TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM CRT * =4:1_SPACING ? TABLE_SPACING_RULE_ITEM CRT_2CRT * =STANDARD ? TABLE_SPACING_RULE_ITEM CRT_2CLK * 50 MIL ? PCIE_EXCARD_R2D TABLE_SPACING_RULE_ITEM CRT_2SWITCHER * 250 MIL ? TABLE_SPACING_RULE_ITEM CRT_SYNC * 16 MIL PCIE_EXCARD_D2R ? TABLE_SPACING_RULE_ITEM MCP_DAC_COMP * =2:1_SPACING ? CRT signal single-ended impedence varies by location: - 37.5-ohm from MCP to first termination resistor - 50-ohm from first to second termination resistor - 75-ohm from output of three-pole filter to connector (if possible) R/G/B signals should be matched as close as possible and < 10 inches SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Sections 2.5.1 & 2.5.2 C PCIE_FC_R2D MCP_PE1_REFCLK Digital Video Signal Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP MCP_PE4_REFCLK TABLE_PHYSICAL_RULE_ITEM DP_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF LVDS_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF MCP_PE2_REFCLK TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM MCP_DV_COMP * 20 MIL Y 20 MIL =STANDARD =STANDARD MCP_PE3_REFCLK =STANDARD CLK_PCIE_100D CLK_PCIE TMDS_IG_TXC DP_100D DISPLAYPORT TMDS_IG_TXC DP_100D DISPLAYPORT TMDS_IG_TXD DP_100D DISPLAYPORT TMDS_IG_TXD DP_100D DISPLAYPORT DP_ML DP_100D DISPLAYPORT DP_ML DP_100D DISPLAYPORT DP_ML DP_100D DISPLAYPORT DP_ML DP_100D DISPLAYPORT DP_ML DP_100D DISPLAYPORT DP_ML DP_100D DISPLAYPORT DP_AUX_CH DP_100D DISPLAYPORT DP_AUX_CH DP_100D DISPLAYPORT DP_AUX_CH DP_100D DISPLAYPORT DP_AUX_CH DP_100D DISPLAYPORT DP_AUX_CH DP_100D DISPLAYPORT DP_AUX_CH DP_100D DISPLAYPORT MCP_HDMI_RSET MCP_DV_COMP MCP_HDMI_VPROBE MCP_DV_COMP LVDS_IG_A_CLK LVDS_100D LVDS LVDS_IG_A_CLK LVDS_100D LVDS LVDS_IG_A_CLK LVDS_100D LVDS LVDS_IG_A_CLK LVDS_100D LVDS LVDS_IG_A_DATA LVDS_100D LVDS LVDS_IG_A_DATA LVDS_100D LVDS LVDS_IG_A_DATA LVDS_100D LVDS LVDS_IG_A_DATA LVDS_100D LVDS LVDS_IG_A_DATA3 LVDS_100D LVDS LVDS_IG_A_DATA3 LVDS_100D LVDS LVDS_IG_B_CLK LVDS_100D LVDS LVDS_IG_B_CLK LVDS_100D LVDS LVDS_IG_B_DATA LVDS_100D LVDS LVDS_IG_B_DATA LVDS_100D LVDS LVDS_IG_B_DATA3 LVDS_100D LVDS LVDS_IG_B_DATA3 LVDS_100D LVDS MCP_IFPAB_RSET MCP_DV_COMP MCP_PEX_CLK_COMP TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM DISPLAYPORT * =3x_DIELECTRIC ? LVDS * =3x_DIELECTRIC ? MCP_PEX_COMP TABLE_SPACING_RULE_HEAD WEIGHT TABLE_SPACING_RULE_ITEM DISPLAYPORT TOP,BOTTOM =4x_DIELECTRIC ? LVDS TOP,BOTTOM =4x_DIELECTRIC ? TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM LVDS intra-pair matching should be mils Pairs should be within 100 mils of clock length DisplayPort/TMDS intra-pair matching should be ps Inter-pair matching should be within 150 ps DIsplayPort AUX CH intra-pair matching should be ps No relationship to other signals Max length of LVDS/DisplayPort/TMDS traces: 12 inches SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Sections 2.5.3 & 2.5.4 SATA Interface Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP SATA_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM SATA_100D_HDD * =100_OHM_DIFF_HDD =100_OHM_DIFF_HDD =100_OHM_DIFF_HDD =100_OHM_DIFF_HDD =100_OHM_DIFF_HDD =100_OHM_DIFF_HDD TABLE_SPACING_RULE_HEAD B SPACING_RULE_SET LAYER LINE-TO-LINE SPACING TABLE_SPACING_RULE_HEAD WEIGHT SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM SATA * =4x_DIELECTRIC TABLE_SPACING_RULE_ITEM ? SATA TOP,BOTTOM =3x_DIELECTRIC ? TABLE_SPACING_RULE_ITEM SATA_TERMP * MIL ? SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.7.1 A SATA_HDD_D2R MCP_SATA_TERMP DP_ML_C_P DP_ML_C_N DP_ML_F_P DP_ML_F_N DP_ML_P DP_ML_N DP_IG_AUX_CH_P DP_IG_AUX_CH_N DP_AUX_CH_C_P DP_AUX_CH_C_N DP_AUX_CH_SW_P DP_AUX_CH_SW_N MCP_HDMI_RSET MCP_HDMI_VPROBE LVDS_IG_A_CLK_F_P LVDS_IG_A_CLK_F_N LVDS_IG_A_CLK_P LVDS_IG_A_CLK_N LVDS_IG_A_DATA_F_P LVDS_IG_A_DATA_F_N LVDS_IG_A_DATA_P LVDS_IG_A_DATA_N LVDS_IG_A_DATA_P LVDS_IG_A_DATA_N LVDS_IG_B_CLK_P LVDS_IG_B_CLK_N LVDS_IG_B_DATA_P LVDS_IG_B_DATA_N LVDS_IG_B_DATA_P LVDS_IG_B_DATA_N MCP_IFPAB_RSET MCP_IFPAB_VPROBE MCP_IFPAB_VPROBE SATA_HDD_R2D PEG_R2D_P PEG_R2D_N PEG_R2D_C_P PEG_R2D_C_N PEG_D2R_P PEG_D2R_N PEG_D2R_C_P PEG_D2R_C_N PCIE_MINI_R2D_P PCIE_MINI_R2D_N PCIE_MINI_R2D_C_P PCIE_MINI_R2D_C_N PCIE_MINI_D2R_P PCIE_MINI_D2R_N PCIE_FW_R2D_P PCIE_FW_R2D_N PCIE_FW_R2D_C_P PCIE_FW_R2D_C_N PCIE_FW_D2R_P PCIE_FW_D2R_N PCIE_FW_D2R_C_P PCIE_FW_D2R_C_N PCIE_EXCARD_R2D_P PCIE_EXCARD_R2D_N PCIE_EXCARD_R2D_C_P PCIE_EXCARD_R2D_C_N PCIE_EXCARD_D2R_P PCIE_EXCARD_D2R_N PCIE_FC_R2D_P PCIE_FC_R2D_N PCIE_FC_R2D_C_P PCIE_FC_R2D_C_N PCIE_FC_D2R_P PCIE_FC_D2R_N PEG_CLK100M_P PEG_CLK100M_N PCIE_CLK100M_MINI_P PCIE_CLK100M_MINI_N PCIE_CLK100M_FC_P PCIE_CLK100M_FC_N PCIE_CLK100M_FW_P PCIE_CLK100M_FW_N PCIE_CLK100M_EXCARD_P PCIE_CLK100M_EXCARD_N MCP_PEX_CLK_COMP TMDS_IG_TXC_P TMDS_IG_TXC_N TMDS_IG_TXD_P TMDS_IG_TXD_N SATA_100D_HDD SATA SATA_100D_HDD SATA SATA_100D_HDD SATA SATA_100D_HDD SATA SATA_100D_HDD SATA SATA_100D_HDD SATA SATA_100D_HDD SATA SATA_100D_HDD SATA SATA_100D_HDD SATA SATA_100D_HDD SATA SATA_100D_HDD SATA SATA_100D_HDD SATA SATA_TERMP SATA_HDD_R2D_C_P SATA_HDD_R2D_C_N SATA_HDD_R2D_P SATA_HDD_R2D_N SATA_HDD_R2D_UF_P SATA_HDD_R2D_UF_N SATA_HDD_D2R_P SATA_HDD_D2R_N SATA_HDD_D2R_C_P SATA_HDD_D2R_C_N SATA_HDD_D2R_UF_P SATA_HDD_D2R_UF_N MCP_SATA_TERMP D 16 34 16 34 16 34 16 34 16 16 C 16 34 16 34 16 61 61 35 61 35 61 60 61 60 61 17 60 17 60 35 60 61 35 60 61 60 60 17 23 B 17 23 59 59 17 59 17 59 59 59 17 59 17 59 17 17 17 17 17 17 17 17 17 23 17 23 19 36 19 36 36 MCP Constraints 36 36 SYNC_MASTER=M97 36 19 36 SYNC_DATE=02/04/2008 NOTICE OF PROPRIETARY PROPERTY 19 36 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING 36 36 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE 36 II NOT TO REPRODUCE OR COPY IT 36 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART 19 SIZE DRAWING NUMBER D APPLE INC SCALE SHT NONE REV 051-7631 2.3.0 OF 67 71 A PCI Bus Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP PCI_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD NET_TYPE ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING TABLE_PHYSICAL_RULE_ITEM MCP_DEBUG PCI_55S PCI PCI_AD PCI_55S PCI PCI_AD24 PCI_55S PCI PCI_AD PCI_55S PCI PCI_AD PCI_55S PCI PCI_C_BE_L PCI_55S PCI PCI_CNTL PCI_55S PCI PCI_CNTL PCI_55S PCI PCI_CNTL PCI_55S PCI PCI_CNTL PCI_55S PCI PCI_CNTL PCI_55S PCI PCI_CNTL PCI_55S PCI PCI_CNTL PCI_55S PCI PCI_REQ0_L PCI_55S PCI PCI_GNT0_L PCI_55S PCI PCI_REQ1_L PCI_55S PCI PCI_GNT1_L PCI_55S PCI PCI_INTW_L PCI_55S PCI PCI_INTX_L PCI_55S PCI PCI_INTY_L PCI_55S PCI PCI_INTZ_L PCI_55S PCI MCP_PCI_CLK2 CLK_PCI_55S CLK_PCI CLK_PCI_55S CLK_PCI LPC_AD LPC_55S LPC LPC_FRAME_L LPC_55S LPC LPC_RESET_L LPC_55S LPC MCP_LPC_CLK0 CLK_LPC_55S CLK_LPC CLK_LPC_55S CLK_LPC CLK_LPC_55S CLK_LPC USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB TABLE_PHYSICAL_RULE_ITEM CLK_PCI_55S * SPACING_RULE_SET LAYER =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD TABLE_SPACING_RULE_HEAD LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM PCI * =STANDARD ? TABLE_SPACING_RULE_ITEM CLK_PCI D * MIL ? SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.8 LPC Bus Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM LPC_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD TABLE_PHYSICAL_RULE_ITEM CLK_LPC_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT MIL ? TABLE_SPACING_RULE_ITEM LPC * TABLE_SPACING_RULE_ITEM CLK_LPC * MIL USB 2.0 Interface Constraints TABLE_PHYSICAL_RULE_HEAD LAYER ALLOW ROUTE ON LAYER? 12 18 D 18 18 ? SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.9.1 PHYSICAL_RULE_SET MCP_DEBUG PCI_AD PCI_AD PCI_AD PCI_PAR PCI_C_BE_L PCI_IRDY_L PCI_DEVSEL_L PCI_PERR_L PCI_SERR_L PCI_STOP_L PCI_TRDY_L PCI_FRAME_L PCI_REQ0_L PCI_GNT0_L PCI_REQ1_L PCI_GNT1_L PCI_INTW_L PCI_INTX_L PCI_INTY_L PCI_INTZ_L MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP PCI_CLK33M_MCP_R PCI_CLK33M_MCP LPC_AD LPC_FRAME_L LPC_RESET_L 18 18 18 39 41 18 39 41 18 24 TABLE_PHYSICAL_RULE_ITEM MCP_USB_RBIAS * =STANDARD MIL MIL =STANDARD =STANDARD =STANDARD USB_90D * =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT =2x_DIELECTRIC ? TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT =4x_DIELECTRIC ? TABLE_SPACING_RULE_ITEM USB C * USB_EXTA TABLE_SPACING_RULE_ITEM USB TOP,BOTTOM SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.10.1 SMBus Interface Constraints USB_MINI TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH =55_OHM_SE =55_OHM_SE MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP USB_EXTD TABLE_PHYSICAL_RULE_ITEM SMB_55S * =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD USB_CAMERA TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM SMB * =2x_DIELECTRIC ? USB_BT SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.11.1 HD Audio Interface Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP USB_TPAD DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM HDA_55S * SPACING_RULE_SET LAYER =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD TABLE_SPACING_RULE_HEAD LINE-TO-LINE SPACING USB_IR WEIGHT TABLE_SPACING_RULE_ITEM HDA * =2x_DIELECTRIC ? USB_EXTB TABLE_SPACING_RULE_ITEM * MCP_HDA_COMP ? MIL SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.12.1 USB_EXCARD B SIO Signal Constraints USB_EXTC TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP LPC_CLK33M_SMC_R LPC_CLK33M_SMC LPC_CLK33M_LPCPLUS USB_EXTA_P USB_EXTA_N USB_EXTA_MUXED_P USB_EXTA_MUXED_N CONN_USB_EXTA_P CONN_USB_EXTA_N USB_MINI_P USB_MINI_N USB_EXTD_P USB_EXTD_N USB_CAMERA_P USB_CAMERA_N USB_CAMERA_CONN_P USB_CAMERA_CONN_N USB_BT_P USB_BT_N CONN_USB2_BT_P CONN_USB2_BT_N USB_TPAD_P USB_TPAD_N CONN_TPAD_USB_P CONN_TPAD_USB_N USB_IR_P USB_IR_N USB_EXTB_P USB_EXTB_N CONN_USB_EXTB_P CONN_USB_EXTB_N USB_EXCARD_P USB_EXCARD_N USB_EXTC_P USB_EXTC_N 18 24 24 39 24 41 19 19 37 C 37 19 19 19 19 19 19 19 19 19 19 19 19 19 19 8 B 8 TABLE_PHYSICAL_RULE_ITEM CLK_SLOW_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD MCP_USB_RBIAS_GND MCP_USB_RBIAS MCP_USB_RBIAS SMBUS_MCP_0_CLK SMB_55S SMB SMBUS_MCP_0_DATA SMB_55S SMB SMBUS_MCP_1_CLK SMB_55S SMB SMBUS_MCP_1_DATA SMB_55S SMB SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.13 HDA_BIT_CLK HDA_55S HDA HDA_55S HDA SPI Interface Constraints HDA_SYNC HDA_55S HDA HDA_55S HDA HDA_55S HDA HDA_55S HDA HDA_55S HDA HDA_55S HDA HDA_55S HDA HDA_55S HDA HDA_BIT_CLK HDA_BIT_CLK_R HDA_SYNC HDA_SYNC_R HDA_RST_R_L HDA_RST_L HDA_SDIN0 HDA_SDIN_CODEC HDA_SDOUT HDA_SDOUT_R MCP_HDA_COMP MCP_HDA_PULLDN_COMP CLK_SLOW_55S CLK_SLOW CLK_SLOW_55S CLK_SLOW PM_CLK32K_SUSCLK_R PM_CLK32K_SUSCLK SPI_55S SPI SPI_55S SPI SPI_55S SPI SPI_55S SPI SPI_55S SPI SPI_55S SPI TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM CLK_SLOW * MIL ? TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP SPI_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD HDA_RST_L TABLE_PHYSICAL_RULE_ITEM HDA_SDIN0 TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT HDA_SDOUT TABLE_SPACING_RULE_ITEM SPI * MIL ? MCP_HDA_PULLDN_COMP SMBUS_MCP_0_CLK SMBUS_MCP_0_DATA SMBUS_MCP_1_CLK SMBUS_MCP_1_DATA 19 12 20 42 12 20 42 20 42 20 42 20 35 20 20 35 20 20 20 35 20 35 20 35 20 20 SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.14 MCP_SUS_CLK SPI_CLK A SPI_MOSI SPI_MISO SPI_CS0 SPI_55S SPI SPI_55S SPI SPI_CLK SPI_55S SPI SPI_MOSI SPI_55S SPI SPI_MISO SPI_55S SPI SPI_CS0 SPI_55S SPI SPI_CLK_R SPI_CLK SPI_MOSI_R SPI_MOSI SPI_MISO SPI_MISO_R SPI_CS0_R_L SPI_CS0_L SPI_CLK_MUX SPI_MOSI_MUX SPI_MISO_MUX SPI_MLB_CS_L 20 24 24 39 MCP Constraints 20 41 48 SYNC_MASTER=M97 20 41 48 SYNC_DATE=02/04/2008 NOTICE OF PROPRIETARY PROPERTY 20 41 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING 48 20 41 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT 41 48 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART 41 48 41 48 SIZE 41 48 DRAWING NUMBER D APPLE INC SCALE SHT NONE REV 051-7631 2.3.0 OF 68 71 A SMC SMBus Net Properties TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 1TO1_DIFFPAIR * =STANDARD =STANDARD =STANDARD =STANDARD 0.1 MM 0.1 MM NET_TYPE ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING TABLE_PHYSICAL_RULE_ITEM D SMBUS_SMC_A_S3_SCL SMB_55S SMB SMBUS_SMC_A_S3_SDA SMB_55S SMB SMBUS_SMC_B_S0_SCL SMB_55S SMB SMBUS_SMC_B_S0_SDA SMB_55S SMB SMBUS_SMC_0_S0_SCL SMB_55S SMB SMBUS_SMC_0_S0_SDA SMB_55S SMB SMBUS_SMC_BSA_SCL SMB_55S SMB SMBUS_SMC_BSA_SDA SMB_55S SMB SMBUS_SMC_MGMT_SCL SMB_55S SMB SMBUS_SMC_MGMT_SDA SMB_55S SMB SMBUS_SMC_A_S3_SCL SMBUS_SMC_A_S3_SDA SMBUS_SMC_B_S0_SCL SMBUS_SMC_B_S0_SDA SMBUS_SMC_0_S0_SCL SMBUS_SMC_0_S0_SDA SMBUS_SMC_BSA_SCL SMBUS_SMC_BSA_SDA SMBUS_SMC_MGMT_SCL SMBUS_SMC_MGMT_SDA 42 42 42 42 42 42 42 42 D 42 42 SMBus Charger Net Properties NET_TYPE PHYSICAL ELECTRICAL_CONSTRAINT_SET CHGR_CSI 1TO1_DIFFPAIR 1TO1_DIFFPAIR CHGR_CSO 1TO1_DIFFPAIR 1TO1_DIFFPAIR SPACING CHGR_CSI_P CHGR_CSI_N CHGR_CSO_P CHGR_CSO_N C C B B SMC Constraints A SYNC_MASTER=M97 SYNC_DATE=02/04/2008 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC SCALE SHT NONE REV 051-7631 2.3.0 OF 69 71 A I1 I2 I3 I4 I5 I6 I7 I8 I10 I9 I12 D I11 I13 I14 I16 I15 I18 I17 I19 I21 I20 I23 I100 I101 I22 I24 I25 I26 I28 I27 I30 I29 I31 I33 I32 I35 I34 I36 C I38 I37 I39 I41 I40 I43 I42 I44 I46 I45 I48 I47 I49 I50 I52 I51 I54 I53 I55 I57 I56 I59 I58 I72 I71 I73 B I74 I76 I75 I78 I77 I79 I81 I80 I83 I82 I84 I86 I85 I102 I103 I104 I105 I106 I108 I109 I107 I110 I112 I113 I111 I114 PP0V75_S0 PP0V75_S3 PP0V75_S3_MEM_VREFCA PP0V75_S3_MEM_VREFDQ PP18V5_DCIN PP18V5_DCIN_ONEWIRE PP18V5_G3H PP18V5_S5_CHGR_SW_R PP1V05_ENET_MCP_PLL_MAC PP1V05_RMGT PP1V05_S0 PP1V05_S0_MCP_PEX_AVDD PP1V05_S0_MCP_PEX_AVDD_R PP1V05_S0_MCP_PEX_DVDD_R PP1V05_S0_MCP_PLL_CORE PP1V05_S0_MCP_PLL_FSB PP1V05_S0_MCP_PLL_NV PP1V05_S0_MCP_PLL_PEX PP1V05_S0_MCP_PLL_SATA PP1V05_S0_MCP_SATA_AVDD PP1V05_S5 PP1V2_S0_FC_VDD PP1V5_S0 PP1V5_S0_FC_AVDDL_F PP1V5_S0_FC_AVDDT_F PP1V5_S3 PP1V8_S0 PP2V_S0_MCPREG_REF PP3V3_LCDVDD_SW PP3V3_LCDVDD_SW_F PP3V3_RMGT PP3V3_S0 PP3V3_S0_CPUTHMSNS_R PP3V3_S0_DPFUSE PP3V3_S0_DPPWR PP3V3_S0_FC_AVDD_F PP3V3_S0_HDD_F PP3V3_S0_IMVP6_3V3 PP3V3_S0_LCD_F PP3V3_S0_MCPREG_VREF3 PP3V3_S0_MCP_DAC PP3V3_S0_MCP_PLL_USB PP3V3_S0_MCP_VPLL PP3V3_S3 PP3V3_S3_AP_AUX PP3V3_S3_AP_AUX_F PP3V3_S0_MIC_F PP3V3_S5 PP3V3_S5_AVREF_SMC PP3V3_S5_MCP PP3V3_S5_SMC_AVCC PP3V42G3H_SW PP3V42_G3H PP3V42_G3H_IPD_F PP3V42_G3H_SMCUSBMUX_R PP5V_S0 PP5V_S0_IMVP6_VDD PP5V_S0_KBDLED_F PP5V_S0_MCPREG_VCC PP5V_S3 PP5V_S3_CAMERA_F PP5V_S3_MCPREG_LDO PP5V_S3_TOPCASE_F PP5V_S3_USB2_EXTA PP5V_S3_USB2_EXTA_F PPBUS_G3H PPBUS_G3HRS5_VSENSE PPBUS_R_G3H PPBUS_S0_LCDBKLT_EN_DIV PPBUS_S0_LCDBKLT_EN_L PPBUS_S0_LCDBKLT_FUSED PPBUS_S0_LCDBKLT_PWR PPDCIN_G3H PPDCIN_G3H_R PPMCPCORE_S0 PPVBATT_G3H_R PPVBAT_G3H_CHGR_OUT PPVBATT_G3H_R PPVBAT_G3H_CHGR_OUT PPVBAT_G3H_CHGR_REG PPVBAT_G3H_CHRGR_REG_0 PPVBAT_G3H_CHRGR_REG_R PPVCORE_S0_CPU PPVDCIN_G3H_PRE PPVDCIN_G3H_PRE2 PPVDCIN_G3H_PRE_0 PPVDCIN_G3H_PRE_R PPVIN_S5_IMVP6_VIN PPVOUT_S0_LCDBKLT PPVOUT_S0_LCDBKLT_SW NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR 25 27 28 29 NET_SPACING_TYPE=PWR 25 27 28 29 NET_SPACING_TYPE=PWR 49 NET_SPACING_TYPE=PWR 49 NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR 58 NET_SPACING_TYPE=PWR 17 22 NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR 22 NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR 15 22 NET_SPACING_TYPE=PWR 13 22 NET_SPACING_TYPE=PWR 20 22 NET_SPACING_TYPE=PWR 16 22 NET_SPACING_TYPE=PWR 19 22 NET_SPACING_TYPE=PWR 19 22 NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PP1V5_MEM NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PP1V5_MEM NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR 59 NET_SPACING_TYPE=PWR 59 NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR 45 NET_SPACING_TYPE=PWR 61 NET_SPACING_TYPE=PWR 35 61 NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR 36 NET_SPACING_TYPE=PWR 50 NET_SPACING_TYPE=PWR 59 NET_SPACING_TYPE=PWR NET_SPACING_TYPE=GND 21 23 NET_SPACING_TYPE=PWR 19 22 NET_SPACING_TYPE=PWR 17 23 NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR 34 NET_SPACING_TYPE=PWR 34 NET_SPACING_TYPE=PWR 59 NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR 39 40 NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR 39 NET_SPACING_TYPE=PWR 49 NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR 38 NET_SPACING_TYPE=PWR 37 NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR 50 NET_SPACING_TYPE=PWR 38 NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR 59 NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR 38 NET_SPACING_TYPE=PWR 37 NET_SPACING_TYPE=PWR 35 37 NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR 43 NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR 63 NET_SPACING_TYPE=PWR 63 NET_SPACING_TYPE=PWR 63 NET_SPACING_TYPE=PWR 62 63 NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR 49 NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR 49 70 NET_SPACING_TYPE=PWR 58 70 NET_SPACING_TYPE=PWR 49 70 NET_SPACING_TYPE=PWR 58 70 NET_SPACING_TYPE=PWR 58 NET_SPACING_TYPE=PWR 58 NET_SPACING_TYPE=PWR 58 NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR 43 58 NET_SPACING_TYPE=PWR 58 NET_SPACING_TYPE=PWR 58 NET_SPACING_TYPE=PWR 58 NET_SPACING_TYPE=PWR 50 NET_SPACING_TYPE=PWR 59 62 NET_SPACING_TYPE=PWR 62 30 30 D TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LINE-TO-LINE SPACING WEIGHT PWR LAYER * =STANDARD ? BUS2PWR_GND * 0.228 MM ? TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM C B M96 Power and Ground Nets A SYNC_MASTER=(MASTER) SYNC_DATE=(MASTER) NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC SCALE SHT NONE REV 051-7631 2.3.0 OF 70 71 A M96 BOARD-SPECIFIC SPACING & PHYSICAL CONSTRAINTS TABLE_BOARD_INFO BOARD LAYERS BOARD AREAS BOARD UNITS (MIL or MM) ALLEGRO VERSION TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,ISL12,ISL13,BOTTOM NO_TYPE,BGA_P1MM MM 15.2 TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE TABLE_SPACING_RULE_ITEM DEFAULT * 0.1 MM ? PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP DEFAULT * Y =50_OHM_SE 0.200 MM 30 MM MM MM * * BGA_P1MM STANDARD * =DEFAULT ? BGA_P1MM * =DEFAULT ? BGA_P2MM TABLE_PHYSICAL_RULE_ITEM * Y =DEFAULT =DEFAULT 12.7 MM =DEFAULT * =DEFAULT ? * BGA_P1MM BGA_P2MM CLK_FSB * BGA_P1MM BGA_P2MM BGA_P3MM LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP * =DEFAULT ? LINE-TO-LINE SPACING WEIGHT TOP,BOTTOM Y STANDARD TABLE_PHYSICAL_ASSIGNMENT_ITEM CLK_LPC * BGA_P1MM BGA_P2MM CLK_PCI * BGA_P1MM BGA_P2MM CLK_PCIE * BGA_P1MM BGA_P2MM CLK_SLOW * BGA_P1MM BGA_P2MM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM DIFFPAIR NECK GAP D TABLE_SPACING_RULE_HEAD SPACING_RULE_SET TABLE_PHYSICAL_RULE_ITEM 55_OHM_SE BGA_P1MM =DEFAULT TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET MEM_50S TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_RULE_ITEM D PHYSICAL_RULE_SET BGA_P1MM MEM_CLK TABLE_SPACING_RULE_ITEM STANDARD AREA_TYPE TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_ASSIGNMENT_HEAD NET_PHYSICAL_TYPE TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD SPACING_RULE_SET 0.210 MM LAYER 0.200 MM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_RULE_ITEM 55_OHM_SE ISL2,ISL13 Y 0.075 MM 0.075 MM =STANDARD =STANDARD =STANDARD 55_OHM_SE * Y 0.066 MM 0.066 MM =STANDARD =STANDARD =STANDARD TABLE_PHYSICAL_RULE_ITEM 1.5:1_SPACING * 0.15 MM ? TABLE_PHYSICAL_RULE_ITEM 2:1_SPACING * 0.2 MM ? TABLE_SPACING_ASSIGNMENT_ITEM FSB_DSTB FSB_DSTB BGA_P1MM BGA_P3MM TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM 2.5:1_SPACING * 0.25 MM ? 3:1_SPACING * 0.3 MM ? 4:1_SPACING * 0.4 MM ? 4:1_SPACING * 0.4 MM ? 2.28:1_SPACING * 0.228 MM ? 1.1:1_SPACING * 0.110 MM ? TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM 50_OHM_SE TOP,BOTTOM Y 0.250 MM 0.200 MM 50_OHM_SE ISL2,ISL13 Y 0.085 MM 0.085 MM =STANDARD =STANDARD =STANDARD 50_OHM_SE * Y 0.066 MM 0.066 MM =STANDARD =STANDARD =STANDARD LAYER ALLOW ROUTE ON LAYER? TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP TABLE_SPACING_RULE_ITEM DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM 40_OHM_SE TOP,BOTTOM Y 0.350 MM 0.200 MM 40_OHM_SE ISL2,ISL13 Y 0.122 MM 0.122 MM TABLE_SPACING_RULE_HEAD SPACING_RULE_SET TABLE_PHYSICAL_RULE_ITEM =STANDARD =STANDARD =STANDARD LINE-TO-LINE SPACING WEIGHT 2X_DIELECTRIC TOP,BOTTOM LAYER 0.230 MM ? 3X_DIELECTRIC TOP,BOTTOM 0.345 MM ? 4X_DIELECTRIC TOP,BOTTOM 0.460 MM ? 5X_DIELECTRIC TOP,BOTTOM 0.575 MM ? 2X_DIELECTRIC ISL2,ISL13 0.110 MM ? 3X_DIELECTRIC ISL2,ISL13 0.165 MM ? 4X_DIELECTRIC ISL2,ISL13 0.220 MM ? 5X_DIELECTRIC ISL2,ISL13 0.275 MM ? 2X_DIELECTRIC * 0.120 MM ? 3X_DIELECTRIC * 0.180 MM ? 4X_DIELECTRIC * 0.240 MM ? 5X_DIELECTRIC * 0.300 MM ? LINE-TO-LINE SPACING WEIGHT * TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM 40_OHM_SE * Y LAYER ALLOW ROUTE ON LAYER? 0.110 MM 0.110 MM =STANDARD =STANDARD =STANDARD TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP TABLE_SPACING_RULE_ITEM DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM 27P4_OHM_SE TOP,BOTTOM Y 0.215 MM TABLE_SPACING_RULE_ITEM 0.200 MM TABLE_PHYSICAL_RULE_ITEM 27P4_OHM_SE * Y 0.215 MM 0.215 MM =STANDARD =STANDARD =STANDARD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 70_OHM_DIFF * N =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD C TABLE_SPACING_RULE_ITEM C TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM 70_OHM_DIFF ISL2,ISL4,ISL5,ISL10,ISL11,ISL13 Y 0.132 MM 0.132 MM 0.200 MM 0.200 MM TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM 70_OHM_DIFF TOP,BOTTOM Y 0.180 MM 0.180 MM 0.150 MM 0.150 MM TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM 90_OHM_DIFF * N =STANDARD =STANDARD 90_OHM_DIFF ISL2,ISL4,ISL5,ISL10,ISL11,ISL13 Y 0.085 MM 90_OHM_DIFF TOP,BOTTOM Y 0.205 MM =STANDARD =STANDARD =STANDARD 0.085 MM 0.250 MM 0.250 MM 0.200 MM 0.160 MM 0.160 MM TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_ITEM GND * =STANDARD ? PP1V5_MEM * =STANDARD ? LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM 100_OHM_DIFF * N =STANDARD =STANDARD =STANDARD =STANDARD 100_OHM_DIFF ISL2,ISL4,ISL5,ISL10,ISL11,ISL13 Y 0.065 MM 0.065 MM =STANDARD 0.280 MM 0.280 MM 100_OHM_DIFF TOP,BOTTOM Y 0.179 MM 0.179 MM 0.200 MM 0.200 MM TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_ITEM GND_P2MM * 0.2 MM 1000 PWR_P2MM * 0.2 MM 1000 LINE-TO-LINE SPACING WEIGHT =STANDARD ? TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 100_OHM_DIFF_HDD * N =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_ITEM MCP_STATIC TABLE_PHYSICAL_RULE_ITEM 100_OHM_DIFF_HDD ISL2,ISL4,ISL5,ISL10,ISL11,ISL13 Y 0.065 MM 0.065 MM 0.280 MM 0.280 MM 100_OHM_DIFF_HDD TOP,BOTTOM Y 0.179 MM 0.179 MM 0.200 MM 0.200 MM PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 40_OHM_SE_MEM TOP,BOTTOM Y 0.170 MM 0.110 MM 10 MM 40_OHM_SE_MEM ISL2,ISL13 Y 0.122 MM 0.066 MM 170 MM =STANDARD =STANDARD 40_OHM_SE_MEM * Y 0.110 MM 0.066 MM 170 MM =STANDARD =STANDARD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 1:1_DIFFPAIR * Y =STANDARD =STANDARD =STANDARD 0.1 MM 0.1 MM TABLE_PHYSICAL_RULE_ITEM B B TABLE_PHYSICAL_RULE_HEAD TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD TABLE_PHYSICAL_RULE_ITEM M96 RULE DEFINITIONS A SYNC_MASTER=M97 SYNC_DATE=02/04/2008 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC SCALE SHT NONE REV 051-7631 2.3.0 OF 71 71 A ... PCBA ,MLB, 1.6GHZ,HY 2GB,MU CAP ,M96 EEE_4DB ,M96_ COMMON ,M96_ HYNIX ,M96_ MU_CAP,CPU_1_6GHZ TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM 630-9514 PCBA ,MLB, 1.6GHZ,HY 2GB,TY CAP ,M96 EEE_2AL ,M96_ COMMON ,M96_ HYNIX ,M96_ TY_CAP,CPU_1_6GHZ... EEE_2AL ,M96_ COMMON ,M96_ HYNIX ,M96_ TY_CAP,CPU_1_6GHZ TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM 630-9738 PCBA ,MLB, 1.8GHZ,HY 2GB,SS CAP ,M96 EEE_4DC ,M96_ COMMON ,M96_ HYNIX ,M96_ SS_CAP,CPU_1_8GHZ 630-9516 PCBA ,MLB, 1.8GHZ,HY... CAP ,M96 EEE_2AN ,M96_ COMMON ,M96_ HYNIX ,M96_ MU_CAP,CPU_1_8GHZ TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM D TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM 630-9517 PCBA ,MLB, 1.8GHZ,HY 2GB,TY CAP ,M96 EEE_2AP ,M96_ COMMON ,M96_ HYNIX ,M96_ TY_CAP,CPU_1_8GHZ