A1342 635c2 k87 MLB 051 8561 820 2877 c00

8 ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5% ALL CAPACITANCE VALUES ARE IN MICROFARADS ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ REV ECN DESCRIPTION OF REVISION C 0000897412 CK APPD DATE PRODUCTION RELEASED 2010-04-26 SCHEM MLB_LDO K87 SCRATCHO D D 04/26/2010 (.csa) (.csa) Page TABLE_TABLEOFCONTENTS_HEAD Contents TABLE_TABLEOFCONTENTS_ITEM 2 TABLE_TABLEOFCONTENTS_ITEM 3 TABLE_TABLEOFCONTENTS_ITEM 4 TABLE_TABLEOFCONTENTS_ITEM 5 TABLE_TABLEOFCONTENTS_ITEM 6 TABLE_TABLEOFCONTENTS_ITEM 7 TABLE_TABLEOFCONTENTS_ITEM 8 TABLE_TABLEOFCONTENTS_ITEM 9 TABLE_TABLEOFCONTENTS_ITEM 10 10 TABLE_TABLEOFCONTENTS_ITEM 11 11 TABLE_TABLEOFCONTENTS_ITEM 12 12 TABLE_TABLEOFCONTENTS_ITEM 13 13 TABLE_TABLEOFCONTENTS_ITEM 14 14 TABLE_TABLEOFCONTENTS_ITEM 15 15 TABLE_TABLEOFCONTENTS_ITEM 16 16 TABLE_TABLEOFCONTENTS_ITEM 17 17 TABLE_TABLEOFCONTENTS_ITEM 18 18 TABLE_TABLEOFCONTENTS_ITEM 19 19 TABLE_TABLEOFCONTENTS_ITEM 20 20 TABLE_TABLEOFCONTENTS_ITEM 23 21 TABLE_TABLEOFCONTENTS_ITEM 24 22 TABLE_TABLEOFCONTENTS_ITEM 25 23 TABLE_TABLEOFCONTENTS_ITEM 26 24 TABLE_TABLEOFCONTENTS_ITEM 28 25 TABLE_TABLEOFCONTENTS_ITEM 29 26 TABLE_TABLEOFCONTENTS_ITEM 31 27 TABLE_TABLEOFCONTENTS_ITEM 32 28 B Date NA NA MASTER MASTER MASTER MASTER TABLE_TABLEOFCONTENTS_ITEM 33 29 TABLE_TABLEOFCONTENTS_ITEM 34 30 TABLE_TABLEOFCONTENTS_ITEM 37 31 TABLE_TABLEOFCONTENTS_ITEM 39 32 TABLE_TABLEOFCONTENTS_ITEM 45 33 TABLE_TABLEOFCONTENTS_ITEM 46 34 TABLE_TABLEOFCONTENTS_ITEM 49 35 TABLE_TABLEOFCONTENTS_ITEM 50 36 TABLE_TABLEOFCONTENTS_ITEM 51 37 TABLE_TABLEOFCONTENTS_ITEM 52 38 Page TABLE_TABLEOFCONTENTS_HEAD 1 C Sync Table of Contents System Block Diagram Power Block Diagram BOM Configuration Revision History Revision History FUNC TEST Power Aliases SIGNAL ALIAS CPU FSB CPU Power & Ground CPU Decoupling eXtended Debug Port(MiniXDP) MCP CPU Interface MCP Memory Interface MCP PCIe Interfaces MCP Graphics MCP SATA, USB & Ethernet MCP HDA, LPC & MISC MCP Power & Ground MCP89 Memory Rail Gating MCP89 GFX Core Rail Gating MCP Standard Decoupling MCP Graphics Support SB Misc DDR3 SO-DIMM Connector A DDR3 SO-DIMM Connector B SO-DIMM Pinswaps FSB/DDR3 Vref Margining X16 WIRELESS CONNECTOR Ethernet PHY (RTL8211CL) ETHERNET CONNECTOR SATA Connectors External USB Connectors SMC SMC Support LPC+SPI Debug Connector K87 SMBus Connections TABLE_TABLEOFCONTENTS_ITEM 54 40 TABLE_TABLEOFCONTENTS_ITEM 55 41 TABLE_TABLEOFCONTENTS_ITEM (K84_MLB) (01/19/2009) MASTER MASTER MASTER MASTER MASTER MASTER MASTER MASTER (K84_MLB) (02/04/2009) T27_MLB 02/16/2010 56 42 TABLE_TABLEOFCONTENTS_ITEM 57 43 TABLE_TABLEOFCONTENTS_ITEM 58 44 TABLE_TABLEOFCONTENTS_ITEM 59 45 TABLE_TABLEOFCONTENTS_ITEM 60 46 TABLE_TABLEOFCONTENTS_ITEM 61 47 TABLE_TABLEOFCONTENTS_ITEM 62 48 TABLE_TABLEOFCONTENTS_ITEM T27_MLB 02/16/2010 T27_MLB 02/16/2010 63 49 TABLE_TABLEOFCONTENTS_ITEM 65 50 TABLE_TABLEOFCONTENTS_ITEM (K84_MLB) (02/25/2009) T27_MLB 02/16/2010 T27_MLB 02/16/2010 T27_MLB 02/16/2010 T27_MLB 02/16/2010 Contents 66 51 TABLE_TABLEOFCONTENTS_ITEM 67 52 TABLE_TABLEOFCONTENTS_ITEM 68 53 TABLE_TABLEOFCONTENTS_ITEM 69 54 TABLE_TABLEOFCONTENTS_ITEM 70 55 TABLE_TABLEOFCONTENTS_ITEM T27_MLB 02/16/2010 T27_MLB 02/16/2010 T27_MLB 02/16/2010 K6_MLB 02/16/2010 T27_MLB 12/15/2009 (T27_MLB) (11/16/2009) T27_MLB 02/16/2010 72 56 TABLE_TABLEOFCONTENTS_ITEM 73 57 TABLE_TABLEOFCONTENTS_ITEM 74 58 TABLE_TABLEOFCONTENTS_ITEM 75 59 TABLE_TABLEOFCONTENTS_ITEM 76 60 TABLE_TABLEOFCONTENTS_ITEM 77 61 TABLE_TABLEOFCONTENTS_ITEM 78 62 TABLE_TABLEOFCONTENTS_ITEM (T27_MLB) (10/07/2009) T27_MLB 02/16/2010 T27_MLB 02/16/2010 MASTER MASTER T27_MLB 02/16/2010 MASTER MASTER MASTER MASTER 79 63 TABLE_TABLEOFCONTENTS_ITEM 90 64 TABLE_TABLEOFCONTENTS_ITEM 93 65 TABLE_TABLEOFCONTENTS_ITEM 94 66 TABLE_TABLEOFCONTENTS_ITEM 97 67 TABLE_TABLEOFCONTENTS_ITEM 98 68 TABLE_TABLEOFCONTENTS_ITEM 100 69 TABLE_TABLEOFCONTENTS_ITEM MASTER MASTER MASTER MASTER (K84_MLB) (10/03/2009) T27_MLB 02/16/2010 (T27_MLB) (10/27/2009) 101 70 TABLE_TABLEOFCONTENTS_ITEM 102 71 TABLE_TABLEOFCONTENTS_ITEM 103 72 TABLE_TABLEOFCONTENTS_ITEM 104 73 TABLE_TABLEOFCONTENTS_ITEM 106 74 TABLE_TABLEOFCONTENTS_ITEM (T27_MLB) (12/15/2009) MASTER MASTER 108 75 TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM Sync Date T27_MLB 02/16/2010 T27_MLB 02/02/2010 MASTER MASTER T27_MLB 02/16/2010 T27_MLB 02/16/2010 MASTER MASTER MASTER MASTER MASTER MASTER T27_MLB 02/16/2010 AUDIO 02/16/2010 AUDIO 02/16/2010 AUDIO 02/16/2010 AUDIO 02/16/2010 AUDIO 02/16/2010 AUDIO 02/16/2010 MASTER MASTER (K6_MLB) (11/06/2009) (K6_MLB) (10/27/2009) (K6_MLB) (11/06/2009) (K84_MLB) (11/18/2009) (K6_MLB) (10/27/2009) (K84_MLB) (02/04/2009) MASTER MASTER (T27_MLB) (10/27/2009) MASTER MASTER (K84_MLB) (10/19/2009) K6_MLB 02/16/2010 MASTER MASTER 53 39 109 76 Voltage Sensing Current Sensing Thermal Sensors Fan Connector WELLSPRING WELLSPRING SMS DEBUG SENSORS AND ADC SPI ROM AUDIO: CODEC/REGULATOR AUDIO: LINE INPUT FILTER AUDIO: HEADPHONE FILTER AUDI0: SPEAKER AMP AUDIO: JACK AUDIO: JACK TRANSLATORS DC-In & Battery Connectors PBus Supply & Battery Charger 5V/3.3V SUPPLY 1.5V/0.75V DDR3 SUPPLY IMVP6 CPU VCore Regulator MCP VCore Regulator CPU VTT(1.05V) SUPPLY Misc Power Supplies Power Sequencing POWER FETS LVDS CONNECTOR DISPLAYPORT SUPPORT DisplayPort Connector LCD Backlight Driver (MC34845) LCD Backlight Support CPU/FSB Constraints Memory Constraints MCP Constraints MCP Constraints Ethernet Constraints SMC Constraints K87 SPECIFIC CONSTRAINTS K87 RULE DEFINITIONS C B MASTER MASTER (K84_MLB) (10/19/2009) T27_MLB 02/16/2010 T27_MLB 02/16/2010 T27_MLB 02/16/2010 T27_MLB 02/16/2010 MASTER MASTER T27_MLB 02/16/2010 MASTER MASTER MASTER MASTER TABLE_TABLEOFCONTENTS_ITEM A A DRAWING TITLE SCHEM,MLB_LDO,SCRATCHO,K87 DRAWING NUMBER Schematic / PCB #’s Apple Inc 051-8561 REVISION R PART NUMBER DESCRIPTION REFERENCE DES 051-8561 SCHEM,MLB_LDO,K87 SCH CRITICAL 820-2877 PCBF,MLB_LDO,K87 PCB CRITICAL QTY CRITICAL BOM OPTION NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED C.0.0 BRANCH PAGE OF 109 SHEET OF 76 SIZE D U1000 INTEL CPU J1300 J6950 K87 2.4GHZ PENRYN K86 1.2GHZ CULV HALL EFFECT CONN MINI XDP CONN PG 69 PG 13 U5920 PG 10 SMS PG 59 FSB J6950,U7000 64-Bit D DC/BATT 1067/1333 MHz D POWER SUPPLY PG 69,70 PG 70-79 U5535,U5515 TEMP SENSORS J3100 J2900 GPIOs MAIN MEMORY FSB INTERFACE PG 55 UDIMMs DDR3-1067/1333MHZ POWER SENSE VOLTAGE AND CURRNET SENSING DIMM PG 53,54 PG 15 PG 19 PG 14 PG 29,30 J5601 FAN CONN PG 56 MISC PG 19 U6100 J4501 HD LID SMS BSB B,0 ADC U4900 SATA CONN SPI BOOT ROM SPI 1.05V/3GHZ Fan Ser Prt J5100 SMC LPC+SPI CONN PG 49 PG 51 PG 18 PG 45 SATA PG 18 J4500 SATA CONN PG 61 NVIDIA MCP 1.05V/3GHZ LPC PG 19 ODD C C J5800 PG 45 U1400 TRACKPAD CONN PWR PG 58 CTRL J9000 LVDS CONN LVDS OUT PG 90 J3401 U5701 BLUETOOTH TRACKPAD/ KEYBOARD PG 34 J4600, J4610 J9000 PG 57 CAMERA PG 90 EXTERNAL USB CONN PG 46 PG 94 HDMI OUT DVI OUT TMDS OUT RGB OUT PG 17 J3401 11 PCI-E UP TO 20 LANES3 AIR PORT CONN B 10 DISPLAY PORT CONN USB DP OUT PG 18 (UP TO 12 DEVICES) J9400 B J1300 SMB PG 34 PG 16 MINI XDP CONN PG 19 PG 13 LAN RGMII PG 17 MAC HDA PCI PG 19 PG 17 U3700 GIGABIT 10/100/1000 E-NET RTL8251CA U6201 PG 37 AUDIO CODEC J3900 PG 62 E-NET CONN PG 32 U6610, U6620, U6630 A LINE IN FILTER HEADPHONE FILTER SPEAKER AMPS PG 63 PG 65 PG 66 SYNC_MASTER=MASTER SYNC_DATE=MASTER PAGE TITLE System Block Diagram DRAWING NUMBER J6701,J6702,J6703,J6704 Apple Inc AUDIO CONNS R NOTICE OF PROPRIETARY PROPERTY: PG 67 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED 051-8561 REVISION C.0.0 BRANCH PAGE OF 109 SHEET OF 76 SIZE D A K86/K87 POWER SYSTEM ARCHITECTURE PP18V5_DCIN_CONN Q7080 02 PPDCIN_G3H_OR_PBUS Q7085 V 8A FUSE PPVBAT_G3H_CHGR_REG D ENABLE PP3V42_G3H_REG 03 3.425V G3HOT LT3470 VOUT U6990 PBUS_VSENSE SMC PWRGD RN5VD30A-F 04 U5010 Q5315 PPBUS_G3H MCP89 PBUS_G3H_VSENSE 01 F7040 30 02 AC DCIN(16.5V) ADAPTER IN CHGR_EN (S5) F6905 6A FUSE A VIN SMC_DCIN_ISENSE RSMRST* 21 MCP_PS_PWRGD PWRGD (8A MAX CURRENT) CPUPWRGD(GPIO49) CPU_RESET# U1400 A PGOOD CPUVTTS0_PGOOD V 01 VOUT VIN IMVP_VR_ON_R Q7055 ISL9504B U7100 U1000 16 P5VS0_EN MCP89 P3V3S3_EN VIN P5VS3_EN_L EN1 PM_SLP_S4_L 5V (RT) P16 14 P3V3S5_EN_L SMC 09-3 U4900 DDRREG_EN RC DELAY 10 C PP5V_S0_FET PPBUS_G3H 02 PM_SLP_S3_L P60 SMC_PM_G2_EN VOUT2 EN2 3.3V (S5) PGOOD1,2 12 4.5V AUDIO MAX8840 (13A MAX CURRENT) VIN PP3V3_S5_REG EN Q7910 PP3V3_S3_FET 10 Q3450 VREG3 P3V3_S3_WLAN P3V3S3_EN P5V3V3_PGOOD 11 P3V3ENET_EN_L P5VS3_EN_L RC DELAY Q7930 Q7960 1.05V NCP1529 U7710 B PP1V05_S0_REG 12 VIN P0V9S5_EN EN Q7890 AP_PWR_EN RSMRST_OUT(P15) PM_WLAN_EN_L ISL8009B U7750 04 15 PM_SLP_RMGT_L 07 VOUT 09 SMC_ONOFF_L 08 PP0V9_ENET_FET VIN MC34845 U9700 BKLT_EN SMC_ADAPTER_EN ENA P0V9_ENET_EN TPS62202 U7760 02 =DDRREG_EN A RC DELAY RC DELAY RC DELAY P1V5S0_EN 15-4 CPUVTTS0_EN 15-5 DDRVTT_EN MCPCORES0_EN =DDTVTT_EN PBUSVSENS_EN (S0) P5VS0_EN (S0) RC DELAY P3V3S0_EN PP1V8_S0_REG SLP_S4_L 18 SLP_S3_L Q7930 PP1V5R1V35_SW_MCP 15-1 1.8V VIN S5 1.5V PP3V3S0_EN PP1V5_S3_REG (12A MAX CURRENT) VOUT1 0.75V VOUT2 S3 TPS51116 U7300 1.5V FDC638P Q7920 13 19 1.05V SLP_S5_L(P95) SLP_S4_L(P94) SLP_S3_L(P93) U4900 20 15-1 15-2 22 PPMCPCORE_S0_R R7525 PPMCPCORE_S0_REG ISL9563A PP3V3_S0 V1 PP1V5_S0 V2 PP1V05_S0 VOUT EN BKLT_EN (25A MAX CURRENT) Power Block Diagram DRAWING NUMBER U7870 ISL88042 Apple Inc V3 051-8561 REVISION R THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED SYNC_DATE=MASTER PAGE TITLE NOTICE OF PROPRIETARY PROPERTY: VIN 15-6 SMC_RESET_L PP1V05_S0_MCP_PLL_OR U7500 RST* MCPPLLDO_PGOOD 02 PM_PWRBTN_L SYNC_MASTER=MASTER MCPCORES0_EN 24 S0PGOOD_RST_L RST* MCP_CORE B MCPCORES0_PGOOD CPUVTTS0_PGOOD TPS74701 U7740 PP0V75_S0_REG (1A MAX CURRENT) 21 PP1V5_S0_FET IMVP_VR_ON_R IMVP_VR_ON(P16) RSMRST_IN(P13) PLT_RST* PWR_BUTTON(P90) P17(BTN_OUT) P5V3V3_PGOOD 17 99ms DLY 18-2 PM_RSMRST_L 17 SLP_S5_L PPVOUT_SW_LCDBKLT 04-1 PM_SLP_S3_L PP3V3_S0_FET 11 VOUT PWRGD(P12) RSMRST_PWRGD PP0V9_S5_REG 02 Q7890,Q7891 PM_SLP_S3_L SMC 23 ALL_SYS_PWRGD P3V3S0_EN 15-3 18 PP4V5_AUDIO_ANALOG VOUT U7840 09-2 P1V8S0_EN U6200 06 (5.5A MAX CURRENT) TPS51125 U7201 04 04 PP5V_S3_REG VOUT1 PM_SLP_RMGT_L RC DELAY 31 VR_PWRGOOD_DELAY PGOOD Q7948 CHGR_BGATE 09-1 PWRGOOD 27 C 09 CPU U2850 25 RESET* VR_ON 24 PPVBAT_G3H_CHGR_R 28 SMC_CPU_VSENSE PPVCORE_S0_CPU (44A MAX CURRENT) SMC_CPU_ISENSE CPU VCORE J6950 U1400 CPU_PWRGD 29 TPS51117 U7600 02 PPVBAT_G3H_CONN PP1V05_S0 (1.05V) SMC_BATT_ISENSE PBUS SUPPLY/ BATTERY CHARGER VOUT CPUVTT R7050 VOUT ISL6259 U7000 (9 TO 12.6V) EN_PSV LPC_RESET_L FSB_CPURST_L R7020 PLTRST* VIN CPUVTTS0_EN (S0) ENABLES 3S2P D 08-1 PWRBTN* C.0.0 BRANCH PAGE OF 109 SHEET OF 76 SIZE D A BOM Variants TABLE_BOMGROUP_HEAD BOM NUMBER BOM NAME BOM OPTIONS 639-1115 PCBA,MLB_LDO,FOXCONN,K87 K86_K87_COMMON,K87_SPECIFIC,FOX_DDR_CONN,EEEE:DD16 Bar Code Labels / EEE #’s TABLE_BOMGROUP_ITEM PART NUMBER QTY DESCRIPTION REFERENCE DES 826-4393 LBL,P/N LABEL,PCB,28MM X MM [EEEE_DD16] CRITICAL CRITICAL BOM OPTION EEEE:DD16 826-4393 LBL,P/N LABEL,PCB,28MM X MM [EEEE_DD17] CRITICAL EEEE:DD17 826-4393 LBL,P/N LABEL,PCB,28MM X MM [EEEE_DD18] CRITICAL EEEE:DD18 826-4393 LBL,P/N LABEL,PCB,28MM X MM [EEEE_DD19] CRITICAL EEEE:DD19 TABLE_BOMGROUP_ITEM 639-1116 PCBA,MLB_LDO,MOLEX,K87 K86_K87_COMMON,K87_SPECIFIC,MOLEX_DDR_CONN,EEEE:DD17 TABLE_BOMGROUP_ITEM 085-1799 K87 MLB_LDO DEVELOPMENT BOM K86_K87_DEVELOPMENT_PVT Development BOM PART NUMBER QTY 085-1632 D DESCRIPTION REFERENCE DES CRITICAL DEVEL K87 MLB_LDO DEVELOPMENT BOM CRITICAL BOM OPTION DEVELOPMENT_BOM D Part Substitutions (differences with K6/K69) BOM Groups (always-present) PART NUMBER TABLE_BOMGROUP_HEAD BOM GROUP BOM OPTIONS 114S0125 TABLE_BOMGROUP_ITEM K86_K87_COMMON K86_K87_COMMON1,PROJECT_PHASE:PROD,COMMON,ALTERNATE,BOOTROM:PROG,WELLSPRING:PROG,MCP_T_DIODE_SENSOR K86_K87_COMMON1 DP_ESD,MIKEY,MCPPLL_R:REG,ENET1V05:INT,LED:K86_K87,S0PGOOD_BJT,ENET_ESD,VFRQ:SLPS3,SMC_DEBUG:YES,SPI:25MHZ,XDP,OLD_AUDIO_SWITCH K87_SPECIFIC CPU:2.4GHZ,IMVP6:2PHASE,SMC:PROG_K87,MCP89M:A02 K86_SPECIFIC CPU:1.2GHZ,IMVP6:1PHASE,SMC:PROG_K86,MCP83M QTY DESCRIPTION RES,MTL FILM,1/16W,113 OHM,1,0402,SMD,LF REFERENCE DES CRITICAL BOM OPTION R5714 LED:K86_K87 TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM BOM Groups (project phase-dependent) TABLE_BOMGROUP_HEAD BOM GROUP BOM OPTIONS TABLE_BOMGROUP_ITEM PROJECT_PHASE:DEV DEVELOPMENT_BOM PROJECT_PHASE:PROD K86_K87_DEBUG:PROD K86_K87_DEVELOPMENT_ONLY DEBUG_ADC,LPCPLUS_CON,S0PGOOD_ISL,EFI_DEBUG,MCPPLL_LDO,EXT1V05,XDP_CON,LPCPLUS K86_K87_DEVELOPMENT_PVT LPCPLUS_CON,XDP_CON,VREFMRGN:YES,LPCPLUS K86_K87_DEBUG:DEV VREFMRGN:YES,BMON:ENG,BKLT:ENG,SENS_R:ENG K86_K87_DEBUG:PROD VREFMRGN:NO,BMON:PROD,BKLT:PROD,SENS_R:PROD,MCPHVDD:P2V5,LDO:FIXED,HTOL_SENSE:YES TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM Module Parts PART NUMBER C B QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION 337S3680 PDC,LGDZ,PRQ,2.40,25W,1066,R0,3M,BGA U1000 CRITICAL CPU:2.4GHZ 337S3792 CDC,SLGYW,PRQ,1.2,10W,800,R0,1M,BGA U1000 CRITICAL CPU:1.2GHZ 337S3797 IC,MCP89M-A01,31X31MM,BGA1168 U1400 CRITICAL MCP89M:A01 337S3866 IC,MCP89M-A02,31X31MM,BGA1168 U1400 CRITICAL MCP89M:A02 337S3876 IC,MCP83M-A02,31X31MM,BGA1168 U1400 CRITICAL MCP83M 516S0706 CONN,204P,SODIMM,SOCKET,DDR3,RAM,BGA J3100 CRITICAL FOX_DDR_CONN 516-0201 CONN,204P,SODIMM,P=0.6MM J2900 CRITICAL FOX_DDR_CONN 516S0790 CONN,204P,SODIMM,SOCKET,DDR3,RAM,BGA J3100 CRITICAL MOLEX_DDR_CONN 516-0213 CONN,204P,SODIMM,P=0.6MM J2900 CRITICAL MOLEX_DDR_CONN 452-1708 SCR.M1.6X0.35X6.0,D4,HO.3,BLK,M97 SCREW1,SCREW2,SCREW3,SCREW4 CRITICAL 870-1940 POGO PIN,MED,NOISE-IMPROVED,SILVER,K87 ZS0900,ZS0901,ZS0902,ZS0903 CRITICAL 870-1940 POGO PIN,MED,NOISE-IMPROVED,SILVER,K87 ZS0908,ZS0909,ZS0911 CRITICAL 870-1939 POGO PIN,TALL,NOISE-IMPROVED,SILVER,K87 ZS0904,ZS0905,ZS0906,ZS0907,ZS0910 CRITICAL 870-1939 POGO PIN,TALL,NOISE-IMPROVED,SILVER,K87 ZS0912,ZS0913,ZS0914,ZS0915,ZS0919 CRITICAL 870-1938 POGO PIN,THIN,NOISE-IMPROVED,SILVER,K87 ZS0917,ZS0918,ZS0916 CRITICAL 353S2718 514-0704 514-0705 514-0706 514-0718 IS IS IS IS IS NEW INTERSIL PART FOR FIXING B4 CLOUD GREY 4/LB3 PLASTIC W/PDNI CLOUD GREY 4/LB3 PLASTIC W/PDNI CLOUD GREY 4/LB3 PLASTIC W/PDNI CLOUD GREY 4/LB3 PLASTIC W/PDNI DONGLE ISSUE PLATING VERSION PLATING VERSION PLATING VERSION PLATING VERSION Programmable Parts OF OF OF OF 514-0692 514-0689 514-0691 514-0694 PART PART PART PART FOR FOR FOR FOR C K86/K87 BOARD STACK-UP RJ45 CONNECTOR USB CONNECTORS MINI DP CONNECTOR AUDIO CONNECTOR TOP SIGNAL GROUND SIGNAL(High Speed) SIGNAL(High Speed) GROUND POWER POWER GROUND B LOCKED BOOTROM APN IS 341S2488 (QL: old info?) 338S0563 IC,SMC,HS8/2117,9X9MM,TLP,HF U4900 CRITICAL SMC:BLANK 341T0252 SUBASSY, IC, SMC, K87 U4900 CRITICAL SMC:PROG_K87 341T0250 SUBASSY, IC, SMC, K86 U4900 CRITICAL SMC:PROG_K86 335S0610 IC,FLASH,SPI,32MBIT,3.3V,86MHZ,8-SOP U6100 CRITICAL BOOTROM:BLANK 341T0251 SUBASSY, IC, BOOT ROM, K86/K87 U6100 CRITICAL BOOTROM:PROG 337S2983 IC,PSOC+ W/ USB,56 PIN,MLF,CY8C24794 U5701 CRITICAL WELLSPRING:BLANK 341S2677 IC,WELLSPRING CONTROLLER,K87 U5701 CRITICAL WELLSPRING:PROG Alternate Parts SIGNAL(High Speed) 10 SIGNAL(High Speed) 11 GROUND BOTTOM SIGNAL TABLE_ALT_HEAD PART NUMBER ALTERNATE FOR PART NUMBER 152S0693 152S0778 BOM OPTION REF DES ALL COMMENTS: DALE/VISHAY, MAGLAYERS AS ALTERNATE 152S0796 152S0685 ALL CYNTEC AS ALTERNATE 157S0058 157S0055 ALL DELTA AS ALTERNATE 138S0603 138S0602 ALL MURATA AS ALTERNATE 128S0093 128S0218 ALL KEMET AS ALTERNATE 152S0874 152S0516 ALL MAGLAYERS AS ALTERNATE 152S0847 152S0586 ALL MAGLAYERS AS ALTERNATE 104S0018 104S0023 ALL DALE/VISHAY AS ALTERNATE 353S2811 353S1832 ALL NEW IMPROVED INTERSIL PART AS ALTERNATE 353S2988 353S2987 ALL MIC5365 AS ALTERNATE TABLE_ALT_ITEM TABLE_ALT_ITEM TABLE_ALT_ITEM TABLE_ALT_ITEM TABLE_ALT_ITEM TABLE_ALT_ITEM A SYNC_MASTER=(K84_MLB) TABLE_ALT_ITEM SYNC_DATE=(01/19/2009) PAGE TITLE BOM Configuration TABLE_ALT_ITEM DRAWING NUMBER TABLE_ALT_ITEM Apple Inc TABLE_ALT_ITEM 051-8561 REVISION R C.0.0 TABLE_ALT_ITEM 376S0908 376S0634 ALL TOSHIBA AS ALTERNATE 376S0907 376S0634 ALL FAIRCHILD AS ALTERNATE NOTICE OF PROPRIETARY PROPERTY: BRANCH TABLE_ALT_ITEM THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED TABLE_ALT_ITEM 376S0912 376S0868 ALL ONSEMI(NEW SPEC) AS ALTERNATE PAGE OF 109 SHEET OF 76 SIZE D A Revision History NOTE: All page numbers are csa, not PDF 10/1/2009:INITIAL RELEASE 0.0.1- ALL PAGES SYNC’ED FROM K84 - REPLACED K84 MCP AND CPU PAGES WITH K6 PAGES - UPDATED SCHEMATIC AND PCB PART NUMBER INFO 2009-12-03: Proto release 1.0.0 2009-12-04: 1.1.0 csa 2: Updated CPU block text to include CPU description for both K86 and K87 csa 3: Updated text note to include "K86" in title csa 4: Added BOM entry under Module Parts table to include CULV processor (337S3779) to minimize delta on this page between K86 and K87 per Diana 2009-12-07: 1.2.0 csa 74: csa 37: csa 4: csa 4: csa 69: 2010-02-15: 2.9.0 2010-02-15: 2.10.0 csa 54: 2010-02-16: 2.11.0 Resync with T27 and K6 =PP3V3_S0_CPUVTTISNS’ =PP5V_S0_HDD’ =PP5V_S0_MCPREG’ =PP1V05_S0_MCP_AVDD_UF’ =PPSPD_S0_MEM_B’ =PP3V3_S0_PWRCTL’ =PP3V3_S0_DPCONN’ Deleted net properties for =PP3V3_S3_WLAN Changed C7434 from NOSTUFF to IMVP6:2PHASE per Intersil Added IMVP6:2PHASE to R7413 per Intersil Changed C7428 from 0.47uF => 0.33uF (132S0101) per Intersil Changed component color to Green Cosmetic cleanup Deleted net properties for =PP5V_S3_CAMERA Deleted net properties for =PPBUS_S0_LCDBKLT Added NET_PHYSICAL property to SATA_HDD_D2R_FILT_P and _N Per K87 power component update CSA 74: R7417 changed to 5.90K, C7428 changed to 0.47uF, C7434 changed to 0.033uF CSA 75: R7572 changed to 147K CSA 70: R7015 changed to 56.2K, C7015 changed to 1000pF, C7042 changed to 0.068uF Per K86/K87: add an RC on the LVDS_IG_BKL_PWM CSA 97: R9725 changed to 200ohm, C9799 of 47pF added R9726.1 connection moved to LVDS_IG_BKLPWM 2010-02-18: 2.16.0 Per K86/K87: Hall eff documentation change Substitute 607-6831 for doc purposes CSA 69: J6955 BOMOPTION change to OMIT Added BOM table with 607-6831 for J6955 Per K86/K86 Task: Measure each Power supply in MLB CSA 74: For K86 only: C7434 = 0.1uF added, R7417 changed to 8.25Kohm CSA 12: For K86 only: C1272 = 330uF added Per K86/K87 schematic: change U9700 to 353S2965 for Freescale backlight issue CSA 97: U9700 changed to APN 353S2965 Added parentheses for SYNC_DATE property on all pages that have broken sync 2010-02-18: 2.17.0 Deleted entry in Module Parts table for R6612, R6617, R6630, R6633 since they were removed when we switched from piezo to dynamic speakers Changed J6955 symbol to K87 Hall effect assembly (339S0114) Per K86/K87 schematic: Change audio jack part number for new connector cap CSA 67: J6700 changed from APN 514-0718 to 514-0750 2010-02-25: 2.18.0 Added OMIT to J6955, BOM table to stuff K84 Hall effect connector Per K86/K87 schematic: add additional 639 for differentiation between Foxconn and Molex DIMM connectors CSA 4: MOLEX_DDR_CONN added to Module Parts, removed from Alternate table Added second 639 and EEEE # to BOM table Added PLACEMENT_NOTE for passive deemphasis circuit Changed 1PHASE BOM table to correctly call out 132S0080 (0.22uF) instead of 0.022uF 2010-02-25: 2.19.0, 2.20.0 Per K87:EMC:ESD: System hangs on air/contact discharge to MPM connector CSA 69: C6970, C6971, C6972 of 1000pF (APN 131S0222) added 2009-12-16: 1.8.0 C *** Resynced all synced pages and picked up the following (change notes from T27): csa 18: T27: Swapped USB_EXTB and USB_EXTD for NVRN-612340 (pg 18) Ensure USB_EXTB is on ports 8-11 (NVRN-612340) T27: Changed USB_RBIAS from 931-ohms to 887-ohms per DG v1.3 (pg 18) Design Guide v1.3 updates csa 20; T27: Added CKPLUS_WAIVE properties to dismiss false errors (pg 20) TASK: Waive false CheckPlus errors *** Started syncing the following pages: csa 29,31: Began syncing from T27 per BOM: K87 needs omit on J3100 and J2900 from T27 T27: Added BOMOPTIONs and APNs for Foxconn and Molex SO-DIMM connectors (pp 29, 31) csa 54: Began syncing from T27 per BATT_ISENSE filter change to address lower max sink current on ISL6259 BMON pin (K17 auto-shutdown issue) C5490 changed from CAP_402-0.022UF,10%,16V,CERM-X5R to CAP_402-0.022UF,20%,16V,CERM T27: Added CKPLUS_WAIVE properties to dismiss false errors (pg 54) T27: Added gain note for U5402 and SMC_BATT_ISENSE (pg 54) T27: Changed RC balance on BATT_ISENSE, same time constant (pg 54) csa 57: Began syncing from T27 per T27 schematic bom option for R5714 & R5030 to keep K87 in sync R5714 has BOMOPTION LED:K6_K69, and we need to substitute a different part on csa *** Made the following changes to follow T27 on the following unsynced pages: csa 25: T27: Removed R2575 & R2580 per DG v1.3 (pg 25) per Design Guide v1.3 updates *** Other changes csa 4: Added BOM table to substitute in parts that have BOMOPTION xxx:K6_K69 (to allow sync with T27) Added R5714 (114S0125) to table with BOMOPTION LED:K86_K87 2010-02-26: 2.21.0 Per K87/K86 Task Measure each power supply in mlb CSA 12: C1200, C1204, C1207, C1209, C1211, C1219, C1202, C1216 NOSTUFFED CSA 12: Added pads for 0603 caps (APN 138S0635) Compoonents C1230, C1231, C1232, C1233, C1234, C1235, C1236, C1237 CSA 74: Changed C7434 from 0.033uF to 0.047uF (APN 132S0189) per Liang csa 34: csa 72: Per K87 Proto1: of systems failing graphics noise (Underwater) acoustic spec by up to 3.1dB CSA 12: C1233, C1230, C1237, C1234 changed from NOSTUFF to STUFFED ** MLB_LDO branch 2010-03-09: 0.8.0 Summary of changes for MLB_LDO: CSA 25: U2590 added, APN 353S2971 R2592 of 10K and C2592 of 1UF, C2593 of 1UF added Nets MCP_PLL_LDO_EN and PP3V3_S0_LDO_R added 2010-03-22: A.1.0 Added BOM table entry for MCP89-A02 per Task: Get part numbers for A02 rev Changed K87_MCP BOM group to call out MCP89-A02 Changed U3440 from AP002 part to AP016 (343S0511) per BOM: APN updates for FPF1009 and SAK parts Changed R3454 to 100k, 1% (114S0411) to match T27 and K69 Updated DLY text note for U3440 to match T27 Changed R3440 color to green, deleted WF text note about needing PU Changed L7220 from 152S0693 to 152S0778 per K69 L7260 combo footprint Alternates table on csa already has 152S0778 as alternate to 152S0693 CSA 25: Copied from K6 Added C2599, R2597, R2596, U2593, Q2592, R2599, C2594, U2594, R2598, C2598 with BOMOPTION HTOL_SENSE:YES Added R2594 and R2591 with LDO:ADJ BOMOPTION Changed BOMOPTION names from LDO:YES and LDO:NO to MCPHVDD:P2V5 and MCPHVDD:P3V3 Added BOM TABLE with LDO:FIXED, LDO:ADJ, and HTOL_SENSE:NO stuffing options CSA 50: Removed SMC alias to TP for SMC_NB_MISC_ISENSE to enable sense circuitry connection to SMC Removed SMC_P10 alias to TP_SMC_P10 CSA 8: Added =PP3V42_G3H_OPA330 alias to power U2594 Added =PP3V3_S0_OPA330 alias to power U2593 CSA 4: Added MCPHVDD:P2V5, LDO:FIXED, HTOL_SENSE:YES to BOM Group K86_K87_DEBUG:PROD 2009-12-22: 1.10.0 csa 4: csa 69: csa 74: csa 78: B Per K86: Move to MCP83 Added BOM table entry for MCP83M (337S3876) This is for K86 ONLY Adding entry to minimize delta on csa between K87 and K86 BOMOPTION is "MCP83M" Per K87: Call out LED:K86_K87 BOMOPTION in the K87_MISC BOM group Added LED:K86_K87 BOMOPTION to the K87_MISC BOM group Per K87: remove ON Semi alternate for Q2300 (376S0624) Removed table entry that says 376S0868 is an alternate for 376S0624 Per K86/K87: Replace "S" APNs with "T" APNs for programmed SMC and BR Changed BOOTROM:PROG to call out 341T0251 (SUBASSY, IC, BOOT ROM, K86/K87) Created SMC:PROG_K87 pointing to 341T0252 (SUBASSY, IC, SMC, K87) Created SMC:PROG_K86 pointing to 341T0250 (SUBASSY, IC, SMC, K86) Changed K87_PROGPARTS BOM group to point to SMC:PROG_K87 Per K87: remove OMIT from J6955 and delete BOM table Deleted BOM table for Hall effect assembly Changed text note to say "HALL EFFECT ASSEMBLY" Deleted OMIT BOMOPTION from J6955 Added text note with part numbers for components of the assembly "Assembly APN: 339S0114 - BOM: 639-0680 - PCBF: 820-2801 - MCO: 056-3515 - Conn APN:518S0788" Cosmetic change: moved R7413, C7406 BOMOPTION label so they don’t look like wire name Per K87: Add NOSTUFF to R7872 to disconnect U7870 from ALL_SYS_PWRGD Changed BOMOPTION for R7872 from S0PGOOD_ISL to NOSTUFF 2010-03-22: A.2.0 Per K87: Add cap to DDC line to avoid DDC line glitch issue CSA 93: Added C9303 3300pF cap on DP_CA_DET CSA 25: Changed U2594 power to 3V3_S0 from 3V42_G3H 2010-03-22: A.3.0 CSA 77: Deleted U7740 1.05V LDO circuit to free space for U2592 and current mirror circuit 2010-03-22: A.4.0 Reverted the changes and synced back to A.0.0 Per K87: Add cap to DDC line to avoid DDC line glitch issue CSA 93: Added C9303 3300pF cap on DP_CA_DET 2010-03-22: A.5.0 CSA 25: Added R2591,R2594 for LDO:ADJ option Changed U2592 to LDO:FIXED option CSA 4: Added Alternate part for U2592 LDO 353S2987(TI), 353S2988(Micrel) to 353S2986(Intersil) LDO:FIXED, MCPHVDD:P2V5 added in bom table 2010-03-30: A.7.0 Reverted the changes and synced back to A.2.0 CSA 4: Added Alternate part for U2592 LDO 353S2987(TI), 353S2988(Micrel) to 353S2986(Intersil) LDO:FIXED, MCPHVDD:P2V5 added in bom table 2010-01-06: 1.11.0 csa 7: csa 70: Per K86/K87 functional net property needed on signals in schematics Added the following functional test points under the J5100 LPC+SPI CONN FUNC_TEST group LPCPLUS_GPIO LPC_SERIRQ SMC_TMS CSA 25,49,50: Changed Q2592 gate control pin to SMC_P24 from SMC_P10 2010-04-1: A.9.0 CSA 25: Added R2600 0ohm resistor to help layout change 2010-04-1: A.10.0 *** BROKE SYNC WITH T27 Per K86/K87: update all instances of 376S0786 schematic symbols Updated Q2355 and Q2356 with new schematic symbols Need to resync with T27 once the change has been made there Per K86/K87: Change U7000 to 353S2929 Changed U7000 from 353S2392 to 353S2929 Updated APN text note CSA 25: Changed R2600 refdes to R2550 to match with page# 2010-04-14: B.0.0 rdar://7822714 CSA 69: R6905 kept same 1ohm C6900 changed to 2.2uF 138S0592 CSA 4: Devel BOM# changed to 085-1799 And BOM OPTIONS to K86_K87_DEVELOPMENT_PVT Removed Intersil LDO(353S2986) 2010-01-08: 2.0.0 csa 45: B 2010-03-31: A.8.0 2010-01-07: 1.12.0 csa 23: C 2010-03-04: B.0.0 2009-12-17: 1.9.0 csa 4: Clean up and rerelease schematic 2010-02-18: 2.12.0 Deleted net properties for the following nets: 2009-12-11: 1.7.0 csa 45: csa 74: Broke sync with T27 Per K69/K86/K87 sensor IN1C unreliable U5400 changed from OPA348 to OPA330 C5434 changed to NOSTUFF Added passive deemphasis to SATA HDD D2R lines: 2009-12-10: 1.6.0 csa 69: D *** Resynced with T27 and K6 (no differences) *** Resynced Audio pages with the following changes: -pg 67, added BOM options for U6700, R6712, and R6713 to support MAX14560 and MAX14504 csa 97: Changed R9710 from 7.32K 0402 1% to 7.68K (APN 114S0304) to support old K84 panel csa 4: Added OLD_AUDIO_SWITCH BOM OPTION to K86_K87_COMMON1 2009-12-09: 1.5.0 multiple: Per K86/K87: Add E3T EEE code for K86 to schematic Added row to EEE table for E3T Changed BOMOPTIONs to be mutually exclusive (changed "_" to ":") 2010-02-02: 2.8.0 2009-12-08: 1.4.0 csa 90: csa 98: csa 108: Per K86/K87: Change L3720 to 152S1182 Changed L3720 to 152S1182 (IND,PWR,SHD,4.7UH,20%,0.91A,31X31X12MM) for lower ESR *** Resynced with T27 and K6 (no differences) *** Resynced Audio pages with the following changes: -pg 62, changed R6211 to 22 Ohms -pg 66, added C6602 -pg 67, no stuffed R6712 and R6713 csa 45: Per K87:EMC: Radiated Emissions: Right Audio emissions fail Added L4530, L4531 (APN 155S0137) to SIL connector pins csa 97: Per K86/k87: Compensation settings change to provide more phase margin, reduce ripple Changed R9726 from 22k to 10k (114S0315) and removed NOSTUFF Changed C9705 from 8.2nF to 33nF (132S0131) Changed C9706 from 120pF to 220pF (131S2225) Component value changes per Leo (Intersil): Added R4585, R4586 (51.1 ohm, 1%, 114S0093) and OMITted Added C4585, C4586 (10pF, 5%, 131S0029) and NOSTUFFed Added BOM table to stuff 0-ohms until we get go-ahead for filter csa 34: csa 74: 2010-01-28: 2.7.0 STILL NEED TO UPDATE VALUE OF C7428! csa 8: 2010-01-22: 2.6.0 2009-12-08: 1.3.0 csa 45: 2010-01-19: 2.5.0 R7417 from 5.36k => 6.34k, 1% (114S0296) C7434 from 0.12uF => 0.022uF, 10% (132S0102) Implemented different stuffing options for 1-phase vs 2-phase: Added IMVP6:2PHASE to the following components: R7417, C7428, R7409, R7411, C7406, R7414, C7414, C7413 Added BOM table to insert the following APNs for IMVP6:1PHASE: R7417 = 7.68k 1% (114S0304) C7428 = 0.22uF 10% (132S0102) R7409 = 1.58k 1% (114S0236) R7411 = 255 1% (114S0160) C7406 = 470pF 10% (132S4720) R7414 = 97.6k 1% (114S0410) C7414 = 1000pF 10% (132S0045) C7413 = 100pF 5% (131S1027) Updated table to add new values for 1phase (PWM freq., Max current, Load line) D See page for csa -> PDF mapping 2010-04-14: C.0.0 Per K86/K87: change SATA HDD D2R passive EQ values Removed NOSTUFF from C4585, C4586 Removed OMIT from R4585, R4586 Deleted BOM table that stuffsdel the bypass option Changed R4585, R4586 to 114S0065 (27.4 ohm, 1%) Changed C4585, C4586 to 131S4713 (47pF, 5%) CSA 4: Added Toshiba(376S0908), Fairchild(376S0907) as an alternate to 376S0634 Added ONsemi new spec part(376S0912) as an alternate to Q2300(376S0868) 2010-01-13: 2.1.0 csa 4: Per K86: Update CPU part number to 337S3792 Changed U1000 CPU:1.2GHZ BOMOPTION from 337S3779 to 337S3792 2010-01-13: 2.2.0 csa 4: csa 51: Cosmetic: changed text sizes and alignment Per K86/K87: Production Debug Components Changed 085-1093 to call out K87_DEVEL_PVT instead of K87_DEVEL_ENG Changed K87_COMMON to call out K87_DEBUG_PVT instead of K87_DEBUG_ENG Diff from the two changes above: Toggled: VREFMRGN:YES ==> VREFMRGN:NO BMON:ENG ==> BMON:PROD BKLT:ENG ==> BKLT:PROD SENS_R:ENG ==> SENS_R:PROD Removed: DEBUG_ADC, S0PGOOD_ISL, EFI_DEBUG, MCPPLL_LDO, EXT1V05, MCP_T_DIODE_SENSOR, XDP_CON Unchanged: LPCPLUS, DEVEL_BOM, SMC_DEBUG:YES, XDP Added LPCPLUS_CON to K87_DEVEL_ENG (does not change BOM for DVT) Changed all instances of K87_DEBUG_xxxx to K87_DEBUG:xxxx Changed all instances of K87_DEVEL_xxxx to K87_DEVEL:xxxx (Per K86/K87: Production Debug Components) Changed J5100 BOMOPTION from LPCPLUS to LPCPLUS_CON to unstuff connector at DVT 2010-01-15: 2.3.0 A csa 74: Per K86 CPU loadline, OCP update Keeping K86 and K87 pgs identical for CSA 74, modifying BOM table for IMVP phase on K87’s schematic to reflect changes for K86 IMVP6:1PHASE BOM Table: R7417 changed to 7.87K (APN 114S0305) R7416 added to BOM Table, 16.9K, (APN 114S0336) Added IMVP6:2PHASE BOM option to R7416 for K87’s 13.7K csa 74, csa 79: Per K86/K87 Text note change Cleaned up text notes for 1phase, 2phase, and edp #s per radar request SYNC_MASTER=MASTER Revision History DRAWING NUMBER 2010-01-18: 2.4.0 csa 4: csa 23: csa 37: Per K86/K87: Switch to new BOM group structure Reverted back to ENG BOM, no longer PROD BOM (i.e reverted much of 2.2.0 changes) Changed BOM group structure to match that in the radar (see PDF attached to radar) Net change was to move LPCPLUS to the 639 (from the 085) Switching from Engineering to Production BOM should only require changing PROJECT_PHASE:DEV to PROJECT_PHASE:PROD Per K86/K87: Update MCP83 description on csa Changed description for 337S3876 to "IC,MCP83M-A02,31X31MM,BGA1168" Per K86/K87: Fix schematic symbol for Q2355, Q2356 *** Started syncing with K6 Syncing with K6 to pick up new symbols for Q2355 and Q2356 Should switch syncing back to T27 once it is updated there Per K86/K87 Ethernet series R’s need to be ohmed Changed R3790-R3795 to 116S0004 (0-ohm, 0402) from 22-ohm SYNC_DATE=MASTER PAGE TITLE Apple Inc 051-8561 REVISION R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED C.0.0 BRANCH PAGE OF 109 SHEET OF 76 SIZE D A Revision History NOTE: All page numbers are csa, not PDF See page for csa -> PDF mapping D D C C B B A SYNC_MASTER=MASTER SYNC_DATE=MASTER PAGE TITLE Revision History DRAWING NUMBER Apple Inc 051-8561 REVISION R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED C.0.0 BRANCH PAGE OF 109 SHEET OF 76 SIZE D A FAN CONNECTORS FUNC_TEST I12 I15 I16 PP5V_S0 FAN_RT_PWM FAN_RT_TACH TRUE TRUE TRUE Functional Test Points 62 42 42 (NEED TO ADD GND TP) X16 WIRELESS CONN MIC FUNC_TEST I303 D I238 I237 I239 TRUE TRUE TRUE BI_MIC_N BI_MIC_P BI_MIC_SHIELD 52 53 75 I301 52 53 75 I302 I300 52 53 I299 SPEAKER FUNC_TEST I227 I226 I228 I230 I229 I231 I298 SPKRAMP_L_N_OUT SPKRAMP_L_P_OUT SPKRAMP_R_N_OUT SPKRAMP_R_P_OUT SPKRAMP_SUB_N_OUT SPKRAMP_SUB_P_OUT TRUE TRUE TRUE TRUE TRUE TRUE I293 51 52 I288 51 52 I292 51 52 I295 51 52 I290 51 52 I271 51 52 I289 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE POWER NETS FUNC_TEST PP3V3_S3_BT_F 30 CONN_PCIE_MINI_D2R_P 30 75 CONN_PCIE_MINI_D2R_N 30 75 CONN_PCIE_MINI_R2D_P 30 75 CONN_PCIE_MINI_R2D_N 30 75 PCIE_CLK100M_MINI_CONN_P 30 75 PCIE_CLK100M_MINI_CONN_N 30 75 (NEED TP) 30 PP3V3_WLAN PCIE_WAKE_L 16 30 CONN_USB2_BT_P 30 75 CONN_USB2_BT_N 30 75 AP_CLKREQ_Q_L 30 AP_RESET_CONN_L 30 (NEED TO ADD GND TP) I287 I285 I280 I281 I282 I376 I396 I283 I279 I278 I270 I273 I274 I275 LVDS FUNC_TEST I276 I258 I417 I260 I245 I262 I261 I256 I257 I255 I252 C I253 I254 I250 I251 I313 I246 I247 I248 I249 I395 I297 I294 PP3V3_S0_LCD_DDC_F PP3V3_SW_LCD_PANEL_F TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE PPVOUT_S0_LCDBKLT LVDS_IG_DDC_CLK LVDS_IG_DDC_DATA LVDS_IG_A_DATA_N LVDS_IG_A_DATA_P LVDS_IG_A_DATA_N LVDS_IG_A_DATA_P LVDS_IG_A_DATA_N LVDS_IG_A_DATA_P LVDS_IG_A_CLK_F_N LVDS_IG_A_CLK_F_P LED_RETURN_1 LED_RETURN_2 LED_RETURN_3 LED_RETURN_4 LED_RETURN_5 LED_RETURN_6 PP5V_S3_CAMERA_F USB_CAMERA_CONN_P USB_CAMERA_CONN_N I410 64 I393 (NEED TP) 64 46 64 67 IPD_FLEX_CONN I391 64 I418 64 I374 64 71 I372 64 71 I370 64 71 I371 64 71 I369 64 71 I368 64 71 I361 64 75 I366 64 75 I365 64 67 I363 64 67 I364 64 67 I362 64 67 I360 64 67 I359 64 67 I357 64 I358 64 75 I377 64 75 I378 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE PP3V3_S3 PP18V5_S3 Z2_CS_L Z2_DEBUG3 Z2_MOSI Z2_MISO Z2_SCLK Z2_BOOST_EN Z2_HOST_INTN Z2_CLKIN Z2_KEY_ACT_L Z2_RESET PSOC_MISO PSOC_MOSI PSOC_SCLK SMBUS_SMC_A_S3_SDA SMBUS_SMC_A_S3_SCL PSOC_F_CS_L PICKB_L I268 I269 I267 I265 I266 TRUE TRUE TRUE TRUE TRUE TRUE 33 46 I354 33 35 I355 33 71 I344 33 71 I345 33 71 I346 33 71 I347 I349 I348 I350 FUNC_TEST I352 (NEED TP) I319 I314 I315 I318 I317 I307 TRUE TRUE TRUE TRUE TRUE TRUE PP5V_S0_HDD_FLT SATA_HDD_R2D_P SATA_HDD_R2D_N SATA_HDD_D2R_C_P SATA_HDD_D2R_C_N SYS_LED_ANODE_R I351 33 I353 33 71 I327 33 71 I328 33 71 I329 33 71 I343 33 I342 (NEED TO ADD GND TP) I341 I339 BATT POWER CONN I340 FUNC_TEST (NEED TP) I322 I321 I320 I305 TRUE TRUE TRUE TRUE PPVBAT_G3H_CONN SMBUS_SMC_BSA_SCL SMBUS_SMC_BSA_SDA SYS_DETECT_L I338 54 55 I336 38 74 I337 38 74 I333 54 I335 (NEED TO ADD GND TP) I334 I332 I330 HALL EFFECT CONNECTOR I326 I308 TRUE TRUE 44 I388 43 44 I386 43 44 I385 43 44 I383 43 44 I382 43 44 I381 44 I380 43 44 I397 43 44 I409 43 44 I412 43 44 I411 43 44 I413 43 44 39 I421 39 I442 62 I446 62 75 I445 I444 62 I443 62 I447 62 75 I448 75 I449 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE PP3V42_G3H SPI_CLK SPI_CS0_L SPI_MISO SPI_MOSI SPIROM_USE_MLB LPCPLUS_GPIO LPC_SERIRQ SMC_TMS D 37 72 37 72 19 37 72 37 72 19 37 47 19 37 19 35 37 35 36 37 (NEED TO ADD GND TP) 8 62 75 8 39 8 19 20 23 30 33 46 33 35 36 44 64 46 64 67 48 35 62 19 35 36 62 C 19 35 62 66 64 8 8 (NEED TO ADD GND TP) 43 44 38 74 38 74 43 44 43 44 I331 FUNC_TEST PP3V42_G3H SMC_LID_R FUNC_TEST (NEED TP) (NEED TO ADD GND TP) B I389 PPVCORE_S0_CPU PPVCORE_S0_MCP PP1V05_S0 PP1V5_S0 PP1V8_S0 PP5V_S0 PP5V_S0 PP3V3_S0 PP1V5R1V35_S3 PP3V3_S3 PP5V_S3 PP3V3_S5 PP3V42_G3H PPBUS_G3H PP0V9_ENET PP3V3_ENET PP3V3_G3_RTC PP3V3_WLAN PP5V_SW_ODD PP5V_S0_HDD_FLT PP3V3_S5_AVREF_SMC PP18V5_S3 PP3V3_SW_LCD_PANEL_F PPVOUT_S0_LCDBKLT PP4V5_AUDIO_ANALOG SMC_PM_G2_EN PM_SLP_S4_L PM_SLP_S3_L PP5V_S3_CAMERA_F PP0V9_S5 PPDDRVTT_S0 PP1V05_S0_MCP_PLL_UF PPVTT_S3_DDR_BUF FUNC_TEST PP5V_SW_ODD SMC_ODD_DETECT SATA_ODD_D2R_C_P SATA_ODD_D2R_C_N SATA_ODD_R2D_P SATA_ODD_R2D_N SATA HDD/SIL I390 J5100 LPC+SPI CONN FUNC_TEST (NEED TO ADD GND TP) KEYBOARD CONN I264 I392 (NEED TP) (NEED TO ADD GND TP) SATA ODD CONN FUNC_TEST TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE FUNC_TEST TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE PP3V3_S3 PP3V42_G3H WS_KBD1 WS_KBD2 WS_KBD3 WS_KBD4 WS_KBD5 WS_KBD6 WS_KBD7 WS_KBD8 WS_KBD9 WS_KBD10 WS_KBD11 WS_KBD12 WS_KBD13 WS_KBD14 WS_KBD15_CAP WS_KBD16_NUM WS_KBD17 WS_KBD18 WS_KBD19 WS_KBD20 WS_KBD21 WS_KBD22 WS_KBD23 WS_KBD_ONOFF_L WS_LEFT_SHIFT_KBD WS_LEFT_OPTION_KBD WS_CONTROL_KBD FSB SIGNALS WITH NOTEST 43 I398 NO_TEST=TRUE 43 I399 NO_TEST=TRUE 43 I400 NO_TEST=TRUE FSB_A_L FSB_ADS_L FSB_ADSTB_L I401 NO_TEST=TRUE FSB_D_L 10 14 69 I402 NO_TEST=TRUE FSB_DINV_L 10 14 69 I404 NO_TEST=TRUE I403 NO_TEST=TRUE I405 NO_TEST=TRUE I406 NO_TEST=TRUE I407 NO_TEST=TRUE I408 NO_TEST=TRUE FSB_DSTB_L_N FSB_DSTB_L_P FSB_HIT_L FSB_HITM_L FSB_LOCK_L FSB_REQ_L 43 10 14 69 10 14 69 10 14 69 43 43 43 43 43 43 43 43 10 14 69 B 10 14 69 10 14 69 10 14 69 10 14 69 10 14 69 43 43 43 43 43 43 43 43 43 43 43 43 43 43 43 (NEED TO ADD GND TP) (NEED TP) 54 (NEED TO ADD GND TP) DC POWER CONN A I312 I304 TRUE TRUE FUNC_TEST PP18V5_DCIN_FUSE ADAPTER_SENSE (NEED TP) 54 SYNC_MASTER=MASTER 54 (NEED TO ADD GND TP) SYNC_DATE=MASTER PAGE TITLE FUNC TEST DRAWING NUMBER Apple Inc 051-8561 REVISION R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED C.0.0 BRANCH PAGE OF 109 SHEET OF 76 SIZE D A "S0,S0M" RAILS =PPVCORE_S0_CPU_REG PPVCORE_S0_CPU 39 MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.3 MM VOLTAGE=1.25V MAKE_BASE=TRUE (CPU VCORE PWR) 63 =PP5V_S0_FET PP5V_S0 11 12 =PP5V_S0_HDD 33 MA =PP5V_S0_MCPREG 60 =PPCPUVTT_S0_REG PP1V05_S0 62 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V MAKE_BASE=TRUE =PP1V05_S0_CPU 10 11 12 13 =PP1V05_S0_MCP_FSB 14 20 23 =PP1V05_S0_MCP_PE_DVDD =PPMCPCORE_S0_REG 23 =PP1V05_S0_MCP_SATA_DVDD 20 23 =PP1V05_S0_MCP_PLL_UF_R 61 15 23 =PP1V05_S0_MCP_PLL_IFP 17 24 =PP1V05_S0_MCP_DP0_VDD 17 24 63 =PP3V3_S0_FET 39 20 23 22 PPDDRVTT_S0 =PPDDRVTT_S0_MEM_A =PPDDRVTT_S0_MEM_B 57 29 =PPVTT_S3_DDR_BUF PPVTT_S3_DDR_BUF =PP1V5_S0_FET 37 =PP5V_S0_FAN_RT 42 =PP5V_S0_CPU_IMVP 58 21 =PPVIN_S0_DDRREG_LDO 57 63 =PP3V3_S3_FET =PPVIN_S5_SMCVREF 36 =PP3V42_G3H_SMBUS_SMC_BSA =PP3V42_G3H_PWRCTL 38 62 =PP3V42_G3H_CHGR =PP3V42_G3H_SMCUSBMUX 34 43 35 36 =PP3V3_S5_LPCPLUS 38 62 75 =PP1V5_S0_CPU 11 12 =PP1V5_S0_MCP_PLL_VLDO 61 =PP1V8R1V5_S0_AUDIO 48 =PP3V3_S0_XDP 13 =PP3V3_S0_MCP 20 23 =PP3V3_S0_ODD 33 =PP3V3_S0_SMBUS_SMC_0_S0 38 PP1V8_S0 29 =PP3V3_S3_WLAN 30 =PP3V3_S3_MCP_GPIO 19 =PP3V3_S3_TPAD 37 PP3V3_G3_RTC 19 20 23 =PP3V42_G3H_ONEWIRE 54 =PP3V42_G3H_HALL 54 =PP3V42_G3H_BMON_ISNS 40 45 =PP3V3_S3_BT 30 =PP3V3_S3_SMBUS_SMC_MGMT 38 38 =PP3V3_S0_SMBUS_MCP_0 38 =PP3V3_S0_FAN_RT 42 =PP3V3_S0_AUDIO 48 52 53 =PP5V_S3_EXTUSB 34 =PP3V3_S0_IMVP 58 =PP5V_S3_CAMERA 64 =PP3V3_S0_LCD_DDC 64 =PP5V_S3_AUDIO_AMP 51 =PP5V_S3_REG =PP3V42_G3H_OPA330 43 44 =PP3V3_S3_SMS =PP3V3_S0_SMBUS_SMC_B_S0 56 D 55 62 =PP3V3_S5_SMC PP3V3_S3 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=3.3V MAKE_BASE=TRUE PP5V_S3 54 =PP18V5_DCIN_CONN PP18V5_G3H MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.3 MM VOLTAGE=18.5V MAKE_BASE=TRUE MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=5V MAKE_BASE=TRUE 55 =PPBUS_G3H =PPDCIN_S5_CHGR 55 PPBUS_G3H 39 MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.6V MAKE_BASE=TRUE =PP5V_S3_MCPDDRFET 21 =PP5V_S3_AUDIO 48 50 52 20 23 =PP5V_S3_DEBUG_ISNS 46 =PP3V3_S0_SMC 36 =PP5V_S3_SYSLED 36 26 =PP3V3_S0_MCPTHMSNS 41 =PP5V_S3_TPAD 44 27 =PP3V3_S0_CPUTHMSNS 41 =PP5V_S3_ODD =PP3V3_S0_DPCONN 66 =PP5V_S3_DEBUG_ADC_AVDD 46 =PPSPD_S0_MEM_A 26 =PP5V_S3_DEBUG_ADC_DVDD 46 =PPSPD_S0_MEM_B 27 =PP5V_S3_P5VS0FET 63 =PP3V3_S0_PWRCTL 62 =PP5V_S3_DDRREG 57 =PP3V3_S0_CPUVTTISNS 40 =PP3V3_S0_SMBUS_MCP_1 38 =PP3V3_S0_P1V8S0 61 =PP3V3_S0_MCP_PLL_VLDO 61 =PP3V3_S0_MCPDDRISNS 40 =PP3V3_S0_DEBUGROM 37 =PP3V3_S0_MCPCOREISNS 40 =PP3V3_S0_OPA330 23 =PPVIN_S0_MCPCORE 59 =PPBUS_S0_LCDBKLT =PPVIN_S5_3V3S5 68 56 =PPVIN_S3_5VS3 =PPBUS_S5_CPUREGS_ISNS_R 56 40 =PPVIN_S3_DDRREG C 57 33 40 =PPBUS_S5_CPUREGS_ISNS PPBUS_S5_IMVP_VTT_ISNS MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.3 MM VOLTAGE=12.6V MAKE_BASE=TRUE =PPVIN_S0_CPUVTTS0 =PPVIN_S5_CPU_IMVP 60 58 "S5" RAILS 61 =PP0V9_S5_REG PP0V9_S5 MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V MAKE_BASE=TRUE 48 19 23 =PP0V9_S5_MCP_VDD_AUXC 20 23 =PP0V9_ENET_P0V9ENETFET 63 PP3V3_S5 62 75 MIN_LINE_WIDTH=0.10MM MIN_NECK_WIDTH=0.10MM VOLTAGE=1.8V MAKE_BASE=TRUE "ENET" RAILS =PP3V3R1V8_S0_MCP_IFP_VDD B PP3V42_G3H =PP3V42_G3H_TPAD 105/241 MA =PP1V05_S0_MCP_PLL_OR =PP1V5R1V35_S0_MCPDDRFET 23 62 75 =PP3V3R1V5_S0_AUDIO =PP3V3R1V5_S0_MCP_HDA 61 15 17 18 19 PP1V5_S0 =PP1V8_S0_REG 27 =PP1V5R1V35_S3_MCP_MEM =PP3V3_S0_MCP_PLL_UF MIN_LINE_WIDTH=1.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=1.5V MAKE_BASE=TRUE 61 26 =PPLVDDR_S3_MEM_B =PP3V3_S0_MCP_HVDD MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=0.75V MAKE_BASE=TRUE 63 60 =PP5V_S0_LPCPLUS =PPLVDDR_S3_MEM_A =PP3V3_S0_MCP_GPIO MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 mm VOLTAGE=0.75V MAKE_BASE=TRUE C =PP5V_S0_CPUVTTS0 PP3V3_S0 LVDDR VRef/VTT (0.75V/0.675V) Rails =PPVTT_S0_DDR_LDO 66 MIN_LINE_WIDTH=0.30MM MIN_NECK_WIDTH=0.20MM VOLTAGE=3.3V MAKE_BASE=TRUE 20 23 =PPVCORE_S0_MCP 57 =PP5VR3V3_S0_DPCADET =PP3V42_G3H_REG =PP3V3_S3_PDCISENS =PP1V05_S0_MCP_M2CLK_DLL =PPVCORE_S0_MCPGFXFET 22 54 MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.42V MAKE_BASE=TRUE =PP3V3_S3_VREFMRGN MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V MAKE_BASE=TRUE (MCP VCORE AFTER SENSE RES) 4250 MA =PP5V_S0_MCPFSBFET 75 =PP3V3_S3_SMBUS_SMC_A_S3 =PP1V05_S0_MCP_AVDD_UF PPVCORE_S0_MCP 59 23 =PP1V05_SW_MCP_FSB 59 PP1V5R1V35_S3 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.17 mm VOLTAGE=1.5V MAKE_BASE=TRUE 62 MIN_LINE_WIDTH=0.30 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=5V MAKE_BASE=TRUE =PPVCORE_S0_CPU D =PPDDR_S3_REG "G3H" RAILS "S3" RAILS 63 57 58 PP1V05_S0_MCP_PLL_UF 63 62 61 =PP3V3_ENET_FET PP3V3_ENET MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V MAKE_BASE=TRUE 17 24 56 =PP3V3_ENET_PHY =PP3V3_ENET_MCP_PLL_MAC =PP3V3_ENET_MCP_RMGT MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V MAKE_BASE=TRUE =PP3V3_S5_REG MIN_LINE_WIDTH=0.30MM MIN_NECK_WIDTH=0.20MM VOLTAGE=3.3V MAKE_BASE=TRUE 31 23 18 20 23 ENET1V05:INT =PP1V05_S0_MCP_PLL_UF R0814 23 PP3V3_ENET_PHY_VDDREG MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V MAKE_BASE=TRUE 5% 1/16W MF-LF 402 63 =PP0V9_ENET_FET =PP3V3_ENET_PHY_VDDREG PP0V9_ENET 31 MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0.9V MAKE_BASE=TRUE =PP0V9_ENET_MCP_RMGT B =PP3V3_S5_MCP_GPIO 18 19 =PP3V3_S5_ROM 47 =PP3V3_S0_LCD_PANEL 64 =PP3V3_S5_MCP 20 23 =PP3V3_S5_MCPPWRGD 25 =PP3V3_S5_P3V3S3FET 63 =PP3V3_S5_P3V3S0FET 63 =PP3V3_S5_P0V9S5 61 =PP3V3_S5_P3V3ENETFET 63 =PP3V3_S5_DP_PORT_PWR 66 =PP3V3_S5_VMON 62 =PP3V3_S5_P0V9ENETFET 63 DIGITAL GROUND GND MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM VOLTAGE=0V 20 23 UNUSED MCP PE0[3:0] AVDD/DVDD 20 =PP1V05_S0_MCP_PE_DVDD0 ENET1V05:INT 20 =PP1V05_S0_MCP_PE_AVDD0 RTL8211_REGOUT PP1V05_S0_REG A (CONNECTS TO MCP BALLS) 20 =PP1V05_S0_MCP_PE_DVDD1 (CONNECTS TO MCP BALLS) 20 =PP1V05_S0_MCP_PE_AVDD1 31 =RTL8211_REGOUT MAKE_BASE=TRUE MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2mm VOLTAGE=1.05V (SINCE PE0[3:0] IS NOT USED ON K6) =PP1V05_S0_MCP_PE_DVDD 23 (CONNECTS TO THE DECAPS) PP1V05_S0_MCP_PE_AVDD 23 (CONNECTS TO THE DECAPS) R0812 402 61 =PP1V05_S0_REG MAKE_BASE=TRUE MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2mm VOLTAGE=1.05V ENET1V05:EXT R0813 402 5% PP1V05_ENET 1/16W MF-LF 1/16W MF-LF 5% MAKE_BASE=TRUE VOLTAGE=1.05V MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2mm =PP1V05_ENET_PHY 31 MAKE_BASE=TRUE SYNC_MASTER=MASTER SYNC_DATE=MASTER PAGE TITLE Power Aliases DRAWING NUMBER Apple Inc FIX ME!! OUTPUT OF REGULATOR VALUES R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED 051-8561 REVISION C.0.0 BRANCH PAGE OF 109 SHEET OF 76 SIZE D A PCI-E ALIASES HEATSINK STANDOFFS USB ALIASES 30 PCIE_MINI_R2D_C_P PCIE_AP_R2D_C_P 30 PCIE_MINI_R2D_C_N PCIE_AP_R2D_C_N CONN_PCIE_MINI_D2R_P PCIE_AP_D2R_P ETHERNET ALIASES UNUSED USB PORTS 16 71 MAKE_BASE=TRUE Z0902 Z0901 STDOFF-4.5OD.98H-1.1-3.48-TH STDOFF-4.5OD.98H-1.1-3.48-TH 16 71 72 18 USB_EXTD_P TP_USB_EXTD_P 72 18 USB_EXTD_N TP_USB_EXTD_N 72 18 USB_EXTC_P TP_USB_EXTC_P 72 18 USB_EXTC_N TP_USB_EXTC_N MAKE_BASE=TRUE 75 30 16 71 MAKE_BASE=TRUE 75 30 PCIE_AP_D2R_N CONN_PCIE_MINI_D2R_N 16 71 MAKE_BASE=TRUE LEFT OF CPU 30 ABOVE CPU 30 D 16 71 PCIE_CLK100M_AP_N CONN_PCIE_MINI_R2D_P PCIE_AP_R2D_P 16 71 75 30 PCIE_AP_R2D_N CONN_PCIE_MINI_R2D_N USB_SDCARD_P TP_USB_SDCARD_P 72 18 USB_SDCARD_N TP_USB_SDCARD_N 72 18 USB_WM_P TP_USB_WM_P 71 72 18 USB_WM_N TP_USB_WM_N 72 18 USB_IR_N TP_USB_IR_N MAKE_BASE=TRUE UNUSED GPU LANES 16 =PEG_D2R_N NC_PEG_D2R_N 16 =PEG_D2R_P NC_PEG_D2R_P NO_TEST=TRUE BELOW CPU BELOW MCP NO_TEST=TRUE FAN STANDOFF 16 =PEG_R2D_C_N NC_PEG_R2D_C_N 16 =PEG_R2D_C_P NC_PEG_R2D_C_P 71 16 PEG_CLK100M_P TP_PEG_CLK100M_P 71 16 PEG_CLK100M_N TP_PEG_CLK100M_N NO_TEST=TRUE OMIT Z0905 NO_TEST=TRUE 3P2R2P7 72 18 USB_IR_P TP_USB_IR_P 72 18 USB_T57_P TP_USB_T57_P 72 18 USB_T57_N TP_USB_T57_N MAKE_BASE=TRUE MAKE_BASE=TRUE TP_USB_MINI_N 72 18 71 MAKE_BASE=TRUE TP_USB_MINI_P USB_MINI_N 72 18 MAKE_BASE=TRUE 75 30 STDOFF-4.5OD.98H-1.1-3.48-TH STDOFF-4.5OD.98H-1.1-3.48-TH PCIE_CLK100M_MINI_N USB_MINI_P 72 18 PCIE_CLK100M_AP_P MAKE_BASE=TRUE Z0904 Z0903 PCIE_CLK100M_MINI_P MAKE_BASE=TRUE MAKE_BASE=TRUE 18 MAKE_BASE=TRUE 18 MAKE_BASE=TRUE 18 MAKE_BASE=TRUE 18 MAKE_BASE=TRUE 18 MAKE_BASE=TRUE 18 TP_ENET_RESET_L TP_MCP_CLK25M_BUF0_R TP_ENET_MDC TP_ENET_TX_CTRL TP_ENET_CLK125M_TXCLK TP_ENET_TXD D MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE =PP3V3_ENET_PHY 31 TP_PCIE_CLKREQ_L IN =MCP_IFPA_TXD_P LVDS_IG_A_DATA_P 17 IN =MCP_IFPA_TXD_N LVDS_IG_A_DATA_N OUT 64 71 OUT 64 71 OUT 64 ENET1V05:INT R0915 MAKE_BASE=TRUE 5% 1/16W MF-LF 402 RTL8211_ENSWREG Z0907 17 IN =MCP_IFPAB_DDC_CLK LVDS_IG_DDC_CLK 17 BI =MCP_IFPAB_DDC_DATA LVDS_IG_DDC_DATA IN =MCP_IFPA_TXD_P NC_LVDS_IG_A_DATA_P3 IN =MCP_IFPA_TXD_N NC_LVDS_IG_A_DATA_N3 17 IN =MCP_IFPB_TXC_P NC_LVDS_IG_B_CLK_P IN =MCP_IFPB_TXC_N IN =MCP_IFPB_TXD_P IN =MCP_IFPB_TXD_N IN LCD_IG_BKLT_PWM 17 17 C 17 71 16 PCIE_FW_D2R_P 71 16 PCIE_FW_D2R_N TP_PCIE_FW_D2R_N Z0910 71 16 PCIE_FW_R2D_C_P TP_PCIE_FW_R2D_C_P 3P2R2P7 71 16 PCIE_FW_R2D_C_N TP_PCIE_FW_R2D_C_N OMIT 16 17 TP_PCIE_FW_D2R_P FW_PWR_EN TP_FW_PWR_EN 16 FW_CLKREQ_L TP_FW_CLKREQ_L 16 FW_PME_L TP_FW_PME_L 71 16 PCIE_CLK100M_FW_P TP_PCIE_CLK100M_FW_P 71 16 PCIE_CLK100M_FW_N TP_PCIE_CLK100M_FW_N R0916 64 MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NC_LVDS_IG_B_DATA_P NO_TEST=TRUE MAKE_BASE=TRUE MCP89 ETHERNET VREF NC_LVDS_IG_B_DATA_N NO_TEST=TRUE 17 IN LCD_IG_BKLT_EN LVDS_IG_BKL_ON MAKE_BASE=TRUE 17 IN LCD_IG_PWR_EN LVDS_IG_PANEL_PWR MAKE_BASE=TRUE 17 IN =MCP_IFPA_TXC_P LVDS_IG_A_CLK_P MAKE_BASE=TRUE 17 IN =MCP_IFPA_TXC_N LVDS_IG_A_CLK_N OUT 67 68 OUT 68 23 20 18 OUT 64 OUT 64 71 OUT 64 71 =PP3V3_ENET_MCP_RMGT R0957 1.47K MAKE_BASE=TRUE 1% 1/16W MF-LF 402 MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MCP_RGMII_VREF DISPLAY PORT ALIASES R0958 MAKE_BASE=TRUE UNUSED ETHERNET LANE 16 OMIT ENET_CLKREQ_L 17 IN DP_IG_ML0_P DP_EXT_ML_P OUT 66 75 OUT 71 OUT 66 75 OUT 71 1% 1/16W MF-LF 402 MAKE_BASE=TRUE Z0913 PCIE_CLK100M_ENET_P TP_PCIE_CLK100M_ENET_P 71 16 PCIE_CLK100M_ENET_N TP_PCIE_CLK100M_ENET_N 71 16 PCIE_ENET_D2R_P TP_PCIE_ENET_D2R_P 71 16 PCIE_ENET_D2R_N TP_PCIE_ENET_D2R_N MAKE_BASE=TRUE 3P2R2P7 17 IN DP_IG_ML0_N DP_EXT_ML_N MAKE_BASE=TRUE 18 OUT 1 1.47K MAKE_BASE=TRUE DP_IG_ML_P TP_ENET_CLKREQ_L 71 16 C MAKE_BASE=TRUE LVDS_IG_BKL_PWM MAKE_BASE=TRUE MAKE_BASE=TRUE 31 NC_LVDS_IG_B_CLK_N MAKE_BASE=TRUE LVDS CONNECTOR HOLE OUT 5% 1/16W MF-LF 402 MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE =RTL8211_ENSWREG MAKE_BASE=TRUE NO_TEST=TRUE UNUSED FIREWIRE LANE MLB MOUNTING (TO TOPCASE) SCREW HOLES BI MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2mm ENET1V05:EXT MAKE_BASE=TRUE 17 17 3P2R2P7 31 73 MAKE_BASE=TRUE 17 3P2R2P7 OMIT MAKE_BASE=TRUE LVDS ALIASES OMIT Z0911 31 73 MAKE_BASE=TRUE MLB MOUNTING (TO C BRACKET) SCREW HOLES Z0906 31 73 MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE 3P2R2P7 31 73 MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE OMIT 31 73 MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE PEG_CLKREQ_L 31 73 MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE 16 ENET_RESET_L MCP_CLK25M_BUF0_R ENET_MDC ENET_TX_CTRL ENET_CLK125M_TXCLK ENET_TXD C0958 0.1UF 20% 10V CERM 402 MAKE_BASE=TRUE DP_IG_ML_N MAKE_BASE=TRUE MAKE_BASE=TRUE 71 16 PCIE_ENET_R2D_C_P TP_PCIE_ENET_R2D_C_P 71 16 PCIE_ENET_R2D_C_N TP_PCIE_ENET_R2D_C_N 17 BI DP_IG_AUX_CH0_P DP_IG_AUX_CH_P 17 BI DP_IG_AUX_CH0_N DP_IG_AUX_CH_N 17 IN DP_IG_ML1_P TP_DP_IG_ML1P MAKE_BASE=TRUE MAKE_BASE=TRUE R0970 EMI IO MEDIUM POGO PINS (870-1794 ) OMIT OMIT ZS0900 2.0DIA-MED-EMI-MLB-K84 ZS0901 2.0DIA-MED-EMI-MLB-K84 ZS0902 2.0DIA-MED-EMI-MLB-K84 SM SM SM OMIT 18 IN ENET_ENERGY_DET 100K =PP3V3_ENET_FET OUT 61 62 63 5% 1/16W MF-LF 402 B 17 IN DP_IG_ML1_N TP_DP_IG_ML1N 17 BI DP_IG_AUX_CH1_P TP_DP_IG_AUX_CH1P 17 BI DP_IG_AUX_CH1_N TP_DP_IG_AUX_CH1N 17 OUT DP_IG_HPD0 DP_EXT_HPD 65 BI 65 BI DP_AUX_CH_C_N DP_AUX_CH_C_P DP_CA_DET DP_EXT_AUX_CH_C_N DP_EXT_AUX_CH_C_P 65 OUT DP_EXT_CA_DET BI 65 71 BI 65 71 MAKE_BASE=TRUE MAKE_BASE=TRUE CPU FSB FREQUENCY STRAPS MAKE_BASE=TRUE MAKE_BASE=TRUE 69 10 MAKE_BASE=TRUE IN CPU_BSEL MAKE_BASE=TRUE =MCP_BSEL OUT 14 MAKE_BASE=TRUE IN 14 66 CPU_PECI_MCP TP_CPU_PECI_MCP MAKE_BASE=TRUE MAKE_BASE=TRUE BI 66 75 BI 66 75 MAKE_BASE=TRUE BSEL IN 0 0 1 1 OMIT ZS0909 2.0DIA-MED-EMI-MLB-K84 ZS0911 2.0DIA-MED-EMI-MLB-K84 ZS0903 2.0DIA-MED-EMI-MLB-K84 SM SM SM SM OMIT R0940 OMIT OMIT 17 DP_IG_HPD1 100K 0 1 0 1 1 1 266 133 200 (166) 333 100 (400) (RSVD) SMC ALIASES 5% 1/16W MF-LF 402 B 66 MAKE_BASE=TRUE ZS0908 2.0DIA-MED-EMI-MLB-K84 FSB MHZ MAKE_BASE=TRUE 35 SMC_SYS_KBDLED TP_SMC_SYS_KBDLED MAKE_BASE=TRUE MCP89 MISC ALIASES 19 EMI TALL POGO PINS (870-1698 ) OMIT ZS0904 2.0DIA-TALL-EMI-MLB-M97-M98 OMIT ZS0905 OMIT ZS0906 2.0DIA-TALL-EMI-MLB-M97-M98 2.0DIA-TALL-EMI-MLB-M97-M98 SM SM OMIT ZS0910 2.0DIA-TALL-EMI-MLB-M97-M98 2.0DIA-TALL-EMI-MLB-M97-M98 SM SM MCP_MEM_VDD_SEL_1V5 CHARGER SIGNAL TP_MCP_MEM_VDD_SEL_1V5 55 IN =CHGR_ACOK SMC_BC_ACOK OUT 35 36 54 MAKE_BASE=TRUE SM 1 IN MAKE_BASE=TRUE OMIT ZS0907 1 CPU VCORE ALIASES OMIT ZS0912 2.0DIA-TALL-EMI-MLB-M97-M98 OMIT ZS0913 OMIT ZS0914 2.0DIA-TALL-EMI-MLB-M97-M98 2.0DIA-TALL-EMI-MLB-M97-M98 SM 58 IN IMVP6_VR_TT TP_IMVP6_VR_TT 58 IN IMVP6_NTC TP_IMVP6_NTC MAKE_BASE=TRUE OMIT ZS0915 OMIT ZS0919 2.0DIA-TALL-EMI-MLB-M97-M98 2.0DIA-TALL-EMI-MLB-M97-M98 SM MAKE_BASE=TRUE SM SM SM 1 1 A SYNC_MASTER=(K84_MLB) SYNC_DATE=(02/04/2009) PAGE TITLE SIGNAL ALIAS EMI THINBC POGO PINS (870-1820 ) OMIT ZS0917 2.0DIA-MLB-THIN-BC-K84 SM DRAWING NUMBER Apple Inc OMIT ZS0918 OMIT ZS0916 2.0DIA-MLB-THIN-BC-K84 2.0DIA-MLB-THIN-BC-K84 SM SM NOSTUFF R NOTICE OF PROPRIETARY PROPERTY: 2.0DIA-MLB-THIN-BC-K84 SM THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED 1 C.0.0 ZS0920 1 051-8561 REVISION BRANCH PAGE OF 109 SHEET OF 76 SIZE D A OMIT 69 14 BI 69 14 BI 69 14 BI 69 14 BI 69 14 BI 69 14 BI 69 14 BI 69 14 BI 69 14 BI 69 14 BI 69 14 BI 69 14 BI 69 14 BI 69 14 BI 69 14 BI 69 14 BI 69 14 BI 69 14 BI 69 14 BI 69 14 BI 69 14 BI 69 14 BI 69 14 BI 69 14 BI 69 14 BI 69 14 BI 69 14 BI 69 14 BI 69 14 BI 69 14 BI 69 14 BI 69 14 BI 69 14 IN 69 14 OUT 69 14 IN 69 14 IN 69 14 IN 69 14 IN 69 14 IN FSB_REQ_L FSB_REQ_L FSB_REQ_L FSB_REQ_L FSB_REQ_L K3 H2 K2 J3 L1 REQ0* REQ1* REQ2* REQ3* REQ4* FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_ADSTB_L Y2 U5 R3 W6 U4 Y5 U1 R4 T5 T3 W2 W5 Y4 U2 V4 W3 AA4 AB2 AA3 V1 A17* A18* A19* A20* A21* A22* A23* A24* A25* A26* A27* A28* A29* A30* A31* A32* A33* A34* A35* ADSTB1* CPU_A20M_L CPU_FERR_L CPU_IGNNE_L A6 A20M* A5 FERR* C4 IGNNE* CPU_STPCLK_L CPU_INTR CPU_NMI CPU_SMI_L D5 C6 B4 A3 TP_CPU_RSVD_M4 TP_CPU_RSVD_N5 TP_CPU_RSVD_T2 TP_CPU_RSVD_V3 TP_CPU_RSVD_B2 TP_CPU_RSVD_F6 TP_CPU_RSVD_D2 TP_CPU_RSVD_D22 TP_CPU_RSVD_D3 M4 N5 T2 V3 B2 F6 D2 D22 D3 STPCLK* LINT0 LINT1 SMI* DEFER* DRDY* DBSY* BR0* IERR* INIT* H1 E2 G5 FSB_ADS_L FSB_BNR_L FSB_BPRI_L H5 F21 E1 FSB_DEFER_L FSB_DRDY_L FSB_DBSY_L F1 D20 B3 LOCK* H4 69 BI 14 69 BI 14 69 BI 14 69 BI 14 69 BI 14 69 BI 14 69 FSB_BREQ0_L BI 14 69 CPU_IERR_L CPU_INIT_L IN FSB_LOCK_L BI RESET* RS0* RS1* RS2* TRDY* C1 F3 F4 G3 G2 FSB_CPURST_L FSB_RS_L FSB_RS_L FSB_RS_L FSB_TRDY_L HIT* HITM* G6 E4 FSB_HIT_L FSB_HITM_L BPM0* BPM1* BPM2* BPM3* PRDY* PREQ* TCK TDI TDO TMS TRST* DBR* AD4 AD3 AD1 AC4 AC2 AC1 AC5 AA6 AB3 AB5 AB6 C20 XDP_BPM_L XDP_BPM_L XDP_BPM_L XDP_BPM_L XDP_BPM_L XDP_BPM_L XDP_TCK XDP_TDI XDP_TDO XDP_TMS XDP_TRST_L XDP_DBRESET_L =PP1V05_S0_CPU 11 12 13 R10001 54.9 1% 1/16W MF-LF 402 D 14 69 14 69 IN 13 14 69 IN 14 69 IN 14 69 IN 14 69 IN 14 69 BI 14 69 BI 14 69 BI 13 69 BI 13 69 BI 13 69 BI 13 69 BI 13 69 OMIT 69 14 BI R10011 69 14 BI 69 14 BI 1% 1/16W MF-LF 402 69 14 BI 69 14 BI 69 14 BI 54.9 69 14 BI IN 10 13 69 69 14 BI IN 10 13 69 69 14 BI OUT 10 13 69 69 14 BI IN 10 13 69 69 14 BI IN 10 13 69 69 14 BI R10021 69 14 BI 69 14 BI 5% 1/16W MF-LF 402 69 14 BI 69 14 BI 69 14 BI 69 14 BI 69 14 BI 69 14 BI 69 14 BI 69 14 BI 69 14 BI 69 14 BI BI OUT 13 25 13 69 68 THERMAL PROCHOT* THERMDA THERMDC THERMTRIP* CPU_PROCHOT_L CPU_THERMD_P CPU_THERMD_N C7 PM_THRMTRIP_L OUT OUT 41 75 OUT 41 75 OUT 14 36 69 14 36 69 H CLK BCLK0 BCLK1 RSVD0 RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 RSVD6 RSVD7 RSVD8 D21 A24 B25 A22 A21 FSB_CLK_CPU_P FSB_CLK_CPU_N IN 14 69 69 14 BI IN 14 69 69 14 BI 69 14 BI 69 14 BI 69 14 BI 69 14 BI 69 14 BI 69 14 BI 69 14 BI 69 14 BI 69 14 BI 69 14 BI 69 14 BI 69 14 BI R1005 CPU JTAG Support R1090 B 69 13 10 XDP_TMS 69 13 10 69 13 10 54.9 XDP_TDI 1% 1/16W MF-LF 402 XDP_TDO R1092 PLACE_NEAR=J1300.51:12.7 mm 1% 1/16W MF-LF 402 54.9 1% 1/16W MF-LF 402 R1091 1K 54.9 PLACE_NEARs: R1005.2: U1000.AD26:12.7 mm R1006.1: U1000.AD26:12.7 mm C1014.1: U1000.AF26:12.7 mm 69 29 R1006 2.0K 1% 1/16W MF-LF 402 NO STUFF C1014 NO STUFF 1% 1/16W MF-LF 402 54.9 69 13 10 XDP_TCK 69 13 10 XDP_TRST_L R1094 649 1% 1/16W MF-LF 402 10% 16V X5R 402 R1010 NO STUFF R1093 0.1uF 5% 1/16W MF-LF 402 R10111 1K 5% 1/16W MF-LF 402 2 NO STUFF 69 OUT 69 OUT 69 OUT FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_DSTB_L_N FSB_DSTB_L_P FSB_DINV_L E22 F24 E26 G22 F23 G25 E25 E23 K24 G24 J24 J23 H22 F26 K22 H23 J26 H26 H25 D0* D1* D2* D3* D4* D5* D6* D7* D8* D9* D10* D11* D12* D13* D14* D15* DSTBN0* DSTBP0* DINV0* FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_DSTB_L_N FSB_DSTB_L_P FSB_DINV_L N22 K25 P26 R23 L23 M24 L22 M23 P25 P23 P22 T24 R24 L25 T25 N25 L26 M26 N24 D16* D17* D18* D19* D20* D21* D22* D23* D24* D25* D26* D27* D28* D29* D30* D31* DSTBN1* DSTBP1* DINV1* CPU_GTLREF CPU_TEST1 CPU_TEST2 TP_CPU_TEST3 CPU_TEST4 TP_CPU_TEST5 TP_CPU_TEST6 TP_CPU_TEST7 CPU_BSEL CPU_BSEL CPU_BSEL AD26 C23 D25 C24 AF26 AF1 A26 C3 B22 B23 C21 GTLREF TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 TEST7 BSEL0 BSEL1 BSEL2 U1000 PENRYN FCBGA OF DATA GRP BI ADS* BNR* BPRI* DATA GRP BI 69 14 FCBGA OF DATA GRP BI 69 14 PENRYN DATA GRP 69 14 U1000 CONTROL BI A3* A4* A5* A6* A7* A8* A9* A10* A11* A12* A13* A14* A15* A16* ADSTB0* XDP/ITP SIGNALS BI 69 14 J4 L5 L4 K5 M3 N2 J1 N3 P5 P2 L2 P4 P1 R1 M1 ADDR GROUP0 BI 69 14 FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_ADSTB_L ADDR GROUP1 BI 69 14 ICH C BI 69 14 RESERVED D 69 14 MISC D32* D33* D34* D35* D36* D37* D38* D39* D40* D41* D42* D43* D44* D45* D46* D47* DSTBN2* DSTBP2* DINV2* Y22 AB24 V24 V26 V23 T22 U25 U23 Y25 W22 Y23 W24 W25 AA23 AA24 AB25 Y26 AA26 U22 FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_DSTB_L_N FSB_DSTB_L_P FSB_DINV_L D48* D49* D50* D51* D52* D53* D54* D55* D56* D57* D58* D59* D60* D61* D62* D63* DSTBN3* DSTBP3* DINV3* AE24 AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21 AC22 AD23 AF22 AC23 AE25 AF24 AC20 FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_DSTB_L_N FSB_DSTB_L_P FSB_DINV_L COMP0 COMP1 COMP2 COMP3 R26 U26 AA1 Y1 CPU_COMP CPU_COMP CPU_COMP CPU_COMP DPRSTP* DPSLP* DPWR* PWRGOOD SLP* PSI* E5 B5 D24 D6 D7 AE6 69 69 69 69 CPU_DPRSTP_L CPU_DPSLP_L FSB_DPWR_L CPU_PWRGD FSB_CPUSLP_L CPU_PSI_L BI 14 69 BI 14 69 BI 14 69 BI 14 69 BI 14 69 BI 14 69 BI 14 69 BI 14 69 BI 14 69 BI 14 69 BI 14 69 BI 14 69 BI 14 69 BI 14 69 BI 14 69 BI 14 69 BI 14 69 BI 14 69 BI 14 69 BI 14 69 BI 14 69 BI 14 69 BI 14 69 BI 14 69 BI 14 69 BI 14 69 BI 14 69 BI 14 69 BI 14 69 BI 14 69 BI 14 69 BI 14 69 BI 14 69 BI 14 69 BI 14 69 BI 14 69 BI 14 69 BI 14 69 IN 14 58 69 IN 14 69 IN 14 69 IN 13 14 69 IN 14 69 OUT C B R10231 R10211 54.9 54.9 1% 1/16W MF-LF 402 58 1% 1/16W MF-LF 402 1 R1022 R1020 27.4 R1012 27.4 1% 1/16W MF-LF 402 1K 5% 1/16W MF-LF 402 1% 1/16W MF-LF 402 PLACE_NEARs: 1% 1/16W MF-LF 402 R1020.1: U1000.R26:12.7 mm R1021.1: U1000.U26:12.7 mm R1022.1: U1000.AA1:12.7 mm R1023.1: U1000.Y1:12.7 mm A SYNC_MASTER=T27_MLB SYNC_DATE=02/16/2010 PAGE TITLE CPU FSB DRAWING NUMBER Apple Inc 051-8561 R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED SIZE D REVISION C.0.0 BRANCH PAGE 10 OF 109 SHEET 10 OF 76 A S5 Rail Enables & PGOOD 62 State 35 IN 75 SMC_PM_G2_EN IN_A MAKE_BASE=TRUE P3V3S5_EN_L OUT_A* (IPD) PP3V3_S5 Threshold: ?? (OD,IPU) Run (S0) 1 Sleep (S3) 1 Soft-Off (S5) 0 Battery Off (G3Hot) 0 (OD,IPU) P0V9S5_EN VFRQ:SLPS4 =P0V9S5_EN OUT 61 PM_SLP_S4_L Q7860 SSM3K15FV PM_SLP_S3_L 55 D R7860 10K OUT VFRQ:LOW D SOD-VESM-HF R7863 66 62 35 19 5% 1/16W MF-LF 402 G S CHGR_VFRQ_GATE 5% 1/16W MF-LF 402 THRM PAD CHGR_VFRQ VFRQ:SLPS4&VFRQ:SLPS3 VFRQ:SLPS3 0.033UF (OD,IPU) 5% 1/16W MF-LF 402 10% 16V X5R 402 OUT_B DLY GND 220PF 10K 5% 1/16W MF-LF 402 C7801 DLY_1C 5% 25V CERM 402 56 MAKE_BASE=TRUE 2:1 + 1.3V - C7841 R78611 62 36 35 19 OUT =PP3V42_G3H_CHGR 55 VFRQ:SLPS4&VFRQ:SLPS3&VFRQ:HIGH R7864 =P3V3S5_EN_L MAKE_BASE=TRUE OUT_A IN_B S5PGOOD_DLY PM_SLP_S3_L Internal pull-ups 100K +/- 20% TDFN WLAN Enable Generation D U7840 SLG4AP012 =P5V3V3_REG_EN OUT PM_SLP_S4_L VDD 20% 10V CERM 402 ISL6259 Frequency Select SMC_PM_G2_ENABLE CRITICAL 0.1uF Power Control Signals =PP3V42_G3H_PWRCTL C7840 56 "WLAN" = ("S3" && "AP_PWR_EN" && ("AC" || "S0")) NOTE: S3 term is guaranteed by S3 pull-up on open-drain AP_PWR_EN signal RSMRST_PWRGD OUT MAKE_BASE=TRUE PM_WLAN_EN_L 35 Q7890 D SSM6N15FEAPE S3 Rail Enables AC_OR_S0_L 5% 1/16W MF-LF 402 Q7890 PP3V3_S0_VMON =P5VS3_EN_L OUT IN G C7813 36 35 19 IN S S G 75 62 75 62 66 62 35 19 IN 62 PM_SLP_S3_L R7812 P3V3S3_EN =P3V3S3_EN MAKE_BASE=TRUE 5% 1/16W MF-LF 402 OUT 63 NO STUFF 0.47UF 19 IN PM_SLP_RMGT_L =P3V3ENET_EN =P0V9ENET_EN MAKE_BASE=TRUE OUT 63 OUT 63 R78101 100K =DDRREG_EN =USB_PWR_EN C7810 OUT OUT 57 63 61 34 PM_SLP_S3_L 1% 1/16W MF-LF 402 15K 5% 1/16W MF-LF 402 S0PGOOD_BJT R7823 VMON_3V3_DIV OUT R7881 R7879 100K R7880 R7882 R7883 33K 22K 15K 10K 5% 1/16W MF-LF 402 5% 1/16W MF-LF 402 5% 1/16W MF-LF 402 5% 1/16W MF-LF 402 5% 1/16W MF-LF 402 2 R7884 OUT 63 =PBUSVSENS_EN OUT 39 75 62 PP1V5_S0 OUT 63 =P1V8S0_EN OUT 61 =P1V5S0_EN OUT 63 =MCPCORES0_EN OUT 59 OUT 60 MAKE_BASE=TRUE MAKE_BASE=TRUE =CPUVTTS0_EN MAKE_BASE=TRUE C7881 0.47UF 10% 6.3V CERM-X5R 402 C7880 0.47UF 10% 6.3V CERM-X5R 402 C7882 0.47UF 10% 6.3V CERM-X5R 402 C7883 0.47UF 10% 6.3V CERM-X5R 402 ALL_SYS_PWRGD MAKE_BASE=TRUE OUT 25 35 S0PGOOD_BJT R7828 S0PGOOD_BJT_L VMON_Q2_BASE S0PGOOD_BJT 10 B 5% 1/16W MF-LF 402 Q1 NC NC CRITICAL S0PGOOD_BJT VMON_Q3_BASE Q2 Q7820 Q3 ASMCC0179 DFN2015H4-8 Q4 1K 7.15K 5% 1/16W MF-LF 402 1% 1/16W MF-LF 402 VMON_Q4_BASE Worst-Case Thresholds: Q2: 0.XXXV Q3: 0.640V Q4: 0.660V 353S2809 VMON_EMITTER S0PGOOD_BJT R78271 100 5% 1/16W MF-LF 402 3.3V w/Divider: 2.345V MAKE_BASE=TRUE R7825 PP1V05_S0 R7822 =P3V3S0_EN MAKE_BASE=TRUE A 10 5% 1/16W MF-LF 402 S0PGOOD_BJT CPUVTTS0_EN 1K S0PGOOD_BJT MCPCORES0_EN 353S2718 5% 1/16W MF-LF 402 =P5VS0_EN R7872 S0PGOOD_RST_L THRM_PAD R7824 62 P1V5S0_EN 5% 1/16W MF-LF 402 P1V8S0_EN RST* NOSTUFF NC 5% 1/16W MF-LF 402 5.1K P3V3S0_EN S0PGOOD_BJT 5% 1/16W MF-LF 402 MAKE_BASE=TRUE 5% 1/16W MF-LF 402 1K 61 10K PM_SLP_S3_R_L MR* 1% 1/16W MF-LF 402 15.0K R7859 IN MCPPLLLDO_PGOOD 150K R7821 MAKE_BASE=TRUE 62 35 19 66 CPUVTTS0_PGOOD IN =PP3V3_S5_VMON S0PGOOD_BJT P1V05ENET_EN 100 IN R78261 R7850 S0 Rail Enables 60 61 GND PP3V3_S0 R7851 VDDA U7870 V2MON V3MON V4MON S0PGOOD_BJT =P1V05ENET_EN MCPCORES0_PGOOD ISL88042IRTJJZ TDFN (IPU) EXT1V051 P5V3V3_PGOOD IN VDD PP3V3_S0 PP1V5_S0 PP1V05_S0 =PP3V3_ENET_FET EXT1V05 10% 6.3V CERM-X5R 402 IN 20% 10V CERM 402 75 62 0.47UF 5% 1/16W MF-LF 402 B DDRREG_EN MAKE_BASE=TRUE 0.1uF C 56 59 CRITICAL S0PGOOD_ISL S0 Rail PGOOD (BJT Version) R7811 5% 1/16W MF-LF 402 1% 1/16W MF-LF 402 C7870 ENET Rail Enables C7812 10% 6.3V CERM-X5R 402 5.1K S0PGOOD_ISL Worst-Case Thresholds: VDD: 2.9140V V2MON: 3.000V V3MON: 0.610V V4MON: 0.610V PM_SLP_S4_L R78711 SMC_ADAPTER_EN 10% 10V CERM 402 S MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V 20.0K SOT563 56 0.068UF SOT563 62 36 35 19 S0PGOOD_ISL Q7891 SSM6N15FEAPE SOT563 NO STUFF G D SSM6N15FEAPE MAKE_BASE=TRUE Q7891 D AP_PWR_EN 10K 5% 1/16W MF-LF 402 S0 Rail PGOOD (ISL Version) IN S 68K SSM6N15FEAPE R78201 1% 1/16W MF-LF 402 30 19 R78132 D =PP3V3_S0_PWRCTL R7870 G P5VS3_EN_L 10K =PP3V42_G3H_PWRCTL C PP5V_S0 S0PGOOD_ISL SOT563 62 S0 Rail PGOOD Circuitry 30 OUT Pull-up is with power FET P0V9S5_PGOOD IN 61 C7884 SYNC_MASTER=(T27_MLB) 0.47UF 10% 6.3V CERM-X5R 402 SYNC_DATE=(10/27/2009) PAGE TITLE Power Sequencing DRAWING NUMBER Apple Inc 051-8561 R VTT Rail Enable 21 19 IN MCP_MEM_VDD_EN VTT rail must ramp up in about the same time as MEMVDD rail (Q2300) =DDRVTT_EN MAKE_BASE=TRUE Unused PGOOD signal 57 OUT 57 IN DDRREG_PGOOD TP_DDRREG_PGOOD MAKE_BASE=TRUE DO NOT SYNC T27, ENET RAILS CHANGED NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED SIZE D REVISION C.0.0 BRANCH PAGE 78 OF 109 SHEET 62 OF 76 A 3.3V S3 FET CRITICAL SM =PP3V3_S3_FET =PP3V3_S5_P3V3S3FET 0.033UF 10K 10% 16V X5R 402 5% 1/16W MF-LF 402 D P3V3S3_EN_L Q7903 FDC638P CRITICAL CHANNEL P-TYPE Q7920 FDC638P_G SM RDS(ON) 48 mOhm @4.5V LOADING 0.811 A (EDP) =PP1V5_S0_FET =PPDDR_S3_REG 57 C7910 1 P3V3S3_SS 0.033UF 10K 10% 16V X5R 402 5% 1/16W MF-LF 402 2 10% 16V CERM 402 D C7921 R79221 0.01UF 5% 1/16W MF-LF 402 SSM3K15FV MOSFET R7910 47K 3.3V S3 FET C7911 R79121 1.5V S0 FET Q7910 FDC638P_G R7920 P1V5S0_EN_L1 SOD-VESM-HF 47K Q7923 SSM3K15FV 1.5V S0 FET MOSFET C7920 0.01UF P1V5S0_SS 5% 1/16W MF-LF 402 D FDC638P CHANNEL P-TYPE RDS(ON) 48 mOhm @4.5V LOADING 0.795 A (EDP) 10% 16V CERM 402 D SOD-VESM-HF G 62 S =P3V3S3_EN IN 62 IN =P1V5S0_EN G S CRITICAL Q7930 3.3V S0 FET C7931 R7932 P3V3S0_EN_L Q7905 G FDC606P CHANNEL P-TYPE RDS(ON) 26 MOHM @4.5V 3.3V ENET FET P3V3S0_SS 62 S =PP3V3_S5_P3V3ENETFET R79621 5% 1/16W MF-LF 402 0.033UF R7960 D =PP3V3_ENET_FET C 61 62 G C7960 0.01UF P3V3ENET_EN_L1 100K P3V3ENET_SS 5% 1/16W MF-LF 402 D Q7961 C7961 10% 16V X5R 402 10K S =P3V3S0_EN IN SOT-23-HF SOD-VESM-HF G Q7960 NTR4101P 1.240 A (EDP) 10% 16V CERM 402 D CRITICAL @ 2.5V Vgs: Rds(on) = 90mOhm max I(max) = 1.7A (85C) 0.01UF 5% 1/16W MF-LF 402 SSM3K15FV MOSFET LOADING C7930 R7930 47K 3.3V S0 FET 10% 16V X5R 402 5% 1/16W MF-LF 402 =PP3V3_S0_FET 0.033UF 100K C D S =PP3V3_S5_P3V3S0FET FDC606P_G SOT-6 10% 16V CERM 402 SSM6N15FEAPE SOT563 G 62 S =P3V3ENET_EN IN MOBILE: Recommend aliasing PM_SLP_RMGT_L and =P3V3ENET_EN Nets separated on ARB for alternate power options 0.9V ENET FET B =PP0V9_ENET_P0V9ENETFET C7990 B 0.1UF R7991 47K 5% 1/16W MF-LF 402 Q7947 D D MOSFET TPCP8102 CHANNEL P-TYPE =PP0V9_ENET_FET D G S RDS(ON) 13.5 MOHM @4.5V LOADING 1.569 A (EDP) G 62 IN Q7990 C7991 0.01UF 10% 16V CERM 402 P0V9ENET_EN_L_RC SOT563 0.01UF P5VS0_SS 10K 1% 1/16W MF-LF 402 Q7991 SOT23 SSM6N15FEAPE C7943 R7944 P0V9ENET_EN_L 10% 16V X5R 402 P5VS0_EN_L S G 47K SSM3K15FV C7942 0.033UF 5% 1/16W MF-LF 402 A =PP5V_S0_FET 23V1K-SM R79431 Q7991 D SOT563 Q7948 =PP5V_S3_P5VS0FET SI2312BDS G SSM6N15FEAPE 1% 1/16W MF-LF 402 5.0V LT S0 FET Q7990 S 69.8K CRITICAL CRITICAL D P0V9ENET_SS 5% 1/16W MF-LF 402 R7992 TPCP8102 100K 1 376S0778 5.0V S0 FET R7990 =PP3V3_S5_P0V9ENETFET (Used to be 5.0V LT S0 FET) 20% 10V CERM 402 MOSFET SI2312BDS Type N-Channel Rds(on) 37 mOhm @2.5V ID(max) 3.25 A @85C Loading 0.140 A (EDP) S =P0V9ENET_EN 10% 16V CERM 402 SYNC_MASTER=MASTER SYNC_DATE=MASTER PAGE TITLE POWER FETS SOD-VESM-HF DRAWING NUMBER G 62 IN =P5VS0_EN Apple Inc S R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED DO NOT SYNC FROM K84 ADDED ENET CIRCUITS, REMOVED 1V05 ENET CIRCUIT 051-8561 SIZE D REVISION C.0.0 BRANCH PAGE 79 OF 109 SHEET 63 OF 76 A D D CHECK IF LVDS_IG_PANEL_PWR GLITCHES ON POWER UP LVDS_IG_PANEL_PWR R9014 1K 5% 1/16W MF-LF 402 APN 353S2805 LCD CONNECTOR CRITICAL U9000 FPF1009 =PP3V3_S0_LCD_PANEL VIN_1 VIN_2 C9009 0.1UF GND LVDS CONNECTOR:518S0650 L9004 ONMFET-2X2-8IN FERR-120-OHM-1.5A PP3V3_SW_LCD_PANEL VOUT_1 C9011 0.1UF 10% 16V X5R 402 10% 16V X5R 402 FOUR GROUNDING VIAS SHOULD BE DISTRIBUTED ALONG THE GROUND SHAPE THAT BOUND THE CONNECTOR BODY CRITICAL J9000 0402-LF VOLTAGE=3.3V MIN_LINE_WIDTH=0.30 MM MIN_NECK_WIDTH=0.20 MM VOUT_2 THRM PAD PLACE_NEAR=J9000.32:1MM PLACE_NEAR=L9004.1:1MM C9015 C9012 PLACE_NEAR=J9000.32:1MM PLACE_NEAR=L9004.1:1MM C9010 0.001UF 10UF 10% 50V X7R 402 20% 6.3V X5R 603 CRITICAL C F-RT-SM 31 32 0.001UF 10% 50V X7R 402 2 PP3V3_SW_LCD_PANEL_F MIN_NECK_WIDTH=0.20 MM MIN_LINE_WIDTH=0.30 MM VOLTAGE=3.3V L9008 120-OHM-0.3A-EMI 20474-030E-11 PP3V3_S0_LCD_DDC_F MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=3.3V 0402-LF 71 71 =PP3V3_S0_LCD_DDC 71 1 R9008 100K 5% 1/16W MF-LF 402 9 LVDS_IG_A_DATA_N LVDS_IG_A_DATA_P (LVDS DDC POWER) R9009 71 100K 71 5% 1/16W MF-LF 402 71 75 75 LVDS_IG_DDC_CLK LVDS_IG_DDC_DATA LVDS_IG_A_DATA_N LVDS_IG_A_DATA_P LVDS_IG_A_DATA_N LVDS_IG_A_DATA_P LVDS_IG_A_CLK_F_N LVDS_IG_A_CLK_F_P CRITICAL L9080 90-OHM-200MA 67 46 AMC2012-SM SYM_VER-1 71 71 LVDS_IG_A_CLK_N LVDS_IG_A_CLK_P 1 NC PPVOUT_S0_LCDBKLT C9017 1000PF 5% 50V C0G-CERM 603 67 67 PLACE_NEAR=J9000.19:1MM 67 L9050 =PP5V_S3_CAMERA FERR-120-OHM-1.5A 0402-LF B LED_RETURN_6 LED_RETURN_5 LED_RETURN_4 LED_RETURN_3 67 LED_RETURN_2 67 LED_RETURN_1 67 PP5V_S3_CAMERA_F NC MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=5V C9016 0.1uF PLACE_NEAR=L9050.2:1MM CRITICAL 20% 10V CERM 402 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 C LVDS I/F LED BKLT I/F B CAMERA I/F 33 34 CAMERA L9060 90-OHM DLP0NS SYM_VER-1 72 18 OUT USB_CAMERA_P 72 18 OUT USB_CAMERA_N 75 USB_CAMERA_CONN_P 75 USB_CAMERA_CONN_N PLACEMENT_NOTE=PLACE CLOSE TO J9000 A SYNC_MASTER=(K84_MLB) PAGE TITLE SYNC_DATE=(10/19/2009) LVDS CONNECTOR DRAWING NUMBER Apple Inc 051-8561 R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED SIZE D REVISION C.0.0 BRANCH PAGE 90 OF 109 SHEET 64 OF 76 A D D C9300 0.1UF DP_IG_AUX_CH_P 71 DP_AUX_CH_C_P D G S DP_EXT_DDC_CLK S OMIT G SIGNAL_MODEL=DP_AUXCH_FET SIGNAL_MODEL=DP_AUXCH_FET OMIT D 10% 16V X5R 402 Q9300 Q9300 SSM6N16FE 376S0857 SSM6N16FE SOT563 SOT563 C9301 0.1UF DP_IG_AUX_CH_N 71 DP_AUX_CH_C_N D G S DP_EXT_DDC_DATA S C D 10% 16V X5R 402 OMIT SIGNAL_MODEL=DP_AUXCH_FET C Q9302 G SIGNAL_MODEL=DP_AUXCH_FET OMIT SSM6N16FE SOT563 C9303 0.0033UF 376S0857 Q9302 SSM6N16FE SOT563 10% 50V CERM 402 DP_CA_DET IN B B PART NUMBER QTY 376S0859 DESCRIPTION REFERENCE DES CRITICAL XSTR,FT,N-CH,DUAL,SOT-563 Q9300,Q9302 CRITICAL BOM OPTION A SYNC_MASTER=K6_MLB SYNC_DATE=02/16/2010 PAGE TITLE DISPLAYPORT SUPPORT DRAWING NUMBER Apple Inc 051-8561 R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED SIZE D REVISION C.0.0 BRANCH PAGE 93 OF 109 SHEET 65 OF 76 A Port Power Switch D D CRITICAL L9400 FERR-120-OHM-3A PP3V3_S0_DPPWR U9480 TPS2051B =PP3V3_S5_DP_PORT_PWR SOT23 IN 62 35 19 IN PM_SLP_S3_L EN PP3V3_S0_DPILIM OUT MIN_LINE_WIDTH=0.50 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=3.3V OC* TP_DPPWR_OC_L 0603 1 C9487 C9485 100UF 0.1UF 20% 20% 6.3V 10V CERM X5R-CERM-1 603 402 FL9400 12-OHM-100MA 20% 16V CERM 402 CRITICAL C9481 1C9480 22UF MIN_LINE_WIDTH=0.50 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=3.3V 0.01UF GND CRITICAL C9400 0.1UF 20% 6.3V POLY-TANT CASE-B2-SM 20% 10V CERM 402 75 C9486 DP_EXT_ML_F_P DP_EXT_ML_F_N DP_ESD CRITICAL 75 10UF 20% 6.3V X5R 603 TCM1210-4SM SYM_VER-2 75 75 DP_EXT_ML_C_P C9410 0.1uF DP_EXT_ML_C_N C9411 0.1uF DP_EXT_ML_P 10% 16V X5R 402 IN 75 DP_EXT_ML_N 10% 16V X5R 402 IN 75 D9410 RCLAMP0524P SLP2510P8 IO NC GND IO NC PLACE_NEAR=J9400.3:3MM R94201 100K 5% 1/16W MF-LF 402 CRITICAL HDMI_CEC J9400 MINIDSPLYPRT-K83-GEN2 F-RT-THSM R9425 C 1M 5% 1/16W MF-LF 402 FL9403 12-OHM-100MA IN DP_EXT_ML_P 75 IN DP_EXT_ML_N 75 BI 75 BI C9414 0.1uF 75 DP_EXT_ML_C_P 10% 16V X5R 402 75 DP_EXT_ML_C_N 10% 16V X5R 402 TCM1210-4SM SYM_VER-2 75 C9415 0.1uF 75 DP_EXT_ML_F_P DP_EXT_ML_F_N DP_EXT_AUX_CH_C_P DP_EXT_AUX_CH_C_N 66 8 =PP3V3_S0_DPCONN =PP5VR3V3_S0_DPCADET R9443 OUT GND AUX_CHP AUX_CHN DP_PWR 5% 1/16W MF-LF 402 5% 1/16W MF-LF 402 2 IO NC 75 DP_EXT_ML_C_P C9412 0.1uF 75 DP_EXT_ML_F_N 75 DP_EXT_ML_C_N C9413 0.1uF DP_EXT_ML_P 10% 16V X5R 402 IN 75 DP_EXT_ML_N 10% 16V X5R 402 IN 75 DP_ESD CRITICAL D9410 SHIELD PINS SLP2510P8 22 21 514-0706 IO NC IO NC 10 GND G DP_CA_DET_Q_L PLACE_NEAR=J9400.12:3MM IO NC 10 PLACE_NEAR=J9400.9:3MM DP_ESD CRITICAL D9400 Q9440 B TCM1210-4SM SYM_VER-2 2N7002DW-X-G S DP_EXT_ML_F_P SLP2510P8 D SOT-363 FL9401 12-OHM-100MA 75 100K Q9440 C 11 13 15 17 19 RCLAMP0524P RCLAMP0524P R94211 100K 5% 1/16W MF-LF 402 GND ML_LANE2P ML_LANE2N RETURN D9411 R94421 100K DP_EXT_CA_DET SM PINS HOT_PLUG_DETECT GND CONFIG1 ML_LANE0P CONFIG2 ML_LANE0N GND GND ML_LANE3P ML_LANE1P ML_LANE3N ML_LANE1N DP_ESD CRITICAL TOP ROW TH PINS GND 75 BOT ROW 10 12 14 16 18 20 RCLAMP0504F SC70-6-1 D PLACE_NEAR=J9400.2:3MM 2N7002DW-X-G SOT-363 S G DP_CA_DET_Q 12-OHM-100MA DP to DVI/HDMI R94221 75 Cable Adapter 1M pull-up to DP_PWR DP_EXT_ML_F_P TCM1210-4SM SYM_VER-2 75 DP_EXT_ML_C_P C9416 75 DP_EXT_ML_C_N C9417 0.1uF (CA) has 100k 5% 1/16W MF-LF 402 Q9440 must have Drain to Gate leakage of 5MOhm B FL9402 75 DP_EXT_ML_F_N 0.1uF DP_EXT_ML_P 10% 16V X5R 402 IN 75 DP_EXT_ML_N 10% 16V X5R 402 IN 75 DP_ESD CRITICAL D9411 RCLAMP0524P SLP2510P8 =PP3V3_S0_DPCONN R94451 OUT DP_EXT_HPD IO NC R94441 10K 10K 5% 1/16W MF-LF 402 5% 1/16W MF-LF 402 IO NC GND 66 PLACE_NEAR=J9400.15:3MM Q9441 D 2N7002DW-X-G SOT-363 S G DP_HPD_Q_L Q9441 D 2N7002DW-X-G A SOT-363 S G DP_HPD_Q SYNC_MASTER=MASTER SYNC_DATE=MASTER PAGE TITLE R9423 100K 5% 1/16W MF-LF 402 DisplayPort Connector DP Source must pull down HPD input with DRAWING NUMBER greater than or equal Apple Inc to 100K (DPv1.1a) R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED DO NOT SYNC K6 PAGE WITH K84 CONNECTOR 051-8561 SIZE D REVISION C.0.0 BRANCH PAGE 94 OF 109 SHEET 66 OF 76 A D D SENS_R:ENG CRITICAL R9700 0.020 68 PPBUS_S0_LCDBKLT_PWR 1% 0.25W MF-LF 805 CRITICAL PPVIN_BKL MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.38 MM VOLTAGE=9V 75 46 ISNS_LCDBKLT_P OUT ISNS_LCDBKLT_N D9710 SOD-123 CRITICAL 10% 25V X5R 402 C9710 PPVOUT_S0_LCDBKLT RB160M-40 CRITICAL R9730 10UF 0.1UF PPVOUT_S0_LCDBKLT_SW MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.38 MM VOLTAGE=50V SWITCH_NODE=TRUE 1217AS-2SM C9713 OUT CRITICAL L9710 33UH-1.8A-110MOHM PLACE_NEAR=L9710:3MM 75 46 PLACE_NEAR=L9710:3MM 10 10% 25V X5R 805 5% 1/16W MF-LF 402 CRITICAL C9715 4.7UF DIDT=TRUE f = 600kHz C9716 4.7UF 20% 50V X7R-CERM 1206 C9717 1000PF 20% 50V X7R-CERM 1206 10% 100V X7R 603 PLACEMENT_NOTE=PLACE CLOSE TO L9710 PLACEMENT_NOTEs: 46 64 MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.24 MM VOLTAGE=50V PLACE_NEAR=D9710.2:3MM PLACE_NEAR=XW9701.1:3MM OMIT XW9701 SM GND_LCDBKLT_PGND MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.4 MM VOLTAGE=0V (C9710-C9711) LCDBKLT_VIN MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.2 MM WF: C9711 AND C9717 NOT IN REF SCHEMATIC VIN PP2V5_S0_LCDBKLT C9727 5% 50V C0G-CERM 603 C VDC1 SWA SWB 23 VDC2 VOUT 24 MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=2.5V PLACE_NEAR=U9700.1:3MM 1000PF 20 C9711 1UF PP5V5_S0_LCDBKLT 10% 25V X5R 603-1 C9700 1 2.2UF C9701 MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=5.5V 2.2UF 20% 10V X5R-CERM 402 R9715 U9700 20% 10V X5R-CERM 402 1M MC34845CEP IN LVDS_IG_BKL_PWM OVP 22 200 1% 1/16W MF-LF 402 16 18 LVDS_IG_BKL_PWM_R C9799 R9726 10K 1% 1/16W MF-LF 402 C9705 PWM WAKE CH1 BKL_MC_CH2 BKL_MC_CH3 EN MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.2 MM COMP CH3 15 ISET CH4 10 BKL_MC_CH4 CH5 11 BKL_MC_CH5 0.033UF CH6 12 BKL_MC_CH6 10% 16V X5R 402 LCDBKLT_COMP_RC 220PF 5% 25V CERM 402 B FAIL 14 R9710 7.68K 1% 1/16W MF-LF 402 NOSTUFF C9724 100PF PLACEMENT_NOTEs: C PLACE NEAR U9700 (C9721-C9726) NOSTUFF 5% 50V CERM 402 C9726 100PF 5% 50V CERM 402 BKLT:PROD R9717 5% 1/16W MF-LF 402 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm LED_RETURN_1 BKLT:PROD MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm R9718 BKLT:PROD R9719 1/16W 5% MF-LF 402 R9720 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm BKLT:PROD R9721 BKLT:PROD R9722 5% 1/16W MF-LF 402 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm IN LED_RETURN_2 MIN_LINE_WIDTH=0.5 mm IN MIN_NECK_WIDTH=0.20 mm LED_RETURN_3 5% 1/16W MF-LF 402 5% 1/16W MF-LF 402 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm BKLT:PROD MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm 5% 1/16W MF-LF 402 MIN_LINE_WIDTH=0.5 mm IN MIN_NECK_WIDTH=0.20 mm LED_RETURN_4 MIN_LINE_WIDTH=0.5 mm IN MIN_NECK_WIDTH=0.20 mm LED_RETURN_5 64 64 64 64 IN 64 MIN_LINE_WIDTH=0.5 mm IN MIN_NECK_WIDTH=0.20 mm 64 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm LED_RETURN_6 LCDBKLT_FAIL R97021 NOSTUFF THRM PAD GND_LCDBKLT_SGND 5% 1/16W MF-LF 402 R97161 243K 1% 1/16W MF-LF 402 PLACE_NEAR=U9700.25:1MM OMIT XW9700 SM MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.24 MM VOLTAGE=0V ISET = 153mA / 5% 50V CERM 402 NOSTUFF 100PF C9725 100PF 5% 50V CERM 402 5% 50V CERM 402 25 1% 1/16W MF-LF 402 C9706 PGNDA PGNDB 3.32K GND R9705 13 19 21 1 100PF 5% 50V CERM 402 C9722 NOSTUFF C9723 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm 17 MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.2 MM BKL_MC_CH1 LCDBKLT_COMP LCDBKLT_ISET 1% 1/16W MF-LF 402 NOSTUFF C9721 100PF LCDBKLT_OVP CH2 47PF 5% 50V CERM 402 OVP = Vovp * (1 + Ra/Rb) VOVP = 6.9V +/- 0.35V LLP (SGND) R9725 68 NOSTUFF 1 CRITICAL B PLACEMENT_NOTE=PLACE XW9700 FAR FROM THE NOISY PINS AND 13.3 Inch, K84 Panel (9 LEDs per string) TARGET: ISET = 20mA, OVP = 35V ACTUAL: ISET = 19.9mA, OVP = 35.2V PART NUMBER DESCRIPTION REFERENCE DES 103S0198 QTY RES,THIN FLIM,1/16W,10.2 OHM,0.1,0402,SM R9717,R9718,R9719 CRITICAL BOM OPTION BKLT:ENG 103S0198 RES,THIN FLIM,1/16W,10.2 OHM,0.1,0402,SM R9720,R9721,R9722 BKLT:ENG 101S0075 RES,MF,0 OHM,5%,1/8W,SMD,LF,0805 R9700 SENS_R:PROD 10.2 ohm resistors for current measurement on LED strings A SYNC_MASTER=MASTER SYNC_DATE=MASTER PAGE TITLE LCD Backlight Driver (MC34845) DRAWING NUMBER Apple Inc 051-8561 R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED DO NOT SYNC FROM K84 L9710 CHANGED TO K6/K69 SIZE D REVISION C.0.0 BRANCH PAGE 97 OF 109 SHEET 67 OF 76 A CRITICAL Q9806 FDC638APZ_SBMS001 SSOT6-HF PPBUS_S0_LCDBKLT_FUSED MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.6V 0402-HF R9808 301K 1% 1/16W MF-LF 402 MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.6V OUT 67 D PPBUS S0 LCDBKLT FET C9802 0.1UF =PPBUS_S0_LCDBKLT IN D PPBUS_S0_LCDBKLT_PWR F9800 2AMP-32V 10% 16V X5R 402 PBUS_S0_LCDBKLT_EN_DIV MOSFET FDC638APZ CHANNEL P-TYPE RDS(ON) 43 mOhm @4.5V LOADING 0.4 A (EDP) R9809 147K 1% 1/16W MF-LF 402 PBUS_S0_LCDBKLT_EN_L D Q9807 SSM6N15FEAPE SOT563 G S BKLT_EN_L 68 LVDS_IG_BKL_ON IN C Q9807 C D SSM6N15FEAPE SOT563 G 25 S BKLT_PLT_RST_L IN B B LVDS_IG_BKL_ON 68 LVDS_IG_BKL_PWM NOSTUFF R9840 1K 5% 1/16W MF-LF 402 67 NOSTUFF R9841 1K 5% 1/16W MF-LF 402 MCP79 HAD INTERNAL 10K PULL-UP FOR THESE SIGNALS MCP89 DRIVES THEM LOW A SYNC_MASTER=(K84_MLB) SYNC_DATE=(10/19/2009) PAGE TITLE LCD Backlight Support DRAWING NUMBER Apple Inc 051-8561 R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED SIZE D REVISION C.0.0 BRANCH PAGE 98 OF 109 SHEET 68 OF 76 A FSB (Front-Side Bus) Constraints CPU / FSB Net Properties TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP FSB_50S * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD FSB_DSTB_50S * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =1:1_DIFFPAIR =1:1_DIFFPAIR ELECTRICAL_CONSTRAINT_SET NET_TYPE PHYSICAL SPACING TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING TABLE_SPACING_RULE_HEAD WEIGHT SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM FSB_DATA * =2x_DIELECTRIC ? FSB_DSTB * =3x_DIELECTRIC ? TABLE_SPACING_RULE_ITEM FSB_DATA TOP,BOTTOM =4x_DIELECTRIC ? FSB_DSTB TOP,BOTTOM =5x_DIELECTRIC ? TABLE_SPACING_RULE_ITEM D TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM FSB_ADDR * TABLE_SPACING_RULE_ITEM ? =STANDARD FSB_ADDR TOP,BOTTOM ? =3x_DIELECTRIC TABLE_SPACING_RULE_ITEM FSB_ADSTB * TABLE_SPACING_RULE_ITEM ? =2x_DIELECTRIC FSB_ADSTB TOP,BOTTOM ? =4x_DIELECTRIC TABLE_SPACING_RULE_ITEM FSB_1X * TABLE_SPACING_RULE_ITEM ? =STANDARD FSB 4X Signal Groups TABLE_PHYSICAL_RULE_ITEM FSB_1X TOP,BOTTOM ? =3x_DIELECTRIC All 4x/2x/1x FSB signals with impedance requirements are 50-ohm single-ended FSB 2X Signals FSB 4X signals / groups shown in signal table on right Signals within each 4x group should be matched within ps of strobe DSTB# complementary pairs should be matched within ps of each other, all DSTB#s matched to +/- 135 ps Spacing is 2x dielectric between DATA#, DINV# signals, with 3x dielectric spacing to the DSTB#s FSB 2X signals / groups shown in signal table on right Signals within each 2x group should be matched within 20 ps ADTSB#s should be matched +/- 270 ps Spacing is 1x dielectric between ADDR#, REQ# signals, with 2x dielectric spacing to ADSTB# FSB 1X signals shown in signal table on right Intel Design Guide recommends FSB signals be routed only on internal layers FSB 1X Signals NOTE: Intel Design Guide allows closer spacing if signal lengths can be shortened SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.1 SOURCE: Santa Rosa Platform DG, Rev 1.5 (#22294), Sections 4.2 & 4.3 CPU Signal Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM CPU_50S * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD CPU_27P4S * =27P4_OHM_SE =27P4_OHM_SE =27P4_OHM_SE =27P4_OHM_SE MIL MIL TABLE_PHYSICAL_RULE_ITEM C NOTE: mil gap is for VCCSense pair, which Intel says to route with mil spacing without specifying a target impedance TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LINE-TO-LINE SPACING WEIGHT CPU_AGTL LAYER * =STANDARD ? CPU_8MIL * MIL ? SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT =2x_DIELECTRIC ? TABLE_SPACING_RULE_ITEM CPU_AGTL TOP,BOTTOM TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM * 25 MIL ? CPU_GTLREF * 25 MIL ? TABLE_SPACING_RULE_ITEM SR DG recommends at least 25 mils, >50 mils preferred TABLE_SPACING_RULE_ITEM CPU_ITP * =2:1_SPACING ? CPU_VCCSENSE * 25 MIL ? TABLE_SPACING_RULE_ITEM Most CPU signals with impedance requirements are 55-ohm single-ended Some signals require 27.4-ohm single-ended impedance SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.1 SOURCE: Santa Rosa Platform DG, Rev 0.9 (#20517), Sections 4.4 & 5.8.2.4 MCP FSB COMP Signal Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM MCP_50S * =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =50_OHM_SE =STANDARD TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING FSB_50S FSB_50S FSB_DSTB_50S FSB_DSTB_50S FSB_DATA FSB_DATA FSB_DSTB FSB_DSTB FSB_D_L FSB_DINV_L FSB_DSTB_L_P FSB_DSTB_L_N FSB_DATA_GROUP1 FSB_DATA_GROUP1 FSB_DSTB1 FSB_DSTB1 FSB_50S FSB_50S FSB_DSTB_50S FSB_DSTB_50S FSB_DATA FSB_DATA FSB_DSTB FSB_DSTB FSB_D_L FSB_DINV_L FSB_DSTB_L_P FSB_DSTB_L_N FSB_DATA_GROUP2 FSB_DATA_GROUP2 FSB_DSTB2 FSB_DSTB2 FSB_50S FSB_50S FSB_DSTB_50S FSB_DSTB_50S FSB_DATA FSB_DATA FSB_DSTB FSB_DSTB FSB_D_L FSB_DINV_L FSB_DSTB_L_P FSB_DSTB_L_N FSB_DATA_GROUP3 FSB_DATA_GROUP3 FSB_DSTB3 FSB_DSTB3 FSB_50S FSB_50S FSB_DSTB_50S FSB_DSTB_50S FSB_DATA FSB_DATA FSB_DSTB FSB_DSTB FSB_D_L FSB_DINV_L FSB_DSTB_L_P FSB_DSTB_L_N FSB_ADDR_GROUP0 FSB_ADDR_GROUP0 FSB_ADSTB0 FSB_50S FSB_50S FSB_50S FSB_ADDR FSB_ADDR FSB_ADSTB FSB_A_L FSB_REQ_L FSB_ADSTB_L FSB_ADDR_GROUP1 FSB_ADSTB1 FSB_50S FSB_50S FSB_ADDR FSB_ADSTB FSB_A_L FSB_ADSTB_L FSB_1X FSB_BREQ0_L FSB_1X FSB_1X FSB_1X FSB_1X FSB_1X FSB_1X FSB_1X FSB_1X FSB_CPURST_L FSB_1X FSB_1X FSB_50S FSB_50S FSB_50S FSB_50S FSB_50S FSB_50S FSB_50S FSB_50S FSB_50S FSB_50S FSB_50S FSB_50S FSB_50S FSB_1X FSB_1X FSB_1X FSB_1X FSB_1X FSB_1X FSB_1X FSB_1X FSB_1X FSB_1X FSB_1X FSB_1X FSB_1X FSB_ADS_L FSB_BREQ0_L FSB_BNR_L FSB_BPRI_L FSB_DBSY_L FSB_DEFER_L FSB_DRDY_L FSB_HIT_L FSB_HITM_L FSB_LOCK_L FSB_CPURST_L FSB_RS_L FSB_TRDY_L CPU_ASYNC CPU_BSEL CPU_FERR_L CPU_ASYNC CPU_INIT_L CPU_ASYNC_R CPU_ASYNC_R CPU_PROCHOT_L CPU_PWRGD CPU_ASYNC CPU_ASYNC PM_THRMTRIP_L FSB_CPUSLP_L CPU_FROM_SB CPU_DPRSTP_L CPU_ASYNC CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_AGTL CPU_AGTL CPU_8MIL CPU_AGTL CPU_AGTL CPU_AGTL CPU_AGTL CPU_AGTL CPU_AGTL CPU_AGTL CPU_AGTL CPU_8MIL CPU_AGTL CPU_AGTL CPU_AGTL CPU_AGTL CPU_A20M_L CPU_BSEL CPU_FERR_L CPU_IGNNE_L CPU_INIT_L CPU_INTR CPU_NMI CPU_PROCHOT_L CPU_PWRGD CPU_SMI_L CPU_STPCLK_L PM_THRMTRIP_L FSB_CPUSLP_L CPU_DPSLP_L CPU_DPRSTP_L FSB_DPWR_L FSB_CLK_CPU FSB_CLK_CPU FSB_CLK_ITP FSB_CLK_ITP FSB_CLK_MCP FSB_CLK_MCP CLK_FSB_100D CLK_FSB_100D CLK_FSB_100D CLK_FSB_100D CLK_FSB_100D CLK_FSB_100D CLK_FSB CLK_FSB CLK_FSB CLK_FSB CLK_FSB CLK_FSB FSB_CLK_CPU_P FSB_CLK_CPU_N FSB_CLK_ITP_P FSB_CLK_ITP_N FSB_CLK_MCP_P FSB_CLK_MCP_N CPU_IERR_L CPU_50S PM_DPRSLPVR (See above) CPU_50S CPU_50S CPU_AGTL CPU_AGTL PM_DPRSLPVR IMVP_DPRSLPVR MCP_CPU_COMP MCP_CPU_COMP MCP_CPU_COMP MCP_CPU_COMP MCP_50S MCP_50S MCP_50S MCP_50S MCP_FSB_COMP MCP_FSB_COMP MCP_FSB_COMP MCP_FSB_COMP MCP_BCLK_VML_COMP_VDD MCP_BCLK_VML_COMP_GND MCP_CPU_COMP_VCC MCP_CPU_COMP_GND CPU_GTLREF CPU_COMP CPU_COMP CPU_COMP CPU_COMP CPU_50S CPU_50S CPU_27P4S CPU_50S CPU_27P4S CPU_GTLREF CPU_COMP CPU_COMP CPU_COMP CPU_COMP CPU_GTLREF CPU_COMP CPU_COMP CPU_COMP CPU_COMP XDP_TDI XDP_TDO XDP_TMS XDP_TCK XDP_TRST_L XDP_BPM_L XDP_BPM_L5 CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_ITP CPU_ITP CPU_ITP CPU_ITP CPU_ITP CPU_ITP CPU_ITP CPU_ITP XDP_TDI XDP_TDO XDP_TMS XDP_TCK XDP_TRST_L XDP_BPM_L XDP_BPM_L XDP_CPURST_L CPU_50S CPU_50S CPU_27P4S CPU_27P4S CPU_27P4S CPU_27P4S CPU_8MIL CPU_8MIL CPU_VCCSENSE CPU_VCCSENSE CPU_VCCSENSE CPU_VCCSENSE CPU_VID IMVP6_VID CPU_VCCSENSE_P CPU_VCCSENSE_N IMVP6_VSEN_P IMVP6_VSEN_N 10 14 10 14 10 14 10 14 10 14 10 14 10 14 D 10 14 10 14 10 14 10 14 10 14 10 14 10 14 10 14 10 14 10 14 10 14 10 14 10 14 10 14 10 14 10 14 10 14 10 14 10 14 10 14 10 14 10 14 10 14 10 14 C 10 13 14 10 14 10 14 TABLE_SPACING_RULE_HEAD TABLE_SPACING_RULE_ITEM CPU_COMP FSB_DATA_GROUP0 FSB_DATA_GROUP0 FSB_DSTB0 FSB_DSTB0 WEIGHT 10 14 10 10 14 10 14 10 14 10 14 10 14 10 14 36 10 13 14 10 14 10 14 10 14 36 10 14 10 14 10 14 58 10 14 10 14 10 14 13 14 13 14 14 14 TABLE_SPACING_RULE_ITEM B MCP_FSB_COMP * ? MIL SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.1.4 FSB Clock Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM CLK_FSB_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT =3x_DIELECTRIC ? TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT =4x_DIELECTRIC ? TABLE_SPACING_RULE_ITEM CLK_FSB * TABLE_SPACING_RULE_ITEM CLK_FSB TOP,BOTTOM SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2.5 (FSB_CPURST_L) CPU_VCCSENSE CPU_VCCSENSE A (CPU_VCCSENSE) (CPU_VCCSENSE) CPU_IERR_L B 10 14 58 58 14 14 14 14 10 29 10 10 10 10 10 13 10 13 10 13 10 13 10 13 10 13 10 13 13 11 58 11 58 11 58 58 58 SYNC_MASTER=T27_MLB SYNC_DATE=02/16/2010 PAGE TITLE CPU/FSB Constraints DRAWING NUMBER Apple Inc 051-8561 R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED SIZE D REVISION C.0.0 BRANCH PAGE 100 OF 109 SHEET 69 OF 76 A Memory Bus Constraints Memory Net Properties TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP MEM_40S * =40_OHM_SE =40_OHM_SE =40_OHM_SE =40_OHM_SE =STANDARD =STANDARD MEM_70D * =70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF ELECTRICAL_CONSTRAINT_SET NET_TYPE PHYSICAL SPACING TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM MEM_A_CLK MEM_A_CLK MEM_70D MEM_70D MEM_CLK MEM_CLK MEM_A_CLK_P MEM_A_CLK_N MEM_A_CKE MEM_40S MEM_CTRL MEM_A_CKE MEM_A_CNTL MEM_A_CNTL MEM_40S MEM_40S MEM_CTRL MEM_CTRL MEM_A_CS_L MEM_A_ODT MEM_A_CMD MEM_A_CMD MEM_A_CMD MEM_A_CMD MEM_A_CMD MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_CMD MEM_CMD MEM_CMD MEM_CMD MEM_CMD MEM_A_A MEM_A_BA MEM_A_RAS_L MEM_A_CAS_L MEM_A_WE_L MEM_A_DQ_BYTE0 MEM_A_DQ_BYTE1 MEM_A_DQ_BYTE2 MEM_A_DQ_BYTE3 MEM_A_DQ_BYTE4 MEM_A_DQ_BYTE5 MEM_A_DQ_BYTE6 MEM_A_DQ_BYTE7 MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ_BYTE0 MEM_A_DQ_BYTE1 MEM_A_DQ_BYTE2 MEM_A_DQ_BYTE3 MEM_A_DQ_BYTE4 MEM_A_DQ_BYTE5 MEM_A_DQ_BYTE6 MEM_A_DQ_BYTE7 MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_A_DM MEM_A_DM MEM_A_DM MEM_A_DM MEM_A_DM MEM_A_DM MEM_A_DM MEM_A_DM MEM_A_DQS0 MEM_A_DQS0 MEM_A_DQS1 MEM_A_DQS1 MEM_A_DQS2 MEM_A_DQS2 MEM_A_DQS3 MEM_A_DQS3 MEM_A_DQS4 MEM_A_DQS4 MEM_A_DQS5 MEM_A_DQS5 MEM_A_DQS6 MEM_A_DQS6 MEM_A_DQS7 MEM_A_DQS7 MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_B_CLK MEM_B_CLK MEM_70D MEM_70D MEM_CLK MEM_CLK MEM_B_CLK_P MEM_B_CLK_N MEM_B_CKE MEM_40S MEM_CTRL MEM_B_CKE MEM_B_CNTL MEM_B_CNTL MEM_40S MEM_40S MEM_CTRL MEM_CTRL MEM_B_CS_L MEM_B_ODT MEM_B_CMD MEM_B_CMD MEM_B_CMD MEM_B_CMD MEM_B_CMD MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_CMD MEM_CMD MEM_CMD MEM_CMD MEM_CMD MEM_B_A MEM_B_BA MEM_B_RAS_L MEM_B_CAS_L MEM_B_WE_L MEM_B_DQ_BYTE0 MEM_B_DQ_BYTE1 MEM_B_DQ_BYTE2 MEM_B_DQ_BYTE3 MEM_B_DQ_BYTE4 MEM_B_DQ_BYTE5 MEM_B_DQ_BYTE6 MEM_B_DQ_BYTE7 MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ_BYTE0 MEM_B_DQ_BYTE1 MEM_B_DQ_BYTE2 MEM_B_DQ_BYTE3 MEM_B_DQ_BYTE4 MEM_B_DQ_BYTE5 MEM_B_DQ_BYTE6 MEM_B_DQ_BYTE7 MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_B_DM MEM_B_DM MEM_B_DM MEM_B_DM MEM_B_DM MEM_B_DM MEM_B_DM MEM_B_DM MEM_B_DQS0 MEM_B_DQS0 MEM_B_DQS1 MEM_B_DQS1 MEM_B_DQS2 MEM_B_DQS2 MEM_B_DQS3 MEM_B_DQS3 MEM_B_DQS4 MEM_B_DQS4 MEM_B_DQS5 MEM_B_DQS5 MEM_B_DQS6 MEM_B_DQS6 MEM_B_DQS7 MEM_B_DQS7 MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MCP_MEM_COMP MCP_MEM_COMP MCP_MEM_COMP MCP_MEM_COMP MCP_MEM_COMP MCP_MEM_COMP MCP_MEM_COMP_VDD MCP_MEM_COMP_GND 15 26 15 26 15 21 26 TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM MEM_CLK2MEM * NV DG says 3x inner, 4x outer ? =4:1_SPACING 15 26 15 26 TABLE_SPACING_RULE_ITEM D MEM_CTRL2CTRL * =2:1_SPACING ? MEM_CTRL2MEM * =2.5:1_SPACING ? NV DG says 2x inner, 4x outer TABLE_SPACING_RULE_ITEM NV DG says 2x inner, 4x outer TABLE_SPACING_RULE_ITEM MEM_CMD2CMD * =1.5:1_SPACING ? MEM_CMD2MEM * =3:1_SPACING ? NV DG says 2x inner, 4x outer TABLE_SPACING_RULE_ITEM NV DG says 2x inner, 4x outer TABLE_SPACING_RULE_ITEM MEM_DATA2DATA * =1.5:1_SPACING ? MEM_DATA2MEM * =3:1_SPACING ? NV DG says 2x inner, 4x outer TABLE_SPACING_RULE_ITEM NV DG says 2x inner, 4x outer TABLE_SPACING_RULE_ITEM MEM_DQS2MEM * =3:1_SPACING ? MEM_2OTHER * 25 MIL ? NV DG says 4x inner, 5x outer TABLE_SPACING_RULE_ITEM Memory Bus Spacing Group Assignments TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET MEM_CLK MEM_CLK * MEM_CLK2MEM TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET MEM_CMD MEM_CLK * MEM_CMD2MEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CLK MEM_CTRL * MEM_CLK2MEM MEM_CLK MEM_CMD * MEM_CLK2MEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CMD MEM_CTRL * MEM_CMD2MEM MEM_CMD MEM_CMD * MEM_CMD2CMD TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CLK MEM_DATA * MEM_CLK2MEM MEM_CLK MEM_DQS * MEM_CLK2MEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CMD MEM_DATA * MEM_CMD2MEM MEM_CMD MEM_DQS * MEM_CMD2MEM TABLE_SPACING_ASSIGNMENT_ITEM NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET TABLE_SPACING_ASSIGNMENT_ITEM MEM_CTRL MEM_CLK * MEM_CTRL2MEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_DATA MEM_CLK * MEM_DATA2MEM TABLE_SPACING_ASSIGNMENT_ITEM C MEM_CTRL MEM_CTRL * MEM_CTRL2CTRL TABLE_SPACING_ASSIGNMENT_ITEM MEM_DATA MEM_CTRL * MEM_DATA2MEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CTRL MEM_CMD * MEM_CTRL2MEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_DATA MEM_CMD * MEM_DATA2MEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CTRL MEM_DATA * MEM_CTRL2MEM MEM_CTRL MEM_DQS * MEM_CTRL2MEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_DATA MEM_DATA * MEM_DATA2DATA MEM_DATA MEM_DQS * MEM_DATA2MEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET TABLE_SPACING_ASSIGNMENT_ITEM MEM_DQS MEM_CLK * MEM_DQS2MEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CLK * * MEM_2OTHER TABLE_SPACING_ASSIGNMENT_ITEM MEM_DQS MEM_CTRL * MEM_DQS2MEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CTRL * * MEM_2OTHER TABLE_SPACING_ASSIGNMENT_ITEM MEM_DQS MEM_CMD * MEM_DQS2MEM MEM_DQS MEM_DATA * MEM_DQS2MEM MEM_CMD * * MEM_2OTHER MEM_DATA * * MEM_2OTHER TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_DQS * MEM_DQS2MEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_DQS * * MEM_2OTHER Need to support MEM_*-style wildcards! DDR3: DQ signals should be matched within ps of associated DQS pair DQS intra-pair matching should be within ps, inter-pair matching shoulw be within 360 ps No DQS to clock matching requirement CLK intra-pair matching should be within ps, inter-pair matching should be within ps CMD/CTRL signals should be matched within 150 ps All memory signals maximum length is 1.030 ps SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.2.3 SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Section 6.2 B MCP MEM COMP Signal Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MCP_MEM_COMP * =40_OHM_SE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP =40_OHM_SE =40_OHM_SE =40_OHM_SE =STANDARD =STANDARD TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT =2x_DIELECTRIC ? TABLE_SPACING_RULE_ITEM MCP_MEM_COMP * 15 26 15 26 15 26 15 28 15 28 15 28 15 28 15 28 15 28 15 28 15 28 15 28 15 28 15 28 15 28 15 28 15 28 15 28 15 28 15 28 15 28 15 28 15 28 15 28 C 15 28 15 28 15 28 15 28 15 28 15 28 15 28 15 28 15 28 15 28 15 28 TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_DQS D 15 26 TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 15 26 SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.2.2 A 15 27 15 27 15 21 27 15 27 15 27 15 27 15 27 15 27 15 27 15 27 15 28 15 28 15 28 B 15 28 15 28 15 28 15 28 15 28 15 28 15 28 15 28 15 28 15 28 15 28 15 28 15 28 15 28 15 28 15 28 15 28 15 28 15 28 15 28 15 28 15 28 15 28 15 28 15 28 15 28 15 28 SYNC_MASTER=T27_MLB SYNC_DATE=02/16/2010 PAGE TITLE Memory Constraints 15 28 15 28 DRAWING NUMBER 15 Apple Inc 15 051-8561 R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED SIZE D REVISION C.0.0 BRANCH PAGE 101 OF 109 SHEET 70 OF 76 A PCI-Express MCP89 Net Properties TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP PCIE_90D * =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF CLK_PCIE_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF SPACING_RULE_SET LAYER ELECTRICAL_CONSTRAINT_SET NET_TYPE PHYSICAL SPACING TABLE_PHYSICAL_RULE_ITEM PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PEG_R2D_P PEG_R2D_N PEG_R2D_C_P PEG_R2D_C_N PEG_D2R_P PEG_D2R_N PEG_D2R_C_P PEG_D2R_C_N PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE PCIE PCIE PCIE PCIE PCIE PCIE_AP_R2D_P PCIE_AP_R2D_N PCIE_AP_R2D_C_P PCIE_AP_R2D_C_N PCIE_AP_D2R_P PCIE_AP_D2R_N PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE_ENET_R2D_P PCIE_ENET_R2D_N PCIE_ENET_R2D_C_P PCIE_ENET_R2D_C_N PCIE_ENET_D2R_P PCIE_ENET_D2R_N PCIE_ENET_D2R_C_P PCIE_ENET_D2R_C_N PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE_FW_R2D_P PCIE_FW_R2D_N PCIE_FW_R2D_C_P PCIE_FW_R2D_C_N PCIE_FW_D2R_P PCIE_FW_D2R_N PCIE_FW_D2R_C_P PCIE_FW_D2R_C_N CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE MCP_PEX_COMP PEG_CLK100M_P PEG_CLK100M_N PCIE_CLK100M_AP_P PCIE_CLK100M_AP_N PCIE_CLK100M_ENET_P PCIE_CLK100M_ENET_N PCIE_CLK100M_FW_P PCIE_CLK100M_FW_N MCP_PEX0_TERMP CRT_RED CRT_GREEN CRT_BLUE CRT_SYNC CRT_SYNC MCP_DAC_RSET MCP_DAC_VREF CRT_50S CRT_50S CRT_50S CRT_50S CRT_50S CRT CRT CRT CRT_SYNC CRT_SYNC MCP_DAC_COMP MCP_DAC_COMP CRT_IG_R_C_PR CRT_IG_G_Y_Y CRT_IG_B_COMP_PB CRT_IG_HSYNC CRT_IG_VSYNC MCP_TV_DAC_RSET MCP_TV_DAC_VREF TMDS_IG_TXC TMDS_IG_TXC TMDS_IG_TXD TMDS_IG_TXD DP_90D DP_90D DP_90D DP_90D DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT TMDS_IG_TXC_P TMDS_IG_TXC_N TMDS_IG_TXD_P TMDS_IG_TXD_N DP_EXT_ML DP_EXT_ML DP_EXT_AUX_CH DP_EXT_AUX_CH DP_90D DP_90D DP_90D DP_90D DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DP_IG_ML_P DP_IG_ML_N DP_IG_AUX_CH_P DP_IG_AUX_CH_N MCP_TMDS0_RSET MCP_TMDS0_VPROBE MCP_DV_COMP LVDS_IG_A_CLK LVDS_IG_A_CLK LVDS_IG_A_DATA LVDS_IG_A_DATA LVDS_IG_A_DATA3 LVDS_IG_A_DATA3 LVDS_IG_B_CLK LVDS_IG_B_CLK LVDS_IG_B_DATA LVDS_IG_B_DATA LVDS_IG_B_DATA3 LVDS_IG_B_DATA3 LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D MCP_IFPAB_RSET MCP_IFPAB_VPROBE MCP_DV_COMP SATA_HDD_R2D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D TABLE_PHYSICAL_RULE_ITEM PEG_R2D TABLE_SPACING_RULE_HEAD LINE-TO-LINE SPACING WEIGHT =3X_DIELECTRIC ? TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT =4X_DIELECTRIC ? TABLE_SPACING_RULE_ITEM PCIE * PEG_D2R TABLE_SPACING_RULE_ITEM PCIE TOP,BOTTOM TABLE_SPACING_RULE_ITEM D CLK_PCIE * 20 MIL ? MCP_PEX_COMP * MIL ? D TABLE_SPACING_RULE_ITEM SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.3 PCIE_AP_R2D NEED PCIe Gen1/Gen2 notes! PCIE_AP_D2R PCIE_ENET_R2D Analog Video Signal Constraints PCIE_ENET_D2R TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP CRT_50S * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD SPACING_RULE_SET LAYER TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_HEAD LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET TABLE_SPACING_RULE_ITEM CRT * ? 20 MIL PCIE_FW_R2D TABLE_SPACING_ASSIGNMENT_ITEM CRT CRT * CRT_2CRT TABLE_SPACING_RULE_ITEM CRT_2CRT * ? 15 MIL PCIE_FW_D2R TABLE_SPACING_RULE_ITEM CRT_2CLK * ? 50 MIL TABLE_SPACING_RULE_ITEM CRT_2SWITCHER * 250 MIL ? CRT_SYNC * =4x_DIELECTRIC ? MCP_DAC_COMP * =2x_DIELECTRIC ? 9 16 16 16 16 16 16 16 16 16 16 16 16 TABLE_SPACING_RULE_ITEM MCP_PE0_REFCLK TABLE_SPACING_RULE_ITEM C MCP_PE1_REFCLK CRT signal single-ended impedence varies by location: - 37.5-ohm from MCP to first termination resistor - 50-ohm from first to second termination resistor - 75-ohm from output of three-pole filter to connector (if possible) R/G/B signals should be matched as close as possible and < 10 inches SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.4.1 MCP_PE2_REFCLK MCP_PE3_REFCLK MCP_PEX_CLK_COMP Digital Video Signal Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP DP_90D * =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF LVDS_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF MCP_DV_COMP * Y 20 MIL 20 MIL =STANDARD =STANDARD =STANDARD SPACING_RULE_SET LAYER TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_HEAD LINE-TO-LINE SPACING WEIGHT =3x_DIELECTRIC ? TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM DISPLAYPORT * TABLE_SPACING_RULE_ITEM DISPLAYPORT TOP,BOTTOM =4x_DIELECTRIC ? LVDS TOP,BOTTOM =4x_DIELECTRIC ? TABLE_SPACING_RULE_ITEM LVDS B * =3x_DIELECTRIC SATA Interface Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP SATA_90D * =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF SPACING_RULE_SET LAYER TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_HEAD WEIGHT TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT =4x_DIELECTRIC ? TABLE_SPACING_RULE_ITEM SATA * =3x_DIELECTRIC ? SATA_TERMP * MIL ? 16 C 16 16 16 16 16 16 16 TABLE_SPACING_RULE_ITEM ? LVDS intra-pair matching should be mils Pairs should be matched within 100 mils NOTE: NV DG recommends 90 ohm differential for LVDS, but cable/display assume 100 ohm DisplayPort/TMDS intra-pair matching should be ps Inter-pair matching should be within 100 ps DisplayPort AUX CH intra-pair matching should be ps No relationship to other signals Max trace length: LVDS 10 inches, DP 8.5 inches SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.4.2 LINE-TO-LINE SPACING 16 TABLE_SPACING_RULE_ITEM SATA TOP,BOTTOM TABLE_SPACING_RULE_ITEM SATA intra-pair matching should be ps Max trace length: 12 inches for SATA Gen1/Gen2, TBD for SATA Gen3 SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.6 SATA_HDD_D2R SATA_ODD_R2D A SATA_ODD_D2R MCP_SATA_TERMP MCP_TMDS0_RSET MCP_TMDS0_VPROBE LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS_IG_A_CLK_P LVDS_IG_A_CLK_N LVDS_IG_A_DATA_P LVDS_IG_A_DATA_N LVDS_IG_A_DATA_P LVDS_IG_A_DATA_N LVDS_IG_B_CLK_P LVDS_IG_B_CLK_N LVDS_IG_B_DATA_P LVDS_IG_B_DATA_N LVDS_IG_B_DATA_P LVDS_IG_B_DATA_N MCP_IFPAB_RSET MCP_IFPAB_VPROBE SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA_HDD_R2D_C_P SATA_HDD_R2D_C_N SATA_HDD_R2D_P SATA_HDD_R2D_N SATA_HDD_D2R_P SATA_HDD_D2R_N SATA_HDD_D2R_C_P SATA_HDD_D2R_C_N SATA_ODD_R2D_C_P SATA_ODD_R2D_C_N SATA_ODD_R2D_P SATA_ODD_R2D_N SATA_ODD_D2R_P SATA_ODD_D2R_N SATA_ODD_D2R_C_P SATA_ODD_D2R_C_N SATA_TERMP MCP_SATA_TERMP 9 65 65 17 24 17 24 B 64 64 64 64 17 24 17 24 18 33 18 33 33 33 18 33 18 33 33 33 18 33 18 33 33 33 18 33 SYNC_MASTER=T27_MLB SYNC_DATE=02/16/2010 PAGE TITLE MCP Constraints 18 33 33 DRAWING NUMBER 33 Apple Inc 18 051-8561 R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED SIZE D REVISION C.0.0 BRANCH PAGE 102 OF 109 SHEET 71 OF 76 A LPC Bus Constraints MCP89 Net Properties TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP LPC_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD CLK_LPC_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD ELECTRICAL_CONSTRAINT_SET NET_TYPE PHYSICAL SPACING TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM LPC_AD LPC_FRAME_L LPC_RESET_L LPC_55S LPC_55S LPC_55S LPC LPC LPC LPC_AD LPC_FRAME_L LPC_RESET_L MCP_LPC_CLK0 CLK_LPC_55S CLK_LPC_55S CLK_LPC_55S CLK_LPC CLK_LPC CLK_LPC LPC_CLK33M_SMC_R LPC_CLK33M_SMC LPC_CLK33M_LPCPLUS USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB_EXTA_P USB_EXTA_N USB_EXTA_MUXED_P USB_EXTA_MUXED_N USB_MINI_P USB_MINI_N USB_EXTD_P USB_EXTD_N USB_CAMERA_P USB_CAMERA_N USB_BT_P USB_BT_N USB_TPAD_P USB_TPAD_N USB_IR_P USB_IR_N USB_EXTB_P USB_EXTB_N USB_T57_P USB_T57_N USB_EXTC_P USB_EXTC_N USB_SDCARD_P USB_SDCARD_N USB_WM_P USB_WM_N 19 35 37 19 35 37 19 25 TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM LPC * =1.5x_DIELECTRIC ? CLK_LPC * =2x_DIELECTRIC ? 19 25 25 35 25 37 TABLE_SPACING_RULE_ITEM D USB_EXTA SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.7 USB 2.0 Interface Constraints USB_MINI TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP USB_EXTD TABLE_PHYSICAL_RULE_ITEM MCP_USB_RBIAS * =STANDARD MIL MIL =STANDARD =STANDARD =STANDARD USB_90D * =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF SPACING_RULE_SET LAYER TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_HEAD LINE-TO-LINE SPACING * =2x_DIELECTRIC USB_BT TABLE_SPACING_RULE_HEAD WEIGHT SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM USB USB_CAMERA TABLE_SPACING_RULE_ITEM ? USB TOP,BOTTOM =4x_DIELECTRIC ? USB_TPAD SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.8 USB_IR SMBus Interface Constraints USB_EXTB TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP SMB_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD USB_T57 TABLE_PHYSICAL_RULE_ITEM USB_EXTC TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT USB_SDCARD TABLE_SPACING_RULE_ITEM SMB * =2x_DIELECTRIC ? USB_WM SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.9 C HD Audio Interface Constraints PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MCP_USB_RBIAS SMBUS_MCP_0_CLK SMBUS_MCP_0_DATA (SMBUS_SMC_MGMT_SCL) (SMBUS_SMC_MGMT_SDA) TABLE_PHYSICAL_RULE_HEAD MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM HDA_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD MCP_USB_RBIAS_GND MCP_USB_RBIAS SMB_55S SMB_55S SMB_55S SMB_55S SMB SMB SMB SMB SMBUS_MCP_0_CLK SMBUS_MCP_0_DATA SMBUS_MCP_1_CLK SMBUS_MCP_1_DATA HDA_55S HDA_55S HDA_55S HDA_55S HDA_55S HDA_55S HDA_55S HDA_55S HDA_55S HDA_55S HDA HDA HDA HDA HDA HDA HDA HDA HDA HDA HDA_BIT_CLK HDA_BIT_CLK_R HDA_SYNC HDA_SYNC_R HDA_RST_R_L HDA_RST_L HDA_SDIN0 HDA_SDIN_CODEC HDA_SDOUT HDA_SDOUT_R MCP_HDA_COMP MCP_HDA_PULLDN_COMP 18 34 D 18 34 34 75 34 75 18 18 18 18 18 64 18 64 18 30 18 30 18 43 18 43 18 18 18 34 18 34 18 18 18 18 18 18 18 18 18 C 13 19 38 13 19 38 19 38 19 38 TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING HDA_BIT_CLK WEIGHT TABLE_SPACING_RULE_ITEM HDA * =2x_DIELECTRIC ? MCP_HDA_COMP * MIL ? HDA_SYNC TABLE_SPACING_RULE_ITEM HDA_RST_L SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.10 HDA_SDIN0 SIO Signal Constraints HDA_SDOUT TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP CLK_SLOW_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD 19 48 19 19 48 19 19 19 48 19 48 48 19 48 19 TABLE_PHYSICAL_RULE_ITEM MCP_HDA_PULLDN_COMP TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT =1.5x_DIELECTRIC ? MCP_SUS_CLK CLK_SLOW_55S CLK_SLOW_55S CLK_SLOW CLK_SLOW PM_CLK32K_SUSCLK_R PM_CLK32K_SUSCLK SPI_CLK SPI_55S SPI_55S SPI_55S SPI_55S SPI_55S SPI_55S SPI_55S SPI SPI SPI SPI SPI SPI SPI SPI_CLK_R SPI_CLK SPI_MOSI_R SPI_MOSI SPI_MISO SPI_CS0_R_L SPI_CS0_L SPI_55S SPI_55S SPI_55S SPI_55S SPI SPI SPI SPI SPI_MLB_CLK SPI_MLB_MOSI SPI_MLB_MISO SPI_MLB_CS_L SPI_55S SPI_55S SPI_55S SPI_55S SPI SPI SPI SPI SPI_ALT_CLK SPI_ALT_MOSI SPI_ALT_MISO SPI_ALT_CS_L 19 19 25 25 35 TABLE_SPACING_RULE_ITEM CLK_SLOW * SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.11 SPI_MOSI SPI Interface Constraints SPI_MISO SPI_CS0 TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM B SPI_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT =1.5x_DIELECTRIC ? TABLE_SPACING_RULE_ITEM SPI * SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.12 A 19 37 37 19 37 37 19 37 19 37 37 B 37 47 37 47 37 47 37 47 37 37 37 37 SYNC_MASTER=T27_MLB SYNC_DATE=02/16/2010 PAGE TITLE MCP Constraints DRAWING NUMBER Apple Inc 051-8561 R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED SIZE D REVISION C.0.0 BRANCH PAGE 103 OF 109 SHEET 72 OF 76 A MCP RGMII (Ethernet) Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP MCP_MII_COMP * =STANDARD 7.5 MIL 7.5 MIL =STANDARD =STANDARD =STANDARD NET_TYPE ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM ENET_MII_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD MCP_MII_COMP MCP_MII_COMP MCP_CLK25M_BUF0 ENET_MII_55S ENET_MII_55S MCP_BUF0_CLK MCP_BUF0_CLK MCP_CLK25M_BUF0_R RTL8211_CLK25M_CKXTAL1 ENET_MII_55S ENET_MII_55S ENET_MII_55S ENET_MII_55S ENET_MII ENET_MII ENET_MII ENET_MII ENET_INTR_L ENET_MDIO ENET_MDC ENET_PWRDWN_L ENET_MII_55S ENET_MII_55S ENET_MII_55S ENET_MII_55S ENET_MII_55S ENET_MII_55S ENET_MII_55S ENET_MII ENET_MII ENET_MII ENET_MII ENET_MII ENET_MII ENET_MII ENET_CLK125M_RXCLK_R ENET_CLK125M_RXCLK ENET_RXD_R ENET_RXD ENET_RXD ENET_RX_CTRL ENET_RXCTL_R ENET_MII_55S ENET_MII_55S ENET_MII_55S ENET_MII_55S ENET_MII_55S ENET_MII ENET_MII ENET_MII ENET_MII ENET_MII ENET_CLK125M_TXCLK_R ENET_CLK125M_TXCLK ENET_TXD ENET_TXD ENET_TX_CTRL ENET_MII_55S ENET_MII ENET_RESET_L ENET_MDI_100D ENET_MDI_100D ENET_MDI_100D ENET_MDI_100D ENET_MDI ENET_MDI ENET_MDI ENET_MDI ENET_MDI_P ENET_MDI_N ENET_MDI_TRAN_P ENET_MDI_TRAN_N TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING MCP_MII_COMP_VDD MCP_MII_COMP_GND MCP_MII_COMP MCP_MII_COMP WEIGHT 18 18 31 31 TABLE_SPACING_RULE_ITEM MCP_BUF0_CLK * =3:1_SPACING ? ENET_MII * 12 MIL ? ENET_INTR_L ENET_MDIO ENET_MDC ENET_PWRDWN_L TABLE_SPACING_RULE_ITEM D 18 31 31 D SOURCE: MCP73 Interface DG (DG-02974-001_v01), Sections 2.7.2 & 2.7.4 88E1116R (Ethernet PHY) Constraints ENET_RXCLK TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP ENET_MDI_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF ENET_RXD_STRAP ENET_RXD_STRAP ENET_RXD TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT 25 MIL ? TABLE_SPACING_RULE_ITEM ENET_MDI * ENET_TXCLK ENET_TXD0 ENET_TXD ENET_TXD SOURCE: MCP73 Interface DG (DG-02974-001_v01), Section 2.7.4 ENET_MDI 31 18 31 31 18 31 18 31 18 31 31 31 31 31 31 31 31 31 32 31 32 32 32 C C B B A SYNC_MASTER=MASTER SYNC_DATE=MASTER PAGE TITLE Ethernet Constraints DRAWING NUMBER Apple Inc 051-8561 R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED SIZE D REVISION C.0.0 BRANCH PAGE 104 OF 109 SHEET 73 OF 76 A SMC SMBus Net Properties TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 1TO1_DIFFPAIR * =STANDARD =STANDARD =STANDARD =STANDARD 0.1 MM 0.1 MM ELECTRICAL_CONSTRAINT_SET NET_TYPE PHYSICAL SPACING TABLE_PHYSICAL_RULE_ITEM SMBUS_SMC_A_S3_SCL SMBUS_SMC_A_S3_SDA SMBUS_SMC_B_S0_SCL SMBUS_SMC_B_S0_SDA SMBUS_SMC_0_S0_SCL SMBUS_SMC_0_S0_SDA SMBUS_SMC_BSA_SCL SMBUS_SMC_BSA_SDA SMBUS_SMC_MGMT_SCL SMBUS_SMC_MGMT_SDA D SMB_55S SMB_55S SMB_55S SMB_55S SMB_55S SMB_55S SMB_55S SMB_55S SMB_55S SMB_55S SMB SMB SMB SMB SMB SMB SMB SMB SMB SMB SMBUS_SMC_A_S3_SCL SMBUS_SMC_A_S3_SDA SMBUS_SMC_B_S0_SCL SMBUS_SMC_B_S0_SDA SMBUS_SMC_0_S0_SCL SMBUS_SMC_0_S0_SDA SMBUS_SMC_BSA_SCL SMBUS_SMC_BSA_SDA SMBUS_SMC_MGMT_SCL SMBUS_SMC_MGMT_SDA 38 38 38 38 38 38 38 38 D 38 38 SMBus Charger Net Properties ELECTRICAL_CONSTRAINT_SET CHGR_CSI CHGR_CSO NET_TYPE PHYSICAL SPACING 1TO1_DIFFPAIR 1TO1_DIFFPAIR 1TO1_DIFFPAIR 1TO1_DIFFPAIR CHGR_CSI_P CHGR_CSI_N CHGR_CSI_R_P CHGR_CSI_R_N 1TO1_DIFFPAIR 1TO1_DIFFPAIR 1TO1_DIFFPAIR 1TO1_DIFFPAIR CHGR_CSO_P CHGR_CSO_N CHGR_CSO_R_P CHGR_CSO_R_N 55 55 55 55 55 55 40 55 40 55 C C B B A SYNC_MASTER=T27_MLB SYNC_DATE=02/16/2010 PAGE TITLE SMC Constraints DRAWING NUMBER Apple Inc 051-8561 R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED SIZE D REVISION C.0.0 BRANCH PAGE 106 OF 109 SHEET 74 OF 76 A TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET ALLOW ROUTE ON LAYER? LAYER MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP SENSE_1TO1_55S * =1:1_DIFFPAIR =55_OHM_SE =55_OHM_SE =55_OHM_SE =1:1_DIFFPAIR =1:1_DIFFPAIR THERM_1TO1_55S * =1:1_DIFFPAIR =55_OHM_SE =55_OHM_SE =55_OHM_SE =1:1_DIFFPAIR =1:1_DIFFPAIR Misc Net Properties DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM ELECTRICAL_CONSTRAINT_SET TABLE_PHYSICAL_RULE_ITEM Power Net Properties NET_TYPE PHYSICAL SPACING ELECTRICAL_CONSTRAINT_SET (PCIE_AP) CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE CLK_PCIE PCIE_CLK100M_AP_CONN_P PCIE_CLK100M_AP_CONN_N (USB_EXTA) (USB_EXTA) (USB_EXTA) (USB_EXTA) (USB_TPAD) (USB_TPAD) (USB_CAMERA) (USB_CAMERA) USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB USB USB USB USB USB USB USB USB USB USB_EXTA_MUXED_P USB_EXTA_MUXED_N USB_LT1_P USB_LT1_N USB_TPAD_R_P USB_TPAD_R_N USB_CAMERA_CONN_P USB_CAMERA_CONN_N USB_LT2_P USB_LT2_N ENET_MDI_100D ENET_MDI_100D ENETCONN ENETCONN ENETCONN_P ENETCONN_N SATA_90D SATA_90D SATA_90D SATA_90D SATA SATA SATA SATA SATA_ODD_R2D_UF_P SATA_ODD_R2D_UF_N SATA_ODD_D2R_UF_P SATA_ODD_D2R_UF_N SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D USB_90D USB_90D LVDS_100D LVDS_100D CLK_PCIE_100D CLK_PCIE_100D USB_90D USB_90D USB_90D USB_90D SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA PCIE PCIE PCIE PCIE USB USB LVDS LVDS CLK_PCIE CLK_PCIE USB USB USB USB SATA_HDD_D2R_FILT_P SATA_HDD_D2R_FILT_N SATA_HDD_D2R_UF_P SATA_HDD_D2R_UF_N SATA_HDD_R2D_UF_P SATA_HDD_R2D_UF_N SATA_HDD_D2R_RDRV_IN_P SATA_HDD_D2R_RDRV_IN_N SATA_HDD_R2D_RDRV_IN_P SATA_HDD_R2D_RDRV_IN_N SATA_HDD_D2R_RDRV_OUT_P SATA_HDD_D2R_RDRV_OUT_N SATA_HDD_R2D_RDRV_OUT_P SATA_HDD_R2D_RDRV_OUT_N SATA_HDD_D2R_NORDRV_P SATA_HDD_D2R_NORDRV_N SATA_HDD_R2D_NORDRV_P SATA_HDD_R2D_NORDRV_N CONN_PCIE_MINI_D2R_P CONN_PCIE_MINI_D2R_N CONN_PCIE_MINI_R2D_P CONN_PCIE_MINI_R2D_N CONN_USB2_BT_P CONN_USB2_BT_N LVDS_IG_A_CLK_F_P LVDS_IG_A_CLK_F_N PCIE_CLK100M_MINI_CONN_P PCIE_CLK100M_MINI_CONN_N CONN_USB_EXTA_P CONN_USB_EXTA_N CONN_USB_EXTB_P CONN_USB_EXTB_N CPUTHMSNS_D2 TABLE_PHYSICAL_RULE_ITEM DIFFPAIR * =1:1_DIFFPAIR =1:1_DIFFPAIR =1:1_DIFFPAIR =1:1_DIFFPAIR TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM D SENSE * =2:1_SPACING ? THERM * =2:1_SPACING ? TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM AUDIO * =2:1_SPACING ? SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_HEAD I300 CPUTHMSNS_D2 34 72 I301 34 72 CPU_THERMD MCPTHMSNS_D2 43 43 MCP_THMDIODE 64 64 SENSE_DIFFPAIR SENSE_DIFFPAIR TABLE_SPACING_RULE_ITEM ENETCONN * ? 25 MILS TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT 33 33 SENSE_DIFFPAIR 33 33 TABLE_SPACING_RULE_ITEM GND * ? =STANDARD TABLE_SPACING_RULE_ITEM MEM_POWER * ? =STANDARD TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT GND_P2MM * 0.20 MM 1000 TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM PWR_P2MM * 0.20 MM 1000 TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET TABLE_SPACING_ASSIGNMENT_ITEM MEM_CLK GND * GND_P2MM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CLK MEM_POWER * PWR_P2MM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CMD GND * GND_P2MM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CMD MEM_POWER * PWR_P2MM TABLE_SPACING_ASSIGNMENT_ITEM C MEM_CTRL GND * GND_P2MM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CTRL MEM_POWER * PWR_P2MM TABLE_SPACING_ASSIGNMENT_ITEM MEM_DATA GND * GND_P2MM TABLE_SPACING_ASSIGNMENT_ITEM MEM_DATA MEM_POWER * PWR_P2MM TABLE_SPACING_ASSIGNMENT_ITEM MEM_DQS GND * GND_P2MM TABLE_SPACING_ASSIGNMENT_ITEM MEM_DQS MEM_POWER * PWR_P2MM PCIE_AP_D2R TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET CLK_PCIE GND * GND_P2MM PCIE GND * GND_P2MM TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET CLK_FSB GND * GND_P2MM CPU_COMP GND * GND_P2MM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM SATA GND * GND_P2MM USB GND * GND_P2MM SB_POWER * PWR_P2MM SATA SB_POWER * PWR_P2MM USB_BT TABLE_SPACING_ASSIGNMENT_ITEM CPU_GTLREF GND * GND_P2MM TABLE_SPACING_ASSIGNMENT_ITEM CLK_PCIE PCIE_AP_R2D TABLE_SPACING_ASSIGNMENT_ITEM LVDS_IG_A_CLK TABLE_SPACING_ASSIGNMENT_ITEM CPU_VCCSENSE GND * GND_P2MM MCP_PE1_REFCLK TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM I296 USB_EXTA TABLE_SPACING_ASSIGNMENT_ITEM USB SB_POWER * I297 PWR_P2MM I299 TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE GND * GND_P2MM 33 33 SENSE_DIFFPAIR 33 33 33 33 SENSE_DIFFPAIR SENSE_DIFFPAIR SENSE_DIFFPAIR GND CPUTHMSNS_D1_P CPUTHMSNS_D1_N CPUTHMSNS_D2_P CPUTHMSNS_D2_N CPU_THERMD_P CPU_THERMD_N MCPTHMSNS_D2_P MCPTHMSNS_D2_N MCP_THMDIODE_P MCP_THMDIODE_N ISNS_1V5_S3_P ISNS_1V5_S3_N ISNS_1V5_S3_R_P ISNS_1V5_S3_R_N ISNS_AIRPORT_P ISNS_AIRPORT_N ISNS_AIRPORT_R_P ISNS_AIRPORT_R_N ISNS_HDD_P ISNS_HDD_N ISNS_HDD_R_P ISNS_HDD_R_N ISNS_LCDBKLT_P ISNS_LCDBKLT_N ISNS_LCDBKLT_R_P ISNS_LCDBKLT_R_N ISNS_ODD_P ISNS_ODD_N ISNS_ODD_R_P ISNS_ODD_R_N ISNS_CPUVTT_P ISNS_CPUVTT_N MCPCORES0_VSEN_P MCPCORES0_VSEN_N PP1V5R1V35_S3 PP3V3_S5 PP3V3_S0 PP1V5_S0 GND THERM THERM THERM THERM THERM THERM THERM THERM THERM THERM SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE MEM_POWER SB_POWER SB_POWER SB_POWER GND 41 41 41 41 10 41 10 41 D 19 41 19 41 30 46 30 46 46 46 33 46 33 46 46 46 46 67 46 67 33 46 33 46 46 46 40 40 22 59 22 59 C 8 62 62 62 30 30 Audio Net Properties 30 30 30 ELECTRICAL_CONSTRAINT_SET NET_TYPE PHYSICAL SPACING 64 64 30 30 34 34 34 DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR AUDIO AUDIO AUDIO AUDIO AUDIO AUDIO AUD_SPKRAMP_LIN_P AUD_SPKRAMP_LIN_N AUD_SPKRAMP_SUBIN_P AUD_SPKRAMP_SUBIN_N AUD_SPKRAMP_RIN_P AUD_SPKRAMP_RIN_N DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR AUDIO AUDIO AUDIO AUDIO AUDIO AUDIO SSM2315L_P SSM2315L_N SSM2315S_P SSM2315S_N SSM2315R_P SSM2315R_N DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR AUDIO AUDIO AUDIO AUDIO AUDIO AUDIO SPKRCONN_L_OUT_P SPKRCONN_L_OUT_N SPKRCONN_S_OUT_P SPKRCONN_S_OUT_N SPKRCONN_R_OUT_P SPKRCONN_R_OUT_N DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR AUDIO AUDIO AUDIO AUDIO BI_MIC_P BI_MIC_N HS_MIC_P HS_MIC_N 34 GND_P2MM * THERM_1TO1_55S THERM_1TO1_55S THERM_1TO1_55S THERM_1TO1_55S THERM_1TO1_55S THERM_1TO1_55S THERM_1TO1_55S THERM_1TO1_55S THERM_1TO1_55S THERM_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S 30 TABLE_SPACING_ASSIGNMENT_ITEM ENET_MDI NET_TYPE PHYSICAL SPACING I277 SPACING_RULE_SET TABLE_SPACING_ASSIGNMENT_ITEM LVDS USB_EXTB I298 TABLE_SPACING_ASSIGNMENT_HEAD SPK_OUT B SPK_OUT SPK_OUT MCP Fanout Constraint Relaxations B 52 53 52 53 52 53 52 53 TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH OVERRIDE OVERRIDE MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP OVERRIDE OVERRIDE TABLE_PHYSICAL_RULE_ITEM MEM_40S * OVERRIDE OVERRIDE 0.09 MM 5.8 MM OVERRIDE OVERRIDE GRAPHICS NET PROPERTIES TABLE_PHYSICAL_RULE_ITEM MCP_DV_COMP TOP OVERRIDE OVERRIDE 0.1 MM 500 MIL OVERRIDE OVERRIDE OVERRIDE OVERRIDE 0.1 MM 500 MIL OVERRIDE OVERRIDE OVERRIDE OVERRIDE ELECTRICAL_CONSTRAINT_SET OVERRIDE OVERRIDE OVERRIDE OVERRIDE TABLE_PHYSICAL_RULE_ITEM MCP_MEM_COMP TOP OVERRIDE OVERRIDE (DP_EXT_ML) TABLE_PHYSICAL_RULE_ITEM MCP_MII_COMP TOP OVERRIDE OVERRIDE 0.1 MM 500 MIL OVERRIDE OVERRIDE OVERRIDE OVERRIDE 0.1 MM 500 MIL OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE TABLE_PHYSICAL_RULE_ITEM MCP_USB_RBIAS TOP OVERRIDE OVERRIDE TABLE_PHYSICAL_RULE_ITEM MCP_DV_COMP * OVERRIDE OVERRIDE OVERRIDE OVERRIDE 0.25 MM 250 MIL OVERRIDE OVERRIDE OVERRIDE (DP_EXT_AUX_CH) OVERRIDE NET_TYPE PHYSICAL SPACING DP_90D DP_90D DP_90D DP_90D DP_90D DP_90D DP_90D DP_90D DP_90D DP_90D DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DP_EXT_ML_P DP_EXT_ML_N DP_EXT_ML_C_P DP_EXT_ML_C_N DP_EXT_ML_F_P DP_EXT_ML_F_N DP_EXT_AUX_CH_C_P DP_EXT_AUX_CH_C_N DP_EXT_DDC_DATA DP_EXT_DDC_CLK 66 66 66 66 66 66 66 66 65 65 A SYNC_MASTER=MASTER SYNC_DATE=MASTER PAGE TITLE K87 SPECIFIC CONSTRAINTS DRAWING NUMBER Apple Inc 051-8561 R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED SIZE D REVISION C.0.0 BRANCH PAGE 108 OF 109 SHEET 75 OF 76 A K87 BOARD-SPECIFIC SPACING & PHYSICAL CONSTRAINTS TABLE_BOARD_INFO BOARD LAYERS BOARD AREAS BOARD UNITS (MIL or MM) ALLEGRO VERSION TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM NO_TYPE,BGA_P1MM MM 15.5.1 TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET TABLE_SPACING_RULE_ITEM DEFAULT * 0.1 MM ? * * BGA_P1MM PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP DEFAULT * Y =50_OHM_SE 0.100MM 30 MM MM MM STANDARD * =DEFAULT ? BGA_P1MM * =DEFAULT ? MEM_CLK * BGA_P1MM BGA_P2MM CLK_FSB * BGA_P1MM BGA_P2MM TABLE_PHYSICAL_RULE_ITEM * Y =DEFAULT =DEFAULT 12.7 MM =DEFAULT BGA_P2MM * =DEFAULT ? CLK_LPC * BGA_P1MM BGA_P2MM BGA_P3MM LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP * =DEFAULT ? LINE-TO-LINE SPACING WEIGHT TOP,BOTTOM Y TABLE_PHYSICAL_ASSIGNMENT_ITEM CLK_PCIE * BGA_P1MM BGA_P2MM CLK_SLOW * BGA_P1MM BGA_P2MM FSB_DSTB FSB_DSTB BGA_P1MM BGA_P3MM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM DIFFPAIR NECK GAP D TABLE_SPACING_RULE_HEAD SPACING_RULE_SET TABLE_PHYSICAL_RULE_ITEM 55_OHM_SE STANDARD TABLE_SPACING_ASSIGNMENT_ITEM TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET BGA_P1MM =DEFAULT TABLE_SPACING_RULE_ITEM D MEM_40S TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_RULE_ITEM STANDARD PHYSICAL_RULE_SET TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM AREA_TYPE BGA_P1MM TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD TABLE_PHYSICAL_ASSIGNMENT_HEAD NET_PHYSICAL_TYPE TABLE_SPACING_ASSIGNMENT_ITEM 0.090 MM LAYER 0.090 MM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM 55_OHM_SE * Y LAYER ALLOW ROUTE ON LAYER? 0.076 MM 0.076 MM =STANDARD =STANDARD 1.5:1_SPACING * 0.15 MM ? 2:1_SPACING * 0.2 MM ? 2.5:1_SPACING * 0.25 MM ? 3:1_SPACING * 0.3 MM ? 4:1_SPACING * 0.4 MM ? LINE-TO-LINE SPACING WEIGHT =STANDARD TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP TABLE_SPACING_RULE_ITEM DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM 50_OHM_SE TOP,BOTTOM Y 0.115 MM TABLE_SPACING_RULE_ITEM 0.115 MM TABLE_PHYSICAL_RULE_ITEM 50_OHM_SE * Y 0.076 MM 0.076 MM =STANDARD =STANDARD =STANDARD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER TABLE_PHYSICAL_RULE_ITEM 40_OHM_SE TOP,BOTTOM Y 0.165 MM TABLE_SPACING_RULE_ITEM 0.100 MM 1.5X_DIELECTRIC TOP,BOTTOM 0.105 MM ? 2X_DIELECTRIC TOP,BOTTOM 0.140 MM ? 3X_DIELECTRIC TOP,BOTTOM 0.210 MM ? 4X_DIELECTRIC TOP,BOTTOM 0.280 MM ? 5X_DIELECTRIC TOP,BOTTOM 0.350 MM ? 1.5X_DIELECTRIC * 0.095 MM ? 2X_DIELECTRIC * 0.126 MM ? 3X_DIELECTRIC * 0.189 MM ? 4X_DIELECTRIC * 0.252 MM ? 5X_DIELECTRIC * 0.315 MM ? TABLE_PHYSICAL_RULE_ITEM 40_OHM_SE * Y 0.126 MM 0.100 MM =STANDARD =STANDARD =STANDARD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM 27P4_OHM_SE TOP,BOTTOM Y 0.310 MM 0.310 MM 27P4_OHM_SE * Y 0.222 MM 0.222 MM TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM =STANDARD =STANDARD TABLE_SPACING_RULE_ITEM =STANDARD TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 70_OHM_DIFF * N =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM C 70_OHM_DIFF ISL3,ISL4,ISL9,ISL10 Y 0.151 MM 0.100 MM =STANDARD 0.224 MM C 0.224 MM TABLE_PHYSICAL_RULE_ITEM 70_OHM_DIFF TOP,BOTTOM Y 0.185 MM 0.100 MM 0.200 MM 0.200 MM PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 90_OHM_DIFF * N =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD 90_OHM_DIFF ISL3,ISL4,ISL9,ISL10 Y 0.095 MM 0.095 MM 0.234 MM 0.234 MM 90_OHM_DIFF TOP,BOTTOM Y 0.112 MM 0.112 MM 0.220 MM 0.220 MM PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 100_OHM_DIFF * N =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD 100_OHM_DIFF ISL3,ISL4,ISL9,ISL10 Y 0.075 MM 0.075 MM 0.244 MM 0.244 MM 100_OHM_DIFF TOP,BOTTOM Y 0.091 MM 0.091 MM 0.230 MM 0.230 MM PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 1:1_DIFFPAIR * Y =STANDARD =STANDARD =STANDARD 0.1 MM 0.1 MM TABLE_PHYSICAL_RULE_HEAD TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD TABLE_PHYSICAL_RULE_ITEM B B A SYNC_MASTER=MASTER SYNC_DATE=MASTER PAGE TITLE K87 RULE DEFINITIONS DRAWING NUMBER Apple Inc 051-8561 R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED SIZE D REVISION C.0.0 BRANCH PAGE 109 OF 109 SHEET 76 OF 76 A ... TABLE_BOMGROUP_ITEM 639-1116 PCBA ,MLB_ LDO,MOLEX ,K87 K86 _K87_ COMMON ,K87_ SPECIFIC,MOLEX_DDR_CONN,EEEE:DD17 TABLE_BOMGROUP_ITEM 085-1799 K87 MLB_ LDO DEVELOPMENT BOM K86 _K87_ DEVELOPMENT_PVT Development... on csa between K87 and K86 BOMOPTION is "MCP83M" Per K87: Call out LED:K86 _K87 BOMOPTION in the K87_ MISC BOM group Added LED:K86 _K87 BOMOPTION to the K87_ MISC BOM group... K86 /K87: Production Debug Components Changed 085-1093 to call out K87_ DEVEL_PVT instead of K87_ DEVEL_ENG Changed K87_ COMMON to call out K87_ DEBUG_PVT instead of K87_ DEBUG_ENG Diff