Apple imac 27 a1419 d8 MLB 051 9504 rev 7 0 0

8 ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5% ALL CAPACITANCE VALUES ARE IN MICROFARADS ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ TABLE_TABLEOFCONTENTS_HEAD TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM C TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM B TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM A TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM DRAWING TITLE=K22 Date 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 45 46 47 49 50 51 52 53 54 55 56 59 61 62 63 64 N/A Table of Contents MASTER System Block Diagram D8_MLB Power Block Diagram (.csa) TABLE_TABLEOFCONTENTS_HEAD 01/05/2012 TABLE_TABLEOFCONTENTS_ITEM 04/23/2012 TABLE_TABLEOFCONTENTS_ITEM 12/19/2011 TABLE_TABLEOFCONTENTS_ITEM 06/22/2012 TABLE_TABLEOFCONTENTS_ITEM 06/20/2012 TABLE_TABLEOFCONTENTS_ITEM 03/25/2012 TABLE_TABLEOFCONTENTS_ITEM 04/02/2012 TABLE_TABLEOFCONTENTS_ITEM D8_MARK BOM Configuration D8_MLB DEBUG LEDS D8_TAVYS Power Connectors/Aliases D8_DOUG Holes/PD parts D8_MLB Unused Signal Aliases D8_MLB_ULTIMATE 08/23/2011 TABLE_TABLEOFCONTENTS_ITEM 03/23/2012 TABLE_TABLEOFCONTENTS_ITEM 03/15/2012 TABLE_TABLEOFCONTENTS_ITEM 03/15/2012 TABLE_TABLEOFCONTENTS_ITEM 03/15/2012 TABLE_TABLEOFCONTENTS_ITEM 03/15/2012 TABLE_TABLEOFCONTENTS_ITEM 03/29/2012 TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM CPU NON-GFX DECOUPLING 12/20/2011 D7_MLB TABLE_TABLEOFCONTENTS_ITEM GFX DECOUPLING & PCH PWR ALIAS 01/26/2012 D8_KOSECOFF Signal Aliases K70_MLB CPU DMI/PEG/FDI/RSVD D8_ROSITA CPU CLOCK/MISC/JTAG D7_MLB CPU DDR3 INTERFACES D7_MLB CPU POWER D7_MLB CPU GROUNDS D7_MLB STRAPS,PULL UPS,PULL DOWNS FOR PCH AND CPU D8_MLB PCH SATA/PCIE/CLK/LPC/SPI D8_MLB PCH DMI/FDI/GRAPHICS D7_MLB PCH PCI/USB D7_MLB PCH MISC N/A TABLE_TABLEOFCONTENTS_ITEM 03/15/2012 TABLE_TABLEOFCONTENTS_ITEM 03/15/2012 TABLE_TABLEOFCONTENTS_ITEM N/A TABLE_TABLEOFCONTENTS_ITEM N/A TABLE_TABLEOFCONTENTS_ITEM 03/15/2012 TABLE_TABLEOFCONTENTS_ITEM N/A TABLE_TABLEOFCONTENTS_ITEM 01/26/2012 TABLE_TABLEOFCONTENTS_ITEM N/A TABLE_TABLEOFCONTENTS_ITEM D8_MLB PCH POWER D8_MLB PCH GROUNDS D7_MLB PCH DECOUPLING D8_MLB CPU and PCH XDP D7_MLB CHIPSET SUPPORT D8_MLB USB 2.0 HUB (BT/SMC) 03/23/2012 TABLE_TABLEOFCONTENTS_ITEM 04/23/2012 TABLE_TABLEOFCONTENTS_ITEM 03/19/2012 TABLE_TABLEOFCONTENTS_ITEM D8_ROSITA CPU Memory S3 Support D8_MARK DDR3 SO-DIMM Connector A Slot0 DDR3 SO-DIMM Connector A Slot1 D8_KOSECOFF 03/19/2012 D8_KOSECOFF TABLE_TABLEOFCONTENTS_ITEM DDR3 SO-DIMM CONNECTOR B SLOT0 03/19/2012 D8_KOSECOFF TABLE_TABLEOFCONTENTS_ITEM DDR3 SO-DIMM CONNECTOR B SLOT1 03/19/2012 D8_KOSECOFF 03/19/2012 D8_KOSECOFF TABLE_TABLEOFCONTENTS_ITEM DDR3 ALIASES AND BITSWAPS TABLE_TABLEOFCONTENTS_ITEM DDR3/FRAMEBUF VREF MARGINING 03/19/2012 D8_KOSECOFF 07/02/2012 TABLE_TABLEOFCONTENTS_ITEM N/A TABLE_TABLEOFCONTENTS_ITEM 03/15/2012 TABLE_TABLEOFCONTENTS_ITEM 03/15/2012 TABLE_TABLEOFCONTENTS_ITEM 07/02/2012 TABLE_TABLEOFCONTENTS_ITEM 07/02/2012 TABLE_TABLEOFCONTENTS_ITEM 07/02/2012 TABLE_TABLEOFCONTENTS_ITEM 03/23/2012 TABLE_TABLEOFCONTENTS_ITEM 03/15/2012 TABLE_TABLEOFCONTENTS_ITEM 01/31/2012 TABLE_TABLEOFCONTENTS_ITEM 03/23/2012 TABLE_TABLEOFCONTENTS_ITEM 03/23/2012 TABLE_TABLEOFCONTENTS_ITEM 03/22/2012 TABLE_TABLEOFCONTENTS_ITEM 07/19/2012 TABLE_TABLEOFCONTENTS_ITEM N/A TABLE_TABLEOFCONTENTS_ITEM 06/22/2012 TABLE_TABLEOFCONTENTS_ITEM 06/20/2012 TABLE_TABLEOFCONTENTS_ITEM 02/25/2012 TABLE_TABLEOFCONTENTS_ITEM AIRPORT/BT TABLE_TABLEOFCONTENTS_ITEM D8_FIYIN Thunderbolt Host (1 of 2) D8_MLB Thunderbolt Host (2 of 2) D7_MLB Thunderbolt Power Support D7_MLB ETHERNET PHY (CAESAR IV+) D8_FIYIN Ethernet Support & Connector D8_FIYIN SD READER CONNECTOR D8_FIYIN Camera Controller D8_ROSITA Camera Controller Support D7_MLB SATA Connectors D8_JERRY EXTERNAL USB PORTS A & B D8_ROSITA EXTERNAL USB PORTS C & D D8_ROSITA SMC D8_MARK SMC Support D8_DOUG SPI and Debug Connector D8_MLB SMBus Connections D8_TAVYS I and V Sense D8_DOUG HDD/SSD Temp Sense D8_JERRY Temperature Sensors 06/07/2012 TABLE_TABLEOFCONTENTS_ITEM 07/19/2012 TABLE_TABLEOFCONTENTS_ITEM 04/23/2012 TABLE_TABLEOFCONTENTS_ITEM 06/13/2012 TABLE_TABLEOFCONTENTS_ITEM 06/13/2012 TABLE_TABLEOFCONTENTS_ITEM 06/13/2012 TABLE_TABLEOFCONTENTS_ITEM 06/13/2012 TABLE_TABLEOFCONTENTS_ITEM D8_DOUG System Fan D8_DOUG I and V Sense D8_MARK AUDIO: CODEC/REGULATORS D8_DAVID AUDIO: HEADPHONE AMP D8_DAVID AUDIO: LEFT SPKR AMP D8_DAVID AUDIO: RIGHT SPKR AMP 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 92 93 94 95 96 97 98 99 114 115 116 117 120 121 122 123 124 125 126 127 128 129 130 131 132 134 135 136 138 139 140 141 142 143 D8_DIRK Audio: Spkr/Mic Conn D8_DAVID DESCRIPTION OF REVISION 0001607307 CK APPD AUDIO: Detects/Grounding D8_DAVID AUDIO: Speaker ID D8_DAVID PM Regulator Enables D8_MARK PM Power Good D8_MARK VReg CPU Core/AXG Cntl D8_MLB VReg CPU Core Phases D8_MLB VReg CPU AXG Phases D8_MLB VReg CPU 1.05V S0 02/25/2012 D8_KOSECOFF VReg CPU VccSA S0 02/25/2012 D8_KOSECOFF VReg 3.3V S5/5V S4 D8_MLB VReg VDDQ and 1.8V S0 D8_KOSECOFF VREG 3.42V G3HOT D8_MLB FET-Controlled S0 and S4 D8_MLB KEPLER PCI-E D8_AARON KEPLER CORE/FB POWER D8_YAN KEPLER FRAME BUFFER I/F D8_YAN GPU SIGNAL & POWER ALIASES D8_YAN GDDR5 Frame Buffer A D8_YAN GDDR5 Frame Buffer B D8_YAN KEPLER EDP/DP/GPIO D8_YAN KEPLER GPIOS,CLK & STRAPS D8_YAN KEPLER PEX PWR/GNDS D8_YAN Internal DP MUXing D8_AARON TBT DDC Crossbar D7_MLB Thunderbolt Connector A D8_AARON Internal DP Support D8_MLB Thunderbolt Connector B D8_AARON Backlight Controller MCU D8_MLB Backlight LED Driver D8_MLB Backlight Controller D8_MLB VReg GPU Core Phases D8_MLB VReg GPU Core Phases D8_MLB VREG GPU CORE PHASE D8_MLB GPU VDDQ AND 1V05 GPU/PCH/TBT VREGS D8_MLB D8 RULE DEFINITIONS D8_KOSECOFF DDR3 Constraints 03/19/2012 D8_KOSECOFF CPU PCIe Constraints D8_AARON CPU MISC/DMI/FDI/XDP Constraints D8_ROSITA SATA/FDI/XDP Constraints D8_MARK PCH and BR Constraints D8_MARK 2012-08-28 D 06/13/2012 06/13/2012 04/23/2012 04/23/2012 02/28/2012 02/28/2012 02/28/2012 02/28/2012 02/25/2012 04/11/2012 05/14/2012 03/13/2012 04/09/2012 C 05/15/2012 04/09/2012 04/09/2012 04/09/2012 04/09/2012 07/27/2012 04/09/2012 03/13/2012 03/15/2012 03/13/2012 03/21/2012 03/13/2012 04/23/2012 04/23/2012 04/23/2012 02/28/2012 02/25/2012 B 02/06/2012 04/18/2012 03/19/2012 03/13/2012 03/23/2012 02/10/2012 02/10/2012 06/22/2012 USB/Camera Constraints D8_KOSECOFF 04/23/2012 SMBus/Sensor Constraints D8_MARK 02/10/2012 VReg Constraints D8_MARK CPU VReg Constraints D8_MARK Platform VReg Constraints D8_MARK TBT/DP Constraints D8_AARON GDDR5/GPU Constraints D8_AARON BLC Constraints D8_MLB GPU VREG CONSTRAINTS D8_MARK ETHERNET/SD CONSTRAINTS D8_FIYIN AUTO-CONSTRAINTS D8_MARK 02/10/2012 02/10/2012 03/13/2012 03/13/2012 12/19/2011 02/10/2012 07/02/2012 A 04/23/2012 DRAWING TITLE SCH,D8,MLB 04/23/2012 AUTO-CONSTRAINTS D8_MARK AUTO-CONSTRAINTS D8_MARK DRAWING NUMBER 04/23/2012 Apple Inc 04/23/2012 AUTO-CONSTRAINTS D8_MARK 051-9504 REVISION 7.0.0 R 04/23/2012 AUTO-CONSTRAINTS D8_MARK AUTO-CONSTRAINTS D8_MARK ENGINEERING RELEASED 06/13/2012 04/23/2012 D8_DAVID ECN 06/29/2012 AUDIO: Jack, Mikey, CHS Switch LAST_MODIFIED=Mon Aug 27 13:24:34 2012 REV Date ABBREV=DRAWING Sync TABLE_TABLEOFCONTENTS_ITEM DATE LAST_MODIFIED=Mon Aug 27 13:24:34 2012 Contents Sync Page Contents Page TABLE_TABLEOFCONTENTS_ITEM D8 MLB (.csa) D NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART DRAWING IV ALL RIGHTS RESERVED BRANCH PAGE prefsb OF 143 SHEET OF 117 SIZE D D D System Block diagram can be found on Kismet PATH: Kismet > K70/72 > Block Diagrams > K70 Block Diagram C C B B A D8_MLB 01/05/2012 PAGE TITLE System Block Diagram DRAWING NUMBER Apple Inc 051-9504 REVISION 7.0.0 R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED BRANCH PAGE prefsb OF 143 SHEET OF 117 SIZE D A PP12V_S0_BLC Supply Module AC/DC U7100 Regulator VD2R D PP12V_ACDC Reg G3H 12V ID2R PD2R PP12V_S0 PP12V_G3H Vin en S0 VC0C Reg S0 Core Reg S0 AXG IC0C VC0G PP12V_S5 PPVCORE_S0_CPU CPU (Core) PC0G PPVAXG_S0 CPU (AXG) D U7400 Regulator U7801 Regulator VD2R Vin en G3H IC0G PC0C IC0I Reg G3H 3V42 Vin en S0 PC0I PP3V42_G3H Reg S0 VccIO PP1V05_S0_CPU CPU (VccIO) VccSA PPVCCSA_S0 CPU SMC, RTC, MojoMux U7500 U7600 Regulator Regulator Vin en S5 VD2R LDO S5 5V PP5V_S5 Reg S5 3.3V PP3V3_S5 V3V3 ALS, CAM, BT USB Hub, SMC, TBT I/O PW0R IW0R Vin en S0 PC0S Reg S0 Bootrom, PCH, SMC, XDP, SD Card, USB Mux, VRD, PwrCtl PP3V3_S4 C IC0S PCH, PwrCtl PP3V3_S4_AP PP3V3_S4_ENET UB400 Regulator Vin en S0 WIFI C VG0C Reg S0 GPU IG0C PG0C PPVCORE_S0_GPU GPU (Core) Ethernet UB750 PP3V3_S0 V3V3 IW1R en S4 Reg S4 Regulator Audio, LCD TCON, SnsCtl, VRD, PCH SD Card, DP Mux, DP X-bar VD2R PH1R 5V PP3V3_S0_SSD SSD PP3V3_TBTLC TBT Router PP5V_S4 CAM, USB Ports, VRegCtl IG0F Vin en S0 PG0F Reg S0 GPU FBVDDQ PPFBVDDQ_S0_GPU 1V05 P1V05_S0 GPU (FB) UB700 VH05 Regulator PH05 IH05 PP5V_S0_HDD HDD (5V) VD2R IR1R PP5V_S0 B Vin en S0 PR1R Reg S0 Audio, PCH VRegCtl, SnsCtl VN1R IN1R PN1R GPU (IOVDD, PLLVDD) P1V05_S0_PCH B PCH (VCC, VccIO) U7700 Regulator PP1V05_TBTCIO Vin en S3 VM0R Reg S3 VDDQ IM0R PM0R PPVDDQ_S3_DDR DIMM (1V5) PP1V05_TBTLC Loads VC0M IC0M LDO S3 PC0M PP1V5_S0 Audio PP1V5_S0_CPU_MEM CPU (Mem) VTT PPDDRVTT_S3 VTT PPDDRVTT_S0 A S0 LDO S0 PPHV_SW_TBTAPWR DIMM VREF Margining CA IH02 = ( 1.176 * PGTR = 1.176 * PH0R = PH02 PC0C PG0C + + PC0G PG0F + PC0M ) + PC0S PH02 PP12V_S0_HDD SYNC_MASTER=D8_MARK TBT Port A PAGE TITLE U7750 Regulator + PC0I TBT Port B PPHV_SW_TBTBPWR HDD (12V) DIMM (VTT) High-side Component Total Power Keys PCTR TBT Router Fan LCD GPU Speaker amps TBT IO VD2R en TBT Router PP5V_S0 + 5.7 (GK104/GK107_BLENDED_CONSTANT) Vin en S0 SYNC_DATE=04/23/2012 Power Block Diagram DRAWING NUMBER Apple Inc Reg S0 PP1V8_S0_REG 1.8V PH05 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED 7.0.0 R CPU PLL NOTICE OF PROPRIETARY PROPERTY: + 051-9504 REVISION BRANCH PAGE prefsb OF 143 SHEET OF 117 SIZE D A BOM Variants TABLE_BOMGROUP_HEAD BOM NUMBER BOM NAME BOM OPTIONS CPU SOCKET TABLE_BOMGROUP_ITEM 639-3816 PCBA,MLB,2.9G,4C,GK107,SAM,D8 TABLE_5_HEAD PART# D8_COMMON,D8,CPU:4C_2P9GHZ,GPU:107EGE,FB:BOTH_SAMSUNG,EEEE:F2FR QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION TABLE_BOMGROUP_ITEM 639-3952 PCBA,MLB,3.1G,4C,GK107,SAM,D8 TABLE_5_ITEM 511S0073 D8_COMMON,D8,CPU:4C_3P1GHZ,GPU:107EGE,FB:BOTH_SAMSUNG,EEEE:F49T U1000 SOCKET,MOLEX,LGA1155,CPU-LF CRITICAL TABLE_BOMGROUP_ITEM 639-4092 PCBA,MLB,2.9G,4C,GK107,HYN.D8 D8_COMMON,D8,CPU:4C_2P9GHZ,GPU:107EGE,FB:BOTH_HYNIX,EEEE:F653 639-4093 PCBA,MLB,3.1G,4C,GK107,HYN.D8 D8_COMMON,D8,CPU:4C_3P1GHZ,GPU:107EGE,FB:BOTH_HYNIX,EEEE:F654 TABLE_BOMGROUP_ITEM D CPU SOCKET ALTERNATES D TABLE_BOMGROUP_ITEM 085-4433 PCBA,MLB,DEV,D8 DEVELOPMENT,D8_DEVEL TABLE_ALT_HEAD PART NUMBER ALTERNATE FOR PART NUMBER BOM OPTION REF DES COMMENTS: 511S0071 511S0073 ALL TYCO SOCKET 511S0072 511S0073 ALL FOXCONN SOCKET TABLE_ALT_ITEM TABLE_ALT_ITEM Bar Code Labels / EEEE #’s D8 SCHEMATIC / PCB #’S TABLE_5_HEAD PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION TABLE_5_HEAD PART# TABLE_5_ITEM 825-7896 LABEL,MLB,2D EEEE_DHNM CRITICAL EEEE:DHNM 825-7896 LABEL,MLB,2D EEEE_F2FR CRITICAL EEEE:F2FR LABEL,MLB,2D EEEE_F49V CRITICAL EEEE:F49V 825-7896 LABEL,MLB,2D EEEE_F49T CRITICAL EEEE:F49T 825-7896 LABEL,MLB,2D EEEE_F653 CRITICAL EEEE:F653 825-7896 LABEL,MLB,2D EEEE_F654 CRITICAL EEEE:F654 REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION 051-9504 SCH,MLB,D8 SCH1 CRITICAL D8 820-3298 PCBF,MLB,D8 PCB1 CRITICAL D8 TABLE_5_ITEM TABLE_5_ITEM DESCRIPTION TABLE_5_ITEM TABLE_5_ITEM 825-7896 QTY TABLE_5_ITEM TABLE_5_ITEM D8 ALTERNATES TABLE_5_ITEM TABLE_ALT_HEAD PART NUMBER ALTERNATE FOR PART NUMBER BOM OPTION REF DES COMMENTS: 377S0147 377S0126 ALL USB diodes 157S0084 157S0058 ALL Enet Magnetics 341S3644 341S3645 U3990 CIVROM TABLE_ALT_ITEM BOM Groups TABLE_ALT_ITEM TABLE_BOMGROUP_HEAD BOM GROUP C BOM OPTIONS TABLE_ALT_ITEM TABLE_BOMGROUP_ITEM D8_COMMON COMMON,ALTERNATE,D8_COMMON1,D8_PROGPARTS,D8_PRODUCTION D8_COMMON1 XDP,RSMRST:GATE,SPEAKERID,VREF:CPU,TBTHV:P12V,FBA,FBB C TABLE_ALT_ITEM TABLE_BOMGROUP_ITEM 376S0975 376S1081 ALL P/NCH DUAL FET 128S0365 128S0368 ALL 150UF CAPS BLK 138S0803 138S0804 ALL 2.2UF CAPS SOFT 102S0880 102S0879 ALL 0.010 OHM,1%,1206 TABLE_ALT_ITEM TABLE_BOMGROUP_ITEM D8_PROGPARTS SMC:PROG,BOOTROM:PROG,TBTROM:PROG,CIVROM:PROG,CAMROM:PROG,BLCMCU:PROG D8_DEVEL XDP_CONN,LPCPLUS,VREFMRGN:EXT,DEVEL_AUDIO,TEMPSNSDEV D8_PRODUCTION VREFMRGN:N,PRODUCTION TABLE_ALT_ITEM TABLE_BOMGROUP_ITEM TABLE_ALT_ITEM TABLE_BOMGROUP_ITEM CPUs TABLE_5_HEAD PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION VRAM MODULE PARTS TABLE_5_ITEM 337S4355 IVB,SR0TA,PRQ,N1,2.9,65W,4+1,1.1,6M,LGA CPU CRITICAL CPU:4C_2P9GHZ 337S4372 IVB,SR0T9,PRQ,N0,3.1,65W,4+1,1.1,6M,LGA CPU CRITICAL CPU:4C_3P1GHZ TABLE_5_ITEM TABLE_5_HEAD PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION TABLE_5_ITEM 333S0619 IC,SGRAM,GDDR5,32MX32,1.5GHz,G-DIE,HF U8400,U8450,U8500,U8550 CRITICAL FB:BOTH_SAMSUNG 333S0620 IC,GDDR5,32MX32,1.5GHZ,VEGA 44NM,B-DIE U8400,U8450,U8500,U8550 CRITICAL FB:BOTH_HYNIX TABLE_5_ITEM ASICs TABLE_5_HEAD PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION TABLE_5_ITEM 337S4277 IC,PANTHER POINT,C1,SLJC7,PRQ,BD82Z77 U1800 CRITICAL 338S1113 IC,TBT,CR-4C,B1,PRQ,288 FCBGA,12X12MM U3600 CRITICAL 337S4280 IC, GPU, NV GK107-GE-PS-A2 U8000 CRITICAL 343S0616 IC,BCM57766A1,ENET&SD,8X8 U3900 CRITICAL TABLE_5_ITEM TABLE_5_ITEM B GPU:107EGE B TABLE_5_ITEM Programmable Parts TABLE_5_HEAD PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION TABLE_5_ITEM 341S3672 IC,EEPROM,CR,V14.1 (B1),D8 U3690 CRITICAL TBTROM:PROG 335S0865 IC,EEPROM,SERIAL,8KB,MLP8 U3690 CRITICAL TBTROM:BLANK 341S3673 IC,PROGRMD,EFI ROM,V00FC,D7/D8 U5110 CRITICAL BOOTROM:PROG 335S0807 IC,64 MBIT SPI SERIAL FLASH U5110 CRITICAL BOOTROM:BLANK 341S3394 IC,PROGRMD,SMC,A3,V2.2A32,D8 U4900 CRITICAL SMC:PROG 338S1098 IC,SMC,LX4FS1AH5BBCIGA3 U4900 CRITICAL SMC:BLANK 341S3675 IC,CAMERA FLASH,V7228,D7/D8 U4202 CRITICAL CAMROM:PROG 335S0852 IC,FLASH,SPI,1MBIT,3V3 U4202 CRITICAL CAMROM:BLANK 341S3645 IC,ENET 1MBIT, SPI,ROM, V1.13 D8 U3990 CRITICAL CIVROM:PROG 335S0862 IC,SERIAL FLASH,2MBIT, 2.7V, REF F U3990 CRITICAL CIVROM:BLANK 341S3674 IC,BLC,MCU, PRPOGRAMMED, V0204, D8 U9700 CRITICAL BLCMCU:PROG 337S3978 IC,BLC MCU LPC2132FBD64/01, LQFP64 U9700 CRITICAL BLCMCU:BLANK TABLE_5_ITEM TABLE_5_ITEM ALTERNATE:335S0812 TABLE_5_ITEM TABLE_5_ITEM TABLE_5_ITEM TABLE_5_ITEM TABLE_5_ITEM TABLE_5_ITEM ALTERNATE:335S0854 TABLE_5_ITEM TABLE_5_ITEM A TABLE_5_ITEM SYNC_MASTER=D8_MLB PAGE TITLE SYNC_DATE=12/19/2011 BOM Configuration DRAWING NUMBER Apple Inc 051-9504 REVISION 7.0.0 R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED BRANCH PAGE prefsb OF 143 SHEET OF 117 SIZE D A LED GND ISOLATION SWITCH S5 LED LED_GND A DEVELOPMENT KMT221GLHS =PP3V3_S5_LED R503 PM_LED_A_PGOOD_REG_VDDQ_S3 A DEVELOPMENT SOT-363 115 64 48 47 40 28 19 15 IN PM_SLP_S3_L G 2N7002DW-X-G S SOT-363 R507 A PM_LED_A_PGOOD_REG_P1V05 A IN SOT-363 115 69 64 IN PM_PGOOD_REG_CPU_P1V05_S0 G A K PM_LED_A_ALL_SYS_PWRGD G A K LED510 DEVELOPMENT D Q509 2N7002DW-X-G S SOT-363 115 66 65 25 IN PM_PGOOD_REG_CPUCORE_S0 G Q509 2N7002DW-X-G S SOT-363 LED_GND BLC_EN LED =PP3V3_S0_LED 5% 1/16W MF-LF 402 115 A PLACE_SIDE=BOTTOM =PP3V3_S0_LED K 115 107 87 IN 2N7002DW-X-G SOT-363 99 21 IN GPU_GOOD G R514 1K PM_LED_A_VIDEO_ON 5% 1/16W MF-LF 402 A LED514 GREEN-3.6MCD 2.0X1.25MM-SM K GREEN-3.6MCD 2.0X1.25MM-SM 115 SYNC_MASTER=D8_TAVYS PAGE TITLE 2N7002DW-X-G SOT-363 89 NC_Q513_2 NO_TEST=TRUE NC_Q513_1 NO_TEST=TRUE G IN BLC_GOOD G Q513 SOT-363 Q513 Apple Inc 2N7002DW-X-G S SOT-363 051-9504 REVISION 7.0.0 R NOTICE OF PROPRIETARY PROPERTY: LED_GND DRAWING NUMBER DEVELOPMENT 2N7002DW-X-G S SYNC_DATE=06/22/2012 DEBUG LEDS D D DEVELOPMENT PM_LED_K_BLC_GOOD PM_LED_A_BLC_GOOD 115 115 PLACE_SIDE=BOTTOM VIDEO_ON_L NC_Q513_6 NO_TEST=TRUE Q511 S DEVELOPMENT LED513 SILK_PART=4 GREEN-3.6MCD 2.0X1.25MM-SM B PM_LED_K_PGOOD_CPUCORE_S0 3 D GREEN-3.6MCD 2.0X1.25MM-SM 115 1K PM_LED_A_GPU_GOOD DEVELOPMENT K R513 PM_LED_K_GPU_GOOD Q511 S A VIDEO_ON LED LED512 SILK_PART=3 G PM_LED_A_PGOOD_CPUCORE_S0 115 115 D PM_LED_A_CPUAXG_PGOOD LED_GND 5% 1/16W MF-LF 402 GREEN-3.6MCD 2.0X1.25MM-SM 5% 1/16W MF-LF 402 PM_LED_K_ALL_SYS_PWRGD ALL_SYS_PWRGD IN REG_CPUAXG_PGOOD 1K LED511 SILK_PART=2 IN 116 66 R512 PLACE_SIDE=BOTTOM 1K DEVELOPMENT 5% 1/16W MF-LF 402 R510 PM_LED_K_CPUAXG_PGOOD =PP3V3_S0_LED 1K =PP3V3_S0_LED DEVELOPMENT GREEN-3.6MCD 2.0X1.25MM-SM D SOT-363 R511 CPU VCORE LED LED509 GPU_GOOD LED SOT-363 LED_GND DEVELOPMENT K 2N7002DW-X-G 112 65 47 A LED_GND =PP3V3_S4_LED A PM_LED_A_PGOOD_CPU_P1V05_S0 Q507 LED_GND 2N7002DW-X-G S 5% 1/16W MF-LF 402 ALL_SYS_PWRGD LED G 1K DEVELOPMENT S D 2N7002DW-X-G PM_PGOOD_REG_FBVDDQ_S0 PM_LED_K_PGOOD_CPU_P1V05_S0 Q507 IN R509 DEVELOPMENT 115 95 64 =PP3V3_S0_LED DEVELOPMENT GREEN-3.6MCD 2.0X1.25MM-SM PM_LED_K_PGOOD_REG_P1V05 S SOT-363 CPU AXG LED DEVELOPMENT K D 2N7002DW-X-G S Q505 LED_GND C DEVELOPMENT D Q505 LED508 GREEN-3.6MCD 2.0X1.25MM-SM B DEVELOPMENT 5% 1/16W MF-LF 402 GREEN-3.6MCD 2.0X1.25MM-SM PM_LED_K_PGOOD_REG_FBVDDQ_S0 LED507 G G 1K DEVELOPMENT K 2 R508 5% 1/16W MF-LF 402 PM_PGOOD_REG_P1V05_S0 PM_PGOOD_REG_GPUCORE_S0 IN 1K 115 95 64 110 92 64 =PP3V3_S0_LED DEVELOPMENT LED506 K D Q503 PM_LED_A_PGOOD_REG_FBVDDQ_S0 DEVELOPMENT PM_LED_K_PGOOD_REG_GPUCORE_S0 115 CPU 1V05_S0 LED A GREEN-3.6MCD 2.0X1.25MM-SM LED_GND =PP3V3_S0_LED DEVELOPMENT PM_LED_A_PGOOD_REG_GPUCORE_S0 LED505 PCH/GPU 1V05 LED 5% 1/16W MF-LF 402 DEVELOPMENT K DEVELOPMENT D 2N7002DW-X-G 1K 115 A DEVELOPMENT R506 LED_GND PM_LED_A_SLP_S3 PM_LED_K_SLP_S3 =PP3V3_S5_LED 5% 1/16W MF-LF 402 S 1K GREEN-3.6MCD 2.0X1.25MM-SM K GPU FBVDD LED R505 DEVELOPMENT PM_LED_K_PGOOD_REG_VDDQ_S3 G D GREEN-3.6MCD 2.0X1.25MM-SM K DEVELOPMENT LED504 GREEN-3.6MCD 2.0X1.25MM-SM Q503 115 DEVELOPMENT LED502 GREEN-3.6MCD 2.0X1.25MM-SM 5% 1/16W MF-LF 402 PM_PGOOD_REG_VDDQ_S3 =PP3V3_S5_LED 1K LED503 IN 1K 115 72 64 A GPU VCORE LED DEVELOPMENT R504 DEVELOPMENT PM_LED_A_S4 115 LED_GND SLP_S3 LED =PP3V3_S5_LED DEVELOPMENT D PM_LED_A_S5 APN: 705S0137 MEM 1V5_S3 LED C 5% 1/16W MF-LF 402 LED501 SILK_PART=1 K K 1K PLACE_SIDE=BOTTOM SM A R502 1K SW500 DEVELOPMENT R501 D 5% 1/16W MF-LF 402 =PP3V3_S4_LED 5% 1/16W MF-LF 402 S4 (SLEEP) LED =PP3V3_S5_LED MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.2 MM THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED BRANCH PAGE prefsb OF 143 SHEET OF 117 SIZE D A SILK_PART=PWRSIG MLB to AC-DC Supplemental Signal Connector OUT PWR_BTN 116 48 PLACE_NEAR=R606.1:3MM C600 0.1UF 1K 95 92 72 70 69 66 116 MAKE_BASE=TRUE R603 117 53 402 117 53 OUT OUT 10K SMC_ACDC_ID_R TSNS_ACDC_N TSNS_ACDC_P 116 6.8V-100PF 5% 1/16W MF-LF 402 PLACE_NEAR=J601.3:30MM PLACE_NEAR=J601.3:3MM R604 D C605 0.1UF BURSTMODE_EN_L PLACE_NEAR=R600.1:3MM FILTER ADDED TO BURSTMODE_EN_L TO PASS SURGE D600 PLACE_NEAR=J601.7:3MM IN PP12V_S0 PWR_BTN_R PLACE_NEAR=J601.1:3MM 5% 1/16W MF-LF 402 10% 16V X7R-CERM 0402 71 48 112 106 =PP3V3_S0_VRD PLACE_NEAR=J601.1:3MM R600 1K 10% 16V X7R-CERM 0402 116 SMC_ACDC_ID_R 5% 1/16W MF-LF 402 D601 518S0863 D602 SMC_ACDC_ID 5% 1/16W MF-LF 402 =PP12V_S0_PWRCTL 54 51 PLACE_NEAR=J601.7:3MM PP12V_G3H_ACDC 10 11 12 106 PP12V_G3H_ACDC EMC J600.5:10MM J600.4:10MM C601 10UF C602 10% 5% 25V NP0-C0G PP12V_S0_HDD MAKE_BASE=TRUE 106 C603 5% 25V NP0-C0G 106 402 106 G3 Rails PP3V3_G3 MAKE_BASE=TRUE PP3V3_G3_RTC =PP3V3_G3_PCH_RTC =PP3V3_G3_PCH 26 115 106 22 106 106 MAKE_BASE=TRUE PP12V_G3H MAKE_BASE=TRUE PP3V42_G3H MAKE_BASE=TRUE B PP5V_S4 MAKE_BASE=TRUE 18 19 106 On with AC/DC plugged in PP12V_ACDC PP12V_S0_FBVDDQ MAKE_BASE=TRUE PP12V_S0_CPU_P1V05 MAKE_BASE=TRUE PP12V_S0_VCCSA MAKE_BASE=TRUE PP12V_S0_P1V05 MAKE_BASE=TRUE PP5V_S0 MAKE_BASE=TRUE Enabled when system has AC and is in run or sleep G3H Rails 106 MAKE_BASE=TRUE S4 Rails Always on: Keeps the PCH RTC alive 106 PP12V_S0_BLC 1000PF 402 805 106 EMC J600.5:10MM 1000PF 25V X5R C PP12V_G3H_ACDC =PP12V_G3H_PWR PP3V3_S4 MAKE_BASE=TRUE 51 PP12V_G3H_SNS =PP12V_G3H_P3V42 =PP12V_G3H_FET_P12V_S0 =PP12V_G3H_FET_P12V_S5 51 73 74 74 PP3V42_G3H_REG =PP3V3_G3H_BT =PP3V3_G3H_RTC_D =PP3V3_G3H_SMC =PP3V3_G3H_SMC_USBMUX =PPVIN_G3H_SMCVREF =PP3V3_G3H_LPCPLUS 73 35 26 47 48 50 45 48 49 PP5V_S4_REG =PP5V_S4_REG_VDDQ_S3 =PP5V_S4_FET_P5V_S0 =PP5V_S4_MEMRESET =PP5V_S4_USB =PP5V_S4_CAMERA PP3V3_S4_FET =PP3V3_S4_ALS =PP3V3_S4_AP_PWR =PP3V3_S4_CAMERA =PP3V3_S4_ENET =PP3V3_S4_LED =PP3V3_S4_MEMRESET =PP3V3_S4_PM =PP3V3_S4_PWRCTL =PP3V3_S4_SENSE =PP3V3_S4_SMBUS =PP3V3_S4_SMBUS_SMC =PP3V3_S4_SMC =PP3V3_S4_TBT =PP3V3_S4_TBTAPWRSW =PP3V3_S4_TBTBPWRSW =PP3V3_S4_USB_HUB =PP3V3_S4_VREFMRGN =PP3V3_S4_AUDIO_DIG 71 72 74 28 45 46 On when in S5 106 106 PP12V_S5 MAKE_BASE=TRUE PP5V_S5 MAKE_BASE=TRUE PP3V3_S5 MAKE_BASE=TRUE PP12V_S5_FET =PP12V_S5_REG_P3V3P5V_S5 =PP12V_S5_REG_VDDQ_S3 =PP12V_S5_PWRCTL =PPHV_SW_TBTAPWRSW =PPHV_SW_TBTBPWRSW =PP12V_S5_SNS 106 74 67 106 55 PP3V3_S4_AP MAKE_BASE=TRUE PP3V3_S4_ENET 106 MAKE_BASE=TRUE 51 28 106 28 PP3V3_S4_AP_SNS =PP3V3_S4_AP PP3V3_S4_ENET_FET =PP3V3_S4_ENET_FET =PP3V3_S4_ENET_SYSCLK =PP3V3_S4_ENET_CLK PP5V_S0_HDD MAKE_BASE=TRUE 71 74 Enabled when system is in run or sleep 50 106 50 PP3V3_S0 MAKE_BASE=TRUE 48 36 37 38 86 88 48 86 48 88 27 PP1V5_S0_CPU_MEM PP1V5_S0_CPU_MEM_SNS =PP1V5_S0_CPU_MEM MAKE_BASE=TRUE 55 15 35 40 39 40 26 26 19 24 26 PPVDDQ_S3 MAKE_BASE=TRUE THIS IS 1.5V RAIL 22 24 PPVDDQ_S3_REG =PPVDDQ_S3_DDR_PWR =PPVDDQ_S3_FET_VDDQ_S0 =PPVDDQ_S3_LDO_DDRVTT 72 51 74 72 22 24 22 24 22 24 106 49 PPVDDQ_S3_DDR MAKE_BASE=TRUE THIS IS 1.5V RAIL 25 45 46 PPVDDQ_S3_DDR_SNS =PPVDDQ_S3_DDR_VREF =PPVDDQ_S3_MEM_A =PPVDDQ_S3_MEM_B =PPVDDQ_S3_MEMRESET 51 PPDDRVTT_S3 MAKE_BASE=TRUE PPDDRVTT_S3_LDO =PPDDRVTT_S3_VREFCA PP12V_S0_BLC_FET =PP12V_S0_BLC 74 D MAKE_BASE=TRUE PPGPUCORE_S0_REG =PPVCORE_S0_GPU 93 94 51 78 11 13 16 PPFBVDDQ_S0_GPU MAKE_BASE=TRUE 72 PP1V5R1V35_S0_GPU_REG =PP1V35_S0_GPU_FBVDDQ 95 110 78 28 29 30 31 32 91 PP12V_S0_FBVDDQ_SNS =PP12V_S0_REG_FBVDDQ 106 51 PPDDRVREF_DQ_MEM_A_S3 MAKE_BASE=TRUE 95 PP12V_S0_REG_CPU_P1V05_SNS =PP12V_S0_REG_CPU_P1V05 PP12V_S0_REG_CPU_VCCSA_SNS =PP12V_S0_REG_VCCSA PP12V_S0_REG_P1V05_SNS =PP12V_S0_REG_P1V05 PP5V_S0_FET =PP5V_S0_AUDIO =PP5V_S0_BLC =PP5V_S0_HDD_PWR =PP5V_S0_ISENSE =PP5V_S0_LPCPLUS =PP5V_S0_PCH =PP5V_S0_REG_CPUCORE =PP5V_S0_REG_CPU_P1V05 =PP5V_S0_REG_FBVDDQ =PP5V_S0_REG_P1V05 =PP5V_S0_REG_P1V8 =PP5V_S0_REG_VCCSA =PP5V_S0_VRD PPDDRVREF_DQ_MEM_A =PPDDRVREF_DQ_MEM_A 34 104 PP1V05_S0_PCH PP1V05_S0_PCH_SNS =PP1V05_S0_PCH =PP1V05_S0_PCH_VCCCLKDMI =PP1V05_S0_PCH_VCCIO_DMI =PP1V05_S0_PCH_VCCIO_PCIE =PP1V05_S0_PCH_VCCIO_SATA =PP1V05_S0_PCH_VCCIO_USB =PP1V05_S0_PCH_VCC_ADPLL =PP1V05_S0_PCH_VCC_ASW =PP1V05_S0_PCH_VCC_CORE =PP1V05_S0_PCH_VCC_DIFFCLK =PP1V05_S0_PCH_VCC_DMI =PP1V05_S0_PCH_VCC_SSC =PP1V05_S0_PCH_V_PROC_IO MAKE_BASE=TRUE 29 30 55 69 106 PPDDRVREF_CA_MEM_A_S3 MAKE_BASE=TRUE 55 PPDDRVREF_CA_MEM_A =PPDDRVREF_CA_MEM_A 34 29 30 70 55 106 PPDDRVREF_DQ_MEM_B_S3 MAKE_BASE=TRUE 95 PPDDRVREF_DQ_MEM_B =PPDDRVREF_DQ_MEM_B 34 31 32 74 56 63 106 PPDDRVREF_CA_MEM_B_S3 MAKE_BASE=TRUE 91 PPDDRVREF_CA_MEM_B =PPDDRVREF_CA_MEM_B 34 31 32 51 18 22 24 22 24 18 19 22 24 18 22 24 22 24 17 22 24 22 24 22 24 22 24 22 24 C 22 24 51 51 104 PP1V05_S0_CPU MAKE_BASE=TRUE 49 24 66 PP1V05_S0_CPU_REG =PPVCCIO_S0_CPU =PPVCCIO_S0_SMC =PPVCCIO_S0_XDP 69 10 11 13 16 28 66 48 25 69 95 104 PP1V05_S0 MAKE_BASE=TRUE 95 72 70 72 92 PP5V_S0_HDD_SNS =PP5V_S0_HDD 51 105 PPVCORE_S0_CPU 105 PPVAXG_S0 104 PPVCCSA_S0 MAKE_BASE=TRUE 52 PP3V3_S0_FET =PP3V3_S0_GPU_IFPX_PLLVDD =PP3V3_S0_GPU_MISC =PP3V3_S0_GPU_VDD33 =PP3V3_S0_AUDIO =PP3V3_S0_AUDIO_DIG =PP3V3_S0_BLC MAKE_BASE=TRUE PPCPUCORE_S0_REG =PPVCORE_S0_CPU PPCPUAXG_S0_REG =PPVAXG_S0_CPU 95 51 38 78 78 78 78 67 68 13 16 51 66 17 68 13 17 51 66 74 78 MAKE_BASE=TRUE 78 PPVCCSA_S0_REG =PPVCCSA_S0_CPU 70 13 16 78 42 56 58 59 62 Thunderbolt Rails (S0) 60 Enabled when Thunderbolt cable is plugged in 89 =PP3V3_TBTLC_FET 38 39 =PP3V3_TBT_PCH_GPIO 15 54 =PP3V3_TBTLC_RTR 15 36 37 38 50 78 92 =PP3V3_TBT_CLK 26 106 85 87 PP3V3_TBTLC MAKE_BASE=TRUE B 84 15 44 29 30 31 32 38 104 38 18 21 24 PP1V05_TBTLC =PP1V05_TBTLC_FET MAKE_BASE=TRUE =PP1V05_TBTLC_RTR 15 19 20 38 38 37 26 15 22 24 17 22 24 22 24 104 PP1V05_TBTCIO =PP1V05_TBTCIO_FET 38 MAKE_BASE=TRUE 22 24 =PP1V05_TBTCIO_RTR 37 28 74 26 41 51 52 53 55 50 50 50 SYNC_MASTER=D8_DOUG 48 51 82 SYNC_DATE=06/20/2012 PAGE TITLE Power Connectors/Aliases 38 66 69 70 72 92 95 DRAWING NUMBER 51 Apple Inc 051-9504 REVISION 7.0.0 R 31 32 28 PP3V3_S0_SSD MAKE_BASE=TRUE NOTICE OF PROPRIETARY PROPERTY: PP3V3_S0_SSD_SNS =PP3V3_S0_SSD 51 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED 44 72 34 THIS IS 1.5V RAIL PPVCORE_S0_GPU 51 29 30 106 106 PPDDRVTT_S0_LDO =PPDDRVTT_S0_CLAMP =PPDDRVTT_S0_MEM_A =PPDDRVTT_S0_MEM_B MAKE_BASE=TRUE 52 34 51 41 PPDDRVTT_S0 51 =PP3V3_S0_DP =PP3V3_S0_ENET =PP3V3_S0_FAN =PP3V3_S0_GPU =PP3V3_S0_INTDPMUX =PP3V3_S0_LED =PP3V3_S0_LED_SATA =PP3V3_S0_MEM_A_SPD =PP3V3_S0_MEM_B_SPD =PP3V3_S0_P3V3TBTFET =PP3V3_S0_PCH =PP3V3_S0_PCH_GPIO =PP3V3_S0_PCH_PM =PP3V3_S0_PCH_STRAPS =PP3V3_S0_PCH_VCC =PP3V3_S0_PCH_VCC_ADAC =PP3V3_S0_PCH_VCC_GPIO =PP3V3_S0_PCH_VCC_HVCMOS =PP3V3_S0_PCH_VCC_PCI =PP3V3_S0_PWRCTL =PP3V3_S0_RSTBUF =PP3V3_S0_SDCARD =PP3V3_S0_SENSE =PP3V3_S0_SMBUS =PP3V3_S0_SMBUS_SMC =PP3V3_S0_SMBUS_TCON =PP3V3_S0_SMC =PP3V3_S0_TBTPWRCTL =PP3V3_S0_VRD =PP3V3_S0_SSD_PWR 60 48 71 Enabled when system is in run 34 74 64 65 GPU Rails (S0) 110 51 24 S3 Rails PP12V_S0_HDD_SNS =PP12V_S0_HDD 65 72 74 71 15 56 84 71 106 A 74 51 65 =PP1V05_S0_GPU_PEX_IOVDD 86 =PP3V3_S5_PCH =PP3V3_S5_PCH_STRAPS =PP3V3_S5_PCH_VCCSUS_HDA =PP3V3_S5_PCH_VCCSUS_USB =PP3V3_S5_PCH_VCC_DSW =PP3V3_S5_PCH_VCC_SPI =PP3V3_S5_PWRCTL =PP3V3_S5_ROM =PP3V3_S5_VRD =PP3V3_S5_XDP =PP3V3_S5_SMC_USBMUX =PP3V3_S5_SENSE =PP3V3_S5_SDCARD PP1V5_S0_FET =PP1V5_S0_AUD_DIG =PP1V5_S0_CPU_MEM_PWR =PP1V5_S0_DP MAKE_BASE=TRUE 55 55 64 65 74 PP3V3_S5_REG =PP3V3_S5_FET_P3V3_S0 =PP3V3_S5_FET_P3V3_S4 =PP3V3_S5_SMC =PP3V3_S5_LED PP1V5_S0 55 40 42 72 PP5V_S5_LDO =PP5V_S5_PWRCTL =PP5V_S5_PCH 26 87 42 43 74 71 88 24 92 PP1V05_S0_REG =PP1V05_S0_PCH_PWR =PP1V05_S0_P1V05TBTFET =PP1V05_S0_GPU_IFPCD_IOVDD =PP1V05_S0_GPU_IFPEF_IOVDD =PP1V05_S0_GPU_PEX_PLLVDD 42 S5 Rails 106 MAKE_BASE=TRUE 22 24 106 106 518-0389 GND 19 PLACE_NEAR=R604.2:3MM MLB to AC-DC Connector Ground/Common 13 16 51 106 CRITICAL J600 72 =PP1V8_S0_CPU_PLL =PP1V8_S0_PCH =PP1V8_S0_PCH_VCC_DFTERM =PP1V8_S0_PCH_VCC_VRM =PP1V8_S0_PCH_CLK 58 59 106 M-RT-TH-1 PP1V8_S0_REG MAKE_BASE=TRUE 74 20% 106 43045-1201 PP1V8_S0 0402 PLACE_NEAR=J601.1:4MM C604 PP12V_S0_FET =PP12V_S0_AUDIO_SPKRAMP =PP12V_S0_FAN =PP12V_S0_FBVDDQ_PWR =PP12V_S0_REG_GPUCORE =PP12V_S0_HDD_PWR =PP12V_S0_LCD =PP12V_S0_REG_CPUCORE =PP12V_S0_REG_CPU_P1V05_PWR =PP12V_S0_REG_CPU_VCCSA_PWR =PP12V_S0_REG_P1V05_PWR 16V X7R-CERM 402 402 48 116 0.01UF 6.8V-100PF 6.8V-100PF RDAR://11059712 1K BURSTMODE_EN_R_L 106 Enabled when system is in run M-RT-SM S0 Rails J601 504050-0791 R606 BRANCH PAGE prefsb OF 143 SHEET OF 117 SIZE D A OMIT OMIT OMIT 8P5R5-NSP D ZH0701 998-4938 (PLATED HOLES, 1.9MM INNER DIAMETER, 4.3MM PAD) 4MM PLATED HOLES (998-4158) ZH0700 WIRELESS CARD MTG HOLES CPU Heatsink 8P5R5-NSP ZH0702 8P5R5-NSP OMIT ZH0703 8P5R5-NSP CRITICAL CRITICAL ZH0721 5P5R1P9-4P3B-NSP ZH0722 D 5P5R1P9-4P3B-NSP 1 GPU HEATSINK MOUNTING FEATURES (998-5013 PLATED HOLE, 3.2MM DIA, 6MM PAD TOP/BOT) HEATPIPE MTG HOLES CRITICAL ZH0720 6P0R3P2-NSP CRITICAL CRITICAL ZH0724 ZH0723 6P0R3P2-NSP 6P0R3P2-NSP ZH0725 6P0R3P2-NSP 1 998-4640 (PLATED HOLES, 10MM DIA, 12MM PAD) CRITICAL ZH0726 10R12 C C Rear Cover 998-5014 (PLATED HOLES, 4MM DRILL, 8.5MM TOP, 8MM BOT) CRITICAL ZH0713 8P5R4P0-8P0B-NSP CRITICAL ZH0714 CRITICAL 8P5R4P0-8P0B-NSP CRITICAL ZH0717 ZH0716 8P5R4P0-8P0B-NSP 8P5R4P0-8P0B-NSP 1 Rear Cover 860-1487 (PCB STANDOFF) B B CRITICAL CRITICAL ZH0718 ZH0715 STDOFF-7.14OD16.45H-TH-1.5-5.2 STDOFF-7.14OD16.45H-TH-1.5-5.2 1 SSD STANDOFF APN: 860-1461 CRITICAL NUT0713 STDOFF-4.5OD2.2ID-5.6H-SM A SYNC_MASTER=D8_MLB PAGE TITLE SYNC_DATE=03/25/2012 Holes/PD parts DRAWING NUMBER Apple Inc 051-9504 REVISION 7.0.0 R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED BRANCH PAGE prefsb OF 143 SHEET OF 117 SIZE D A PCH PCIe CPU Reserved 10 TP_CPU_RSVD NC_CPU_RSVD 10 TP_CPU_RSVD NC_CPU_RSVD 10 MAKE_BASE=TRUE CPU_CFG MAKE_BASE=TRUE NO_TEST=TRUE TP_CPU_CFG 12 NC_MEM_A_DQ_CB 12 TP_MEM_A_DQS_N NC_MEM_A_DQSNX MAKE_BASE=TRUE MAKE_BASE=TRUE 12 TP_MEM_A_DQS_P TP_PCIE1_D2RP NC_PCIE1_D2RPX 18 TP_PCIE1_R2D_CN NC_PCIE1_R2D_CNX 18 TP_PCIE1_R2D_CP NC_PCIE1_R2D_CPX 18 TP_PCIE2_D2RN NC_PCIE2_D2RNX 18 TP_PCIE2_D2RP NC_PCIE2_D2RPX 18 TP_PCIE2_R2D_CN NC_PCIE2_R2D_CNX 18 TP_PCIE2_R2D_CP NC_PCIE2_R2D_PNX MAKE_BASE=TRUE TP_MEM_B_DQ_CB 12 TP_MEM_B_DQS_N NO_TEST=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE NO_TEST=TRUE 18 DMI_MIDBUS_CLK100M_N 18 DMI_MIDBUS_CLK100M_P NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE 19 NC_CRT_IG_RED 19 TP_CRT_IG_GREEN NC_CRT_IG_GREEN 19 TP_CRT_IG_BLUE 19 TP_CRT_IG_HSYNC 19 TP_CRT_IG_VSYNC 19 TP_CRT_IG_DDC_CLK 19 TP_CRT_IG_DDC_DATA MAKE_BASE=TRUE MAKE_BASE=TRUE NO_TEST=TRUE NC_DMI_MIDBUS_CLK100NX NO_TEST=TRUE NC_DMI_MIDBUS_CLK100PX MAKE_BASE=TRUE NO_TEST=TRUE TP_PCIE_CLK100M_PE0N 18 TP_PCIE_CLK100M_PE0P NC_PCIE_CLK100M_PE0NX MAKE_BASE=TRUE MAKE_BASE=TRUE 18 TP_PCIE_CLK100M_PE4N MAKE_BASE=TRUE 18 TP_PCIE_CLK100M_PE4P MAKE_BASE=TRUE MAKE_BASE=TRUE NC_CRT_IG_DDC_DATA MAKE_BASE=TRUE NC_DP_IG_B_MLNX DP_IG_B_MLP NC_DP_IG_B_MLPX 19 DP_IG_B_AUX_N MAKE_BASE=TRUE MAKE_BASE=TRUE DP_IG_B_AUX_P NC_PCIE_CLK100M_PE5NX 18 TP_PCIE_CLK100M_PE5P NC_PCIE_CLK100M_PE5PX MAKE_BASE=TRUE TP_PCIE_CLK100M_PE6N NC_PCIE_CLK100M_PE6NX 21 TP_PCIE_CLK100M_PE6P NC_PCIE_CLK100M_PE6PX MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE 21 TP_PCIE_CLK100M_PE7N NC_PCIE_CLK100M_PE7NX 21 TP_PCIE_CLK100M_PE7P NC_PCIE_CLK100M_PE7PX MAKE_BASE=TRUE NO_TEST=TRUE NC_PE_TNX MAKE_BASE=TRUE TP_PE_RX_N 10 NO_TEST=TRUE MAKE_BASE=TRUE 10 NO_TEST=TRUE NC_PE_TPX MAKE_BASE=TRUE NO_TEST=TRUE NC_PE_RNX MAKE_BASE=TRUE TP_PE_RX_P NO_TEST=TRUE NC_PE_RPX MAKE_BASE=TRUE NO_TEST=TRUE PCH USB 20 USB_PCH_4_N USB_PCH_4_P USB_PCH_5_N 20 USB_PCH_5_P 20 20 20 20 B NO_TEST=TRUE NC_USB_PCH_5NX MAKE_BASE=TRUE NO_TEST=TRUE USB_PCH_11_P NO_TEST=TRUE NO_TEST=TRUE 20 USB_PCH_12_N NC_USB_PCH_12NX 20 USB_PCH_12_P NC_USB_PCH_12PX MAKE_BASE=TRUE MAKE_BASE=TRUE 20 USB_PCH_13_P DP_IG_C_MLN 18 TP_SATA_D_R2D_CP 18 TP_SATA_D_D2RN 18 TP_SATA_D_D2RP MAKE_BASE=TRUE NC_SATA_D_R2D_CPX MAKE_BASE=TRUE 19 DP_IG_C_AUX_N 19 DP_IG_C_AUX_P 19 DP_IG_C_HPD 19 DP_IG_C_CTRL_CLK NC_DP_IG_C_CTRL_CLK 19 DP_IG_C_CTRL_DATA NC_DP_IG_C_CTRL_DATA NO_TEST=TRUE NC_DP_IG_C_AUXNX MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE NC_SATA_D_D2RPX MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE NO_TEST=TRUE TP_SATA_E_R2D_CN NC_SATA_E_R2D_CNX MAKE_BASE=TRUE TP_SATA_E_R2D_CP TP_SATA_E_D2RN 18 TP_SATA_E_D2RP 19 DP_IG_D_AUXN NC_DP_IG_D_AUXNX 19 DP_IG_D_AUXP 18 TP_SATA_F_R2D_CN 19 DP_IG_D_HPD NC_DP_IG_D_HPD 19 DP_IG_D_CTRL_CLK NC_DP_IG_D_CTRL_CLK 19 DP_IG_D_CTRL_DATA MAKE_BASE=TRUE MAKE_BASE=TRUE TP_SATA_F_R2D_CP 18 TP_SATA_F_D2RN 18 TP_SATA_F_D2RP NC_SATA_F_D2RNX MAKE_BASE=TRUE NC_SATA_F_D2RPX MAKE_BASE=TRUE NC_PCH_RESERVE_0 TP_PCH_RESERVE_1 NC_PCH_RESERVE_1 19 TP_PCH_RESERVE_2 19 TP_PCH_RESERVE_3 MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE TP_SDVO_TVCLKINP NC_SDVO_TVCLKINPX NC_PCH_RESERVE_4 NC_PCH_RESERVE_5 MAKE_BASE=TRUE MAKE_BASE=TRUE TP_PCH_RESERVE_6 19 TP_PCH_RESERVE_7 NC_SDVO_STALLPX 19 TP_SDVO_INTN NC_SDVO_INTNX 19 TP_PCH_RESERVE_8 TP_PCH_RESERVE_9 NC_PCH_CLKOUT_DPPX 18 PCH_CLK25M_XTALOUT NC_PCH_CLK25M_XTALOUT MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE NC_SDVO_INTPX 18 TP_PCH_GPIO65_CLKOUTFLEX1 NC_PCH_GPIO65_CLKOUTFLEX1 19 TP_PCH_RESERVE_11 NC_PCH_RESERVE_11 19 TP_PCH_RESERVE_12 NC_PCH_RESERVE_12 19 TP_PCH_RESERVE_13 19 TP_PCH_RESERVE_14 MAKE_BASE=TRUE MAKE_BASE=TRUE TP_PCH_TP12 TP_PCH_TP13 TP_PCH_TP14 TP_PCH_TP15 18 TP_PCH_L_BKLTCTL NC_PCH_L_BKLTCTL 18 TP_PCH_L_BKLTEN NC_PCH_L_BKLTEN 18 TP_PCH_L_VDD_EN MAKE_BASE=TRUE TP_PCH_TP19 21 TP_PCH_TP20 NO_TEST=TRUE NC_PCH_TP17 MAKE_BASE=TRUE 21 NO_TEST=TRUE NC_PCH_TP16 TP_PCH_TP17 TP_PCH_TP18 NO_TEST=TRUE NO_TEST=TRUE NC_PCH_TP18 MAKE_BASE=TRUE NO_TEST=TRUE NC_PCH_TP19 MAKE_BASE=TRUE NO_TEST=TRUE NC_PCH_TP20 MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE NO_TEST=TRUE 20 TP_PCI_C_BE_L NC_PCI_C_BE_L 20 TP_PCI_PAR NC_PCI_PAR MAKE_BASE=TRUE MAKE_BASE=TRUE 20 TP_PCI_RESET_L 20 TP_PCH_PCI_GNT0_L TP_PCH_INIT3V3_L NO_TEST=TRUE NO_TEST=TRUE NC_PCH_INIT3V3_L MAKE_BASE=TRUE 18 NO_TEST=TRUE NC_PCI_GNT0_L MAKE_BASE=TRUE 19 NO_TEST=TRUE NC_PCI_RESET_L MAKE_BASE=TRUE TP_LPC_DREQ0_L NO_TEST=TRUE NC_LPC_DREQ0_L MAKE_BASE=TRUE NO_TEST=TRUE PCH Miscellaneous NO_TEST=TRUE NC_PCH_RESERVE_14 MAKE_BASE=TRUE 19 TP_PCH_RESERVE_17 19 TP_PCH_RESERVE_18 19 TP_PCH_RESERVE_19 19 TP_PCH_RESERVE_20 19 TP_PCH_RESERVE_21 NC_PCH_RESERVE_21 19 TP_PCH_RESERVE_22 NC_PCH_RESERVE_22 MAKE_BASE=TRUE MAKE_BASE=TRUE NO_TEST=TRUE NO_TEST=TRUE NC_PCH_RESERVE_19 MAKE_BASE=TRUE NO_TEST=TRUE NC_PCH_RESERVE_20 MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE 19 TP_PCH_RESERVE_23 NC_PCH_RESERVE_23 19 TP_PCH_RESERVE_24 NC_PCH_RESERVE_24 MAKE_BASE=TRUE MAKE_BASE=TRUE NO_TEST=TRUE NO_TEST=TRUE 19 TP_PCH_RESERVE_25 NC_PCH_RESERVE_25 19 TP_PCH_RESERVE_26 NC_PCH_RESERVE_26 19 TP_PCH_RESERVE_27 NC_PCH_RESERVE_27 MAKE_BASE=TRUE MAKE_BASE=TRUE NC_HDA_SDIN1 TP_HDA_SDIN2 NC_HDA_SDIN2 18 TP_HDA_SDIN3 21 TP_PCH_PWM0 21 TP_PCH_PWM1 21 TP_PCH_PWM2 21 TP_PCH_PWM3 21 TP_PCH_SST NC_PCH_SST 18 TP_PCH_CL_CLK1 NC_PCH_CL_CLK1 18 TP_PCH_CL_DATA1 NC_PCH_CL_DATA1 18 TP_PCH_CL_RST1 20 TP_PCI_CLK33M_OUT2 NC_PCI_CLK33M_OUT2 20 TP_PCI_CLK33M_OUT3 NC_PCI_CLK33M_OUT3 MAKE_BASE=TRUE MAKE_BASE=TRUE NO_TEST=TRUE NO_TEST=TRUE NC_HDA_SDIN3 MAKE_BASE=TRUE NO_TEST=TRUE NC_PCH_RESERVE_18 MAKE_BASE=TRUE TP_HDA_SDIN1 NO_TEST=TRUE NC_PCH_RESERVE_17 MAKE_BASE=TRUE 18 18 NO_TEST=TRUE NC_PCH_RESERVE_16 TP_PCH_RESERVE_28 MAKE_BASE=TRUE NO_TEST=TRUE TP_PCH_RESERVE_16 19 NC_PCI_AD NC_PCH_RESERVE_13 19 NO_TEST=TRUE C TP_PCI_AD NO_TEST=TRUE NC_PCH_RESERVE_15 NO_TEST=TRUE PCH PCI 20 NO_TEST=TRUE TP_PCH_RESERVE_15 NO_TEST=TRUE NC_PCH_L_VDD_EN TP_PCH_TP16 21 NO_TEST=TRUE NC_PCH_TP15 MAKE_BASE=TRUE 21 NO_TEST=TRUE NC_PCH_TP14 MAKE_BASE=TRUE 21 NO_TEST=TRUE NC_PCH_TP13 MAKE_BASE=TRUE 21 NO_TEST=TRUE NC_PCH_TP12 MAKE_BASE=TRUE 21 NO_TEST=TRUE NC_PCH_TP11 MAKE_BASE=TRUE 21 NO_TEST=TRUE NC_PCH_RESERVE_10 19 NO_TEST=TRUE NC_PCH_PWM0 MAKE_BASE=TRUE NO_TEST=TRUE NC_PCH_PWM1 MAKE_BASE=TRUE NO_TEST=TRUE NC_PCH_PWM2 MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE NC_PCH_CL_RST1 MAKE_BASE=TRUE NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE PCH and CPU FDI NO_TEST=TRUE TP_PCH_GPIO66_CLKOUTFLEX2 NC_PCH_GPIO66_CLKOUTFLEX2 18 TP_PCH_GPIO67_CLKOUTFLEX3 NC_PCH_GPIO67_CLKOUTFLEX3 NO_TEST=TRUE 10 TP_CPU_FDI_TX_N NC_CPU_FDI_TNX 10 TP_CPU_FDI_TX_P NC_CPU_FDI_TPX MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE 19 PCH_FDI_RX_N 19 PCH_FDI_RX_P NO_TEST=TRUE NO_TEST=TRUE NC_PCH_FDI_RPX MAKE_BASE=TRUE A NO_TEST=TRUE NC_PCH_FDI_RNX MAKE_BASE=TRUE NO_TEST=TRUE 10 TP_CPU_FDI_FSYNC NC_CPU_FDI_FSYNC 10 TP_CPU_FDI_LSYNC NC_CPU_FDI_LSYNC 10 TP_CPU_FDI_INT NC_CPU_FDI_INT MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE NO_TEST=TRUE SYNC_MASTER=D8_MLB_ULTIMATE SYNC_DATE=04/02/2012 PAGE TITLE Unused Signal Aliases NO_TEST=TRUE DRAWING NUMBER NO_TEST=TRUE Apple Inc 051-9504 REVISION 7.0.0 R B NO_TEST=TRUE NC_PCH_PWM3 NC_PCH_RESERVE_28 MAKE_BASE=TRUE NO_TEST=TRUE 18 MAKE_BASE=TRUE TP_PCH_TP11 MAKE_BASE=TRUE NO_TEST=TRUE NC_PCH_GPIO64_CLKOUTFLEX0 MAKE_BASE=TRUE 21 NO_TEST=TRUE NC_PCH_TP8 NO_TEST=TRUE TP_PCH_RESERVE_10 NO_TEST=TRUE NO_TEST=TRUE TP_PCH_GPIO64_CLKOUTFLEX0 MAKE_BASE=TRUE NC_PCH_TP10 MAKE_BASE=TRUE NO_TEST=TRUE 19 NO_TEST=TRUE NO_TEST=TRUE 18 MAKE_BASE=TRUE NC_PCH_TP9 TP_PCH_TP10 D NO_TEST=TRUE NC_PCH_TP7 NO_TEST=TRUE NC_PCH_RESERVE_9 MAKE_BASE=TRUE NC_PCH_CLKOUT_DPNX TP_PCH_TP9 21 MAKE_BASE=TRUE NO_TEST=TRUE NC_PCH_RESERVE_8 MAKE_BASE=TRUE NO_TEST=TRUE PCH Clocks TP_PCH_CLKOUT_DPP 21 NO_TEST=TRUE NC_PCH_TP6 NO_TEST=TRUE NC_PCH_RESERVE_7 MAKE_BASE=TRUE NO_TEST=TRUE TP_PCH_CLKOUT_DPN TP_PCH_TP8 MAKE_BASE=TRUE NO_TEST=TRUE NC_PCH_RESERVE_6 MAKE_BASE=TRUE NO_TEST=TRUE TP_SDVO_STALLP MAKE_BASE=TRUE 21 NO_TEST=TRUE NC_PCH_TP5 NO_TEST=TRUE TP_PCH_RESERVE_5 NO_TEST=TRUE 19 MAKE_BASE=TRUE TP_PCH_TP7 MAKE_BASE=TRUE NO_TEST=TRUE NC_PCH_RESERVE_3 TP_PCH_RESERVE_4 NO_TEST=TRUE NC_SDVO_STALLNX MAKE_BASE=TRUE 21 NO_TEST=TRUE 19 NO_TEST=TRUE 19 MAKE_BASE=TRUE TP_PCH_TP6 NO_TEST=TRUE NC_PCH_TP4 NO_TEST=TRUE 19 NO_TEST=TRUE NC_SDVO_TVCLKINNX MAKE_BASE=TRUE 21 NC_PCH_RESERVE_2 MAKE_BASE=TRUE NO_TEST=TRUE 18 NO_TEST=TRUE TP_PCH_RESERVE_0 NO_TEST=TRUE NO_TEST=TRUE 18 NO_TEST=TRUE 19 19 TP_SDVO_TVCLKINN MAKE_BASE=TRUE TP_PCH_TP5 MAKE_BASE=TRUE NO_TEST=TRUE 19 NO_TEST=TRUE 19 MAKE_BASE=TRUE 21 NO_TEST=TRUE NC_PCH_TP3 NO_TEST=TRUE NC_SATA_F_R2D_CPX MAKE_BASE=TRUE MAKE_BASE=TRUE TP_PCH_TP4 NO_TEST=TRUE PCH Reserved NO_TEST=TRUE NC_DP_IG_D_CTRL_DATA MAKE_BASE=TRUE 21 MAKE_BASE=TRUE NO_TEST=TRUE NC_SATA_F_R2D_CNX MAKE_BASE=TRUE NO_TEST=TRUE NC_DP_IG_D_AUXPX MAKE_BASE=TRUE TP_PCH_TP3 MAKE_BASE=TRUE MAKE_BASE=TRUE NO_TEST=TRUE NC_DP_IG_D_MLPX MAKE_BASE=TRUE 21 21 NO_TEST=TRUE DP_IG_D_MLP MAKE_BASE=TRUE NC_PCH_TP2 NO_TEST=TRUE NC_SATA_E_D2RPX MAKE_BASE=TRUE NC_PCH_TP1 TP_PCH_TP2 NO_TEST=TRUE NC_SATA_E_D2RNX MAKE_BASE=TRUE TP_PCH_TP1 NO_TEST=TRUE NC_SATA_E_R2D_CPX MAKE_BASE=TRUE NO_TEST=TRUE NC_DP_IG_D_MLNX MAKE_BASE=TRUE NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE NC_DP_IG_C_HPD MAKE_BASE=TRUE TP_SDVO_INTP NO_TEST=TRUE NC_DP_IG_C_AUXPX 19 19 NO_TEST=TRUE NC_SATA_D_D2RNX NO_TEST=TRUE NC_DP_IG_C_MLPX MAKE_BASE=TRUE TP_SDVO_STALLN NO_TEST=TRUE 21 21 NO_TEST=TRUE DP_IG_C_MLP DP_IG_D_MLN NO_TEST=TRUE NC_SATA_D_R2D_CNX NO_TEST=TRUE NC_USB_PCH_13PX MAKE_BASE=TRUE MAKE_BASE=TRUE TP_SATA_D_R2D_CN 18 19 19 NO_TEST=TRUE NC_SATA_C_D2RPX NO_TEST=TRUE NC_USB_PCH_13NX MAKE_BASE=TRUE MAKE_BASE=TRUE 18 18 NC_DP_IG_C_MLNX MAKE_BASE=TRUE NC_USB_PCH_11PX MAKE_BASE=TRUE USB_PCH_13_N 19 NO_TEST=TRUE NC_SATA_C_D2RNX NO_TEST=TRUE NC_USB_PCH_11NX MAKE_BASE=TRUE MAKE_BASE=TRUE NO_TEST=TRUE NC_DP_IG_B_CTRL_DATA MAKE_BASE=TRUE NO_TEST=TRUE NC_USB_PCH_6PX USB_PCH_11_N TP_SATA_C_D2RP MAKE_BASE=TRUE MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE 18 18 19 NC_USB_PCH_6NX USB_PCH_6_P TP_SATA_C_D2RN 18 NC_DP_IG_B_CTRL_CLK MAKE_BASE=TRUE NO_TEST=TRUE NC_USB_PCH_5PX USB_PCH_6_N 18 19 NC_USB_PCH_4PX MAKE_BASE=TRUE 20 DP_IG_B_DDC_DATA NC_SATA_C_R2D_CPX NO_TEST=TRUE NC_DP_IG_B_HPD MAKE_BASE=TRUE 19 TP_SATA_C_R2D_CP NO_TEST=TRUE MAKE_BASE=TRUE 20 DP_IG_B_DDC_CLK NC_USB_PCH_4NX MAKE_BASE=TRUE 20 19 NO_TEST=TRUE 21 10 DP_IG_B_HPD 18 NO_TEST=TRUE NC_DP_IG_B_AUXPX MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE TP_PE_TX_P 19 NO_TEST=TRUE NC_DP_IG_B_AUXNX MAKE_BASE=TRUE NO_TEST=TRUE TP_PCIE_CLK100M_PE5N TP_PE_TX_N NO_TEST=TRUE NC_PCIE_CLK100M_PE4PX 18 10 NO_TEST=TRUE DP_IG_B_MLN 19 18 NC_SATA_C_R2D_CNX NO_TEST=TRUE NC_CRT_IG_DDC_CLK PCH Test Points TP_SATA_C_R2D_CN NC_CRT_IG_VSYNC MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE C NO_TEST=TRUE 19 NO_TEST=TRUE NC_PCIE_CLK100M_PE4NX NO_TEST=TRUE 19 NO_TEST=TRUE NC_PCIE_CLK100M_PE0PX NO_TEST=TRUE NC_CRT_IG_HSYNC MAKE_BASE=TRUE 18 NO_TEST=TRUE NC_CRT_IG_BLUE MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NC_MEM_B_DQSPX MAKE_BASE=TRUE MAKE_BASE=TRUE NO_TEST=TRUE NC_MEM_B_DQSNX MAKE_BASE=TRUE TP_MEM_B_DQS_P NO_TEST=TRUE NC_MEM_B_DQ_CB MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE NC_MEM_A_DQSPX MAKE_BASE=TRUE 12 12 18 MAKE_BASE=TRUE TP_MEM_A_DQ_CB NO_TEST=TRUE PCH SATA TP_CRT_IG_RED NC_PCIE1_D2RNX MAKE_BASE=TRUE NO_TEST=TRUE PCH Unused Display TP_PCIE1_D2RN 18 CPU Memory D 5 19 PCH_FDI_FSYNC NC_PCH_FDI_FSYNC 19 PCH_FDI_LSYNC NC_PCH_FDI_LSYNC 19 PCH_FDI_INT MAKE_BASE=TRUE MAKE_BASE=TRUE NO_TEST=TRUE NO_TEST=TRUE NC_PCH_FDI_INT MAKE_BASE=TRUE NO_TEST=TRUE NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED BRANCH PAGE prefsb OF 143 SHEET OF 117 SIZE D A D D ALIASES (BLANK) C C B B A SYNC_MASTER=K70_MLB PAGE TITLE SYNC_DATE=08/23/2011 Signal Aliases DRAWING NUMBER Apple Inc 051-9504 REVISION 7.0.0 R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED BRANCH PAGE prefsb OF 143 SHEET OF 117 SIZE D A SHORT B4 & C4 TOGETHER, ROUTE AS A SINGLE MIL TRACE TO R1010.1 ROUTE B5 TO R1010.1 AS A SEPERATE 12 MIL TRACE 99 19 IN 99 19 IN 99 19 D 99 19 99 19 IN IN OUT 99 19 OUT 99 19 OUT 99 19 99 19 OUT OUT 99 19 OUT 99 19 OUT 99 19 OUT 8 8 8 8 8 8 8 C W5 V3 Y3 AA4 DMI_RX_0 DMI_RX_1 DMI_RX_2 DMI_RX_3 DMI_N2S_N DMI_N2S_N DMI_N2S_N DMI_N2S_N V6 W8 Y7 AA8 DMI_N2S_P DMI_N2S_P DMI_N2S_P DMI_N2S_P TP_CPU_FDI_TX_N TP_CPU_FDI_TX_N TP_CPU_FDI_TX_N TP_CPU_FDI_TX_N TP_CPU_FDI_TX_N TP_CPU_FDI_TX_N TP_CPU_FDI_TX_N TP_CPU_FDI_TX_N AC7 AC3 AD1 AD3 AD6 AE8 AF2 AG1 TP_CPU_FDI_TX_P TP_CPU_FDI_TX_P TP_CPU_FDI_TX_P TP_CPU_FDI_TX_P TP_CPU_FDI_TX_P TP_CPU_FDI_TX_P TP_CPU_FDI_TX_P TP_CPU_FDI_TX_P AC8 AC2 AD2 AD4 AD7 AE7 AF3 AG2 FDI_TX_0* FDI_TX_1* FDI_TX_2* FDI_TX_3* FDI_TX_4* FDI_TX_5* FDI_TX_6* FDI_TX_7* FDI_TX_0 FDI_TX_1 FDI_TX_2 FDI_TX_3 FDI_TX_4 FDI_TX_5 FDI_TX_6 FDI_TX_7 8 TP_CPU_FDI_INT AG3 FDI_INT TP_CPU_FDI_LSYNC TP_CPU_FDI_LSYNC AC4 FDI_LSYNC_0 AE4 FDI_LSYNC_1 99 CPU_FDI_COMPIO AE2 FDI_COMPIO AE1 FDI_ICOMPO R1011 8 8 8 8 8 8 B DMI_TX_0 DMI_TX_1 DMI_TX_2 DMI_TX_3 AC5 FDI_FSYNC_0 AE5 FDI_FSYNC_1 5% 1/16W MF-LF 402 V7 W7 Y6 AA7 8 TP_PE_RX_N TP_PE_RX_N TP_PE_RX_N TP_PE_RX_N P4 R1 T3 U1 PE_RX_0* PE_RX_1* PE_RX_2* PE_RX_3* TP_PE_RX_P TP_PE_RX_P TP_PE_RX_P TP_PE_RX_P P3 R2 T4 U2 PE_RX_0 PE_RX_1 PE_RX_2 PE_RX_3 TP_PE_TX_N TP_PE_TX_N TP_PE_TX_N TP_PE_TX_N P7 T8 R5 U6 PE_TX_0* PE_TX_1* PE_TX_2* PE_TX_3* TP_PE_TX_P TP_PE_TX_P TP_PE_TX_P TP_PE_TX_P P8 T7 R6 U5 PE_TX_0 PE_TX_1 PE_TX_2 PE_TX_3 PLACE_NEAR=U1000.B4:12.7MM =PPVCCIO_S0_CPU OMIT_TABLE U1000 11 13 16 28 66 R1010 98 CPU_PEG_COMP BGA-SKT-K70 SYM OF 10 DMI_TX_0* DMI_TX_1* DMI_TX_2* DMI_TX_3* TP_CPU_FDI_FSYNC TP_CPU_FDI_FSYNC PLACE_NEAR=U1000.AE2:6.3MM DMI_S2N_P DMI_S2N_P DMI_S2N_P DMI_S2N_P IVY-BRIDGE PEG_COMPI B4 PEG_ICOMPO B5 PEG_RCOMPO C4 PEG_RX_0* PEG_RX_1* PEG_RX_2* PEG_RX_3* PEG_RX_4* PEG_RX_5* PEG_RX_6* PEG_RX_7* PEG_RX_8* PEG_RX_9* PEG_RX_10* PEG_RX_11* PEG_RX_12* PEG_RX_13* PEG_RX_14* PEG_RX_15* B12 D11 C9 E9 B7 C5 A6 E1 F3 G1 H4 J2 K4 L2 M4 N2 PEG_D2R_C_N PEG_D2R_C_N PEG_D2R_C_N PEG_D2R_C_N PEG_D2R_C_N PEG_D2R_C_N PEG_D2R_C_N PEG_D2R_C_N PEG_D2R_C_N PEG_D2R_C_N PEG_D2R_C_N PEG_D2R_C_N PEG_D2R_C_N PEG_D2R_C_N PEG_D2R_C_N PEG_D2R_C_N PEG_RX_0 PEG_RX_1 PEG_RX_2 PEG_RX_3 PEG_RX_4 PEG_RX_5 PEG_RX_6 PEG_RX_7 PEG_RX_8 PEG_RX_9 PEG_RX_10 PEG_RX_11 PEG_RX_12 PEG_RX_13 PEG_RX_14 PEG_RX_15 B11 D12 C10 E10 B8 C6 A5 E2 F4 G2 H3 J1 K3 L1 M3 N1 PEG_D2R_C_P PEG_D2R_C_P PEG_D2R_C_P PEG_D2R_C_P PEG_D2R_C_P PEG_D2R_C_P PEG_D2R_C_P PEG_D2R_C_P PEG_D2R_C_P PEG_D2R_C_P PEG_D2R_C_P PEG_D2R_C_P PEG_D2R_C_P PEG_D2R_C_P PEG_D2R_C_P PEG_D2R_C_P PEG_TX_0* PEG_TX_1* PEG_TX_2* PEG_TX_3* PEG_TX_4* PEG_TX_5* PEG_TX_6* PEG_TX_7* PEG_TX_8* PEG_TX_9* PEG_TX_10* PEG_TX_11* PEG_TX_12* PEG_TX_13* PEG_TX_14* PEG_TX_15* C14 E13 G13 F11 J13 D7 C3 E5 F7 G9 G6 K8 J6 M7 L5 N6 PEG_R2D_N PEG_R2D_N PEG_R2D_N PEG_R2D_N PEG_R2D_N PEG_R2D_N PEG_R2D_N PEG_R2D_N PEG_R2D_N PEG_R2D_N PEG_R2D_N PEG_R2D_N PEG_R2D_N PEG_R2D_N PEG_R2D_N PEG_R2D_N PEG_TX_0 PEG_TX_1 PEG_TX_2 PEG_TX_3 PEG_TX_4 PEG_TX_5 PEG_TX_6 PEG_TX_7 PEG_TX_8 PEG_TX_9 PEG_TX_10 PEG_TX_11 PEG_TX_12 PEG_TX_13 PEG_TX_14 PEG_TX_15 C13 E14 G14 F12 J14 D8 D3 E6 F8 G10 G5 K7 J5 M8 L6 N5 PEG_R2D_P PEG_R2D_P PEG_R2D_P PEG_R2D_P PEG_R2D_P PEG_R2D_P PEG_R2D_P PEG_R2D_P PEG_R2D_P PEG_R2D_P PEG_R2D_P PEG_R2D_P PEG_R2D_P PEG_R2D_P PEG_R2D_P PEG_R2D_P IVY-BRIDGE 24.9 BGA-SKT-K70 1% 1/16W MF-LF 402 IN 75 98 IN 75 98 IN 75 98 IN 75 98 IN 75 98 IN 75 98 IN 75 98 IN 75 98 IN 75 98 IN 75 98 IN 75 98 IN 75 98 IN 75 98 IN 75 98 IN 75 98 IN 75 98 IN 75 98 IN 75 98 IN 75 98 IN 75 98 99 25 IN IN 75 98 99 25 IN IN 75 98 99 25 15 IN IN 75 98 99 25 15 IN IN 75 98 99 25 IN IN 75 98 99 25 15 IN IN 75 98 99 25 15 IN IN 75 98 99 25 IN IN 75 98 99 25 IN IN 75 98 99 25 IN IN 75 98 99 25 IN IN 75 98 99 25 IN IN 75 98 IN OUT 75 98 IN OUT 75 98 IN OUT 75 98 IN 99 25 OUT 75 98 IN 99 25 OUT 75 98 IN OUT 75 98 OUT 75 98 OUT 75 98 OUT 75 98 OUT 75 98 OUT 75 98 OUT 75 98 OUT 75 98 OUT 75 98 OUT 75 98 OUT 75 98 OUT 75 98 OUT 75 98 OUT 75 98 OUT 75 98 OUT 75 98 OUT 75 98 OUT 75 98 OUT 75 98 OUT 75 98 OUT 75 98 OUT 75 98 OUT 75 98 OUT 75 98 OUT 75 98 OUT 75 98 OUT 75 98 8 8 8 8 8 8 8 8 TP_CPU_RSVD TP_CPU_RSVD TP_CPU_RSVD TP_CPU_RSVD TP_CPU_RSVD TP_CPU_RSVD TP_CPU_RSVD TP_CPU_RSVD TP_CPU_RSVD TP_CPU_RSVD TP_CPU_RSVD TP_CPU_RSVD TP_CPU_RSVD TP_CPU_RSVD TP_CPU_RSVD TP_CPU_RSVD NC_SNS_CPU_THERMDN NO_TEST=TRUE NC_SNS_CPU_THERMDP NO_TEST=TRUE TP_CPU_RSVD C38 C39 D38 H7 H8 J9 J31 J33 J34 K9 K31 K34 L9 L31 L33 L34 M34 N33 N34 CPU_CFG CPU_CFG CPU_CFG CPU_CFG CPU_CFG CPU_CFG CPU_CFG CPU_CFG CPU_CFG CPU_CFG CPU_CFG CPU_CFG CPU_CFG CPU_CFG CPU_CFG CPU_CFG CPU_CFG CPU_CFG H36 J36 J37 K36 L36 N35 L37 M36 J38 L35 M38 N36 N38 N39 N37 N40 G37 G36 SYM OF 10 RSVD_C38 RSVD_P35 P35 RSVD_C39 RSVD_P37 P37 RSVD_D38 RSVD_P39 P39 RSVD_H7 RSVD_R34 R34 RSVD_H8 RSVD_R36 R36 RSVD_J9 RSVD_R38 R38 RSVD_J31 RSVD_R40 R40 RSVD_J33 RSVD_AB6 AB6 RSVD_J34 RSVD_AB7 AB7 RSVD_K9 RSVD_AD34 AD34 RSVD_K31 RSVD_AD35 AD35 RSVD_K34 RSVD_AD37 AD37 RSVD_L9 RSVD_AE6 AE6 RSVD_L31 RSVD_AF4 AF4 RSVD_AG4 AG4 RSVD_L33 RSVD_L34 RSVD_AJ11 AJ11 RSVD_M34 ThermDC RSVD_AJ29 AJ29 RSVD_AJ30 AJ30 RSVD_N33 ThermDA RSVD_N34 RSVD_AJ31 AJ31 RSVD_AN20 AN20 CFG_0 RSVD_AP20 AP20 RSVD_AT11 AT11 CFG_1 CFG_2 RSVD_AT14 AT14 CFG_3 RSVD_AU10 AU10 RSVD_AV34 AV34 CFG_4 RSVD_AW34 AW34 CFG_5 CFG_6 RSVD_AY10 AY10 TP_CPU_RSVD TP_CPU_RSVD TP_CPU_RSVD TP_CPU_RSVD TP_CPU_RSVD TP_CPU_RSVD TP_CPU_RSVD TP_CPU_RSVD TP_CPU_RSVD TP_CPU_RSVD TP_CPU_RSVD TP_CPU_RSVD TP_CPU_RSVD TP_CPU_RSVD TP_CPU_RSVD TP_CPU_RSVD TP_CPU_RSVD TP_CPU_RSVD TP_CPU_RSVD TP_CPU_RSVD TP_CPU_RSVD TP_CPU_RSVD TP_CPU_RSVD TP_CPU_RSVD TP_CPU_RSVD TP_CPU_RSVD TP_CPU_RSVD RESERVED IN U1000 PCI EXPRESS GRAPHICS IN 99 19 OMIT_TABLE DMI 99 19 DMI_RX_0* DMI_RX_1* DMI_RX_2* DMI_RX_3* (Unused) IN W4 V4 Y4 AA5 FLEXIBLE DISPLAY INTERFACE 99 19 DMI_S2N_N DMI_S2N_N DMI_S2N_N DMI_S2N_N PCI EXPRESS IN (Available for Workstation only) 99 19 CFG_7 CFG_8 CFG_9 CFG_10 CFG_11 CFG_12 CFG_13 CFG_14 CFG_15 CFG_16 CFG_17 RSVD_NCTF_AV1 AV1 RSVD_NCTF_AW2 AW2 RSVD_NCTF_AY3 AY3 RSVD_NCTF_B39 B39 NCTF_A38 NCTF_C2 NCTF_D1 NCTF_AU40 NCTF_AW38 8 D 8 8 8 8 8 8 8 8 8 8 8 8 TP_CPU_RSVD_NCTF TP_CPU_RSVD_NCTF TP_CPU_RSVD_NCTF TP_CPU_RSVD_NCTF A38 C2 D1 AU40 AW38 C TP_CPU_NCTF TP_CPU_NCTF TP_CPU_NCTF TP_CPU_NCTF TP_CPU_NCTF INTEL SUGGESTS TO KEEP THESE TPS ( IVY BRIDGE EDS #473717 TABLE 6-5 ) CFG [1:0] RESERVED CONFIGURATION LANE CFG [2] PCIE STATIC X16 LANE REVERSAL = NORMAL OPERATION = LANES REVERSED CFG [3] PCIE STATIC X4 LANE REVERSAL = NORMAL OPERATION = LANES REVERSED CFG [4] RESERVED CONFIGURATION LANE CFG [6:5] PCIE BIFURCATION CFG [17:7] RESERVED CONFIGURATION LANE 11 = X16 (DEFAULT) 10 = X8 01 = RSVD 00 = X8, X4 B A SYNC_MASTER=D8_ROSITA SYNC_DATE=03/23/2012 PAGE TITLE CPU DMI/PEG/FDI/RSVD DRAWING NUMBER Apple Inc 051-9504 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED D 7.0.0 R NOTICE OF PROPRIETARY PROPERTY: SIZE REVISION BRANCH prefsb PAGE 10 OF 143 SHEET 10 OF 117 A SMBus SMBus-specific Physical Rules TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP SMB_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD TABLE_PHYSICAL_RULE_ITEM Physical Net Type to Rule Map TABLE_PHYSICAL_ASSIGNMENT_HEAD D NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET SMB_PHY * SMB_55S D TABLE_PHYSICAL_ASSIGNMENT_ITEM SMBus-specific Spacing Definitions Constraints TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT SMB_ISO * =2x_DIELECTRIC ? TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET SMB * * SMB_ISO TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM Sensor Sensor-specific Physical Rules TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 1:1_DIFFPAIR * Y =STANDARD =STANDARD =STANDARD 0.1 MM 0.085 MM SNS_50S * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM Physical Net Type to Rule Map TABLE_PHYSICAL_ASSIGNMENT_HEAD NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET SNS_DIFF_PHY * 1:1_DIFFPAIR SNS_PHY * SNS_50S TABLE_PHYSICAL_ASSIGNMENT_ITEM TABLE_PHYSICAL_ASSIGNMENT_ITEM C Sensor-specific Spacing Definitions C Constraints TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT SENSE_ISO * =4:1_SPACING ? TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET SENSE * * SENSE_ISO SENSE POWER * PWR_P2MM SENSE GND * GND_P2MM TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM B B A SYNC_MASTER=D8_MARK SYNC_DATE=04/23/2012 PAGE TITLE SMBus/Sensor Constraints DRAWING NUMBER Apple Inc 051-9504 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED D 7.0.0 R NOTICE OF PROPRIETARY PROPERTY: SIZE REVISION BRANCH prefsb PAGE 127 OF 143 SHEET 103 OF 117 A DC-DC Power-specific Physical Rules CPU VccIO PCH 1.05V S0 TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP Electrical Contraint Set TABLE_PHYSICAL_RULE_ITEM GND_P3MM * Y 0.300 MM 0.200 MM =STANDARD 3.0 MM Physical Spacing Voltage DIDT NO_TEST I1 POWER_PHY POWER 5V I2 POWER_PHY POWER 5V REG_VCC_U7400 REG_PVCC_U7400 GND_PHY GND 0V AGND_CPU_P1V05S0 69 I5 POWER_PHY VR_SWITCH 12V TRUE REG_CPU_PHASE_P1V05S0 69 I7 VR_CTL_PHY VR_SWITCH 12V TRUE I6 VR_CTL_PHY VR_SWITCH 12V TRUE I8 VR_CTL_PHY VR_SWITCH 12V TRUE I9 VR_CTL_PHY VR_SWITCH 12V TRUE I10 VR_CTL_PHY VR_LGATE 12V TRUE I12 VR_CTL_PHY VR_SWITCH 12V TRUE I11 VR_CTL_PHY VR_CTL I14 VR_CTL_PHY VR_CTL =STANDARD Input Bus TABLE_PHYSICAL_RULE_ITEM GND_P5MM * Y 0.500 MM 0.200 MM 3.0 MM =STANDARD =STANDARD POWER_50S * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD TABLE_PHYSICAL_RULE_ITEM 69 69 TABLE_PHYSICAL_RULE_ITEM POWER_P3MM * Y 0.300 MM 0.200 MM 3.0 MM =STANDARD =STANDARD POWER_P6MM * Y 0.600 MM 0.200 MM 3.0 MM =STANDARD =STANDARD Local Ground TABLE_PHYSICAL_RULE_ITEM D I3 D TABLE_PHYSICAL_RULE_ITEM POWER_P5MM * Y 0.500 MM 0.200 MM =STANDARD 3.0 MM =STANDARD 1.05V S0 Physical Net Type to Rule Map TABLE_PHYSICAL_ASSIGNMENT_HEAD NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET TABLE_PHYSICAL_ASSIGNMENT_ITEM VR_CTL_PHY * POWER_P5MM TABLE_PHYSICAL_ASSIGNMENT_ITEM VR_CTL_PHY BGA STANDARD VR_VID_PHY * POWER_50S POWER_PHY * POWER_P6MM TABLE_PHYSICAL_ASSIGNMENT_ITEM TABLE_PHYSICAL_ASSIGNMENT_ITEM TABLE_PHYSICAL_ASSIGNMENT_ITEM GND_PHY * GND_P5MM Constraints Power and Common I13 VSNS_CPU_VCCIO SNS_DIFF_PHY SENSE I15 VSNS_CPU_VCCIO SNS_DIFF_PHY SENSE I16 SNS_DIFF_PHY SENSE I17 SNS_DIFF_PHY SENSE I19 SENSE I18 SENSE I21 VR_CTL_PHY VR_CTL I20 VR_CTL_PHY VR_CTL POWER_PHY POWER TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET TRUE TRUE REG_CPU_BOOT_P1V05S0 REG_CPU_BOOT_P1V05S0_RC REG_CPU_UGATE_P1V05S0 REG_CPU_UGATE_P1V05S0_R REG_CPU_LGATE_P1V05S0 REG_CPU_SNUBBER_P1V05S0 69 69 69 69 69 REG_CPU_P1V05S0_OCSET REG_CPU_P1V05S0_VO 69 69 SNS_CPU_VCCIO_P SNS_CPU_VCCIO_N SNS_CPU_P1V05S0_XW_P SNS_CPU_P1V05S0_XW_N REG_CPU_P1V05S0_FB REG_CPU_P1V05S0_RTN 13 69 13 69 69 69 69 69 REG_CPU_P1V05S0_SREF REG_CPU_P1V05S0_FSEL 69 69 TABLE_SPACING_ASSIGNMENT_ITEM POWER * * POWER_ISO GND * * GND_ISO NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET Output Bus TABLE_SPACING_ASSIGNMENT_ITEM Power-specific Spacing Definitions Power and Common I22 PP1V05_S0_CPU 1.05V TABLE_SPACING_RULE_HEAD C SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT POWER_ISO * =STANDARD ? C DC-DC Baddies TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 TABLE_SPACING_ASSIGNMENT_ITEM VR_SWITCH * * SWNODE_ISO VR_SWITCH * BGA BGA_P1MM VR_SWITCH VR_SWITCH * SWNODE_SW2SW TABLE_SPACING_ASSIGNMENT_ITEM DC-DC Baddies PCH/GPU/TBT 1.05V S0 TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT SWNODE_ISO * =8:1_SPACING 1000 TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_RULE_ITEM * =1:1_SPACING ? * =2:1_SPACING ? SWNODE_SW2GND * =2:1_SPACING ? POWER * SWNODE_SW2PWR VR_SWITCH GND * SWNODE_SW2GND VR_LGATE * * SWNODE_ISO Electrical Contraint Set TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_RULE_ITEM SWNODE_SW2SW SWNODE_SW2PWR VR_SWITCH I44 TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_RULE_ITEM VR_LGATE VR_SWITCH * =3:1_SPACING I46 DC-DC Control NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET TABLE_SPACING_ASSIGNMENT_ITEM LINE-TO-LINE SPACING NO_TEST POWER_PHY POWER 5V REG_VCC_UB700 95 GND_PHY GND 0V P1V05_AGND 95 1.05V S0 TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 TABLE_SPACING_RULE_HEAD LAYER DIDT Local Ground ? DC-DC Control SPACING_RULE_SET Voltage SWNODE_LG2SW TABLE_SPACING_RULE_ITEM * Spacing TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_RULE_ITEM SWNODE_LG2SW Physical Input Bus WEIGHT VR_CTL * * VR_CTL_ISO I47 POWER_PHY VR_SWITCH 12V TRUE I48 POWER_PHY VR_SWITCH 12V TRUE I49 VR_CTL_PHY VR_SWITCH 12V TRUE I50 VR_CTL_PHY VR_SWITCH 12V TRUE I51 VR_CTL_PHY VR_SWITCH 12V TRUE I52 VR_CTL_PHY VR_SWITCH 12V TRUE I53 VR_CTL_PHY VR_LGATE 12V TRUE I54 VR_CTL_PHY VR_SWITCH 12V TRUE I55 VR_CTL_PHY VR_CTL I56 VR_CTL_PHY VR_CTL I72 POWER_PHY VR_SWITCH 12V I73 POWER_PHY VR_SWITCH 12V TABLE_SPACING_RULE_ITEM VR_CTL_ISO * =3:1_SPACING ? TABLE_SPACING_ASSIGNMENT_ITEM VR_VID * * VR_VID_ISO TABLE_SPACING_RULE_ITEM VR_VID_ISO B * =4X_DIELECTRIC ? CPU VccSA Electrical Contraint Set Physical Spacing Voltage DIDT NO_TEST I24 POWER_PHY POWER 5V I25 POWER_PHY POWER 5V REG_VCC_U7500 REG_PVCC_U7500 GND_PHY GND 0V AGND_VCCSAS0 TRUE TRUE REG_PHASE_P1V05S0 REG_PHASE_P1V05S0_L REG_BOOT_P1V05S0 REG_BOOT_P1V05S0_RC REG_UGATE_P1V05S0 REG_UGATE_P1V05S0_R REG_LGATE_P1V05S0 REG_SNUBBER_P1V05S0 95 95 95 95 95 95 95 95 REG_P1V05S0_OCSET REG_P1V05S0_VO REG_P1V05S0_VO_R P1V05_OCSET_R 95 B 95 95 95 Input Bus 70 70 Local Ground I26 70 VCCIO I27 POWER_PHY VR_SWITCH 12V TRUE I28 VR_CTL_PHY VR_SWITCH 12V TRUE I29 VR_CTL_PHY VR_SWITCH 12V TRUE I31 VR_CTL_PHY VR_SWITCH 12V TRUE I30 VR_CTL_PHY VR_LGATE 12V TRUE I33 VR_CTL_PHY VR_SWITCH 12V TRUE I32 VR_CTL_PHY VR_CTL I35 VR_CTL_PHY VR_CTL A I37 VSNS_CPU_VCCSA SNS_DIFF_PHY SENSE I36 VSNS_CPU_VCCSA SNS_DIFF_PHY SENSE I38 SENSE I39 SENSE I40 VR_CTL_PHY VR_CTL I41 VR_CTL_PHY VR_CTL TRUE REG_VCCSAS0_OCSET REG_VCCSAS0_VO SNS_CPU_VCCSA SNS_VCCSAS0_XW_P SNS_VCCSAS0_XW_N REG_VCCSAS0_FB REG_VCCSAS0_RTN SENSE I34 TRUE REG_PHASE_VCCSAS0 REG_BOOT_VCCSAS0 REG_BOOT_VCCSAS0_RC REG_UGATE_VCCSAS0 REG_LGATE_VCCSAS0 REG_SNUBBER_VCCSAS0 REG_VCCSAS0_SREF REG_VCCSAS0_FSEL 70 I61 SENSE I62 SENSE REG_P1V05S0_FB REG_P1V05S0_RTN 95 95 REG_P1V05S0_SREF REG_P1V05S0_FSEL I63 VR_CTL_PHY VR_CTL I64 VR_CTL_PHY VR_CTL I68 POWER_PHY POWER 1.05V PP1V05_S0_PCH I66 POWER_PHY POWER 1.05V PP1V05_S0 PP1V05_TBTLC PP1V05_TBTCIO 95 95 70 70 Output Bus 70 70 70 FET Switched 70 I67 POWER_PHY POWER 1.05V 70 I69 POWER_PHY POWER 1.05V 38 13 70 70 70 70 70 70 SYNC_MASTER=D8_MARK 70 PAGE TITLE Output Bus I42 POWER_PHY POWER 0.925V PPVCCSA_S0 SYNC_DATE=02/10/2012 VReg Constraints DRAWING NUMBER Apple Inc 051-9504 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED D 7.0.0 R NOTICE OF PROPRIETARY PROPERTY: SIZE REVISION BRANCH prefsb PAGE 128 OF 143 SHEET 104 OF 117 A CPU Core Phases Electrical Contraint Set Physical Spacing Voltage DIDT NO_TEST Electrical Contraint Set Physical Spacing Voltage I836 POWER_PHY POWER 12V I1136 POWER_PHY POWER 5V PP12V_S0_CPUCORE_FLT REG_VCC_U7100 GND_PHY GND 0V AGND_CPU I1264 I1183 POWER_PHY POWER 12V I1185 VR_CTL_PHY VR_CTL I1186 VR_CTL_PHY VR_CTL I1187 POWER_PHY VR_SWITCH 12V TRUE I1188 VR_CTL_PHY VR_SWITCH 12V TRUE I1189 VR_CTL_PHY VR_SWITCH 12V TRUE I1190 VR_CTL_PHY VR_SWITCH 12V TRUE I1191 VR_CTL_PHY VR_LGATE 12V TRUE I1192 VR_CTL_PHY VR_SWITCH 12V TRUE I1193 POWER_PHY POWER 1.1V NO_TEST 66 67 68 66 66 67 68 Phase REG_LVCC_U7210 I883 POWER_PHY POWER I884 VR_CTL_PHY VR_CTL I885 VR_CTL_PHY VR_CTL I887 POWER_PHY VR_SWITCH 12V TRUE I888 VR_CTL_PHY VR_SWITCH 12V TRUE I890 VR_CTL_PHY VR_SWITCH 12V TRUE I889 VR_CTL_PHY VR_SWITCH 12V TRUE I891 VR_CTL_PHY VR_LGATE 12V TRUE I892 VR_CTL_PHY VR_SWITCH 12V TRUE I893 POWER_PHY POWER 1.1V I894 ISNS_CPU_CORE SNS_DIFF_PHY SENSE I895 ISNS_CPU_CORE SNS_DIFF_PHY SENSE 12V REG_PWM_CPUCORE_1 REG_PWM_CPUCORE_1_R TRUE TRUE PPCPUCORE_S0_SENSE_1 REG_ISENCORE_1_P REG_ISENCORE_1_N REG_ISENCORE_1_NR SENSE I896 REG_PHASE_CPUCORE_1 REG_BOOT_CPUCORE_1 REG_BOOT_CPUCORE_1_RC REG_UGATE_CPUCORE_1 REG_LGATE_CPUCORE_1 REG_SNUBBER_CPUCORE_1 67 66 67 66 67 67 I1194 ISNS_CPU_AXG SNS_DIFF_PHY SENSE 67 I1195 ISNS_CPU_AXG SNS_DIFF_PHY SENSE 67 I1196 SENSE 67 I1197 SENSE 67 I1278 ISNS_CPU_AXG SNS_DIFF_PHY SENSE I1277 ISNS_CPU_AXG SNS_DIFF_PHY SENSE I1279 ISNS_CPU_AXG SNS_DIFF_PHY SENSE I1280 ISNS_CPU_AXG SNS_DIFF_PHY SENSE I1027 VR_CTL_PHY VR_CTL I1026 VR_CTL_PHY VR_CTL I1028 VR_CTL_PHY VR_CTL I1029 VR_CTL_PHY VR_CTL I1030 VR_CTL_PHY VR_CTL 66 67 I1031 VR_CTL_PHY VR_CTL 66 I1033 VR_CTL_PHY VR_CTL I1041 VR_CTL_PHY VR_CTL I1042 VR_CTL_PHY VR_CTL 67 66 67 67 POWER_PHY I1138 POWER REG_LVCC_U7230 12V REG_PWM_CPUCORE_2 REG_PWM_CPUCORE_2_R I1140 VR_CTL_PHY VR_CTL I1141 VR_CTL_PHY VR_CTL I1142 POWER_PHY VR_SWITCH 12V TRUE I1143 VR_CTL_PHY VR_SWITCH 12V TRUE I1145 VR_CTL_PHY VR_SWITCH 12V TRUE I1144 VR_CTL_PHY VR_SWITCH 12V TRUE I1147 VR_CTL_PHY VR_LGATE 12V TRUE I1146 VR_CTL_PHY VR_SWITCH 12V TRUE I1149 POWER_PHY POWER 1.1V I1148 ISNS_CPU_CORE SNS_DIFF_PHY SENSE I1151 ISNS_CPU_CORE SNS_DIFF_PHY SENSE TRUE TRUE PPCPUCORE_S0_SENSE_2 REG_ISENCORE_2_P REG_ISENCORE_2_N REG_ISENCORE_2_NR SENSE I1150 REG_PHASE_CPUCORE_2 REG_BOOT_CPUCORE_2 REG_BOOT_CPUCORE_2_RC REG_UGATE_CPUCORE_2 REG_LGATE_CPUCORE_2 REG_SNUBBER_CPUCORE_2 POWER_PHY POWER REG_LVCC_U7250 12V REG_PWM_CPUCORE_3 REG_PWM_CPUCORE_3_R I1156 VR_CTL_PHY VR_CTL I1155 VR_CTL_PHY VR_CTL I1158 POWER_PHY VR_SWITCH 12V TRUE I1157 VR_CTL_PHY VR_SWITCH 12V TRUE I1159 VR_CTL_PHY VR_SWITCH 12V TRUE I1160 VR_CTL_PHY VR_SWITCH 12V TRUE I1161 VR_CTL_PHY VR_LGATE 12V TRUE I1162 VR_CTL_PHY VR_SWITCH 12V TRUE I1163 POWER_PHY POWER 1.1V I1164 ISNS_CPU_CORE SNS_DIFF_PHY SENSE I1165 ISNS_CPU_CORE SNS_DIFF_PHY SENSE TRUE TRUE PPCPUCORE_S0_SENSE_3 REG_ISENCORE_3_P REG_ISENCORE_3_N REG_ISENCORE_3_NR SENSE I1166 REG_PHASE_CPUCORE_3 REG_BOOT_CPUCORE_3 REG_BOOT_CPUCORE_3_RC REG_UGATE_CPUCORE_3 REG_LGATE_CPUCORE_3 REG_SNUBBER_CPUCORE_3 68 REG_PWM_CPUAXG REG_PWM_CPUAXG_R TRUE TRUE 66 68 66 REG_PHASE_CPUAXG REG_BOOT_CPUAXG REG_BOOT_CPUAXG_RC REG_UGATE_CPUAXG REG_LGATE_CPUAXG REG_SNUBBER_CPUAXG D 68 68 68 68 68 68 PPCPUAXG_S0_SENSE 68 REG_ISENAXG_P REG_ISENAXG_N REG_ISENAXG_PR REG_ISENAXG_NR SNS_AXG_R_P SNS_AXG_R_N SNS_AXG_XW_P SNS_AXG_XW_N 68 68 66 68 66 68 66 66 66 66 ISL6364 67 67 REG_CPUCORE_COMP CPUCORE_COMP_RC REG_CPUCORE_FB CPUCORE_FB_RC CPUCORE_FB_R_1 CPUCORE_FB_R_2 CPUCORE_PSICOMP_RC REG_CPUCORE_PSICOMP REG_CPUCORE_HFCOMP 66 66 66 66 66 66 66 66 C 66 67 67 67 67 67 67 I1032 SENSE I1035 SENSE I1045 VR_CTL_PHY VR_CTL I1046 VR_CTL_PHY VR_CTL I1050 VR_CTL_PHY VR_CTL I1054 VR_CTL_PHY VR_CTL I1056 VR_CTL_PHY VR_CTL I1055 VR_CTL_PHY VR_CTL I1051 VR_CTL_PHY VR_CTL I1052 VR_CTL_PHY VR_CTL I1053 VR_CTL_PHY VR_CTL VR_CTL 66 67 67 66 67 Phase I1152 REG_LVCC_U7330 66 67 Phase B DIDT AXG Local Ground C CPU AXG Phase and Core Controller Input Bus D 67 I1057 VR_CTL_PHY 66 67 I1059 VR_CTL_PHY VR_CTL 66 I1060 VR_CTL_PHY VR_CTL 67 I1012 VR_CTL_PHY VR_CTL 67 I1017 VR_CTL_PHY VR_CTL 67 I1013 VR_CTL_PHY VR_CTL 67 I1011 VR_CTL_PHY VR_CTL 67 I1015 VR_CTL_PHY VR_CTL 67 I1016 VR_CTL_PHY VR_CTL I1198 VR_CTL_PHY VR_CTL 67 REG_CPUCORE_VSEN REG_CPUCORE_RGND 66 66 REG_CPUCORE_IMON CPUCORE_IMON_R 51 66 66 REG_CPUCORE_TM REG_CPUCORE_SUTH REG_CPUCORE_NPSI REG_CPUCORE_FDVID REG_CPUCORE_IAUTO REG_CPUCORE_SW_FREQ REG_CPUCORE_RAMPADJ REG_CPUCORE_EN_PWR CPUCORE_EN_PWR_R REG_CPUCORE_RSET 66 66 66 66 66 66 66 66 66 66 REG_CPUAXG_COMP CPUAXG_COMP_RC REG_CPUAXG_FB CPUAXG_FB_RC CPUAXG_FB_R_1 CPUAXG_FB_R_2 REG_CPUAXG_HFCOMP 66 66 66 66 66 66 66 B 66 67 67 66 67 Phase POWER_PHY I1167 REG_LVCC_U7310 12V REG_PWM_CPUCORE_4 REG_PWM_CPUCORE_4_R I1171 VR_CTL_PHY VR_CTL I1170 VR_CTL_PHY VR_CTL I1173 POWER_PHY VR_SWITCH 12V TRUE I1172 VR_CTL_PHY VR_SWITCH 12V TRUE I1174 VR_CTL_PHY VR_SWITCH 12V TRUE I1175 VR_CTL_PHY VR_SWITCH 12V TRUE I1176 VR_CTL_PHY VR_LGATE 12V TRUE I1177 VR_CTL_PHY VR_SWITCH 12V TRUE POWER_PHY I1178 POWER I1179 ISNS_CPU_CORE SNS_DIFF_PHY SENSE I1180 ISNS_CPU_CORE SNS_DIFF_PHY SENSE 1.1V I1265 ISNS_CPU_CORE SNS_DIFF_PHY SENSE I1266 ISNS_CPU_CORE SNS_DIFF_PHY SENSE I1267 ISNS_CPU_CORE SNS_DIFF_PHY SENSE I1268 ISNS_CPU_CORE SNS_DIFF_PHY SENSE I1269 ISNS_CPU_CORE SNS_DIFF_PHY SENSE I1270 ISNS_CPU_CORE SNS_DIFF_PHY SENSE I1271 ISNS_CPU_CORE SNS_DIFF_PHY SENSE I1272 ISNS_CPU_CORE SNS_DIFF_PHY SENSE TRUE TRUE REG_PHASE_CPUCORE_4 REG_BOOT_CPUCORE_4 REG_BOOT_CPUCORE_4_RC REG_UGATE_CPUCORE_4 REG_LGATE_CPUCORE_4 REG_SNUBBER_CPUCORE_4 PPCPUCORE_S0_SENSE_4 REG_ISENCORE_4_P REG_ISENCORE_4_N REG_ISENCORE_4_NR SENSE I1181 A POWER SNS_CORE_XW_P SNS_CORE_XW_N 68 I1018 SENSE I1023 SENSE REG_CPUAXG_VSEN REG_CPUAXG_RGND VR_CTL_PHY VR_CTL I1043 VR_CTL_PHY VR_CTL I1047 VR_CTL_PHY VR_CTL I1048 VR_CTL_PHY VR_CTL I1049 VR_CTL_PHY VR_CTL 68 I1063 VR_VID_PHY VR_VID 68 I1062 VR_VID_PHY VR_VID 68 I1061 VR_VID_PHY VR_VID I1066 VR_VID_PHY VR_VID I1065 VR_VID_PHY VR_VID I1064 VR_VID_PHY VR_VID I1068 POWER_PHY POWER 1.1V I1069 POWER_PHY POWER 1.1V 66 68 68 68 68 66 68 66 REG_CPUAXG_IMON CPUAXG_IMON_R I1044 66 68 66 51 66 66 REG_CPUAXG_TM REG_CPUAXG_TCOMP REG_CPUAXG_SW_FREQ 66 66 66 CPU_VIDSCLK CPU_VIDSCLK_R CPU_VIDALERT_L CPU_VIDALERT_R_L CPU_VIDSOUT CPU_VIDSOUT_R 13 66 13 13 66 13 13 66 13 68 Output Bus 66 68 66 PPVCORE_S0_CPU PPVAXG_S0 6 66 SNS_CORE_R_P SNS_CORE_R_N 66 SYNC_MASTER=D8_MARK 66 SNS_CPU_VAXG_P SNS_CPU_VAXG_N SNS_CPU_VCORE_P SNS_CPU_VCORE_N SYNC_DATE=02/10/2012 PAGE TITLE 13 66 CPU VReg Constraints 13 66 DRAWING NUMBER 13 66 Apple Inc 13 66 051-9504 ISNS_CPU_CORE SNS_DIFF_PHY SENSE I1275 ISNS_CPU_CORE SNS_DIFF_PHY SENSE SNS_P1V05_IOVDD_XW_P SNS_P1V05_IOVDD_XW_N NOTICE OF PROPRIETARY PROPERTY: 95 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED 95 D 7.0.0 R I1276 SIZE REVISION BRANCH prefsb PAGE 129 OF 143 SHEET 105 OF 117 A 3.3V S5/5V S4 Physical DDR3 Vref Spacing Voltage DIDT NO_TEST Physical Input Bus Spacing Voltage DIDT Ground/Common NO_TEST Memory Vref I843 POWER_PHY POWER 12V I1254 POWER_PHY POWER 5V I1255 POWER_PHY POWER 5V REG_VIN_U7600 REG_VCC1_U7600 REG_VCC2_U7600 71 I1351 POWER_PHY POWER 3.3V 71 I1353 POWER_PHY POWER 3.3V I1352 POWER_DDR_PHY POWER_DDR 0.75V I849 POWER_PHY VR_SWITCH I847 VR_CTL_PHY VR_SWITCH 12V TRUE I851 VR_CTL_PHY VR_SWITCH 12V TRUE I848 VR_CTL_PHY VR_SWITCH 12V TRUE I850 VR_CTL_PHY VR_LGATE 12V TRUE I852 VR_CTL_PHY VR_SWITCH 12V TRUE I1071 VR_CTL_PHY VR_CTL I1072 VR_CTL_PHY VR_CTL I1136 VR_CTL_PHY VR_CTL I1082 VR_CTL_PHY VR_CTL I1078 VR_CTL_PHY VR_CTL I1077 VR_CTL_PHY 12V TRUE TRUE REG_PHASE_P3V3S5 REG_BOOT_P3V3S5 REG_BOOT_P3V3S5_RC REG_UGATE_P3V3S5 REG_LGATE_P3V3S5 REG_SNUBBER_P3V3S5 REG_P3V3S5_ISEN REG_P3V3S5_OCSET REG_P3V3S5_FSET REG_P3V3S5_VOUT REG_P3V3S5_VOUT_R REG_P3V3S5_FB VR_CTL PP3V3_S4_VREFMRGN_DAC PP3V3_S4_VREFMRGN_CTRL 34 71 71 71 71 PPDDRVREF_DQ_MEM_A_S3 PPDDRVREF_DQ_MEM_B_S3 CPU_DIMM_VREF_DAC_A CPU_DIMM_VREF_DAC_B 34 Spacing Voltage GND_PHY GND 0V DIDT NO_TEST GND I1354 POWER_DDR_PHY POWER_DDR 0.75V I1411 POWER_DDR_PHY POWER_DDR 0.75V I1412 POWER_DDR_PHY POWER_DDR 0.75V I1355 POWER_DDR_PHY POWER_DDR 0.75V I1356 POWER_DDR_PHY POWER_DDR 0.75V PPDDRVREF_CA_MEM_A_S3 PPDDRVREF_CA_MEM_B_S3 I1389 POWER_DDR_PHY POWER_DDR 0.75V CPU_DDR_VREF 11 I1408 POWER_DDR_PHY POWER_DDR 0.75V PPDDRVTT_S3 6 11 34 D 11 34 3V42 S0 71 71 Physical Common I1390 71 3.3V S5 D Physical Spacing Voltage 5V DIDT NO_TEST 3V42 S0 TRUE I1393 POWER_PHY VR_SWITCH P3V42G3H_SW 73 71 I1394 VR_CTL_PHY VR_CTL P3V42G3H_FB 73 71 I1395 VR_CTL_PHY VR_CTL P3V42G3H_SHDN_L 73 I1396 POWER_PHY POWER 3.3V I1398 POWER_PHY POWER 3.3V 71 71 71 71 PP3V3_G3 PP3V42_G3H 6 5V S3 C I1137 POWER_PHY VR_SWITCH 12V TRUE I1138 VR_CTL_PHY VR_SWITCH 12V TRUE I1139 VR_CTL_PHY VR_SWITCH 12V TRUE I1140 VR_CTL_PHY VR_SWITCH 12V TRUE I1141 VR_CTL_PHY VR_LGATE 12V TRUE I1143 VR_CTL_PHY VR_SWITCH 12V TRUE I1142 VR_CTL_PHY VR_CTL I1144 VR_CTL_PHY VR_CTL I1145 VR_CTL_PHY VR_CTL I1146 VR_CTL_PHY VR_CTL I1148 VR_CTL_PHY VR_CTL I1147 VR_CTL_PHY VR_CTL TRUE REG_PHASE_P5VS4 REG_BOOT_P5VS4 REG_BOOT_P5VS4_RC REG_UGATE_P5VS4 REG_LGATE_P5VS4 REG_SNUBBER_P5VS4 REG_P5VS4_ISEN REG_P5VS4_OCSET REG_P5VS4_FSET REG_P5VS4_VOUT REG_P5VS4_VOUT_R REG_P5VS4_FB 71 71 71 1.8V S0 71 71 POWER 5V I1153 POWER_PHY POWER 5V I1149 POWER_PHY POWER 3.3V POWER_PHY POWER 5V I1218 POWER_PHY POWER 3.3V I1233 POWER_PHY POWER 3.3V I1219 POWER_PHY POWER 3.3V I1382 POWER_PHY POWER 3.3V I1399 POWER_PHY POWER 3.3V I1407 POWER_PHY POWER 3.3V PP5V_S5 PP5V_S4 PP3V3_S5 PP5V_S0 PP3V3_S4 PP3V3_S0 PP3V3_S4_ENET PP3V3_TBTLC PP3V3_S4_AP PP3V3_S0_SSD GND_PHY B 72 VR_CTL_PHY VR_CTL REG_P1V8S0_SYNCH 72 PP1V8_S0 PP5V_S0_HDD 71 TRUE POWER_PHY POWER 1.8V C Physical Spacing Voltage POWER_PHY POWER 5V Spacing Voltage POWER 12V PP12V_ACDC POWER_PHY POWER 12V PP12V_S0 I1387 POWER_PHY POWER 12V PP12V_S5 I1397 POWER_PHY POWER 12V PP12V_G3H I1413 POWER_PHY POWER 12V PP12V_G3H_P3V42 73 6 6 HDD S0 DIDT NO_TEST 6 HDD S0 I1392 6 12V S5 DIDT NO_TEST Input Bus Spacing Voltage NO_TEST POWER 5V REG_V5IN_U7700 72 FET Switched GND 0V AGND_VDDQS3 72 Sensed I1386 VDDQ S3 REG_PHASE_VDDQS3 REG_PHASE_VDDQS3_L REG_BOOT_VDDQS3 REG_BOOT_VDDQS3_RC REG_UGATE_VDDQS3 REG_UGATE_VDDQS3_R REG_LGATE_VDDQS3 REG_SNUBBER_VDDQS3 I1200 POWER_PHY VR_SWITCH 12V TRUE I1267 POWER_PHY VR_SWITCH 12V TRUE I1201 VR_CTL_PHY VR_SWITCH 12V TRUE I1202 VR_CTL_PHY VR_SWITCH 12V TRUE I1203 VR_CTL_PHY VR_SWITCH 12V TRUE I1204 VR_CTL_PHY VR_SWITCH 12V TRUE I1216 VR_CTL_PHY VR_LGATE 12V TRUE I1206 VR_CTL_PHY VR_SWITCH 12V TRUE I1381 POWER_PHY POWER 1.5V I1212 VR_CTL_PHY VR_CTL REG_VDDQS3_VDDQSNS I1207 VR_CTL_PHY VR_CTL I1208 VR_CTL_PHY VR_CTL REG_VDDQS3_VREF REG_VDDQS3_REFIN I1209 VR_CTL_PHY VR_CTL I1215 VR_CTL_PHY VR_CTL REG_VDDQS3_MODE REG_VDDQS3_TRIP I1213 VR_CTL_PHY VR_CTL LDO_DDRVTTS0_SNS 72 TRUE NO_TEST Output Bus Physical DIDT DIDT 71 Local Ground I1325 72 REG_P1V8S0_VFB I1165 71 I1384 POWER_PHY REG_PHASE_P1V8S0 I1166 Input Bus I1211 5V VR_CTL I1155 71 VDDQ S3 (1.5V)/VTT S0 Physical VR_SWITCH VR_CTL_PHY 71 FET Switched I1236 POWER_PHY 1.8V S0 I1185 POWER_PHY Voltage 71 Output Bus I1151 Spacing Physical 71 72 72 POWER_PHY B 72 72 I1402 POWER_PHY POWER 12V PP12V_S0_FBVDDQ 72 I1403 POWER_PHY POWER 12V 72 I1405 POWER_PHY POWER 12V 72 I1404 POWER_PHY POWER 12V PP12V_S0_CPU_P1V05 PP12V_S0_VCCSA PP12V_S0_P1V05 I1388 POWER_PHY POWER 12V I1409 POWER_PHY POWER 12V 72 PPVDDQ_S3_SENSE PP12V_S0_HDD PP12V_S0_BLC 6 6 72 72 72 72 72 Output Bus POWER 1.5V PPVDDQ_S3 POWER_DDR 0.75V PPDDRVTT_S0 POWER_PHY POWER 1.5V PP1V5_S0 I1238 POWER_PHY POWER 1.5V I1380 POWER_PHY POWER 1.5V PPVDDQ_S3_DDR PP1V5_S0_CPU_MEM I1406 POWER_PHY POWER 1.5V PPFBVDDQ_S0_GPU I1210 POWER_PHY I1214 POWER_DDR_PHY FET Switched I1239 A SYNC_MASTER=D8_MARK Sensed SYNC_DATE=02/10/2012 PAGE TITLE Platform VReg Constraints DRAWING NUMBER Apple Inc 051-9504 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED D 7.0.0 R NOTICE OF PROPRIETARY PROPERTY: SIZE REVISION BRANCH prefsb PAGE 130 OF 143 SHEET 106 OF 117 A Thunderbolt TABLE_PHYSICAL_RULE_HEAD LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM TBT_I2C_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD TBT_SPI_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TBTDP_90D * =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF 0.075MM TBT_GEN_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD TABLE_PHYSICAL_RULE_ITEM D Thunderbolt-specific Spacing Definitions Physical Spacing I511 DP_85D DISPLAYPORT DP_85D DISPLAYPORT I512 DP_TBTSNK0_ML DP_85D DISPLAYPORT I514 DP_TBTSNK0_ML DP_85D DISPLAYPORT I513 I516 DP_85D DISPLAYPORT DP_85D DISPLAYPORT I517 DP_TBTSNK0_AUX DP_85D DISPLAYPORT I518 DP_TBTSNK0_AUX DP_85D DISPLAYPORT I515 I519 TABLE_SPACING_RULE_HEAD LAYER LINE-TO-LINE SPACING WEIGHT NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET * * BGA_TBT BGA_TBT_AREA TBT_I2C * * TBT_I2C_ISO I521 I520 TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_RULE_ITEM TBT_I2C_ISO * =2x_DIELECTRIC ? TBT_SPI_ISO * =2x_DIELECTRIC ? DP_TBTSNK1_ML DP_85D DISPLAYPORT DP_85D DISPLAYPORT DP_85D DISPLAYPORT DP_85D DISPLAYPORT I522 DP_85D DISPLAYPORT I524 DP_85D DISPLAYPORT I523 DP_TBTSNK1_ML TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_RULE_ITEM TBTDP_ISO * =5x_DIELECTRIC ? TBT_SPI * * TBT_SPI_ISO I526 DP_TBTSNK1_AUX DP_85D DISPLAYPORT I525 DP_TBTSNK1_AUX DP_85D DISPLAYPORT TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_RULE_ITEM TBTDP_ISO TOP,BOTTOM =7x_DIELECTRIC ? TBT_GEN_ISO * =2X_DIELECTRIC ? BGA_TBT_AREA * 0.075MM ? TBTDP * * TBTDP_ISO TBT_GEN * * TBT_GEN_ISO Electrical Contraint Set DP_TBTSNK0_ML_C_P NO_TEST=TRUE DP_TBTSNK0_ML_C_N NO_TEST=TRUE DP_TBTSNK0_ML_P NO_TEST=TRUE DP_TBTSNK0_ML_N NO_TEST=TRUE DP_TBTSNK0_AUXCH_C_P DP_TBTSNK0_AUXCH_C_N DP_TBTSNK0_AUXCH_P DP_TBTSNK0_AUXCH_N DP_TBTSNK1_ML_C_P DP_TBTSNK1_ML_C_N DP_TBTSNK1_ML_P DP_TBTSNK1_ML_N DP_TBTSNK1_AUXCH_C_P DP_TBTSNK1_AUXCH_C_N DP_TBTSNK1_AUXCH_P DP_TBTSNK1_AUXCH_N 36 81 TABLE_SPACING_RULE_ITEM I603 DP_INTPNL_TBT_ML_MUX DP_85D DISPLAYPORT I604 DP_INTPNL_TBT_ML_MUX DP_85D DISPLAYPORT I686 DP_INTPNL_TBT_ML_MUX DP_85D DISPLAYPORT I687 DP_INTPNL_TBT_ML_MUX DP_85D DISPLAYPORT DP_TBTSRC_ML_P DP_TBTSRC_ML_N DP_TBTSRC_ML_C_P DP_TBTSRC_ML_C_N 36 81 36 36 36 75 36 75 SOURCE: Bill Cornelius’s T29 Routing Notes DP_INTPNL_TBT_AUX_MUX DP_85D DISPLAYPORT I530 DP_INTPNL_TBT_AUX_MUX DP_85D DISPLAYPORT I601 DP_85D DISPLAYPORT I602 DP_85D DISPLAYPORT TBT_A_R2D TBTDP_90D TBTDP I542 TBT_A_R2D TBTDP_90D TBTDP I710 I711 TBT_A_R2D_PINV TBT_A_R2D_PINV TBTDP_90D TBTDP_90D TBTDP TBTDP TBTDP_90D TBTDP TBTDP_90D TBTDP I595 DP_TBTPA_ML1 DP_85D DISPLAYPORT NO_TEST=TRUE 36 81 I596 DP_TBTPA_ML1 DP_85D DISPLAYPORT NO_TEST=TRUE 36 81 I680 DP_TBTPA_ML3 DP_85D DISPLAYPORT NO_TEST=TRUE 36 I681 DP_TBTPA_ML3 DP_85D DISPLAYPORT DISPLAYPORT I543 36 I545 DP_85D 36 75 I547 DP_85D DISPLAYPORT 36 75 I678 DP_85D DISPLAYPORT I679 DP_85D DISPLAYPORT I546 DP_85D DISPLAYPORT I548 DP_85D DISPLAYPORT TBTDP_90D TBTDP NO_TEST=TRUE 36 36 36 NO_TEST=TRUE 84 I549 NO_TEST=TRUE 84 I550 TBTDP_90D TBTDP NO_TEST=TRUE 84 I564 TBT_A_D2R1 TBTDP_90D TBTDP NO_TEST=TRUE 84 I563 TBT_A_D2R1 TBTDP_90D TBTDP I675 TBT_A_D2R0 TBTDP_90D TBTDP DP_TBTSRC_AUXCH_P DP_TBTSRC_AUXCH_N DP_TBTSRC_AUX_C_P DP_TBTSRC_AUX_C_N I674 TBT_A_D2R0 TBTDP_90D TBTDP 84 I599 DP_TBT_A_AUXCH DP_85D DISPLAYPORT 84 I600 DP_TBT_A_AUXCH DP_85D DISPLAYPORT 84 I565 DP_85D DISPLAYPORT 84 I566 DP_85D DISPLAYPORT DisplayPort I648 DP_85D DISPLAYPORT I649 DP_85D DISPLAYPORT DP-specific Physical Rules I650 TBTDP_90D TBTDP I651 TBTDP_90D TBTDP TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP DP_85D * =85_OHM_DIFF =85_OHM_DIFF 0.08MM =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF TABLE_PHYSICAL_RULE_ITEM C Spacing I541 I544 36 * I529 Physical Port A TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_RULE_ITEM TBT/DP Net Properties Electrical Contraint Set TABLE_SPACING_ASSIGNMENT_HEAD SPACING_RULE_SET TBT IC Net Properties Thunderbolt-specific Physical Rules PHYSICAL_RULE_SET DP-specific Spacing Definitions TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE TABLE_SPACING_RULE_ITEM DP_ISO * =6.7X_DIELECTRIC ? SPACING_RULE_SET I531 TBT_I2C_55S TBT_I2C I532 TBT_I2C_55S TBT_I2C I533 TBT_SPI_CLK TBT_I2C_55S TBT_SPI I534 TBT_SPI_MOSI TBT_I2C_55S TBT_SPI I538 TBT_SPI_MISO TBT_I2C_55S TBT_SPI I535 TBT_SPI_CS_L TBT_I2C_55S TBT_SPI I2C_TBTRTR_SCL I2C_TBTRTR_SDA 36 50 * * TBT_SPI_CLK TBT_SPI_MOSI TBT_SPI_MISO TBT_SPI_CS_L MAX LENGTH OF DISPLAYPORT TRACES: INCHES DISPLAYPORT INTRA-PAIR MATCHING SHOULD BE PS INTER-PAIR MATCHING SHOULD BE WITHIN 150 PS DISPLAYPORT AUX CHANNEL INTRA-PAIR MATCHING SHOULD BE PS TBT_GEN_55S TBT_GEN I689 TBT_GEN_55S TBT_GEN I691 TBT_GEN_55S TBT_GEN I690 TBT_GEN_55S TBT_GEN I693 TBT_GEN_55S TBT_GEN I692 TBT_GEN_55S TBT_GEN I695 TBT_GEN_55S TBT_GEN I694 TBT_GEN_55S TBT_GEN I697 TBT_GEN_55S TBT_GEN I696 TBT_GEN_55S TBT_GEN I698 TBT_GEN_55S TBT_GEN I699 TBT_GEN_55S TBT_GEN I701 TBT_GEN_55S TBT_GEN I700 TBT_GEN_55S TBT_GEN I702 TBT_GEN_55S TBT_GEN TBT_GEN_55S I703 B TBT_GEN I704 TBT_GEN_55S TBT_GEN I705 TBT_GEN_55S TBT_GEN I706 TBT_GEN_55S TBT_GEN I707 TBT_GEN_55S TBT_GEN I708 TBT_GEN_55S TBT_GEN I709 TBT_GEN_55S TBT_GEN DP_A_LSX_ML_P DP_A_LSX_ML_N TBT_A_D2R_C_P TBT_A_D2R_C_N TBT_A_D2R_P TBT_A_D2R_N TBT_A_D2R_P TBT_A_D2R_N DP_TBTPA_AUXCH_C_P DP_TBTPA_AUXCH_C_N DP_TBTPA_AUXCH_P DP_TBTPA_AUXCH_N DP_A_AUXCH_DDC_P DP_A_AUXCH_DDC_N TBT_A_D2R1_AUXDDC_P TBT_A_D2R1_AUXDDC_N 36 86 NO_TEST=TRUE 36 86 NO_TEST=TRUE 36 86 NO_TEST=TRUE 36 86 NO_TEST=TRUE 86 NO_TEST=TRUE 86 NO_TEST=TRUE 36 86 NO_TEST=TRUE 36 86 NO_TEST=TRUE 36 86 NO_TEST=TRUE 36 86 NO_TEST=TRUE 86 NO_TEST=TRUE 86 NO_TEST=TRUE 86 NO_TEST=TRUE 86 D 86 86 NO_TEST=TRUE 86 NO_TEST=TRUE 86 NO_TEST=TRUE 36 86 NO_TEST=TRUE 36 86 NO_TEST=TRUE 36 86 NO_TEST=TRUE 36 86 36 86 36 86 86 86 86 86 NO_TEST=TRUE 86 NO_TEST=TRUE 86 C 36 36 Port B 36 36 DP_ISO I688 NO_TEST=TRUE 36 50 TABLE_SPACING_ASSIGNMENT_ITEM DISPLAYPORT TBT_A_R2D_C_P TBT_A_R2D_C_N TBT_A_R2D_C_N TBT_A_R2D_C_P TBT_A_R2D_P TBT_A_R2D_N DP_TBTPA_ML_C_P DP_TBTPA_ML_C_N DP_TBTPA_ML_C_P DP_TBTPA_ML_C_N DP_TBTPA_ML_P DP_TBTPA_ML_N DP_TBTPA_ML_P DP_TBTPA_ML_N TBT_A_CONFIG1_BUF TBT_A_CONFIG2_RC 36 86 36 86 TBT_B_CONFIG1_BUF TBT_B_CONFIG2_RC TBT_A_LSTX TBT_A_LSRX TBT_B_LSTX TBT_B_LSRX DP_TBTSNK0_HPD DP_TBTSNK1_HPD DP_TBTSRC_HPD DP_TBTSNK0_DDC_CLK DP_TBTSNK0_DDC_DATA DP_TBTSNK1_DDC_CLK DP_TBTSNK1_DDC_DATA 36 88 36 88 I652 TBT_B_R2D I653 TBTDP_90D TBTDP TBTDP_90D TBTDP I655 TBT_B_R2D TBTDP_90D TBTDP I654 TBTDP_90D TBTDP I657 DP_TBTPB_ML1 DP_85D DISPLAYPORT I658 DP_TBTPB_ML1 DP_85D DISPLAYPORT I685 DP_TBTPB_ML3 DP_85D DISPLAYPORT I684 DP_TBTPB_ML3 DP_85D DISPLAYPORT I683 DP_85D DISPLAYPORT I682 DP_85D DISPLAYPORT I656 DP_85D DISPLAYPORT I660 DP_85D DISPLAYPORT I659 DP_85D DISPLAYPORT I662 DP_85D DISPLAYPORT 81 85 I661 TBTDP_90D TBTDP 81 85 I663 TBTDP_90D TBTDP 81 85 I665 TBT_B_D2R1 TBTDP_90D TBTDP 81 85 I664 TBT_B_D2R1 TBTDP_90D TBTDP I676 TBT_B_D2R0 TBTDP_90D TBTDP I677 TBT_B_D2R0 TBTDP_90D TBTDP I666 DP_TBT_B_AUXCH DP_85D DISPLAYPORT I667 DP_TBT_B_AUXCH DP_85D DISPLAYPORT I669 DP_85D DISPLAYPORT I670 DP_85D DISPLAYPORT I668 DP_85D DISPLAYPORT I672 DP_85D DISPLAYPORT I671 TBTDP_90D TBTDP I673 TBTDP_90D TBTDP 36 86 36 86 36 88 36 88 36 82 36 82 TBT_B_R2D_C_P TBT_B_R2D_C_N TBT_B_R2D_P TBT_B_R2D_N DP_TBTPB_ML_C_P DP_TBTPB_ML_C_N DP_TBTPB_ML_C_P DP_TBTPB_ML_C_N DP_TBTPB_ML_P DP_TBTPB_ML_N DP_TBTPB_ML_P DP_TBTPB_ML_N DP_B_LSX_ML_P DP_B_LSX_ML_N NO_TEST=TRUE 36 88 NO_TEST=TRUE 36 88 NO_TEST=TRUE 88 NO_TEST=TRUE 88 NO_TEST=TRUE 36 88 NO_TEST=TRUE 36 88 NO_TEST=TRUE 36 88 NO_TEST=TRUE 36 88 NO_TEST=TRUE 88 NO_TEST=TRUE 88 NO_TEST=TRUE 88 NO_TEST=TRUE 88 NO_TEST=TRUE 88 NO_TEST=TRUE 88 NO_TEST=TRUE 88 NO_TEST=TRUE 88 NO_TEST=TRUE 36 88 36 84 VIDEO_ON VIDEO_ON_L BDV_BKL_PWM GPU_LCD_BKLT_PWM LCD_BL_PWM LCD_BL_FILT LCD_BKLT_PWM 74 87 87 48 84 82 84 84 84 84 89 TBT_B_D2R_C_P TBT_B_D2R_C_N TBT_B_D2R_P TBT_B_D2R_N TBT_B_D2R_P TBT_B_D2R_N DP_TBTPB_AUXCH_C_P DP_TBTPB_AUXCH_C_N DP_TBTPB_AUXCH_P DP_TBTPB_AUXCH_N DP_B_AUXCH_DDC_P DP_B_AUXCH_DDC_N TBT_B_D2R1_AUXDDC_P TBT_B_D2R1_AUXDDC_N NO_TEST=TRUE 36 88 NO_TEST=TRUE 36 88 NO_TEST=TRUE 36 88 36 88 36 88 B 88 88 88 88 NO_TEST=TRUE 88 NO_TEST=TRUE 88 *: Only used on hosts supporting T29 video-in DisplayPort Electrical Contraint Set Physical Spacing Graphics Source A I642 DP_INTPNL_EG_ML_MUX DP_85D DISPLAYPORT I643 DP_INTPNL_EG_ML_MUX DP_85D DISPLAYPORT I644 DP_INTPNL_EG_AUX_MUX DP_85D DISPLAYPORT I645 DP_INTPNL_EG_AUX_MUX DP_85D DISPLAYPORT I646 DP_85D DISPLAYPORT I647 DP_85D DISPLAYPORT DP_INT_EG_ML_P DP_INT_EG_ML_N DP_INT_EG_AUX_P DP_INT_EG_AUX_N DP_INT_EG_AUX_C_P DP_INT_EG_AUX_C_N NO_TEST=TRUE 81 84 NO_TEST=TRUE 81 84 NO_TEST=TRUE 81 84 NO_TEST=TRUE 81 84 84 SYNC_MASTER=D8_AARON 84 PAGE TITLE Internal Panel I605 DP_85D DISPLAYPORT I606 DP_85D DISPLAYPORT I607 DP_INTPNL_ML_CONN DP_85D DISPLAYPORT I608 DP_INTPNL_ML_CONN DP_85D DISPLAYPORT I609 DP_INTPNL_AUX_CONN DP_85D DISPLAYPORT I610 DP_INTPNL_AUX_CONN DP_85D DISPLAYPORT DP_INTPNL_ML_C_P DP_INTPNL_ML_C_N DP_INTPNL_ML_P DP_INTPNL_ML_N DP_INTPNL_AUX_P DP_INTPNL_AUX_N NO_TEST=TRUE 84 NO_TEST=TRUE 84 NO_TEST=TRUE 84 87 NO_TEST=TRUE 84 87 DRAWING NUMBER 84 87 84 87 Internal DP SPDIF I611 DP_INT_SPDIF_AUDIO HDA SYNC_DATE=03/13/2012 TBT/DP Constraints 56 87 Apple Inc 051-9504 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED D 7.0.0 R NOTICE OF PROPRIETARY PROPERTY: SIZE REVISION BRANCH prefsb PAGE 131 OF 143 SHEET 107 OF 117 A GDDR5 Electrical Contraint Set GDDR5-specific Physical Rules Memory Address TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET ALLOW ROUTE ON LAYER? LAYER MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM GDDR_45S * =45_OHM_SE =45_OHM_SE =45_OHM_SE =STANDARD =45_OHM_SE GDDR_50S * =50_OHM_SE =50_OHM_SE =50_OHM_SE 12 MM =STANDARD =STANDARD GDDR_80D * =80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF TABLE_PHYSICAL_RULE_ITEM Physical Net Type to Rule Map TABLE_PHYSICAL_ASSIGNMENT_HEAD AREA_TYPE PHYSICAL_RULE_SET GDDR_MA_PHY * GDDR_45S TABLE_PHYSICAL_ASSIGNMENT_ITEM * Electrical Contraint Set Physical Spacing Memory Address I642 GDDR_A0_MA GDDR_MA_PHY GDDR_A_0_MA I643 GDDR_A1_MA GDDR_MA_PHY GDDR_A_1_MA FB_A0_A FB_A1_A NO_TEST=TRUE 77 79 I695 GDDR_B0_MA GDDR_MA_PHY GDDR_B_0_MA NO_TEST=TRUE 77 79 I694 GDDR_B1_MA GDDR_MA_PHY GDDR_B_1_MA Address Dynamic Bus Inv FB_B0_A FB_B1_A NO_TEST=TRUE 77 80 NO_TEST=TRUE 77 80 NO_TEST=TRUE 77 80 NO_TEST=TRUE 77 80 NO_TEST=TRUE 77 80 NO_TEST=TRUE 77 80 NO_TEST=TRUE 77 80 NO_TEST=TRUE 77 80 NO_TEST=TRUE 77 80 NO_TEST=TRUE 77 80 NO_TEST=TRUE 77 80 NO_TEST=TRUE 77 80 NO_TEST=TRUE 77 80 NO_TEST=TRUE 77 80 NO_TEST=TRUE 77 80 NO_TEST=TRUE 77 80 NO_TEST=TRUE 77 80 NO_TEST=TRUE 77 80 NO_TEST=TRUE 77 80 NO_TEST=TRUE 77 80 NO_TEST=TRUE 77 80 NO_TEST=TRUE 77 80 NO_TEST=TRUE 77 80 NO_TEST=TRUE 77 80 NO_TEST=TRUE 77 80 NO_TEST=TRUE 77 80 NO_TEST=TRUE 77 80 NO_TEST=TRUE 77 80 NO_TEST=TRUE 77 80 NO_TEST=TRUE 77 80 NO_TEST=TRUE 77 80 NO_TEST=TRUE 77 80 NO_TEST=TRUE 77 80 NO_TEST=TRUE 77 80 NO_TEST=TRUE 77 80 NO_TEST=TRUE 77 80 NO_TEST=TRUE 77 80 NO_TEST=TRUE 77 80 NO_TEST=TRUE 77 80 NO_TEST=TRUE 77 80 NO_TEST=TRUE 77 80 NO_TEST=TRUE 77 80 NO_TEST=TRUE 77 80 NO_TEST=TRUE 77 80 NO_TEST=TRUE 77 80 NO_TEST=TRUE 77 80 NO_TEST=TRUE 77 80 NO_TEST=TRUE 77 80 NO_TEST=TRUE 77 80 NO_TEST=TRUE 77 80 Address Dynamic Bus Inv I644 GDDR_A0_ADBI GDDR_ADBI_PHY GDDR_A_0_ADBI I645 GDDR_A1_ADBI GDDR_ADBI_PHY GDDR_A_1_ADBI FB_A0_ABI_L FB_A1_ABI_L NO_TEST=TRUE 77 79 I696 GDDR_B0_ADBI GDDR_ADBI_PHY GDDR_B_0_ADBI NO_TEST=TRUE 77 79 I697 GDDR_B1_ADBI GDDR_ADBI_PHY GDDR_B_1_ADBI GDDR_45S FB_B0_ABI_L FB_B1_ABI_L D Control I647 GDDR_A0_CKE GDDR_CTRL_PHY GDDR_A_0_CTRL I648 GDDR_A0_CTRL GDDR_CTRL_PHY GDDR_A_0_CTRL I649 GDDR_A0_CTRL GDDR_CTRL_PHY GDDR_A_0_CTRL I650 GDDR_A0_CTRL GDDR_CTRL_PHY GDDR_A_0_CTRL I651 GDDR_A0_CTRL GDDR_CTRL_PHY GDDR_A_0_CTRL I652 GDDR_A1_CKE GDDR_CTRL_PHY GDDR_A_1_CTRL I654 GDDR_A1_CTRL GDDR_CTRL_PHY GDDR_A_1_CTRL I653 GDDR_A1_CTRL GDDR_CTRL_PHY GDDR_A_1_CTRL I655 GDDR_A1_CTRL GDDR_CTRL_PHY GDDR_A_1_CTRL I656 GDDR_A1_CTRL GDDR_CTRL_PHY GDDR_A_1_CTRL I657 GDDR_A0_CLK GDDR_CLK_PHY GDDR_A_0_CLK I658 GDDR_A0_CLK GDDR_CLK_PHY GDDR_A_0_CLK I660 GDDR_A1_CLK GDDR_CLK_PHY GDDR_A_1_CLK I659 GDDR_A1_CLK GDDR_CLK_PHY GDDR_A_1_CLK TABLE_PHYSICAL_ASSIGNMENT_ITEM GDDR_ADBI_PHY Spacing Control NET_PHYSICAL_TYPE GDDR5 Frame Buffer B =STANDARD TABLE_PHYSICAL_RULE_ITEM D Physical GDDR5 Frame Buffer A FB_A0_CKE_L FB_A0_CS_L FB_A0_WE_L FB_A0_CAS_L FB_A0_RAS_L NO_TEST=TRUE 77 79 I698 GDDR_B0_CKE GDDR_CTRL_PHY GDDR_B_0_CTRL NO_TEST=TRUE 77 79 I701 GDDR_B0_CTRL GDDR_CTRL_PHY GDDR_B_0_CTRL NO_TEST=TRUE 77 79 I700 GDDR_B0_CTRL GDDR_CTRL_PHY GDDR_B_0_CTRL NO_TEST=TRUE 77 79 I702 GDDR_B0_CTRL GDDR_CTRL_PHY GDDR_B_0_CTRL NO_TEST=TRUE 77 79 I703 GDDR_B0_CTRL GDDR_CTRL_PHY GDDR_B_0_CTRL NO_TEST=TRUE 77 79 I704 GDDR_B1_CKE GDDR_CTRL_PHY GDDR_B_1_CTRL NO_TEST=TRUE 77 79 I705 GDDR_B1_CTRL GDDR_CTRL_PHY GDDR_B_1_CTRL NO_TEST=TRUE 77 79 I706 GDDR_B1_CTRL GDDR_CTRL_PHY GDDR_B_1_CTRL NO_TEST=TRUE 77 79 I708 GDDR_B1_CTRL GDDR_CTRL_PHY GDDR_B_1_CTRL NO_TEST=TRUE 77 79 I707 GDDR_B1_CTRL GDDR_CTRL_PHY GDDR_B_1_CTRL NO_TEST=TRUE 77 79 I693 GDDR_B0_CLK GDDR_CLK_PHY GDDR_B_0_CLK NO_TEST=TRUE 77 79 I710 GDDR_B0_CLK GDDR_CLK_PHY GDDR_B_0_CLK NO_TEST=TRUE 77 79 I709 GDDR_B1_CLK GDDR_CLK_PHY GDDR_B_1_CLK NO_TEST=TRUE 77 79 I711 GDDR_B1_CLK GDDR_CLK_PHY GDDR_B_1_CLK NO_TEST=TRUE 77 79 I713 GDDR_B0_DQ_BYTE0 GDDR_DQ_PHY GDDR_B_0_DQ NO_TEST=TRUE 77 79 I712 GDDR_B0_DQ_BYTE1 GDDR_DQ_PHY GDDR_B_0_DQ NO_TEST=TRUE 77 79 I714 GDDR_B0_DQ_BYTE2 GDDR_DQ_PHY GDDR_B_0_DQ NO_TEST=TRUE 77 79 I715 GDDR_B0_DQ_BYTE3 GDDR_DQ_PHY GDDR_B_0_DQ NO_TEST=TRUE 77 79 I716 GDDR_B1_DQ_BYTE0 GDDR_DQ_PHY GDDR_B_1_DQ NO_TEST=TRUE 77 79 I718 GDDR_B1_DQ_BYTE1 GDDR_DQ_PHY GDDR_B_1_DQ NO_TEST=TRUE 77 79 I717 GDDR_B1_DQ_BYTE2 GDDR_DQ_PHY GDDR_B_1_DQ NO_TEST=TRUE 77 79 I719 GDDR_B1_DQ_BYTE3 GDDR_DQ_PHY GDDR_B_1_DQ NO_TEST=TRUE 77 79 I720 GDDR_B0_EDC0 GDDR_EDC_PHY GDDR_B_0_EDC NO_TEST=TRUE 77 79 I721 GDDR_B0_EDC1 GDDR_EDC_PHY GDDR_B_0_EDC NO_TEST=TRUE 77 79 I723 GDDR_B0_EDC2 GDDR_EDC_PHY GDDR_B_0_EDC NO_TEST=TRUE 77 79 I722 GDDR_B0_EDC3 GDDR_EDC_PHY GDDR_B_0_EDC NO_TEST=TRUE 77 79 I725 GDDR_B1_EDC0 GDDR_EDC_PHY GDDR_B_1_EDC NO_TEST=TRUE 77 79 I724 GDDR_B1_EDC1 GDDR_EDC_PHY GDDR_B_1_EDC NO_TEST=TRUE 77 79 I726 GDDR_B1_EDC2 GDDR_EDC_PHY GDDR_B_1_EDC NO_TEST=TRUE 77 79 I727 GDDR_B1_EDC3 GDDR_EDC_PHY GDDR_B_1_EDC NO_TEST=TRUE 77 79 I729 GDDR_B0_DBI0 GDDR_DBI_PHY GDDR_B_0_DBI NO_TEST=TRUE 77 79 I728 GDDR_B0_DBI1 GDDR_DBI_PHY GDDR_B_0_DBI NO_TEST=TRUE 77 79 I730 GDDR_B0_DBI2 GDDR_DBI_PHY GDDR_B_0_DBI NO_TEST=TRUE 77 79 I731 GDDR_B0_DBI3 GDDR_DBI_PHY GDDR_B_0_DBI NO_TEST=TRUE 77 79 I732 GDDR_B1_DBI0 GDDR_DBI_PHY GDDR_B_1_DBI NO_TEST=TRUE 77 79 I733 GDDR_B1_DBI1 GDDR_DBI_PHY GDDR_B_1_DBI NO_TEST=TRUE 77 79 I734 GDDR_B1_DBI2 GDDR_DBI_PHY GDDR_B_1_DBI NO_TEST=TRUE 77 79 I735 GDDR_B1_DBI3 GDDR_DBI_PHY GDDR_B_1_DBI FB_B0_CKE_L FB_B0_CS_L FB_B0_WE_L FB_B0_CAS_L FB_B0_RAS_L TABLE_PHYSICAL_ASSIGNMENT_ITEM GDDR_CTRL_PHY * GDDR_45S GDDR_CLK_PHY * GDDR_80D GDDR_DQ_PHY * GDDR_45S TABLE_PHYSICAL_ASSIGNMENT_ITEM TABLE_PHYSICAL_ASSIGNMENT_ITEM TABLE_PHYSICAL_ASSIGNMENT_ITEM GDDR_EDC_PHY * GDDR_45S FB_A1_CKE_L FB_A1_CS_L FB_A1_WE_L FB_A1_CAS_L FB_A1_RAS_L FB_B1_CKE_L FB_B1_CS_L FB_B1_WE_L FB_B1_CAS_L FB_B1_RAS_L TABLE_PHYSICAL_ASSIGNMENT_ITEM GDDR_DBI_PHY * GDDR_45S GDDR_WCK_PHY * GDDR_80D Clock TABLE_PHYSICAL_ASSIGNMENT_ITEM Main Segment Min Spacing Rules for 4.5 Gbps or Less (AMD Doc# 49919) C Table 5-6/5-7 5-6/5-7 5-6/5-7 5-6/5-7 5-6/5-7 5-6/5-7 5-6/5-7 5-6/5-7 Trace-to-Trace Micro Design 2:1 2:1 2:1 2:1 2:1 2:1 5:1 5:1 3:1 3:1 7:1 7:1 3:1 3:1 5:1 5:1 Strip 2:1 2:1 2:1 5:1 3:1 7:1 3:1 5:1 Isolation Micro Design 5:1 5:1 5:1 5:1 5:1 5:1 5:1 5:1 5:1 5:1 7:1 7:1 5:1 5:1 5:1 5:1 Design 2:1 2:1 2:1 5:1 3:1 7:1 3:1 5:1 Strip 5:1 5:1 5:1 5:1 5:1 7:1 5:1 5:1 Design 5:1 5:1 5:1 5:1 5:1 7:1 5:1 5:1 Comments Memory address (MA) Implented 4.5 Gbps or less rules for K70 Address dynamic bus inversion (ADBI) Control (CTRL) Clock (CLK) Data (DQ) Error detection pins (EDC) Using larger isolation rules, Data dynamic bus inversion (DBI) Forwarded clock (WCK) GDDR5-specific Spacing Definitions TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM GDDR_ISO GDDR_DQ2DQ * ? =3x_DIELECTRIC TABLE_SPACING_RULE_ITEM GDDR_ISO TOP,BOTTOM TABLE_SPACING_RULE_ITEM ? =5x_DIELECTRIC GDDR_DQ2DQ TOP,BOTTOM ? =3x_DIELECTRIC TABLE_SPACING_RULE_ITEM GDDR_MA2MA * =2x_DIELECTRIC ? GDDR_MA2MA TOP,BOTTOM =3X_DIELECTRIC ? GDDR_ADBI2ADBI * =2x_DIELECTRIC ? GDDR_EDC_ISO * =3X_DIELECTRIC ? GDDR_EDC_ISO TOP,BOTTOM =5X_DIELECTRIC ? GDDR_EDC2EDC * =3X_DIELECTRIC ? TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM ? GDDR_CTRL2CTRL =2x_DIELECTRIC ? GDDR_EDC2EDC TOP,BOTTOM =5X_DIELECTRIC ? GDDR_DBI2DBI * =3x_DIELECTRIC ? TABLE_SPACING_RULE_ITEM ? =2x_DIELECTRIC GDDR_DBI2DBI TOP,BOTTOM ? =3x_DIELECTRIC TABLE_SPACING_RULE_ITEM GDDR_CLK2CLK * TABLE_SPACING_RULE_ITEM ? =3X_DIELECTRIC GDDR_WCK2WCK * ? =3X_DIELECTRIC TABLE_SPACING_RULE_ITEM GDDR_CLK2CLK TOP,BOTTOM GDDR_WCK2WCK Constraints (x in {A, B}, y in {0, 1}) Memory Address: MAxy[8:0] TOP,BOTTOM ? =5x_DIELECTRIC Data: DQxy[31:0] TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET GDDR_*_*_MA * * GDDR_ISO NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET GDDR_*_*_DQ * * GDDR_ISO =SAME * GDDR_MA2MA TABLE_SPACING_ASSIGNMENT_ITEM GDDR_*_*_DQ Address Dynamic Bus Inversion: ADBIxy =SAME * GDDR_DQ2DQ Error Detection: EDCxy[3:0] TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET * * NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET GDDR_ISO TABLE_SPACING_ASSIGNMENT_ITEM GDDR_*_*_EDC * * GDDR_EDC_ISO TABLE_SPACING_ASSIGNMENT_ITEM GDDR_*_*_ADBI =SAME * GDDR_A0_DQ_BYTE2 GDDR_DQ_PHY GDDR_A_0_DQ I664 GDDR_A0_DQ_BYTE3 GDDR_DQ_PHY GDDR_A_0_DQ I666 GDDR_A1_DQ_BYTE0 GDDR_DQ_PHY GDDR_A_1_DQ I665 GDDR_A1_DQ_BYTE1 GDDR_DQ_PHY GDDR_A_1_DQ I667 GDDR_A1_DQ_BYTE2 GDDR_DQ_PHY GDDR_A_1_DQ I668 GDDR_A1_DQ_BYTE3 GDDR_DQ_PHY GDDR_A_1_DQ FB_A1_DQ FB_A1_DQ FB_A1_DQ FB_A1_DQ FB_B0_DQ FB_B0_DQ FB_B0_DQ FB_B0_DQ FB_B1_DQ FB_B1_DQ FB_B1_DQ FB_B1_DQ C Error Detection I670 GDDR_A0_EDC0 GDDR_EDC_PHY GDDR_A_0_EDC I669 GDDR_A0_EDC1 GDDR_EDC_PHY GDDR_A_0_EDC I671 GDDR_A0_EDC2 GDDR_EDC_PHY GDDR_A_0_EDC I672 GDDR_A0_EDC3 GDDR_EDC_PHY GDDR_A_0_EDC I673 GDDR_A1_EDC0 GDDR_EDC_PHY GDDR_A_1_EDC I675 GDDR_A1_EDC1 GDDR_EDC_PHY GDDR_A_1_EDC I674 GDDR_A1_EDC2 GDDR_EDC_PHY GDDR_A_1_EDC I676 GDDR_A1_EDC3 GDDR_EDC_PHY GDDR_A_1_EDC FB_A0_EDC FB_A0_EDC FB_A0_EDC FB_A0_EDC FB_B0_EDC FB_B0_EDC FB_B0_EDC FB_B0_EDC FB_A1_EDC FB_A1_EDC FB_A1_EDC FB_A1_EDC FB_B1_EDC FB_B1_EDC FB_B1_EDC FB_B1_EDC Data Dynamic Bus Inv I677 GDDR_A0_DBI0 GDDR_DBI_PHY GDDR_A_0_DBI I678 GDDR_A0_DBI1 GDDR_DBI_PHY GDDR_A_0_DBI I680 GDDR_A0_DBI2 GDDR_DBI_PHY GDDR_A_0_DBI I679 GDDR_A0_DBI3 GDDR_DBI_PHY GDDR_A_0_DBI I682 GDDR_A1_DBI0 GDDR_DBI_PHY GDDR_A_1_DBI I681 GDDR_A1_DBI1 GDDR_DBI_PHY GDDR_A_1_DBI I683 GDDR_A1_DBI2 GDDR_DBI_PHY GDDR_A_1_DBI I684 GDDR_A1_DBI3 GDDR_DBI_PHY GDDR_A_1_DBI FB_A0_DBI_L FB_A0_DBI_L FB_A0_DBI_L FB_A0_DBI_L FB_B0_DBI_L FB_B0_DBI_L FB_B0_DBI_L FB_B0_DBI_L GDDR_ADBI2ADBI FB_A1_DBI_L FB_A1_DBI_L FB_A1_DBI_L FB_A1_DBI_L FB_B1_DBI_L FB_B1_DBI_L FB_B1_DBI_L FB_B1_DBI_L Forwarded Clock I685 GDDR_A0_WCK0 GDDR_WCK_PHY GDDR_A_0_WCK I687 GDDR_A0_WCK0 GDDR_WCK_PHY GDDR_A_0_WCK I686 GDDR_A0_WCK1 GDDR_WCK_PHY GDDR_A_0_WCK I688 GDDR_A0_WCK1 GDDR_WCK_PHY GDDR_A_0_WCK I689 GDDR_A1_WCK0 GDDR_WCK_PHY GDDR_A_1_WCK I690 GDDR_A1_WCK0 GDDR_WCK_PHY GDDR_A_1_WCK I692 GDDR_A1_WCK1 GDDR_WCK_PHY GDDR_A_1_WCK I691 GDDR_A1_WCK1 GDDR_WCK_PHY GDDR_A_1_WCK Physical Spacing I747 CLK_GPU_55S CLK_GPU I748 CLK_GPU_55S CLK_GPU I749 CLK_PCIE_PHY CLK_PCIE I750 I763 CLK_PCIE_PHY CLK_GPU_55S CLK_PCIE CLK_GPU I764 I765 CLK_GPU_55S CLK_GPU_55S CLK_GPU CLK_GPU I766 I767 CLK_GPU_55S CLK_GPU_55S CLK_GPU CLK_GPU I768 CLK_GPU_55S CLK_GPU_55S CLK_GPU CLK_GPU I771 CLK_GPU_55S CLK_GPU_55S CLK_GPU CLK_GPU I772 CLK_GPU_55S CLK_GPU I773 I775 CLK_GPU_55S CLK_GPU_55S CLK_GPU CLK_GPU I774 CLK_GPU_55S CLK_GPU I776 TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 TABLE_SPACING_ASSIGNMENT_ITEM GDDR_*_*_ADBI I662 FB_A0_DQ FB_A0_DQ FB_A0_DQ FB_A0_DQ Forwarded Clock TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM GDDR_*_*_MA GDDR_A_0_DQ TABLE_SPACING_ASSIGNMENT_HEAD TABLE_SPACING_ASSIGNMENT_ITEM B GDDR_A_0_DQ GDDR_DQ_PHY TABLE_SPACING_RULE_ITEM ? =5x_DIELECTRIC GDDR_DQ_PHY GDDR_A0_DQ_BYTE1 Data Dynamic Bus Inv TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM GDDR_CTRL2CTRL TOP,BOTTOM GDDR_A0_DQ_BYTE0 I663 TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM * FB_B1_CLK_P FB_B1_CLK_N Data I661 TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM =2x_DIELECTRIC FB_B0_CLK_P FB_B0_CLK_N TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM GDDR_ADBI2ADBI TOP,BOTTOM Data TABLE_SPACING_RULE_ITEM ? =3X_DIELECTRIC * FB_A1_CLK_P FB_A1_CLK_N Error Detection TABLE_SPACING_RULE_HEAD WEIGHT Clock FB_A0_CLK_P FB_A0_CLK_N FB_A0_WCLK_P FB_A0_WCLK_N FB_A0_WCLK_P FB_A0_WCLK_N FB_A1_WCLK_P FB_A1_WCLK_N FB_A1_WCLK_P FB_A1_WCLK_N NO_TEST=TRUE 77 79 I736 GDDR_B0_WCK0 GDDR_WCK_PHY GDDR_B_0_WCK NO_TEST=TRUE 77 79 I737 GDDR_B0_WCK0 GDDR_WCK_PHY GDDR_B_0_WCK NO_TEST=TRUE 77 79 I739 GDDR_B0_WCK1 GDDR_WCK_PHY GDDR_B_0_WCK NO_TEST=TRUE 77 79 I738 GDDR_B0_WCK1 GDDR_WCK_PHY GDDR_B_0_WCK NO_TEST=TRUE 77 79 I740 GDDR_B1_WCK0 GDDR_WCK_PHY GDDR_B_1_WCK NO_TEST=TRUE 77 79 I741 GDDR_B1_WCK0 GDDR_WCK_PHY GDDR_B_1_WCK NO_TEST=TRUE 77 79 I743 GDDR_B1_WCK1 GDDR_WCK_PHY GDDR_B_1_WCK NO_TEST=TRUE 77 79 I742 GDDR_B1_WCK1 GDDR_WCK_PHY GDDR_B_1_WCK Physical Spacing GDDR_50S GDDR_50S GDDR_50S GDDR_50S GDDR_50S GDDR_50S GDDR_50S GDDR_50S GDDR_CTRL GDDR_CTRL GDDR_CTRL GDDR_CTRL GDDR_CTRL GDDR_CTRL GDDR_CTRL GDDR_CTRL FB_B0_WCLK_P FB_B0_WCLK_N FB_B0_WCLK_P FB_B0_WCLK_N FB_B1_WCLK_P FB_B1_WCLK_N FB_B1_WCLK_P FB_B1_WCLK_N B TABLE_SPACING_ASSIGNMENT_ITEM GDDR_*_*_EDC =SAME * GDDR_EDC2EDC GPU Control: Reset, CKExy, CSxy, WExy, RASxy, CASxy Data Dynamic Bus Inversion: DDBIxy[3:0] TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET GDDR_CTRL * * GDDR_ISO GDDR_*_*_CTRL * * GDDR_ISO GDDR_*_*_CTRL =SAME * GDDR_CTRL2CTRL Electrical Contraint Set TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE Clocks TABLE_SPACING_ASSIGNMENT_ITEM GDDR_*_*_DBI * * GDDR_ISO GDDR_*_*_DBI =SAME * GDDR_DBI2DBI TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM Forwarded Clock: WCKxy[1:0] TABLE_SPACING_ASSIGNMENT_HEAD Clock: CKxy NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE TABLE_SPACING_ASSIGNMENT_ITEM GDDR_*_*_WCK SPACING_RULE_SET * * GDDR_ISO TABLE_SPACING_ASSIGNMENT_ITEM GDDR_*_*_CLK * * GDDR_ISO GDDR_*_*_CLK =SAME * GDDR_CLK2CLK TABLE_SPACING_ASSIGNMENT_ITEM GDDR_*_*_WCK =SAME * GDDR_WCK2WCK I769 TABLE_SPACING_ASSIGNMENT_ITEM A Frame Buffer Reset SPACING_RULE_SET TABLE_SPACING_ASSIGNMENT_ITEM I770 GPU GPU-specific Physical Rules CLK_GPU_55S CLK_GPU I564 SMB_PHY SMB I563 SMB_PHY SMB I753 SMB_PHY SMB I754 SMB_PHY SMB PEX_TSTCLK_O_PL PEX_TSTCLK_O_NG GPU_TESTMODE GPU_PEX_TERMP FB_A0_CK_MID FB_A1_CK_MID FB_B0_CK_MID FB_B1_CK_MID FB_C0_CK_MID FB_C1_CK_MID FB_D0_CK_MID FB_D1_CK_MID GPU_JTAG_TCK GPU_ROM_SCLK GPU_ROM_SCLK_R GPU_XTALOUT GPU_OSC_27M_XTALOUT GPU_OSC_27M_XTALIN Electrical Contraint Set 75 75 Reset 81 I744 75 I755 I756 NO_TEST=TRUE 79 NO_TEST=TRUE 79 NO_TEST=TRUE 80 NO_TEST=TRUE 80 I757 I758 I759 I760 NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE I761 GDDR_A0_RESET GDDR_A1_RESET GDDR_B0_RESET GDDR_B1_RESET GDDR_C0_RESET GDDR_C1_RESET GDDR_D0_RESET GDDR_D1_RESET FB_A0_RESET_L FB_A1_RESET_L FB_B0_RESET_L FB_B1_RESET_L FB_C0_RESET_L FB_C1_RESET_L FB_D0_RESET_L FB_D1_RESET_L 77 79 77 79 77 80 77 80 ULTIMATE ONLY ULTIMATE ONLY NO_TEST=TRUE 78 81 81 82 82 SYNC_MASTER=D8_AARON SYNC_DATE=03/13/2012 PAGE TITLE GDDR5/GPU Constraints 81 82 81 82 DRAWING NUMBER TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM CLK_GPU_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD GPU-specific Spacing Definitions TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE TABLE_SPACING_RULE_ITEM CLK_GPU_ISO * =4:1_SPACING ? * * CLK_GPU_ISO GPU_SMB_CLK GPU_SMB_DAT GPU_SMB_CLK_R GPU_SMB_DAT_R I599 PCIE_50S COMP_PCIE I600 I762 PCIE_50S PCIE_50S COMP_PCIE COMP_PCIE FB_CAL_PD_VDDQ FB_CAL_PU_GND FB_CAL_TERM_GND Apple Inc 81 82 81 82 051-9504 NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED 77 77 77 D 7.0.0 R 50 82 SIZE REVISION 50 82 PCIe Compensation TABLE_SPACING_ASSIGNMENT_ITEM CLK_GPU SPACING_RULE_SET SMB BRANCH prefsb PAGE 132 OF 143 SHEET 108 OF 117 A Backlight Controller Physical BLC-specific Physical Rules LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM BLC_P6MM * Y 0.600 MM 0.100 MM =STANDARD 3.0 MM =STANDARD TABLE_PHYSICAL_RULE_ITEM BLC_P3MM * Y 0.300 MM 0.100 MM =STANDARD 3.0 MM =STANDARD Physical Net Type to Rule Map D TABLE_PHYSICAL_ASSIGNMENT_HEAD NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET POWER_BLC * BLC_P6MM POWER_BLC_RET * BLC_P3MM TABLE_PHYSICAL_ASSIGNMENT_ITEM TABLE_PHYSICAL_ASSIGNMENT_ITEM * Voltage I750 POWER_PHY POWER 12V I772 I806 I807 POWER_PHY POWER_PHY POWER_PHY POWER POWER POWER 12V 14V 3.3V I867 POWER_PHY POWER 3.3V I809 POWER_PHY POWER 3.3V I864 POWER_PHY POWER 3.3V I841 POWER_PHY POWER 8V I810 POWER_PHY POWER 8V I847 POWER_PHY POWER 8V I862 POWER_PHY POWER 14V I863 POWER_PHY POWER 12V I865 POWER_PHY POWER_PHY POWER POWER 5V 12V TABLE_PHYSICAL_ASSIGNMENT_ITEM BLC_CTL_PHY Spacing DIDT BLC_P3MM I866 BLC-specific Spacing Definitions BLC High Voltage Output Constraints BLC High Voltage Output TABLE_SPACING_RULE_HEAD LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE TABLE_SPACING_RULE_ITEM BLC_HV_ISO * 1000 1.00MM SPACING_RULE_SET PP12V_S0_BLC_VIN2 PP12V_S0_BLC_VINP PRE_REG_OUT BLC_P3V3S BLC_P3V3_REF BLC_P3V3 PP3V3_S0_BLC_R SPTX_VIN PP8V_BLC BLC_VIN2 BOOST_FET_DRAIN BOOST_VDD PP5V_S0_BLC_R PP12V_S0_BLC_F BLC_HV BLC_HV BLC Baddies BLC_HV * BLC_CTL_ISO * * TABLE_SPACING_RULE_HEAD LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE TABLE_SPACING_RULE_ITEM PHASE_ISO C * 2000 =8:1_SPACING PHASE_SW2SW * =1:1_SPACING ? PHASE_SW2PWR * =2:1_SPACING ? BLC_PHASE * * ? * PHASE_SW2SW BLC_PHASE POWER * PHASE_SW2PWR TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM GND * PHASE_SW2GND BLC Control TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT BLC_CTL_ISO * =3:1_SPACING ? NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET BLC_CTL * * BLC_CTL_ISO TABLE_SPACING_ASSIGNMENT_ITEM BKLT MISCELLANEOUS Electrical Contraint Set Physical Spacing SPI I564 SMB_PHY SMB I563 SMB_PHY SMB I812 SMB_PHY SMB I811 SMB_PHY SMB SMB_PCH_BLC_SCL SMB_PCH_BLC_SDA SMB_TCON_BLC_SCL SMB_TCON_BLC_SDA 50 89 50 89 50 89 50 89 12M REFERENCE CRYSTAL I842 CLK_XTAL XTAL I843 CLK_XTAL XTAL I844 CLK_XTAL XTAL I845 CLK_PCH_50S CLK_PCH I846 CLK_PCH_50S CLK_PCH 0V BLC_PHASE 0V I805 BLC_CTL_PHY BLC_PHASE 0V I816 GND_PHY GND 0V 89 90 89 91 89 91 89 D 90 89 90 90 91 89 89 89 90 91 91 BLC_GND_1 BLC_GND_2 BLC_GND_3 AGND_BLC 90 91 90 91 90 91 90 91 Backlight LED_DRIVER_GATE1 LED_DRIVER_GATE1_R LED_DRIVER_GATE2 LED_DRIVER_GATE2_R LED_DRIVER_GATE3 LED_DRIVER_GATE3_R I755 BLC_CTL_PHY BLC_PHASE I756 BLC_CTL_PHY BLC_PHASE I798 BLC_CTL_PHY BLC_PHASE I797 BLC_CTL_PHY BLC_PHASE I800 BLC_CTL_PHY BLC_PHASE I799 BLC_CTL_PHY BLC_PHASE I795 BLC_CTL_PHY BLC_CTL I794 BLC_CTL_PHY BLC_CTL I796 BLC_CTL_PHY BLC_CTL I801 BLC_CTL_PHY BLC_CTL I803 BLC_CTL_PHY BLC_CTL I802 BLC_CTL_PHY BLC_CTL I828 BLC_CTL_PHY BLC_CTL I827 BLC_CTL_PHY BLC_CTL I826 BLC_CTL_PHY BLC_CTL I833 BLC_CTL_PHY BLC_HV I832 BLC_CTL_PHY BLC_HV 80V I831 BLC_CTL_PHY BLC_HV 80V I830 BLC_CTL_PHY BLC_CTL 80V I834 BLC_CTL_PHY BLC_CTL 80V I829 BLC_CTL_PHY BLC_CTL 80V I835 BLC_CTL_PHY BLC_CTL I836 BLC_CTL_PHY BLC_CTL I837 BLC_CTL_PHY BLC_CTL I840 BLC_CTL_PHY BLC_CTL I839 BLC_CTL_PHY BLC_CTL I838 BLC_CTL_PHY BLC_CTL I819 BLC_CTL_PHY BLC_CTL I818 BLC_CTL_PHY BLC_CTL I817 I758 BLC_CTL_PHY BLC_CTL_PHY BLC_CTL BLC_CTL I759 BLC_CTL_PHY BLC_CTL I781 BLC_CTL_PHY BLC_CTL I822 BLC_CTL_PHY BLC_CTL I821 BLC_CTL_PHY BLC_CTL I820 BLC_CTL_PHY BLC_CTL I849 BLC_CTL_PHY BLC_CTL I848 BLC_CTL_PHY BLC_CTL I850 I851 BLC_CTL_PHY BLC_CTL_PHY BLC_CTL BLC_CTL I852 BLC_CTL_PHY BLC_CTL I853 BLC_CTL_PHY BLC_CTL 90 90 90 90 90 90 LED_DRVR_CS_RC_1 LED_DRVR_CS_RC_2 LED_DRVR_CS_RC_3 90 90 90 LED_DRIVER_CS1 LED_DRIVER_CS2 LED_DRIVER_CS3 90 90 90 LED_DRVR_CS_C1 LED_DRVR_CS_C2 LED_DRVR_CS_C3 LED_DRIVER_FDBK_R_1 LED_DRIVER_FDBK_R_2 LED_DRIVER_FDBK_R_3 80V BLC_MCU_XTAL_IN BLC_MCU_XTAL_OUT BLC_MCU_XTAL_OUT_R 89 89 89 90 I856 BLC_CTL_PHY BLC_CTL I855 BLC_CTL_PHY BLC_CTL I854 BLC_CTL_PHY BLC_CTL I857 BLC_CTL_PHY BLC_CTL I860 BLC_CTL_PHY BLC_CTL TRUE I861 BLC_CTL_PHY BLC_CTL TRUE I859 BLC_CTL_PHY BLC_CTL I858 BLC_CTL_PHY BLC_CTL C 90 90 90 90 90 LED_DRIVER_FDBK1 LED_DRIVER_FDBK2 LED_DRIVER_FDBK3 BLC_PWM_1_R BLC_PWM_2_R BLC_PWM_3_R BLC_PWM_1 BLC_PWM_2 BLC_PWM_3 LED_DRIVER_REF1 LED_DRIVER_REF2 LED_DRIVER_REF3 LED_DRIVER_COMP1 LED_DRIVER_COMP2 LED_DRIVER_COMP3 BCOMP1 BCOMP2 BCOMP3 LED_DRIVER_FLT1 LED_DRIVER_FLT2 LED_DRIVER_FLT3 LED_FLT_R_1 LED_FLT_R_2 LED_FLT_R_3 TABLE_SPACING_ASSIGNMENT_HEAD TABLE_SPACING_RULE_ITEM B PHASE_ISO BLC_PHASE BLC_PHASE BLC Control SPACING_RULE_SET BLC_PHASE TABLE_SPACING_RULE_ITEM =2:1_SPACING BLC_PHASE BLC_CTL_PHY TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_RULE_ITEM * BLC_CTL_PHY 89 91 TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_RULE_ITEM PHASE_SW2GND BLC_HV_ISO BLC Baddies LAYER I751 I804 89 90 91 TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM SPACING_RULE_SET NO_TEST Local Ground SPACING_RULE_SET Input Bus TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET 90 90 90 89 90 89 90 89 90 90 91 90 91 90 91 90 91 90 91 90 91 90 90 90 90 90 90 90 90 90 90 B 90 90 PRE_REG_OUT_R BOOST_FB BOOST_COMP BOOST_COMP_C BOOST_GDRV BOOST_GDRV_R BOOST_ISNS BOOST_ISNS_R 89 89 89 89 89 89 89 89 250K REFERENCE CLOCKS STRCLK_R1 LED_DRVR_CLK 89 90 90 I752 BLC_CTL_PHY BLC_HV 80V I753 BLC_CTL_PHY BLC_HV 80V I754 BLC_CTL_PHY BLC_HV 80V LED_DRVR_DRAIN_1 LED_DRVR_DRAIN_2 LED_DRVR_DRAIN_3 90 90 90 OUTPUT BUS A I789 POWER_BLC_RET BLC_HV 80V I788 POWER_BLC_RET BLC_HV 80V I790 POWER_BLC_RET BLC_HV I791 POWER_BLC_RET BLC_HV 80V 80V I792 POWER_BLC_RET BLC_HV 80V I793 POWER_BLC_RET BLC_HV 80V I783 POWER_BLC_RET BLC_HV 80V I782 POWER_BLC_RET BLC_HV 80V I784 POWER_BLC_RET BLC_HV 80V I785 POWER_BLC_RET BLC_HV 80V I786 POWER_BLC_RET BLC_HV I787 POWER_BLC_RET BLC_HV 80V 80V I825 POWER_BLC BLC_HV 80V I824 POWER_BLC BLC_HV 80V I823 POWER_BLC BLC_HV 80V IS1_BLC_F IS2_BLC_F IS3_BLC_F IS1_BLC IS2_BLC IS3_BLC 91 91 91 90 91 90 91 90 91 BLC_LED_P_1 BLC_LED_N_1 BLC_LED_P_2 BLC_LED_N_2 BLC_LED_P_3 BLC_LED_N_3 BLC_VOUT1 BLC_VOUT2 BLC_VOUT3 91 SYNC_MASTER=D8_MLB PAGE TITLE 91 91 DRAWING NUMBER 91 Apple Inc 91 90 91 90 91 051-9504 NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED SIZE D REVISION 7.0.0 R 91 90 91 SYNC_DATE=12/19/2011 BLC Constraints BRANCH prefsb PAGE 134 OF 143 SHEET 109 OF 117 A GPU CORE PHASES Electrical Contraint Set GPU CORE CONTROLLER Physical Spacing Voltage DIDT NO_TEST Electrical Contraint Set Physical Spacing Voltage DIDT NO_TEST Input Bus I836 POWER_PHY POWER 12V I1136 POWER_PHY POWER 5V PP12V_S0_GPUCORE_FLT PP5V_S0_GPU_VCORE_VCC ISL6334 92 93 94 I1424 VR_CTL_PHY VR_CTL I1368 VR_CTL_PHY VR_CTL I1367 VR_CTL_PHY VR_CTL I1369 VR_CTL_PHY VR_CTL I1370 VR_CTL_PHY VR_CTL I1371 VR_CTL_PHY VR_CTL I1372 VR_CTL_PHY VR_CTL 93 I1373 VR_CTL_PHY VR_CTL 93 I1374 VR_CTL_PHY VR_CTL I1375 VR_CTL_PHY VR_CTL I1440 VR_CTL_PHY VR_CTL 92 Local Ground GND_PHY I1264 D GND AGND_GPU 0V Phase I883 POWER_PHY POWER 12V I1496 POWER_PHY POWER 12V I884 VR_CTL_PHY VR_CTL I885 VR_CTL_PHY VR_CTL I887 POWER_PHY VR_SWITCH VR_CTL_PHY I888 I890 VR_CTL_PHY I889 I891 I893 I894 ISNS_GPU_CORE REG_PWM_GPUCORE_1 VR_GPU_PWM1_R 12V 12V TRUE TRUE 12V TRUE VR_CTL_PHY VR_SWITCH 12V TRUE VR_CTL_PHY VR_LGATE 12V TRUE VR_SWITCH POWER_PHY POWER SNS_DIFF_PHY SENSE I895 ISNS_GPU_CORE SNS_DIFF_PHY SENSE I1466 ISNS_GPU_CORE SNS_DIFF_PHY SENSE I1467 ISNS_GPU_CORE SNS_DIFF_PHY SENSE I1468 REG_LVCC_UB510 REG_UVCC_UB510 VR_SWITCH VR_CTL_PHY I892 VR_SWITCH ISNS_GPU_CORE 12V TRUE TRUE TRUE REG_ISEN_GCORE_1_P REG_ISEN_GCORE_1_N VR_GPU_ISNS1_R_P VR_GPU_ISNS1_R_N VR_GPU_ISNS1_RR_2 Phase C POWER_PHY POWER I1140 VR_CTL_PHY VR_CTL I1141 VR_CTL_PHY VR_CTL POWER_PHY I1142 REG_LVCC_UB530 REG_PWM_GPUCORE_2 VR_GPU_PWM2_R 12V 12V TRUE I1143 VR_CTL_PHY VR_SWITCH 12V TRUE I1145 VR_CTL_PHY VR_SWITCH 12V TRUE I1144 VR_CTL_PHY VR_SWITCH 12V TRUE I1147 VR_CTL_PHY VR_LGATE 12V TRUE I1146 VR_CTL_PHY VR_SWITCH 12V TRUE I1149 POWER_PHY POWER 0.9V I1148 ISNS_GPU_CORE SNS_DIFF_PHY SENSE I1151 ISNS_GPU_CORE SNS_DIFF_PHY SENSE I1469 ISNS_GPU_CORE SNS_DIFF_PHY SENSE I1471 ISNS_GPU_CORE SNS_DIFF_PHY SENSE I1470 ISNS_GPU_CORE Phase TRUE REG_ISEN_GCORE_2_P REG_ISEN_GCORE_2_N VR_GPU_ISNS2_R_P VR_GPU_ISNS2_R_N VR_GPU_ISNS2_RR_2 SENSE REG_VCC_UB550 REG_UVCC_UB550 REG_LVCC_UB550 REG_PWM_GPUCORE_3 VR_GPU_PWM3_R I1498 POWER POWER 12V 12V I1152 POWER_PHY POWER 12V I1156 VR_CTL_PHY VR_CTL I1155 VR_CTL_PHY VR_CTL I1158 POWER_PHY VR_SWITCH 12V TRUE I1157 VR_CTL_PHY VR_SWITCH 12V TRUE I1159 VR_CTL_PHY VR_SWITCH 12V TRUE I1160 VR_CTL_PHY VR_SWITCH 12V TRUE I1161 VR_CTL_PHY VR_LGATE 12V TRUE I1162 VR_CTL_PHY VR_SWITCH 12V TRUE 0.9V POWER_PHY POWER I1164 ISNS_GPU_CORE SNS_DIFF_PHY SENSE I1165 ISNS_GPU_CORE SNS_DIFF_PHY SENSE I1472 ISNS_GPU_CORE SNS_DIFF_PHY SENSE I1473 ISNS_GPU_CORE SNS_DIFF_PHY SENSE I1474 ISNS_GPU_CORE I1163 TRUE REG_PHASE_GPUCORE_2 REG_BOOT_GPUCORE_2 REG_BOOT_GPUCORE_2_RC REG_UGATE_GPUCORE_2 REG_LGATE_GPUCORE_2 REG_SNUBBER_GPUCORE_2 PPGPUCORE_S0_SENSE_2 POWER_PHY POWER_PHY I1497 B VR_SWITCH REG_PHASE_GPUCORE_1 REG_BOOT_GPUCORE_1 REG_BOOT_GPUCORE_1_RC REG_UGATE_GPUCORE_1 REG_LGATE_GPUCORE_1 REG_SNUBBER_GPUCORE_1 PPGPUCORE_S0_SENSE_1 0.9V SENSE I1138 92 TRUE TRUE REG_PHASE_GPUCORE_3 REG_BOOT_GPUCORE_3 REG_BOOT_GPUCORE_3_RC REG_UGATE_GPUCORE_3 REG_LGATE_GPUCORE_3 REG_SNUBBER_GPUCORE_3 PPGPUCORE_S0_SENSE_3 REG_ISEN_GCORE_3_P REG_ISEN_GCORE_3_N VR_GPU_ISNS3_R_P VR_GPU_ISNS3_R_N VR_GPU_ISNS3_RR_2 SENSE 92 93 92 I1441 VR_CTL I1442 VR_CTL 93 I1444 VR_CTL 93 I1443 VR_CTL 93 I1445 VR_CTL_PHY VR_CTL 93 I1446 VR_CTL_PHY VR_CTL I1448 VR_CTL_PHY VR_CTL 93 93 VR_CTL I1447 93 VR_CTL I1449 92 93 I1480 VR_CTL_PHY VR_CTL 92 93 I1481 VR_CTL_PHY VR_CTL 92 I1482 VR_CTL_PHY VR_CTL 92 I1495 VR_CTL_PHY VR_CTL I1485 VR_CTL_PHY VR_CTL I1484 VR_CTL_PHY VR_CTL I1486 VR_CTL_PHY VR_CTL 92 VR_CTL I1488 93 VR_CTL I1489 92 93 I1490 92 VR_GPU_COMP VR_GPU_COMP_R VR_GPU_COMP_RC VR_GPU_FB VR_GPU_FB_R VR_GPU_VDIFF VR_VDF_R1 VR_VDF_R2 VR_GPU_TCOMP VR_GPU_OFS VR_GPU_FS VR_GPU_EN_VTT PM_EN_REG_GPUCORE_S0 PM_PGOOD_REG_GPUCORE_S0 GPU_PSI_L VR_GPU_IOUT VR_GPU_IMON VR_GPU_FAN VR_GPU_VRDHOT VR_GPU_EN_PWR VR_GPU_SS VR_GPU_DAC VR_GPU_REF VR_GPU_TM VR_GPU_IMON VR_GPU_FAN VR_GPU_VRHOT GPU_PSI_R GPU_PSI_L_R VR_GPU_IMON_R VSNS_GPU_VDD VSNS_GPU_VSS VR_GPU_VSEN VR_GPU_RGND VR_CTL_PHY VR_CTL I1376 VSNS_GPU_VDD SNS_DIFF_PHY SENSE 93 I1377 VSNS_GPU_VSS SNS_DIFF_PHY SENSE 93 I1378 SNS_DIFF_PHY SENSE 93 I1379 SNS_DIFF_PHY SENSE 92 92 92 92 92 D 92 92 92 92 92 92 92 64 92 64 92 82 92 51 92 110 92 110 92 92 92 92 92 51 92 110 92 110 92 78 92 78 92 C 92 92 93 93 GPU VIDS 93 I1425 VR_VID I1431 VR_VID 93 I1432 VR_VID 92 93 I1426 VR_VID 92 93 I1427 VR_VID 92 I1428 VR_VID 92 I1429 VR_VID 92 I1430 VR_VID I1434 VR_VID I1433 VR_VID I1438 VR_VID 93 93 93 92 93 92 93 93 I1439 VR_VID I1437 VR_VID I1435 VR_VID I1436 VR_VID REG_GPUCORE_VID7 REG_GPUCORE_VID6 REG_GPUCORE_VID5 REG_GPUCORE_VID4 REG_GPUCORE_VID3 REG_GPUCORE_VID2 REG_GPUCORE_VID1 REG_GPUCORE_VID0 GPU_VCORE_VID6 GPU_VCORE_VID5 GPU_VCORE_VID4 GPU_VCORE_VID3 GPU_VCORE_VID2 GPU_VCORE_VID1 GPU_VCORE_VID0 92 78 92 78 92 78 92 78 92 78 92 78 92 92 78 82 78 82 78 82 78 82 78 82 78 82 93 93 Output Bus 93 I1423 POWER_PHY POWER PPVCORE_S0_GPU 0.9V 93 93 B 92 93 GPU FBVDDQ 92 93 92 92 Electrical Contraint Set Physical Spacing Voltage DIDT NO_TEST I1450 POWER_PHY POWER 5V I1451 POWER_PHY POWER 5V REG_VCC_UB750 REG_PVCC_UB750 GND_PHY GND 0V AGND_FBVDDQ 92 Input Bus Phase REG_LVCC_UB650 REG_PWM_GPUCORE_4 VR_GPU_PWM4_R I1167 POWER_PHY POWER 12V I1171 VR_CTL_PHY VR_CTL I1170 VR_CTL_PHY VR_CTL I1173 POWER_PHY VR_SWITCH 12V I1172 VR_CTL_PHY VR_SWITCH 12V TRUE I1174 VR_CTL_PHY VR_SWITCH 12V TRUE I1175 VR_CTL_PHY VR_SWITCH 12V TRUE I1176 VR_CTL_PHY VR_LGATE 12V TRUE I1177 VR_CTL_PHY VR_SWITCH 12V TRUE I1178 POWER_PHY POWER 0.9V 94 92 94 I1475 ISNS_GPU_CORE SNS_DIFF_PHY SENSE I1477 ISNS_GPU_CORE SNS_DIFF_PHY SENSE I1476 ISNS_GPU_CORE SNS_DIFF_PHY SENSE I1478 ISNS_GPU_CORE SNS_DIFF_PHY SENSE I1479 ISNS_GPU_CORE TRUE TRUE REG_PHASE_GPUCORE_4 REG_BOOT_GPUCORE_4 REG_BOOT_GPUCORE_4_RC REG_UGATE_GPUCORE_4 REG_LGATE_GPUCORE_4 REG_SNUBBER_GPUCORE_4 PPGPUCORE_S0_SENSE_4 REG_ISEN_GCORE_4_P REG_ISEN_GCORE_4_N VR_GPU_ISNS4_R_P VR_GPU_ISNS4_R_N VR_GPU_ISNS4_RR_2 SENSE 95 Local Ground 92 I1452 TRUE 95 95 94 94 FBVDDQ 94 I1453 POWER_PHY VR_SWITCH 12V TRUE 94 I1454 VR_CTL_PHY VR_SWITCH 12V TRUE 94 I1455 VR_CTL_PHY VR_SWITCH 12V TRUE 94 I1456 VR_CTL_PHY VR_SWITCH 12V TRUE 94 I1457 VR_CTL_PHY VR_SWITCH 12V TRUE I1460 VR_CTL_PHY VR_LGATE 12V TRUE I1459 VR_CTL_PHY VR_SWITCH 12V TRUE 92 94 92 94 92 92 A TRUE REG_UGATE_FBVDDQ_R REG_LGATE_FBVDDQ REG_SNUBBER_FBVDDQ I1491 ISNS_GPU_CORE SNS_DIFF_PHY SENSE I1492 ISNS_GPU_CORE SNS_DIFF_PHY SENSE I1493 ISNS_GPU_CORE SNS_DIFF_PHY SENSE I1494 ISNS_GPU_CORE SNS_DIFF_PHY SENSE VSNS_FBVDDQ VSNS_FBVDDQ_P VSNS_FBVDDQ_N SNS_FBVDDQ_XW_P SNS_FBVDDQ_XW_N SENSE I1487 92 TRUE REG_PHASE_FBVDDQ REG_BOOT_FBVDDQ REG_BOOT_FBVDDQ_RC REG_UGATE_FBVDDQ SENSE FBVDDQ_SENSE_R I1463 VR_CTL_PHY VR_CTL I1464 VR_CTL_PHY VR_CTL REG_FBVDDQ_OCSET REG_FBVDDQ_VO REG_FBVDDQ_FB REG_FBVDDQ_RTN I1458 I1461 SENSE I1462 SENSE 95 95 95 95 95 95 78 95 78 95 95 95 SYNC_MASTER=D8_MARK GPU VREG CONSTRAINTS DRAWING NUMBER 95 Apple Inc 95 95 051-9504 NOTICE OF PROPRIETARY PROPERTY: POWER_PHY POWER 1.5V PP1V5R1V35_S0_GPU_REG 95 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED SIZE D REVISION 7.0.0 R Output Bus I1465 SYNC_DATE=02/10/2012 PAGE TITLE BRANCH prefsb PAGE 135 OF 143 SHEET 110 OF 117 A D D VENI, VIDI, VICI! Electrical Contraint Set Ethernet I474 I475 ENET_MDI_NORM ENET_MDI_NORM I476 I477 Physical Spacing ENET_DIFF_PHY ENET_DIFF ENET_DIFF_PHY ENET_DIFF ENET_DIFF_PHY ENET_TRANS ENET_DIFF_PHY ENET_TRANS ENET_RDAC SD_PHY SD NO_TEST=TRUE 39 I480 SD_PHY SD I499 SD_PHY SD ENET_CR_DATA SDCONN_DATA SDCONN_DATA_R ENET_SD_CMD SDCONN_CMD SDCONN_CMD_R ENET_SD_CLK SDCONN_CLK SDCONN_CLK_R NO_TEST=TRUE 39 I478 ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP ENET_50S * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD ENET_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF I479 TABLE_PHYSICAL_RULE_ITEM SD_DATA TABLE_PHYSICAL_RULE_ITEM =100_OHM_DIFF =100_OHM_DIFF =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD SD_PHY SD I482 SD_PHY SD I500 SD_PHY SD I481 TABLE_PHYSICAL_RULE_ITEM =STANDARD TABLE_PHYSICAL_ASSIGNMENT_HEAD NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET ENET_COMP_PHY * ENET_50S ENET_DIFF_PHY * ENET_100D TABLE_PHYSICAL_ASSIGNMENT_ITEM TABLE_PHYSICAL_ASSIGNMENT_ITEM TABLE_PHYSICAL_ASSIGNMENT_ITEM * SD_50S Constraints Ethernet TABLE_SPACING_RULE_HEAD LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE TABLE_SPACING_RULE_ITEM ENET_DIFF_ISO * =6:1_SPACING ? ENET_DIFF2DIFF * =3:1_SPACING ? 1.27 MM * * ENET_DIFF_ISO ENET_DIFF ENET_DIFF * ENET_DIFF2DIFF * 40 39 C SD_PHY SD SD_PHY SD I486 =4:1_SPACING SD_CLK SD_PHY SD I485 SD_PHY SD I488 SD_PHY SD ENET_MEDIA_SENSE ENET_SD_DETECT_L I487 SD_PHY SD SDCONN_WP I490 SPI_50S SPI I489 SPI_50S SPI I492 SPI_50S SPI I491 SPI_50S SPI ENET_SCLK ENET_MISO ENET_MOSI ENET_CS_L 39 41 NO_TEST=TRUE 41 NO_TEST=TRUE 39 NO_TEST=TRUE 39 41 NO_TEST=TRUE 41 NO_TEST=TRUE 39 41 NO_TEST=TRUE 41 15 18 39 39 41 39 41 39 39 39 39 ENET_TRANS * * ENET_TRANS_ISO COMP_ENET * * COMP_ENET_ISO ENET_TRANS ENET_TRANS * ENET_DIFF2DIFF NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET SD * * SD_ISO TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM ? TABLE_SPACING_RULE_ITEM COMP_ENET_ISO SPACING_RULE_SET ENET_DIFF TABLE_SPACING_RULE_ITEM * 40 TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_RULE_ITEM ENET_TRANS_ISO 40 CIV SPI CIV-specific Spacing Definitions Ethernet SPACING_RULE_SET SD_CMD I484 I483 Physical Net Type to Rule Map SD_PHY 40 SD TABLE_PHYSICAL_RULE_HEAD LAYER * 40 COMP_ENET I501 PHYSICAL_RULE_SET SD_50S 40 ENET_COMP_PHY ENET_TRANS I502 CIV-specific Physical Rules 39 40 ENET_TRANS ENET_TRANS I503 C 39 40 ENETCONN_MCT3 ENETCONN_MCT2 ENETCONN_MCT1 ENETCONN_MCT0 ENET_TRANS I504 Caesar IV (Ethernet/SD) ENETCONN_MDI_P ENETCONN_MDI_N ENETCONN_MDI_T_P ENETCONN_MDI_T_N kV isolation TABLE_SPACING_ASSIGNMENT_ITEM ? B B TABLE_SPACING_ASSIGNMENT_ITEM SD SD TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_ASSIGNMENT_HEAD TABLE_SPACING_RULE_ITEM SD_ISO * =3:1_SPACING ? TABLE_SPACING_ASSIGNMENT_ITEM A SYNC_MASTER=D8_FIYIN SYNC_DATE=07/02/2012 PAGE TITLE ETHERNET/SD CONSTRAINTS DRAWING NUMBER Apple Inc 051-9504 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED D 7.0.0 R NOTICE OF PROPRIETARY PROPERTY: SIZE REVISION BRANCH prefsb PAGE 136 OF 143 SHEET 111 OF 117 A AUTO-CONSTRAINTS PG BLC_* Physical 4V5_* Physical Spacing I30 Netname I31 D I1 I2 POWER_PHY PM POWER 4V5_REG_EN 4V5_REG_IN I32 56 BLC_CTL_PHY I33 56 I34 I35 I36 SMB_PHY I37 I38 ACDC_* Spacing I39 I40 I41 Netname I42 I3 I4 PM PM ACDC_BURST_EN ACDC_BURST_EN_L I43 48 I44 48 I45 I46 I47 I48 I49 Spacing XDP_PHY ALL_* I50 Netname I52 XDP_PHY XDP_PHY XDP_PHY XDP_PHY XDP_PHY XDP_PHY I51 I53 I5 PM ALL_SYS_PWRGD I54 47 65 I55 I56 I57 I58 C I59 AP_* Spacing I60 I61 I62 Netname I63 I6 I7 I8 I9 I10 I11 I12 I13 GENERIC_ISO GENERIC_ISO GENERIC_ISO GENERIC_ISO GENERIC_ISO PM PM PM AP_CLKREQ_L AP_CLKREQ_L_ISO AP_CLKREQ_Q_L AP_EVENT_L AP_PWR_EN_ISO AP_RESET_CONN_L AP_RESET_L AP_WAKE_L I64 15 21 I65 15 35 I66 35 I67 35 47 48 I68 15 35 I69 35 I70 26 35 I71 35 I72 Spacing PM PM BLC_CTL GENERIC_ISO GENERIC_ISO GENERIC_ISO SMB GENERIC_ISO GENERIC_ISO GENERIC_ISO PM PM PM CLK_JTAG GENERIC_ISO XDP XDP XDP XDP XDP XDP GENERIC_ISO GENERIC_ISO GENERIC_ISO GENERIC_ISO GENERIC_ISO GENERIC_ISO GENERIC_ISO GENERIC_ISO GENERIC_ISO GENERIC_ISO GENERIC_ISO GENERIC_ISO GENERIC_ISO GENERIC_ISO GENERIC_ISO GENERIC_ISO GENERIC_ISO GENERIC_ISO GENERIC_ISO GENERIC_ISO GENERIC_ISO GENERIC_ISO Voltage 5V BT_* Netname BLC_EXT_BOOT BLC_EXT_BOOT_L BLC_MCU_AOUT_R BLC_MCU_BV BLC_MCU_BV_D BLC_MCU_BV_R BLC_MCU_B_SDA_CONN BLC_MCU_FLAG_V BLC_MCU_PWM5 BLC_MCU_PWM5_R BLC_MCU_RESET BLC_MCU_RESET_L BLC_MCU_RESET_R_L BLC_MCU_RTCK BLC_MCU_RXD0 BLC_MCU_TCK BLC_MCU_TDI BLC_MCU_TDO BLC_MCU_TMS BLC_MCU_TRST BLC_MCU_TXD0 BLC_MCU_UVLO BLC_ON BLC_ON_DRAIN BLC_ON_R BLC_P_ON BLC_P_ON_BYPASS BLC_P_ON_D BLC_P_ON_DRAIN BLC_P_ON_D_R BLC_P_ON_GATE BLC_P_ON_R BLC_SKIP BLC_SNUB_1 BLC_SNUB_2 BLC_SNUB_3 BLC_UVLO BLC_VIN2_GATE BLC_VIN2_SRC BLC_VINP_GATE BLC_VIN_SNS BLC_VSYNC BLC_VSYNC_R 48 89 I80 89 I81 91 I82 Spacing Netname PM PM PM BT_PWR_EN BT_PWR_RST_L BT_PWR_RST_L_Q 35 15 20 35 D 35 89 91 91 91 89 89 BURSTMODE_* 89 89 89 Spacing Netname PM PM BURSTMODE_EN BURSTMODE_EN_L 89 89 I83 89 I84 71 48 71 89 89 89 89 89 CAM_* 89 89 89 Spacing Netname PM PM PM CAM_EXT_BOOT CAM_PROC_RESET CAM_PROC_RESET_L 91 91 I85 91 I86 89 90 91 I87 42 43 43 42 43 91 91 91 C 91 91 CPU_* 91 90 90 Physical Spacing Netname CPU_PHY CPU_PHY PM PM PM GENERIC_ISO CPU CPU CPU_PWRGD_1V05_R CPU_PWRGD_3V3 CPU_PWRGD_3V3_R CPU_SKTOCC CPU_THRMTRIP_3V3 CPU_THRMTRIP_R_L 90 90 I88 89 91 I89 91 I90 91 I91 91 I92 90 I93 28 28 28 64 47 48 48 87 89 89 DEBUG_* BLC12V_* I14 I15 I16 B I17 I18 Spacing Netname PM PM PM PM PM BLC12V_FAULT BLC12V_FAULT_L BLC12V_UVLO BLC12V_UVLO_OUT BLC12V_UVLO_REF BOOST_* I73 I74 I75 I76 I77 I78 I79 Spacing Netname GENERIC_ISO GENERIC_ISO GENERIC_ISO PM PM GENERIC_ISO GENERIC_ISO BOOST_BP BOOST_BYPASS BOOST_BYPASS_GATE BOOST_EN_GATE BOOST_EN_L BOOST_RC BOOST_SS I94 Spacing Netname PM DEBUG_RESET_L 89 91 89 89 89 89 Physical Spacing Netname TBT_GEN_55S TBT_GEN_55S PM PM GENERIC_ISO GENERIC_ISO TBT_GEN TBT_GEN GENERIC_ISO TBT_GEN TBT_GEN GENERIC_ISO DP_AUXIO_EN DP_GPU_MUX_EN DP_INTPNL_HPD DP_INT_EG_HPD DP_TBTPA_DDC_CLK DP_TBTPA_DDC_DATA DP_TBTPA_HPD DP_TBTPB_DDC_CLK DP_TBTPB_DDC_DATA DP_TBTPB_HPD I95 Spacing I96 I97 Voltage I98 Netname I99 GENERIC_ISO GENERIC_ISO GENERIC_ISO GENERIC_ISO GENERIC_ISO GENERIC_ISO PM GENERIC_ISO GENERIC_ISO PM PM I19 I20 I21 I22 I23 I24 I25 I26 I27 I28 I29 BLC_BL BLC_BL_GATE BLC_BST BLC_BST_R BLC_BYPASS_GATE BLC_DIM_MCU BLC_EN BLC_ENA BLC_ENA1 BLC_EN_DELAY BLC_EN_R B DP_* 89 BLC_* Physical 26 49 89 I100 89 91 I101 91 I102 89 91 I103 89 I104 91 TBT_GEN_55S TBT_GEN_55S 15 86 88 84 84 87 82 84 85 86 85 86 36 86 85 88 85 88 36 88 89 87 89 90 89 89 91 87 89 A AUTO-CONSTRAINTS GENERATED Fri 04/06/12 07:24:10 PM PAGE TITLE A AUTO-CONSTRAINTS DRAWING NUMBER Apple Inc 051-9504 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED D 7.0.0 R NOTICE OF PROPRIETARY PROPERTY: SIZE REVISION BRANCH prefsb PAGE 138 OF 143 SHEET 112 OF 117 AUTO-CONSTRAINTS PG ENETCONN_* I1 Spacing Netname GENERIC_ISO ENETCONN_TCT FET_* 40 Physical Spacing POWER_PHY POWER_PHY POWER_PHY GENERIC_ISO GENERIC_ISO GENERIC_ISO GENERIC_ISO GENERIC_ISO GENERIC_ISO GENERIC_ISO GENERIC_ISO POWER POWER POWER I33 I34 D I35 I36 I37 I38 ENET_* I39 I40 Physical Spacing Netname I41 I42 I2 I3 I4 I5 I6 I7 I8 I9 I10 I11 XDP_PHY I12 I13 I14 I15 I16 I17 I18 GENERIC_ISO GENERIC_ISO GENERIC_ISO PM PM PM PM PM PM XDP PM PM PM PM GENERIC_ISO GENERIC_ISO PM ENET_ACT ENET_ASF_GPIO ENET_CLKREQ_L ENET_CLKREQ_L_Q ENET_CR_1V8_EN ENET_CR_1V8_EN_R ENET_CR_3V3_EN_L ENET_CR_3V3_EN_L_R ENET_CR_PWREN ENET_LOW_PWR ENET_PWR_EN_L ENET_PWR_EN_L_R ENET_RESET_L ENET_SD_RESET_L ENET_SR_DISABLE ENET_SR_LX ENET_WAKE_L 40 I43 HDD_* Voltage Netname 12V 12V 12V FET_EN_P12V_S0 FET_EN_P12V_S0_BLC FET_EN_P12V_S0_BLC_R FET_EN_P12V_S0_R FET_EN_P12V_S5 FET_EN_P12V_S5_R FET_EN_VDDQ_S0 FET_HDD_SLGSW FET_VCC_U7950 FET_VCC_U7970 FET_VCC_U7980 74 I70 74 I71 74 I72 74 I73 74 I74 Spacing Netname GENERIC_ISO GENERIC_ISO PM GENERIC_ISO GENERIC_ISO HDD_12V_S0_GATE HDD_OOB_1V00_REF HDD_PWR_EN HDD_PWR_EN_L HDD_PWR_EN_R Physical Spacing Netname SMB_PHY SMB_PHY SMB SMB I2C_TCON_MAS_SCL I2C_TCON_MAS_SDA I20 I21 I22 GENERIC_ISO GENERIC_ISO GENERIC_ISO GENERIC_ISO FAN_0_PWM_FET FAN_0_PWM_FILT FAN_0_TACH_FET FAN_0_TACH_FILT 52 74 74 I2C_* 74 I75 I76 FLAG_* 39 41 Spacing Netname GENERIC_ISO FLAG_V 40 I44 89 90 91 39 41 26 41 Spacing Netname GENERIC_ISO IFPD_RSET 39 39 40 I77 G3_* 40 Spacing Netname GENERIC_ISO G3_POWERON_L IFPEF_* 54 Spacing Netname SENSE GND_SMC_AVSS I52 I53 I54 I55 I26 I27 I28 I29 I30 I31 I32 I80 Spacing Netname GENERIC_ISO GENERIC_ISO GENERIC_ISO GENERIC_ISO GENERIC_ISO GENERIC_ISO XDP XDP XDP XDP GENERIC_ISO GENERIC_ISO GENERIC_ISO GENERIC_ISO GENERIC_ISO GENERIC_ISO SPI SPI SPI SPI SPI SPI SPI GPU_ALT_VREF GPU_BUFRSTN GPU_IFPAB_PLLVDD GPU_IFPA_IOVDD GPU_IFPB_IOVDD GPU_IFPC_IOVDD GPU_JTAG_TDI GPU_JTAG_TDO GPU_JTAG_TMS GPU_JTAG_TRST_L GPU_MLS_STRAP0 GPU_MLS_STRAP1 GPU_MLS_STRAP2 GPU_MLS_STRAP3 GPU_MLS_STRAP4 GPU_RESET_L GPU_ROM_CS_L GPU_ROM_CS_L_R GPU_ROM_SI GPU_ROM_SI_R GPU_ROM_SO GPU_ROM_SO_R GPU_ROM_WP_L I82 I83 I51 FB_* I25 I79 82 95 I50 FB_A0_VREFC FB_A0_VREFD FB_A1_VREFC FB_A1_VREFD FB_B0_VREFC FB_B0_VREFD FB_B1_VREFC FB_B1_VREFD FB_VREF IFPEF_RSET 81 ISNSA_* I81 I49 GENERIC_ISO GENERIC_ISO GENERIC_ISO GENERIC_ISO GENERIC_ISO GENERIC_ISO GENERIC_ISO GENERIC_ISO GENERIC_ISO GENERIC_ISO 47 48 51 55 GPU_* FBVDD_ALTVO Netname Netname 54 I48 I24 I78 Spacing 54 Netname Spacing 81 C 47 48 GND_* 54 I47 B 50 87 IFPD_* 40 Physical GENERIC_ISO 50 87 26 39 41 FBVDD_* I23 52 39 40 I46 Spacing 52 74 FAN_* I19 D 21 52 74 15 18 40 I45 Netname 52 47 48 C Spacing 52 79 I56 79 I57 79 I58 79 I59 80 I60 80 I61 80 I62 80 I63 77 I64 I65 I66 I67 I68 I69 XDP_PHY XDP_PHY XDP_PHY XDP_PHY SPI_50S SPI_50S SPI_50S SPI_50S SPI_50S SPI_50S SPI_50S A 77 82 I84 83 I85 81 I86 81 I87 81 I88 81 I89 78 81 I90 78 81 I91 78 81 I92 81 I93 81 82 I94 81 82 I95 81 82 I96 81 82 I97 81 82 I98 26 75 82 I99 81 82 I100 82 I101 81 82 I102 Electrical Physical Spacing Netname SNS_CURRENT SNS_CURRENT SNS_CURRENT SNS_CURRENT SNS_CURRENT SNS_CURRENT SNS_CURRENT SNS_CURRENT SNS_CURRENT SNS_CURRENT SNS_CURRENT SNS_CURRENT SNS_CURRENT SNS_CURRENT SNS_CURRENT SNS_CURRENT SNS_CURRENT SNS_CURRENT SNS_CURRENT SNS_CURRENT SNS_CURRENT SNS_CURRENT SNS_CURRENT SNS_CURRENT SNS_DIFF_PHY SNS_DIFF_PHY SNS_DIFF_PHY SNS_DIFF_PHY SNS_DIFF_PHY SNS_DIFF_PHY SNS_DIFF_PHY SNS_DIFF_PHY SNS_DIFF_PHY SNS_DIFF_PHY SNS_DIFF_PHY SNS_DIFF_PHY SNS_DIFF_PHY SNS_DIFF_PHY SNS_DIFF_PHY SNS_DIFF_PHY SNS_DIFF_PHY SNS_DIFF_PHY SNS_DIFF_PHY SNS_DIFF_PHY SNS_DIFF_PHY SNS_DIFF_PHY SNS_DIFF_PHY SNS_DIFF_PHY SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE ISNSA_P12VG3H_N ISNSA_P12VG3H_P ISNSA_P12VS0_CPU_P1V05_N ISNSA_P12VS0_CPU_P1V05_P ISNSA_P12VS0_CPU_VCCSA_N ISNSA_P12VS0_CPU_VCCSA_P ISNSA_P12VS0_FBVDDQ_N ISNSA_P12VS0_FBVDDQ_P ISNSA_P12VS0_HDD_N ISNSA_P12VS0_HDD_P ISNSA_P12VS0_P1V05_N ISNSA_P12VS0_P1V05_P ISNSA_P1V05S0_PCH_N ISNSA_P1V05S0_PCH_P ISNSA_P1V5S0_CPU_MEM_N ISNSA_P1V5S0_CPU_MEM_P ISNSA_P3V3S0_SSD_N ISNSA_P3V3S0_SSD_P ISNSA_P3V3S4_AP_N ISNSA_P3V3S4_AP_P ISNSA_P5VS0_HDD_N ISNSA_P5VS0_HDD_P ISNSA_PVDDQS3_DDR_N ISNSA_PVDDQS3_DDR_P 51 51 55 55 55 55 51 51 51 51 B 55 55 51 51 51 51 51 51 55 55 51 51 51 51 82 81 82 82 82 AUTO-CONSTRAINTS GENERATED Fri 04/06/12 07:24:10 PM PAGE TITLE A AUTO-CONSTRAINTS DRAWING NUMBER Apple Inc 051-9504 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED D 7.0.0 R NOTICE OF PROPRIETARY PROPERTY: SIZE REVISION BRANCH prefsb PAGE 139 OF 143 SHEET 113 OF 117 AUTO-CONSTRAINTS PG ISNS_* I1 I2 D I3 I4 I5 I6 I7 I8 I9 I10 I11 I12 I13 I14 I15 I16 I17 I18 I19 I20 I21 LPCPLUS_* Physical Spacing Netname SNS_PHY SNS_PHY SNS_PHY SNS_PHY SNS_PHY SNS_PHY SNS_PHY SNS_PHY SNS_PHY SNS_PHY SNS_PHY SNS_PHY SNS_PHY SNS_PHY SNS_PHY SNS_PHY SNS_PHY SNS_PHY SNS_PHY SNS_PHY SNS_PHY SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE ISNS_CPUAXG_FB ISNS_CPUAXG_N ISNS_CPUAXG_P ISNS_CPUCORE_FB ISNS_CPUCORE_N ISNS_CPUCORE_P ISNS_GPUCORE_FB ISNS_GPUCORE_N ISNS_GPUCORE_P ISNS_P12VG3H_R ISNS_P12VS0_CPU_P1V05_R ISNS_P12VS0_CPU_VCCSA_R ISNS_P12VS0_FBVDDQ_R ISNS_P12VS0_HDD_R ISNS_P12VS0_P1V05_R ISNS_P1V05S0_PCH_R ISNS_P1V5S0_CPU_MEM_R ISNS_P3V3S0_SSD_R ISNS_P3V3S4_AP_R ISNS_P5VS0_HDD_R ISNS_PVDDQS3_DDR_R 51 I43 Spacing Netname GENERIC_ISO LPCPLUS_GPIO P1V2_* 21 49 I59 Spacing Netname PM P1V2_S4_EN PCH_* Physical 43 I67 51 I68 51 I69 51 I70 51 I71 51 LPC_* 51 I72 P1V8_* I73 51 I74 Spacing 51 Netname Spacing Netname I75 51 I76 55 I44 55 I45 GENERIC_ISO GENERIC_ISO LPC_PWRDWN_L LPC_SERIRQ 19 26 47 49 I60 PM P1V8_S4_EN 43 18 47 49 I77 I78 51 I79 51 I80 55 I81 51 51 55 Spacing 51 I61 I47 Spacing Netname GENERIC_ISO P3V3AP_VMON Netname 51 PM PM MEMVTT_EN MEMVTT_EN_L I22 I23 I83 P3V3_* MEM_* Netname ISOLATE_CPU_MEM_5V ISOLATE_CPU_MEM_5V_L Spacing 28 Netname I62 28 I63 I48 GENERIC_ISO MEM_EVENT_L Spacing Netname GENERIC_ISO GENERIC_ISO P3V3_S0_EN_G P3V3_S3_EN_G Physical Spacing I24 I25 I26 I27 I28 I29 I30 XDP_PHY XDP_PHY XDP_PHY XDP_PHY XDP_PHY XDP_PHY XDP_PHY XDP XDP XDP XDP XDP XDP XDP JTAG_GMUX_TMS JTAG_TBT_TDI JTAG_TBT_TDI_ISOL JTAG_TBT_TDO JTAG_TBT_TDO_ISOL JTAG_TBT_TMS JTAG_TBT_TMS_ISOL LED_* B I31 I32 I33 I34 I35 I36 I37 I38 I39 I40 I41 I42 Spacing Netname PM PM PM GENERIC_ISO GENERIC_ISO GENERIC_ISO GENERIC_ISO GENERIC_ISO GENERIC_ISO GENERIC_ISO GENERIC_ISO GENERIC_ISO LED_DRIVER_EN LED_DRIVER_EN_L LED_DRIVER_EN_L_R LED_DRIVER_OVP1 LED_DRIVER_OVP1P LED_DRIVER_OVP1_OUT LED_DRIVER_OVP2 LED_DRIVER_OVP2P LED_DRIVER_OVP2_OUT LED_DRIVER_OVP3 LED_DRIVER_OVP3P LED_DRIVER_OVP3_OUT I64 I49 15 36 I50 XDP_PHY XDP_PHY XDP XDP Netname GENERIC_ISO PM PCIE_CLKREQ5_GPIO44_L PCIE_WAKE_L 15 21 15 21 21 43 19 21 21 21 19 15 18 18 20 15 19 18 19 35 40 C Spacing Netname GENERIC_ISO PEG_CLKREQ_L 15 18 75 Spacing Netname GENERIC_ISO P3V42G3H_BOOST MOJO_RX_L MOJO_TX_L PGOOD_* 73 45 47 48 45 47 48 Spacing Netname PM PGOOD_P1V5_S0_DLY 15 21 15 36 I85 15 18 28 P5V_* 15 36 I51 OCA_* Spacing Netname Spacing Netname GENERIC_ISO P5V_S0_EN_G GENERIC_ISO OCA_FET_DRAIN I65 PLT_* 74 91 I86 I87 PCA9557D_* 90 91 91 OVP_* Spacing Netname Spacing Netname GENERIC_ISO PCA9557D_RESET_L GENERIC_ISO GENERIC_ISO GENERIC_ISO GENERIC_ISO GENERIC_ISO GENERIC_ISO GENERIC_ISO OVP_OREF OVP_OUT1 OVP_OUT1_R OVP_OUT2 OVP_OUT2_R OVP_OUT3 OVP_OUT3_R 91 Spacing Netname PCH PCH PLT_RESET_L PLT_RST_BUF_L B 20 26 26 90 91 89 90 I66 26 28 34 PM_* 90 90 91 I52 89 90 I53 90 I54 90 91 I55 89 90 I56 90 I57 I58 91 91 91 I88 91 I89 91 I90 91 I91 I93 I94 I95 I96 I97 A Spacing Netname PM PM PM PM PM PM PM PM PM PM PM_CLKRUN_L PM_DSW_PWRGD PM_EN_FET_P12V_S0 PM_EN_FET_P12V_S0_R PM_EN_FET_P3V3_S0 PM_EN_FET_P3V3_S4 PM_EN_FET_P5V_S0 PM_EN_FET_VDDQ_S0 PM_EN_LDO_DDRVTT_S0 PM_EN_REG_CPUCORE_S0 91 I92 AUTO-CONSTRAINTS GENERATED Fri 04/06/12 07:24:10 PM PAGE TITLE 47 48 49 47 48 65 64 74 74 64 74 64 74 64 74 64 74 64 72 64 66 A AUTO-CONSTRAINTS DRAWING NUMBER Apple Inc 051-9504 NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED SIZE D REVISION 7.0.0 R D 21 89 PEG_* 74 Netname 20 15 21 15 21 P3V42G3H_* MOJO_* Spacing 21 89 29 30 31 32 47 48 Netname Physical Spacing 74 I84 JTAG_* PCH_BLC_EXT_BOOT PCH_BLC_EXT_BOOT_R PCH_BLC_MCU_RESET PCH_BLC_MCU_RESET_R PCH_CAM_RESET PCH_CAM_RESET_R PCH_DSWVRMEN PCH_PECI PCH_PROCPWRGD PCH_RCIN_L PCH_RI_L PCH_SMBALERT_L PCH_SRTCRST_L PCH_STRP_TOPBLK_SWP_L PCH_SUSWARN_L PCIE_* 35 28 ISOLATE_* PM PM PM PM PM PM PM PM GENERIC_ISO CPU CPU GENERIC_ISO GENERIC_ISO GENERIC_ISO GENERIC_ISO GENERIC_ISO GENERIC_ISO 28 64 I82 Spacing Netname P3V3AP_* MEMVTT_* 51 I46 C CPU_PHY CPU_PHY Spacing BRANCH prefsb PAGE 140 OF 143 SHEET 114 OF 117 AUTO-CONSTRAINTS PG PM_* I1 I2 D I3 I4 I5 I6 I7 I8 I9 I10 I11 I12 I13 I14 I15 I16 I17 I18 I19 I20 I21 I22 I23 I24 I25 I26 I27 I28 C I29 I30 I31 I32 I33 I34 I35 I36 I37 I38 I39 I40 I41 I42 I43 I44 I45 I46 I47 I48 I49 I50 I51 I52 I53 I54 B I55 I56 I57 I58 I59 I60 I61 I62 I63 I64 I65 I66 I67 I68 I69 I129 I130 PP12V_* Spacing Netname PM PM PM PM PM PM PM PM PM PM PM PM PM PM PM PM PM PM PM PM PM PM PM PM PM PM PM PM PM PM PM PM PM PM PM PM PM PM PM PM PM PM PM PM PM PM PM PM PM PM PM PM PM PM PM PM PM PM PM PM PM PM PM PM PM PM PM PCH PCH PM PM PM_EN_REG_CPU_P1V05_S0 PM_EN_REG_FBVDDQ_S0 PM_EN_REG_GPUCORE_S0_R PM_EN_REG_P1V05_S0 PM_EN_REG_P1V8_S0 PM_EN_REG_P3V3_S5 PM_EN_REG_P5V_S4 PM_EN_REG_VCCSA_S0 PM_EN_REG_VDDQ_S3 PM_EN_S0 PM_EN_S4 PM_EN_USB_PWR PM_LED_A_ALL_SYS_PWRGD PM_LED_A_BLC_GOOD PM_LED_A_CPUAXG_PGOOD PM_LED_A_GPU_GOOD PM_LED_A_PGOOD_CPUCORE_S0 PM_LED_A_PGOOD_CPU_P1V05_S0 PM_LED_A_PGOOD_REG_FBVDDQ_S0 PM_LED_A_PGOOD_REG_GPUCORE_S0 PM_LED_A_PGOOD_REG_P1V05 PM_LED_A_PGOOD_REG_VDDQ_S3 PM_LED_A_S4 PM_LED_A_S5 PM_LED_A_SLP_S3 PM_LED_A_VIDEO_ON PM_LED_K_ALL_SYS_PWRGD PM_LED_K_BLC_GOOD PM_LED_K_CPUAXG_PGOOD PM_LED_K_GPU_GOOD PM_LED_K_PGOOD_CPUCORE_S0 PM_LED_K_PGOOD_CPU_P1V05_S0 PM_LED_K_PGOOD_REG_FBVDDQ_S0 PM_LED_K_PGOOD_REG_GPUCORE_S0 PM_LED_K_PGOOD_REG_P1V05 PM_LED_K_PGOOD_REG_VDDQ_S3 PM_LED_K_SLP_S3 PM_MEM_PWRGD_L PM_PCH_APWROK PM_PCH_PWROK PM_PCH_PWROK_APWROK PM_PCH_SYS_PWROK PM_PGOOD_FBVDDQ_VDDQ_S0 PM_PGOOD_FET_P12V_S0 PM_PGOOD_FET_P12V_S0_BLC PM_PGOOD_FET_P12V_S5 PM_PGOOD_FET_P3V3_S0 PM_PGOOD_FET_P5V_S0 PM_PGOOD_FET_VDDQ_S0 PM_PGOOD_P3V3_S4_FET PM_PGOOD_REG_ALL_P1V05_S0 PM_PGOOD_REG_ALL_P1V05_S0_R PM_PGOOD_REG_CPUCORE_S0 PM_PGOOD_REG_CPU_P1V05_S0 PM_PGOOD_REG_FBVDDQ_S0 PM_PGOOD_REG_P1V05_S0 PM_PGOOD_REG_P1V8_S0 PM_PGOOD_REG_P3V3_S5 PM_PGOOD_REG_P5V_S4 PM_PGOOD_REG_VCCSA_S0 PM_PGOOD_REG_VDDQ_S3 PM_PWRBTN_L PM_RSMRST_PCH_L PM_RSMRST_PCH_L_R PM_SLP_S3_L PM_SLP_S4_L PM_SLP_S5_L PM_SYSRST_L PM_THRMTRIP_L PGOOD_P12V_S0_R PGOOD_P12V_S0 64 69 I70 64 95 I71 92 I72 64 95 I73 PP3V3RHV_* Physical Spacing Voltage Netname POWER_PHY POWER_PHY POWER_PHY POWER_PHY POWER POWER POWER POWER 12V 12V 12V 12V PP12V_LCD PP12V_LCD_EXT PP12V_S0_FAN_0_FILT PP12V_S0_HDD_FET 87 I93 87 I94 Physical Spacing Voltage Netname POWER_PHY POWER_PHY POWER POWER 12V 12V PP3V3RHV_SW_TBTAPWR PP3V3RHV_SW_TBTBPWR Physical Spacing Voltage Netname POWER_PHY POWER_PHY POWER_PHY POWER_PHY POWER_PHY POWER_PHY POWER_PHY POWER_PHY POWER_PHY POWER_PHY POWER_PHY POWER_PHY POWER_PHY POWER_PHY POWER_PHY POWER_PHY POWER_PHY POWER_PHY POWER_PHY POWER_PHY POWER_PHY POWER POWER POWER POWER POWER POWER POWER POWER POWER POWER POWER POWER POWER POWER POWER POWER POWER POWER POWER POWER POWER 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V PP3V3_DMIC_CONN PP3V3_G3H_AVREF_SMC PP3V3_G3H_BT_FET PP3V3_G3H_BT_FLT PP3V3_G3H_SMC_USBMUX_R PP3V3_G3H_SMC_VDDA PP3V3_G3_RTC PP3V3_GPU_IFPX_PLLVDD PP3V3_PVDDQS3_ISNS PP3V3_S0_PCH_VCCA_DAC_F PP3V3_S0_SSD_FLT PP3V3_S0_SW_SD_PWR PP3V3_S4_ALS_F PP3V3_S4_AP_FET PP3V3_S4_AP_FLT PP3V3_S4_ENET_FET_AVDDH PP3V3_S4_ENET_FET_BIASVDDH PP3V3_S4_ENET_FET_SRVDD PP3V3_S4_ENET_FET_XTALVDDH PP3V3_S4_USB_HUB_VDD PP3V3_S5_XDP_R 86 88 D 54 44 52 64 72 64 71 74 64 71 PP3V3_* 64 70 64 72 PP1V05_* 64 64 Physical 45 46 64 Spacing Voltage Netname I95 I96 I74 I75 I76 I77 I78 I79 I80 I81 POWER_PHY POWER_PHY POWER_PHY POWER_PHY POWER_PHY POWER_PHY POWER_PHY POWER_PHY POWER POWER POWER POWER POWER POWER POWER POWER 1.05V 1.05V 1.05V 1.05V 1.05V 1.05V 1.05V 1.05V PP1V05_GPU_FB_DLL_AVDD PP1V05_GPU_FB_PLL_AVDD PP1V05_GPU_IFPD_IOVDD PP1V05_GPU_IFPEF_IOVDD PP1V05_GPU_PLLVDD PP1V05_GPU_SP_PLLVDD PP1V05_S0_PCH_VCCADPLLA_F PP1V05_S0_PCH_VCCADPLLB_F 77 I97 77 I98 81 I99 81 I100 81 I101 81 83 I102 17 22 I103 17 22 I104 I105 I106 I107 I108 I109 PP1V2_* I110 I111 Physical Spacing Voltage Netname POWER_PHY POWER_PHY POWER_PHY POWER_PHY POWER_PHY POWER_PHY POWER_PHY POWER POWER POWER POWER POWER POWER POWER 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V PP1V2_ENET_INTREG PP1V2_G3H_SMC_VDDC PP1V2_S4_ENET_PHY_AVDDL PP1V2_S4_ENET_PHY_GPHYPLL PP1V2_S4_ENET_PHY_PCIEPLL PP1V2_USB_HUB_CRFILT PP1V2_USB_HUB_PLLFILT I112 I113 I82 I83 I84 I85 I86 I87 I88 40 I114 47 I115 42 47 48 35 35 45 47 26 81 51 17 22 44 41 42 35 35 39 39 39 C 39 27 25 39 39 39 27 27 PP4V5_* 28 19 65 15 19 26 35 43 65 89 Physical Spacing Voltage Netname POWER_PHY POWER 4.5V PP4V5_AUDIO_ANALOG 65 19 48 65 I116 PP1V5_* 64 56 60 62 74 74 91 Physical Spacing Voltage Netname POWER_PHY POWER 1.5V PP1V5_S0_DP_BIAS 74 64 74 I89 84 PP5V_* 64 74 28 64 74 27 35 64 74 Physical Spacing Voltage Netname POWER_PHY POWER_PHY POWER_PHY POWER_PHY POWER_PHY POWER_PHY POWER_PHY POWER_PHY POWER_PHY POWER_PHY POWER_PHY POWER_PHY POWER POWER POWER POWER POWER POWER POWER POWER POWER POWER POWER POWER 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V PP5V_AUDIO_HPAMP PP5V_S0_HDD_FET PP5V_S0_PCH_V5REF PP5V_S4_EXTA PP5V_S4_EXTA_F PP5V_S4_EXTB PP5V_S4_EXTB_F PP5V_S4_EXTC PP5V_S4_EXTC_F PP5V_S4_EXTD PP5V_S4_EXTD_F PP5V_S5_PCH_V5REFSUS 64 65 28 64 I117 PP1V8_* 25 65 66 I118 64 69 I119 Physical 64 95 Spacing Voltage Netname I120 64 95 64 72 I121 I90 POWER_PHY POWER 1.8V PP1V8_S0_PCH_VCCVRM_F 22 24 I122 65 71 I123 64 71 I124 64 65 70 I125 64 72 I126 15 19 25 47 I127 PP3V3R1V8_* 19 65 I128 56 57 44 52 24 45 B 45 45 45 46 46 46 46 24 65 15 19 28 40 47 48 64 Physical Spacing Netname POWER_PHY POWER PP3V3R1V8_ENET_LR_OUT_REG 15 19 47 64 15 19 47 64 19 25 26 47 I92 39 21 48 65 64 65 74 A AUTO-CONSTRAINTS GENERATED Fri 04/06/12 07:24:10 PM PAGE TITLE A AUTO-CONSTRAINTS DRAWING NUMBER Apple Inc 051-9504 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED D 7.0.0 R NOTICE OF PROPRIETARY PROPERTY: SIZE REVISION BRANCH prefsb PAGE 141 OF 143 SHEET 115 OF 117 AUTO-CONSTRAINTS PG PPHV_* I1 I2 S5_* Physical Spacing Voltage Netname POWER_PHY POWER_PHY POWER POWER 12V 12V PPHV_SW_TBTAPWR PPHV_SW_TBTBPWR 86 I23 Spacing Netname PM S5_PWRGD SMCISNS_* 47 65 I47 88 I48 D I49 I50 I51 PPVBATT_* Physical Spacing Voltage Netname POWER_PHY POWER_PHY POWER POWER 3.3V 3.3V PPVBATT_G3_RTC PPVBATT_G3_RTC_R Netname I55 I56 I24 I4 I53 I54 Spacing I3 I52 SATALED_* GENERIC_ISO SATALED_L 44 I57 26 I58 26 I59 I60 I61 Physical Spacing Netname SNS_PHY SNS_PHY SNS_PHY SNS_PHY SNS_PHY SNS_PHY SNS_PHY SNS_PHY SNS_PHY SNS_PHY SNS_PHY SNS_PHY SNS_PHY SNS_PHY SNS_PHY SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SMCISNS_CPUAXG SMCISNS_CPUCORE SMCISNS_GPUCORE SMCISNS_P12VG3H SMCISNS_P12VS0_CPU_P1V05 SMCISNS_P12VS0_CPU_VCCSA SMCISNS_P12VS0_FBVDDQ SMCISNS_P12VS0_HDD SMCISNS_P12VS0_P1V05 SMCISNS_P1V05S0_PCH SMCISNS_P1V5S0_CPU_MEM SMCISNS_P3V3S0_SSD SMCISNS_P3V3S4_AP SMCISNS_P5VS0_HDD SMCISNS_PVDDQS3_DDR 48 51 48 51 D 48 51 48 51 48 55 48 55 48 51 48 51 48 55 48 51 48 51 48 51 48 55 48 51 48 51 SDCONN_* PU_* Spacing Netname GENERIC_ISO PU_U6900 I25 I26 I5 64 I27 Spacing Netname GENERIC_ISO GENERIC_ISO GENERIC_ISO SDCONN_DETECT SDCONN_ILIM SDCONN_OC_L SMCVSNS_* 41 41 41 I62 I63 I64 PWR_* C I65 SD_* I66 I67 Spacing Netname Spacing Netname I68 I69 I6 I7 PM PM PWR_BTN PWR_BTN_R 48 I28 GENERIC_ISO I9 I10 CPU_PHY I11 I12 I13 I14 I15 VR_CTL_PHY VR_CTL_PHY VR_CTL_PHY VR_CTL_PHY I16 I17 I18 B I19 I20 Spacing Netname PM PM CPU PM VR_CTL VR_CTL VR_CTL VR_CTL PM PM PM PM PM REG_CPUAXG_PGOOD REG_CPUCORE_PGOOD REG_CPUCORE_VRHOT_L REG_CPU_P1V05S0_PGOOD REG_FBVDDQ_SET0 REG_FBVDDQ_SET1 REG_FBVDDQ_SET1_R REG_FBVDDQ_SREF REG_P1V8S0_PGOOD REG_P3V3S5_PGOOD REG_P5VS4_PGOOD REG_VCCSAS0_PGOOD REG_VDDQS3_PGOOD 66 I30 PM PM RTC_RESET_L RTC_RESET_L_R 41 I71 41 I72 69 I75 95 I76 95 I77 SMBUS_* 95 Physical Spacing Netname GENERIC_ISO GENERIC_ISO PM GENERIC_ISO GENERIC_ISO GENERIC_ISO CPU PM GENERIC_ISO XTAL GENERIC_ISO GENERIC_ISO GENERIC_ISO GENERIC_ISO GENERIC_ISO PM PM PM PM PM SENSE SENSE SENSE SENSE SENSE SENSE SENSE CPU CPU PM GENERIC_ISO PM CPU PM SMC_ACDC_ID SMC_ACDC_ID_R SMC_ASSERT_RTCRST SMC_BLC_MUX_RX_L SMC_BLC_MUX_TX_L SMC_CPU_CATERR_L SMC_CPU_PECI SMC_DELAYED_PWRGD SMC_DP_HPD_L SMC_EXTAL SMC_FAN_0_CTL SMC_FAN_0_TACH SMC_GFX_OVERTEMP SMC_GFX_OVERTEMP_Q SMC_GFX_OVERTEMP_R_L SMC_GFX_THROTTLE_L SMC_GFX_THROTTLE_R_L SMC_LRESET_L SMC_MANUAL_RST_L SMC_ONOFF_L SMC_OOB1_RX_CN SMC_OOB1_RX_FILT SMC_OOB1_RX_L SMC_OOB1_RX_R SMC_OOB1_TX_L SMC_OOB2_RX_L SMC_OOB2_TX_L SMC_PECI_L SMC_PECI_L_R SMC_PME_S4_WAKE_L SMC_PM_G2_EN SMC_PM_PCH_SYS_PWROK SMC_PROCHOT SMC_RESET_L I79 Physical 72 Spacing Netname I80 71 71 CPU_PHY I78 95 CLK_XTAL I81 I31 70 I32 72 I33 I38 I39 I40 Netname SLG_ENET_RESET_L SLG_ENET_RESET_R_L I74 I37 Spacing PM PM I73 I36 RTC_* Netname 66 I35 I41 I42 I22 SMCVSNS_CPUAXG SMCVSNS_CPUCORE SMCVSNS_GPUCORE SMCVSNS_P12VG3H SMCVSNS_P1V05S0_PCH SMCVSNS_P1V5S0_CPU_MEM SMCVSNS_P3V3S0 SMCVSNS_P5VS0_HDD SMCVSNS_PVDDQS3_DDR 48 51 48 51 48 51 48 51 48 51 C 48 51 48 51 48 51 48 51 SMC_* Spacing 66 I34 I21 I70 Netname SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SLG_* I29 I8 41 Spacing SNS_PHY SNS_PHY SNS_PHY SNS_PHY SNS_PHY SNS_PHY SNS_PHY SNS_PHY SNS_PHY REG_* Physical SD_DETECT_LVL Physical 18 26 48 I43 48 I44 I45 I46 SMB_PHY SMB_PHY SMB_PHY SMB_PHY SMB_PHY SMB_PHY SMB_PHY SMB_PHY SMB_PHY SMB_PHY SMB_PHY SMB_PHY SMB_PHY SMB_PHY SMB_PHY SMB_PHY SMB SMB SMB SMB SMB SMB SMB SMB SMB SMB SMB SMB SMB SMB SMB SMB SMBUS_PCH_CLK SMBUS_PCH_CLK_R SMBUS_PCH_DATA SMBUS_PCH_DATA_R SMBUS_SMC_0_S0_SCL SMBUS_SMC_0_S0_SDA SMBUS_SMC_1_S0_SCL SMBUS_SMC_1_S0_SDA SMBUS_SMC_2_S4_SCL SMBUS_SMC_2_S4_SDA SMBUS_SMC_3_SCL SMBUS_SMC_3_SDA SMBUS_SMC_4_ASF_SCL SMBUS_SMC_4_ASF_SDA SMBUS_SMC_5_G3H_SCL SMBUS_SMC_5_G3H_SDA 18 50 I82 50 I83 18 50 I84 50 I85 47 50 I86 47 50 I87 47 50 I88 47 50 I89 47 50 I90 47 50 I91 47 50 I92 47 50 I93 47 48 50 I94 47 48 50 I95 47 48 50 I96 47 48 50 I97 I98 I99 I100 I101 I102 I103 I104 A CPU_PHY CPU_PHY AUTO-CONSTRAINTS GENERATED Fri 04/06/12 07:24:10 PM 48 48 48 89 48 89 47 48 48 38 47 48 65 47 48 47 48 47 54 47 54 47 48 82 B 82 82 47 82 82 26 47 48 47 48 44 44 52 47 52 52 47 48 44 48 44 48 47 48 48 35 47 48 47 48 74 47 48 47 48 47 48 49 PAGE TITLE A AUTO-CONSTRAINTS DRAWING NUMBER Apple Inc 051-9504 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED D 7.0.0 R NOTICE OF PROPRIETARY PROPERTY: SIZE REVISION BRANCH prefsb PAGE 142 OF 143 SHEET 116 OF 117 AUTO-CONSTRAINTS PG SMC_* Spacing Netname CLK_XTAL CLK_XTAL GENERIC_ISO GENERIC_ISO GENERIC_ISO PM GENERIC_ISO GENERIC_ISO GENERIC_ISO PM GENERIC_ISO GENERIC_ISO GENERIC_ISO GENERIC_ISO PM GENERIC_ISO XTAL XTAL SMC_ROMBOOT SMC_RUNTIME_SCI_L SMC_RX_L SMC_S4_WAKESRC_EN SMC_TCK SMC_TDI SMC_TDO SMC_THRMTRIP SMC_TMS SMC_TO_BLC_RX_L SMC_TO_BLC_TX_L SMC_TX_L SMC_WAKE_L SMC_WAKE_SCI_L SMC_XTAL SMC_XTAL_R I1 I2 D I3 I4 I5 I6 I7 I8 I9 I10 I11 I12 I13 I14 I15 I16 TBT_* Physical Physical 48 49 I24 15 21 47 I25 47 48 49 I26 35 47 48 I27 47 48 49 I28 47 48 49 I29 47 48 49 I30 47 48 I31 47 48 49 I32 48 I33 48 I34 47 48 49 I35 47 I36 15 21 47 I37 47 48 I38 48 I39 TBT_GEN_55S TBT_GEN_55S I40 I41 I42 I43 VREFMRGN_* Spacing Voltage Netname GENERIC_ISO TBT_GEN PM GENERIC_ISO TBT_GEN PM GENERIC_ISO GENERIC_ISO GENERIC_ISO GENERIC_ISO PM GENERIC_ISO GENERIC_ISO GENERIC_ISO PM PM PM PM PM PM 3.3V TBT_A_BIAS TBT_A_CONFIG1_RC TBT_A_HV_EN TBT_B_BIAS TBT_B_CONFIG1_RC TBT_B_HV_EN TBT_CLKREQ_ISOL_L TBT_CLKREQ_L TBT_DDC_XBAR_EN_L TBT_EN_CIO_PWR TBT_EN_CIO_PWR_L TBT_EN_LC_ISOL TBT_EN_LC_PWR TBT_PCH_CLKREQ_L TBT_PWR_EN TBT_PWR_EN_PCH TBT_PWR_ON_POC_RST_L TBT_PWR_REQ_L TBT_S0_EN TBT_SW_RESET_L 3.3V 86 I74 86 I75 I17 I18 I19 C I20 Netname SMB_PHY SMB_PHY SMB_PHY SMB_PHY SMB SMB SMB SMB SML_PCH_0_CLK SML_PCH_0_DATA SML_PCH_1_CLK SML_PCH_1_DATA 18 50 I47 I48 I49 I50 GENERIC_ISO SPI_DESCRIPTOR_OVERRIDE_L I51 I52 I21 15 47 I53 I54 I55 I56 I57 I58 SSD_* I59 I60 Spacing Netname GENERIC_ISO SSD_CLKREQ_L I61 I62 I22 15 18 34 D 88 36 88 38 VTTCLAMP_* 15 38 36 85 38 Spacing Netname GENERIC_ISO GENERIC_ISO VTTCLAMP_EN VTTCLAMP_L 36 38 38 I76 36 38 I77 28 28 15 21 15 26 36 18 26 36 38 15 20 36 WOL_* 64 21 38 Spacing Netname GENERIC_ISO WOL_EN 15 21 40 Electrical Physical Spacing Netname SNS_TEMP SNS_TEMP SNS_TEMP SNS_TEMP SNS_TEMP SNS_TEMP SNS_TEMP SNS_TEMP SNS_TEMP SNS_TEMP SNS_TEMP SNS_TEMP SNS_TEMP SNS_TEMP SNS_TEMP SNS_TEMP SNS_TEMP SNS_TEMP SNS_TEMP SNS_TEMP SNS_TEMP SNS_TEMP SNS_TEMP SNS_TEMP SNS_DIFF_PHY SNS_DIFF_PHY SNS_DIFF_PHY SNS_DIFF_PHY SNS_DIFF_PHY SNS_DIFF_PHY SNS_DIFF_PHY SNS_DIFF_PHY SNS_DIFF_PHY SNS_DIFF_PHY SNS_DIFF_PHY SNS_DIFF_PHY SNS_DIFF_PHY SNS_DIFF_PHY SNS_DIFF_PHY SNS_DIFF_PHY SNS_DIFF_PHY SNS_DIFF_PHY SNS_DIFF_PHY SNS_DIFF_PHY SNS_DIFF_PHY SNS_DIFF_PHY SNS_DIFF_PHY SNS_DIFF_PHY SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE TSNS_1_1_N TSNS_1_1_P TSNS_1_2_N TSNS_1_2_P TSNS_1_3_N TSNS_1_3_P TSNS_2_1_N TSNS_2_1_P TSNS_2_2_N TSNS_2_2_P TSNS_2_3_N TSNS_2_3_P TSNS_2_4_N TSNS_2_4_P TSNS_2_5_N TSNS_2_5_P TSNS_2_6_N TSNS_2_6_P TSNS_2_7_N TSNS_2_7_P TSNS_ACDC_N TSNS_ACDC_P TSNS_SKIN_N TSNS_SKIN_P 18 50 I46 Netname 34 18 50 I45 Spacing VREFMRGN_CA_SODIMMA_EN VREFMRGN_CA_SODIMMB_EN TSNS_* 18 50 I44 SPI_* GENERIC_ISO GENERIC_ISO 88 I78 Spacing Netname 36 86 SML_* Physical Spacing I63 I64 I65 I66 I67 C 53 53 53 53 53 53 53 53 53 53 53 53 53 53 53 53 53 53 53 53 53 53 53 53 SYS_* B I23 Spacing Netname PM SYS_PWROK_R B UVP_* 65 I68 I69 I70 I71 I72 I73 Spacing Netname PM PM PM PM PM PM UVP_IN_1 UVP_IN_1_REF UVP_IN_2 UVP_IN_3 UVP_IN_4 UVP_REF A 91 91 91 91 91 91 AUTO-CONSTRAINTS GENERATED Fri 04/06/12 07:24:10 PM PAGE TITLE A AUTO-CONSTRAINTS DRAWING NUMBER Apple Inc 051-9504 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED D 7.0.0 R NOTICE OF PROPRIETARY PROPERTY: SIZE REVISION BRANCH prefsb PAGE 143 OF 143 SHEET 117 OF 117 ... =PP3V3_S4_USB_HUB 0. 1UF 10K U 2 70 0 10% 16V X7R-CERM 04 02 C 2 70 4 10% 16V X7R-CERM 04 02 27 C 0. 1UF R 2 70 4 100 K 5% 1/16W MF-LF 402 R 2 70 5 100 K 5% 1/16W MF-LF 402 USB2412-DZK 102 R 271 11 R 271 01 5% 1/20W MF 201 5% 1/20W... DP_TBTSNK0_ML_N 1 07 36 100 K 5% 1/16W MF-LF 402 36 1 07 1 07 36 1 07 36 1 07 36 36 1 07 1 07 36 1 07 36 DP_TBTSNK0_ML_P 36 1 07 1 07 36 10% 16V X5R-CERM 02 01 0. 1UF 1 07 81 36 1 07 10% 16V X5R-CERM 02 01 0. 1UF... VSS _00 4 VSS _00 5 VSS _00 6 VSS _0 07 VSS _00 8 VSS _00 9 VSS _01 0 VSS _01 1 VSS _01 2 VSS _01 3 VSS _01 4 VSS _01 5 VSS _01 6 VSS _0 17 VSS _01 8 VSS _01 9 VSS _02 0 VSS _02 1 VSS _02 2 VSS _02 3 VSS _02 4 VSS _02 5 VSS _02 6 VSS_ 0 27 VSS _02 8