apple macbook unibody a1278 m97

8 REV ZONE ECN ENG APPD DESCRIPTION OF CHANGE DATE M97 MLB SCHEMATIC A 625211 PRODUCTION RELEASED DATE 08/29/08 ? REFERENCED FROM T18 08/27/2008 D (.csa) Date Page TABLE_TABLEOFCONTENTS_HEAD TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM B CK APPD ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5% ALL CAPACITANCE VALUES ARE IN MICROFARADS ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ C TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 Contents Sync Table of Contents (.csa) System Block Diagram 08/22/2007 TABLE_TABLEOFCONTENTS_HEAD 12/12/2007 TABLE_TABLEOFCONTENTS_ITEM 03/13/2008 TABLE_TABLEOFCONTENTS_ITEM T18_MLB Power Block Diagram DRAGON TABLE_TABLEOFCONTENTS_ITEM BOM Configuration M97_MLB TABLE_TABLEOFCONTENTS_ITEM Revision History M97_MLB 04/04/2008 JTAG Scan Chain TABLE_TABLEOFCONTENTS_ITEM BEN TABLE_TABLEOFCONTENTS_ITEM FUNC TEST M97_MLB Power Aliases BEN SIGNAL ALIAS M97_MLB 04/21/2008 TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM 10 CPU FSB 12/12/2007 TABLE_TABLEOFCONTENTS_ITEM 12/12/2007 TABLE_TABLEOFCONTENTS_ITEM 03/31/2008 TABLE_TABLEOFCONTENTS_ITEM 12/12/2007 TABLE_TABLEOFCONTENTS_ITEM T18_MLB 11 CPU Power & Ground T18_MLB 12 CPU Decoupling RAYMOND eXtended Debug Port (XDP) T18_MLB 13 14 MCP CPU Interface 04/04/2008 TABLE_TABLEOFCONTENTS_ITEM 04/04/2008 TABLE_TABLEOFCONTENTS_ITEM 04/04/2008 TABLE_TABLEOFCONTENTS_ITEM T18_MLB 15 MCP Memory Interface T18_MLB MCP Memory Misc T18_MLB MCP PCIe Interfaces T18_MLB 16 17 18 MCP Ethernet & Graphics 04/04/2008 TABLE_TABLEOFCONTENTS_ITEM 04/04/2008 TABLE_TABLEOFCONTENTS_ITEM 04/04/2008 TABLE_TABLEOFCONTENTS_ITEM 04/04/2008 TABLE_TABLEOFCONTENTS_ITEM 06/26/2008 TABLE_TABLEOFCONTENTS_ITEM 04/04/2008 TABLE_TABLEOFCONTENTS_ITEM 03/08/2008 TABLE_TABLEOFCONTENTS_ITEM T18_MLB 19 MCP PCI & LPC T18_MLB 20 MCP SATA & USB T18_MLB 21 MCP HDA & MISC T18_MLB 22 MCP Power & Ground T18_MLB MCP79 A01 Silicon Support T18_MLB 24 25 MCP Standard Decoupling 04/04/2008 TABLE_TABLEOFCONTENTS_ITEM 12/12/2007 TABLE_TABLEOFCONTENTS_ITEM 04/05/2008 TABLE_TABLEOFCONTENTS_ITEM 03/31/2008 TABLE_TABLEOFCONTENTS_ITEM 06/30/2008 TABLE_TABLEOFCONTENTS_ITEM 05/09/2008 TABLE_TABLEOFCONTENTS_ITEM 04/04/2008 TABLE_TABLEOFCONTENTS_ITEM T18_MLB 26 MCP Graphics Support T18_MLB 28 SB Misc RAYMOND 29 FSB/DDR3 Vref Margining BEN 31 DDR3 SO-DIMM Connector A BEN 32 DDR3 SO-DIMM Connector B BEN DDR3 Support T18_MLB 33 34 Right Clutch Connector VENICE CONNECTOR TABLE_TABLEOFCONTENTS_ITEM 03/13/2008 TABLE_TABLEOFCONTENTS_ITEM 05/23/2008 TABLE_TABLEOFCONTENTS_ITEM 07/01/2008 TABLE_TABLEOFCONTENTS_ITEM 04/04/2008 TABLE_TABLEOFCONTENTS_ITEM YITE 37 Ethernet PHY (RTL8211CL) SUMA 38 Ethernet & AirPort Support SUMA ETHERNET CONNECTOR SUMA 39 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 Contents 45 SATA Connectors External USB Connectors Front Flex Support SMC SMC Support M97 SMBUS CONNECTIONS TABLE_TABLEOFCONTENTS_ITEM P 05/28/2008 TABLE_TABLEOFCONTENTS_ITEM 05/09/2008 TABLE_TABLEOFCONTENTS_ITEM 04/21/2008 TABLE_TABLEOFCONTENTS_ITEM 02/04/2008 TABLE_TABLEOFCONTENTS_ITEM YUNWU 54 04/07/2008 Current Sensing 100 Sync 01/04/2008 CPU/FSB Constraints T18_MLB Memory Constraints T18_MLB MCP Constraints T18_MLB MCP Constraints T18_MLB Ethernet Constraints T18_MLB 101 102 103 104 106 01/04/2008 01/04/2008 12/14/2007 03/19/2008 T18_MLB M97 SPECIAL CONSTRAINTS M97_MLB M97 RULE DEFINITIONS M97_MLB 109 TABLE_TABLEOFCONTENTS_ITEM 03/20/2008 Thermal Sensors YUNWU 56 01/18/2008 Fan CHANGZHANG 57 04/22/2008 WELLSPRING YUAN.MA 58 05/09/2008 WELLSPRING YUAN.MA 59 06/26/2008 SMS YUNWU 61 05/02/2008 SPI ROM 01/04/2008 SMC Constraints 107 YUNWU 55 C CHANGZHANG 62 07/01/2008 AUDIO: CODEC AUDIO 63 07/03/2008 AUDI0: MIKEY AUDIO 66 07/01/2008 AUDI0: SPEAKER AMP AUDIO 67 07/01/2008 AUDIO: JACK 68 AUDIO m il AUDIO: JACK TRANSLATORS 69 DC-In & Battery Connectors 70 PBUS Supply/Battery Charger 72 5V/3.3V SUPPLY 73 1.5V/0.75V DDR3 SUPPLY 74 IMVP6 CPU VCore Regulator 75 MCP VCORE REGULATOR 76 07/01/2008 AUDIO 03/13/2008 JACK 01/31/2008 RAYMOND 02/08/2008 RAYMOND 01/31/2008 RAYMOND 01/31/2008 RAYMOND 01/31/2008 RAYMOND 02/08/2008 CPU VTT(1.05V) SUPPLY RAYMOND MISC POWER SUPPLIES RAYMOND 77 TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM BEN VOLTAGE SENSING 98 06/26/2008 CHANGZHANG 53 97 TABLE_TABLEOFCONTENTS_ITEM 71 72 73 74 75 76 77 78 Date Contents a n i LPC+SPI Debug Connector 52 94 05/28/2008 YUAN.MA 51 93 TABLE_TABLEOFCONTENTS_ITEM T18_MLB 50 90 TABLE_TABLEOFCONTENTS_HEAD YUAN.MA 49 79 04/14/2008 01/18/2008 YUAN.MA 48 78 Page CHANGZHANG 46 y r (.csa) Sync e r 04/22/2008 YITE 35 Date Page T17_MLB D 01/23/2008 04/22/2008 POWER SEQUENCING YUAN.MA POWER FETS YUAN.MA LVDS CONNECTOR NMARTIN DISPLAYPORT SUPPORT AMASON DisplayPort Connector AMASON LCD BACKLIGHT DRIVER YITE LCD Backlight Support YITE 04/04/2008 04/04/2008 04/18/2008 B 06/30/2008 08/12/2008 06/30/2008 PVT BUILD A DIMENSIONS ARE IN MILLIMETERS X.XX DRAFTER THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING ENG APPD MFG APPD QA APPD DESIGNER RELEASE SCALE I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART ANGLES QTY DESCRIPTION REFERENCE DES CRITICAL 051-7537 SCHEM,MLB,M97 SCH CRITICAL 820-2327 PCBF,MLB,M97 PCB CRITICAL A NOTICE OF PROPRIETARY PROPERTY DESIGN CK X.XXX Schematic / PCB #’s PART NUMBER APPLE INC METRIC XX TITLE DO NOT SCALE DRAWING BOM OPTION SCHEM,MLB,M97 NONE SIZE THIRD ANGLE PROJECTION MATERIAL/FINISH NOTED AS APPLICABLE D DRAWING NUMBER REV 051-7537 A SHT 1 OF 109 U1000 U1300 INTEL CPU XDP CONN 2.X OR 3.X GHZ PG 12 PENRYN PG FSB D D J6950 64-Bit 800/1067/1333 MHz y r DC/BATT POWER SUPPLY PG 13 PG 60 J2900 UDIMMs MAIN FSB INTERFACE GPIOs DDR2-800MHZ DDR3-1067/1333MHZ MEMORY DIMM PG 14 U4900 PG 25,26 TEMP SENSOR PG 41 Misc a n i CLK PG 24 U6100 SYNTH POWER SENSE PG 45 SPI Boot ROM J4510 J5650,5600,5610,5611,5660,5720,5730,5750 FAN CONN AND CONTROL SPI SATA PG 52 Conn 1.05V/3GHZ PG 48,49 PG 20 PG 38 HD NVIDIA J4520 J4900 B,0 SATA Conn C LPC ODD Prt LPC Conn Port80,serial C PG 43 PG 18 J9000 PWR LVDS CONN CTRL LVDS OUT PG 71 m il RGB OUT J4720 DP OUT HDMI OUT PG 16 PCI-E PCI (UP TO FOUR PORTS) PG 17 PG 18 P PG 39 UP TO 20 LANES3 e r RGMII EXTERNAL USB Connectors PG 40 PG 40 PG 17 PG 40 J3900,4635,4655 CAMERA USB TMDS OUT J4710 IR DVI OUT PG 71 J4710 TRACKPAD/ KEYBOARD PG 40 PG 19 DISPLAY PORT CONN J4700 Bluetooth (UP TO 12 DEVICES) J9400 A Ser PG 41 U1400 B Fan SMC PG 19 PG 38 ADC BSB J5100 MCP79 SATA 1.05V/3GHZ B SMB SMB PG 20 CONN HDA PG 44 DIMM’s PG 20 U6200 Audio Codec PG 53 U6301 U6400 U6500 System Block Diagram U6600,6605,6610,6620 U3700 GB Line In Line Out Speaker E-NET Amp Amp Amp Amps PG 54 PG 55 PG 56 PG 57 HEADPHONE SYNC_MASTER=T18_MLB SYNC_DATE=12/12/2007 NOTICE OF PROPRIETARY PROPERTY 88E1116 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING PG 31 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE J3400 II NOT TO REPRODUCE OR COPY IT U3900 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART Mini PCI-E J6800,6801,6802,6803 E-NET AirPort Conn PG 28 Audio SIZE Conns D PG 33 PG 59 APPLE INC DRAWING NUMBER SCALE SHT NONE REV 051-7537 A OF 109 A M97 POWER SYSTEM ARCHITECTURE D6905 02 PPVIN_G3H_P3V42G3H D6905 V 7A FUSE PPVBAT_G3H_CHGR_REG D ENABLE VIN SMC_BATT_ISENSE ISL6258A U7000 CPU VCORE A SMC_CPU_ISENSE PPVCORE_CPU_S0_REG (44A MAX CURRENT) VOUT VIN J6950 ISL9504B IMVP_VR_ON Q7050 VR_ON 28 25 PPVBAT_G3H_CHGR_OUT SMC_CPU_VSENSE V U5480 01 VR_PWRGOOD_DELAY PGOOD U7400 06 P1V05S0_EN 1.05V SO PP1V05_S0_FET FETS CHGR_BGATE PPBUS_G3H (Q7951 TO Q7953) 1.05V (S5) 26 22 4.6V AUDIO MAX8902A VIN U6201 MCP79 11 11-1 P3V3S3_EN RC DELAY PM_SLP_S4_L 11-3 RC DELAY U1400 P60 P5VRTS0_EN_L 04 U4900 DDRREG_EN SMC_PM_G2_EN 05 Q7800 (S5) P3V3S5_EN_L 02 11-2 e r VIN BKLT_EN B GOSHAWK6P U9701 ENA VOUT 15 PM_SLP_S3_L 1.2V YUKON VIN U3850 Q3801 PM_ENET_EN_L PPVOUT_S0_LCDBKLT ENETADD_EN 16 Q3802 WOL_EN SMC_ADAPTER_EN 04-1 P 02 VIN =DDRREG_EN =DDTVTT_EN PM_SLP_S3_L A RC DELAY RC DELAY RC DELAY RC DELAY P1V8S0_EN 16-3 MCPDDR_EN 16-2 CPUVTTS0_EN MCPCORES0_EN 16-3 16-4 16-2 P1V05S0_EN (S0) P3V3S0_EN (S0) PBUSVSENS_EN (S0) P5VRTS0_EN_L (S0) S5 S3 PP5VRT_S0_REG VOUT1 (4A MAX CURRENT) VOUT2 3.3V EN2 (4A MAX CURRENT) Q7910 PGOOD1,2 VOUT2 RESET* U1000 07 PP3V3_S3_FET 13 RSMRST_OUT(P15) PP3V3_S0_FET PWRGD(P12) 18 09 RSMRST_PWRGD SMC_ONOFF_L 05 MCPCORESO_PGOOD CPUVTTS0_PGOOD SLP_S5_L 99ms DLY IMVP_VR_ON(P16) RSMRST_IN(P13) PLT_RST* PWR_BUTTON(P90) P17(BTN_OUT) IMVP_VR_ON B 25 PM_PWRBTN_L SMC_RESET_L SLP_S4_L(P94) SLP_S3_L SLP_S3_L(P93) U4900 S0PGOOD_PWROK 21 10 SLP_S5_L(P95) SLP_S4_L P5V_LT_S3_PGOOD PP1V5_S0 PM_RSMRST_L RST* R5491 PP1V5_S0_FET 1.8V LDO 14 TPS79918DRV U7760 TPS51116 U7300 PP1V8_S0_REG 19-1 RST* PP0V75_S0_REG (1A MAX CURRENT) PP3V3_S0 V1 PP1V5_S0 V2 PP1V05_S0 20 EN2 SMC 24 ALL_SYS_PWRGD P3V3S0_EN Q3810 P3V3_ENET_FET PP1V5_S3_REG (12A MAX CURRENT) VOUT2 32 17 P5V3V3_PGOOD VOUT1 MCP_CORE C CPU PWRGOOD PP3V3_S5 P3V3ENET_EN_L 1.5V MCPCORES0_EN U1400 PP4V6_AUDIO_ANALOG PP5VRT_S0 Q7930 (Q7901 & Q7971) 16-2 30 CPU_RESET# P3V3S3_EN (0.8A MAX CURRENT) S3 TO S0 FETS 0.75V VOUT2 U2850 P5V3V3_PGOOD PP1V2_ENET_REG RUN2 CPU_PWRGD CPUPWRGD(GPIO49) VREG3 (0.8A MAX CURRENT) LTC34074 P1V2ENET_EN 5V (RT) 29 (1.9V) PPVOUT_ENET_AVDD_REG VOUT1 RUN1 VIN EN1 TPS51125 U7200 SMC_PM_G2_EN P5VLTS3_EN RC DELAY 08 PP3V3_S5_REG PCI_RESET0# 15-1 VOUT RSMRST* MCP_PS_PWRGD PS_PWRGD PP1V05_S5_REG m il P16 15 U7750 02 SMC SLP_S3# TPS62510 06 P1V05_S5_EN 31 LPC_RESET_L PLTRST* VOUT EN 06-1 PWRBTN* FSB_CPURST_L a n i CPUVTTS0_PGOOD 02 BATT_POS_F MCP79 PGOOD A SMC_DCIN_ISENSE (9 TO 12.6V) PPCPUVTT_S0 TPS51117 U7600 U5403 VOUT PBUS SUPPLY/ BATTERY CHARGER C VOUT CPUVTT ENABLES A 3S2P y r R5492 PPCPUVTT_S0_REG_R (8A MAX CURRENT) (1.05V) U7970 6A FUSE D 23 VIN EN_PSV 04 U5000 02 CPUVTTS0_EN (S0) CHGR_EN (S5) SMC PWRGD RN5VD30A-F Q5315 PPBUS_G3H 01 AC DCIN(16.5V) ADAPTER IN PP3V42_G3H_REG 03 3.425V G3HOT LT3470 VOUT U6990 PBUS_VSENSE R5490 PPVCORE_S0_MCP_REG_R V3 Power Block Diagram SYNC_MASTER=DRAGON LTC2909 U7870 SYNC_DATE=03/13/2008 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING PPVCORE_S0_MCP (25A MAX CURRENT) I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT P5VLTS3_EN 16-2 5V (LT) 11-2 EN1 PP5VLT_S3_REG 12 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART PP5VLT_S3 VOUT1 SIZE (7A MAX CURRENT) 02 DRAWING NUMBER D VIN 16-1 APPLE INC ISL6236 U7500 SCALE SHT NONE REV 051-7537 A OF 109 A BOM Variants Bar Code Labels / EEE #’s TABLE_BOMGROUP_HEAD BOM NUMBER BOM NAME BOM OPTIONS 630-9554 PCBA,MLB,BETTER,M97 M97_COMMON,CPU_2_0GHZ,EEE_2KA PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION TABLE_BOMGROUP_ITEM 826-4393 LBL,P/N LABEL,PCB,28MM X MM [EEE:2K9] CRITICAL EEE_2K9 826-4393 LBL,P/N LABEL,PCB,28MM X MM [EEE:2KA] CRITICAL EEE_2KA 826-4393 LBL,P/N LABEL,PCB,28MM X MM [EEE:1DJ] CRITICAL EEE_1DJ TABLE_BOMGROUP_ITEM 630-9314 PCBA,MLB,BEST,M97 M97_COMMON,CPU_2_4GHZ,EEE_1DJ BOM Groups D D TABLE_BOMGROUP_HEAD BOM GROUP BOM OPTIONS M97_COMMON COMMON,ALTERNATE,M97_MCP,M97_MISC,M97_DEBUG_PVT,M97_PROGPARTS M97_MCP MCP_B02,MCP_PROD,MEMRESET_HW,MEMRESET_MCP,BOOT_MODE_USER,MCPSEQ_SMC,MCP_CS1_NO M97_MISC ONEWIRE_PU,BKLT_PLL_NOT,DP_ESD,ENG_BMON,MIKEY M97_PROGPARTS BOOTROM_PROG,SMC_PROG,IR_PROG,WELLSPRING_PROG M97_DEBUG_ENG SMC_DEBUG_YES,XDP,XDP_CONN,LPCPLUS,VREFMRGN,TPAD_DEBUG M97_DEBUG_PVT SMC_DEBUG_YES,XDP,LPCPLUS,NO_VREFMRGN M97_DEBUG_PROD SMC_DEBUG_YES,XDP,LPCPLUS_NOT,NO_VREFMRGN TABLE_BOMGROUP_ITEM y r TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM a n i Module Parts PART NUMBER C DESCRIPTION REFERENCE DES 337S3622 QTY PDC,QJGL,QS,2.0,25W,1066,M0,3M,BGA U1000 CRITICAL CRITICAL BOM OPTION CPU_2_0GHZ_QS 337S3624 PDC,QDYD,QS,2.26,25W,1066,M0,3M,BGA U1000 CRITICAL CPU_2_26GHZ_QS 337S3625 PDC,QDYJ,QS,2.4,25W,1066,M0,3M,BGA U1000 CRITICAL CPU_2_4GHZ_QS 337S3646 PDC,SLG8E,PRQ,2.0,25W,1066,M0,3M,BGA U1000 CRITICAL CPU_2_0GHZ 337S3653 PDC,SL3BU,PRQ,2.26,25W,1066,C0,3M,BGA U1000 CRITICAL CPU_2_26GHZ 337S3639 PDC,SLB4N,PRQ,2.4,25W,1066,M0,3M,BGA U1000 CRITICAL CPU_2_4GHZ 338S0540 IC,GMCP,MCP79,35X35MM,BGA1437,A01 U1400 CRITICAL MCP_A01 338S0591 IC,GMCP,MCP79,35X35MM,BGA1437,A01P U1400 CRITICAL MCP_A01P 338S0603 IC,GMCP,MCP79,35X35MM,BGA1437,A01Q U1400 CRITICAL MCP_A01Q 338S0600 IC,GMCP,MCP79,35X35MM,BGA1437,B01 U1400 CRITICAL MCP_B01 338S0635 IC,GMCP,MCP79,35X35MM,BGA1437,B02 U1400 CRITICAL MCP_B02 338S0570 IC,RTL8211CL,GIGE TRANSCEIVER,48P,TQFP U3700 CRITICAL m il Programmable Parts 338S0563 IC,SMC,HS8/2117,9X9MM,TLP,HF U4900 CRITICAL 341S2287 IC,SMC,M97 U4900 CRITICAL SMC_BLANK SMC_PROG 335S0610 IC,FLASH,SPI,32MBIT,3.3V,86MHZ,8-SOP U6100 CRITICAL BOOTROM_BLANK 341S2285 IC,PRGRM,EFI BOOTROM,UNLOCK,M97 U6100 CRITICAL BOOTROM_PROG 338S0375 IC,CY7C63833,ENCORE II,USB CONTROLLER U4800 CRITICAL IR_BLANK 341S2093 IC,IR CONTROLLER,M97 U4800 CRITICAL IR_PROG 337S2983 IC,PSOC+ W/ USB,56 PIN,MLF,CY8C24794 U5701 CRITICAL WELLSPRING_BLANK 341S2348 IC,WELLSPRING CONTROLLER,M97 U5701 CRITICAL WELLSPRING_PROG e r B Alternate Parts TABLE_ALT_HEAD PART NUMBER ALTERNATE FOR PART NUMBER BOM OPTION REF DES COMMENTS: 152S0778 152S0693 ALL CYNTEC AS ALTERNATE 152S0796 152S0685 ALL CYNTEC AS ALTERNATE 152S0694 152S0138 ALL MAGLAYERS AS ALTERNATE 157S0058 157S0055 ALL DELTA AS ALTERNATE 104S0018 104S0023 ALL DALE/VISHAY AS ALTERNATE 128S0093 128S0218 ALL KEMET AS ALTERNATE 152S0874 152S0516 ALL MAGLAYERS AS ALTERNATE 152S0847 152S0586 ALL MAGLAYERS AS ALTERNATE 514-0612 514-0607 ALL FOXLINK AS ALTERNATE 514-0613 514-0608 ALL FOXLINK AS ALTERNATE TABLE_ALT_ITEM TABLE_ALT_ITEM TABLE_ALT_ITEM TABLE_ALT_ITEM TABLE_ALT_ITEM TABLE_ALT_ITEM TABLE_ALT_ITEM TABLE_ALT_ITEM TABLE_ALT_ITEM TABLE_ALT_ITEM A P C M97 BOARD STACK-UP Top 10 11 BOTTOM SIGNAL GROUND SIGNAL(High SIGNAL(High GROUND POWER POWER GROUND SIGNAL(High SIGNAL(High GROUND SIGNAL Speed) Speed) B Speed) Speed) BOM Configuration SYNC_MASTER=M97_MLB A NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC SCALE SHT NONE REV 051-7537 A OF 109 Revision History D D y r a n i C C m il e r B P A B A SYNC_MASTER=M97_MLB A NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC NOTE: All page numbers are csa, not PDF SCALE SHT NONE See page for csa -> PDF mapping REV 051-7537 A OF 109 D D 1.05V TO 3.3V LEVEL TRANSLATOR (M97: ON ICT FIXTURE) y r =PP3V3_S0_XDP 13D6 8C5 To XDP connector and/or level translator =PP1V05_S0_CPU 12B6 11C6 10D5 8D7 13D6 U1000 CPU From XDP connector JTAG_ALLDEV C0601 JTAG_ALLDEV 0.1UF C0602 0.1UF 20% 10V CERM 402 20% 10V CERM 402 71A3 13B6 10C6 10A6 6C7 IN 71A3 13B3 10C6 10B6 IN 71A3 13B3 10C6 10B6 6C7 IN 71A3 13B3 10C6 10A6 6C7 IN XDP_TCK XDP_TDI XDP_TMS XDP_TRST_L XDP a n i R0603 71A3 10C6 10B6 XDP_TDO XDP_TDO_CONN 5% 1/16W MF-LF 402 JTAG_ALLDEV R06011 11 10K 5% 1/16W MF-LF 402 From XDP connector or via level translator VCCA VCCB U0600 C U1400 MCP NLSV4T244 71A3 13B6 10C6 10A6 6C6 XDP_TCK NOSTUFF R06021 5% 1/16W MF-LF 402 71A3 13B3 10C6 10B6 6C6 71A3 13B3 10C6 10A6 6C6 XDP_TMS XDP_TRST_L JTAG_LVL_TRANS_EN_L 12 UQFN A1 A2 A3 JTAG_ALLDEV A4 B1 B2 B3 B4 JTAG_MCP_TCK JTAG_MCP_TDI JTAG_MCP_TMS JTAG_MCP_TRST_L 10 13B6 21B7 13B3 C XDP 13C3 21B7 23C5 R0604 13C3 21B7 23C5 13C3 21B7 OUT XDP connector 21B7 JTAG_MCP_TDO JTAG_MCP_TDO_CONN 5% 1/16W MF-LF 402 OE* GND OUT 13C3 XDP connector m il e r B P A B JTAG Scan Chain SYNC_MASTER=BEN SYNC_DATE=04/04/2008 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC SCALE SHT NONE REV 051-7537 A OF 109 A Functional Test Points RIGHT CLUTCH CONN PP5V_S3_BTCAMERA_F TRUE PCIE_MINI_D2R_P TRUE PCIE_MINI_D2R_N TRUE PCIE_MINI_R2D_P TRUE PCIE_MINI_R2D_N TRUE PCIE_CLK100M_MINI_CONN_P TRUE PCIE_CLK100M_MINI_CONN_N TRUE USB_CAMERA_CONN_P TRUE USB_CAMERA_CONN_N TRUE PP5V_WLAN TRUE PCIE_WAKE_L TRUE SMBUS_SMC_A_S3_SCL TRUE SMBUS_SMC_A_S3_SDA TRUE CONN_USB2_BT_P TRUE CONN_USB2_BT_N TRUE MINI_CLKREQ_Q_L TRUE MINI_RESET_CONN_L TRUE Fan Connectors D I12 I15 I16 TRUE TRUE TRUE PP5VRT_S0 FAN_RT_PWM FAN_RT_TACH (NEED TP) 7D3 8D5 I303 46B4 I301 (NEED TO ADD GND TP) I238 I237 I239 31B7 I227 I298 I293 54B1 54D2 54B1 54D2 I226 54D2 55A6 I228 I230 I229 I231 I232 I233 I259 I258 C I260 I245 I262 I261 I256 I257 I255 I252 I253 I254 I250 I251 I313 I246 I247 I248 I249 53C3 54C2 I290 53C3 54C2 I271 53B2 54C2 I289 I269 I267 I265 I266 B I312 I304 I321 I320 THERMAL FUNC_TEST MCPTHMSNS_D2_P TRUE MCPTHMSNS_D2_N TRUE LVDS FUNC_TEST PP3V3_LCDVDD_SW_F TRUE PP3V3_S0_LCD_F TRUE PPVOUT_S0_LCDBKLT TRUE LVDS_IG_DDC_CLK TRUE LVDS_IG_DDC_DATA TRUE LVDS_IG_A_DATA_N TRUE LVDS_IG_A_DATA_P TRUE LVDS_IG_A_DATA_N TRUE LVDS_IG_A_DATA_P TRUE LVDS_IG_A_DATA_N TRUE LVDS_IG_A_DATA_P TRUE LVDS_IG_A_CLK_F_N TRUE LVDS_IG_A_CLK_F_P TRUE LED_RETURN_1 TRUE LED_RETURN_2 TRUE LED_RETURN_3 TRUE LED_RETURN_4 TRUE LED_RETURN_5 TRUE LED_RETURN_6 TRUE 31B7 74B3 45B5 77D3 I314 45B5 77D3 I315 I318 I317 7C3 66C2 I316 I325 I310 I311 I309 I308 I307 I393 (NEED TP) I392 7C3 36A7 I391 36A7 73A3 I390 36A7 73A3 I389 36A7 73A3 I388 36A7 73A3 I387 7B7 36B5 73A3 I386 I385 7C3 66B2 69B3 69C1 I384 18A3 66C5 18A3 66B5 18B3 66C2 73B3 I375 18B3 66C2 73B3 I374 18B3 66C2 73B3 I373 18B3 66C2 73B3 I372 18B3 66C2 73B3 I370 18B3 66C2 73B3 I371 66B2 73B3 I369 66B2 73B3 I368 66B3 69C1 I361 66B3 69B1 I366 66B3 69B1 I367 66B3 69B1 I365 66B3 69B1 I363 66B3 69B1 I364 47C8 48C3 48C3 48C5 47D8 48C3 47C8 48C3 47B6 48C3 47C8 48C1 47C8 48C1 47C8 48C1 47C8 48C1 e r I377 36B5 73A3 I378 36B5 73A3 36B5 73A3 7C5 36B5 73A3 KEYBOARD CONN I354 I355 I344 I345 P I348 (NEED TP) (NEED TP) 7A7 42C5 76D3 I350 56A8 I352 56A8 I351 I353 7A7 42C5 76D3 I327 39C5 40B2 56A8 BATT SIGNAL CONN (NEED TP) PP3V42_G3H TRUE SMBUS_SMC_BSA_SCL TRUE SMBUS_SMC_BSA_SCL TRUE SMC_BIL_BUTTON_DB_L TRUE I342 I341 7B5 7C3 8D1 I339 7A7 42C5 76D3 7A7 42C5 76D3 56A5 I340 I338 I336 (NEED TO ADD GND TP) I337 FRONT FLEX CONN PP3V42_G3H_LIDSWITCH_R TRUE PP5V_S3_IR_R TRUE IR_RX_OUT TRUE SMC_LID_R TRUE SYS_LED_ANODE_R TRUE 38B6 I335 38B6 8D7 8C7 y r 8C7 8C7 8B7 8B7 7D7 8D5 8C5 8D3 7B5 8D3 8C3 8B3 8B3 7A7 7B5 8D1 8C1 8B1 8B1 21C8 22A5 26D4 7D5 31C5 7B7 36D3 7C5 36A7 39D4 40B6 7C5 48C1 48D3 7C5 48B4 48C3 7C7 66C2 7C7 66B2 69B3 69C1 C 69A8 69B6 69C4 69C8 51A3 51D3 52D6 39D5 64D8 21C3 39C5 40A2 64C8 21C3 34B7 39C5 41A5 64D5 68D8 47C8 48C1 I358 BATT POWER CONN PPVBAT_G3H_CONN_F TRUE GND_BATT_CONN TRUE SMBUS_SMC_BSA_SCL TRUE SMBUS_SMC_BSA_SCL TRUE SMC_BS_ALRT_L TRUE D 8D7 m il 47C8 48C3 36B7 39B8 56D7 PPVCORE_S0_CPU PPCPUVTT_S0 PPVCORE_S0_MCP PP0V75_S0 PP1V05_S0 PP1V5_S0 PP1V8_S0 PP5VRT_S0 PP3V3_S0 PP1V5_S3 PP3V3_S3 PP5VLT_S3 PP1V1R1V05_S5 PP3V3_S5 PP3V42_G3H PPBUS_G3H PP3V3_ENET_PHY PP1V2R1V05_ENET PP3V3_G3_RTC PP5V_WLAN PP5V_SW_ODD PP5V_S0_HDD_FLT PP3V3_S5_AVREF_SMC PP18V5_S3 PP3V3_S3_LDO PP3V3_LCDVDD_SW_F PPVOUT_S0_LCDBKLT BKL_VREF_4V9 PP4V6_AUDIO_ANALOG SMC_PM_G2_EN PM_SLP_S4_L PM_SLP_S3_L (NEED TO ADD GND TP) 47C8 48C3 I357 (NEED TP) 56D6 I380 47C8 48C3 36D3 (NEED TO ADD GND TP) I381 47C8 48C3 (NEED TO ADD GND TP) DC POWER CONN PP18V5_DCIN_FUSE TRUE ADAPTER_SENSE TRUE I382 7C3 48C1 48D3 I359 TP) 7C3 I383 48B4 48C3 48C4 48C7 I362 SATA ODD CONN (NEED PP5V_SW_ODD TRUE SMC_ODD_DETECT TRUE SATA_ODD_D2R_C_P TRUE SATA_ODD_D2R_C_N TRUE SATA_ODD_R2D_P TRUE SATA_ODD_R2D_N TRUE IPD_FLEX_CONN PP3V3_S3_LDO TRUE PP18V5_S3 TRUE TPAD_GND_F TRUE Z2_CS_L TRUE Z2_DEBUG3 TRUE Z2_MOSI TRUE Z2_MISO TRUE Z2_SCLK TRUE Z2_BOOST_EN TRUE Z2_HOST_INTN TRUE Z2_BOOT_CFG1 TRUE Z2_CLKIN TRUE Z2_KEY_ACT_L TRUE Z2_RESET TRUE PSOC_MISO TRUE PSOC_MOSI TRUE PSOC_SCLK TRUE SMBUS_SMC_A_S3_SDA TRUE SMBUS_SMC_A_S3_SCL TRUE PSOC_F_CS_L TRUE PICKB_L TRUE 7C3 48B4 48C3 I333 A I276 (NEED TO ADD GND TP) 66C3 I343 I324 I275 31A7 SATA HDD CONN PP5V_S0_HDD_FLT TRUE SATA_HDD_R2D_P TRUE SATA_HDD_R2D_N TRUE SATA_HDD_D2R_C_P TRUE SATA_HDD_D2R_C_N TRUE SATA_ODD_R2D_N TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE a n i I274 31C7 I319 I329 I323 I273 I272 I328 I326 I379 (NEED TO ADD GND TP) I349 I322 I270 31B7 74B3 I347 I306 I278 7B5 42D2 76D3 I346 I305 I279 7B5 42D2 76D3 I360 I268 I283 53B2 54C2 (NEED TO ADD GND TP) I264 I376 17B6 23C5 31C7 I296 I295 I282 7C3 31C5 I292 53B2 54C2 I281 31C8 73D3 31B7 74C3 I294 I291 I280 31C8 73D3 31B7 74C3 I297 53A2 54C2 I284 31C7 73D3 I299 FUNC_TEST SPKRAMP_L_N_OUT SPKRAMP_L_P_OUT SPKRAMP_R_N_OUT SPKRAMP_R_P_OUT SPKRAMP_SUB_N_OUT SPKRAMP_SUB_P_OUT I285 31C7 73D3 I288 SPEAKER TRUE TRUE TRUE TRUE TRUE TRUE I286 17B6 31C7 73D3 I300 MIC FUNC_TEST MIC_HI_CONN TRUE MIC_LO_CONN TRUE MIC_SHLD_CONN TRUE I287 17B6 31C7 73D3 I302 46C4 DEBUG VOLTAGE I334 I332 I330 38A4 38C4 I331 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE 7C5 42D2 76D3 7D5 42D2 76D3 47C8 48C1 47D8 48C1 PP3V3_S3 PP3V42_G3H WS_KBD1 WS_KBD2 WS_KBD3 WS_KBD4 WS_KBD5 WS_KBD6 WS_KBD7 WS_KBD8 WS_KBD9 WS_KBD10 WS_KBD11 WS_KBD12 WS_KBD13 WS_KBD14 WS_KBD15_CAP WS_KBD16_NUM WS_KBD17 WS_KBD18 WS_KBD19 WS_KBD20 WS_KBD21 WS_KBD22 WS_KBD23 WS_KBD_ONOFF_L WS_LEFT_SHIFT_KBD WS_LEFT_OPTION_KBD WS_CONTROL_KBD B 7D3 8D3 7A7 7C3 8D1 47C6 47D2 47C6 47D2 47C6 47D2 47C6 47D2 47C6 47D2 47C6 47D2 47C6 47D2 47C6 47D2 47C6 47D2 47C6 47D2 47C2 47C6 47C2 47C6 47C2 47C6 47C2 47C6 47C2 47C2 47C2 47C6 47C2 47D7 47C2 47D7 47C2 47D7 FUNC TEST 47C2 47D7 47C2 47D7 SYNC_MASTER=M97_MLB 47C2 47D7 47B3 47B5 47C2 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING 47B3 47B5 47C2 47B3 47B5 47C2 (NEED TO ADD GND TP) 38B6 A NOTICE OF PROPRIETARY PROPERTY 47C2 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE 38B6 II NOT TO REPRODUCE OR COPY IT (NEED TO ADD GND TP) III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART I356 KBD BACKLIGHT CONN KBDLED_ANODE TRUE SIZE DRAWING NUMBER D 48A4 (NEED TO ADD GND TP) APPLE INC SCALE SHT NONE REV 051-7537 A OF 109 "S0,S0M" RAILS =PPVCORE_S0_CPU_REG (CPU VCORE PWR) PPVCORE_S0_CPU 58B8 =PP5VRT_S0_REG =PPVCORE_S0_CPU =PPVCORE_S0_CPU_VSENSE PP5VRT_S0 =PP5V_S0_HDD =PP5V_S0_LPCPLUS =PP5V_S0_FAN_RT 11B5 11D6 12D6 43D8 D =PP5V_S0_CPU_IMVP =PPCPUVTT_S0_REG 65A6 62C2 PPCPUVTT_S0 =PP5V_S0_ODD =PP5V_S0_KBDLED =PP5V_S0_DP_AUX_MUX =PP5V_S0_CPUVTTS0 7D3 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V MAKE_BASE=TRUE =PP1V05_S0_CPU =PP1V05_S0_MCP_FSB =PP1V05_S0_SMC_LS 61C1 44D8 =PPMCPCORE_S0_REG =PP1V5_S3_REG PP1V5_S3 (MCP VCORE REG OUTPUT) 46C5 36D5 65D6 =PP3V3_S3_FET PP3V3_S3 65D3 28D7 29D7 30C6 67B6 62C8 =PP3V3_S3_SMBUS_SMC_A_S3 =PP3V3_S3_PDCISENS =PP3V3_S3_SMBUS_SMC_MGMT =PP3V3_S3_VREFMRGN =PP3V3_S3_WLAN =PP3V3_S3_MCP_GPIO =PP3V3_S3_TPAD =PP3V3_S3_SMS 6D8 10D5 11C6 12B6 13D6 40D3 MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V MAKE_BASE=TRUE 42D3 59B3 42B5 27D8 31A6 21A3 47A6 47B5 47C5 47D2 49B7 49D6 a n i 43D8 =PP5VLT_S3_REG PP5VLT_S3 7D3 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5V MAKE_BASE=TRUE =PPVCORE_S0_MCP PPVCORE_S0_MCP (MCP VCORE AFTER SENSE RES) C 59C8 =PP0V75_S0_REG 7D3 MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V MAKE_BASE=TRUE PP0V75_S0 65C6 =PP3V3_S0_FET =PP3V3_S0_XDP =PP3V3_S0_MCP =PP3V3_S0_MCP_DAC_UF =PP3V3_S0_MCP_VPLL_UF =PP3V3_S0_ODD =PP3V3_S0_LPCPLUS =PP3V3_S0_SMBUS_SMC_0_S0 =PP3V3_S0_SMBUS_SMC_B_S0 =PP3V3_S0_SMBUS_MCP_0 =PP3V3_S0_FAN_RT =PP3V3_S0_AUDIO 7D3 65B3 28A4 29A4 =PP3V3_S0_IMVP 65A5 =PP1V05_S0_FET PP1V05_S0 =PP1V05_S0_MCP_PEX_DVDD =PP1V05_S0_MCP_AVDD_UF =PP1V05_S0_MCP_PLL_UF =PP1V05_S0_MCP_SATA_DVDD =PP1V05_S0_MCP_HDMI_VDD =PP1V05_S0_VMON 44C8 =PP1V5_S0_FET =PP3V3_S0_MCP_PLL_UF 8A8 24D8 =PP3V3R1V5_S0_MCP_HDA =PP3V3_S0_SMC =PP3V3_S0_MCPTHMSNS =PP3V3_S0_CPUTHMSNS =PP5VR3V3_S0_MCPCOREISNS =PP3V3_S0_DPCONN =PPSPD_S0_MEM_A =PPSPD_S0_MEM_B =PP3V3_S0_PWRCTL =PP3V3_S0_VMON =PP3V3_S0_MCPDDRISNS =PP3V3_S0_CPUVTTISNS =PPVIN_S0_P1V8S0 =PP3V3_FC_CON =PP3V3_S0_TPAD =PP3V3_S0_SMBUS_MCP_1 24D4 24C4 8A8 24D6 18A6 25D7 64A8 PP1V5_S0_R =PP1V5_S0_FET_R (DDR PWR REG OUTPUT) MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.5V MAKE_BASE=TRUE =PP1V5_S0_CPU =PP1V5_S0_VMON =PP1V5_FC_CON e r 11B6 12B6 64A8 32C3 B =PP1V5_S0 (DDR PWR AFTER SENSE RES.) 44C7 PP1V5_S0 7D3 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.5V MAKE_BASE=TRUE =PP1V8R1V5_S0_MCP_MEM =PP1V5_S0_MEM_MCP 63C2 =PP1V8_S0_REG PP1V8_S0 16C3 16C7 24C8 29B3 P 7D3 MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.8V MAKE_BASE=TRUE =PP3V3R1V8_S0_MCP_IFP_VDD 18B6 25D7 PEX & SATA AVDD/DVDD aliases 24D1 =PP1V05_S0_MCP_PEX_AVDD0 =PP1V05_S0_MCP_PEX_AVDD1 PP1V05_S0_MCP_PEX_AVDD MAKE_BASE=TRUE 206 mA (A01) A 24D8 8B7 =PP1V05_S0_MCP_PEX_DVDD0 =PP1V05_S0_MCP_PEX_DVDD1 =PP1V05_S0_MCP_PEX_DVDD 206 mA (A01) 24C2 =PP1V05_S0_MCP_SATA_AVDD0 =PP1V05_S0_MCP_SATA_AVDD1 PP1V05_S0_MCP_SATA_AVDD MAKE_BASE=TRUE 6D8 13D6 21C2 22B3 24B8 25D4 25B7 36B7 36D5 41C3 42D5 42C3 42D8 46C5 51A7 51D8 52D6 54D8 55B5 m il =PP3V3_S0_LCD =PP3V3_S0_MCP_GPIO =PP3V3_S0_HDCPROM 7D3 MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.1V MAKE_BASE=TRUE 65D1 =PP5V_S3_EXTUSB =PP5V_S3_IR =PP5V_S3_BTCAMERA =PP5V_S3_VTTCLAMP =PP5V_S3_MCPDDRFET =PP5V_S3_SYSLED =PP5V_S3_TPAD =PP5V_S3_WLAN =PP5V_S3_1V5S30V75S0 =PP5V_S3_AUDIO =PP5V_S3_AUDIO_AMP =PP5V_S3_P1V05S0FET 7D3 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V MAKE_BASE=TRUE MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0.75V MAKE_BASE=TRUE =PPVTT_S0_VTTCLAMP =PP0V75_S0_MEM_VTT_A =PP0V75_S0_MEM_VTT_B PP3V3_S0 60D8 66C5 59D7 27D3 =PPVTT_S3_DDR_BUF 18C1 19D1 21A4 25B8 24B6 21D3 21D8 24A8 40A1 40D2 45C6 45D6 44D7 37C7 56D1 56B8 57C1 =PP18V5_DCIN_CONN =PPBUS_G3H 38B4 38D7 31B3 65A3 65D4 40B8 48C8 31C1 59C5 =PP1V05_S0_MCP_SATA_DVDD =PP1V05_S0_MCP_SATA_DVDD0 =PP1V05_S0_MCP_SATA_DVDD1 127 mA (A01) =PP3V3_S5_SMC =PP3V3_S5_LPCPLUS =PP3V42_G3H_RTC_D =PP3V42_G3H_BMON_ISNS 40B8 42C5 64B3 64D3 64D8 57A8 57C6 57D5 47B3 47B5 47C2 47C5 56A3 56B3 39D4 40C1 40C7 40D8 49D7 41B7 41C3 41C7 41D5 26D8 44A8 PP18V5_G3H MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.3 MM VOLTAGE=18.5V MAKE_BASE=TRUE =PP18V5_G3H_CHGR 57D8 PPBUS_G3H 7C3 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.3 MM VOLTAGE=12.6V MAKE_BASE=TRUE =PPBUS_S0_LCDBKLT =PPVIN_S0_MCPCORES0 =PPVIN_S0_MCPREG_VIN =PPVIN_S5_1V5S30V75S0 =PPVIN_S5_3V3S5 =PPVIN_S0_5VRTS0 =PPVIN_S3_5VLTS3 =PPBUS_G3HRS5 =PPCPUVCORE_VTT_ISNS_R 70D8 61C3 61C6 59C2 58B3 58B6 58C6 C 61D8 43B8 44B8 44B7 =PPCPUVCORE_VTT_ISNS PPBUS_G3H_CPU_ISNS MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.3 MM VOLTAGE=12.6V MAKE_BASE=TRUE (AFTER HIGH SIDE CPU VCORE & CPU VTT SENSING RES.) =PPVIN_S0_CPUVTTS0 =PPVIN_S5_CPU_IMVP PPVTT_S3_DDR_BUF MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=0.75V MAKE_BASE=TRUE 62C6 60C2 60D4 60D8 "ENET" RAILS 34D2 =PP3V3_ENET_FET PP3V3_ENET_PHY MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V MAKE_BASE=TRUE 7C3 =PP3V3_ENET_MCP_RMGT 18C7 18D3 24A6 24B6 29A8 =PP3V3_ENET_PHY 64A5 64B8 44C7 "S5" RAILS 34B2 44B7 =PP1V05_ENET_FET PP1V2R1V05_ENET 63B4 =PP1V05_S5_REG 48A6 42C8 58B1 =PP3V3_S5_REG 7C3 MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V MAKE_BASE=TRUE 63C5 32C3 33D7 PP1V1R1V05_S5 7C3 =PP1V05_ENET_MCP_PLL_MAC MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V MAKE_BASE=TRUE =PP1V05_ENET_MCP_RMGT =PP1V05_S5_MCP_VDD_AUXC =PP1V05_ENET_P1V05ENETFET =PP1V05_S5_P1V05S0FET 34C4 PP3V3_S5 7C3 =PP1V05_ENET_PHY 22A3 24C8 B 24A8 18D3 24C6 33D2 65B6 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V MAKE_BASE=TRUE =PP3V3_S5_MCP_GPIO =PP3V3_S5_ROM =PP3V3_S5_LCD =PP3V3_S5_MCP =PP3V3_S5_MCPPWRGD =PP3V3_S5_SMBUS_MCP_1 =PP3V3_S5_MCP_A01 =PP3V3_S5_PWRCTL =PP3V3_S5_P1V05ENETFET =PP3V3_S5_P3V3S3FET =PP3V3_S5_P3V3S0FET =PP3V3_S5_P1V05S5 =PP3V3_S5_P1V05FET =PP3V3_S5_MEMRESET =PP3V3_S5_P3V3ENETFET =PP3V3_S5_DP_PORT_PWR 206 mA (A01) 17B6 57 mA (A01) 17A6 127 mA (A01) 18C7 20C1 41B5 41C7 50C6 66C8 22B3 24B8 26B8 42C7 23C4 41B4 64B3 64C4 34C5 65D8 65C8 Power Aliases 63B7 65A8 SYNC_MASTER=BEN A 30C6 NOTICE OF PROPRIETARY PROPERTY 34D5 68D8 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING 20A6 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE 43 mA (A01) II NOT TO REPRODUCE OR COPY IT 20B6 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC REV 051-7537 SCALE SHT NONE D 37B8 38B4 53B8 53C8 53D8 28A8 17A3 20B6 =PPVIN_S5_SMCVREF =PP3V42_G3H_SMBUS_SMC_BSA =PP3V42_G3H_PWRCTL =PP3V42_G3H_CHGR =PP3V42_G3H_SMCUSBMUX =PP3V42_G3H_LIDSWITCH =PP3V42_G3H_TPAD =PP3V42_G3H_BATT 65B8 127 mA (A01) 24D6 8B7 7A7 7B5 7C3 (BEFORE HIGH SIDE SENSING RES.) 51A7 55D4 68A8 68B8 17B3 20B6 y r 7B5 7D3 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V MAKE_BASE=TRUE 48A5 61C8 44D7 22D5 24D8 61B1 PP3V42_G3H 60D8 9C2 14A2 14B7 22D3 24C8 =PPVCORE_S0_MCP_VSENSE =PP3V42_G3H_REG MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.42V MAKE_BASE=TRUE =PP1V5_S3_P1V5S0FET =PP1V5_S3_MEM_A =PP1V5_S3_MEM_B =PP1V5_S3_MEMRESET 36A5 41D5 PPVCORE_S0_MCP_R =PPVCORE_S0_MCP_REG_R 56B4 7D3 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.5V MAKE_BASE=TRUE 7D3 7D7 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5V MAKE_BASE=TRUE 7D3 MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.3 MM VOLTAGE=1.25V MAKE_BASE=TRUE "G3H" RAILS "S3" RAILS 59B1 60D1 A OF 109 HEATSINK STANDOFFS STDOFF-4.5OD.98H-1.1-3.48-TH UNUSED GPU LANES =PEG_D2R_N NC_PEG_D2R_N 17D6 17C6 =PEG_D2R_P NC_PEG_D2R_P 17D3 17C3 =PEG_R2D_C_N NC_PEG_R2D_C_N NO_TEST=TRUE Z0901 Z0902 17D6 17C6 STDOFF-4.5OD.98H-1.1-3.48-TH NO_TEST=TRUE 1 NO_TEST=TRUE 17D3 17C3 ABOVE CPU 17C6 TP_PEG_PRSNT_L 17C3 D Z0904 Z0903 17C3 MCP_CLK27M_XTALIN MCP_CLK27M_XTALOUT NC_MCP_CLK27M_XTALOUT CRT_IG_R_C_PR NC_CRT_IG_R_C_PR NO_TEST=TRUE NO_TEST=TRUE 17B6 PCIE_FW_D2R_P TP_PCIE_FW_D2R_P PCIE_FW_D2R_N TP_PCIE_FW_D2R_N MAKE_BASE=TRUE MAKE_BASE=TRUE CRT_IG_B_COMP_PB NC_CRT_IG_B_COMP_PB 18B3 CRT_IG_HSYNC NC_CRT_IG_HSYNC 18B3 ETHERNET ALIASES MAKE_BASE=TRUE 18C3 NO_TEST=TRUE 17B6 MAKE_BASE=TRUE NC_CRT_IG_G_Y_Y NO_TEST=TRUE MAKE_BASE=TRUE CRT_IG_VSYNC 34C5 MAKE_BASE=TRUE 34B5 MAKE_BASE=TRUE NO_TEST=TRUE 33C2 MAKE_BASE=TRUE 33C6 MAKE_BASE=TRUE PCIE_FW_R2D_C_P TP_PCIE_FW_R2D_C_P 17B3 PCIE_FW_R2D_C_N TP_PCIE_FW_R2D_C_N LVDS ALIASES MAKE_BASE=TRUE 18B3 UNUSED LVDS SIGNALS LVDS_IG_A_DATA_P NC_LVDS_IG_A_DATA_P3 18B3 LVDS_IG_A_DATA_N MAKE_BASE=TRUE FAN STANDOFF 17C6 PCIE_FW_PRSNT_L TP_PCIE_FW_PRSNT_L NO_TEST=TRUE MAKE_BASE=TRUE 17C6 Z0905 FW_CLKREQ_L TP_FW_CLKREQ_L STDOFF-4.5OD.98H-1.1-3.48-TH 17C3 PCIE_CLK100M_FW_P TP_PCIE_CLK100M_FW_P 17C3 PCIE_CLK100M_FW_N TP_PCIE_CLK100M_FW_N 18B3 MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM VOLTAGE=0V LVDS_IG_B_CLK_P 18B3 LVDS_IG_B_CLK_N MAKE_BASE=TRUE NC_LVDS_IG_B_CLK_N a n i NO_TEST=TRUE MAKE_BASE=TRUE 18B3 LVDS_IG_B_DATA_P MAKE_BASE=TRUE NC_LVDS_IG_B_DATA_P NO_TEST=TRUE UNUSED EXPRESS CARD LANE 18B3 LVDS_IG_B_DATA_N MAKE_BASE=TRUE NC_LVDS_IG_B_DATA_N NO_TEST=TRUE 17B6 TP_PCIE_EXCARD_D2R_P PCIE_EXCARD_D2R_P MAKE_BASE=TRUE 17B6 TP_PCIE_EXCARD_D2R_N PCIE_EXCARD_D2R_N MAKE_BASE=TRUE AUDIO CHASSIS GND 17B3 PCIE_EXCARD_R2D_C_P TP_PCIE_EXCARD_R2D_C_P 17B3 PCIE_EXCARD_R2D_C_N TP_PCIE_EXCARD_R2D_C_N 17C6 PCIE_EXCARD_PRSNT_L TP_PCIE_EXCARD_PRSNT_L OMIT MAKE_BASE=TRUE C 55A4 54A3 =GND_CHASSIS_AUDIO_JACK =GND_CHASSIS_AUDIO_MIC 17C6 EXCARD_CLKREQ_L TP_EXCARD_CLKREQ_L 14B6 MAKE_BASE=TRUE Z0906 TH 19B7 SL-3.10X2.70 TP_PCIE_CLK100M_EXCARD_P PCIE_CLK100M_EXCARD_P MAKE_BASE=TRUE 17C3 TP_GMUX_JTAG_TCK_L MAKE_BASE=TRUE TP_GMUX_JTAG_TDO 19D4 GMUX_JTAG_TDI TP_GMUX_JTAG_TDI 19D4 GMUX_JTAG_TMS AIRPORT CARD PRESENT SIGNAL MLB MOUNTING SCREW HOLES OMIT Z0909 3R2P5 OMIT Z0908 3R2P5 1 PCIE_MINI_PRSNT_L 18D6 FOR VENICE CARD 17B6 TP_PE4_CLKREQ_L 18C6 FC_CLKREQ_L 17B6 =MCP_MII_RXER =MCP_MII_COL =MCP_MII_CRS m il 32C5 MAKE_BASE=TRUE TP_PE4_PRSNT_L FC_PRSNT_L 18C6 32B3 MAKE_BASE=TRUE 17B3 TP_PCIE_CLK100M_PE4P 17B3 TP_PCIE_CLK100M_PE4N 17B6 TP_PCIE_PE4_D2RP 17B6 TP_PCIE_PE4_D2RN PCIE_CLK100M_FC_P 32C5 73D3 MAKE_BASE=TRUE OMIT Z0911 3R2P5 OMIT Z0912 3R2P5 OMIT Z0913 3R2P5 PCIE_CLK100M_FC_N 32B5 73D3 MAKE_BASE=TRUE 18B6 PCIE_FC_D2R_N =DVI_HPD_GMUX_INT 32B5 73D3 MAKE_BASE=TRUE 17B3 TP_PCIE_PE4_R2D_CP PCIE_FC_R2D_C_P 32C6 73D3 MAKE_BASE=TRUE 17B3 TP_PCIE_PE4_R2D_CN PCIE_FC_R2D_C_N 32C6 73D3 MAKE_BASE=TRUE e r VENICE BOARD STANDOFFS VENICE Z0914 B STDOFF-4.0OD3.0H-TH VENICE VENICE Z0915 STDOFF-4.0OD3.0H-TH STDOFF-4.0OD3.0H-TH 20C3 20C3 20D3 20D3 20C3 20C3 20D3 EMI IO POGO PINS ZS0901 1.4DIA-SHORT-EMI-MLB-M97-M98 SM TP_USB_EXTC_P TP_USB_EXTC_N TP_USB_EXTD_P TP_USB_EXTD_N TP_USB_EXCARD_P TP_USB_EXCARD_N =MCP_BSEL Extra FSB Pull-ups 24C8 22D3 14B7 14A2 8D7 =PP1V05_S0_MCP_FSB C MCP_A01&MCP_A01P&MCP_A01Q NO STUFF R0970 R0990 220 200 150 5% 1/16W MF-LF 402 5% 1/16W MF-LF 402 5% 1/16W MF-LF 402 NO STUFF R0930 NO STUFF R0960 62 47K 71B3 60C7 14A3 10B2 OUT 71C3 14B6 10D6 OUT 71C3 14A3 13B2 10D6 OUT 71C3 14A3 10B8 OUT 71C3 14A3 10B8 OUT MAKE_BASE=TRUE R0980 150 5% 1/16W MF-LF 402 5% 1/16W MF-LF 402 R0940 20K NO STUFF R0950 MAKE_BASE=TRUE 266 133 200 (166) 333 100 (400) (RSVD) Exist in MRB but not Intel designs Here for CYA If found to be necessary, will move to page14.csa MCP_MII_PD HPLUG_DET2 14A7 OUT FSB MHZ 1 1 5% 1/16W MF-LF 402 CPU_DPRSTP_L FSB_BREQ0_L FSB_CPURST_L CPU_INTR CPU_NMI 5% 1/16W MF-LF 402 B TP_USB_MINI_P USB_MINI_P USB_MINI_N MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE TP_USB_MINI_N MAKE_BASE=TRUE ZS0903 1.4DIA-SHORT-EMI-MLB-M97-M98 1.4DIA-SHORT-EMI-MLB-M97-M98 SM SM SM SIGNAL ALIAS ZS0904 ZS0905 ZS0906 ZS0907 2.0DIA-TALL-EMI-MLB-M97-M98 2.0DIA-TALL-EMI-MLB-M97-M98 2.0DIA-TALL-EMI-MLB-M97-M98 SM SM SM SM CPU_BSEL MAKE_BASE=TRUE 0 1 0 1 MAKE_BASE=TRUE 2.0DIA-TALL-EMI-MLB-M97-M98 IN 0 0 1 1 MAKE_BASE=TRUE 1.4DIA-SHORT-EMI-MLB-M97-M98 EMI POGO PINS A P 20D3 USB_EXTC_P USB_EXTC_N USB_EXTD_P USB_EXTD_N USB_EXCARD_P USB_EXCARD_N ZS0902 71C3 10B4 10A4 BSEL UNUSED USB PORTS ZS0900 MAKE_BASE=TRUE MAKE_BASE=TRUE USB ALIASES Z0916 MAKE_BASE=TRUE DP HOTPLUG PULL-DOWN 32C5 73C3 MAKE_BASE=TRUE PCIE_FC_D2R_P MAKE_BASE=TRUE D 21C3 MAKE_BASE=TRUE TP_PP3V3_ENET_PHY_VDDREG MAKE_BASE=TRUE NC_RTL8211_REGOUT LAN ALIASES MAKE_BASE=TRUE OMIT Z0910 3R2P5 TP_GMUX_JTAG_TMS MAKE_BASE=TRUE MAKE_BASE=TRUE 31D7 17C6 MAKE_BASE=TRUE GMUX_JTAG_TCK_L GMUX_JTAG_TDO TP_PCIE_CLK100M_EXCARD_N PCIE_CLK100M_EXCARD_N TP_CPU_PECI_MCP TP_FW_PME_L 17B6 17B6 MAKE_BASE=TRUE 17C3 CPU_PECI_MCP FW_PME_L MAKE_BASE=TRUE MAKE_BASE=TRUE 54B8 54A8 MISC MCP79 ALIASES MAKE_BASE=TRUE GND_CHASSIS_AUDIO MAKE_BASE=TRUE PM_SLP_RMGT_L CPU FSB FREQUENCY STRAPS MAKE_BASE=TRUE NC_LVDS_IG_B_CLK_P NO_TEST=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE NC_LVDS_IG_A_DATA_N3 NO_TEST=TRUE MAKE_BASE=TRUE =P3V3ENET_EN =P1V05ENET_EN =PP3V3_ENET_PHY_VDDREG =RTL8211_REGOUT =RTL8211_ENSWREG y r 33C2 NC_CRT_IG_VSYNC MAKE_BASE=TRUE 17B3 MAKE_BASE=TRUE MAKE_BASE=TRUE 18C6 CRT_IG_G_Y_Y TP_MEM_A_A15 TP_MEM_B_A15 NC_MCP_CLK27M_XTALIN 18C3 UNUSED FW LANE BELOW CPU 29C5 MEM_A_A MEM_B_A MAKE_BASE=TRUE MAKE_BASE=TRUE 18C3 28C5 NC_MCP_TV_DAC_VREF NO_TEST=TRUE BELOW MCP UNUSED ADDRESS PINS MAKE_BASE=TRUE MAKE_BASE=TRUE TP_PEG_CLK100M_N 1 18C6 TP_PEG_CLK100M_P PEG_CLK100M_N MCP_TV_DAC_VREF NO_TEST=TRUE MAKE_BASE=TRUE STDOFF-4.5OD.98H-1.1-3.48-TH STDOFF-4.5OD.98H-1.1-3.48-TH PEG_CLK100M_P 18C6 NO_TEST=TRUE MAKE_BASE=TRUE PEG_PRSNT_L 18C6 SO-DIMM ALIASES UNUSED CRT & TV-OUT INTERFACE MCP_TV_DAC_RSET NC_MCP_TV_DAC_RSET NO_TEST=TRUE MAKE_BASE=TRUE NC_PEG_R2D_C_P NO_TEST=TRUE LEFT OF CPU DACS ALIASES MAKE_BASE=TRUE =PEG_R2D_C_P PCI-E ALIASES SYNC_MASTER=M97_MLB A NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC SCALE SHT NONE REV 051-7537 A OF 109 OMIT 71D3 14C6 BI 71D3 14C6 BI 71D3 14C6 BI 71D3 14C6 BI 71D3 14C6 BI 71D3 14C6 BI 71D3 14C6 BI 71C3 14B6 BI 71C3 14B6 BI 71C3 14B6 BI 71C3 14B6 BI 71C3 14B6 BI 71C3 14C6 BI 71C3 14C6 BI 71C3 14C6 BI 71C3 14C6 BI 71C3 14C6 BI 71C3 14C6 BI 71C3 14C6 71C3 14C6 BI BI 71C3 14C6 BI 71C3 14C6 BI 71C3 14C6 C BI 71C3 14B6 BI 71C3 14C6 BI 71C3 14C6 BI 71C3 14C6 BI 71C3 14C6 BI 71C3 14C6 BI 71C3 14B6 BI 71C3 14B6 BI 71C3 14B6 BI 71C3 14B6 BI 71C3 14A3 71C3 14B7 71C3 14A3 K3 FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_ADSTB_L Y2 IN CPU_A20M_L OUT CPU_FERR_L IN CPU_IGNNE_L 71B3 14A3 IN 71C3 14A3 9B2 IN 71C3 14A3 9B2 IN 71B3 14A3 FSB_REQ_L FSB_REQ_L FSB_REQ_L FSB_REQ_L FSB_REQ_L IN CPU_STPCLK_L CPU_INTR CPU_NMI CPU_SMI_L TP_CPU_RSVD_M4 TP_CPU_RSVD_N5 TP_CPU_RSVD_T2 TP_CPU_RSVD_V3 TP_CPU_RSVD_B2 TP_CPU_RSVD_F6 TP_CPU_RSVD_D2 TP_CPU_RSVD_D22 TP_CPU_RSVD_D3 N2 J1 N3 P5 P2 L2 P4 P1 R1 M1 H2 K2 J3 L1 U5 R3 W6 U4 Y5 U1 R4 T5 T3 W2 W5 Y4 U2 V4 W3 AA4 AB2 AA3 V1 A6 A5 C4 D5 C6 B4 A3 M4 N5 T2 V3 B2 F6 D2 D22 D3 FCBGA OF REQ0* REQ1* REQ2* REQ3* REQ4* A17* A18* A19* A20* A21* A22* A23* A24* A25* A26* A27* A28* A29* A30* A31* A32* A33* A34* A35* ADSTB1* G5 DEFER* DRDY* DBSY* H5 E1 FSB_DEFER_L FSB_DRDY_L FSB_DBSY_L BR0* F1 FSB_BREQ0_L F21 BI 14B6 71C3 BI 14B6 71C3 BI 14B3 71C3 BI 14B3 71C3 BI 14B6 71C3 BI 14B6 71C3 BI 9B2 14B6 71C3 IN LOCK* H4 FSB_LOCK_L BI RESET* RS0* RS1* RS2* TRDY* C1 FSB_CPURST_L FSB_RS_L FSB_RS_L FSB_RS_L FSB_TRDY_L D20 BPM0* BPM1* BPM2* BPM3* PRDY* PREQ* TCK TDI TDO TMS TRST* DBR* F3 F4 G3 G2 71B3 FSB_HIT_L FSB_HITM_L G6 E4 AD4 AD3 AD1 AC4 AC2 AC1 AC5 AA6 AB3 AB5 AB6 C20 =PP1V05_S0_CPU 6D8 8D7 11C6 12B6 13D6 R1000 54.9 1% 1/16W MF-LF 402 D B3 CPU_IERR_L CPU_INIT_L IERR* INIT* HIT* HITM* XDP_BPM_L XDP_BPM_L XDP_BPM_L XDP_BPM_L XDP_BPM_L XDP_BPM_L XDP_TCK XDP_TDI XDP_TDO XDP_TMS XDP_TRST_L XDP_DBRESET_L 14A3 71C3 IN 9B2 13B2 14A3 71C3 IN 14A6 71C3 IN 14A6 71C3 IN 14A6 71C3 IN 14B6 71C3 BI 14B6 71C3 BI 14B6 71C3 BI OMIT 13C6 71A3 BI 13C6 71A3 BI 13C6 71A3 BI 13C6 71A3 BI R1001 13C6 71A3 13C6 71A3 BI THERMTRIP* RSVD0 RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 RSVD6 RSVD7 RSVD8 BI 71D3 14D3 BI 71D3 14D3 BI BI 6C4 10B6 71A3 71D3 14D3 IN 6C6 6C7 10B6 13B3 71A3 71D3 14D3 BI IN 6C6 6C7 10A6 13B3 71A3 71D3 14D3 BI 71D3 14D3 BI OUT 13B3 26A3 R1002 OUT 45D5 77D3 B25 OUT 45D5 77D3 C7 PM_THRMTRIP_L OUT 14B7 40C4 71B3 71D3 14D3 OUT 14B6 40D4 60C8 71B3 A21 FSB_CLK_CPU_P FSB_CLK_CPU_N BI 71D3 14D3 BI 71D3 14D6 BI 71D3 14D6 BI 71D3 14D6 BI 71D3 14D3 BI 71D3 14D3 BI e r 1K CPU JTAG Support B R1090 71A3 13B3 10C6 6C7 6C6 XDP_TMS 71A3 13B3 10C6 6C6 XDP_TDI XDP_TDO P 71A3 10C6 6C4 71A3 13B3 10C6 6C7 6C6 XDP_TCK XDP_TRST_L R1006 2.0K R1092 54.9 PLACEMENT_NOTE=Place R1092 near ITP connector (if present) 71A3 13B6 10C6 6C7 6C6 1% 1/16W MF-LF 402 1% 1/16W MF-LF 402 1% 1/16W MF-LF 402 R1091 54.9 54.9 R1005 1% 1/16W MF-LF 402 1% 1/16W MF-LF 402 R1094 649 BI 71D3 14C3 BI 71D3 14C3 BI 54.9 1% 1/16W MF-LF 402 BI 71D3 14C3 BI 71D3 14C3 BI 71D3 14C3 BI 71D3 14C3 BI 71D3 14C3 BI 71D3 14C3 BI 71D3 14C3 BI 71D3 14C3 BI 71D3 14C3 BI 71D3 14D6 BI 71D3 14D6 BI 71D3 14D6 BI a n i FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_DSTB_L_N FSB_DSTB_L_P FSB_DINV_L CPU_GTLREF CPU_TEST1 CPU_TEST2 TP_CPU_TEST3 CPU_TEST4 TP_CPU_TEST5 TP_CPU_TEST6 TP_CPU_TEST7 OUT CPU_BSEL OUT CPU_BSEL OUT CPU_BSEL 71B3 27B1 NO STUFF C1014 10% 16V X5R 402 R1010 5% 1/16W MF-LF 402 R1011 1K NO STUFF 71C3 9C2 71C3 9C2 71C3 9C2 E22 F24 E26 G22 F23 G25 E25 E23 K24 G24 J24 J23 H22 F26 K22 H23 J26 H26 H25 N22 K25 P26 R23 L23 M24 L22 M23 P25 P23 P22 T24 R24 L25 T25 N25 L26 M26 N24 AD26 C23 D25 C24 AF26 AF1 A26 C3 B22 B23 C21 D0* D1* D2* D3* D4* D5* D6* D7* D8* D9* D10* D11* D12* D13* D14* D15* DSTBN0* DSTBP0* DINV0* D16* D17* D18* D19* D20* D21* D22* D23* D24* D25* D26* D27* D28* D29* D30* D31* DSTBN1* DSTBP1* DINV1* GTLREF TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 TEST7 BSEL0 BSEL1 BSEL2 U1000 PENRYN FCBGA OF D32* D33* D34* D35* D36* D37* D38* D39* D40* D41* D42* D43* D44* D45* D46* D47* DSTBN2* DSTBP2* DINV2* D48* D49* D50* D51* D52* D53* D54* D55* D56* D57* D58* D59* D60* D61* D62* D63* DSTBN3* DSTBP3* DINV3* COMP0 COMP1 COMP2 COMP3 MISC DPRSTP* DPSLP* DPWR* PWRGOOD SLP* PSI* FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_DSTB_L_N FSB_DSTB_L_P FSB_DINV_L Y22 AB24 V24 V26 V23 T22 U25 U23 Y25 W22 Y23 W24 W25 AA23 AA24 AB25 Y26 AA26 U22 FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_DSTB_L_N FSB_DSTB_L_P FSB_DINV_L AE24 AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21 AC22 AD23 AF22 AC23 AE25 AF24 AC20 BI 14C3 71D3 BI 14C3 71D3 BI 14C3 71D3 BI 14C3 71D3 BI 14C3 71D3 BI 14C3 71D3 BI 14C3 71D3 BI 14C3 71D3 BI 14C3 71D3 BI 14C3 71D3 BI 14C3 71D3 BI 14C3 71D3 BI 14C3 71D3 BI 14B3 71D3 BI 14B3 71D3 BI 14B3 71D3 BI 14D6 71D3 BI 14D6 71D3 BI 14D6 71D3 BI 14B3 71D3 BI 14B3 71D3 BI 14B3 71D3 BI 14B3 71D3 BI 14B3 71D3 BI 14B3 71D3 BI 14B3 71D3 BI 14B3 71D3 BI 14B3 71D3 BI 14B3 71D3 BI 14B3 71D3 BI 14B3 71D3 BI 14B3 71D3 BI 14B3 71D3 BI 14B3 71D3 BI 14B3 71D3 BI 14D6 71D3 BI 14D6 71D3 BI 14D6 71D3 C B R26 71A3 CPU_COMP U26 71A3 CPU_COMP AA1 71A3 CPU_COMP Y1 E5 B5 D24 D6 D7 AE6 71B3 CPU_COMP CPU_DPRSTP_L CPU_DPSLP_L FSB_DPWR_L CPU_PWRGD FSB_CPUSLP_L CPU_PSI_L IN 9B2 14A3 60C7 71B3 IN 14A3 71B3 R1021 54.9 IN 14A3 71B3 IN 13C7 14A3 71B3 IN 14A3 71B3 OUT R1023 1% 1/16W MF-LF 402 54.9 1% 1/16W MF-LF 402 60C7 5% 1/16W MF-LF 402 PLACEMENT_NOTE=Place C1014 within 12.7mm of CPU PLACEMENT_NOTE=Place R1005 within 12.7mm of CPU PLACEMENT_NOTE=Place R1006 within 12.7mm of CPU 2 R1020 27.4 1% 1/16W MF-LF 402 1% 1/16W MF-LF 402 Place within 12.7mm of CPU CPU FSB SYNC_MASTER=T18_MLB SYNC_DATE=12/12/2007 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC REV 051-7537 SCALE SHT NONE R1022 PLACEMENT_NOTE (all resistors): 1% 1/16W MF-LF 402 SYNC FROM T18 CHANGE CPU FROM SOCKET TO BGA SYMBOL 27.4 R1012 1K 5% 1/16W MF-LF 402 0.1uF NO STUFF NO STUFF R1093 BI 71D3 14C3 71D3 14C3 14B3 71B3 IN BI FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_DSTB_L_N FSB_DSTB_L_P FSB_DINV_L m il 14B3 71B3 IN BI 71D3 14D3 71D3 14D3 A22 BI 71D3 14D3 A BI 71D3 14D3 6C6 10B6 13B3 71A3 H CLK BCLK0 BCLK1 BI 71D3 14D3 IN CPU_PROCHOT_L CPU_THERMD_P CPU_THERMD_N A24 BI IN 5% 1/16W MF-LF 402 D21 71D3 14D3 71D3 14D3 THERMAL PROCHOT* THERMDA THERMDC BI 71D3 14D3 54.9 1% 1/16W MF-LF 402 71D3 14D3 6C6 6C7 10A6 13B6 71A3 OUT y r 14B6 71C3 68 A20M* FERR* IGNNE* STPCLK* LINT0 LINT1 SMI* FSB_ADS_L FSB_BNR_L FSB_BPRI_L H1 E2 DATA GRP BI ADS* BNR* BPRI* PENRYN DATA GRP BI 71D3 14C6 M3 U1000 DATA GRP 71D3 14C6 K5 A3* A4* A5* A6* A7* A8* A9* A10* A11* A12* A13* A14* A15* A16* ADSTB0* DATA GRP BI L4 CONTROL 71D3 14C6 L5 XDP/ITP SIGNALS BI J4 ADDR GROUP0 BI 71D3 14D6 FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_ADSTB_L ADDR GROUP1 BI 71D3 14D6 ICH BI 71D3 14D6 RESERVED D 71D3 14D6 A OF 10 109 A 3.3V 1.05V S5 ENABLE Power Control Signals R7802 64D3 64B3 8D1 100K =PP3V42_G3H_PWRCTL PM_G2_P3V3S5_EN_L =P3V3S5_EN_L OUT 3.3V_S0, 1.8V_S0 ENABLE MCPDDR, CPUVTT,MCPCORES0 ENABLE 1.5V S0 AND 1.05V S0 ENABLE 58A5 MAKE_BASE=TRUE 5% 1/16W MF-LF 402 D D PM_SLP_S3_L Run (S0) 1 Sleep (S3) 1 Soft-Off (S5) 0 10% 10V CERM SMC_PM_G2_EN IN PM_SLP_S4_L D 402 SOD-VESM-HF 39D5 7C3 SMC_PM_G2_ENABLE C7802 0.068UF Q7800 SSM3K15FV State NO STUFF Battery Off (G3Hot) R7813 64D8 64B3 8D1 0 =PP3V42_G3H_PWRCTL 68K 100K 5% 1/16W MF-LF 402 y r 5% R7800 G 1/16W MF-LF 402 S Q7813 D 2 5.1K PM_G2_P1V05S5_EN OUT 63B7 68D8 41A5 39C5 34B7 21C3 7C3 C7801 IN G PM_SLP_S3_L S (PM_SLP_S3_L) 10% 6.3V CERM-X5R 402 NO STUFF R7879 C7858 64B3 8A3 =PP3V3_S5_PWRCTL 0.1UF 5% 1/16W MF-LF 402 a n i 100K B R7881 5% 1/16W MF-LF 402 22K (PM_SLP_S3_L_BUF) R7882 5% 1/16W MF-LF 402 1 MCP_A01&MCP_A01P&MCP_A01Q R7883 5% 1/16W MF-LF 402 33K 5.1K =P3V3S0_EN OUT 65B8 =PBUSVSENS_EN OUT 43B7 R7884 5% 1/16W MF-LF 402 CERM 5% 1/16W MF-LF 402 P1V05S0_EN P1V8S0_EN PM_SLP_S4_L (PM_S4_STATE_L) MAKE_BASE=TRUE =P3V3S3_EN OUT 65C8 MCPDDR_EN 10% 6.3V CERM-X5R 402 OUT 59B8 =USB_PWR_EN OUT 37B7 m il 0.47UF 2 10% 6.3V CERM-X5R 402 P5VLTS3_EN =P5VLTS3_EN MAKE_BASE=TRUE OUT 61B8 e r B 3.3V 1.05V AND 1.5V S0 RAILS MONITOR CIRCUIT 8B5 =PP3V3_S0_VMON P C7870 0.1uF 20% 10V CERM 402 VCC U7870 LTC2909 NC =PP1V05_S0_VMON SEL ADJ1 ADJ2 REF DFN RST* GND A TMR C7880 0.47UF 10% 6.3V CERM-X5R C7881 0.47UF 402 10% 6.3V CERM-X5R C7882 =CPUVTTS0_EN OUT 62B7 =MCPCORES0_EN OUT 61B8 10% 6.3V CERM-X5R 402 402 C NO STUFF C7883 0.47UF 0.47UF C7884 0.47UF 10% 6.3V CERM-X5R 402 10% 6.3V CERM-X5R 402 VOLTAGE MONITOR 64D8 64D3 8D1 =PP3V42_G3H_PWRCTL 64C4 8A3 =PP3V3_S5_PWRCTL C7840 1 0.1uF 20% 10V CERM 402 SENSE U7840 B R7840 100K VDD RESET* 5% 1/16W MF-LF 402 RSMRST_PWRGD 39D8 P1V05_S5_PGOOD 63A6 TPS3808G33DBVRG4 CT CT SOT23-6 MR* TPS3808 MR* HAS INTERNAL PULLUP GND C7841 0.001UF 20% 50V CERM 402 OTHER S0 RAILS PGOOD 8B5 =PP3V3_S0_PWRCTL TIE TMR TO GND TRST = 200MS R7820 10K 5% 1/16W MF-LF 402 S0PGOOD_PWROK POWER SEQUENCING Unused PGOOD signal THRM_PAD 58A2 P5V3V3_PGOOD IN TP_DDRREG_PGOOD =PP1V5_S0_VMON MCPCORES0_EN NO STUFF =DDRREG_EN C7812 5% 1/16W MF-LF 402 65C4 MAKE_BASE=TRUE NO STUFF 100 5% MAKE_BASE=TRUE OUT MAKE_BASE=TRUE 1/16W MF-LF 402 DDRREG_EN R7812 CPUVTTS0_EN R7859 2 5% 1/16W MF-LF 402 63C4 =MCPDDR_EN MAKE_BASE=TRUE 0.47UF 5.1K 100K 5% 1/16W MF-LF 402 R7811 65A8 OUT R7810 OUT =P1V8S0_EN MAKE_BASE=TRUE C7810 8B7 R7880 SOT665 S3 ENABLE 8B7 MAKE_BASE=TRUE TC7SZ08AFEAPE A U7859 Y (PM_SLP_S3_L) PM_SLP_S3_L_BUF 20% 10V CERM 402 NO STUFF C 10% 10V 402 0.47UF IN 58A7 C7813 2 OUT NO STUFF 0.068UF =P1V05_S5_EN MAKE_BASE=TRUE =P5VRTS0_EN_L MAKE_BASE=TRUE SOD-VESM-HF 5% 1/16W MF-LF 402 40A2 39C5 21C3 7C3 PM_SLP_S3_L_INVERT SSM3K15FV R7801 DDRREG_PGOOD 59B3 SYNC_MASTER=YUAN.MA SYNC_DATE=04/22/2008 MAKE_BASE=TRUE 61B8 MCPCORES0_PGOOD IN LTC2909 THRESHOLD IS 95% (3.136V) 1.5V 1.05V COMPARED TO 0.5V 62B7 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING CPUVTTS0_PGOOD IN I TO MAINTAIN THE DOCUMENT IN CONFIDENCE 61B8 II NOT TO REPRODUCE OR COPY IT P5V_LT_S3_PGOOD IN ALL_SYS_PWRGD OUT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART 26A8 39D8 MAKE_BASE=TRUE SIZE (S0PGOOD_PWROK) DRAWING NUMBER D APPLE INC SCALE SHT NONE REV 051-7537 A OF 78 109 A 1.5V S0 FET 3.3V S3 FET (1.5V S0 FET FOR DDR3 MEM, MCP79 AND CPU) CRITICAL Q7910 FDC638P_G 3.3V S3 FET SM =PP3V3_S3_FET 8D4 =PP3V3_S5_P3V3S3FET 8A3 D MOSFET FDC638P CHANNEL P-TYPE =PP1V5_S3_P1V5S0FET 8D3 D R7912 C7911 1 10K RDS(ON) 10% 16V 5% 1/16W 402 402 P3V3S3_SS 8C3 Q7903 SSM3K15FV y r 20% 10V CERM 402 R7901 =PP5V_S3_MCPDDRFET 10% MF-LF 16V 402 CERM R7903 402 D 10K 5% 1/16W MF-LF 402 64C6 IN G Q7971 D 47K SOT563 3.3V S0 FET 64C1 CRITICAL Q7930 C FDC606P_G 5% 402 X5R MF-LF 26 MOHM @4.5V LOADING 1.431 A (EDP) P3V3S0_SS 2 5% 10% 1/16W Q7905 16V MF-LF CERM 402 SSM3K15FV 402 D SOD-VESM-HF 64C1 IN G S =P3V3S0_EN 1.05V S0 FET 8B3 NO STUFF 8C3 220K P1V05S0_SS D R7954 0.1UF =PP3V3_S5_P1V05FET SOT6-HF NO STUFF C7952 8A3 P1V05S0_RC R7953 NO STUFF SSM6N15FEAPE SOT563 NO STUFF R7951 P1V05_EN_L A 100K D Q7951 D SSM6N15FEAPE S =PPVTT_S0_VTTCLAMP FDC655BN CHANNEL N-TYPE RDS(ON) 30 MOHM @4.0V VGS LOADING 1.1A (EDP) =PP1V05_S0_FET G S 1 8C3 10% 10V CERM 402 1.5V S0 FET MOSFET SI7108DNS CHANNEL N-TYPE MCPDDR_EN_L_RC RDS(ON) MOHM @3.5V VGS LOADING 5A (EDP) C B 10 VTTCLAMP_L 90mA max load @ 0.9V 81mW max power CKT FROM T18 S SOT563 100K 5% 1/16W MF-LF 402 D SSM6N15FEAPE R7976 2 G VTTCLAMP_EN 8C8 Q7975 D NO STUFF C7976 SSM6N15FEAPE 20% 50V CERM 402 R7955 5% 59C8 26C1 1/8W IN G 0.001UF SOT563 S POWER FETS SYNC_MASTER=YUAN.MA SYNC_DATE=04/04/2008 NOTICE OF PROPRIETARY PROPERTY =DDRVTT_EN MF-LF 805 SOT563 C7903 0.068UF Q7975 0.068UF P1V05_EN_L_RC 1 =PP5V_S3_VTTCLAMP C7953 10% 10V CERM 402 S 5% 1/10W MF-LF 603 G 8B8 R7975 8C7 NO STUFF 5% 1/16W MF-LF 402 NO STUFF G Q7951 10K 5% 1/16W MF-LF 402 510 5% 1/16W MF-LF 402 20% 10V CERM 402 NO STUFF MOSFET =PP1V5_S0_FET MCP79 DDR PAD LEAKAGE IS HIGH ENOUGH THAT NVIDIA RECOMMENDS UNPOWERING DURING SLEEP IN ORDER TO SUPPORT UNPOWERING RAIL, HARDWARE MUST GUARANTEE MEM_CKE SIGNALS ARE LOW BEFORE RAIL IS TURNED OFF, AND REMAINS LOW UNTIL AFTER RAIL TURNS BACK ON OR DIMMS WILL EXIT SELF-REFRESH PREMATURELY MEM_VTT_EN OUTPUT FROM MCP79 USED TO ENABLE CLAMP ON VTT RAIL, WHICH PULLS ALL CKE SIGNALS LOW THROUGH VTT TERMINATION RESISTORS 1.05V S0 FET Q7953 FDC655BN_G 5% 1/16W MF-LF 402 NO STUFF P NO STUFF CRITICAL R7952 =PP5V_S3_P1V05S0FET =PP1V05_S5_P1V05S0FET MCP79 DDRVTT FET e r B S =MCPDDR_EN m il 0.01UF 47K P-TYPE RDS(ON) C7930 R7930 P3V3S0_EN_L D 402 FDC606P CHANNEL G 10% 16V 1/16W MOSFET 0.033UF 100K 8C6 R7932 C7931 3.3V S0 FET =PP3V3_S0_FET S =PP3V3_S5_P3V3S0FET 8A3 SOT-6 IN G 5% 1/16W MF-LF 402 SSM6N15FEAPE PWRPK-1212-8-HF SOT563 MCPDDR_EN_L =P3V3S3_EN D Q7971 a n i S SI7108DN SSM6N15FEAPE R7971 G CRITICAL Q7901 S 100K SOD-VESM-HF D MCPDDR_SS 5% 1/16W MF-LF 402 5% 1/16W 0.1UF 0.182 A (EDP) 0.01UF 47K LOADING C7910 R7910 P3V3S3_EN_L 48 mOhm @4.5V X5R MF-LF C7902 0.033UF THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT 64C1 IN G S III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART P1V05S0_EN 62C2 8D8 =PPCPUVTT_S0_REG SIZE DRAWING NUMBER D APPLE INC SCALE SHT NONE REV 051-7537 A OF 79 109 A D D y r LCD a n i C9015 0.001UF 10% 50V X7R L9004 8A3 Q9003 =PP3V3_S5_LCD R9023 LCDVDD_PWREN_L Q9004 SSM3K15FV D 10K 5% 1/16W MF-LF 402 SOD-VESM-HF C9009 0.001UF MIN_NECK_WIDTH=0.20 MM 8C5 C9011 0.1UF 10% 16V X5R 402 0.0033UF G 18B6 S R9008 100K 5% 1/16W MF-LF 402 18A3 7C7 18A3 7C7 10% 50V CERM 402 LVDS_IG_PANEL_PWR R9014 1K 5% 1/16W MF-LF 2402 7C7 R9009 100K 5% 1/16W MF-LF 402 LVDS_IG_DDC_CLK LVDS_IG_DDC_DATA P A CRITICAL J9000 20474-030E-11 F-RT-SM 31 32 0.001UF 10% 50V X7R 2 402 7C7 7C3 PP3V3_LCDVDD_SW_F 69C6 BKL_SYNC PP3V3_S0_LCD_F C MIN_LINE_WIDTH=0.25 MM VOLTAGE=3.3V MIN_NECK_WIDTH=0.20 MM 18B3 7C7 73B3 18B3 7C7 73B3 18B3 7C7 73B3 73B3 18B3 7C7 LVDS_IG_A_DATA_N LVDS_IG_A_DATA_P 10 LVDS_IG_A_DATA_N LVDS_IG_A_DATA_P 11 12 13 73B3 18B3 7C7 73B3 18B3 7C7 14 LVDS_IG_A_DATA_N LVDS_IG_A_DATA_P 15 16 CRITICAL L9080 90-OHM-200MA AMC2012-SM LVDS_IG_A_CLK_F_N 7C7 LVDS_IG_A_CLK_F_P 73B3 7C7 17 73B3 18 LVDS I/F SYM_VER-1 73B3 18B3 73B3 18B3 LVDS_IG_A_CLK_N LVDS_IG_A_CLK_P 69C1 7B7 69B1 7B7 69B1 7B7 69B1 7B7 e r B C9010 (LVDS DDC POWER) m il C9013 0402-LF =PP3V3_S0_LCD 10UF LCDVDD_PWREN_L_R 1 C9012 20% 6.3V X5R 603 L9008 LVDS CONNECTOR:518S0650 MIN_NECK_WIDTH=0.20 MM VOLTAGE=3.3VMIN_LINE_WIDTH=0.30 MM CRITICAL 120-OHM-0.3A-EMI VOLTAGE=3.3V MIN_LINE_WIDTH=0.30 MM 10% 50V CERM 402 0402-LF PP3V3_LCDVDD_SW G 5% 1/16W MF-LF 402 D 100K S R9002 C FDC606P_G SOT-6 402 FERR-120-OHM-1.5A CRITICAL CONNECTOR 69B1 7B7 69B1 7B7 19 20 NC 69C1 69B3 7C7 7C3 21 PPVOUT_S0_LCDBKLT 22 23 NC LED_RETURN_1 LED_RETURN_2 LED_RETURN_3 LED_RETURN_4 LED_RETURN_5 LED_RETURN_6 LED BKLT I/F 24 25 26 27 28 29 30 NC B 33 34 LVDS CONNECTOR SYNC_MASTER=NMARTIN SYNC_DATE=04/04/2008 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC SCALE SHT NONE REV 051-7537 A OF 90 109 A 18B6 18B6 18B6 18B6 18B6 18B6 18B6 18B6 18B6 D 18A3 18A3 =MCP_HDMI_TXC_P =MCP_HDMI_TXC_N =MCP_HDMI_TXD_P =MCP_HDMI_TXD_N =MCP_HDMI_TXD_P =MCP_HDMI_TXD_N =MCP_HDMI_TXD_P =MCP_HDMI_TXD_N =MCP_HDMI_HPD =MCP_HDMI_DDC_CLK =MCP_HDMI_DDC_DATA DP_ML_P DP_ML_N DP_ML_P DP_ML_N DP_ML_P DP_ML_N DP_ML_P DP_ML_N DP_HPD BI 33 0.1UF 5% 1/16W MF-LF 402 Display Port Interoperability spec says that sources or sinks which both DP and DVI must depend on the external adapter for pull ups on DDC lines (since DP AUX CH has 100K pull up/down on the MLB) DP_IG_DDC_CLK 67D1 BI 73B3 33 5% 1/16W MF-LF 402 C9301 0.1UF 73B3 DP_AUX_CH_SW_P 10% 16V X5R 402 C Q9300 D SSM6N15FEAPE Q9300 S SOT563 G DP_IG_AUX_CH_P 73B3 18B6 BI 73B3 18B6 BI =PP5V_S0_DP_AUX_MUX 8D5 R9302 100K 5% 1/16W MF-LF 402 R9306 1K 5% 1/16W MF-LF 402 Q9301 D SSM3K15FV SOD-VESM-HF DP_CA_DET IN A 68C1 73B3 MAKE_BASE=TRUE 68C1 73C3 MAKE_BASE=TRUE 68C1 73B3 MAKE_BASE=TRUE 68A8 D 67C8 MAKE_BASE=TRUE 67C8 MAKE_BASE=TRUE S 68C8 73B3 C e r DDC_CA_DET_LS5V_L B 68B8 G 68C1 73C3 MAKE_BASE=TRUE m il DP_IG_AUX_CH_N D SSM6N15FEAPE SOT563 68B1 73B3 MAKE_BASE=TRUE y r 68B8 73B3 DP_AUX_CH_C_P BI R9301 68C1 73C3 MAKE_BASE=TRUE a n i DP_AUX_CH_SW_N 10% 16V X5R 402 68C8 73B3 MAKE_BASE=TRUE MAKE_BASE=TRUE C9300 R9300 DP_IG_DDC_DATA 67D1 68C8 73C3 MAKE_BASE=TRUE DP_IG_DDC_CLK DP_IG_DDC_DATA DP_AUX_CH_C_N BI P S G B DP_IG_CA_DET OUT 18B6 DISPLAYPORT SUPPORT SYNC_MASTER=AMASON SYNC_DATE=04/18/2008 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC SCALE SHT NONE REV 051-7537 A OF 93 109 A Port Power Switch DP_ESD CRITICAL CRITICAL L9400 64D5 41A5 39C5 34B7 21C3 7C3 IN =PP3V3_S5_DP_PORT_PWR IN PP3V3_S0_DPILIM OC* MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=3.3V TP_DPPWR_OC_L 1 10UF 20% 6.3V X5R 603 0.1UF 2 C9400 IO 20% 6.3V X5R 603 10% 16V CERM 402 5% 1/16W MF-LF 402 R9401 CRITICAL 5% R9413 F-RT-THSM NO STUFF 1/16W MF-LF 402 1M 1/16W MF-LF 402 FL9403 12-OHM-100MA IN DP_ML_P C9414 73B3 67D1 IN DP_ML_N C9415 73B3 67C4 BI DP_AUX_CH_C_P BI DP_AUX_CH_C_N 73C3 67D1 73C3 DP_ML_C_P 10% 16V X5R 402 73B3 DP_ML_C_N 10% 16V X5R 402 0.1uF 0.1uF R9425 5% TCM1210-4SM SYM_VER-2 5% 1/16W MF-LF 402 BOT ROW TOP ROW TH PINS SM PINS DP_HPD DP_C_A_DET HDMI_CEC GND ML_LANE3P 73B3 73B3 DP_ML_CONN_P DP_ML_CONN_N 10 12 ML_LANE3N GND AUX_CHP AUX_CHN DP_PWR 14 20 DP_ESD CRITICAL =PP3V3_S0_DPCONN R9443 5% 1/16W MF-LF 402 67A7 OUT D9411 R9442 100K 5% 1/16W MF-LF 402 DP_CA_DET RCLAMP0524P R9421 100K SLP2510P8 100K 5% 1/16W MF-LF 402 2 IO GND D Q9440 SOT-363 S G DP_CA_DET_L_Q 3 D Q9440 B 2N7002DW-X-G SOT-363 S G DP_CA_DET_Q R9422 R9445 67D1 OUT 10K 5% 1/16W MF-LF 402 DP_HPD R9446 100K 5% 1/16W MF-LF 402 P R9444 10K 5% 1/16W MF-LF 402 5% 1/16W MF-LF 402 MCP79 requires pull Q9441 down HPD input with 2N7002DW-X-G SOT-363 100K if DP_HPD is used D S G DP_HPD_L_Q 73B3 11 13 15 17 19 DP_ESD CRITICAL D9400 5% 1/16W MF-LF 402 5% 1/16W MF-LF 402 NO STUFF 10 NO STUFF DP_ML_CONN_P DP_ML_CONN_N 12-OHM-100MA TCM1210-4SM SYM_VER-2 73B3 DP_ML_CONN_N 5% 1/16W MF-LF 402 5% 1/16W MF-LF 402 NO STUFF FL9400 12-OHM-100MA TCM1210-4SM SYM_VER-2 73C3 DP_ML_C_P TCM1210-4SM SYM_VER-2 Q9441 2N7002DW-X-G SOT-363 73B3 DP_ML_C_N G DP_ML_P 10% 16V C9411 DP_ML_N 10% 16V 10% DP_ML_P 10% DP_ML_N DP_ML_P 10% 16V DP_ML_N 10% 16V 0.1uF 73C3 DP_ML_C_P C9412 73B3 DP_ML_C_N C9413 73C3 DP_ML_C_P C9416 73B3 DP_ML_C_N C9417 0.1uF 0.1uF 0.1uF 0.1uF 16V 16V X5R X5R X5R X5R X5R X5R 402 402 402 402 402 402 IN 67D1 73C3 IN 67D1 73B3 IN 67D1 73C3 IN 67D1 73B3 IN 67D1 73C3 IN 67D1 73B3 NO STUFF R9402 R9432 5% 1/16W MF-LF 402 5% 1/16W MF-LF 402 NO STUFF DP_ESD CRITICAL D9411 RCLAMP0524P SLP2510P8 RCLAMP0504F SC70-6-1 IO IO NC 6 NC B DisplayPort Connector D S C C9410 0.1uF FL9402 12-OHM-100MA DP_ML_CONN_P 73B3 FL9401 R9430 NO STUFF A 2 73B3 514-0610 10 DP to DVI/HDMI Cable Adapter (CA) has 100k pull-up to DP_PWR 1M Q9440 must have Drain to Gate leakage of 5MOhm =PP3V3_S0_DPCONN e r 2N7002DW-X-G 68B8 8B5 IO NC NC GND ML_LANE0P ML_LANE0N GND ML_LANE1P ML_LANE1N73B3 GND ML_LANE2P ML_LANE2N RETURN SHIELD PINS 22 68A8 8B5 DP_ML_CONN_P DP_ML_CONN_N 73B3 m il 16 18 73B3 67D4 R9431 J9400 DSPLYPRT-M97-2 NO STUFF 21 C y r IO NC R9400 HDMI_CEC NC a n i 100K R9403 IO C9486 20% 6.3V X5R-CERM 603 R9420 22UF 10UF 20% 10V CERM 402 IO NC NC CRITICAL NO STUFF C9485 C9481 SLP2510P8 PP3V3_S0_DPPWR MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=3.3V 0.01UF 2 0603 GND C9480 SLP2510P8 FERR-120-OHM-3A TPS2051B SOT23 OUT EN PM_SLP_S3_L D9410 RCLAMP0524P GND 8A3 D D9410 RCLAMP0524P GND U9480 GND D DP_ESD CRITICAL SYNC_MASTER=AMASON DP_HPD_Q SYNC_DATE=06/30/2008 NOTICE OF PROPRIETARY PROPERTY R9423 100K 5% 1/16W MF-LF 402 DP Source must pull down HPD input with greater than or equal to 100K (DPv1.1a) THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC SCALE SHT NONE REV 051-7537 A OF 94 109 A *Q9701, D9701, C9709, C9710, L9701, R9702, AND R9715 SHOULD ALL BE PLACED NEAR EACHOTHER *BOOST_FET_CNTL AND PPVOUT_S0_LCDBKLT_SW SHOULD BE KEPT AS SHORT AS POSSIBLE CRITICAL PLACEMENT_NOTE=Place near Q9701 L9701 D9701 22UH-2.5A PPBUS_S0_LCDBKLT_PWR VOLTAGE=12.6V MIN_NECK_WIDTH=0.25 mm MIN_LINE_WIDTH=0.4 mm D PPVIN_S0_LCDBKLT_BUF 1 VOLTAGE=12.6V MIN_NECK_WIDTH=0.20MM MIN_LINE_WIDTH=0.5MM R9730 0.1 1% 1/6W MF 402-HF R9701 1% 1/16W MF-LF 402 C9701 10UF PPVOUT_S0_LCDBKLT_SW VOLTAGE=30V MIN_NECK_WIDTH=0.25 mm MIN_LINE_WIDTH=0.5 mm SWITCH_NODE=TRUE 1 GND_BKL_PWRGND 69D7 69C3 69B4 MIN_NECK_WIDTH=0.20MM MIN_LINE_WIDTH=0.5MM PLACEMENT_NOTE=Place near C9701 Q9701 S C9702 C9710 4.7UF 10% 50V X7R-CERM 1206 10% 50V X7R-CERM 1206 PLACEMENT_NOTE=Place near C9709 MIN_NECK_WIDTH=0.20MM MIN_LINE_WIDTH=0.5MM 10% 25V X5R 402 C9709 SSOT6 MIN_NECK_WIDTH=0.20MM MIN_LINE_WIDTH=0.6MM CRITICAL 4.7UF FDC5612 G 0.1UF y r D BOOST_FET_CNTL PLACEMENT_NOTE=Place near L9701 GND_BKL_PWRGND D CRITICAL CRITICAL BKL_VIN XW9701 SM 69D6 69C3 69B4 PLACEMENT_NOTE=Place near PPVOUT_S0_LCDBKLT_SW 10% 25V X5R 805 PLACEMENT_NOTE=Place near J9000 DFLS1100 PLACEMENT_NOTE=Place near Q9701 100 CRITICAL PLACEMENT_NOTE=Place near C9710 POWERDI-123 IHLP2525CZ-SM IN 70C3 69C7 BOOST_SINK 69D7 69D6 69B4 GND_BKL_PWRGND PLACEMENT_NOTE=Place near C9709 and Q9701 a n i BKLT_EN 187K BKLT_PLL 1% 1/16W MF-LF 402 66C2 BKL_SYNC IN BKL_VSYNC 2 C9713 0.1UF 100K 10% 25V X5R 402 1% 1/16W MF-LF 402 R9706 XW9702 SM 2 PLACEMENT_NOTE=Place near C9709 and Q9701 VIN 10K 1% 1/16W MF-LF 402 10% 10V X5R 402-1 0.4 1% 1/6W MF 402 *R9702 AND R9715 PIN SHOULD BE PLACED NEAR C9709 PIN 5% 1/16W MF-LF 402 R9705 1UF 3.01K 1 C C9703 R9715 0.4 1% 1/6W MF 402 MIN_NECK_WIDTH=0.20MM MIN_LINE_WIDTH=0.5MM R9734 R9707 R9702 100 1% 1/16W MF-LF 402 GND_BKL_PWRGND_X BKL_VREF_4V9 U9701 5% 1/16W MF-LF 402 VREF ENA 17 VSYNC C9712 47PF DRV QFN APP001A 69D7 70C3 69A8 7C3 69C4 69B6 R9731 PPBUS_S0_LCDBKLT_PWR R9704 7C3 69A8 69B6 69C8 BKL_VREF_4V9 ISWSEN ISEN1 10 PPVOUT_S0_LCDBKLT 5% 50V CERM 402 BKL_ISET R9717 10.2 2 2.0M 1% 1/16W MF-LF 402 1% 1/16W MF-LF 402 5% 1/16W MF-LF 402 R9703 1K C9706 0.0022UF NOSTUFF 10% 50V CERM 402 5% 1/16W MF-LF 402 BKL_LRT 10% 10V X5R 402 R9713 Q9702 BKLT_PLL_NOT NTUD3127CXXG SOT-963 N-CHN Q9702 NTUD3127CXXG R9711 30.1K 1% 1/16W MF-LF 402 A 1% 1/16W MF-LF 402 D SOT-963 LVDS_IG_BKL_PWM R9710 10K BKL_PWR_EN_L CRITICAL P BKL_VREF_IN_4V9 P-CHN 100K 1% 1/16W MF-LF 402 G R9700 D S BKL_VREF_4V9 G S 69D7 69D6 69C3 C9707 2.2UF 20% 6.3V CERM 402-LF MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm OUT 7B7 66B3 10.2 LED_RETURN_3 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm 0.1% OUT 7B7 66B3 OUT 7B7 66B3 OUT 7B7 66B3 OUT 7B7 66B3 1/16W TF 402 R9720 THRM_PAD 10.2 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm LED_RETURN_4 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm 0.1% 1/16W TF 402 R9721 GND_BKL_PWRGND 10.2 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm LED_RETURN_5 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm 0.1% B 1/16W TF 402 R9722 10.2 R9727 LED_RETURN_6 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm 0.1% 1/16W TF 402 15.0K BKLT_PLL BKL_LRT_RC 7B7 66B3 R9719 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm R9714 5% 1/16W MF-LF 402 LED_RETURN_2 0.1% BKL_ISEN6 BKLT_PLL 10K OUT 1/16W TF 402 PLACEMENT_NOTE=Away from Q9701 BKLT_PLL 10.2 BKL_ISEN5 1% 1/16W MF-LF 402 PPVOUT_S0_LCDBKLT PLACEMENT_NOTE=Away from Q9701 7C3 7C7 66B2 69C1 C9708 0.1UF 10% 25V X5R 402 CRITICAL VSEN MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm R9718 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm R9723 1.2M 1 5% 1/16W MF-LF 402 PLACEMENT_NOTE=Away from Q9701 IN 18 LRT BKL_ISEN4 1% 1/10W MF-LF 603 BKL_VSEN LCD BACKLIGHT DRIVER 2 BKL_VREF_4V9 70A7 18B6 ISEN6 16 BKL_ISEN3 R9724 SYNC_MASTER=YITE SYNC_DATE=08/12/2008 71.5K 69C4 69A8 7C3 69C8 B 69C8 69C4 69B6 7C3 ISEN5 15 19 LPF 13 20% 10V CERM 402 0.1UF e r C9705 ISEN4 14 20 DIM GNDA NOSTUFF BKL_SSTCMP_RC C9714 1UF NOSTUFF SSTCMP BKL_LPF RT BKL_SSTCMP BKL_DIM R9733 1 BKLT_PWM_RC R9709 BKL_RT LED_RETURN_1 0.1% 1/16W TF 402 BKL_ISEN2 21 PLACEMENT_NOTE=Away from Q9701 R9708 ISEN2 11 CRITICAL ISEN3 12 m il PLACEMENT_NOTE=Away from Q9701 100K ISET NOTICE OF PROPRIETARY PROPERTY 1% 1/16W MF-LF 402 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC *R9707, R9708, R9709, R9713, R9714, R9727, AND R9729 SHOULD AWAY FROM BOOST CIRCUIT REV 051-7537 SCALE SHT NONE C NOSTUFF BKL_ISEN1 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm PLACEMENT_NOTE=Away from Q9701 7C3 7C7 66B2 69B3 OUT VOLTAGE=30V MIN_NECK_WIDTH=0.20 mm MIN_LINE_WIDTH=0.5 mm A OF 97 109 A Q9806 FDC638APZ_SBMS001 PPBUS S0 LCDBkLT FET MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.6V 0402-HF PPBUS_S0_LCDBKLT_FUSED MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.6V R9808 FDC638APZ CHANNEL P-TYPE LOADING 0.1UF 1% 10% 16V X5R 402 1/16W MF-LF RDS(ON) D 43 mOhm @4.5V C9802 301K MOSFET IN 402 y r 0.4 A (EDP) D =PPBUS_S0_LCDBKLT 2AMP-32V 8C1 F9800 SSOT6-HF PPBUS_S0_LCDBKLT_EN_DIV R9809 147K 1% 1/16W MF-LF 402 PPBUS_S0_LCDBKLT_EN_L Q9807 D a n i SSM6N15FEAPE SOT563 70B7 18B6 LVDS_IG_BKL_ON IN G S PPBUS_S0_LCDBKLT_PWR MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.6V BKLT_EN_L Q9807 D S SSM6N15FEAPE SOT563 C 26C1 BKLT_PLT_RST_L IN R9840 1K 5% 1/16W MF-LF 402 R9841 1K 5% 1/16W MF-LF 402 A P 18B6 70C8 18B6 69A8 69C7 69D7 C m il e r B LVDS_IG_BKL_ON LVDS_IG_BKL_PWM G OUT B LCD Backlight Support SYNC_MASTER=YITE SYNC_DATE=06/30/2008 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC SCALE SHT NONE REV 051-7537 A OF 98 109 A FSB (Front-Side Bus) Constraints CPU / FSB Net Properties TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP FSB_50S * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD NET_TYPE ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING TABLE_PHYSICAL_RULE_ITEM FSB_DATA_GROUP0 FSB_50S FSB_DATA FSB_DATA_GROUP0 FSB_50S FSB_DATA FSB_DSTB0 FSB_DSTB_50S FSB_DSTB FSB_DSTB0 FSB_DSTB_50S FSB_DSTB FSB_DATA_GROUP1 FSB_50S FSB_DATA FSB_DATA_GROUP1 FSB_50S FSB_DATA FSB_DSTB1 FSB_DSTB_50S FSB_DSTB FSB_DSTB1 FSB_DSTB_50S FSB_DSTB FSB_DATA_GROUP2 FSB_50S FSB_DATA FSB_DATA_GROUP2 FSB_50S FSB_DATA FSB_DSTB2 FSB_DSTB_50S FSB_DSTB FSB_DSTB2 FSB_DSTB_50S FSB_DSTB FSB_DATA_GROUP3 FSB_50S FSB_DATA FSB_DATA_GROUP3 FSB_50S FSB_DATA FSB_DSTB3 FSB_DSTB_50S FSB_DSTB FSB_DSTB3 FSB_DSTB_50S FSB_DSTB FSB_ADDR_GROUP0 FSB_50S FSB_ADDR FSB_ADDR_GROUP0 FSB_50S FSB_ADDR FSB_ADSTB0 FSB_50S FSB_ADSTB FSB_ADDR_GROUP1 FSB_50S FSB_ADDR FSB_ADSTB1 FSB_50S FSB_ADSTB FSB_1X FSB_50S FSB_1X FSB_BREQ0_L FSB_50S FSB_1X FSB_BREQ1_L FSB_50S FSB_1X FSB_1X FSB_50S FSB_1X TABLE_PHYSICAL_RULE_ITEM * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =1:1_DIFFPAIR =1:1_DIFFPAIR TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LINE-TO-LINE SPACING WEIGHT FSB_DATA LAYER * =2x_DIELECTRIC ? FSB_DSTB * =3x_DIELECTRIC ? TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LINE-TO-LINE SPACING WEIGHT FSB_DATA TOP,BOTTOM LAYER =4x_DIELECTRIC ? FSB_DSTB TOP,BOTTOM =5x_DIELECTRIC ? TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM D TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM FSB_ADDR * =STANDARD TABLE_SPACING_RULE_ITEM ? FSB_ADDR TOP,BOTTOM =3x_DIELECTRIC ? TABLE_SPACING_RULE_ITEM FSB_ADSTB * =2x_DIELECTRIC TABLE_SPACING_RULE_ITEM ? FSB_ADSTB TOP,BOTTOM =4x_DIELECTRIC ? TABLE_SPACING_RULE_ITEM FSB_1X * =STANDARD FSB 4X Signal Groups FSB_DSTB_50S TABLE_SPACING_RULE_ITEM ? FSB_1X TOP,BOTTOM =3x_DIELECTRIC ? All 4x/2x/1x FSB signals with impedance requirements are 50-ohm single-ended FSB 2X Signals FSB 4X signals / groups shown in signal table on right Signals within each 4x group should be matched within ps of strobe DSTB# complementary pairs should be matched within ps of each other, all DSTB#s matched to +/- 300 ps Spacing is 2x dielectric between DATA#, DINV# signals, with 3x dielectric spacing to the DSTB#s DSTB# complementary pairs are spaced normally and are NOT routed as differential pairs FSB 2X signals / groups shown in signal table on right Signals within each 2x group should be matched within 20 ps ADTSB#s should be matched +/- 300 ps Spacing is 1x dielectric between ADDR#, REQ# signals, with 2x dielectric spacing to ADSTB# FSB 1X signals shown in signal table on right Signals within each 1x group should be matched to CPU clock, +0/-1000 mils FSB 1X Signals Design Guide recommends each strobe/signal group is routed on the same layer Intel Design Guide recommends FSB signals be routed only on internal layers NOTE: Intel Design Guide allows closer spacing if signal lengths can be shortened SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2 SOURCE: Santa Rosa Platform DG, Rev 1.5 (#22294), Sections 4.2 & 4.3 CPU Signal Constraints C PHYSICAL_RULE_SET LAYER MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM CPU_50S * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD FSB_50S FSB_1X FSB_50S FSB_1X FSB_1X FSB_50S FSB_1X FSB_1X FSB_50S FSB_1X FSB_1X FSB_50S FSB_1X FSB_1X FSB_50S FSB_1X FSB_1X FSB_50S FSB_1X FSB_CPURST_L FSB_50S FSB_1X FSB_1X FSB_50S FSB_1X FSB_1X FSB_50S FSB_1X CPU_ASYNC CPU_50S CPU_AGTL CPU_BSEL CPU_50S CPU_AGTL CPU_FERR_L CPU_50S CPU_8MIL CPU_ASYNC CPU_50S CPU_AGTL =STANDARD TABLE_PHYSICAL_RULE_ITEM CPU_27P4S * =27P4_OHM_SE =27P4_OHM_SE =27P4_OHM_SE =27P4_OHM_SE MIL MIL NOTE: mil gap is for VCCSense pair, which Intel says to route with mil spacing without specifying a target impedance TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT =STANDARD ? TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT =2x_DIELECTRIC ? TABLE_SPACING_RULE_ITEM CPU_AGTL * TABLE_SPACING_RULE_ITEM CPU_AGTL TOP,BOTTOM m il TABLE_SPACING_RULE_ITEM CPU_8MIL * MIL ? TABLE_SPACING_RULE_ITEM CPU_COMP * 25 MIL ? TABLE_SPACING_RULE_ITEM CPU_GTLREF * SR DG recommends at least 25 mils, >50 mils preferred ? 25 MIL TABLE_SPACING_RULE_ITEM CPU_ITP * =2:1_SPACING ? CPU_VCCSENSE * 25 MIL ? TABLE_SPACING_RULE_ITEM Most CPU signals with impedance requirements are 55-ohm single-ended Some signals require 27.4-ohm single-ended impedance SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2 SOURCE: Santa Rosa Platform DG, Rev 0.9 (#20517), Sections 4.4 & 5.8.2.4 e r MCP FSB COMP Signal Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MCP_50S * =50_OHM_SE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD TABLE_PHYSICAL_RULE_ITEM B TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM MCP_FSB_COMP * MIL ? SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2.4 FSB Clock Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER CLK_FSB_100D * ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH =100_OHM_DIFF MINIMUM NECK WIDTH =100_OHM_DIFF =100_OHM_DIFF TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT SPACING_RULE_SET TABLE_SPACING_RULE_ITEM CLK_FSB * =3x_DIELECTRIC ? CLK_FSB SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2.5 A P MAXIMUM NECK LENGTH =100_OHM_DIFF LAYER TOP,BOTTOM DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM =100_OHM_DIFF LINE-TO-LINE SPACING =4x_DIELECTRIC CPU_INIT_L CPU_50S CPU_AGTL CPU_ASYNC_R CPU_50S CPU_AGTL CPU_ASYNC_R CPU_50S CPU_AGTL CPU_PROCHOT_L CPU_50S CPU_AGTL CPU_PWRGD CPU_50S CPU_AGTL CPU_ASYNC CPU_50S CPU_AGTL CPU_ASYNC CPU_50S CPU_AGTL PM_THRMTRIP_L CPU_50S CPU_8MIL FSB_CPUSLP_L CPU_50S CPU_AGTL CPU_FROM_SB CPU_50S CPU_AGTL CPU_DPRSTP_L CPU_50S CPU_AGTL CPU_ASYNC CPU_50S CPU_AGTL MCP_CPU_COMP MCP_50S MCP_FSB_COMP MCP_CPU_COMP MCP_50S MCP_FSB_COMP MCP_CPU_COMP MCP_50S MCP_FSB_COMP MCP_CPU_COMP MCP_50S MCP_FSB_COMP FSB_CLK_CPU CLK_FSB_100D CLK_FSB FSB_CLK_CPU CLK_FSB_100D CLK_FSB FSB_CLK_ITP CLK_FSB_100D CLK_FSB FSB_CLK_ITP CLK_FSB_100D CLK_FSB FSB_CLK_MCP CLK_FSB_100D CLK_FSB FSB_CLK_MCP CLK_FSB_100D CLK_FSB CPU_IERR_L CPU_50S PM_DPRSLPVR CPU_50S CPU_AGTL (See above) CPU_50S CPU_AGTL CPU_GTLREF CPU_50S CPU_GTLREF CPU_COMP CPU_50S CPU_COMP CPU_COMP CPU_27P4S CPU_COMP CPU_COMP CPU_50S CPU_COMP CPU_COMP CPU_27P4S CPU_COMP XDP_TDI CPU_50S CPU_ITP XDP_TDO CPU_50S CPU_ITP XDP_TMS CPU_50S CPU_ITP XDP_TCK CPU_50S CPU_ITP XDP_TRST_L CPU_50S CPU_ITP XDP_BPM_L CPU_50S CPU_ITP XDP_BPM_L5 CPU_50S CPU_ITP (FSB_CPURST_L) CPU_50S CPU_ITP CPU_50S CPU_8MIL CPU_50S CPU_8MIL CPU_27P4S CPU_VCCSENSE TABLE_SPACING_RULE_HEAD TABLE_SPACING_RULE_ITEM FSB_D_L FSB_DINV_L FSB_DSTB_L_P FSB_DSTB_L_N FSB_D_L FSB_DINV_L FSB_DSTB_L_P FSB_DSTB_L_N FSB_A_L FSB_REQ_L FSB_ADSTB_L FSB_A_L FSB_ADSTB_L FSB_ADS_L FSB_BREQ0_L FSB_BREQ1_L FSB_BNR_L FSB_BPRI_L FSB_DBSY_L FSB_DEFER_L FSB_DRDY_L FSB_HIT_L FSB_HITM_L FSB_LOCK_L FSB_CPURST_L FSB_RS_L FSB_TRDY_L CPU_A20M_L CPU_BSEL CPU_FERR_L CPU_IGNNE_L CPU_INIT_L CPU_INTR CPU_NMI CPU_PROCHOT_L CPU_PWRGD CPU_SMI_L CPU_STPCLK_L PM_THRMTRIP_L FSB_CPUSLP_L CPU_DPSLP_L CPU_DPRSTP_L FSB_DPWR_L MCP_BCLK_VML_COMP_VDD MCP_BCLK_VML_COMP_GND MCP_CPU_COMP_VCC MCP_CPU_COMP_GND FSB_CLK_CPU_P FSB_CLK_CPU_N FSB_CLK_ITP_P FSB_CLK_ITP_N FSB_CLK_MCP_P FSB_CLK_MCP_N CPU_IERR_L =100_OHM_DIFF WEIGHT FSB_D_L FSB_DINV_L FSB_DSTB_L_P FSB_DSTB_L_N 10C4 14D3 10C4 14D6 10C4 14D6 10C4 14D6 10B4 10C4 14C3 14D3 10B4 14D6 10B4 14D6 D 10B4 14D6 10C2 14B3 14C3 y r 10C2 14D6 10C2 14D6 10C2 14D6 10B2 10C2 14B3 10B2 14D6 10B2 14D6 10B2 14D6 10D8 14C6 14D6 10D8 14B6 10D8 14B6 a n i FSB_1X FSB_1X TABLE_PHYSICAL_RULE_HEAD ALLOW ROUTE ON LAYER? FSB_D_L FSB_DINV_L FSB_DSTB_L_P FSB_DSTB_L_N 10C8 14B6 14C6 10C8 14B6 10D6 14B6 9B2 10D6 14B6 14B6 10D6 14B6 10D6 14B3 10D6 14B6 10D6 14B3 10D6 14B6 10C6 14B6 10C6 14B6 C 10D6 14B6 9B2 10D6 13B2 14A3 10D6 14A6 10D6 14B6 10C8 14A3 9C2 10A4 10B4 10C8 14B7 10C8 14A3 10D6 14A3 9B2 10B8 14A3 9B2 10B8 14A3 10C5 14B6 40D4 60C8 10B2 13C7 14A3 10B8 14A3 10B8 14A3 10C6 14B7 40C4 10A2 14A3 10B2 14A3 9B2 10B2 14A3 60C7 10B2 14A3 14A6 14A6 14A6 14A6 10B6 14B3 10B6 14B3 B 13C3 14A3 13B3 14A3 14A4 14A4 10D6 PM_DPRSLPVR IMVP_DPRSLPVR CPU_GTLREF CPU_COMP CPU_COMP CPU_COMP CPU_COMP 21C7 60D8 60C7 10B4 27B1 10B3 10B3 10B3 10B3 ? CPU_VCCSENSE CPU_VCCSENSE CPU_27P4S CPU_VCCSENSE (CPU_VCCSENSE) (CPU_VCCSENSE) CPU_27P4S CPU_VCCSENSE CPU_27P4S CPU_VCCSENSE XDP_TDI XDP_TDO XDP_TMS XDP_TCK XDP_TRST_L XDP_BPM_L XDP_BPM_L XDP_CPURST_L CPU_VID IMVP6_VID CPU_VCCSENSE_P CPU_VCCSENSE_N IMVP6_VSEN_P IMVP6_VSEN_N 6C6 10B6 10C6 13B3 6C4 10B6 10C6 6C6 6C7 10B6 10C6 13B3 6C6 6C7 10A6 10C6 13B6 6C6 6C7 10A6 10C6 13B3 10C6 13C6 10C5 13C6 13B4 11B6 60C7 CPU/FSB Constraints 11A5 60A5 SYNC_MASTER=T18_MLB SYNC_DATE=01/04/2008 11A5 60A5 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC SCALE SHT NONE REV 051-7537 A OF 100 109 A Memory Bus Constraints Memory Net Properties TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP MEM_40S * =40_OHM_SE =40_OHM_SE =40_OHM_SE =40_OHM_SE =STANDARD =STANDARD NET_TYPE ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING TABLE_PHYSICAL_RULE_ITEM MEM_A_CLK MEM_70D_VDD MEM_CLK MEM_A_CLK MEM_70D_VDD MEM_CLK MEM_A_CNTL MEM_40S_VDD MEM_CTRL MEM_A_CNTL MEM_40S_VDD MEM_CTRL MEM_A_CNTL MEM_40S_VDD MEM_CTRL MEM_A_CMD MEM_40S_VDD MEM_CMD MEM_A_CMD MEM_40S_VDD MEM_CMD MEM_A_CMD MEM_40S_VDD MEM_CMD MEM_A_CMD MEM_40S_VDD MEM_CMD MEM_A_CMD MEM_40S_VDD MEM_CMD MEM_A_DQ_BYTE0 TABLE_PHYSICAL_RULE_ITEM MEM_40S_VDD * =40_OHM_SE =40_OHM_SE =40_OHM_SE =40_OHM_SE =STANDARD =STANDARD MEM_A_CLK_P MEM_A_CLK_N 15B5 28C5 28C7 15B5 28C5 28C7 TABLE_PHYSICAL_RULE_ITEM MEM_70D * =70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF MEM_70D_VDD * =70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_HEAD SPACING_RULE_SET D LAYER LINE-TO-LINE SPACING WEIGHT =4:1_SPACING ? TABLE_SPACING_RULE_ITEM MEM_CLK2MEM * TABLE_SPACING_RULE_ITEM MEM_CTRL2CTRL * =2:1_SPACING ? MEM_A_CKE MEM_A_CS_L MEM_A_ODT MEM_A_A MEM_A_BA MEM_A_RAS_L MEM_A_CAS_L MEM_A_WE_L 15A5 28D5 28D7 15B5 28C5 28C7 15A5 28C5 15B5 15C5 28C5 28C7 15C5 28C5 28C7 15C5 28C7 y r 15C5 28C7 TABLE_SPACING_RULE_ITEM MEM_CTRL2MEM * =2.5:1_SPACING ? MEM_CMD2CMD * =1.5:1_SPACING ? MEM_40S MEM_DATA MEM_A_DQ_BYTE1 MEM_40S MEM_DATA MEM_A_DQ_BYTE2 MEM_40S MEM_DATA MEM_A_DQ_BYTE3 MEM_40S MEM_DATA MEM_A_DQ_BYTE4 MEM_40S MEM_DATA MEM_A_DQ_BYTE5 MEM_40S MEM_DATA MEM_A_DQ_BYTE6 MEM_40S MEM_DATA MEM_A_DQ_BYTE7 MEM_40S MEM_DATA MEM_A_DQ_BYTE0 MEM_40S MEM_DATA MEM_A_DQ_BYTE1 MEM_40S MEM_DATA MEM_A_DQ_BYTE2 MEM_40S MEM_DATA MEM_A_DQ_BYTE3 MEM_40S MEM_DATA MEM_A_DQ_BYTE4 MEM_40S MEM_DATA MEM_A_DQ_BYTE5 MEM_40S MEM_DATA MEM_A_DQ_BYTE6 MEM_40S MEM_DATA MEM_A_DQ_BYTE7 MEM_40S MEM_DATA MEM_A_DQS0 MEM_70D MEM_DQS MEM_A_DQS0 MEM_70D MEM_DQS MEM_A_DQS1 MEM_70D MEM_DQS MEM_A_DQS1 MEM_70D MEM_DQS MEM_A_DQS2 MEM_70D MEM_DQS MEM_A_DQS2 MEM_70D MEM_DQS MEM_A_DQS3 MEM_70D MEM_DQS MEM_A_DQS3 MEM_70D MEM_DQS MEM_A_DQS4 MEM_70D MEM_DQS MEM_A_DQS4 MEM_70D MEM_DQS MEM_A_DQS5 MEM_70D MEM_DQS MEM_A_DQS5 MEM_70D MEM_DQS MEM_A_DQS6 MEM_70D MEM_DQS MEM_70D MEM_DQS TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM MEM_CMD2MEM * =3:1_SPACING ? TABLE_SPACING_RULE_ITEM MEM_DATA2DATA * =1.5:1_SPACING ? TABLE_SPACING_RULE_ITEM MEM_DATA2MEM * =3:1_SPACING ? TABLE_SPACING_RULE_ITEM MEM_DQS2MEM * =3:1_SPACING ? MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ 15B7 28C2 28C4 28D2 28D4 15B7 28C2 28C4 15B7 15C7 28B2 28B4 28C2 28C4 15C7 28C2 28C4 15C7 28B5 28B7 15C7 28B5 28B7 15D7 28B5 28B7 15D7 28A5 28A7 TABLE_SPACING_RULE_ITEM MEM_2OTHER * 25 MIL ? Memory Bus Spacing Group Assignments TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET MEM_CLK MEM_CLK * MEM_CLK2MEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CMD MEM_CLK * MEM_CMD2MEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CLK MEM_CTRL * MEM_CLK2MEM MEM_CLK MEM_CMD * MEM_CLK2MEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CMD MEM_CTRL * MEM_CMD2MEM MEM_CMD MEM_CMD * MEM_CMD2CMD MEM_CMD MEM_DATA * MEM_CMD2MEM MEM_CMD MEM_DQS * MEM_CMD2MEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CLK MEM_DATA * MEM_CLK2MEM MEM_CLK MEM_DQS * MEM_CLK2MEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_HEAD C NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET MEM_CTRL MEM_CLK * MEM_CTRL2MEM TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET MEM_DATA MEM_CLK * MEM_DATA2MEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CTRL MEM_CTRL * MEM_CTRL2CTRL MEM_CTRL MEM_CMD * MEM_CTRL2MEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_DATA MEM_CTRL * MEM_DATA2MEM MEM_DATA MEM_CMD * MEM_DATA2MEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CTRL MEM_DATA * MEM_CTRL2MEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_DATA MEM_DATA * MEM_DATA2DATA TABLE_SPACING_ASSIGNMENT_ITEM MEM_CTRL MEM_DQS * MEM_CTRL2MEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_DATA MEM_DQS * MEM_DATA2MEM TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET MEM_DQS MEM_CLK * MEM_DQS2MEM MEM_DQS MEM_CTRL * MEM_DQS2MEM NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET MEM_CLK * * MEM_2OTHER MEM_CTRL * * MEM_2OTHER TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CMD * MEM_DQS2MEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CMD * * MEM_2OTHER TABLE_SPACING_ASSIGNMENT_ITEM MEM_DATA MEM_DQS * MEM_DQS2MEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_DATA * * MEM_2OTHER TABLE_SPACING_ASSIGNMENT_ITEM MEM_DQS MEM_DQS * MEM_DQS2MEM m il TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_DQS MEM_A_DQS6 TABLE_SPACING_ASSIGNMENT_HEAD TABLE_SPACING_ASSIGNMENT_ITEM MEM_DQS * * MEM_2OTHER Need to support MEM_*-style wildcards! DDR2: B DQ signals should be matched within 20 ps of associated DQS pair DQS intra-pair matching should be within ps, no inter-pair matching requirement All DQS pairs should be matched within 100 ps of clocks CLK intra-pair matching should be within ps, inter-pair matching should be within 140 ps A/BA/cmd signals should be matched within 75 ps, no CLK matching requirement All memory signals maximum length is 1.005 ps CLK minimum length is 594 ps (lengths include substrate) DQ/A/BA/cmd signal spacing is 3x dielectric, DQS/CLK is 4x dielectric e r DDR3: DQ signals should be matched within ps of associated DQS pair DQS intra-pair matching should be within ps, inter-pair matching shoulw be within 180 ps No DQS to clock matching requirement CLK intra-pair matching should be within ps, inter-pair matching should be within ps A/BA/cmd signals should be matched within ps of CLK pairs All memory signals maximum length is 1.005 ps CLK minimum length is 594 ps (lengths include substrate) DQ/A/BA/cmd signal spacing is 3x dielectric, DQS/CLK is 4x dielectric SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.3 SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Section 6.2 MCP MEM COMP Signal Constraints PHYSICAL_RULE_SET LAYER MCP_MEM_COMP * ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH Y MINIMUM NECK WIDTH MIL MIL TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM MCP_MEM_COMP * MIL ? SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.3.4 A P MAXIMUM NECK LENGTH =STANDARD DIFFPAIR PRIMARY GAP =STANDARD MEM_A_DQS7 MEM_70D MEM_DQS MEM_A_DQS7 MEM_70D MEM_DQS MEM_B_CLK MEM_70D_VDD MEM_CLK MEM_B_CLK MEM_70D_VDD MEM_CLK MEM_B_CNTL MEM_40S_VDD MEM_CTRL MEM_B_CNTL MEM_40S_VDD MEM_CTRL MEM_B_CNTL MEM_40S_VDD MEM_CTRL MEM_B_CMD MEM_40S_VDD MEM_CMD MEM_B_CMD MEM_40S_VDD MEM_CMD MEM_B_CMD MEM_40S_VDD MEM_CMD MEM_B_CMD MEM_40S_VDD MEM_CMD MEM_B_CMD MEM_40S_VDD MEM_CMD MEM_B_DQ_BYTE0 MEM_40S MEM_DATA MEM_B_DQ_BYTE1 MEM_40S MEM_DATA MEM_B_DQ_BYTE2 MEM_40S MEM_DATA MEM_B_DQ_BYTE3 MEM_40S MEM_DATA MEM_B_DQ_BYTE4 MEM_40S MEM_DATA MEM_B_DQ_BYTE5 MEM_40S MEM_DATA MEM_B_DQ_BYTE6 MEM_40S MEM_DATA MEM_B_DQ_BYTE7 MEM_40S MEM_DATA MEM_B_DQ_BYTE0 MEM_40S MEM_DATA MEM_B_DQ_BYTE1 MEM_40S MEM_DATA MEM_B_DQ_BYTE2 MEM_40S MEM_DATA MEM_B_DQ_BYTE3 MEM_40S MEM_DATA MEM_B_DQ_BYTE4 MEM_40S MEM_DATA MEM_B_DQ_BYTE5 MEM_40S MEM_DATA MEM_B_DQ_BYTE6 MEM_40S MEM_DATA MEM_B_DQ_BYTE7 MEM_40S MEM_DATA MEM_B_DQS0 MEM_70D MEM_DQS MEM_B_DQS0 MEM_70D MEM_DQS MEM_B_DQS1 MEM_70D MEM_DQS MEM_B_DQS1 MEM_70D MEM_DQS MEM_B_DQS2 MEM_70D MEM_DQS MEM_B_DQS2 MEM_70D MEM_DQS MEM_B_DQS3 MEM_70D MEM_DQS MEM_B_DQS3 MEM_70D MEM_DQS MEM_B_DQS4 MEM_70D MEM_DQS MEM_B_DQS4 MEM_70D MEM_DQS MEM_B_DQS5 MEM_70D MEM_DQS MEM_B_DQS5 MEM_70D MEM_DQS MEM_B_DQS6 MEM_70D MEM_DQS TABLE_PHYSICAL_RULE_HEAD DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM 15A7 28C4 a n i TABLE_SPACING_ASSIGNMENT_HEAD TABLE_SPACING_ASSIGNMENT_ITEM MEM_A_DM MEM_A_DM MEM_A_DM MEM_A_DM MEM_A_DM MEM_A_DM MEM_A_DM MEM_A_DM D 15C5 28C5 =STANDARD MEM_B_DQS6 MEM_70D MEM_DQS MEM_B_DQS7 MEM_70D MEM_DQS MEM_B_DQS7 MEM_70D MEM_DQS MCP_MEM_COMP MCP_MEM_COMP MCP_MEM_COMP MCP_MEM_COMP MCP_MEM_COMP MCP_MEM_COMP 15A7 28C2 15A7 28B4 15A7 28C2 15A7 28B5 15B7 28B7 15B7 28B5 15B7 28A7 MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_B_CLK_P MEM_B_CLK_N MEM_B_CKE MEM_B_CS_L MEM_B_ODT MEM_B_A MEM_B_BA MEM_B_RAS_L MEM_B_CAS_L MEM_B_WE_L MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DM MEM_B_DM MEM_B_DM MEM_B_DM MEM_B_DM MEM_B_DM MEM_B_DM MEM_B_DM 15D5 28C2 15D5 28C2 15D5 28C4 15D5 28C4 15D5 28B2 15D5 28B2 C 15D5 28C4 15D5 28C4 15D5 28B7 15D5 28B7 15D5 28B5 15D5 28B5 15D5 28B7 15D5 28B7 15D5 28A5 15D5 28A5 15B1 29C5 29C7 15B1 29C5 29C7 15A1 29D5 29D7 15B1 29C5 29C7 15A1 29C5 15B1 15C1 29C5 29C7 15C1 29C5 29C7 15C1 29C5 15C1 29C7 15C1 29C7 15B3 29C2 29C4 29D2 29D4 15B3 29C2 29C4 15B3 15C3 29C2 29C4 15C3 29B2 29B4 29C2 29C4 B 15C3 29B5 29B7 15C3 29B5 29B7 15D3 29B5 29B7 15D3 29A5 29A7 15A3 29C4 15A3 29C2 15A3 29C2 15A3 29B4 15A3 29B5 15B3 29B7 15B3 29B5 15B3 29A7 MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MCP_MEM_COMP_VDD MCP_MEM_COMP_GND 15D1 29C2 15D1 29C2 15D1 29C4 15D1 29C4 15D1 29C4 15D1 29C4 15D1 29B2 15D1 29B2 15D1 29B7 15D1 29B7 15D1 29B5 Memory Constraints 15D1 29B5 15D1 29B7 SYNC_MASTER=T18_MLB SYNC_DATE=01/04/2008 15D1 29B7 NOTICE OF PROPRIETARY PROPERTY 15D1 29A5 15D1 29A5 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING 16C6 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE 16C6 II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC SCALE SHT NONE REV 051-7537 A OF 101 109 A NET_TYPE PCI-Express ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP PCIE_90D * =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF PCIE_90D PCIE PCIE_90D PCIE PCIE_90D PCIE TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM CLK_PCIE_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF PCIE_MINI_R2D =100_OHM_DIFF PCIE_MINI_D2R TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM * =3X_DIELECTRIC ? CLK_PCIE * 20 MIL ? PCIE PCIE_90D PCIE PCIE_90D PCIE PCIE_90D PCIE PCIE_90D PCIE PCIE_90D PCIE PCIE_90D PCIE PCIE_90D PCIE PCIE_90D PCIE CLK_PCIE_100D CLK_PCIE CLK_PCIE_100D CLK_PCIE CLK_PCIE_100D CLK_PCIE CLK_PCIE_100D CLK_PCIE CLK_PCIE_100D CLK_PCIE CLK_PCIE_100D CLK_PCIE TABLE_SPACING_RULE_HEAD WEIGHT PCIE PCIE_90D PCIE TOP,BOTTOM =4X_DIELECTRIC ? D TABLE_SPACING_RULE_ITEM * MIL PCIE_FC_R2D ? SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.4 PCIE_FC_D2R MCP_PE1_REFCLK MCP_PE4_REFCLK MCP_PEX_COMP Digital Video Signal Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM DP_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF LVDS_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF MCP_DV_COMP * Y 20 MIL 20 MIL =STANDARD =STANDARD =STANDARD SPACING_RULE_SET LAYER TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_HEAD LINE-TO-LINE SPACING SPACING_RULE_SET LAYER LINE-TO-LINE SPACING * =3x_DIELECTRIC WEIGHT TABLE_SPACING_RULE_ITEM ? DISPLAYPORT TOP,BOTTOM =4x_DIELECTRIC ? TABLE_SPACING_RULE_ITEM LVDS * =3x_DIELECTRIC TABLE_SPACING_RULE_ITEM ? LVDS TOP,BOTTOM =4x_DIELECTRIC ? TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP SATA_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF SATA_100D_HDD * =100_OHM_DIFF_HDD =100_OHM_DIFF_HDD =100_OHM_DIFF_HDD =100_OHM_DIFF_HDD =100_OHM_DIFF_HDD =100_OHM_DIFF_HDD SPACING_RULE_SET LAYER DIFFPAIR NECK GAP e r TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_HEAD B =4x_DIELECTRIC ? TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT =3x_DIELECTRIC ? TABLE_SPACING_RULE_ITEM SATA * TABLE_SPACING_RULE_ITEM SATA TOP,BOTTOM TABLE_SPACING_RULE_ITEM SATA_TERMP * MIL ? SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.7.1 P A DISPLAYPORT DP_100D DISPLAYPORT TMDS_IG_TXD DP_100D DISPLAYPORT TMDS_IG_TXD DP_100D DISPLAYPORT DP_ML DP_100D DISPLAYPORT DP_100D DISPLAYPORT DP_100D DISPLAYPORT DP_100D DISPLAYPORT DP_100D DISPLAYPORT DP_100D DISPLAYPORT DP_100D DISPLAYPORT DP_100D DISPLAYPORT DP_100D DISPLAYPORT DP_100D DISPLAYPORT DP_AUX_CH SATA Interface Constraints WEIGHT DP_100D TMDS_IG_TXC DP_ML LVDS intra-pair matching should be mils Pairs should be within 100 mils of clock length DisplayPort/TMDS intra-pair matching should be ps Inter-pair matching should be within 150 ps DIsplayPort AUX CH intra-pair matching should be ps No relationship to other signals Max length of LVDS/DisplayPort/TMDS traces: 12 inches SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Sections 2.5.3 & 2.5.4 LINE-TO-LINE SPACING TMDS_IG_TXC m il TABLE_SPACING_RULE_HEAD WEIGHT TABLE_SPACING_RULE_ITEM DISPLAYPORT 7D5 31C7 17B3 31C5 17B3 31C5 7D5 17B6 31C7 7D5 17B6 31C7 32C5 32C5 9B5 32C6 MCP_DV_COMP MCP_HDMI_VPROBE MCP_DV_COMP LVDS_IG_A_CLK LVDS_100D LVDS LVDS_100D LVDS LVDS_100D LVDS LVDS_100D LVDS LVDS_IG_A_DATA LVDS_100D LVDS LVDS_IG_A_DATA LVDS_100D LVDS DP_ML DP_100D DISPLAYPORT DP_100D DISPLAYPORT I182 MCP_IFPAB_RSET SATA_HDD_R2D SATA_HDD_D2R SATA_ODD_R2D SATA_ODD_D2R DP_ML_P DP_ML_C_P DP_ML_N DP_ML_C_N DP_IG_AUX_CH_P DP_IG_AUX_CH_N DP_AUX_CH_SW_P DP_AUX_CH_SW_N DP_AUX_CH_C_P DP_AUX_CH_C_N LVDS_IG_A_CLK_P LVDS_IG_A_CLK_F_P LVDS_IG_A_CLK_N LVDS_IG_A_CLK_F_N LVDS_IG_A_DATA_P LVDS_IG_A_DATA_N DP_ML_CONN_P DP_ML_CONN_N SATA_100D SATA SATA_100D SATA SATA_100D SATA SATA_100D SATA SATA_HDD_R2D_C_P SATA_HDD_R2D_C_N SATA_HDD_R2D_P SATA_HDD_R2D_N SATA_HDD_R2D_UF_P SATA_HDD_R2D_UF_N SATA_HDD_D2R_P SATA_HDD_D2R_N SATA_HDD_D2R_C_P SATA_HDD_D2R_C_N SATA_HDD_D2R_UF_P SATA_HDD_D2R_UF_N SATA_ODD_R2D_C_P SATA_ODD_R2D_C_N SATA_ODD_R2D_P SATA_ODD_R2D_N SATA_ODD_R2D_UF_P SATA_ODD_R2D_UF_N SATA_ODD_D2R_P SATA_ODD_D2R_N SATA_ODD_D2R_C_P SATA_ODD_D2R_C_N SATA_ODD_D2R_UF_P SATA_ODD_D2R_UF_N SATA_TERMP MCP_SATA_TERMP SATA_100D_HDD SATA SATA_100D_HDD SATA SATA_100D_HDD SATA SATA_100D_HDD SATA SATA_100D_HDD SATA SATA_100D_HDD SATA SATA_100D_HDD SATA SATA_100D_HDD SATA SATA_100D_HDD SATA SATA_100D_HDD SATA SATA_100D_HDD SATA SATA_100D_HDD SATA SATA_100D SATA SATA_100D SATA SATA_100D SATA SATA_100D SATA SATA_100D SATA SATA_100D SATA SATA_100D SATA SATA_100D SATA 9B5 32B5 17C3 31C5 17C3 31C5 7D5 31C8 7D5 31C8 9B5 32C5 9B5 32C5 17A6 67D1 68C1 68C8 68C2 68C7 67D1 68B1 68C1 68C8 68B2 68C2 68C7 18B6 67C7 18B6 67B7 67C6 67C5 67C4 68C8 67D4 68B8 18A6 25C7 18A6 25C7 18B3 66B3 7C7 66B2 18B3 66B3 7C7 66B2 B 7C7 18B3 66C2 7C7 18B3 66C2 68C3 68C4 68C5 68B3 68C3 68C4 68C5 18A3 25C6 18A3 25C6 20D6 36A3 20D6 36A3 7C5 36A7 7C5 36A7 36A5 36A5 20D6 36A3 20D6 36A3 7C5 36A7 7C5 36A7 36A5 MCP Constraints 36A5 20D6 36C2 SYNC_MASTER=T18_MLB SYNC_DATE=01/04/2008 20D6 36C2 NOTICE OF PROPRIETARY PROPERTY 7B7 36B5 7B7 7C5 36B5 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING 36C4 36C4 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE 20D6 36B2 II NOT TO REPRODUCE OR COPY IT 20D6 36B2 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART 7B7 36B5 SIZE 7B7 36B5 DRAWING NUMBER D 36B4 36B4 APPLE INC MCP_SATA_TERMP C TMDS_IG_TXC_P TMDS_IG_TXC_N TMDS_IG_TXD_P TMDS_IG_TXD_N MCP_IFPAB_RSET MCP_IFPAB_VPROBE MCP_DV_COMP MCP_IFPAB_VPROBE 9B5 32B5 y r PCIE_CLK100M_FC_P PCIE_CLK100M_FC_N MCP_PEX_CLK_COMP D 9B5 32C6 PCIE_CLK100M_MINI_P PCIE_CLK100M_MINI_N PCIE_CLK100M_MINI_CONN_P PCIE_CLK100M_MINI_CONN_N MCP_HDMI_RSET MCP_HDMI_VPROBE MCP_HDMI_RSET LVDS_IG_A_CLK I183 PCIE_FC_R2D_P PCIE_FC_R2D_N PCIE_FC_R2D_C_P PCIE_FC_R2D_C_N PCIE_FC_D2R_P PCIE_FC_D2R_N a n i MCP_PEX_CLK_COMP C 7D5 31C7 TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM MCP_PEX_COMP PCIE_MINI_R2D_P PCIE_MINI_R2D_N PCIE_MINI_R2D_C_P PCIE_MINI_R2D_C_N PCIE_MINI_D2R_P PCIE_MINI_D2R_N SCALE SHT 20A6 NONE REV 051-7537 A OF 102 109 A PCI Bus Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP PCI_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD NET_TYPE ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING TABLE_PHYSICAL_RULE_ITEM MCP_DEBUG PCI_55S PCI PCI_AD PCI_55S PCI PCI_AD24 PCI_55S PCI PCI_AD PCI_55S PCI PCI_AD PCI_55S PCI PCI_C_BE_L PCI_55S PCI PCI_CNTL PCI_55S PCI PCI_CNTL PCI_55S PCI PCI_CNTL PCI_55S PCI PCI_CNTL PCI_55S PCI PCI_CNTL PCI_55S PCI PCI_CNTL PCI_55S PCI PCI_CNTL PCI_55S PCI PCI_REQ0_L PCI_55S PCI PCI_GNT0_L PCI_55S PCI PCI_REQ1_L PCI_55S PCI PCI_GNT1_L PCI_55S PCI PCI_INTW_L PCI_55S PCI PCI_INTX_L PCI_55S PCI PCI_INTY_L PCI_55S PCI PCI_INTZ_L PCI_55S PCI MCP_PCI_CLK2 CLK_PCI_55S CLK_PCI CLK_PCI_55S CLK_PCI LPC_AD LPC_55S LPC LPC_FRAME_L LPC_55S LPC LPC_RESET_L LPC_55S LPC TABLE_PHYSICAL_RULE_ITEM CLK_PCI_55S * SPACING_RULE_SET LAYER =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD TABLE_SPACING_RULE_HEAD LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM PCI * =STANDARD ? TABLE_SPACING_RULE_ITEM CLK_PCI D * MIL ? SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.8 LPC Bus Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM LPC_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD TABLE_PHYSICAL_RULE_ITEM CLK_LPC_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT MIL ? TABLE_SPACING_RULE_ITEM LPC * TABLE_SPACING_RULE_ITEM CLK_LPC * MIL USB 2.0 Interface Constraints ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM MCP_USB_RBIAS * =STANDARD MIL MIL =STANDARD =STANDARD =STANDARD USB_90D * =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF MCP_LPC_CLK0 TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT =2x_DIELECTRIC ? TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT =4x_DIELECTRIC ? TABLE_SPACING_RULE_ITEM USB C * USB_EXTA CLK_LPC_55S CLK_LPC CLK_LPC_55S CLK_LPC CLK_LPC_55S CLK_LPC USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB USB_90D USB TABLE_SPACING_RULE_ITEM USB TOP,BOTTOM SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.10.1 SMBus Interface Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP SMB_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD SPACING_RULE_SET LAYER TABLE_PHYSICAL_RULE_ITEM USB_CAMERA TABLE_SPACING_RULE_HEAD LINE-TO-LINE SPACING m il WEIGHT TABLE_SPACING_RULE_ITEM SMB * =2x_DIELECTRIC ? USB_BT SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.11.1 HD Audio Interface Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM HDA_55S * SPACING_RULE_SET LAYER =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD TABLE_SPACING_RULE_HEAD LINE-TO-LINE SPACING * =2x_DIELECTRIC ? USB_EXTB e r TABLE_SPACING_RULE_ITEM * MCP_HDA_COMP ? MIL SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.12.1 B SIO Signal Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM CLK_SLOW_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM CLK_SLOW * MIL ? SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.13 SPI Interface Constraints P =STANDARD LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP SPI_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD TABLE_SPACING_RULE_HEAD LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM SPI * MIL ? SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.14 A PCI_CLK33M_MCP_R PCI_CLK33M_MCP LPC_AD LPC_FRAME_L LPC_RESET_L LPC_CLK33M_SMC_R LPC_CLK33M_SMC LPC_CLK33M_LPCPLUS USB_EXTA_P USB_EXTA_N USB_EXTA_MUXED_P USB_EXTA_MUXED_N CONN_USB_EXTA_P CONN_USB_EXTA_N USB_CAMERA_P USB_CAMERA_N USB_CAMERA_CONN_P USB_CAMERA_CONN_N USB_BT_P USB_BT_N CONN_USB2_BT_P CONN_USB2_BT_N USB_TPAD_P USB_TPAD_N USB_TPAD_R_P USB_TPAD_R_N USB_IR_P USB_IR_N USB_EXTB_P USB_EXTB_N CONN_USB_EXTB_P CONN_USB_EXTB_N y r 19D2 19D7 19D2 19D7 MCP_USB_RBIAS_GND MCP_USB_RBIAS SMBUS_MCP_0_CLK SMB_55S SMB SMBUS_MCP_0_DATA SMB_55S SMB SMBUS_MCP_1_CLK SMB_55S SMB SMBUS_MCP_1_DATA SMB_55S SMB HDA_BIT_CLK HDA_55S HDA HDA_55S HDA HDA_55S HDA HDA_55S HDA HDA_55S HDA HDA_55S HDA HDA_55S HDA HDA_55S HDA HDA_55S HDA HDA_55S HDA HDA_BIT_CLK HDA_BIT_CLK_R HDA_SYNC HDA_SYNC_R HDA_RST_R_L HDA_RST_L HDA_SDIN0 HDA_SDIN_CODEC HDA_SDOUT HDA_SDOUT_R MCP_HDA_COMP MCP_HDA_PULLDN_COMP CLK_SLOW_55S CLK_SLOW CLK_SLOW_55S CLK_SLOW PM_CLK32K_SUSCLK_R PM_CLK32K_SUSCLK SPI_55S SPI SPI_55S SPI SPI_55S SPI SPI_55S SPI SPI_55S SPI SPI_55S SPI SPI_55S SPI SPI_55S SPI SPI_55S SPI SPI_55S SPI SPI_55S SPI SPI_55S SPI SPI_55S SPI HDA_SYNC HDA_RST_L TABLE_PHYSICAL_RULE_ITEM HDA_SDIN0 HDA_SDOUT MCP_HDA_PULLDN_COMP MCP_SUS_CLK SPI_CLK SPI_MOSI SPI_MISO SPI_CS0 19C5 19C5 19B3 39C8 41D3 41D5 19C3 39C8 41D5 19B3 26D4 19B3 26C4 26C1 39C8 26B1 41D3 20D3 37A8 20D3 37A8 37C4 37C4 C 37C3 37C3 20D3 31B5 20D3 31B5 7D5 31B7 7D5 31B7 20C3 31B5 20C3 31B5 7C5 31B7 7C5 31B7 20D3 47B8 20D3 47B8 47B7 47B7 20D3 38C7 20D3 38C7 20C3 37A4 20C3 37A4 37A3 37A3 B MCP_USB_RBIAS TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET SPACING_RULE_SET USB_TPAD USB_IR WEIGHT TABLE_SPACING_RULE_ITEM HDA D a n i TABLE_PHYSICAL_RULE_HEAD LAYER 13C3 19D7 ? SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.9.1 PHYSICAL_RULE_SET MCP_DEBUG PCI_AD PCI_AD PCI_AD PCI_PAR PCI_C_BE_L PCI_IRDY_L PCI_DEVSEL_L PCI_PERR_L PCI_SERR_L PCI_STOP_L PCI_TRDY_L PCI_FRAME_L PCI_REQ0_L PCI_GNT0_L PCI_REQ1_L PCI_GNT1_L PCI_INTW_L PCI_INTX_L PCI_INTY_L PCI_INTZ_L SMBUS_MCP_0_CLK SMBUS_MCP_0_DATA SMBUS_MCP_1_CLK SMBUS_MCP_1_DATA SPI_CLK_R SPI_CLK SPI_ALT_CLK SPI_MOSI_R SPI_MOSI SPI_ALT_MOSI SPI_MISO SPI_MISO_R SPI_ALT_MISO SPI_CS0_R_L SPI_CS0_L 20B4 13B6 21C3 42D8 13B6 21C3 42D8 21C3 42C8 21C3 42C8 21D2 51C7 21A7 21D4 21C2 51C7 21A7 21C4 21A7 21D4 21D2 51B7 21D7 51C7 21D2 51C7 21A7 21D4 21C7 21B3 26B4 26B1 39C5 MCP Constraints 21B3 41A5 41C8 41A1 50C5 SYNC_MASTER=T18_MLB 41C5 41D3 21B3 41A5 41C7 SYNC_DATE=12/14/2007 NOTICE OF PROPRIETARY PROPERTY 41B1 50C4 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING 41C5 41D5 21B3 41A5 41B7 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE 50C4 II NOT TO REPRODUCE OR COPY IT 41B5 41D5 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART 21B3 41B7 SIZE SPI_CS1_R_L SPI_CS1_R_L_USE_MLB DRAWING NUMBER D 41B2 APPLE INC SCALE SHT NONE REV 051-7537 A OF 103 109 A MCP RGMII (Ethernet) Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP MCP_MII_COMP * =STANDARD 7.5 MIL 7.5 MIL =STANDARD =STANDARD =STANDARD NET_TYPE ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING TABLE_PHYSICAL_RULE_ITEM MCP_MII_COMP_VDD MCP_MII_COMP_GND MCP_MII_COMP MCP_MII_COMP MCP_MII_COMP MCP_MII_COMP MCP_CLK25M_BUF0 ENET_MII_55S MCP_BUF0_CLK ENET_MII_55S MCP_BUF0_CLK ENET_MII_55S ENET_MII TABLE_PHYSICAL_RULE_ITEM ENET_MII_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT MCP_CLK25M_BUF0_R RTL8211_CLK25M_CKXTAL1 18C6 18C6 18C3 34A5 33B6 34A3 TABLE_SPACING_RULE_ITEM MCP_BUF0_CLK * =3:1_SPACING ? ENET_MII * 12 MIL ? ENET_INTR_L TABLE_SPACING_RULE_ITEM D SOURCE: MCP73 Interface DG (DG-02974-001_v01), Sections 2.7.2 & 2.7.4 88E1116R (Ethernet PHY) Constraints ENET_MDIO ENET_MII_55S ENET_MII ENET_MDC ENET_MII_55S ENET_MII ENET_PWRDWN_L ENET_MII_55S ENET_MII ENET_MII_55S ENET_MII ENET_MII_55S ENET_MII ENET_MII_55S ENET_MII ENET_RXD ENET_MII_55S ENET_MII ENET_RXD_STRAP ENET_MII_55S ENET_MII ENET_RXD ENET_MII_55S ENET_MII ENET_MII_55S ENET_MII ENET_MII_55S ENET_MII ENET_TXCLK ENET_MII_55S ENET_MII ENET_TXD0 ENET_MII_55S ENET_MII ENET_TXD ENET_MII_55S ENET_MII ENET_TXD ENET_MII_55S ENET_MII ENET_CLK125M_TXCLK_R ENET_CLK125M_TXCLK ENET_TXD ENET_TXD ENET_TX_CTRL ENET_MII_55S ENET_MII ENET_RESET_L ENET_MDI_100D ENET_MDI ENET_MDI_100D ENET_MDI ENET_MDI_100D ENET_MDI ENET_MDI_100D ENET_MDI ENET_MDI_P ENET_MDI_N ENET_MDI_TRAN_P ENET_MDI_TRAN_N ENET_RXCLK TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP ENET_MDI_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT 25 MIL ? TABLE_SPACING_RULE_ITEM ENET_MDI * SOURCE: MCP73 Interface DG (DG-02974-001_v01), Section 2.7.4 ENET_INTR_L ENET_MDIO ENET_MDC ENET_PWRDWN_L ENET_CLK125M_RXCLK_R ENET_CLK125M_RXCLK ENET_RXD_R ENET_RXD ENET_RXD ENET_RX_CTRL ENET_RXCTL_R 18C3 33B6 18C3 33B6 D 33C4 y r 18D6 33C1 33B4 33C4 18D6 33C1 18D6 33B1 33C1 18D6 33B1 33B4 33C6 18D3 33C8 18D3 33C6 18D3 33B6 33C6 a n i ENET_MDI C 18C3 33B6 18C3 33B7 33B3 35B7 35C7 33B3 35B7 35C7 35B4 35C4 35C5 35B4 35C4 35C5 C m il e r B P A B Ethernet Constraints SYNC_MASTER=T18_MLB SYNC_DATE=03/19/2008 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC SCALE SHT NONE REV 051-7537 A OF 104 109 A SMC SMBus Net Properties TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 1TO1_DIFFPAIR * =STANDARD =STANDARD =STANDARD =STANDARD 0.1 MM 0.1 MM NET_TYPE ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING TABLE_PHYSICAL_RULE_ITEM D SMBUS_SMC_A_S3_SCL SMB_55S SMB SMBUS_SMC_A_S3_SDA SMB_55S SMB SMBUS_SMC_B_S0_SCL SMB_55S SMB SMBUS_SMC_B_S0_SDA SMB_55S SMB SMBUS_SMC_0_S0_SCL SMB_55S SMB SMBUS_SMC_0_S0_SDA SMB_55S SMB SMBUS_SMC_BSA_SCL SMB_55S SMB SMBUS_SMC_BSA_SDA SMB_55S SMB SMBUS_SMC_MGMT_SCL SMB_55S SMB SMBUS_SMC_MGMT_SDA SMB_55S SMB SMBUS_SMC_A_S3_SCL SMBUS_SMC_A_S3_SDA SMBUS_SMC_B_S0_SCL SMBUS_SMC_B_S0_SDA SMBUS_SMC_0_S0_SCL SMBUS_SMC_0_S0_SDA SMBUS_SMC_BSA_SCL SMBUS_SMC_BSA_SDA SMBUS_SMC_MGMT_SCL SMBUS_SMC_MGMT_SDA 7B5 7D5 42D2 7B5 7C5 42D2 42C2 42C2 42D5 42D5 7A7 42C5 42C5 42B5 y r SMBus Charger Net Properties NET_TYPE ELECTRICAL_CONSTRAINT_SET PHYSICAL CHGR_CSI 1TO1_DIFFPAIR 1TO1_DIFFPAIR CHGR_CSO 1TO1_DIFFPAIR 1TO1_DIFFPAIR D 42B5 SPACING CHGR_CSI_P CHGR_CSI_N CHGR_CSO_P CHGR_CSO_N a n i C C m il e r B P A B SMC Constraints SYNC_MASTER=T18_MLB SYNC_DATE=01/04/2008 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC SCALE SHT NONE REV 051-7537 A OF 106 109 A M97 SENSOR NET PROPERTIES TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP DIFFPAIR * =STANDARD =STANDARD =STANDARD =STANDARD 0.1 MM 0.1 MM NET_TYPE ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING TABLE_PHYSICAL_RULE_ITEM DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR D DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR CHGR_CSO_R_P CHGR_CSO_R_N CPUTHMSNS_D2_P CPUTHMSNS_D2_N CPU_THERMD_P CPU_THERMD_N ISNS_CPUVTT_P ISNS_CPUVTT_N ISNS_P1V5S0MCP_P ISNS_P1V5S0MCP_N ISNS_PVCORES0MCP_P ISNS_PVCORES0MCP_N MCPTHMSNS_D2_P MCPTHMSNS_D2_N MCP_THMDIODE_P MCP_THMDIODE_N 44A8 57B3 44A8 57B3 45C5 45C5 10C6 45D5 10C6 45D5 44B7 44B7 D 44C7 44C7 y r 44D8 44D8 61C4 7C7 45B5 7C7 45B5 21C3 45C5 21C3 45B5 a n i C C m il e r B P A B M97 SPECIAL CONSTRAINTS SYNC_MASTER=M97_MLB A NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC SCALE SHT NONE REV 051-7537 A OF 107 109 M97 BOARD-SPECIFIC SPACING & PHYSICAL CONSTRAINTS TABLE_BOARD_INFO BOARD LAYERS BOARD AREAS BOARD UNITS (MIL or MM) ALLEGRO VERSION TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM NO_TYPE,BGA_P1MM MM 15.5.1 TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE TABLE_SPACING_RULE_ITEM DEFAULT * 0.1 MM ? PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP STANDARD * =DEFAULT ? TABLE_PHYSICAL_RULE_ITEM BGA_P1MM * =DEFAULT ? TABLE_PHYSICAL_RULE_ITEM BGA_P2MM * =DEFAULT ? * * BGA_P1MM * Y =50_OHM_SE 0.100MM 30 MM MM MM * Y =DEFAULT =DEFAULT 12.7 MM =DEFAULT =DEFAULT * BGA_P1MM BGA_P2MM CLK_FSB * BGA_P1MM BGA_P2MM CLK_LPC * BGA_P1MM BGA_P2MM BGA_P3MM MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP * =DEFAULT ? LINE-TO-LINE SPACING WEIGHT TOP,BOTTOM Y MEM_40S_VDD BGA_P1MM STANDARD TABLE_PHYSICAL_ASSIGNMENT_ITEM CLK_PCI * BGA_P1MM BGA_P2MM CLK_PCIE * BGA_P1MM BGA_P2MM CLK_SLOW * BGA_P1MM BGA_P2MM TABLE_PHYSICAL_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM DIFFPAIR NECK GAP D TABLE_SPACING_RULE_HEAD SPACING_RULE_SET TABLE_PHYSICAL_RULE_ITEM 55_OHM_SE STANDARD TABLE_SPACING_ASSIGNMENT_ITEM TABLE_PHYSICAL_RULE_HEAD MINIMUM LINE WIDTH BGA_P1MM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_RULE_ITEM ALLOW ROUTE ON LAYER? MEM_40S BGA_P1MM MEM_CLK TABLE_SPACING_RULE_ITEM DEFAULT LAYER PHYSICAL_RULE_SET DIFFPAIR NECK GAP STANDARD PHYSICAL_RULE_SET AREA_TYPE TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_RULE_ITEM D TABLE_PHYSICAL_ASSIGNMENT_HEAD NET_PHYSICAL_TYPE TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD SPACING_RULE_SET 0.090 MM LAYER 0.090 MM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM 55_OHM_SE * Y 0.076 MM 0.076 MM =STANDARD =STANDARD 1.5:1_SPACING * 0.15 MM ? 2:1_SPACING * 0.2 MM ? y r TABLE_SPACING_ASSIGNMENT_ITEM =STANDARD FSB_DSTB FSB_DSTB BGA_P1MM TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH 50_OHM_SE TOP,BOTTOM Y 0.115 MM 0.115 MM MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP TABLE_SPACING_RULE_ITEM DIFFPAIR NECK GAP 2.5:1_SPACING * 0.25 MM ? 3:1_SPACING * 0.3 MM ? 4:1_SPACING * 0.4 MM ? LINE-TO-LINE SPACING WEIGHT ? TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM 50_OHM_SE * Y 0.076 MM 0.076 MM =STANDARD =STANDARD =STANDARD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER TABLE_PHYSICAL_RULE_ITEM 40_OHM_SE TOP,BOTTOM Y TABLE_SPACING_RULE_ITEM 0.100 MM 0.165 MM 2X_DIELECTRIC TOP,BOTTOM 0.140 MM 3X_DIELECTRIC TOP,BOTTOM 0.210 MM ? 4X_DIELECTRIC TOP,BOTTOM 0.280 MM ? 5X_DIELECTRIC TOP,BOTTOM 0.350 MM ? 2X_DIELECTRIC * 0.126 MM ? a n i TABLE_PHYSICAL_RULE_ITEM 40_OHM_SE * Y 0.126 MM 0.100 MM =STANDARD =STANDARD =STANDARD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM 27P4_OHM_SE TOP,BOTTOM Y 0.310 MM 0.310 MM 27P4_OHM_SE * Y 0.222 MM 0.222 MM TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM =STANDARD =STANDARD =STANDARD TABLE_SPACING_RULE_ITEM 3X_DIELECTRIC * 0.189 MM ? 4X_DIELECTRIC * 0.252 MM ? 5X_DIELECTRIC * 0.315 MM ? TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 70_OHM_DIFF * N =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD 70_OHM_DIFF ISL3,ISL4,ISL9,ISL10 Y 0.151 MM 0.100 MM =STANDARD 0.224 MM 0.224 MM 70_OHM_DIFF TOP,BOTTOM Y 0.185 MM 0.100 MM 0.200 MM 0.200 MM PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 90_OHM_DIFF * N =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD 90_OHM_DIFF ISL3,ISL4,ISL9,ISL10 Y 0.095 MM 0.095 MM 0.234 MM 0.234 MM 90_OHM_DIFF TOP,BOTTOM Y 0.112 MM 0.112 MM 0.220 MM 0.220 MM PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 100_OHM_DIFF * N =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD 100_OHM_DIFF ISL3,ISL4,ISL9,ISL10 Y 0.075 MM 0.075 MM 0.244 MM 0.244 MM 100_OHM_DIFF TOP,BOTTOM Y 0.091 MM 0.091 MM 0.230 MM 0.230 MM PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 100_OHM_DIFF_HDD * N =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD 100_OHM_DIFF_HDD ISL3,ISL4,ISL9,ISL10 Y 0.083 MM 0.083 MM 0.400 MM 0.400 MM 100_OHM_DIFF_HDD TOP,BOTTOM Y 0.095 MM 0.095 MM 0.400 MM 0.400 MM PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM C TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM e r TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD TABLE_PHYSICAL_RULE_ITEM B 110_OHM_DIFF * N =STANDARD =STANDARD 110_OHM_DIFF ISL3,ISL4,ISL9,ISL10 Y 0.075 MM 0.075 MM =STANDARD =STANDARD =STANDARD 0.330 MM 0.330 MM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM 110_OHM_DIFF TOP,BOTTOM Y 0.077 MM 0.077 MM PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH 1:1_DIFFPAIR * Y =STANDARD =STANDARD 0.330 MM 0.330 MM DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_HEAD A MAXIMUM NECK LENGTH P =STANDARD 0.1 MM C m il TABLE_PHYSICAL_RULE_HEAD MAXIMUM NECK LENGTH BGA_P3MM TABLE_PHYSICAL_RULE_ITEM 0.1 MM B M97 RULE DEFINITIONS SYNC_MASTER=M97_MLB A NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC SCALE SHT NONE REV 051-7537 A OF 109 109 ... PCBA,MLB,BEST ,M97 M97_COMMON,CPU_2_4GHZ,EEE_1DJ BOM Groups D D TABLE_BOMGROUP_HEAD BOM GROUP BOM OPTIONS M97_ COMMON COMMON,ALTERNATE ,M97_ MCP ,M97_ MISC ,M97_ DEBUG_PVT ,M97_ PROGPARTS M97_ MCP MCP_B02,MCP_PROD,MEMRESET_HW,MEMRESET_MCP,BOOT_MODE_USER,MCPSEQ_SMC,MCP_CS1_NO... 1.4DIA-SHORT-EMI-MLB -M97- M98 1.4DIA-SHORT-EMI-MLB -M97- M98 SM SM SM SIGNAL ALIAS ZS0904 ZS0905 ZS0906 ZS0907 2.0DIA-TALL-EMI-MLB -M97- M98 2.0DIA-TALL-EMI-MLB -M97- M98 2.0DIA-TALL-EMI-MLB -M97- M98 SM SM... MCP_B02,MCP_PROD,MEMRESET_HW,MEMRESET_MCP,BOOT_MODE_USER,MCPSEQ_SMC,MCP_CS1_NO M97_ MISC ONEWIRE_PU,BKLT_PLL_NOT,DP_ESD,ENG_BMON,MIKEY M97_ PROGPARTS BOOTROM_PROG,SMC_PROG,IR_PROG,WELLSPRING_PROG M97_ DEBUG_ENG SMC_DEBUG_YES,XDP,XDP_CONN,LPCPLUS,VREFMRGN,TPAD_DEBUG M97_ DEBUG_PVT