apple macbook pro a1297 k92

8 ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5% ALL CAPACITANCE VALUES ARE IN MICROFARADS ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ Date Contents TABLE_TABLEOFCONTENTS_HEAD TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM C TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM B TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM Sync 1 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 ECN DESCRIPTION OF REVISION Table of Contents K17_MLB System Block Diagram K60_MLB Revision History K17_MLB Revision History K17_MLB BOM Configuration TABLE_TABLEOFCONTENTS_HEAD 04/26/2010 TABLE_TABLEOFCONTENTS_ITEM 04/26/2010 TABLE_TABLEOFCONTENTS_ITEM 04/26/2010 TABLE_TABLEOFCONTENTS_ITEM 04/26/2010 TABLE_TABLEOFCONTENTS_ITEM 04/26/2010 TABLE_TABLEOFCONTENTS_ITEM 04/26/2010 TABLE_TABLEOFCONTENTS_ITEM 04/26/2010 TABLE_TABLEOFCONTENTS_ITEM 04/26/2010 TABLE_TABLEOFCONTENTS_ITEM K17_MLB Functional / ICT Test K17_MLB Power Aliases K17_MLB Signal Aliases K17_MLB CPU DMI/PEG/FDI/RSVD K60_MLB 10 11 CPU CLOCK/MISC/JTAG 07/16/2010 TABLE_TABLEOFCONTENTS_ITEM 04/26/2010 TABLE_TABLEOFCONTENTS_ITEM 07/16/2010 TABLE_TABLEOFCONTENTS_ITEM 04/26/2010 TABLE_TABLEOFCONTENTS_ITEM 07/21/2010 TABLE_TABLEOFCONTENTS_ITEM 07/21/2010 TABLE_TABLEOFCONTENTS_ITEM 10/19/2010 TABLE_TABLEOFCONTENTS_ITEM K91_MLB 12 CPU DDR3 INTERFACES K60_MLB 13 CPU POWER K91_MLB 14 CPU POWER AND GND K60_MLB 16 CPU DECOUPLING-I K91_MLB 17 CPU DECOUPLING-II K91_MLB PCH SATA/PCIE/CLK/LPC/SPI K91_MLB PCH DMI/FDI/GRAPHICS K91_MLB 18 19 20 PCH PCI/FLASHCACHE/USB 10/17/2010 TABLE_TABLEOFCONTENTS_ITEM 10/20/2010 TABLE_TABLEOFCONTENTS_ITEM 10/20/2010 TABLE_TABLEOFCONTENTS_ITEM 07/09/2010 TABLE_TABLEOFCONTENTS_ITEM 05/20/2010 TABLE_TABLEOFCONTENTS_ITEM 08/06/2010 TABLE_TABLEOFCONTENTS_ITEM 10/17/2010 TABLE_TABLEOFCONTENTS_ITEM K91_MLB 21 PCH MISC K91_MLB 22 PCH POWER K91_MLB 23 PCH GROUNDS K92_YUN 24 PCH DECOUPLING K91_YUN CPU & PCH XDP K91_MLB 25 26 USB HUBS 06/29/2010 TABLE_TABLEOFCONTENTS_ITEM 06/29/2010 TABLE_TABLEOFCONTENTS_ITEM 06/14/2010 TABLE_TABLEOFCONTENTS_ITEM 05/14/2010 TABLE_TABLEOFCONTENTS_ITEM 06/14/2010 TABLE_TABLEOFCONTENTS_ITEM 04/26/2010 TABLE_TABLEOFCONTENTS_ITEM 08/26/2010 TABLE_TABLEOFCONTENTS_ITEM K92_BEN 28 Chipset Support K91_MLB 29 DDR3 SO-DIMM Connector A K92_YUN 30 DDR3 Byte/Bit Swaps K92_YUN 31 DDR3 SO-DIMM Connector B K92_YUN 32 CPU Memory S3 Support K17_MLB FSB/DDR3/FRAMEBUF Vref Margining K91_YUN 33 34 X19/ALS/CAMERA CONNECTOR 10/21/2010 TABLE_TABLEOFCONTENTS_ITEM 07/27/2010 TABLE_TABLEOFCONTENTS_ITEM 11/09/2010 TABLE_TABLEOFCONTENTS_ITEM 11/09/2010 TABLE_TABLEOFCONTENTS_ITEM 11/09/2010 TABLE_TABLEOFCONTENTS_ITEM 10/19/2010 TABLE_TABLEOFCONTENTS_ITEM 08/24/2010 TABLE_TABLEOFCONTENTS_ITEM 10/20/2010 TABLE_TABLEOFCONTENTS_ITEM 10/20/2010 TABLE_TABLEOFCONTENTS_ITEM 07/22/2010 TABLE_TABLEOFCONTENTS_ITEM 11/08/2010 TABLE_TABLEOFCONTENTS_ITEM 08/24/2010 TABLE_TABLEOFCONTENTS_ITEM K91_MLB 35 ExpressCard Connector K92_ERIC 36 T29 Host (1 of 2) T29_REF 37 T29 Host (2 of 2) T29_REF 38 T29 Power Support T29_REF 39 ETHERNET PHY (CAESAR IV) K92_ERIC Ethernet Connector K92_ERIC 40 41 FireWire LLC/PHY (FW643) K91_MLB 42 FireWire Port & PHY Power K91_MLB 43 FireWire Connector K91_MLB 45 SATA Connectors K92_ERIC External USB Connectors K92_ERIC 46 47 PROJECT SPECIFIC CONNS 07/22/2010 TABLE_TABLEOFCONTENTS_ITEM 04/26/2010 TABLE_TABLEOFCONTENTS_ITEM 07/12/2010 TABLE_TABLEOFCONTENTS_ITEM K92_ERIC 48 Front Flex Support K17_MLB 49 SMC K91_BEN 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 CK APPD DATE 2009-05-19 rev3.11.3 (.csa) Date Page 04/27/2010 TABLE_TABLEOFCONTENTS_ITEM Contents Sync 50 SMC Support K91_BEN LPC+SPI Debug Connector K91_YUN 51 52 K92 SMBus Connections K17_MLB Voltage & Load Side Current Sensing K92_DINESH 53 54 High Side and CPU/AXG Current Sensing (.csa) 07/12/2010 TABLE_TABLEOFCONTENTS_HEAD 09/23/2010 TABLE_TABLEOFCONTENTS_ITEM 04/26/2010 TABLE_TABLEOFCONTENTS_ITEM 09/24/2010 TABLE_TABLEOFCONTENTS_ITEM 10/29/2010 TABLE_TABLEOFCONTENTS_ITEM 09/24/2010 TABLE_TABLEOFCONTENTS_ITEM 04/26/2010 TABLE_TABLEOFCONTENTS_ITEM 10/11/2010 TABLE_TABLEOFCONTENTS_ITEM 07/27/2010 TABLE_TABLEOFCONTENTS_ITEM K92_DINESH 55 Thermal Sensors K92_DINESH 56 Fan Connectors K17_MLB 57 WELLSPRING K92_ERIC WELLSPRING K92_ERIC 58 59 Digital Accelerometer 06/02/2010 TABLE_TABLEOFCONTENTS_ITEM 05/27/2010 TABLE_TABLEOFCONTENTS_ITEM 07/30/2010 TABLE_TABLEOFCONTENTS_ITEM 06/16/2010 TABLE_TABLEOFCONTENTS_ITEM 10/22/2010 TABLE_TABLEOFCONTENTS_ITEM 10/22/2010 TABLE_TABLEOFCONTENTS_ITEM 11/02/2010 TABLE_TABLEOFCONTENTS_ITEM K92_DINESH 61 SPI ROM K92_BEN 62 AUDIO:CODEC K92_KAVITHA 63 AUDIO: LINE IN K92_AUDIO 65 AUDIO: HEADPHONE OUT K92_KAVITHA 66 AUDIO:SPEAKER AMP K92_KAVITHA AUDIO: JACKS K92_KAVITHA AUDIO: JACK TRANSLATORS K92_KAVITHA DC-In & Battery Connectors K92_CHANG PBus Supply & Battery Charger K91_CHANG System Agent Supply K91_CHANG 5V / 3.3V Power Supply K92_ERIC 1.5V DDR3 Supply K91_CHANG CPU IMVP7 & AXG VCore Regulator K92_ERIC CPU IMVP7 & AXG VCore Output K92_ERIC CPU VCCIO (1.05V) Power Supply K92_ERIC Misc Power Supplies K91_CHANG Power FETs K91_MLB Power Control 1/ENABLE K92_YUAN Whistler PCI-E K91_MLB Whistler CORE/FB POWER K92_BEN Whistler FRAME BUFFER I/F K18_MLB GDDR5 Frame Buffer A K91_YUN GDDR5 Frame Buffer B K91_YUN Whistler LVDS/DP/GPIO K92_SUMA Whistler GPIOs & STRAPs K91_MLB 67 68 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 D Date Page Contents Sync 99 07/30/2010 Power Sequencing EG/PCH S0 K92_YUAN CPU Constraints K91_MLB Memory Constraints K17_MLB PCH Constraints K92_YUN PCH Constraints K91_MLB Ethernet/FW Constraints K91_MLB T29 Constraints T29_REF SMC Constraints K17_MLB GPU (Whistler) CONSTRAINTS K91_MLB Project Specific Constraints K91_MLB PCB Rule Definitions K17_MLB PCH Power Aliases K17_MLB DEBUG SENSORS AND ADC K92_DINESH DEBUG SENSORS AND ADC K92_DINESH Power Supplies BIST K92_DINESH 100 07/22/2010 101 05/14/2010 102 06/25/2010 103 07/22/2010 104 07/22/2010 105 10/20/2010 106 05/14/2010 107 07/21/2010 108 07/22/2010 109 05/14/2010 121 04/27/2010 130 09/07/2010 131 07/28/2010 132 08/23/2010 C 11/22/2010 69 06/28/2010 70 07/21/2010 71 07/21/2010 72 08/30/2010 73 07/21/2010 74 11/09/2010 75 09/27/2010 76 09/23/2010 77 07/21/2010 78 10/18/2010 79 07/22/2010 80 10/19/2010 81 06/03/2010 82 04/27/2010 84 08/23/2010 85 08/23/2010 86 10/21/2010 87 B 07/17/2010 88 06/01/2010 Whistler DP PWR/GNDs K92_BEN GPU (Whistler) CORE SUPPLY K91_CHANG LVDS Display Connector K17_MLB Muxed Graphics Support K92_YUN DisplayPort/T29 A MUXing K91_MLB DisplayPort/T29 A Connector K91_MLB 1V0 GPU / 1V5 FB Power Supply K91_CHANG Graphics MUX (GMUX) K92_YUAN LCD Backlight Driver (LP8545) K92_DINESH 89 07/21/2010 90 04/26/2010 92 06/25/2010 93 10/22/2010 94 10/22/2010 95 07/21/2010 96 07/28/2010 09/07/2010 97 98 04/26/2010 LCD Backlight Support K17_MLB TABLE_TABLEOFCONTENTS_ITEM ALIASES RESOLVED A SCHEM,BLACK_PEARL,MLB,K92 (.csa) Page REV pre-evt 11/22/10 D A DRAWING TITLE SCHEM,MLB,K92 DRAWING NUMBER Schematic / PCB #’s PART NUMBER QTY Apple Inc DESCRIPTION REFERENCE DES CRITICAL 051-8618 SCHEM,BLACK_PEARL,MLB,K92 SCH CRITICAL 820-2914 PCBF,BLACK_PEARL,MLB,K92 PCB CRITICAL BOM OPTION R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED DRAWING TITLE=MLB ABBREV=DRAWING LAST_MODIFIED=Tue Nov 23 20:44:38 2010 SIZE D REVISION BRANCH PAGE OF 132 SHEET OF 105 J2500 INTEL CPU U8000 XDP CONN WHISTLBR PG 23 SANDYBRIDGE PG 9-13 PG 74 J2900 UDIMMs DDR3 /1333MHZ DIMM J6900/J6950 D D PG 26,28 DC/BATT POWER SUPPLY PG 63 GPIO PG 19 FDI DMI RTC PG 17 PG 17 PG 16 U4900 TEMP SENSOR CLOCK CK505 U2700 Misc PG 52 CLK PG 19 U6100 BUFFER P8 24 PG 16 J4500 SATA Conn HD SPI J4501 SATA 3.0/ 6GHZ PG 53 INTEL SATA U4900 ADC B,0 BSB COUGAR POINT SMC LPC PG 16 SATA 2.0 /3GHZ C FAN CONN AND CONTROL PG 58 SATA PG 84 J5650,5660 PG 16 P8 41 CBTL06141EE U9320 POWER PGSENSE 51 SPI Boot ROM Fan Ser Prt J5100 PG 54 LPC Conn Port80,serial C PG 47 Conn ODD PG 16 U1800 P8 41 PWR J9400 CTRL DP OUT DISPLAY PORT CONN U3600 PG 17 RGB OUT USBDN4 PG 85 HDMI OUT U9600 GMUX XP25-5 LVDS OUT PG 87 USB PG 18 PG 18 TMDS OUT PCI PG 18 J9000 LVDS CONN B (UP TO 14 DEVICES) DVI OUT 10 11 12 13 USX2061 USBDN3 USBDN2 PG 73 USBDN1 J5713/J5800 J3401 Bluetooth PG 31 EXTA J3500 TRACKPAD/ KEYBOARD J4600,J4610,4720 EXTERNAL USB EXPRESSCARD PG 53/54 PG 32 PG 41 EXTC EXTB U3600 USBDN4 JTAG B USX2061 USBDN3 SMB PG 83 PG 16 PG 16 PEG PERN2 PG 16 IHDA PCI-E PERN3 PERN1 PERN4 USBDN2 PG 73 SMB CONN PG 16 DIMM’s USBDN1 PG 48 EXPRESSCARD PG 16 J3402 J4800 CAMERA PG 31 IR PG 44 U6200 AudioCodec CS4206ACNZC PG 57 LINE IN U6500 U4100 U3900 A U6610,6620,6630,6640,6650 J3500 GB E-NET FW643 BCM57765 EXPRESSCARD CONN HEADPHONE Amp Speaker Amps PG 38 SYNC_MASTER=K60_MLB SYNC_DATE=04/26/2010 PAGE TITLE System Block Diagram PG 60 PG 36 PG 32 DRAWING NUMBER LINE OUT J3401 J4310 Mini PCI-E AIRPORT Apple Inc J4000 FW-800 Conn E-NET Conn PG 40 PG 37 R J6780,6781,6782,6700,6750 Audio Conns PG 31 NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED PG 61 SIZE D REVISION BRANCH PAGE OF 132 SHEET OF 105 A K92 POWER SYSTEM ARCHITECTURE PPDCIN_G3H_OR_PBUS_R D6990 SMC PWRGD NCP303LSN U5000 (PAGE 46) R6990 SMC_RESET_L ENABLE SMC AVREF SUPPLY 3.425V G3HOT J6900 V F7040 D PP3V42_G3H SMC_TPAD_RST_L U7000 VIN PPVBAT_G3H_CHGR_REG PP5V_S3_GFXIMVP6_VDD VDD F7041 8A FUSE ISL6259HRTZ PBUS SUPPLY/ BATTERY CHARGER VOUT VR_ON VIN PP1V0_FW TPS22924 VOUT (PAGE 70) FW_PWR_EN EN V A A CHGR_BGATE PPCPUVCCIO_S3 PGOOD EN PGOOD CPU VCORE VOUT VIN ISL95831 CPUIMVP7_VR_ON U7400 VR_ON SMC_CPU_HI_ISENSE SMC_CPU_FSB_ISENSE CPUVTTS0_PGOOD CPUVTTS0_EN R5388 PPVBAT_G3H_CHGR_R PPCPUVTT_S0 ISL95870 U7600 (PAGE 82) Q7055 A VOUT 1.05V GPUVCORE_PGOOD (PAGE 64) PPVBATT_G3H_CONN PP5V_S0_CPUVTTS0 VIN SMC_GPU_ISENSE GPUVCORE_EN SMC_BATT_ISENSE J6950 PPVCORE_GPU U5410 ISL6263C U8900 U5001 R7640 SMC_GPU_VSENSE GPU VCORE A R7050 V A VIN VOUT SMC_DCIN_ISENSE PPVCORE_S0_CPU COUGAR_POINT PM_PWRBTN_L PWRBTN# SMC_CPU_ISENSE SYS_RERST# RSMRST# CPUIMVP7_PGOOD PGOOD ACPRESENT PM_PCH_PWRGD PLT_RERST_L PS_PWRGD PLTRST# PP5V_S3 U1800 GMUX U9600 XP25-5 EG_RAIL1_EN PB17A EG_RAIL2_EN P3V3GPU_EN PB17B EG_RAIL3_EN GPUVCORE_EN PB18A EG_RAIL4_EN R7350/U5440 PM_ALL_GPU_PGOOD P1V0GPU_EN EN1 PP1V0_S0GPU VIN VOUT1 P1V5FB_EN SMC P3V3S5_EN A VOUT2 EN2 1.8V(R/H) ISL6236 U9500 (PAGE 86) U4900 P1V0GPU_PGOOD POK2 P1V5FB_PGOOD VIN P3V3S5_EN Q9806 EN1 5V EN2 3.3V VREG5 TPS51916 DDRREG_PGOOD U7300 PGOOD (PAGE 67) BKLT_PLT_RST_L && LCD_BKLT_EN DDRREG_EN DELAY U1800 P3V3S3_EN VIN LP8545SQX U9701 BKLT_EN CPU A ENA VOUT PP1V5_S3RS0 PP3V3_S0 Q7860 VOUT ON SLG5AP020 MAX8840 VOUT EN (PAGE 57) P5VS0_EN PP5V_S3 PP5V_S3 PM_ALL_GPU_PGOOD PP3V3_S5 VIN TPS61045 VOUT2 U5805 (R/H) VOUT U7980 PP18V5_S3 RSMRST_PWRGD P5VS3_PGOOD PPVOUT_S0_LCDBKLT P1V5_S0_EN EN P3V3GPU_EN ISL8009B U7710 OUT PP1V5_S0 Q7922 LTC1872 U7790 IMVP_VR_ON PM_SYSRST_L PP3V3_ENET PP3V3_S0_PWRCTL U4201 PM_PWRBTN_L P17(BTN_OUT) PM_SLP_S5_L P5VS3_PGOOD PM_SLP_S3_L&&WOL_EN||SMC_ADAPTER_EN SLP_S5_L(P95) PM_SLP_S4_L RES* SMC_RESET_L SLP_S4_L(P94) TPS22924 PP3V3_S0_FET VOUT 99ms DLY IMVP_VR_ON(P16) P1V8S0_PGOOD Q7830 VIN PM_RSMRST_L RSMRST_OUT(P15) PWR_BUTTON(P90) SYSRST(PA2) PP3V3_S3 PP10V_FW RSMRST_IN(P13) (PAGE 71) Q7810 Q4260 SLP_S3#(P12) (P64) SMC_ONOFF_L VIN B SMC_ADAPTER_EN PWRGD(P12) PP3V3_S0_GPU P3V3S3_EN (PAGE 16-21) SMC ALL_SYS_PWRGD (PAGE 54) Q7870 P3V3S5_PGOOD PM_SLP_S3_L RESET* (PAGE 9-14) PP4V5_AUDIO_ANALOG U6201 PP5V_S0_FET (PAGE 88) PM_SLP_S4_L SM_DRAMPWROK U1000 VCCCPUPWRGD RD220 VOUT1 TPS51980 U7201 (PAGE 66) PGOOD1 PGOOD2 P5VS3_EN DELAY SLP_S4#(H7) PPVTT_S0_DDR_LDO U7801 (PAGE 54) (L/H) RC PP1V5_S3 VIN PM_SLP_S5_L RC A PPDDR_S3_REG VOUT1 PP5V_S5 P1V5CPU_EN P5VS3_EN B VLDOIN 1.5V S3 0.75V VOUT2 SMC_GPU_1V5_ISENSE POK1 COUGAR_POINT SLP_S5#(E4) S5 PP1V5R1V35_GPU_FB_ISNS DELAY SMC_PM_G2_EN (PAGE 16-21) R5410 1.103V(L/H) RC U2850 SMC_DDR_ISENSE VIN DDRREG_EN (PAGE 87) (PAGE 45) C DRAMPWROK MEMVTT_EN P60 CPU_PWRGD PROCPWRGD PM_MEM_PWRGD PB16B PL32A U4202 (PAGE 39) SMC_CPU_VSENSE (PAGE 68) C D SMC_ONOFF_L A DCIN(16.5V) IN 2S4P REF3333VOUT (PAGE 46) R7020 ADAPTER (6 TO 8.4V) VIN PPBUS_G3H F6905 6A FUSE AC Q5315 PP3V3_S5_AVREF_SMC PP3V42_G3H PM6640 U6990 (PAGE 63) SMC_PBUS_VSENSE S0PGOOD_PWROK PP3V3_FW_FWPHY PM_SLP_S3_L SLP_S3_L(P93) H8S2117 U4900 (PAGE 45) (PAGE 39) (PAGE 71) PP3V3_S0 P3V3S0_EN FW_PWR_EN SMC_ADAPTER_EN&&PM_SLP_S3_L VCC R7978 PP3V3_S0_VMON VIN PM_SLP_S3_L_R P1V8_S0_EN EN ISL8014 VOUT U7720 PGOOD PP1V8_S0 PP1V5_S0_VMON P1V8S0_PGOOD PP1V05_S0_VMON (PAGE 70) A RC DELAY RC DELAY P1V8S0_EN PP3V3_FW_FET PP1V2_S0 P5VS0_EN V3MON RST* PG V4MON(PAGE 73) TRST = 200mS P1V2ENET_PGOOD SYNC_MASTER=K17_MLB P1V2S0_EN P3V3S0_EN RC DELAY CPUVTTS0_EN RC DELAY P1V5CPU_EN SYNC_DATE=04/26/2010 PAGE TITLE Revision History P1V2ENET_EN EN Q7850 U7971 V2MONISL88042IRTJJZ ISL8014A DRAWING NUMBER P1V2GMUX_EN VIN U7760 VOUT PP1V2_ENET Apple Inc R (PAGE 71) PBUSVSENS_EN NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED SIZE D REVISION BRANCH PAGE OF 132 SHEET OF 105 A PROTO2/EVT 11/11/10 PROTO2/EVT 11/15/10 PROTO2/EVT 11/19/10 EVT 11/22/10 rev3.9 rev3.0 for board 820-2914-05.brd release rev3.6 for board 820-2914-06.brd release rev3.7 for board 820-2914-07.brd release for board 820-2914-07.brd release D D C C B B A SYNC_MASTER=K17_MLB SYNC_DATE=04/26/2010 PAGE TITLE Revision History DRAWING NUMBER Apple Inc R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED SIZE D REVISION BRANCH PAGE OF 132 SHEET OF 105 A Alternate Parts TABLE_ALT_HEAD BOM Variants PART NUMBER ALTERNATE FOR PART NUMBER 157S0058 BOM OPTION REF DES COMMENTS: 157S0055 ALL Delta alt to TDK Magnetics 152S0896 152S0518 ALL MAG LAYERS ALT TO CYNTEC 152S0915 152S0796 ALL MAG LAYERS ALT TO CYNTEC 155S0457 155S0329 ALL MAG LAYERS ALT TO MURATA 516S0805 516S0806 ALL FOXCONN ALT TO MOLEX 353S2805 353S2603 ALL Fairchild 8’ alt to 6’wafer 127S0111 127S0060 ALL Rohm alt to Kemet 353S3085 353S1658 ALL ST Micro alt to LT 152S0905 152S1307 ALL Cyntec (used on K90i) as alt 353S3055 353S3151 ALL Pericom alt to NXP DP Mux TABLE_ALT_ITEM TABLE_BOMGROUP_HEAD BOM NUMBER BOM NAME BOM OPTIONS 639-1303 PCBA,MLB,K92 K92_COMMON,CPU:2_2GHZ,FB_1G_SAMSUNG,EEEE_DG5Y 639-1464 PCBA,MLB,CFG2,K92 K92_COMMON,CPU:2_2GHZ,FB_1G_HYNIX,VRAM_HYNIX,EEEE_DG60 639-1466 PCBA,MLB,CFG3,K92 K92_COMMON,CPU:2_3GHZ,FB_1G_SAMSUNG,EEEE_DG62 639-1465 PCBA,MLB,CFG4,K92 K92_COMMON,CPU:2_3GHZ,FB_1G_HYNIX,VRAM_HYNIX,EEEE_DG61 TABLE_ALT_ITEM TABLE_BOMGROUP_ITEM TABLE_ALT_ITEM TABLE_BOMGROUP_ITEM TABLE_ALT_ITEM TABLE_BOMGROUP_ITEM TABLE_ALT_ITEM TABLE_BOMGROUP_ITEM TABLE_ALT_ITEM TABLE_BOMGROUP_ITEM D 085-1898 K92 MLB DEVELOPMENT BOM K92_DEVEL:ENG D TABLE_ALT_ITEM TABLE_ALT_ITEM K92 BOM GROUPS (U5850) TABLE_ALT_ITEM TABLE_BOMGROUP_HEAD BOM GROUP TABLE_BOMGROUP_ITEM K92_COMMON ALTERNATE,COMMON,K92_COMMON1,K92_COMMON2,K92_PROGPARTS K92_COMMON1 CPUMEM_S0,EXT_HP_AMP,SMC_DEBUG_YES,USBHUB_2514B 376S0855 376S0613 ALL radar8515240 Toshiba FET 870-1939 870-1698 ALL Silver alt to Gold tall pogo pins GPUVID_1P11V,HUB1_2NONREM,HUB2_2NONREM,KB_BL,ENET:B0,T29BST:Y,T29:YES,T29_DP_HPD:ALL_OR SNB_CPT_XDP,DEBUG_ADC,LPCPLUS:YES,VREFMRGN,GMUX_JTAG_CONN,S0PGOOD_ISL,BMON:ENG,CPURIPPLE_ENG,IMVPISNS_ENG,SDRVI2C:MCU TABLE_ALT_ITEM 870-2015 870-1699 ALL Silver alt to Gold short pogo pins 376S0972 376S0612 ALL add ROHM part as 2nd source 138S0676 138S0691 ALL add Murata part as 2nd source 128S0327 128S0264 ALL add NEC part as 2nd source 376S0977 376S0859 ALL add new part as 2nd source 138S0681 138S0638 ALL add new part as 2nd source TABLE_BOMGROUP_ITEM TABLE_ALT_ITEM TABLE_BOMGROUP_ITEM K92_DEVEL:PVT TABLE_ALT_ITEM SNB_CPT_XDP,LPCPLUS:YES,VREFMRGN_NOT TABLE_BOMGROUP_ITEM K92_PROGPARTS TABLE_ALT_ITEM SMC_PROG:EVT,BOOTROM_PROG:EVT,ENETROM_PROG:B0_NOSD,TPAD_PROG:EVT,T29ROM:PROG,GMUX_PROG,T29MCU:PROG TABLE_BOMGROUP_ITEM K92_PVT VREFMRGN_NOT,XDP,XDP_CPU_BPM,BMON:PROD SNB_CPT_XDP XDP,XDP_CONN,XDP_CPU_BPM,XDP_PCH (Q3200, etc) TABLE_ALT_ITEM TABLE_BOMGROUP_ITEM K92_COMMON2 (U9390) TABLE_ALT_ITEM TABLE_BOMGROUP_ITEM K92_DEVEL:ENG (L7630) TABLE_ALT_ITEM BOM OPTIONS TABLE_ALT_ITEM TABLE_BOMGROUP_ITEM TABLE_ALT_ITEM (Q3888,Q9430) Bar Code Labels / EEEE #’s PART NUMBER C DESCRIPTION REFERENCE DES 826-4393 QTY LBL,P/N LABEL,PCB,28MM X MM [EEEE_DG5Y] CRITICAL CRITICAL BOM OPTION EEEE_DG5Y 826-4393 LBL,P/N LABEL,PCB,28MM X MM [EEEE_DG60] CRITICAL EEEE_DG60 826-4393 LBL,P/N LABEL,PCB,28MM X MM [EEEE_DG61] CRITICAL EEEE_DG61 338S0895 IC,SMC,HS8/2117,9MMX9MM,TLP 826-4393 LBL,P/N LABEL,PCB,28MM X MM [EEEE_DG62] CRITICAL EEEE_DG62 341S2855 IC,SMC,DEVELOPMENT-PROTO,K92 341S2855 IC,SMC,DEVELOPMENT-PROTO1,K92 341S2995 IC,SMC,DEVELOPMENT-PROTO2,K92 341S2862 IC,SMC,DEVELOPMENT-EVT,K92 341S2865 IC,SMC,DEVELOPMENT-DVT,K92 341S2868 IC,SMC,DEVELOPMENT-PVT,K92 SMC PART NUMBER Module Parts PART NUMBER B QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION QTY DESCRIPTION 337S4032 IC,CPU,SNB,SR00W,PRQ,D2,2.2,45W,4+2,1.30,6M,BGA 337S4033 IC,CPU,SNB,SR00U,PRQ.D2,2.3,45W,4+2,1.30,8M,BGA 337S4029 IC,PCH,COUGARPOINT SLH9D,PRQ,BD82HM63 343S0534 IC,ASIC,GBIT ETHNET&SD CTRLR,686 QFN 8X8 343S0494 IC,ASIC,GBIT ETHNET&SD CTRLR,686 QFN 8X8 338S0753 IC,FW643-E,1394B PHY/OHCI LINK/PCI-E,12 U1000 U1000 U1800 U3900 U3900 U4100 333S0543 IC,SGRAM,GDDR5,32MX32.1.25GHz,E-DIE,HF U8400,U8450,U8500,U8550 CRITICAL FB_512_SAMSUNG 335S0740 64 MBIT SPI SERIAL DUAL I/O FLASH 333S0564 IC,SDRAM,GDDR5,32MX32,1.25GHz,A-DIE1.35V U8400,U8450,U8500,U8550 CRITICAL FB_512_HYNIX 341S2893 IC,EFI,ROM,PROTO, K90/K90I/K91/K91F/K92 333S0571 IC,SGRAM,GDDR5,64MX32,3.6GBPS,C-DIE,HF U8400,U8450,U8500,U8550 CRITICAL FB_1G_SAMSUNG 341S2934 IC,EFI,ROM,PROTO1, K90/K90I/K91/K91F/K92 333S0572 IC,SGRAM,GDDR5,64MX32,3.6GBPS,M-DIE,HF U8400,U8450,U8500,U8550 CRITICAL FB_1G_HYNIX 341S2991 IC,EFI,ROM,PROTO1, K90/K90I/K91/K91F/K92 337S3936 IC,GPU,AMD,WHISTLER,962FCBGA,40NM,ES 341S2894 IC,EFI,ROM,EVT, K90/K90I/K91/K91F/K92 338S0945 Light Ridge,S LHAJ,FCBGA,15x15mmm 341S2895 IC,EFI,ROM,DVT, K90/K90I/K91/K91F/K92 353S3055 IC, P13VEDP212,x2 DISPLAYPORT 2:1 MUX, QFN 341S2896 IC,EFI,ROM,PVT, K90/K90I/K91/K91F/K92 U8000 U3600 U9390 CRITICAL CPU:2_2GHZ CRITICAL CPU:2_3GHZ 335S0777 QTY DESCRIPTION 341S2899 IC,T29 EEPROM,K92 341S2384 IR,ENCORE II, CY7C63833-LFXC 335S0724 IC,GPU ROM,K91/F,K92 341S2957 IC,GPU ROM,K91/F,K92 336S0042 IC,PLD,LATTICE,LFXP2-5E-5,132 BALL CSBGA 341S2996 IC,GMUX,K92 337S3997 IC,MCU,32B,LPC1112A,16KB/2KB,HVQFN25 341S2939 IC,PROGRAMMED MCU,32B,LPC1112A,16KB/2KB,HVQFN25 CRITICAL BOM OPTION CRITICAL SMC_BLANK CRITICAL SMC_PROG:PROTO0 CRITICAL SMC_PROG:PROTO1 CRITICAL SMC_PROG:PROTO2 CRITICAL SMC_PROG:EVT CRITICAL SMC_PROG:DVT CRITICAL SMC_PROG:PVT C CRITICAL ENET:B0 CRITICAL ENET:A0 EFI PART NUMBER CRITICAL CRITICAL CRITICAL T29:YES CRITICAL QTY DESCRIPTION REFERENCE DES U6100 U6100 U6100 U6100 U6100 U6100 U6100 CRITICAL BOM OPTION CRITICAL BOOTROM_BLANK CRITICAL BOOTROM_PROG:PROTO0 CRITICAL BOOTROM_PROG:PROTO1 CRITICAL BOOTROM_PROG:PROTO2 CRITICAL BOOTROM_PROG:EVT CRITICAL BOOTROM_PROG:DVT CRITICAL BOOTROM_PROG:PVT B Ethernet PART NUMBER REFERENCE DES IC,EEPROM,SERIAL,8KB,SOIC U4900 U4900 U4900 U4900 U4900 U4900 U4900 CRITICAL Programmed Parts-All Builds PART NUMBER REFERENCE DES U3690 U3690 U4800 U8701 U8701 U9600 U9600 U9330 U9330 CRITICAL CRITICAL CRITICAL BOM OPTION T29ROM:BLANK T29ROM:PROG QTY DESCRIPTION 335S0539 IC,FLASH,SERIAL,SPI,1MBIT,2V7,8P,SOIC 341S2685 IC,ENET ROM,PROTO1,K92 341S3027 IC,ENET ROM, PROTO2, EVT,DVT,PVT,K92 REFERENCE DES U3990 U3990 U3990 CRITICAL BOM OPTION CRITICAL ENETROM_BLANK CRITICAL ENETROM_PROG:A0_SD CRITICAL ENETROM_PROG:B0_NOSD CRITICAL GPUROM will NOSUFFED @EVT CRITICAL GPUROM:BLANK CRITICAL GPUROM:PROG CRITICAL GMUX_BLANK CRITICAL GMUX_PROG 341S2902 IC,TP PSOC,PROTO,K90,K90i,K91,K91F,K92 CRITICAL T29MCU:BLANK 341S3024 IC,TP PSOC,proto2,K90,K90i,K91,K91F,K92T CRITICAL T29MCU:PROG 341S3024 IC,TP PSOC,proto1,EVT,K90,K90i,K91,K91F,K92T 341S3024 IC,TP PSOC,proto1,DVT,pVT,K90,K90i,K91,K91F,K92T PSOC PART NUMBER QTY DESCRIPTION A REFERENCE DES U5701 U5701 U5701 U5701 CRITICAL BOM OPTION CRITICAL TPAD_PROG:PROTO1 CRITICAL TPAD_PROG:PROTO2 CRITICAL TPAD_PROG:EVT CRITICAL TPAD_PROG:DVTPVT SYNC_MASTER=K17_MLB SYNC_DATE=04/26/2010 PAGE TITLE BOM Configuration DRAWING NUMBER Apple Inc R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED SIZE D REVISION BRANCH PAGE OF 132 SHEET OF 105 A J5650 (LEFT FAN CONN) FAN_LT_PWM FAN_LT_TACH TRUE PP5V_S0 TRUE TRUE I1488 J5660 (RIGHT FAN CONN) FAN_RT_PWM TRUE FAN_RT_TACH TRUE PP5V_S0 GND TRUE FUNC_TEST I1561 TRUE 52 I1051 TRUE 52 I1050 TRUE 47 22 41 52 54 65 68 69 70 73 87 104 105 GND TRUE TPs I1053 TPs 52 I557 I558 I559 TRUE I1054 TRUE I1056 TRUE 54 65 68 69 70 73 87 104 105 I1058 47 I1057 22 41 52 TPs J6780 (MIC FR CONN) AUD_DMIC_CLK_FR TRUE AUD_DMIC_SDA_FR TRUE AUD_DMIC_PWR_FR TRUE GND TRUE TPs I1490 I1491 I1492 TRUE I985 I987 TRUE I986 TRUE I988 TRUE TRUE TRUE TRUE WIFI_EVENT_L PCIE_AP_R2D_P PCIE_AP_R2D_N PCIE_AP_D2R_P PCIE_AP_D2R_N PCIE_CLK100M_AP_CONN_P PCIE_CLK100M_AP_CONN_N AP_CLKREQ_Q_L PCIE_WAKE_L AP_RESET_CONN_L I1103 31 45 46 I1102 31 95 I1104 31 95 I1105 16 31 95 I1107 16 31 95 I1106 31 100 I1108 31 100 I1109 31 I1110 17 25 31 32 85 I1111 31 I1112 I1059 TRUE PP3V3_WLAN I1061 TRUE I1060 TRUE I1063 TRUE I1066 TRUE PP3V3_S3_BT_F SMBUS_SMC_0_S0_SDA SMBUS_SMC_0_S0_SCL USB_BT_P USB_BT_N I1065 J6783 (MIC BK CONN) AUD_DMIC_CLK_BK TRUE AUD_DMIC_SDA_BK TRUE AUD_DMIC_PWR_BK TRUE GND TRUE TRUE I1052 I1055 TPs D J3401(AIRPORT/BT CONN) Functional Test Points TRUE TRUE 31 46 TP needed I1113 I1114 31 I1115 31 45 48 51 80 98 I1117 31 45 48 51 80 98 I1116 24 31 94 24 31 94 GND TP needed 61 61 61 TPs I1062 I1064 J6781 (LEFT SPEAKER) SPKRAMP_FL_OUT_P SPKRAMP_FL_OUT_N SPKRAMP_BL_OUT_P SPKRAMP_BL_OUT_N I1451 60 61 I1479 60 61 I1478 60 61 J3402 (CAMERA/ALS CONN) USB_CAMERA_CONN_P TRUE USB_CAMERA_CONN_N TRUE PP5V_S3_ALSCAMERA_F TRUE SMBUS_SMC_A_S3_SDA TRUE SMBUS_SMC_A_S3_SCL TRUE GND TRUE 31 94 31 94 31 31 45 48 54 55 98 31 45 48 54 55 98 TP needed 60 61 J6782 (RIGHT & SUB SPEAKER) TRUE I989 I990 TRUE I992 TRUE I991 TRUE I994 TRUE I993 TRUE J3500 (EXPRESS CARD CONN) SPKRAMP_LFE_OUT_P SPKRAMP_LFE_OUT_N SPKRAMP_FR_OUT_P SPKRAMP_FR_OUT_N SPKRAMP_BR_OUT_P SPKRAMP_BR_OUT_N I1067 TRUE I1068 TRUE 60 61 I1069 TRUE 60 61 I1071 TRUE I1070 TRUE I1072 TRUE I1074 TRUE I1073 TRUE I1075 TRUE 60 61 60 61 J9000 (LVDS CONN) C I995 TRUE I996 TRUE I997 TRUE I998 TRUE I1000 TRUE I1001 TRUE I1002 TRUE I1004 TRUE I1003 TRUE I1005 I1007 TRUE I1006 TRUE I1009 TRUE I1008 TRUE I1010 TRUE I1011 TRUE I1012 B TRUE TRUE I1014 TRUE I1013 TRUE I1015 TRUE I1016 TRUE I1017 TRUE I1018 TRUE I1019 TRUE I1020 TRUE I1022 TRUE I1021 TRUE TRUE I1024 TRUE I1026 TRUE I1025 TRUE I1028 TRUE I1027 TRUE I1029 TRUE TRUE PP3V3_SW_LCD PP3V3_S0 PPVOUT_S0_LCDBKLT LVDS_DDC_CLK LVDS_DDC_DATA LVDS_CONN_A_DATA_P LVDS_CONN_A_DATA_N LVDS_CONN_A_DATA_P LVDS_CONN_A_DATA_N LVDS_CONN_A_DATA_P LVDS_CONN_A_DATA_N LVDS_CONN_A_CLK_F_P LVDS_CONN_A_CLK_F_N LVDS_CONN_B_DATA_P LVDS_CONN_B_DATA_N LVDS_CONN_B_DATA_P LVDS_CONN_B_DATA_N LVDS_CONN_B_DATA_P LVDS_CONN_B_DATA_N LVDS_CONN_B_CLK_F_P LVDS_CONN_B_CLK_F_N LED_RETURN_1 LED_RETURN_2 LED_RETURN_3 LED_RETURN_4 LED_RETURN_5 LED_RETURN_6 GND J4500 (SATA ODD CONN) PP5V_SW_ODD SMC_ODD_DETECT SATA_ODD_D2R_UF_P SATA_ODD_D2R_UF_N SATA_ODD_R2D_P SATA_ODD_R2D_N GND 83 84 85 54 57 61 46 48 49 32 35 36 12 23 25 26 28 39 40 41 50 51 52 62 72 73 80 88 89 91 100 102 TPs TPs TPs 83 84 83 84 99 I1076 TRUE I1077 TRUE I1079 TRUE I1078 TRUE 83 84 99 I1081 TRUE 83 84 99 I1080 TRUE 83 84 99 I1082 TRUE 83 84 99 I1083 83 84 99 I1084 I1031 TRUE I1033 TRUE I1472 TRUE I1473 TRUE I1474 TRUE I1475 TRUE I1476 TRUE TRUE PP5V_S0_HDD_FLT SATA_HDD_R2D_P SATA_HDD_R2D_N SATA_HDD_D2R_C_P SATA_HDD_D2R_C_N PP5V_S3_IR_R IR_RX_OUT SYS_LED_ANODE_R GND 53 53 53 53 53 53 53 53 53 53 53 53 53 53 53 53 53 53 53 53 53 53 53 53 53 53 TRUE TRUE PP1V5_S0_EXCARD_SWITCH 32 PCIE_WAKE_L 17 25 31 32 85 SMBUS_PCH_CLK 16 23 26 28 30 32 95 SMBUS_PCH_DATA 16 23 26 28 30 32 48 62 89 95 PP3V3_S0_EXCARD_SWITCH 32 PP3V3_S3_EXCARD_SWITCH 32 USB2_EXCARD_CONN_N 32 100 USB2_EXCARD_CONN_P 32 100 EXCARD_CPUSB_L 32 EXCARD_CLKREQ_CONN_L 32 EXCARD_CPPE_L 32 PLT_RESET_SWITCH_L 32 PCIE_EXCARD_D2R_P 16 32 100 PCIE_EXCARD_D2R_N 16 32 100 PCIE_EXCARD_R2D_P 32 100 PCIE_EXCARD_R2D_N 32 100 PCIE_CLK100M_EXCARD_CONN_P 32 100 PCIE_CLK100M_EXCARD_CONN_N 32 100 TP needed POWER RAILS FUNC_TEST 41 48 62 89 TRUE 41 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE PM_SLP_S3_L PPBUS_G3H PP3V42_G3H PP5V_S3 PP5V_S0 PPVCORE_S0_CPU PP3V3_S5 PP3V3_S3 PP3V3_S0 TRUE PP1V2_S0 TRUE PP1V8_S0 TRUE PPVTTDDR_S3 TRUE PPVP_FW 17 29 45 73 35 39 49 50 63 64 90 104 25 42 44 45 46 47 48 53 63 64 73 87 104 105 22 41 47 52 54 65 68 69 70 73 12 14 49 69 105 TPs 54 55 18 24 25 29 30 31 32 48 49 50 73 88 104 32 35 36 12 23 25 26 28 39 40 41 46 48 49 50 51 52 54 61 62 72 73 88 57 80 83 84 85 88 89 91 100 102 71 14 20 25 71 72 88 102 83 99 83 84 99 I1085 TRUE 83 84 99 I1086 TRUE 83 84 99 I1087 TRUE 83 84 99 I1273 TRUE 83 84 99 I1089 TRUE 83 84 99 I1088 TRUE I1090 TRUE 83 99 83 99 I1091 TRUE 83 89 I1098 TRUE 83 89 I1097 TRUE 83 89 I1095 TRUE 83 89 I1484 TRUE 83 89 I1485 TRUE 83 89 TPs I1096 TRUE I1092 TRUE I1093 TPs TRUE I1094 TRUE I1099 TRUE I1100 TRUE 41 104 41 45 41 94 I1101 TRUE 41 94 TRUE PP3V3_S3 PP18V5_S4 PP3V3_S4 Z2_CS_L Z2_DEBUG3 Z2_MISO Z2_BOOST_EN Z2_MOSI Z2_CLKIN Z2_KEY_ACT_L Z2_RESET Z2_HOST_INTN Z2_SCLK PSOC_F_CS_L PICKB_L PSOC_MISO PSOC_MOSI PSOC_SCLK SMBUS_SMC_A_S3_SCL SMBUS_SMC_A_S3_SDA GND TRUE 18 24 25 29 30 31 32 48 49 50 54 55 73 88 104 54 PP3V3_S0GPU 72 75 79 80 82 84 TRUE TRUE PP3V3_S5_AVREF_SMC 45 46 TRUE PP18V5_S4 54 TRUE PPDCIN_G3H 49 63 64 TRUE 53 54 53 54 53 54 54 75 79 81 103 49 75 82 72 103 53 54 53 54 FUNC_TEST SYS_LED_ANODE_R TRUE LPC_CLK33M_LPCPLUS TRUE 53 54 53 54 53 54 TRUE 53 54 LPC_AD 53 54 TRUE SPI_ALT_MOSI 53 54 TRUE 25 47 95 16 45 47 88 95 47 53 54 TRUE 53 54 TRUE SMC_TMS 45 46 47 31 45 48 54 55 98 TRUE LPCPLUS_RESET_L 25 47 88 95 TRUE 31 45 48 54 55 98 TPS 47 16 45 47 88 95 17 45 47 TRUE SMC_TDO 45 46 47 TRUE SMC_TRST_L 45 47 TRUE SMC_MD1 45 47 41 94 41 94 TPs I1134 41 TPs I1135 41 94 I1137 41 94 J6950 (MAIN BATT CONN) PPVBAT_G3H_CONN TRUE SMBUS_SMC_BSA_SCL TRUE SMBUS_SMC_BSA_SDA TRUE SYS_DETECT_L TRUE GND TRUE 63 64 TPs TRUE SMC_TX_L TRUE SPIROM_USE_MLB 19 47 56 TRUE SPI_ALT_CLK 47 TRUE SPI_ALT_CS_L 47 TRUE LPC_SERIRQ 16 45 47 TRUE LPC_PWRDWN_L 17 45 47 TRUE SMC_TDI 45 46 47 TRUE SMC_TCK 63 TPs 41 94 41 94 44 I1148 44 I1150 44 I1149 I1151 J4800 (FRONT CABLE CONN) PP3V42_G3H_LIDSWITCH_R PP5V_S3_IR_R TRUE SMC_LID_R TRUE IR_RX_OUT TRUE SYS_LED_ANODE TRUE GND TRUE TRUE 42 45 46 47 45 48 63 64 98 45 48 63 64 98 45 46 47 45 47 TRUE SMC_RESET_L SMC_NMI SMC_RX_L TRUE LPCPLUS_GPIO 19 47 TRUE 45 46 53 TRUE 44 TRUE 44 45 46 47 64 44 I1599 I1600 97 I1601 97 I1602 SATA_HDD_R2D_UF_N SATA_HDD_R2D_UF_P SATA_HDD_R2D_RC_UF_N SATA_HDD_R2D_RC_UF_P SATA_HDD_R2D_RDRVR_OUT_N I1541 79 I1542 79 80 I1543 12 I1544 12 I1545 I1546 51 I1547 17 92 I1549 17 92 I1550 17 17 NC_CRT_IG_BLUE NC_CRT_IG_GREEN NC_CRT_IG_RED 17 17 NC_CRT_IG_DDC_CLK NC_CRT_IG_DDC_DATA 17 18 18 18 16 16 17 92 16 17 NC_CRT_IG_BLUE NC_CRT_IG_GREEN NC_CRT_IG_RED TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE 17 17 6 17 17 17 NC_CRT_IG_DDC_CLK TRUE MAKE_BASE=TRUE NC_CRT_IG_DDC_DATA TRUE MAKE_BASE=TRUE 17 17 NC_LVDS_IG_CTRL_CLK NC_LVDS_IG_CTRL_DATA NC_PCH_LVDS_VBG NC_LVDS_IG_CTRL_CLK TRUE MAKE_BASE=TRUE NC_LVDS_IG_CTRL_DATA TRUE MAKE_BASE=TRUE NC_PCH_LVDS_VBG TRUE MAKE_BASE=TRUE NC_CRT_IG_HSYNC NC_CRT_IG_VSYNC 17 6 17 17 6 18 18 17 6 18 17 17 NC_HDA_SDIN1 NC_HDA_SDIN2 NC_HDA_SDIN3 TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE 17 16 17 17 6 16 17 NO_TEST 6 18 18 85 85 97 17 NC_PCI_AD NC_PCI_C_BE_L NC_PCI_GNT3_L NC_PCI_GNT2_L NC_PCI_GNT1_L NC_PCI_GNT0_L NC_PCI_PAR NC_PCI_RESET_L NC_PCI_PME_L NC_PCI_CLK33M_OUT3 TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TP_NV_DQ TP_NV_DQS TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE NC_NV_DQ NC_NV_DQS TP_NV_CE_L TRUE MAKE_BASE=TRUE NC_NV_CE_L NC_NV_ALE NC_NV_CLE NC_NV_RB_L TP_NV_WR_RE_L TP_NV_WE_CK_L TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE NC_NV_ALE NC_NV_CLE NC_NV_RB_L NC_NV_WR_RE_L NC_NV_WE_CK_L 85 97 85 97 85 85 85 85 6 41 94 6 41 94 16 41 94 16 41 94 19 41 94 19 41 94 41 94 41 94 19 19 53 16 41 94 16 41 94 6 41 94 6 41 94 16 41 94 16 16 41 94 16 41 94 16 SATA_HDD_D2R_RDRVR_OUT_P 41 94 SATA_HDD_D2R_RDRVR_IN_N 41 94 SATA_HDD_D2R_RDRVR_IN_P 41 94 16 6 6 41 94 6 41 94 NC_PCIE_CLK100M_PE4N NC_PCIE_CLK100M_PE4P NC_PCIE_CLK100M_PE5N NC_PCIE_CLK100M_PE5P NC_PCIE_CLK100M_PE6N NC_PCIE_CLK100M_PE6P NC_PCIE_CLK100M_PE7N NC_PCIE_CLK100M_PE7P NC_PSOC_P1_3 NC_SATA_C_D2RN NC_SATA_C_D2RP NC_SATA_C_R2D_CN NC_SATA_C_R2D_CP NC_SATA_D_D2RN NC_SATA_D_D2RP NC_SATA_D_R2D_CN NC_SATA_D_R2D_CP NC_SATA_SSD2_D2RN NC_SATA_SSD2_D2RP NC_SATA_SSD2_R2D_CN NC_SATA_SSD2_R2D_CP TRUE 54 TRUE PM_SYSRST_L 17 25 45 I1146 54 TRUE LCD_BKLT_PWM 88 89 44 46 TRUE NC_BCM57765_SPD100LED_L NC_BCM57765_TRAFFICLED_L NC_BCM57765_SPD100LED_L NC_CE_L_MS_INS_L 38 40 TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE NC_SDVO_TVCLKINN NC_SDVO_TVCLKINP NC_SDVO_STALLN NC_SDVO_STALLP TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE NC_SDVO_STALLN NC_SDVO_STALLP NC_SDVO_INTN NC_SDVO_INTP TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE NC_SDVO_INTN NC_SDVO_INTP NC_GPU_BUFRST_L NC_GPU_GSTATE TP_GPU_GSTATE TP_GPU_MIOA_D NC_GPU_MIOA_DE 6 6 6 6 18 6 18 NC_LVDS_EG_B_CLKN NC_LVDS_EG_B_CLKP NC_LVDS_EG_BKL_PWM TP_LVDS_IG_B_CLKN TP_LVDS_IG_B_CLKP TP_LVDS_IG_BKL_PWM 18 18 6 6 6 NC_PCH_SST NC_PCH_NC1 NC_PCH_NC2 NC_PCH_NC3 NC_PCH_NC4 NC_PCH_NC5 NC_PCH_TP19 NC_PCH_TP18 NC_PCH_TP17 NC_PCH_TP16 NC_PCH_TP15 NC_PCH_TP14 NC_PCH_TP13 NC_PCH_TP12 NC_PCH_TP11 NC_PCH_TP10 NC_PCH_TP9 NC_PCH_TP8 NC_PCH_TP7 NC_PCH_TP6 NC_PCH_TP5 NC_PCH_TP4 NC_PCH_TP3 NC_PCH_TP2 NC_PCH_TP1 6 6 6 6 16 6 16 6 19 6 19 6 19 6 19 6 53 6 6 6 6 6 16 6 16 6 16 6 16 6 6 TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE 6 I1436 TRUE I1437 TRUE I1438 TRUE I1439 TRUE I1440 TRUE 36 36 I1441 TRUE I1442 TRUE 36 PCH_VSS_NCTF PCH_VSS_NCTF PCH_VSS_NCTF PCH_VSS_NCTF PCH_VSS_NCTF PCH_VSS_NCTF PCH_VSS_NCTF I1443 TRUE I1444 TRUE I1445 TRUE I1446 TRUE I1447 TRUE I1448 TRUE I1449 TRUE I1450 TRUE I1142 I1141 I1143 I1486 I1131 I1132 J6995 (BAT LED CONN) PP3V42_G3H TRUE SMBUS_SMC_BSA_SDA TRUE SMBUS_SMC_BSA_SCL TRUE SMC_BIL_BUTTON_L TRUE SMC_LID_R TRUE GND TRUE J6900 (DC POWER CONN) ADAPTER_SENSE PP18V5_DCIN_FUSE TRUE GND TRUE TRUE 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 NC_LVDS_EG_B_CLKN TRUE MAKE_BASE=TRUE NC_LVDS_EG_B_CLKP TRUE MAKE_BASE=TRUE NC_LVDS_EG_BKL_PWM TRUE MAKE_BASE=TRUE NC_LVDS_IG_B_CLKN TRUE MAKE_BASE=TRUE NC_LVDS_IG_B_CLKP TRUE MAKE_BASE=TRUE NC_LVDS_IG_BKL_PWM TRUE MAKE_BASE=TRUE 6 6 6 6 6 6 6 B 6 6 6 6 6 6 6 6 PCH_VSS_NCTF PCH_VSS_NCTF PCH_VSS_NCTF PCH_VSS_NCTF PCH_VSS_NCTF PCH_VSS_NCTF PCH_VSS_NCTF PCH_VSS_NCTF 6 SYNC_DATE=04/26/2010 PAGE TITLE Functional / ICT Test 25 42 44 45 46 47 48 53 63 64 73 104 DRAWING NUMBER 45 48 63 64 98 45 48 63 64 98 Apple Inc 45 46 63 R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED 63 TPs TPs SIZE D REVISION 44 63 BRANCH PAGE OF 132 SHEET OF 105 C NC_PCH_SST NC_PCH_NC1 NC_PCH_NC2 NC_PCH_NC3 NC_PCH_NC4 NC_PCH_NC5 NC_PCH_TP19 NC_PCH_TP18 NC_PCH_TP17 NC_PCH_TP16 NC_PCH_TP15 NC_PCH_TP14 NC_PCH_TP13 NC_PCH_TP12 NC_PCH_TP11 NC_PCH_TP10 NC_PCH_TP9 NC_PCH_TP8 NC_PCH_TP7 NC_PCH_TP6 NC_PCH_TP5 NC_PCH_TP4 NC_PCH_TP3 NC_PCH_TP2 NC_PCH_TP1 SYNC_MASTER=K17_MLB I1140 has TP 38 17 NC_GPU_BUFRST_L TRUE MAKE_BASE=TRUE NC_GPU_GSTATE TRUE MAKE_BASE=TRUE NC_GPU_GSTATE TRUE MAKE_BASE=TRUE NC_GPU_MIOA_D TRUE MAKE_BASE=TRUE NC_GPU_MIOA_DE TRUE MAKE_BASE=TRUE TRUE NC_CE_L_MS_INS_L MAKE_BASE=TRUE NC_FW643_AVREG NC_FW643_TDI NC_SDVO_TVCLKINN NC_SDVO_TVCLKINP TRUE NC_BCM57765_TRAFFICLED_L MAKE_BASE=TRUE 36 D 38 40 NC_DP_IG_D_HPD TRUE MAKE_BASE=TRUE NC_DP_IG_D_CTRL_CLK TRUE MAKE_BASE=TRUE NC_DP_IG_D_CTRL_DATA TRUE MAKE_BASE=TRUE NC_DP_IG_D_MLP TRUE MAKE_BASE=TRUE NC_DP_IG_D_MLN TRUE MAKE_BASE=TRUE NC_DP_IG_D_AUXP TRUE MAKE_BASE=TRUE NC_DP_IG_D_AUXN TRUE MAKE_BASE=TRUE NC_PCIE_CLK100M_PE4N TRUE MAKE_BASE=TRUE NC_PCIE_CLK100M_PE4P TRUE MAKE_BASE=TRUE NC_PCIE_CLK100M_PE5N TRUE MAKE_BASE=TRUE NC_PCIE_CLK100M_PE5P TRUE MAKE_BASE=TRUE NC_PCIE_CLK100M_PE6N TRUE MAKE_BASE=TRUE NC_PCIE_CLK100M_PE6P TRUE MAKE_BASE=TRUE NC_PCIE_CLK100M_PE7N TRUE MAKE_BASE=TRUE NC_PCIE_CLK100M_PE7P TRUE MAKE_BASE=TRUE NC_PSOC_P1_3 TRUE MAKE_BASE=TRUE NC_SATA_C_D2RN TRUE MAKE_BASE=TRUE NC_SATA_C_D2RP TRUE MAKE_BASE=TRUE NC_SATA_C_R2D_CN TRUE MAKE_BASE=TRUE NC_SATA_C_R2D_CP TRUE MAKE_BASE=TRUE NC_SATA_D_D2RN TRUE MAKE_BASE=TRUE NC_SATA_D_D2RP TRUE MAKE_BASE=TRUE NC_SATA_D_R2D_CN TRUE MAKE_BASE=TRUE NC_SATA_D_R2D_CP TRUE MAKE_BASE=TRUE NC_SATA_SSD2_D2RN TRUE MAKE_BASE=TRUE NC_SATA_SSD2_D2RP TRUE MAKE_BASE=TRUE NC_SATA_SSD2_R2D_CN TRUE MAKE_BASE=TRUE NC_SATA_SSD2_R2D_CP TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE 36 38 40 NC_DP_IG_D_HPD NC_DP_IG_D_CTRL_CLK NC_DP_IG_D_CTRL_DATA TP_DP_IG_D_MLP TP_DP_IG_D_MLN NC_DP_IG_D_AUXP NC_DP_IG_D_AUXN 85 85 97 has TP 38 40 NC_DP_IG_C_HPD TRUE MAKE_BASE=TRUE NC_DP_IG_C_CTRL_CLK TRUE MAKE_BASE=TRUE NC_DP_IG_C_CTRL_DATA TRUE MAKE_BASE=TRUE NC_DP_IG_C_MLP TRUE MAKE_BASE=TRUE NC_DP_IG_C_MLN TRUE MAKE_BASE=TRUE NC_DP_IG_C_AUXP TRUE MAKE_BASE=TRUE NC_DP_IG_C_AUXN TRUE MAKE_BASE=TRUE 18 85 38 40 38 40 NC_DP_IG_C_HPD NC_DP_IG_C_CTRL_CLK NC_DP_IG_C_CTRL_DATA TP_DP_IG_C_MLP TP_DP_IG_C_MLN NC_DP_IG_C_AUXP NC_DP_IG_C_AUXN 16 NC NO_TESTs 38 40 38 40 MAKE_BASE=TRUE 17 17 6 45 46 45 46 MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TP_PCI_AD TP_PCI_C_BE_L NC_PCI_GNT3_L NC_PCI_GNT2_L NC_PCI_GNT1_L NC_PCI_GNT0_L NC_PCI_PAR NC_PCI_RESET_L NC_PCI_PME_L NC_PCI_CLK33M_OUT3 NBC TP_FW643_AVREG NC_FW643_TDI 38 NC_CRT_IG_HSYNC NC_CRT_IG_VSYNC NC_HDA_SDIN1 NC_HDA_SDIN2 NC_HDA_SDIN3 45 46 45 46 17 92 17 17 NC_SMC_FAN_3_TACH NC_SMC_FAN_3_CTL NC_SMC_FAN_2_TACH NC_SMC_FAN_2_CTL NC_FW2_TPBP NC_FW2_TPBN NC_FW2_TPBIAS NC_FW2_TPAP NC_FW2_TPAN NC_FW0_TPBP NC_FW0_TPBN NC_FW0_TPAP 17 92 97 97 NC NO_TESTs 17 92 NO_TEST 17 85 SATA_HDD_R2D_RDRVR_IN_P SATA_HDD_D2R_C_N SATA_HDD_D2R_C_P DMI_S2N_P DMI_S2N_N DMI_N2S_P DMI_N2S_N DMI_N2S_P DMI_N2S_N I1540 79 17 85 SATA_HDD_R2D_RDRVR_IN_N SATA_HDD_D2R_RDRVR_OUT_N TRUE TRUE TRUE TRUE TRUE TRUE NO_TEST TRUE TRUE TRUE TRUE I1539 79 NC NO_TESTs SATA_HDD_R2D_RDRVR_OUT_P SATA_HDD_R2D_C_N SATA_HDD_R2D_C_P SATA_HDD_R2D_UF_N SATA_HDD_R2D_UF_P SATA_HDD_D2R_N SATA_HDD_D2R_P 79 38 36 TRUE A TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TP_DVPCLK TP_DVPCNTL TP_DVPCNTL_M TP_DVPDATA TP_GPU_JTAG_TRST_L TP_DC_TEST_A4 TP_DC_TEST_D1 TP_EDP_TX_P TP_T29_SENSOR_ALERT 42 45 46 47 TRUE J5815 (KBD BACKLIGHT CONN) KBDLED_ANODE SMC_KDBLED_PRESENT_L GND TRUE DP_A_BIAS_N_0 DP_A_BIAS_P_0 DP_A_BIAS_N_2 DP_A_BIAS_P_2 DP_A_BIAS DP_SDRVA_ML_R_N DP_SDRVA_ML_R_P DP_SDRVA_ML_R_N DP_SDRVA_ML_R_P T29_A_BIAS_R2D_N0 T29_A_BIAS_R2D_P0 T29_A_BIAS_R2D_N1 T29_A_BIAS_R2D_P1 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE 44 I1145 I1152 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE I1548 ISSP_SCLK_P1_1 ISSP_SDATA_P1_0 SMC_ONOFF_L TPs T29_D2R_P 33 85 97 T29_D2R_N 33 85 97 T29_D2R_C_P 85 86 97 T29_D2R_C_N 85 86 97 T29_R2D_C_P 33 85 97 T29_R2D_C_N 33 85 97 T29_R2D_P 85 97 T29_R2D_N 85 97 T29DPA_ML_P 85 86 97 T29DPA_ML_N 85 86 97 DP_T29SNK0_AUXCH_C_P 33 79 97 DP_T29SNK0_AUXCH_C_N 33 79 97 DP_T29SNK0_AUXCH_P 33 97 DP_T29SNK0_AUXCH_N 33 97 DP_T29SNK0_ML_C_P 33 79 DP_T29SNK0_ML_C_N 33 79 DP_T29SNK0_ML_P 33 97 DP_T29SNK0_ML_N 33 97 DP_T29SNK1_AUXCH_C_P 33 79 97 DP_T29SNK1_AUXCH_C_N 33 79 97 DP_T29SNK1_AUXCH_P 33 97 DP_T29SNK1_AUXCH_N 33 97 DP_T29SNK1_ML_C_P 33 79 DP_T29SNK1_ML_C_N 33 79 DP_T29SNK1_ML_P 33 97 DP_T29SNK1_ML_N 33 97 TP_DP_T29SRC_AUXCH_CN 33 TP_DP_T29SRC_AUXCH_CP 33 TP_DP_T29SRC_ML_CP 33 TP_DP_T29SRC_ML_CN 33 DP_SDRVA_ML_C_P 85 97 DP_SDRVA_ML_C_N 85 97 DP_SDRVA_ML_C_P 85 97 DP_SDRVA_ML_C_N 85 97 DP_SDRVA_ML_P 85 97 DP_SDRVA_ML_N 85 97 DP_SDRVA_ML_P 85 97 DP_SDRVA_ML_N 85 97 TP_T29_PCIE_RESET0_L 33 TP_T29_PCIE_RESET1_L 33 TP_T29_PCIE_RESET2_L 33 TP_T29_PCIE_RESET3_L 33 T29DPA_D2R1_AUXCH_N 86 97 T29DPA_D2R1_AUXCH_P 86 97 T29_D2R1_BIAS DP_EXTA_ML_P 85 44 SPI_ALT_MISO LPC_FRAME_L PM_CLKRUN_L 53 54 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE 39 40 PP1V8_S0GPU PPVCORE_GPU PP1V8_S0GPU_ISNS_R TRUE 46 53 54 72 NO_TEST=TRUE 30 67 J5800 (IPD FLEX CONN) I1136 TRUE 48 53 63 64 25 42 44 45 46 47 73 104 53 83 99 J4501 (SATA HDD CONN) I1032 46 53 54 72 60 61 60 61 NO_TEST=TRUE J5713 (KEY BOARD CONN) PP3V3_S4 TRUE PP3V42_G3H TRUE WS_KBD1 TRUE WS_KBD2 TRUE WS_KBD3 TRUE WS_KBD4 TRUE WS_KBD5 TRUE WS_KBD6 TRUE WS_KBD7 TRUE WS_KBD8 TRUE WS_KBD9 TRUE WS_KBD10 TRUE WS_KBD11 TRUE WS_KBD12 TRUE WS_KBD13 TRUE WS_KBD14 TRUE WS_KBD15_CAP TRUE WS_KBD16_NUM TRUE WS_KBD17 TRUE WS_KBD18 TRUE WS_KBD19 TRUE WS_KBD20 TRUE WS_KBD21 TRUE WS_KBD22 TRUE WS_KBD23 TRUE WS_KBD_ONOFF_L TRUE WS_LEFT_SHIFT_KBD TRUE WS_LEFT_OPTION_KBD TRUE WS_CONTROL_KBD TRUE GND TRUE A "G3Hot" (Always-Present) Rails 90 64 63 35 50 49 39 PPBUS_G3H PPBUS_G3H MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=12.8V MAKE_BASE=TRUE PPBUS_G3H PPBUS_G3H 70 65 50 69 68 67 PPVIN_S5_HS_COMPUTING_ISNS 35 39 49 50 63 64 90 35 39 49 50 63 64 90 35 39 49 50 63 64 90 35 39 49 50 63 64 90 PPVIN_S5_HS_COMPUTING_ISNS 50 65 67 68 69 70 50 65 67 68 69 70 50 65 67 68 69 70 50 65 67 68 69 70 50 65 67 68 69 70 50 66 VOLTAGE=12.8V MAKE_BASE=TRUE PPVIN_S5_HS_OTHER_ISNS 82 50 87 PPVIN_S5_HS_GPU_ISNS 50 66 PPVIN_S5_HS_GPU_ISNS MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM PPDCIN_G3H PP3V42_G3H 49 63 64 VOLTAGE=18.5V MAKE_BASE=TRUE 17 16 25 20 PPVRTC_G3H 104 103 72 66 54 PP5V_S5 5V Rails B 104 82 42 31 29 72 67 46 44 43 25 42 44 45 46 47 48 53 63 64 73 104 25 42 44 45 46 47 48 53 63 64 73 104 25 42 44 45 46 47 48 53 63 64 73 104 25 42 44 45 46 47 48 53 63 64 73 104 25 42 44 45 46 47 48 53 63 64 73 104 PP3V3_S3 25 42 44 45 46 47 48 53 63 64 73 104 25 42 44 45 46 47 48 53 63 64 73 104 PP5V_S3 25 42 44 45 46 47 48 53 63 64 73 104 25 42 44 45 46 47 48 53 63 64 73 104 25 42 44 45 46 47 48 53 63 64 73 104 25 42 44 45 46 47 48 53 63 64 73 104 25 42 44 45 46 47 48 53 63 64 73 104 16 17 20 25 VOLTAGE=3.42V MAKE_BASE=TRUE 32 31 30 29 25 24 18 104 88 73 55 54 50 49 48 PP5V_S5 54 66 72 103 104 54 66 72 103 104 54 66 72 103 104 54 66 72 103 104 54 66 72 103 104 PP5V_S3 29 31 42 43 44 46 67 72 82 104 VOLTAGE=5V MAKE_BASE=TRUE 29 31 42 43 44 46 67 72 82 104 29 31 42 43 44 46 67 72 82 104 29 31 42 43 44 46 67 72 82 104 29 31 42 43 44 46 67 72 82 104 29 31 42 43 44 46 67 72 82 104 29 31 42 43 44 46 67 72 82 104 29 31 42 43 44 46 67 72 82 104 29 31 42 43 44 46 67 72 82 104 PP5V_S3_ISNS_R 66 104 VOLTAGE=5V MAKE_BASE=TRUE PP5V_S3_ISNS_R PP5V_S0 66 104 PP5V_S0 MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=5V MAKE_BASE=TRUE PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 A 104 72 PP5V_S0_ISNS_R 22 41 47 52 54 65 68 69 70 73 87 104 105 22 41 47 52 54 65 68 69 70 73 87 104 105 22 41 47 52 54 65 68 69 70 73 87 104 105 22 41 47 52 54 65 68 69 70 73 87 104 105 22 41 47 52 54 65 68 69 70 73 87 104 105 22 41 47 52 54 65 68 69 70 73 87 104 105 22 41 47 52 54 65 68 69 70 73 87 104 105 22 41 47 52 54 65 68 69 70 73 87 104 105 22 41 47 52 54 65 68 69 70 73 87 104 105 22 41 47 52 54 65 68 69 70 73 87 104 105 22 41 47 52 54 65 68 69 70 73 87 104 105 22 41 47 52 54 65 68 69 70 73 87 104 105 22 41 47 52 54 65 68 69 70 73 87 104 105 22 41 47 52 54 65 68 69 70 73 87 104 105 22 41 47 52 54 65 68 69 70 73 87 104 105 PP5V_S0_ISNS_R MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM PP5V_S0_ISNS_R 72 22 PP5V_SUS 72 104 72 104 22 72 PP5V_SUS PP1V0_FW_FWPHY VOLTAGE=5V MAKE_BASE=TRUE 104 73 29 15 13 10 PP1V5_S3RS0_CPUDDR 66 104 PP3V3_FW_FWPHY 38 39 40 PP3V3_FW_FWPHY 38 39 40 67 30 PP1V0_FW_FWPHY 38 39 VOLTAGE=1.0V MAKE_BASE=TRUE PPVTTDDR_S3 67 29 28 26 PP0V75_S0_DDRVTT VOLTAGE=3.3V MAKE_BASE=TRUE 16 20 22 25 32 41 57 71 PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3 48 49 50 54 55 73 88 104 18 24 25 29 30 31 32 35 23 14 13 12 10 105 104 102 73 70 68 45 39 18 24 25 29 30 31 32 48 49 50 54 55 73 88 104 18 24 25 29 30 31 32 48 49 50 54 55 73 88 104 PP1V05_S0 ? mA 73 88 73 88 73 88 18 24 25 29 30 31 32 48 49 50 54 55 104 18 24 25 29 30 31 32 48 49 50 54 55 104 18 24 25 29 30 31 32 48 49 50 54 55 104 73 88 73 88 18 24 25 29 30 31 32 48 49 50 54 55 104 18 24 25 29 30 31 32 48 49 50 54 55 104 18 24 25 29 30 31 32 48 49 50 54 55 73 88 104 18 24 25 29 30 31 32 48 49 50 54 55 73 88 104 18 24 25 29 30 31 32 48 49 50 54 55 73 88 104 18 24 25 29 30 31 32 48 49 50 54 55 73 88 104 18 24 25 29 30 31 32 48 49 50 54 55 73 88 104 PP3V3_S3_ISNS_R VOLTAGE=3.3V MAKE_BASE=TRUE PP3V3_S3_ISNS_R PP3V3_S0 72 104 105 69 49 14 12 PPVCORE_S0_CPU 80 79 75 72 84 82 VOLTAGE=1.2V MAKE_BASE=TRUE VOLTAGE=3.3V MAKE_BASE=TRUE PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PPVCORE_S0_AXG PPVCCSA_S0_CPU PP1V5_S3_CPU_VCCDQ PP1V05_S0_CPU_VCCPQE PP3V3_ENET PP1V05_S0 10 12 13 14 23 35 39 45 68 70 73 102 104 105 VOLTAGE=1.05V MAKE_BASE=TRUE PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V5_S0GPU_ISNS_R 103 78 104 51 52 54 57 61 62 72 73 80 83 84 85 88 12 23 25 26 28 32 35 36 39 40 41 46 48 49 50 89 91 100 102 48 49 50 51 52 54 57 61 62 12 23 25 26 28 32 35 36 39 40 41 46 72 73 80 83 84 85 88 89 91 100 102 PP1V2_ENET 13 14 23 35 39 45 68 70 73 102 14 23 35 39 45 68 70 73 102 39 45 68 70 73 102 104 105 14 14 23 35 39 45 68 70 73 102 PP1V5R1V35_GPU_FB_ISNS PP1V0_S0GPU_ISNS_R 103 87 7 12 14 49 69 105 12 14 49 69 105 103 81 79 75 74 7 12 13 15 49 69 12 13 15 49 69 PPVCCSA_S0_CPU 12 15 65 MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.5V MAKE_BASE=TRUE PP1V05_S0_CPU_VCCPQE 103 72 PP1V8_S0GPU_ISNS_R 10 12 14 VOLTAGE=1.05V MAKE_BASE=TRUE 103 81 79 75 PP3V3_ENET PP1V05_T29 12 23 2552 35 34 26 28 32 35 36 39 40 41 46 48 49 50 51 54 57 61 62 72 73 80 83 84 85 88 89 91 100 102 12 23 25 26 28 32 35 36 39 40 28 32 3541 46 48 49 50 51 52 54 57 61 124162 72 73 80 83 84 85 88 89 91 23 25 26100 102 36 39 40 61 62 72 73 80 83 84 85 46 48 49 50 51 52 54 57 25 36 71 73 88 89 91 100 86 35 102 25 36 71 73 25 36 71 73 36 71 VOLTAGE=1.2V MAKE_BASE=TRUE 36 71 16 19 25 33 34 35 88 VOLTAGE=3.3V MAKE_BASE=TRUE MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM 75 76 77 78 103 87 103 87 103 74 75 79 81 103 74 75 79 81 103 74 75 79 81 103 B 74 75 79 81 103 74 75 79 81 103 74 75 79 81 103 74 75 79 81 103 74 75 79 81 103 72 103 72 103 75 79 81 103 75 79 81 103 75 79 81 103 75 79 81 103 75 79 81 103 75 79 81 103 75 79 81 103 75 79 81 103 75 79 81 103 75 79 81 103 75 79 81 103 75 79 81 103 75 79 81 103 PAGE TITLE Power Aliases DRAWING NUMBER 16 19 25 33 34 35 88 Apple Inc 16 19 25 33 34 35 88 R VOLTAGE=1.05V MAKE_BASE=TRUE NOTICE OF PROPRIETARY PROPERTY: 34 35 35 86 VOLTAGE=15V MAKE_BASE=TRUE 35 86 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED SIZE D REVISION 34 35 PP15V_T29 75 76 77 78 103 SYNC_DATE=04/26/2010 16 19 25 33 34 35 88 PP15V_T29 PP15V_T29 75 76 77 78 103 SYNC_MASTER=K17_MLB 16 19 25 33 34 35 88 PP1V05_T29 84 85 88 89 91 100 102 12 23 25 26 28 32 35 36 39 40 41 46 48 49 50 51 52 54 57 61 62 72 73 80 83 75 76 77 78 103 PP1V8_S0GPU PP1V8_S0GPU PP1V8_S0GPU PP1V8_S0GPU PP1V8_S0GPU PP1V8_S0GPU PP1V8_S0GPU PP1V8_S0GPU PP1V8_S0GPU PP1V8_S0GPU PP1V8_S0GPU PP1V8_S0GPU 25 36 71 73 PP3V3_T29 PP3V3_T29 PP3V3_T29 PP3V3_T29 PP1V05_T29 MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM 75 76 77 78 103 MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.8V MAKE_BASE=TRUE VOLTAGE=3.3V MAKE_BASE=TRUE PP1V2_ENET MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM 87 103 PP1V5R1V35_GPU_FB_ISNS PP1V8_S0GPU_ISNS_R PP1V8_S0GPU PP1V8_S0GPU ENET Rails PP3V3_T29 102 51 52 54 57 61 62 72 73 80 83 84 85 88 23 25 26 28 32 35 36 39 40 41 46 48 49 89 91 100 12 80 83 84 85 88 89 91 100 102 50 46 48 49 50 51 52 54 57 61 62 72 73 12 23 25 26 28 32 35 36 39 40 41 102 57 61 62 72 73 80 83 84 85 88 89 91 100 12 23 25 26 28 32 35 36 39 40 41 46 48 49 50 51 52 54 84 85 88 89 91 100 102 12 23 25 26 28 32 35 36 39 40 41 46 48 49 50 51 52 54 57 61 62 72 73 80 83 PP1V5_S0GPU_ISNS_R PP1V8_S0GPU_ISNS_R T29 Rails PP3V3_T29 87 103 MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.8V MAKE_BASE=TRUE 84 85 88 89 91 100 102 12 23 25 26 28 32 35 36 39 40 41 46 48 49 50 51 52 54 57 61 62 72 73 80 83 88 35 34 33 25 19 16 7 72 75 79 80 82 84 12 15 MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM PP1V2_ENET 12 23 25 26 28 32 35 36 39 40 41 46 48 49 50 51 52 54 57 61 62 72 73 80 83 84 85 88 89 91 100 102 72 75 79 80 82 84 PP1V0_S0GPU PP1V0_S0GPU PP1V0_S0GPU PP1V0_S0GPU PP1V0_S0GPU PP1V0_S0GPU PP1V0_S0GPU 12 15 65 PP1V5_S3_CPU_VCCDQ 72 75 79 80 82 84 MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.0V MAKE_BASE=TRUE VOLTAGE=0.9V MAKE_BASE=TRUE PPVCCSA_S0_CPU 72 75 79 80 82 84 PP1V0_S0GPU_ISNS_R PP1V0_S0GPU PP1V0_S0GPU VOLTAGE=1.05V MAKE_BASE=TRUE PPVCORE_S0_AXG C 72 75 79 80 82 84 MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.0V MAKE_BASE=TRUE VOLTAGE=1.1V MAKE_BASE=TRUE PPVCORE_S0_AXG 72 75 79 80 82 84 PP1V5R1V35_GPU_FB_ISNS PP1V5R1V35_GPU_FB_ISNS PP1V5R1V35_GPU_FB_ISNS PP1V5R1V35_GPU_FB_ISNS PP1V0_S0GPU_ISNS_R 10 12 13 14 23 35 39 45 68 70 73 102 104 105 PPVCORE_S0_CPU 72 75 79 80 82 84 MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.5V MAKE_BASE=TRUE 10 12 13 14 23 35 39 45 68 70 73 102 104 105 Chipset Rails MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM 84 85 88 89 91 100 102 12 23 25 26 28 32 35 36 39 40 41 46 48 49 50 51 52 54 57 61 62 72 73 80 83 13 14 23 35 39 45 68 70 73 102 13 35 13 75 13 72 75 79 80 82 84 MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.5V MAKE_BASE=TRUE 10 12 13 14 23 35 39 45 68 70 73 102 104 105 10 12 13 14 23 35 39 45 68 70 73 102 104 105 PP3V3_ENET PP3V3_ENET PP3V3_ENET 84 85 88 89 91 100 102 12 23 25 26 28 32 35 36 39 40 41 46 48 49 50 51 52 54 57 61 62 72 73 80 83 10 12 105 10 12 105 10 12 105 23 10 12 77 76 10 12 105 49 75 82 PP1V5_S0GPU_ISNS_R 10 103 87 12 13 14 23 35 39 45 68 70 73 102 104 105 104 104 104 49 75 82 PP3V3_S0GPU PP3V3_S0GPU PP3V3_S0GPU PP3V3_S0GPU PP3V3_S0GPU PP3V3_S0GPU PP3V3_S0GPU 23 71 MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM 84 85 88 89 91 100 102 12 23 25 26 28 32 35 36 39 40 41 46 48 49 50 51 52 54 57 61 62 72 73 80 83 26 28 29 67 MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V MAKE_BASE=TRUE 23 71 PP1V05_SUS MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM 26 28 29 67 PPVCORE_GPU PP3V3_S0GPU PP3V3_S0GPU VOLTAGE=1.05V MAKE_BASE=TRUE MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM 51 52 54 57 61 62 72 73 80 83 84 85 88 12 23 25 26 28 32 35 36 39 40 41 46 48 49 50 89 91 100 102 48 49 50 51 52 54 57 61 62 887 12 23 25 26 28 32 35 36 39 40 41 46 4972 73 80 83 84 85 88 89 91 100 102 12 23 25 26 28 32 35 36 39 40 41 46 48 50 51 52 54 57 61 62 72 73 80 83 84 85 896 91 100 102 83 84 85 88 89 91 100 102 1212 23 25 26 28 32 35 36 39 40 41 46 48 49 50 51 52 54 57 61 62 72 73 80 23 25 26 28 32 35 36 39 40 41 46 48 49 50 51 52 54 57 61 62 72 73 80 83 84 85 88 89 91 100 6102 48 49 50 51 52 54 57 61 62 72 73 88 12 23 25 26 28 32 35 36 39 40 41 46 49 80 83 84 85 88 89 91 100 102 12 23 25 26 28 32 35 36 39 40 41 46 48 50 51 52 54 57 61 62 72 73 80 83 84 85 89 91 100 102 84 85 88 89 14 12 10 7 12 23 25 26 28 32 35 36 39 40 41 46 48 49 50 51 52 54 57 61 62 72 73 80 83 91 100 102 48 49 50 51 52 54 57 61 62 72 887 12 23 25 26 28 32 35 36 39 40 41 46 4973 80 83 84 85 88 89 91 100 102 12 23 25 26 28 32 35 36 39 40 41 46 48 50 51 52 54 57 61 62 72 73 80 83 84 85 89 91 100 102 73 71 36 25 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP1V05_SUS PPVCORE_S0_CPU 80 83 84 85 88 89 91 100 102 12 23 25 26 28 32 35 36 39 40 41 46 100 102 48 49 50 51 52 54 57 61 62 72 73 73 80 83 84 85 88 89 91 62 72 57 61 69 49 15 13 12 7 12 23 25 26 28 32 35 36 39 40 41 46 48 49 50 51 52 54 84 85 88 89 91 100 102 12 23 25 26 28 32 35 36 39 40 41 46 48 49 50 51 52 54 57 61 62 72 73 80 83 26 28 29 67 MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.15V MAKE_BASE=TRUE 71 88 MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM 72 104 MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.2 MM 26 28 29 67 PPVCORE_GPU PPVCORE_GPU 16 20 22 25 32 41 57 71 MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM 18 24 25 29 30 31 32 48 49 50 54 55 73 88 104 30 67 "GPU" Rails 16 20 22 25 32 41 57 71 16 17 18 19 20 22 46 71 72 73 PP3V3_S3 PPVTTDDR_S3 10 13 15 29 73 104 16 20 22 25 32 41 57 71 PP1V2_S0 PP1V05_SUS 10 13 15 29 73 104 PP0V75_S0_DDRVTT PP0V75_S0_DDRVTT PP0V75_S0_DDRVTT 16 20 22 25 32 41 57 71 PP1V2_S0 16 17 18 19 20 22 46 71 72 73 71 23 7 16 17 18 19 20 22 46 71 72 73 PP1V5_S3RS0_CPUDDR PP1V5_S3RS0_CPUDDR PP0V75_S0_DDRVTT VOLTAGE=1.5V MAKE_BASE=TRUE MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM 16 17 18 19 20 22 46 71 72 73 10 13 15 29 73 104 MIN_LINE_WIDTH=2 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0.75V MAKE_BASE=TRUE 38 39 16 17 18 19 20 22 46 71 72 73 PP1V2_S0 D 72 100 104 MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=0.75V MAKE_BASE=TRUE MAKE_BASE=TRUE VOLTAGE=3.3V 16 17 18 19 20 22 46 71 72 73 16 17 18 19 20 22 46 71 72 73 72 100 104 VOLTAGE=3.3V MAKE_BASE=TRUE PP1V5_S0 PP1V5_S0 PP1V5_S0 16 17 18 19 20 22 46 71 72 73 26 28 29 67 72 MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.5V MAKE_BASE=TRUE 39 40 PP1V5_S0 66 104 26 28 29 67 72 PP1V5_S3RS0_CPUDDR 39 40 MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V MAKE_BASE=TRUE PP3V3_S0 VOLTAGE=12.8V MAKE_BASE=TRUE PP1V5_S0 PP1V5_S0 26 28 29 67 72 PP1V5_S3RS0 1.5V/1.05V Rails 46 53 54 72 20 16 71 57 41 32 25 22 26 28 29 67 72 39 40 46 53 54 72 46 53 54 72 26 28 29 67 72 MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.5V MAKE_BASE=TRUE 12 14 PP1V0_FW_FWPHY MAKE_BASE=TRUE VOLTAGE=3.3V 22 72 PP1V5_S3RS0 VOLTAGE=1.8V MAKE_BASE=TRUE MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM 17 19 20 22 23 24 25 29 46 48 56 71 72 73 83 86 91 100 102 104 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 VOLTAGE=5V MAKE_BASE=TRUE PP5V_SUS MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM 8 22 41 47 52 54 65 68 69 70 73 87 104 105 14 20 25 71 72 88 102 MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM 17 19 20 22 23 24 25 29 46 48 56 71 72 73 83 86 91 100 102 104 39 38 MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM PP3V3_S0 MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM 105 104 87 54 52 47 41 22 73 70 69 68 65 PP3V3_S3_ISNS_R 54 66 72 103 104 100 91 89 88 85 84 46 41 40 39 36 35 32 28 26 25 23 12 83 80 73 72 62 61 57 54 52 51 50 49 48 102 PP5V_S3 PP5V_S3 PP5V_S3 PP5V_S3 PP5V_S3_ISNS_R PP3V3_FW_FWPHY 17 19 20 22 23 24 25 29 46 48 56 71 72 73 83 86 91 100 102 104 PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3 54 66 72 103 104 PP5V_S3 PP5V_S3 PP5V_S3 PP5V_S3 104 66 PP3V3_S3 14 20 25 71 72 88 102 PPVP_FW PPVP_FW 17 19 20 22 23 24 25 29 46 48 56 71 72 73 83 86 91 100 102 104 PP3V3_S3 PP3V3_S3 VOLTAGE=5V MAKE_BASE=TRUE 54 66 72 103 104 104 72 7 54 66 72 103 104 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM 17 19 20 22 23 24 25 29 46 48 56 71 72 73 83 86 91 100 102 104 17 19 20 22 23 24 25 29 46 48 56 71 72 73 83 86 91 100 102 104 17 19 20 22 23 24 25 29 46 48 56 71 72 73 83 86 91 100 102 104 PP3V3_SUS PP3V3_SUS PP3V3_SUS PP3V3_SUS PP3V3_SUS PP3V3_SUS PP3V3_SUS MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm 14 20 25 71 72 88 102 PPVP_FW 17 19 20 22 23 24 25 29 46 48 56 71 72 73 83 86 91 100 102 104 40 39 38 PP1V5_S3 PP1V5_S3 PP1V5_S3 PP1V5_S3 PP1V5_S3 PP1V5_S3RS0 14 20 25 71 72 88 102 "FW" (FireWire) Rails PPVP_FW 26 28 29 67 72 MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.5V MAKE_BASE=TRUE 14 20 25 71 72 88 102 PP1V8_S0_CPU_VCCPLL_R MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM 25 42 44 45 46 47 48 53 63 64 73 104 16 17 20 25 PP5V_S5 PP5V_S5 PP5V_S5 PP5V_S5 PP5V_S5 PP5V_S5 PP5V_S5 PP5V_S5 PP5V_S5 PP1V8_S0_CPU_VCCPLL_R PP1V5_S3 PP1V5_S3 14 20 25 71 72 88 102 104 100 72 7 17 19 20 22 23 24 25 29 46 48 56 14 12 71 72 73 83 86 916 100 102 104 1717 19 20 22 23 24 25 29 46 48 56 71 72 73 83 86 91 100 102 104 83 86 91 19 20 22 23 24 25 29 46 48 56 71 72 73 100 102 104 91 100 102 104 17 19 20 40 39 22 23 24 25 29 46 48 56 71 72 73 83 86 PP3V3_SUS MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.8V MAKE_BASE=TRUE PP1V8_S0 PP1V8_S0 PP1V8_S0 PP1V8_S0 PP1V8_S0 24 25 29 46 48 56 71 102 104 24 25 29 46 48 56 71 102 104 24 25 29 46 48 56 71 102 104 PP1V8_S0 PP3V3_S5_ISNS_R PP3V3_SUS PP1V8_S0 MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM 102 88 72 71 25 20 14 6 17 19 20 22 23 24 25 29 46 48 56 71 72 73 83 86 91 100 102 104 PP3V3_S5_ISNS_R MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM 25 42 44 45 46 47 48 53 63 64 73 104 PPVRTC_G3H MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.2 MM PP3V3_S5_ISNS_R VOLTAGE=3.42V MAKE_BASE=TRUE PPVRTC_G3H MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.2 MM 66 104 49 63 64 PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H C PP3V3_S4 PP3V3_S4 PP1V8_S0 17 19 20 22 23 72 73 83 86 91 100 17 19 20 22 23 72 73 83 86 91 100 17 19 20 22 23 72 73 83 86 91 100 PP3V3_S4 MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM 49 63 64 72 71 46 22 20 19 18 17 16 73 PP3V42_G3H MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.2 MM 72 54 53 46 7 50 82 87 PPDCIN_G3H PPDCIN_G3H 64 63 53 45 44 42 25 48 47 46 104 73 PP3V3_S4 50 82 87 PPDCIN_G3H MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM 72 67 29 28 26 29 46 48 56 71 72 73 83 86 91 100 102 104 17 19 20 22 23 24 25 102 88 72 71 25 20 14 6 17 19 20 22 23 24 25 29 46 48 56 71 72 73 83 86 91 100 102 104 50 82 87 VOLTAGE=12.8V MAKE_BASE=TRUE PPVIN_S5_HS_GPU_ISNS PPVIN_S5_HS_GPU_ISNS 64 63 49 VOLTAGE=3.3V MAKE_BASE=TRUE PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 50 65 67 68 69 70 VOLTAGE=5V MAKE_BASE=TRUE PPVIN_S5_HS_OTHER_ISNS MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM DDR Rails PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 35 39 49 50 63 64 90 PPVIN_S5_HS_COMPUTING_ISNS PPVIN_S5_HS_COMPUTING_ISNS PPVIN_S5_HS_COMPUTING_ISNS PPVIN_S5_HS_COMPUTING_ISNS PPVIN_S5_HS_COMPUTING_ISNS PPVIN_S5_HS_OTHER_ISNS PP3V3_S5 MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM 35 39 49 50 63 64 90 MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM 66 50 PP3V3_S5 35 39 49 50 63 64 90 35 39 49 50 63 64 90 PPBUS_G3H PPBUS_G3H PPBUS_G3H PPBUS_G3H PPBUS_G3H D 3.3V/1.8V Rails BRANCH PAGE OF 132 SHEET OF 105 A 91 88 87 82 74 PM_ALL_GPU_PGOOD PM_ALL_GPU_PGOOD 74 82 87 88 91 Top GPU Center TM Hole 88 TP_LVDS_MUX_SEL_EG EG_RESET_L STDOFF-4.5OD.98H-1.1-3.48-TH ZT0980 88 18 LVDS_IG_BKL_ON 88 18 LVDS_IG_PANEL_PWR GFXIMVP_VID 94 18 NC_LVDS_IG_A_DATAP TP_LVDS_MUX_SEL_EG 88 EG_RESET_L 74 88 LVDS_IG_BKL_ON 18 88 LVDS_IG_PANEL_PWR 18 88 94 18 NC_LVDS_IG_A_DATAN MEMVTT_EN 29 67 8 18 94 NC_LVDS_IG_A_DATAN 18 94 NC_LVDS_IG_B_DATAP 18 NC_LVDS_IG_B_DATAN 18 NO_TEST=TRUE NC_LVDS_IG_B_DATAP MAKE_BASE=TRUE MAKE_BASE=TRUE LCD_BKLT_EN 88 90 NC_PEG_D2R_P NC_PEG_D2R_N =PEG_D2R_P MAKE_BASE=TRUE 18 PEX_CLKREQ_L PEG_CLKREQ_L 88 16 TP_LVDS_IG_B_CLKP 18 TP_LVDS_IG_B_CLKN 18 TP_LVDS_IG_BKL_PWM TP_LVDS_IG_B_CLKN 18 TP_LVDS_IG_BKL_PWM 18 MAKE_BASE=TRUE =PEG_R2D_C_N NC_PEG_R2D_C_N TP_LVDS_IG_B_CLKP 18 MAKE_BASE=TRUE 80 88 PEG_CLKREQ_L =PEG_R2D_C_P NC_PEG_R2D_C_P PEX_CLKREQ_L MAKE_BASE=TRUE D NO_TEST=TRUE MAKE_BASE=TRUE =PEG_D2R_N MAKE_BASE=TRUE 88 80 NO_TEST=TRUE NC_LVDS_IG_B_DATAN 18 MAKE_BASE=TRUE Bottom GPU Left TM Hole NC_GPU_XTALOUT NC_LVDS_IG_A_DATAP NO_TEST=TRUE MAKE_BASE=TRUE Unused PEG lanes ZT0987 MAKE_BASE=TRUE MAKE_BASE=TRUE 16 88 MAKE_BASE=TRUE SH0936 1.4DIA-SHORT-EMI-MLB-M97-M98 SH0920 61 SM ZT0915 GND GND GND GND SM 1.4DIA-SHORT-EMI-MLB-M97-M98 Frame Holes GND_CHASSIS_AUDIO_JACK GND 92 74 PEG_D2R_N 92 74 SH0910 3R2P5 1.4DIA-SHORT-EMI-MLB-M97-M98 SM 24 32 USB_EXTC_OC_L 24 43 USB_EXCARD_N 24 32 100 USB_EXCARD_P 24 32 100 USB_EXTC_OC_L 43 24 =PEG_D2R_N =PEG_R2D_C_P 100 32 24 USB_EXCARD_N =PEG_R2D_C_N 100 32 24 USB_EXCARD_P MAKE_BASE=TRUE MAKE_BASE=TRUE 92 74 PEG_R2D_C_P 92 74 PEG_R2D_C_N MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE SM DP_IG_AUX_CH_P 94 84 17 DP_IG_AUX_CH_P 17 84 94 DP_IG_AUX_CH_N 17 84 94 DP_IG_DDC_CLK 17 80 84 DP_IG_DDC_DATA 17 80 84 MAKE_BASE=TRUE DP_IG_AUX_CH_N 94 84 17 39 19 ZT0960 FW_PLUG_DET_L FW_PLUG_DET_L 19 39 3R2P5 DP_IG_DDC_CLK 84 80 17 39 38 FW643_WAKE_L 38 39 MAKE_BASE=TRUE 36 TP_SDCONN_DATA C 36 TP_SDCONN_CLK 36 TP_SDCONN_CMD SDCONN_DATA 36 36 1.4DIA-SHORT-EMI-MLB-M97-M98 SM TP_SDCONN_DETECT_L 36 TP_SDCONN_WP 36 TP_ENET_CR_PWREN TP_SDCONN_DETECT_L 8 NC_ISNS_P3V3S0MPCH_N NC_ISNS_P3V3S0MPCH_P NC_ISNS_P3V3S0MPCH_N NC_ISNS_P3V3S0MPCH_P NC_ISNS_PVTTS0PCH_N NC_ISNS_PVTTS0PCH_P MAKE_BASE=TRUE 95 33 PCIE_T29_D2R_N 95 33 PCIE_T29_R2D_C_P 95 33 36 =PEG_D2R_N =PEG_R2D_C_P PCIE_T29_R2D_C_N NC_ISNS_PVTTS0PCH_N NC_ISNS_PVTTS0PCH_P C MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE NC_ISNS_P1V05S0PCH_P MAKE_BASE=TRUE =PEG_D2R_P MAKE_BASE=TRUE TP_SDCONN_CLK TP_SDCONN_CMD MAKE_BASE=TRUE 3R2P5 PCIE_T29_D2R_P MAKE_BASE=TRUE MAKE_BASE=TRUE NC_ISNS_P1V05S0PCH_N 17 84 T29 Signals 95 33 SH0914 NC_ISNS_P1V05S0PCH_P MAKE_BASE=TRUE DP_IG_HPD Unused SD card signals ZT0940 MAKE_BASE=TRUE SM DP_IG_HPD 84 17 SM 1.4DIA-SHORT-EMI-MLB-M97-M98 NC_ISNS_P1V05S0PCH_N MAKE_BASE=TRUE DP_IG_DDC_DATA 84 80 17 1.4DIA-SHORT-EMI-MLB-M97-M98 SH0912 MAKE_BASE=TRUE FW643_WAKE_L MAKE_BASE=TRUE SH0913 Rev A NCs MAKE_BASE=TRUE MAKE_BASE=TRUE ZT0971 EXCARD_OC_L MAKE_BASE=TRUE =PEG_D2R_P MAKE_BASE=TRUE 1.4DIA-SHORT-EMI-MLB-M97-M98 ZT0932 EXCARD_OC_L 32 24 PEG_D2R_P GND SH0911 USB Hub Aliases GPU signals GND MAKE_BASE=TRUE 3R2P5 92 NO_TEST=TRUE MAKE_BASE=TRUE MEMVTT_EN MAKE_BASE=TRUE 18 LCD_BKLT_EN 90 88 Bottom CPU Left TM Hole 3R2P5 NC_GPU_XTALOUT MAKE_BASE=TRUE 67 29 MAKE_BASE=TRUE STDOFF-4.5OD.98H-1.1-3.48-TH MAKE_BASE=TRUE =PEG_R2D_C_N MAKE_BASE=TRUE 36 MAKE_BASE=TRUE TP_SDCONN_WP 36 TP_ENET_CR_PWREN 36 Unused T29 Ports MAKE_BASE=TRUE ZT0970 3R2P5 SH0923 97 T29_D2R_P 97 T29_D2R_N NC_T29_D2RP MAKE_BASE=TRUE MAKE_BASE=TRUE 1.4DIA-SHORT-EMI-MLB-M97-M98 AUDIO ALIASES SH0924 97 T29_R2D_C_P 97 T29_R2D_C_N ZT0934 SM ZT0931 XW0900 STDOFF-4.0OD3.35H-TH STDOFF-4.0OD3.35H-TH 87 73 70 69 68 65 54 52 47 41 22 105 104 PP5V_S0_AUDIO ZT0988 T29_A_BIAS_R SH0917 2.0DIA-TALL-EMI-MLB-M97-M98 ZT0989 XW0902 SM STDOFF-4.5OD.98H-1.1-3.48-TH T29_LSEO_LSOE3 T29_LSEO_LSOE3 33 T29_LSEO_LSOE2 33 MAKE_BASE=TRUE NO_TEST=TRUE T29_LSEO_LSOE2 33 T29_A_BIAS_R 88 33 23 19 JTAG_ISP_TCK 88 33 19 JTAG_ISP_TDI 88 18 LVDS_IG_PANEL_PWR JTAG_ISP_TCK 19 23 33 88 JTAG_ISP_TCK 19 23 33 88 JTAG_ISP_TDI 19 33 88 JTAG_ISP_TDO 19 33 88 MAKE_BASE=TRUE 2.0DIA-TALL-EMI-MLB-M97-M98 GND SH0919 2.0DIA-TALL-EMI-MLB-M97-M98 R0902 MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.11MM VOLTAGE=0V JTAG_ISP_TDO 5% 1/16W MF-LF 402 86 86 T29_A_BIAS_R SM PP3V3_S3 SH0931 ZT0958 1 R0915 2.0DIA-TALL-EMI-MLB-M97-M98 SM 1 SH0922 2.0DIA-TALL-EMI-MLB-M97-M98 10K 5% 1/16W MF-LF 402 5% 1/16W MF-LF 402 USB_T29A_P 51 5% 1/20W MF 201 24 94 T29_A_BIAS_R 24 94 85 DP_A_BIAS_N_2 A 2.0DIA-TALL-EMI-MLB-M97-M98 1 SH0941 STDOFF-4.0OD1.85H-SM STDOFF-4.0OD1.85H-SM 85 DP_A_BIAS_P_2 SH0901 SM SIGNAL_MODEL=EMPTY C0910 Heat spreader mounting boss for PCH 0.01UF 10% 10V X5R 201 SYNC_DATE=04/26/2010 Signal Aliases 10% 10V X5R 201 DRAWING NUMBER Apple Inc T29BST:N SH0942 SH0943 STDOFF-4.0OD2.23H-SM STDOFF-4.0OD2.23H-SM NOTICE OF PROPRIETARY PROPERTY: R0950 90 64 63 50 49 39 35 PPBUS_G3H 5% 1/8W MF-LF 805 C0908 PP15V_T29 35 86 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED SIZE D REVISION R SIGNAL_MODEL=EMPTY PAGE TITLE C0911 0.01UF 10% 10V X5R 201 DP_A_BIAS_N_0 C0905 0.01UF 2.0DIA-TALL-EMI-MLB-M97-M98 85 SIGNAL_MODEL=EMPTY SYNC_MASTER=K17_MLB 2.0DIA-TALL-EMI-MLB-M97-M98 SM SIGNAL_MODEL=EMPTY DP_A_BIAS_P_0 0.01UF 2.0DIA-TALL-EMI-MLB-M97-M98 SM 85 SIGNAL_MODEL=EMPTY 1 SH0935 SM 0.01UF 10% 10V X5R 201 DP_A_BIAS caps SH0940 2.0DIA-TALL-EMI-MLB-M97-M98 SH0903 85 C0904 10% Heat spreader mounting boss for T29 router SH0933 10% 10V X5R 201 SM SM T29_A_BIAS_R2D_N1 0.01UF 10V X5R SIGNAL_=EMPTY SH0900 DP_A_BIAS caps 86 C0907 201 2.0DIA-TALL-EMI-MLB-M97-M98 51 5% 1/20W MF 201 T29_A_BIAS_D2R_N1 SM 0.01UF R0927 T29_A_BIAS_R 2.0DIA-TALL-EMI-MLB-M97-M98 SH0934 C0903 10% SIGNAL_MODEL=EMPTY 10V X5R 201 SIGNAL_MODEL=EMPTY 86 SH0932 B 85 R0924 86 201 SM SIGNAL_MODEL=EMPTY 0.01UF 10% SIGNAL_MODEL=EMPTY 10V X5R R0916 USB_T29A_N 2.0DIA-TALL-EMI-MLB-M97-M98 T29_A_BIAS_R2D_P1 86 C0906 10K SM SH0902 51 5% 1/20W MF 201 T29_A_BIAS_D2R_P1 18 24 25 29 30 31 32 48 49 50 54 55 73 88 104 4.0OD1.65H-M1.6X0.35 5% 1/20W MF 201 2.0DIA-TALL-EMI-MLB-M97-M98 51 Unused USB ports SH0921 4.0OD1.65H-M1.6X0.35 0.01UF R0926 ZT0957 85 C0902 10% 10V X5R SIGNAL_MODEL=EMPTY 201 SIGNAL_MODEL=EMPTY SM Bosses for Flex Protector Bracket T29_A_BIAS_R T29_A_BIAS caps 2.0DIA-TALL-EMI-MLB-M97-M98 R0923 MAKE_BASE=TRUE 100K SM SH0930 88 33 19 T29_A_BIAS_R2D_N0 SIGNAL_MODEL=EMPTY SM 0.01UF 10% SIGNAL_MODEL=EMPTY 10V X5R 201 5% 1/20W MF 201 MAKE_BASE=TRUE 1 51 T29 / GMUX JTAG Signals 60 85 C0901 R0922 86 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5V Digital Ground SIGNAL_MODEL=EMPTY T29_LSEO_LSOE2 MAKE_BASE=TRUE NO_TEST=TRUE SH0918 T29_A_BIAS_R2D_P0 5% 1/20W MF 201 60 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5V PP5V_S0_AUDIO_AMP_L 51 NO_TEST=TRUE SM ZT0991 T29_LSEO_LSOE3 33 PP5V_S0_AUDIO_AMP_R XW0901 SM STDOFF-4.5OD.98H-1.1-3.48-TH 86 33 57 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5V SM SH0916 2.0DIA-TALL-EMI-MLB-M97-M98 STDOFF-4.5OD.98H-1.1-3.48-TH R0921 NO_TEST=TRUE SM PP5V_S0 SIGNAL_MODEL=EMPTY 33 NC_T29_R2D_CN MAKE_BASE=TRUE T29_A_BIAS caps 33 NO_TEST=TRUE NC_T29_R2D_CP MAKE_BASE=TRUE 2.0DIA-TALL-EMI-MLB-M97-M98 33 NO_TEST=TRUE NC_T29_D2RN MAKE_BASE=TRUE SM B CPUIMVP_VID MAKE_BASE=TRUE GFX_VID MAKE_BASE=TRUE 1 TP_CPU_VTT_SELECT MAKE_BASE=TRUE Left CPU TM Hole TP_CPU_VTT_SELECT 92 MAKE_BASE=TRUE 92 MAKE_BASE=TRUE ZT0930 STDOFF-4.5OD.98H-1.1-3.48-TH CPU_VID 92 MAKE_BASE=TRUE 88 74 D MAKE_BASE=TRUE 1 ZT0983 CPU signals ZT0981 STDOFF-4.5OD.98H-1.1-3.48-TH STDOFF-4.5OD.98H-1.1-3.48-TH STDOFF-4.5OD.98H-1.1-3.48-TH Right CPU ZT0984 TM Hole STDOFF-4.5OD.98H-1.1-3.48-TH ZT0982 GMUX ALIASES Thermal Module Holes Bottom GPU Right TM Hole BRANCH PAGE OF 132 SHEET OF 105 A PP1V05_S0 10 12 13 14 23 35 39 45 68 70 73 102 104 105 R1010 24.9 1% 1/16W MF-LF 402 IN 92 17 IN 92 17 IN 92 17 IN 92 17 IN 92 17 IN 92 17 OUT 92 17 OUT 92 17 OUT 92 17 OUT 92 17 OUT 92 17 OUT 92 17 OUT 92 17 OUT 92 17 OUT 92 17 OUT 92 17 OUT 92 17 OUT 92 17 OUT 92 17 OUT 92 17 C OUT 92 17 OUT 92 17 OUT 92 17 OUT 92 17 OUT 92 17 OUT 92 17 OUT 92 17 IN 92 17 IN 92 17 92 17 92 17 B FDI_TX_0* FDI_TX_1* FDI_TX_2* FDI_TX_3* FDI_TX_4* FDI_TX_5* FDI_TX_6* FDI_TX_7* FDI_TX_0 FDI_TX_1 FDI_TX_2 FDI_TX_3 FDI_TX_4 FDI_TX_5 FDI_TX_6 FDI_TX_7 FDI0_FSYNC FDI1_FSYNC IN FDI_LSYNC FDI_LSYNC AB7 AB3 FDI0_LSYNC FDI1_LSYNC TP_EDP_TX_N TP_EDP_TX_N TP_EDP_TX_N TP_EDP_TX_N AG2 AF1 AE6 AG6 R1030 24.9 EDP_TX_0* EDP_TX_1* EDP_TX_2* EDP_TX_3* TP_EDP_TX_P TP_EDP_TX_P TP_EDP_TX_P TP_EDP_TX_P AG4 AF3 AF7 AG8 EDP_TX_0 EDP_TX_1 EDP_TX_2 EDP_TX_3 TP_EDP_AUX_P TP_EDP_AUX_N AE4 AE2 EDP_AUX EDP_AUX* CPU_EDP_COMP AB1 AC2 EDP_ICOMPO EDP_COMPIO AE8 EDP_HPD PLACE_NEAR=U1000.AB1:12.7mm CPU_EDP_HPD 10K PU disables eDP HPD CPU_CFG should be pulled down to enable EDP 92 23 92 23 92 23 92 23 92 23 CPU_CFG CPU_CFG CPU_CFG CPU_CFG CPU_CFG 92 23 92 23 92 23 92 23 NOSTUFF A EDP NOSTUFF1 NOSTUFF1 NOSTUFF1 NOSTUFF1 NOSTUFF1 R1044 R1046 R1047 R1040 R1041 R1043 1K 1K 1K 1K 1K 1K 1K 1K 5% 1/16W MF-LF 402 5% 1/16W MF-LF 402 5% 1/16W MF-LF 402 5% 1/16W MF-LF 402 5% 1/16W MF-LF 402 5% 1/16W MF-LF 402 5% 1/16W MF-LF 402 5% 1/16W MF-LF 402 2 2 92 23 92 23 CPU_PEG_COMP 92 23 92 23 PEG_RX_0* PEG_RX_1* PEG_RX_2* PEG_RX_3* PEG_RX_4* PEG_RX_5* PEG_RX_6* PEG_RX_7* PEG_RX_8* PEG_RX_9* PEG_RX_10* PEG_RX_11* PEG_RX_12* PEG_RX_13* PEG_RX_14* PEG_RX_15* F23 H23 H21 H19 J20 G18 K17 F15 H15 H13 H11 J12 E8 G10 J8 F7 =PEG_D2R_N =PEG_D2R_N =PEG_D2R_N =PEG_D2R_N =PEG_D2R_N =PEG_D2R_N =PEG_D2R_N =PEG_D2R_N =PEG_D2R_N =PEG_D2R_N =PEG_D2R_N =PEG_D2R_N NC_PEG_D2R_N NC_PEG_D2R_N NC_PEG_D2R_N NC_PEG_D2R_N PEG_RX_0 PEG_RX_1 PEG_RX_2 PEG_RX_3 PEG_RX_4 PEG_RX_5 PEG_RX_6 PEG_RX_7 PEG_RX_8 PEG_RX_9 PEG_RX_10 PEG_RX_11 PEG_RX_12 PEG_RX_13 PEG_RX_14 PEG_RX_15 G22 K23 K21 F19 K19 H17 K15 G14 J16 K13 F11 K11 F9 H9 H7 G6 =PEG_D2R_P =PEG_D2R_P =PEG_D2R_P =PEG_D2R_P =PEG_D2R_P =PEG_D2R_P =PEG_D2R_P =PEG_D2R_P =PEG_D2R_P =PEG_D2R_P =PEG_D2R_P =PEG_D2R_P NC_PEG_D2R_P NC_PEG_D2R_P NC_PEG_D2R_P NC_PEG_D2R_P PEG_TX_0* PEG_TX_1* PEG_TX_2* PEG_TX_3* PEG_TX_4* PEG_TX_5* PEG_TX_6* PEG_TX_7* PEG_TX_8* PEG_TX_9* PEG_TX_10* PEG_TX_11* PEG_TX_12* PEG_TX_13* PEG_TX_14* PEG_TX_15* A22 B23 C18 D21 B19 E20 A14 D17 B15 E16 D13 A10 B11 D9 B7 E12 =PEG_R2D_C_N =PEG_R2D_C_N =PEG_R2D_C_N =PEG_R2D_C_N =PEG_R2D_C_N =PEG_R2D_C_N =PEG_R2D_C_N =PEG_R2D_C_N =PEG_R2D_C_N =PEG_R2D_C_N =PEG_R2D_C_N =PEG_R2D_C_N NC_PEG_R2D_C_N NC_PEG_R2D_C_N NC_PEG_R2D_C_N NC_PEG_R2D_C_N PEG_TX_0 PEG_TX_1 PEG_TX_2 PEG_TX_3 PEG_TX_4 PEG_TX_5 PEG_TX_6 PEG_TX_7 PEG_TX_8 PEG_TX_9 PEG_TX_10 PEG_TX_11 PEG_TX_12 PEG_TX_13 PEG_TX_14 PEG_TX_15 C22 D23 A18 B21 D19 F21 C14 B17 D15 F17 B13 C10 D11 B9 D7 F13 =PEG_R2D_C_P =PEG_R2D_C_P =PEG_R2D_C_P =PEG_R2D_C_P =PEG_R2D_C_P =PEG_R2D_C_P =PEG_R2D_C_P =PEG_R2D_C_P =PEG_R2D_C_P =PEG_R2D_C_P =PEG_R2D_C_P =PEG_R2D_C_P NC_PEG_R2D_C_P NC_PEG_R2D_C_P NC_PEG_R2D_C_P NC_PEG_R2D_C_P IN 92 23 IN 92 23 IN 92 23 IN 92 23 IN 92 23 IN 92 23 IN 92 23 IN 23 IN 23 IN 23 IN 23 IN 92 23 IN 92 23 IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT 2 B57 D57 B55 A54 A58 D55 C56 E54 J54 G56 F55 K55 F57 E58 H57 H55 D53 K57 CPU_CFG CPU_CFG CPU_CFG CPU_CFG CPU_CFG CPU_CFG CPU_CFG CPU_CFG CPU_CFG CPU_CFG CPU_CFG CPU_CFG CPU_CFG CPU_CFG CPU_CFG CPU_CFG CPU_CFG CPU_CFG NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NOTE: Intel is investigating processor driven VREF_DQ generation This connection is to support the same NOSTUFF R1021 30 26 PP0V75_S3_MEM_VREFDQ_A 1 R1020 1% 1/16W MF-LF 402 NOSTUFF R1023 30 28 PP0V75_S3_MEM_VREFDQ_B 5% 1/16W MF-LF 402 R1022 1K 1% 1/16W MF-LF 402 AD5 RSVD_25 AH5 RSVD_26 AJ6 RSVD_27 NC NC G52 RSVD_38 G64 RSVD_39 NC AJ10 RSVD_40 BI CPU_THERMD_P CPU_THERMD_N BE6 AA4 AC4 AC6 RSVD_53 RSVD_54 RSVD_55 RSVD_56 RSVD_57 RSVD_58 RSVD_59 RSVD_60 RSVD_61 RSVD_62 RSVD_63 RSVD_64 RSVD_65 RSVD_66 RSVD_67 RSVD_68 F5 K9 H5 L10 G4 K7 K5 M9 L6 J2 L2 P7 M5 J4 L4 N6 RSVD_69 RSVD_70 RSVD_71 RSVD_72 G48 K49 H49 J50 RSVD_78 RSVD_79 RSVD_80 RSVD_81 RSVD_82 RSVD_83 RSVD_84 RSVD_85 RSVD_86 RSVD_87 RSVD_88 RSVD_89 RSVD_90 RSVD_91 RSVD_92 RSVD_93 RSVD_94 RSVD_95 RSVD_96 RSVD_97 AY13 BB13 BB15 AY15 AW14 BD13 BA16 BE16 BD15 BC14 BF19 BH19 BF21 BH21 BF23 BH23 BF25 BH25 BJ22 BG22 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC D NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC C RSVD_28 (DDR_VREF0) RSVD_29 (DDR_VREF1) RSVD_30 RSVD_31 RSVD_32 RSVD_33 RSVD_34 D49 RSVD_35 B53 RSVD_36 NC NC NC NC NC BI BF3 BG4 BD19 AY45 AY41 BG62 BB43 NC NC NC 100 51 RSVD_1 RSVD_2 RSVD_3 RSVD_4 RSVD_5 RSVD_6 RSVD_7 RSVD_8 RSVD_9 RSVD_10 RSVD_11 RSVD_12 RSVD_13 RSVD_14 RSVD_15 RSVD_16 RSVD_17 RSVD_18 RSVD_19 RSVD_20 NC NC NC NC NC NC NC 100 51 CFG_5 (IPU) RESERVED CFG_6 (IPU) CFG_7 (IPU) OMIT CFG_8 (IPU) CFG_9 (IPU) CFG_10 (IPU) CFG_11 (IPU) CFG_12 (IPU) CFG_13 (IPU) CFG_14 (IPU) CFG_15 (IPU) CFG_16 (IPU) CFG_17 (IPU) AW50 RSVD_22 BB57 RSVD_23 BF63 RSVD_24 NC NC NC NC NC 1K BB17 AY17 BD29 BD33 BC30 BE32 AW42 BA48 BC42 AW46 BG26 BB25 BG34 BH35 BJ34 BF35 BF41 BH43 BJ42 BF43 CFG_0 (IPU) U1000 CFG_1 (IPU)SANDY-BRIDGE CFG_2 (IPU) MOBILE-REV1 CFG_3 (IPU) BGA CFG_4 (IPU) (5 OF 11) NC NC NC CPU_MEM_VREFDQ_A CPU_MEM_VREFDQ_B 5% 1/16W MF-LF 402 CPU_CFG CPU_CFG CPU_CFG CPU_CFG R1042 R1045 92 92 23 DMI_TX_0 DMI_TX_1 DMI_TX_2 DMI_TX_3 FDI_INT 1% 1/16W MF-LF 402 1% 1/16W MF-LF 402 DMI_TX_0* DMI_TX_1* DMI_TX_2* DMI_TX_3* AD9 IN BGA (SYM OF 11) OMIT FDI_INT AC8 AA2 FDI_FSYNC FDI_FSYNC 10K W6 W10 Y9 AA10 U2 W4 V3 AA6 FDI_DATA_P FDI_DATA_P FDI_DATA_P FDI_DATA_P FDI_DATA_P FDI_DATA_P FDI_DATA_P FDI_DATA_P PP1V05_S0 R1031 V7 W8 AA8 AC10 U4 W2 V1 Y5 PEG_ICOMPI G2 PEG_ICOMPO H1 PEG_RCOMPO F3 SANDY-BRIDGE MOBILE-REV1 DMI_RX_0 DMI_RX_1 DMI_RX_2 DMI_RX_3 IN 102 68 45 39 35 13 12 10 23 14 73 70 105 104 N2 R2 P3 T5 FDI_DATA_N FDI_DATA_N FDI_DATA_N FDI_DATA_N FDI_DATA_N FDI_DATA_N FDI_DATA_N FDI_DATA_N OUT 92 17 N4 R4 P1 U6 DMI_N2S_P DMI_N2S_P DMI_N2S_P DMI_N2S_P OUT 92 17 N8 T9 R6 U8 DMI_N2S_N DMI_N2S_N DMI_N2S_N DMI_N2S_N OUT 92 17 DMI_S2N_P DMI_S2N_P DMI_S2N_P DMI_S2N_P U1000 DMI_RX_0* DMI_RX_1* DMI_RX_2* DMI_RX_3* PCI EXPRESS BASED INTERFACE SIGNALS IN 92 17 N10 R10 R8 U10 DMI 92 17 DMI_S2N_N DMI_S2N_N DMI_S2N_N DMI_S2N_N INTEL FLEXIBLE DISPLAY INTERFACE SIGNALS D IN EMBEDDED DISPLAY PORT 92 17 B RSVD_41 RSVD_42 RSVD_43 RSVD_44 C52 RSVD_45 D3 C4 C24 D25 B25 RSVD_46 RSVD_47 RSVD_48 RSVD_49 RSVD_50 K47 RSVD_51 (THERMDA) H47 RSVD_52 (THERMDC) NOSTUFF1 R1049 1K 5% 1/16W MF-LF 402 A PAGE TITLE CPU DMI/PEG/FDI/RSVD These can be Placed close to J2500 and Only for debug access DRAWING NUMBER Apple Inc FOR SANDYBRIDGE PROCESSOR SIZE D REVISION R CFG CFG CFG CFG CFG [7] :PEG DEFER TRAINING [6:5] :PCIE BIFURCATION [4] :eDP ENABLE/DISABLE [3] :PCIE x4 LANE REVERSAL [2] :PCIE x16 LANE REVERSAL = (DEFAULT) IMMEDIATELY AFTER xxRESETB = WAIT FOR BIOS 11 = X16 (DEFAULT) 10 = X8 01 = RSVD 00 = X8, X4, X4 = DISABLED = ENABLED = NORMAL OPERATION = LANES REVERSED = NORMAL OPERATION = LANES REVERSED NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED BRANCH PAGE 10 OF 132 SHEET OF 105 D D 73 70 68 45 39 35 23 14 13 12 10 105 104 102 PP1V05_S0 PP1V05_S0_CPU_VCCPQE 12 14 R1140 PP1V05_S0 R1100 1K R1101 5% 1/20W MF 201 68 5% 1/16W MF-LF NOSTUFF R1104 R1102 BGA (2 OF 11) OMIT 5% 1/20W MF 5% 1/16W MF-LF 402 201 402 NC 92 17 AH9 PROC_SELECT* CPU_PROC_SEL_L OUT R1103 CPU_PROCHOT_L CPU_CATERR_L H53 CATERR* 92 45 19 BI CPU_PECI F53 PECI CPU_PROCHOT_R_L H51 PROCHOT* OUT PM_THRMTRIP_L F51 THERMTRIP* R11261 75 1% 1/16W MF-LF 402 25 23 IN 92 19 43.2 1% 1/16W MF-LF 402 92 17 IN PM_SYNC K53 PM_SYNC 92 23 19 IN CPU_PWRGD C60 UNCOREPWRGOOD PP1V5_S3RS0_CPUDDR 29 BE24 SM_DRAMRST* PLACE_NEAR=R1121.2:1mm BJ44 SM_VREF CPU_DDR_VREF R1120 1% 1/16W MF-LF 402 B IN R1121 PM_MEM_PWRGD R1120 and R1121 are Intel recommended 130 BCLK D5 BCLK* C6 (IPD) (IPU) ITPCPU_CLK100M_P ITPCPU_CLK100M_N IN 16 92 IN 16 92 DMI_CLK100M_CPU_P DMI_CLK100M_CPU_N IN 16 92 IN 16 92 J62 H65 XDP_CPU_PRDY_L XDP_CPU_PREQ_L TCK J58 TMS H59 H63 XDP_CPU_TCK XDP_CPU_TMS XDP_CPU_TRST_L TDI K61 TDO K59 XDP_CPU_TDI XDP_CPU_TDO XDP_DBRESET_L OUT 23 25 92 DBR* H61 (IPU) BPM_0* (IPU) BPM_1* (IPU) BPM_2* (IPU) BPM_3* (IPU) BPM_4* (IPU) BPM_5* (IPU) BPM_6* (IPU) BPM_7* C62 D61 E62 F63 D59 F61 F59 G60 XDP_BPM_L XDP_BPM_L XDP_BPM_L XDP_BPM_L XDP_BPM_L XDP_BPM_L XDP_BPM_L XDP_BPM_L OUT 23 92 IN 23 92 IN 23 92 IN 23 92 IN 23 92 IN 23 92 OUT 23 92 BI 23 92 BI 23 92 BI 23 92 BI 23 92 BI 23 92 BI 23 92 BI 23 92 BI 23 92 C R1141 1K 1 1% 1/16W values MF-LF 402 PLACE_NEAR=U1000.AY25:51.562mm R1112 104 73 29 15 13 10 BJ46 SM_RCOMP_0 BG46 SM_RCOMP_1 BF45 SM_RCOMP_2 CPU_SM_RCOMP CPU_SM_RCOMP CPU_SM_RCOMP 200 Unused eDP CLK (IPU) TRST* AY25 SM_DRAMPWROK CPU_MEM_RESET_L OUT DPLL_REF_CLK DPLL_REF_CLK_L BCLK_ITP K63 BCLK_ITP* K65 (IPU) K51 RESET* PLT_RESET_LS1V1_L PM_MEM_PWRGD_R 92 29 17 DPLL_REF_CLK AJ4 DPLL_REF_CLK* AJ2 (IPU) PREQ* R1125 PLT_RST_CPU_BUF_L 104 73 29 15 13 10 5% 1/16W MF-LF 402 (IPU) PRDY* 5% 1/16W MF-LF 402 PP1V05_S0 OUT JTAG & BPM 73 70 68 45 39 35 23 14 13 12 10 105 104 102 BI 92 PWR MGMT 92 68 46 56 B59 PROC_DETECT* THERMAL C 1K SANDY-BRIDGE MOBILE-REV1 1K 51 NOSTUFF CLOCKS NOSTUFF U1000 DDR3 MISC 73 70 68 45 39 35 23 14 13 12 10 105 104 102 R1113 R1114 R1111 140 25.5 200 10K 1% 1/16W MF-LF 402 1% 1/16W MF-LF 402 1% PLACE_NEAR=U1000.BF45:12.7mm 1/16W MF-LF 402 5% 1/16W MF-LF 402 2 5% 1/16W MF-LF 402 PLACE_NEAR=U1800.AY11:157mm B PP1V5_S3RS0_CPUDDR R11301 PLACE_NEAR=U1000.BG46:12.7mm NOSTUFF 100 PLACE_NEAR=U1000.BJ44:2.54mm 1% 1/16W MF-LF 402 PLACE_NEAR=U1000.BJ46:12.7mm NOSTUFF R11311 PLACE_NEAR=U1000.BJ44:2.54mm 100 1% 1/16W MF-LF 402 C1130 0.1UF 10% NOSTUFF 16V X5R 402 PLACE_NEAR=U1000.BJ44:2.54mm A A PAGE TITLE CPU CLOCK/MISC/JTAG DRAWING NUMBER Apple Inc SIZE D REVISION R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED BRANCH PAGE 11 OF 132 SHEET 10 OF 105 GPU Rail Sequencing 91 88 72 P3V3GPU_EN 91 88 72 GPUVCORE_EN 91 88 82 P1V0GPU_EN 91 88 87 P3V3GPU_EN 71 56 48 46 29 25 24 23 22 20 19 17 104 102 100 86 83 73 91 89 88 85 84 46 41 40 39 36 35 32 28 26 25 23 12 83 80 73 72 62 61 57 54 52 51 50 49 102 P3V3GPU_EN GPUVCORE_EN GPUVCORE_EN MAKE_BASE=TRUE 91 88 87 P1V0GPU_EN OUT 72 88 91 OUT 82 88 91 OUT 87 88 91 P1V0GPU_EN MAKE_BASE=TRUE P1V5FB1V8GPU_R_EN 91 88 P1V5FB1V8GPU_R_EN MAKE_BASE=TRUE P1V5FB_EN P1V5FB_EN MAKE_BASE=TRUE 5% 1/16W MF-LF 402 R9932 91 87 91 72 P1V8GPU_EN 0.47UF 0.1UF 20% 10V CERM 402 IN 74LVC2G08GT ALL_SYS_PWRGD SOT833 A U9950Y CPUIMVP_PGOOD B PM_S0_PGOOD 08 74LVC2G08GT P1V8GPU_EN OUT U9950Y 72 91 R9962 SOT833 A B C9931 SYS_PWROK_R 1K PM_PCH_SYS_PWROK OUT 17 23 5% 1/16W MF-LF 402 08 0.47UF 10% 6.3V CERM-X5R 402 68 87 91 5% 1/16W MF-LF 402 C9950 C9932 PLACE_NEAR=U7880.2:7mm PLACE_NEAR=U1800.p12:7mm MAKE_BASE=TRUE 5% 1/16W MF-LF 402 OUT IN 1K 88 73 45 23 48 100 R9963 5% 1/16W MF-LF 402 R9931 72 PP3V3_S5 PP3V3_S0 R99501 PLACE_NEAR=U9500.27:7mm 91 88 D NO STUFF MAKE_BASE=TRUE 91 88 82 PCH S0 PWRGD Whistler GPU requires rails to come up in the following order: 1) GPU_3.3V 2) GPUVcore 3) GPU_1.0V 4) GPU_1.8V;GDDR5 1.5/1.35V D 2 NO STUFF 10% 6.3V CERM-X5R 402 SMC_DELAYED_PWRGD NO STUFF 45 35 PLACE_NEAR=U1800.L22:5.54mm NO STUFF R9961 5% 1/16W MF-LF 402 C C PM_PCH_PWROK MAKE_BASE=TRUE R9960 OUT PM_PCH_PWROK 17 91 17 91 5% 1/16W MF-LF 402 EXT GPU PWRGD Pullup Unused PGOOD signal PP3V3_S0 102 100 91 89 88 85 84 46 41 40 39 36 35 32 28 26 25 23 12 83 80 73 72 62 61 57 54 52 51 50 49 48 B B R99901 100K 5% 1/16W MF-LF 4022 102 100 91 89 88 85 84 46 41 40 39 36 35 32 28 26 25 23 12 83 80 73 72 62 61 57 54 52 51 50 49 48 PP3V3_S0 NO STUFF PLACE_NEAR=U8000.AH16:7mm R99911 10K 91 88 87 82 74 IN PM_ALL_GPU_PGOOD 91 88 87 82 74 IN PM_ALL_GPU_PGOOD 91 88 87 82 74 IN PM_ALL_GPU_PGOOD 5% 1/16W MF-LF 402 OUT CPUIMVP_AXG_PGOOD IN TP_DDRREG_PGOOD IN 67 91 TP_P1V5S3RS0_RAMP_DONE IN 72 91 74 82 87 88 91 91 67 PM_ALL_GPU_PGOOD TP_DDRREG_PGOOD MAKE_BASE=TRUE MAKE_BASE=TRUE 91 72 TP_P1V5S3RS0_RAMP_DONE MAKE_BASE=TRUE A 68 SYNC_MASTER=K92_YUAN SYNC_DATE=07/30/2010 PAGE TITLE Power Sequencing EG/PCH S0 DRAWING NUMBER Apple Inc SIZE D REVISION R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED BRANCH PAGE 99 OF 132 SHEET 91 OF 105 A CPU Signal Constraints CPU Net Properties TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP CPU_50S * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD CPU_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD ELECTRICAL_CONSTRAINT_SET NET_TYPE SPACING PHYSICAL TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM CPU_27P4S * =27P4_OHM_SE =27P4_OHM_SE =27P4_OHM_SE =27P4_OHM_SE MIL MIL NOTE: mil gap is for VCCSense pair, which Intel says to route with mil spacing without specifying a target impedance TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT =STANDARD ? TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT =2x_DIELECTRIC ? TABLE_SPACING_RULE_ITEM D CPU_AGTL * * PCIE PCIE PCIE PCIE DMI_S2N_P DMI_S2N_N DMI_N2S_P DMI_N2S_N FDI_DATA FDI_DATA PCIE_85D PCIE_85D CPU_50S CPU_50S PCIE PCIE CPU_AGTL CPU_AGTL FDI_DATA_P FDI_DATA_N FDI_FSYNC FDI_LSYNC TOP,BOTTOM CLK_PCIE_90D CLK_PCIE_90D CLK_PCIE CLK_PCIE DMI_CLK100M_CPU_P DMI_CLK100M_CPU_N CPU_VID * ? 0.457 MM I125 CPU_PECI PM_SYNC PM_MEM_PWRGD CPU_50S CPU_50S CPU_50S CPU_50S CPU_AGTL PCIE CPU_AGTL CPU_AGTL FDI_INT CPU_PECI PM_SYNC PM_MEM_PWRGD XDP_CPU_PWRGOOD XDP_BDRESET_L XDP_PRDY_L XDP_PREQ_l CPU_50S CPU_50S CPU_50S CPU_50S CPU_ITP CPU_ITP CPU_ITP CPU_ITP XDP_CPU_PWRGD XDP_DBRESET_L XDP_CPU_PRDY_L XDP_CPU_PREQ_L CPU_SM_RCOMP CPU_SM_RCOMP CPU_SM_RCOMP CPU_CFG CPU_CFG CPU_CATERR_L CPU_27P4S CPU_27P4S CPU_27P4S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_COMP CPU_COMP CPU_COMP CPU_ITP CPU_ITP CPU_AGTL CPU_AGTL CPU_AGTL CPU_AGTL CPU_AGTL CPU_8MIL CPU_SM_RCOMP0 CPU_SM_RCOMP1 CPU_SM_RCOMP2 CPU_CFG CPU_CFG CPU_CATERR_L CPU_PROC_SEL_L TP_CPU_VTT_SELECT CPU_PROCHOT_L CPU_PWRGD PM_THRMTRIP_L CLK_PCIE_90D CLK_PCIE_90D CLK_PCIE_90D CLK_PCIE_90D CLK_PCIE_90D CLK_PCIE_90D CPU_55S CPU_50S CPU_27P4S CPU_27P4S CPU_27P4S CPU_27P4S CPU_27P4S CPU_27P4S CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CPU_8MIL CPU_AGTL CPU_COMP CPU_COMP CPU_COMP CPU_COMP CPU_COMP CPU_COMP ITPCPU_CLK100M_P ITPCPU_CLK100M_N ITPXDP_CLK100M_P ITPXDP_CLK100M_N XDP_CPU_CLK100M_P XDP_CPU_CLK100M_N CPU_PSI_L PM_DPRSLPVR CPU_PEG_COMP CPU_PEG_RBIAS CPU_COMP3 CPU_COMP2 CPU_COMP1 CPU_COMP0 CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_ITP CPU_ITP CPU_ITP CPU_ITP CPU_ITP CPU_ITP CPU_ITP CPU_ITP XDP_CPU_TDI XDP_CPU_TDO XDP_CPU_TMS XDP_CPU_TCK XDP_CPU_TRST_L XDP_BPM_L XDP_BPM_L XDP_CPURST_L CPU_55S CPU_50S CPU_8MIL CPU_AGTL CPU_VID CPUIMVP_IMON CPU_VCCSENSE CPU_VCCSENSE CPU_VCCSENSE CPU_VCCSENSE CPU_27P4S CPU_27P4S CPU_27P4S CPU_27P4S CPU_VCCSENSE CPU_VCCSENSE CPU_VCCSENSE CPU_VCCSENSE CPU_VCCSENSE_P CPU_VCCSENSE_N CPU_VCCIOSENSE_P CPU_VCCIOSENSE_N CPU_VCCSENSE CPU_VCCSENSE CPU_27P4S CPU_27P4S CPU_27P4S CPU_27P4S CPU_27P4S CPU_27P4S CPU_VCCSENSE CPU_VCCSENSE CPU_VCCSENSE CPU_VCCSENSE CPU_VCCSENSE CPU_VCCSENSE CPU_AXG_SENSE_P CPU_AXG_SENSE_N CPU_VCC_VALSENSE_P CPU_VCC_VALSENSE_N CPU_AXG_VALSENSE_P CPU_AXG_VALSENSE_N DMI_CLK100M TABLE_SPACING_RULE_ITEM CPU_COMP * 20 MIL ? CPU_ITP * =2:1_SPACING ? CPU_VCCSENSE * 25 MIL ? 17 17 17 17 17 17 17 D 17 TABLE_SPACING_RULE_ITEM ? MIL PCIE_85D PCIE_85D PCIE_85D PCIE_85D TABLE_SPACING_RULE_ITEM CPU_AGTL TABLE_SPACING_RULE_ITEM CPU_8MIL DMI_S2N DMI_S2N DMI_N2S DMI_N2S I126 10 16 10 16 TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM Most CPU signals with impedance requirements are 50-ohm single-ended Some signals require 27.4-ohm single-ended impedance SOURCE: Calpella SFF DG (DG-407364_v1.5), Section 2.8 PCI-Express TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 17 10 19 45 10 17 10 17 29 23 10 23 25 10 23 10 23 TABLE_PHYSICAL_RULE_ITEM PCIE_85D * =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF CLK_PCIE_90D * =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF SPACING_RULE_SET LAYER TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_HEAD LINE-TO-LINE SPACING WEIGHT =3X_DIELECTRIC ? TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT =4X_DIELECTRIC ? TABLE_SPACING_RULE_ITEM PCIE * I124 TABLE_SPACING_RULE_ITEM PCIE TOP,BOTTOM TABLE_SPACING_RULE_ITEM CLK_PCIE * 20 MIL I115 ? CPU_PROCHOT_L CPU_PWRGD PM_THRMTRIP_L C XDP_CLK_CPU XDP_CLK_CPU XDP_CLK_PCH XDP_CLK_PCH XDP_CLK_ITP XDP_CLK_ITP PM_DPRSLPVR CPU_COMP CPU_COMP CPU_COMP CPU_COMP XDP_TDI XDP_TDO XDP_TMS XDP_TCK XDP_TRST_L XDP_BPM XDP_BPM_L (FSB_CPURST_L) 23 23 10 10 17 10 46 68 10 19 23 10 19 C 10 16 10 16 16 23 16 23 23 23 10 23 10 23 10 23 10 23 10 23 10 23 10 23 23 B B I120 I121 I122 I123 PM_DPRSLPVR PEG_R2D PEG_D2R A CPU_55S CPU_50S CPU_50S CPU_50S CPU_8MIL CPU_AGTL CPU_AGTL CPU_AGTL GFX_VID GFX_DPRSLPVR GFX_VR_EN GFXIMVP_IMON PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE_85D CPU_50S CPU_50S CPU_50S PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE CPU_VID CPU_VID CPU_VID PEG_R2D_P PEG_R2D_N PEG_R2D_C_P PEG_R2D_C_N PEG_D2R_P PEG_D2R_N PEG_D2R_C_P PEG_D2R_C_N CPU_VIDSOUT CPU_VIDSCLK CPU_VIDALERT_L 12 68 12 68 12 70 12 70 12 68 12 68 12 12 12 12 74 74 74 74 74 74 74 74 12 68 12 68 SYNC_MASTER=K91_MLB SYNC_DATE=07/22/2010 PAGE TITLE CPU Constraints 12 68 DRAWING NUMBER Apple Inc SIZE D REVISION R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED BRANCH PAGE 100 OF 132 SHEET 92 OF 105 A Memory Bus Constraints Memory Net Properties TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP MEM_37S * =37_OHM_SE =37_OHM_SE =37_OHM_SE =37_OHM_SE =STANDARD =STANDARD MEM_40S * =40_OHM_SE =40_OHM_SE =40_OHM_SE =40_OHM_SE =STANDARD =STANDARD ELECTRICAL_CONSTRAINT_SET NET_TYPE PHYSICAL SPACING TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM MEM_A_CLK MEM_A_CLK MEM_72D MEM_72D MEM_CLK MEM_CLK MEM_A_CLK_P MEM_A_CLK_N MEM_A_CNTL MEM_A_CNTL MEM_A_CNTL MEM_37S MEM_37S MEM_37S MEM_CTRL MEM_CTRL MEM_CTRL MEM_A_CKE MEM_A_CS_L MEM_A_ODT MEM_A_CMD MEM_A_CMD MEM_A_CMD MEM_A_CMD MEM_A_CMD MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_CMD MEM_CMD MEM_CMD MEM_CMD MEM_CMD MEM_A_A MEM_A_BA MEM_A_RAS_L MEM_A_CAS_L MEM_A_WE_L MEM_A_DQ_BYTE0 MEM_A_DQ_BYTE1 MEM_A_DQ_BYTE2 MEM_A_DQ_BYTE3 MEM_A_DQ_BYTE4 MEM_A_DQ_BYTE5 MEM_A_DQ_BYTE6 MEM_A_DQ_BYTE7 MEM_50S MEM_50S MEM_50S MEM_50S MEM_50S MEM_50S MEM_50S MEM_50S MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQS0 MEM_A_DQS0 MEM_A_DQS1 MEM_A_DQS1 MEM_A_DQS2 MEM_A_DQS2 MEM_A_DQS3 MEM_A_DQS3 MEM_A_DQS4 MEM_A_DQS4 MEM_A_DQS5 MEM_A_DQS5 MEM_A_DQS6 MEM_A_DQS6 MEM_A_DQS7 MEM_A_DQS7 MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_B_CLK MEM_B_CLK MEM_72D MEM_72D MEM_CLK MEM_CLK MEM_B_CLK_P MEM_B_CLK_N MEM_B_CNTL MEM_B_CNTL MEM_B_CNTL MEM_37S MEM_37S MEM_37S MEM_CTRL MEM_CTRL MEM_CTRL MEM_B_CKE MEM_B_CS_L MEM_B_ODT MEM_B_CMD MEM_B_CMD MEM_B_CMD MEM_B_CMD MEM_B_CMD MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_CMD MEM_CMD MEM_CMD MEM_CMD MEM_CMD MEM_B_A MEM_B_BA MEM_B_RAS_L MEM_B_CAS_L MEM_B_WE_L MEM_B_DQ_BYTE0 MEM_B_DQ_BYTE1 MEM_B_DQ_BYTE2 MEM_B_DQ_BYTE3 MEM_B_DQ_BYTE4 MEM_B_DQ_BYTE5 MEM_B_DQ_BYTE6 MEM_B_DQ_BYTE7 MEM_50S MEM_50S MEM_50S MEM_50S MEM_50S MEM_50S MEM_50S MEM_50S MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQS0 MEM_B_DQS0 MEM_B_DQS1 MEM_B_DQS1 MEM_B_DQS2 MEM_B_DQS2 MEM_B_DQS3 MEM_B_DQS3 MEM_B_DQS4 MEM_B_DQS4 MEM_B_DQS5 MEM_B_DQS5 MEM_B_DQS6 MEM_B_DQS6 MEM_B_DQS7 MEM_B_DQS7 MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N 11 26 11 26 TABLE_PHYSICAL_RULE_ITEM MEM_72D * =72_OHM_DIFF =72_OHM_DIFF =72_OHM_DIFF =72_OHM_DIFF =72_OHM_DIFF =72_OHM_DIFF MEM_50S * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD TABLE_PHYSICAL_RULE_ITEM 11 26 11 26 11 26 TABLE_PHYSICAL_RULE_ITEM D MEM_85D * SPACING_RULE_SET LAYER =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF TABLE_SPACING_RULE_HEAD LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM MEM_CLK2MEM * ? =4:1_SPACING 11 26 11 26 D 11 26 11 26 11 26 TABLE_SPACING_RULE_ITEM MEM_CTRL2CTRL * =3:1_SPACING ? MEM_CTRL2MEM * =2.5:1_SPACING ? TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM MEM_CMD2CMD * =1.5:1_SPACING ? TABLE_SPACING_RULE_ITEM MEM_CMD2MEM * ? =3:1_SPACING TABLE_SPACING_RULE_ITEM MEM_DATA2DATA * =1.5:1_SPACING ? MEM_DATA2MEM * =3:1_SPACING ? TABLE_SPACING_RULE_ITEM 11 27 11 27 11 27 11 27 11 26 27 11 27 11 27 11 27 TABLE_SPACING_RULE_ITEM MEM_DQS2MEM * =3:1_SPACING ? MEM_2OTHER * 25 MILS ? TABLE_SPACING_RULE_ITEM Memory Bus Spacing Group Assignments TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET MEM_CMD MEM_CLK * MEM_CMD2MEM MEM_CMD MEM_CTRL * MEM_CMD2MEM MEM_CMD MEM_CMD * MEM_CMD2CMD MEM_CMD MEM_DATA * MEM_CMD2MEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CLK MEM_CLK * MEM_CLK2MEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CLK MEM_CTRL * MEM_CLK2MEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CLK MEM_CMD * MEM_CLK2MEM MEM_CLK MEM_DATA * MEM_CLK2MEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CLK MEM_DQS * MEM_CLK2MEM NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET C TABLE_SPACING_ASSIGNMENT_ITEM MEM_CMD MEM_DQS * MEM_CMD2MEM NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET TABLE_SPACING_ASSIGNMENT_HEAD TABLE_SPACING_ASSIGNMENT_HEAD TABLE_SPACING_ASSIGNMENT_ITEM MEM_CTRL MEM_CLK * MEM_CTRL2MEM MEM_CTRL MEM_CTRL * MEM_CTRL2CTRL TABLE_SPACING_ASSIGNMENT_ITEM MEM_DATA MEM_CLK * MEM_DATA2MEM MEM_DATA MEM_CTRL * MEM_DATA2MEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CTRL MEM_CMD * MEM_CTRL2MEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_DATA MEM_CMD * MEM_DATA2MEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CTRL MEM_DATA * MEM_CTRL2MEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_DATA MEM_DATA * MEM_DATA2DATA TABLE_SPACING_ASSIGNMENT_ITEM MEM_CTRL MEM_DQS * MEM_CTRL2MEM NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET MEM_DQS MEM_CLK * MEM_DQS2MEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_DATA MEM_DQS * MEM_DATA2MEM NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET MEM_CLK * * MEM_2OTHER TABLE_SPACING_ASSIGNMENT_HEAD TABLE_SPACING_ASSIGNMENT_HEAD TABLE_SPACING_ASSIGNMENT_ITEM MEM_CTRL * MEM_DQS2MEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CTRL * * MEM_2OTHER TABLE_SPACING_ASSIGNMENT_ITEM MEM_DQS MEM_CMD * MEM_DQS2MEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CMD * * MEM_2OTHER TABLE_SPACING_ASSIGNMENT_ITEM MEM_DQS MEM_DATA * MEM_DQS2MEM MEM_DQS MEM_DQS * MEM_DQS2MEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_DATA * * MEM_2OTHER MEM_DQS * * MEM_2OTHER TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM Need to support MEM_*-style wildcards! DDR3: B 11 26 27 11 27 11 27 11 27 11 27 C 11 27 11 27 11 27 11 27 11 27 11 27 11 27 11 27 11 27 11 27 11 28 11 28 TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_DQS 11 27 DQ/DM signals should be matched within 0.508mm of associated DQS pair DQS intra-pair matching should be within 0.127mm, no inter-pair matching requirement DQS to clock matching should be within [CLK-12.7mm] and [CLK+25.4mm] CLK intra-pair matching should be within 0.127mm, inter-pair matching should be within 0.508mm CONTROL signals should be matched within [CLK-12.7mm] to [CLK+0.0mm] of CLK pairs A/BA/CMD signals should be matched within [CLK-12.7mm] to [CLK+12.7mm] of CLK pairs DQ/DQS/A/BA/cmd signal spacing is 4x dielectric, CLK is 5x dielectric Maximum length of any signal from die pad to SODIMM pad is 139.7mm, from procesor ball to SODIMM pad is 114.3mm 11 28 11 28 11 28 11 28 11 28 11 28 11 28 11 28 11 27 11 27 11 27 11 27 B 11 27 28 11 27 11 27 11 27 SOURCE: Calpella SFF Platform DG, Rev 1.5 (#407364), Section 2.2 A 11 27 28 11 27 28 11 27 11 27 11 27 11 27 11 27 11 27 11 27 11 27 11 27 11 27 11 27 11 27 11 27 SYNC_MASTER=K17_MLB SYNC_DATE=05/14/2010 PAGE TITLE Memory Constraints 11 27 DRAWING NUMBER Apple Inc SIZE D REVISION R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED BRANCH PAGE 101 OF 132 SHEET 93 OF 105 A Digital Video Signal Constraints LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP ELECTRICAL_CONSTRAINT_SET TABLE_PHYSICAL_RULE_ITEM DP_85D * =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF LVDS_85D * =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF SPACING_RULE_SET LAYER PCH Net Properties TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET NET_TYPE PHYSICAL SPACING TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_HEAD LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM DISPLAYPORT ISL3,ISL4,ISL9,ISL10 =4:1_SPACING ? LVDS ISL3,ISL4,ISL9,ISL10 =4:1_SPACING ? DISPLAYPORT TOP,BOTTOM =4:1_SPACING ? LVDS TOP,BOTTOM =4:1_SPACING ? TABLE_SPACING_RULE_ITEM D DP_AUX_CH DP_AUX_CH DP_85D DP_85D DISPLAYPORT DISPLAYPORT DP_IG_AUX_CH_P DP_IG_AUX_CH_N LVDS_IG_A_CLK LVDS_IG_A_CLK LVDS_IG_A_DATA LVDS_IG_A_DATA LVDS_IG_A_DATA3 LVDS_IG_A_DATA3 LVDS_85D LVDS_85D LVDS_85D LVDS_85D LVDS_85D LVDS_85D LVDS LVDS LVDS LVDS LVDS LVDS LVDS_IG_A_CLK_P LVDS_IG_A_CLK_N LVDS_IG_A_DATA_P LVDS_IG_A_DATA_N NC_LVDS_IG_A_DATAP NC_LVDS_IG_A_DATAN LVDS_IG_B_DATA LVDS_IG_B_DATA LVDS_85D LVDS_85D LVDS LVDS LVDS_IG_B_DATA_P LVDS_IG_B_DATA_N DP_SATA_G3_R2D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA_HDD_R2D_C_P 16 41 SATA_HDD_R2D_C_N 16 41 SATA_HDD_R2D_P 41 SATA_HDD_R2D_N 41 SATA_HDD_R2D_UF_P 41 SATA_HDD_R2D_UF_N 41 SATA_HDD_R2D_RDRVR_OUT_P 41 SATA_HDD_R2D_RDRVR_OUT_N 41 SATA_HDD_R2D_RDRVR_IN_P 41 SATA_HDD_R2D_RDRVR_IN_N 41 SATA_HDD_R2D_RC_UF_P 41 SATA_HDD_R2D_RC_UF_N 41 SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA SATA SATA SATA SATA SATA SATA SATA SATA_HDD_D2R_P 16 41 SATA_HDD_D2R_N 16 41 SATA_HDD_D2R_RDRVR_OUT_P 41 SATA_HDD_D2R_RDRVR_OUT_N 41 SATA_HDD_D2R_RDRVR_IN_P 41 SATA_HDD_D2R_RDRVR_IN_N 41 SATA_HDD_D2R_C_P 41 SATA_HDD_D2R_C_N 41 SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA SATA SATA SATA SATA SATA SATA_ODD_R2D_C_P SATA_ODD_R2D_C_N SATA_ODD_R2D_P SATA_ODD_R2D_N SATA_ODD_R2D_UF_P SATA_ODD_R2D_UF_N SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA SATA SATA SATA SATA SATA SATA_ODD_D2R_P SATA_ODD_D2R_N SATA_ODD_D2R_C_P SATA_ODD_D2R_C_N SATA_ODD_D2R_UF_P SATA_ODD_D2R_UF_N PCH_SATA3_ICOMP PCH_SATA_ICOMP SATA_50SE SATA_37SE SATA_ICOMP SATA_ICOMP PCH_SATA3COMP PCH_SATAICOMP USB_HUB1_UP USB_85D USB_85D USB_85D USB_85D USB_85D USB_85D USB_85D USB_85D USB_85D USB_85D USB_85D USB_85D USB_85D USB_85D USB_85D USB_85D USB_85D USB_85D PCH_USB_RBIAS USB_85D USB_85D USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB_RBIAS USB USB USB_HUB1_UP_P USB_HUB1_UP_N USB_HUB2_UP_P USB_HUB2_UP_N USB_EXTA_P USB_EXTA_N USB_EXTB_P USB_EXTB_N USB_EXTC_P USB_EXTC_N USB_CAMERA_CONN_P USB_CAMERA_CONN_N USB_BT_P USB_BT_N USB_TPAD_P USB_TPAD_N USB_IR_P USB_IR_N PCH_USB_RBIAS USB_T29A_P USB_T29A_N 17 84 17 84 TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM SOURCE: HR PLATFORM DESIGN GUIDE, TABLES 191,193 SATA Interface Constraints 18 88 18 88 18 88 D 18 88 18 18 18 88 18 88 TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP SATA_90D * =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF SATA_37SE * =37_OHM_SE =37_OHM_SE =37_OHM_SE =37_OHM_SE =37_OHM_SE =37_OHM_SE SATA_50SE * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM SATA_HDD_RDVR_R2D TABLE_PHYSICAL_RULE_ITEM DP_SATA_G3_R2D TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LINE-TO-LINE SPACING WEIGHT SATA ISL3,ISL4,ISL9,ISL10 LAYER =5:1_SPACING ? SATA_ICOMP * 15 MIL ? TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT =5:1_SPACING ? TABLE_SPACING_RULE_ITEM DP_SATA_G3_R2D TABLE_SPACING_RULE_ITEM SATA TOP,BOTTOM DP_SATA_G3_R2D TABLE_SPACING_RULE_ITEM DP_SATA_G3_R2D SOURCE: HR PLATFORM DESIGN GUIDE, TABLES 191,193 SATA_HDD_D2R SATA_HDD_D2R SATA_HDD_D2R C SATA_HDD_RDVR_D2R USB 2.0 Interface Constraints SATA_ODD_R2D TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM PCH_USB_RBIAS * =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD TABLE_PHYSICAL_RULE_ITEM USB_85D * =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT ISL3,ISL4,ISL9,ISL10 =4:1_SPACING SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT SATA_ODD_D2R TABLE_SPACING_RULE_ITEM ? USB TOP,BOTTOM =4:1_SPACING ? SATA_ODD_D2R TABLE_SPACING_RULE_ITEM USB_RBIAS * 15 MIL 16 41 16 41 41 41 41 41 TABLE_SPACING_RULE_HEAD TABLE_SPACING_RULE_ITEM USB SATA_ODD_R2D C ? SATA_ODD_D2R SOURCE: HR PLATFORM DESIGN GUIDE, TABLES 191,193 USB_HUB2_UP USB_EXTA B USB_EXTB USB_EXTC USB_CAMERA USB_BT USB_TPAD USB_IR PCH_USB_RBIAS USB_T29A A 16 41 16 41 41 41 41 41 16 16 18 24 18 24 18 24 18 24 24 42 B 24 42 24 42 24 42 24 43 24 43 31 31 24 31 24 31 24 53 24 53 24 44 24 44 18 24 24 SYNC_MASTER=K92_YUN SYNC_DATE=06/25/2010 PAGE TITLE PCH Constraints DRAWING NUMBER Apple Inc SIZE D REVISION R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED BRANCH PAGE 102 OF 132 SHEET 94 OF 105 A LPC Bus Constraints LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP ELECTRICAL_CONSTRAINT_SET TABLE_PHYSICAL_RULE_ITEM LPC_50S * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD CLK_LPC_50S * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD PCH Net Properties TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET NET_TYPE PHYSICAL SPACING TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT MIL ? TABLE_SPACING_RULE_ITEM LPC * TABLE_SPACING_RULE_ITEM CLK_LPC D * ? MIL SMBus Interface Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM SMB_50S * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD LPC_AD LPC_FRAME_L LPC_RESET_L LPC_50S LPC_50S LPC_50S LPC LPC LPC LPC_AD LPC_FRAME_L LPCPLUS_RESET_L PCH_LPC_CLK0 PCH_LPC_CLK0 PCH_LPC_CLK0 CLK_LPC_50S CLK_LPC_50S CLK_LPC_50S CLK_LPC CLK_LPC CLK_LPC LPC_CLK33M_SMC_R LPC_CLK33M_SMC LPC_CLK33M_LPCPLUS SMBUS_PCH_CLK SMBUS_PCH_DATA SMBUS_PCH_0_CLK SMBUS_PCH_0_DATA SMBUS_PCH_1_CLK SMBUS_PCH_1_DATA SMB_50S SMB_50S SMB_50S SMB_50S SMB_50S SMB_50S SMB SMB SMB SMB SMB SMB SMBUS_PCH_CLK SMBUS_PCH_DATA SML_PCH_0_CLK SML_PCH_0_DATA SML_PCH_1_CLK SML_PCH_1_DATA HDA_BIT_CLK HDA_50S HDA_50S HDA_50S HDA_50S HDA_50S HDA_50S HDA_50S HDA_50S HDA_50S HDA_50S HDA HDA HDA HDA HDA HDA HDA HDA HDA HDA HDA_BIT_CLK HDA_BIT_CLK_R HDA_SYNC HDA_SYNC_R HDA_RST_R_L HDA_RST_L HDA_SDIN0 AUD_SDI_R HDA_SDOUT HDA_SDOUT_R SPI_CLK SPI_CLK SPI_MOSI SPI_MOSI SPI_MISO SPI_CS0 SPI_55S SPI_55S SPI_55S SPI_55S SPI_55S SPI_55S SPI_55S SPI SPI SPI SPI SPI SPI SPI SPI_CLK_R SPI_CLK SPI_MOSI_R SPI_MOSI SPI_MISO SPI_CS0_R_L SPI_CS0_L PCIE_ENET_R2D PCIE_ENET_R2D PCIE_ENET_R2D PCIE_ENET_R2D PCIE_ENET_D2R PCIE_ENET_D2R PCIE_ENET_D2R PCIE_ENET_D2R PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE_ENET_R2D_P PCIE_ENET_R2D_N PCIE_ENET_R2D_C_P PCIE_ENET_R2D_C_N PCIE_ENET_D2R_P PCIE_ENET_D2R_N PCIE_ENET_D2R_C_P PCIE_ENET_D2R_C_N PCIE_AP_R2D PCIE_AP_R2D PCIE_AP_R2D PCIE_AP_R2D PCIE_AP_D2R PCIE_AP_D2R PCIE_AP_D2R PCIE_AP_D2R PCIE_AP_R2D PCIE_AP_R2D PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE_AP_R2D_P PCIE_AP_R2D_N PCIE_AP_R2D_C_P PCIE_AP_R2D_C_N PCIE_AP_D2R_P PCIE_AP_D2R_N PCIE_AP_D2R_PI_P PCIE_AP_D2R_PI_N PCIE_AP_R2D_PI_P PCIE_AP_R2D_PI_N PCIE_FW_R2D PCIE_FW_R2D PCIE_FW_R2D PCIE_FW_R2D PCIE_FW_D2R PCIE_FW_D2R PCIE_FW_D2R PCIE_FW_D2R PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE_FW_R2D_P PCIE_FW_R2D_N PCIE_FW_R2D_C_P PCIE_FW_R2D_C_N PCIE_FW_D2R_P PCIE_FW_D2R_N PCIE_FW_D2R_C_P PCIE_FW_D2R_C_N CLK_PCIE_90D CLK_PCIE_90D CLK_PCIE_90D CLK_PCIE_90D CLK_PCIE_90D CLK_PCIE_90D CLK_PCIE_90D CLK_PCIE_90D CPU_50S CPU_50S CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE PCIE_CLK100M_PCH_P PCIE_CLK100M_PCH_N PCIE_CLK100M_T29_P PCIE_CLK100M_T29_N PCH_CLK96M_DOT_P PCH_CLK96M_DOT_N PCH_CLK100M_SATA_P PCH_CLK100M_SATA_N PCH_CLK14P3M_REFCLK PCH_CLK33M_PCIIN CLK_PCIE_90D CLK_PCIE_90D CLK_PCIE_90D CLK_PCIE_90D CLK_PCIE_90D CLK_PCIE_90D CLK_PCIE_90D CLK_PCIE_90D CLK_PCIE_90D CLK_PCIE_90D CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE PEG_CLK100M_P PEG_CLK100M_N PCIE_CLK100M_ENET_P PCIE_CLK100M_ENET_N PCIE_CLK100M_AP_P PCIE_CLK100M_AP_N PCIE_CLK100M_FW_P PCIE_CLK100M_FW_N PCIE_CLK100M_EXCARD_P PCIE_CLK100M_EXCARD_N PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE_T29_R2D_C_P PCIE_T29_R2D_C_N PCIE_T29_R2D_P PCIE_T29_R2D_N PCIE_T29_D2R_P PCIE_T29_D2R_N PCIE_T29_D2R_C_P PCIE_T29_D2R_C_N TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT HDA_SYNC TABLE_SPACING_RULE_ITEM SMB * =2x_DIELECTRIC ? HDA_RST_L HD Audio Interface Constraints HDA_SDIN0 TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP HDA_SDOUT TABLE_PHYSICAL_RULE_ITEM HDA_50S * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD 16 45 47 88 16 45 47 88 25 47 88 18 25 25 45 25 47 D 16 23 26 28 30 32 41 48 62 89 16 23 26 28 30 32 41 48 62 89 16 48 16 48 16 48 16 48 16 57 16 16 57 16 16 16 57 16 57 57 16 57 16 TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT =2x_DIELECTRIC ? TABLE_SPACING_RULE_ITEM HDA * SIO Signal Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 16 47 47 16 47 47 16 47 16 47 47 TABLE_PHYSICAL_RULE_ITEM C CLK_SLOW_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM CLK_SLOW * ? MIL SPI Interface Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP SPI_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM SPI * MIL ? B I253 I254 I262 I261 PCIE_CLK100M PCIE_CLK100M PCIE_CLK100M_T29_ PCIE_CLK100M_T29_ I255 I257 I256 I259 PCIE_CLK100M PCIE_CLK100M I258 I260 PCIE_CLK100M PCIE_CLK100M_ENET PCIE_CLK100M_AP PCIE_CLK100M_FW PCIE_CLK100M_EXCARD A I263 I264 I265 I267 I266 I268 I270 I269 PCIE_T29_R2D PCIE_T29_R2D PCIE_T29_R2D PCIE_T29_R2D PCIE_T29_D2R PCIE_T29_D2R PCIE_T29_D2R PCIE_T29_D2R 36 C 36 16 36 16 36 16 36 16 36 36 36 31 31 16 31 16 31 16 31 16 31 31 31 31 31 38 38 16 38 16 38 16 38 16 38 38 B 38 16 16 16 33 16 33 16 16 16 16 16 16 25 16 74 16 74 16 36 16 36 16 31 16 31 16 38 16 38 16 32 16 32 33 33 33 SYNC_MASTER=K91_MLB SYNC_DATE=07/22/2010 PAGE TITLE PCH Constraints 33 DRAWING NUMBER 33 33 Apple Inc 33 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED D R 33 NOTICE OF PROPRIETARY PROPERTY: SIZE REVISION BRANCH PAGE 103 OF 132 SHEET 95 OF 105 A CAESAR II (Ethernet) Constraints Ethernet Net Properties NET_TYPE PHYSICAL SPACING TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP ENET_50S * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD ELECTRICAL_CONSTRAINT_SET TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT =3:1_SPACING ? ENET_50S ENET_50S ENET_50S ENET_3X ENET_3X ENET_3X BCM5764_CLK25M_XTALI BCM5764_CLK25M_XTALO ENET_RESET_L ENET_100D ENET_100D ENET_MDI ENET_MDI ENET_MDI_P ENET_MDI_N 32 36 TABLE_SPACING_RULE_ITEM ENET_3X * ENET_MDI SOURCE: Broadcom 5764-DS04-RDS Page 38 D 36 37 36 37 CAESAR II (Ethernet PHY) Constraints D TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP ENET_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF SPACING_RULE_SET LAYER TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_HEAD LINE-TO-LINE SPACING WEIGHT 0.6 MM ? TABLE_SPACING_RULE_ITEM ENET_MDI * SOURCE: Broadcom 5764-DS04-RDS Page 38 FireWire Interface Constraints FireWire Net Properties NET_TYPE SPACING PHYSICAL TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP FW_110D * =110_OHM_DIFF =110_OHM_DIFF =110_OHM_DIFF =110_OHM_DIFF =110_OHM_DIFF =110_OHM_DIFF SPACING_RULE_SET LAYER ELECTRICAL_CONSTRAINT_SET TABLE_PHYSICAL_RULE_ITEM I162 I163 TABLE_SPACING_RULE_HEAD LINE-TO-LINE SPACING WEIGHT I164 TABLE_SPACING_RULE_ITEM FW_TP * =3:1_SPACING I165 ? FW_P1_TPA FW_P1_TPA FW_P1_TPB FW_P1_TPB FW_110D FW_110D FW_110D FW_110D FW_TP FW_TP FW_TP FW_TP FW_PORT1_TPA_P FW_PORT1_TPA_N FW_PORT1_TPB_P FW_PORT1_TPB_N 38 40 38 40 38 40 38 40 C C Port and Not Used B B A SYNC_MASTER=K91_MLB SYNC_DATE=07/22/2010 PAGE TITLE Ethernet/FW Constraints DRAWING NUMBER Apple Inc SIZE D REVISION R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED BRANCH PAGE 104 OF 132 SHEET 96 OF 105 A DisplayPort Signal Constraints ELECTRICAL_CONSTRAINT_SET T29 I2C Signal Constraints T29_R2D0 T29_R2D0 T29_R2D1 T29_R2D1 TABLE_PHYSICAL_RULE_HEAD LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM T29_I2C_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =55_OHM_SE =STANDARD TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT =2x_DIELECTRIC ? T29_D2R0 T29_D2R0 T29_D2R1 T29_D2R1 TABLE_SPACING_RULE_ITEM T29_I2C * T29/DP Net Properties NOTE: DisplayPort Physical/Spacing Constraints provided by Chipset or GPU page PHYSICAL_RULE_SET D T29 SPI Signal Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP T29_SPI_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD SPACING_RULE_SET LAYER NET_TYPE SPACING PHYSICAL T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_100D T29DP_100D T29DP_100D T29DP_100D T29DP_100D T29DP_100D T29DP T29DP T29DP T29DP T29DP T29DP T29DP T29DP T29DP T29DP T29DP T29DP T29_R2D_P T29_R2D_N T29_R2D_P T29_R2D_N T29_R2D_C_F_P T29_R2D_C_F_N T29_D2R_C_P T29_D2R_C_N T29_D2R_C_P T29_D2R_C_N T29DPA_D2R1_AUXCH_P T29DPA_D2R1_AUXCH_N T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP T29DP T29DP T29DP T29DP T29DP T29DP T29DP T29DP T29DP T29DP T29DP DP_SDRVA_ML_C_P DP_SDRVA_ML_C_N DP_SDRVA_ML_R_P DP_SDRVA_ML_R_N DP_SDRVA_ML_P DP_SDRVA_ML_N DP_SDRVA_ML_P DP_SDRVA_ML_N DP_SDRVA_AUXCH_P DP_SDRVA_AUXCH_N DP_SDRVA_AUXCH_C_P DP_SDRVA_AUXCH_C_N T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP T29DP T29DP T29DP T29DP T29DP T29DPA_ML_P T29DPA_ML_N T29DPA_ML_C_P T29DPA_ML_C_N DP_A_EXT_AUXCH_P DP_A_EXT_AUXCH_N T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_100D T29DP_100D T29DP_100D T29DP_100D T29DP_100D T29DP_100D T29DP T29DP T29DP T29DP T29DP T29DP T29DP T29DP T29DP T29DP T29DP T29DP T29_R2D_P T29_R2D_N T29_R2D_P T29_R2D_N T29_R2D_C_F_P T29_R2D_C_F_N T29_D2R_C_P T29_D2R_C_N T29_D2R_C_P T29_D2R_C_N T29DPB_D2R3_AUXCH_P T29DPB_D2R3_AUXCH_N T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP T29DP T29DP T29DP T29DP T29DP T29DP T29DP T29DP T29DP T29DP T29DP DP_SDRVB_ML_C_P DP_SDRVB_ML_C_N DP_SDRVB_ML_R_P DP_SDRVB_ML_R_N DP_SDRVB_ML_P DP_SDRVB_ML_N DP_SDRVB_ML_P DP_SDRVB_ML_N DP_SDRVB_AUXCH_P DP_SDRVB_AUXCH_N DP_SDRVB_AUXCH_C_P DP_SDRVB_AUXCH_C_N T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP T29DP T29DP T29DP T29DP T29DP T29DPB_ML_P T29DPB_ML_N T29DPB_ML_C_P T29DPB_ML_C_N DP_B_EXT_AUXCH_P DP_B_EXT_AUXCH_N 85 85 85 85 85 85 85 86 85 86 D 85 86 85 86 86 86 TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_HEAD LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM T29_SPI * ? =2x_DIELECTRIC DP_SDRVA_ML_EVEN DP_SDRVA_ML_EVEN DP_SDRVA_ML_ODD DP_SDRVA_ML_ODD DP_SDRVA_AUXCH DP_SDRVA_AUXCH T29/DP Connector Signal Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP T29DP_80D * =80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM T29DP_100D * SPACING_RULE_SET LAYER =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF TABLE_SPACING_RULE_HEAD LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM T29DP * =5x_DIELECTRIC TABLE_SPACING_RULE_ITEM ? T29DP TOP,BOTTOM =7x_DIELECTRIC ? SOURCE: Bill Cornelius’s T29 Routing Notes T29_R2D2 T29_R2D2 T29_R2D3 T29_R2D3 C T29_D2R2 T29_D2R2 T29_D2R3 T29_D2R3 DP_SDRVB_ML_EVEN DP_SDRVB_ML_EVEN DP_SDRVB_ML_ODD DP_SDRVB_ML_ODD DP_SDRVB_AUXCH DP_SDRVB_AUXCH B T29 IC Net Properties ELECTRICAL_CONSTRAINT_SET DP_T29SNK0_ML DP_T29SNK0_ML DP_T29SNK0_AUXCH DP_T29SNK0_AUXCH DP_T29SNK1_ML DP_T29SNK1_ML DP_T29SNK1_AUXCH DP_T29SNK1_AUXCH A T29_SPI_CLK T29_SPI_MOSI T29_SPI_MISO T29_SPI_CS_L NET_TYPE PHYSICAL SPACING DP_85D DP_85D DP_85D DP_85D DP_85D DP_85D DP_85D DP_85D DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DP_T29SNK0_ML_C_P DP_T29SNK0_ML_C_N DP_T29SNK0_ML_P DP_T29SNK0_ML_N DP_T29SNK0_AUXCH_C_P DP_T29SNK0_AUXCH_C_N DP_T29SNK0_AUXCH_P DP_T29SNK0_AUXCH_N DP_85D DP_85D DP_85D DP_85D DP_85D DP_85D DP_85D DP_85D DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DP_T29SNK1_ML_C_P DP_T29SNK1_ML_C_N DP_T29SNK1_ML_P DP_T29SNK1_ML_N DP_T29SNK1_AUXCH_C_P DP_T29SNK1_AUXCH_C_N DP_T29SNK1_AUXCH_P DP_T29SNK1_AUXCH_N DP_85D DP_85D DP_85D DP_85D DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DP_T29SRC_ML_C_P DP_T29SRC_ML_C_N DP_T29SRC_AUXCH_C_P DP_T29SRC_AUXCH_C_N T29_I2C_55S T29_I2C_55S T29_I2C T29_I2C I2C_T29_SCL I2C_T29_SDA T29_SPI_55S T29_SPI_55S T29_SPI_55S T29_SPI_55S T29_SPI T29_SPI T29_SPI T29_SPI T29_SPI_CLK T29_SPI_MOSI T29_SPI_MISO T29_SPI_CS_L T29DP_80D T29DP_80D T29DP_100D T29DP_100D T29DP T29DP T29DP T29DP T29_R2D_C_P T29_R2D_C_N T29_D2R_P T29_D2R_N 85 85 85 85 85 97 85 97 85 85 85 85 85 85 85 86 85 86 85 86 85 86 85 86 85 86 C Only used on dual-port hosts 97 97 B 33 79 33 79 33 33 33 79 33 79 33 33 33 79 33 79 33 33 33 79 33 79 33 33 Only used on hosts supporting T29 video-in 33 48 85 SYNC_MASTER=T29_REF 33 48 85 SYNC_DATE=10/20/2010 PAGE TITLE T29 Constraints 33 DRAWING NUMBER Apple Inc 33 SIZE D 33 REVISION R 33 NOTICE OF PROPRIETARY PROPERTY: BRANCH 33 85 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED 33 85 33 85 33 85 PAGE 105 OF 132 SHEET 97 OF 105 A SMC SMBus Net Properties TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 1TO1_DIFFPAIR * =STANDARD =STANDARD =STANDARD =STANDARD 0.1 MM 0.1 MM ELECTRICAL_CONSTRAINT_SET NET_TYPE SPACING PHYSICAL TABLE_PHYSICAL_RULE_ITEM SMBUS_SMC_A_S3_SCL SMBUS_SMC_A_S3_SDA SMBUS_SMC_B_S0_SCL SMBUS_SMC_B_S0_SDA SMBUS_SMC_0_S0_SCL SMBUS_SMC_0_S0_SDA SMBUS_SMC_BSA_SCL SMBUS_SMC_BSA_SDA SMBUS_SMC_MGMT_SCL SMBUS_SMC_MGMT_SDA D SMB_50S SMB_50S SMB_50S SMB_50S SMB_50S SMB_50S SMB_50S SMB_50S SMB_50S SMB_50S SMB SMB SMB SMB SMB SMB SMB SMB SMB SMB SMBUS_SMC_A_S3_SCL SMBUS_SMC_A_S3_SDA SMBUS_SMC_B_S0_SCL SMBUS_SMC_B_S0_SDA SMBUS_SMC_0_S0_SCL SMBUS_SMC_0_S0_SDA SMBUS_SMC_BSA_SCL SMBUS_SMC_BSA_SDA SMBUS_SMC_MGMT_SCL SMBUS_SMC_MGMT_SDA 31 45 48 54 55 31 45 48 54 55 45 48 51 45 48 51 31 45 48 51 80 31 45 48 51 80 45 48 63 64 45 48 63 64 D 45 48 103 104 45 48 103 104 SMBus Charger Net Properties ELECTRICAL_CONSTRAINT_SET NET_TYPE PHYSICAL SPACING CHGR_CSI 1TO1_DIFFPAIR 1TO1_DIFFPAIR CHGR_CSI_P CHGR_CSI_N CHGR_CSO 1TO1_DIFFPAIR 1TO1_DIFFPAIR CHGR_CSO_P CHGR_CSO_N 64 64 64 64 C C B B A SYNC_MASTER=K17_MLB SYNC_DATE=05/14/2010 PAGE TITLE SMC Constraints DRAWING NUMBER Apple Inc SIZE D REVISION R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED BRANCH PAGE 106 OF 132 SHEET 98 OF 105 A GDDR5 Frame Buffer Signal Constraints GDDR5 FB A Net Properties GDDR5 FB B Net Properties TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM GDDR5_45R50SE * =50_OHM_SE =50_OHM_SE =50_OHM_SE 12.7 MM =STANDARD =STANDARD GDDR5_45SE * =45_OHM_SE =45_OHM_SE =45_OHM_SE =45_OHM_SE =STANDARD =STANDARD NET_TYPE ELECTRICAL_CONSTRAINT_SET TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM GDDR5_80D * =80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM GDDR5_CLK * =5x_DIELECTRIC ? TABLE_SPACING_RULE_ITEM D GDDR5_CMD * =2x_DIELECTRIC ? TABLE_SPACING_RULE_ITEM GDDR5_DATA * =3x_DIELECTRIC ? TABLE_SPACING_RULE_ITEM GDDR5_EDC * =7x_DIELECTRIC ? Digital Video Signal Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM DP_85D * =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF LVDS_85D * =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT DISPLAYPORT * =3x_DIELECTRIC ? TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT DISPLAYPORT TOP,BOTTOM =4x_DIELECTRIC ? TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM LVDS * =3x_DIELECTRIC I293 I294 I295 TABLE_SPACING_RULE_ITEM ? LVDS TOP,BOTTOM =4x_DIELECTRIC ? I296 I297 LVDS intra-pair matching should be 0.127 mm Pairs should be within 0.508mm of entire channel DisplayPort/TMDS intra-pair matching should be 0.127mm Inter-pair matching should be within 2.54cm DIsplayPort AUX CH intra-pair matching should be 0.127mm Max length 330.2mm Max length of LVDS/DisplayPort/TMDS traces: 13 inches SOURCE: Calpella SFF DG Rev 1.5 (407364) and Family GPU DG-04202-001-v04 I298 Max Length 241.3mm I299 I300 I301 I302 I303 I304 C FB_A0_CLK FB_A0_CLK FB_A1_CLK FB_A1_CLK FB_A0_CMD FB_A1_CMD FB_A0_CMD FB_A1_CMD FB_A0_CMD FB_A1_CMD FB_A0_CMD FB_A1_CMD FB_A0_CMD FB_A1_CMD FB_A0_CMD FB_A1_CMD FB_A0_CMD FB_A1_CMD FB_A0_EDC0 FB_A0_EDC1 FB_A0_EDC2 FB_A0_EDC3 FB_A1_EDC0 FB_A1_EDC1 FB_A1_EDC2 FB_A1_EDC3 FB_A0_DBI_L0 FB_A0_DBI_L1 FB_A0_DBI_L2 FB_A0_DBI_L3 FB_A1_DBI_L0 FB_A1_DBI_L1 FB_A1_DBI_L2 FB_A1_DBI_L3 FB_A0_WCLK0 FB_A0_WCLK0 FB_A0_WCLK1 FB_A0_WCLK1 FB_A1_WCLK0 FB_A1_WCLK0 FB_A1_WCLK1 FB_A1_WCLK1 FB_A0_DQ_BYTE0 FB_A0_DQ_BYTE1 FB_A0_DQ_BYTE2 FB_A0_DQ_BYTE3 FB_A1_DQ_BYTE0 FB_A1_DQ_BYTE1 FB_A1_DQ_BYTE2 FB_A1_DQ_BYTE3 FB_AB_RESET PHYSICAL NET_TYPE ELECTRICAL_CONSTRAINT_SET SPACING GDDR5_80D GDDR5_80D GDDR5_80D GDDR5_80D GDDR5_45R50SE GDDR5_45R50SE GDDR5_45R50SE GDDR5_45R50SE GDDR5_45R50SE GDDR5_45R50SE GDDR5_45R50SE GDDR5_45R50SE GDDR5_45R50SE GDDR5_45R50SE GDDR5_45R50SE GDDR5_45R50SE GDDR5_45R50SE GDDR5_45R50SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_80D GDDR5_80D GDDR5_80D GDDR5_80D GDDR5_80D GDDR5_80D GDDR5_80D GDDR5_80D GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45R50SE GDDR5_CLK GDDR5_CLK GDDR5_CLK GDDR5_CLK GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_EDC GDDR5_EDC GDDR5_EDC GDDR5_EDC GDDR5_EDC GDDR5_EDC GDDR5_EDC GDDR5_EDC GDDR5_DATA GDDR5_DATA GDDR5_DATA GDDR5_DATA GDDR5_DATA GDDR5_DATA GDDR5_DATA GDDR5_DATA GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_DATA GDDR5_DATA GDDR5_DATA GDDR5_DATA GDDR5_DATA GDDR5_DATA GDDR5_DATA GDDR5_DATA GDDR5_CMD FB_A0_CLK_P FB_A0_CLK_N FB_A1_CLK_P FB_A1_CLK_N FB_A0_A FB_A1_A FB_A0_ABI_L FB_A1_ABI_L FB_A0_RAS_L FB_A1_RAS_L FB_A0_CAS_L FB_A1_CAS_L FB_A0_WE_L FB_A1_WE_L FB_A0_CKE_L FB_A1_CKE_L FB_A0_CS_L FB_A1_CS_L FB_A0_EDC FB_A0_EDC FB_A0_EDC FB_A0_EDC FB_A1_EDC FB_A1_EDC FB_A1_EDC FB_A1_EDC FB_A0_DBI_L FB_A0_DBI_L FB_A0_DBI_L FB_A0_DBI_L FB_A1_DBI_L FB_A1_DBI_L FB_A1_DBI_L FB_A1_DBI_L FB_A0_WCLK_P FB_A0_WCLK_N FB_A0_WCLK_P FB_A0_WCLK_N FB_A1_WCLK_P FB_A1_WCLK_N FB_A1_WCLK_P FB_A1_WCLK_N FB_A0_DQ FB_A0_DQ FB_A0_DQ FB_A0_DQ FB_A1_DQ FB_A1_DQ FB_A1_DQ FB_A1_DQ FB_RESET_L 76 77 76 77 76 77 76 77 76 77 76 77 76 77 76 77 76 77 76 77 76 77 76 77 76 77 76 77 76 77 76 77 76 77 76 77 76 77 76 77 I305 76 77 I306 76 77 I307 76 77 I310 76 77 I309 76 77 I308 76 77 76 77 76 77 I311 76 77 I312 76 77 I313 76 77 I316 76 77 I315 76 77 I314 76 77 76 77 76 77 76 77 76 77 76 77 76 77 76 77 76 77 76 77 76 77 76 77 76 77 76 77 76 77 76 77 76 77 FB_B0_CLK FB_B0_CLK FB_B1_CLK FB_B1_CLK FB_B0_CMD FB_B1_CMD FB_B0_CMD FB_B1_CMD FB_B0_CMD FB_B1_CMD FB_B0_CMD FB_B1_CMD FB_B0_CMD FB_B1_CMD FB_B0_CMD FB_B1_CMD FB_B0_CMD FB_B1_CMD FB_B0_EDC0 FB_B0_EDC1 FB_B0_EDC2 FB_B0_EDC3 FB_B1_EDC0 FB_B1_EDC1 FB_B1_EDC2 FB_B1_EDC3 FB_B0_DBI_L0 FB_B0_DBI_L1 FB_B0_DBI_L2 FB_B0_DBI_L3 FB_B1_DBI_L0 FB_B1_DBI_L1 FB_B1_DBI_L2 FB_B1_DBI_L3 FB_B0_WCLK0 FB_B0_WCLK0 FB_B0_WCLK1 FB_B0_WCLK1 FB_B1_WCLK0 FB_B1_WCLK0 FB_B1_WCLK1 FB_B1_WCLK1 FB_B0_DQ_BYTE0 FB_B0_DQ_BYTE1 FB_B0_DQ_BYTE2 FB_B0_DQ_BYTE3 FB_B1_DQ_BYTE0 FB_B1_DQ_BYTE1 FB_B1_DQ_BYTE2 FB_B1_DQ_BYTE3 PHYSICAL GDDR5_80D GDDR5_80D GDDR5_80D GDDR5_80D GDDR5_45R50SE GDDR5_45R50SE GDDR5_45R50SE GDDR5_45R50SE GDDR5_45R50SE GDDR5_45R50SE GDDR5_45R50SE GDDR5_45R50SE GDDR5_45R50SE GDDR5_45R50SE GDDR5_45R50SE GDDR5_45R50SE GDDR5_45R50SE GDDR5_45R50SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_80D GDDR5_80D GDDR5_80D GDDR5_80D GDDR5_80D GDDR5_80D GDDR5_80D GDDR5_80D GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE LVDS_A_CLK LVDS_A_CLK LVDS_A_DATA LVDS_A_DATA LVDS_B_CLK LVDS_B_CLK LVDS_B_DATA LVDS_B_DATA 76 78 76 78 76 78 76 78 76 78 76 78 76 78 76 78 D 76 78 76 78 76 78 76 78 76 78 76 78 76 78 76 78 76 78 76 78 76 78 76 78 76 78 76 78 76 78 76 78 76 78 76 78 76 78 76 78 76 78 76 78 76 78 76 78 76 78 76 78 C 76 78 76 78 76 78 76 78 76 78 76 78 76 78 76 78 76 78 76 78 76 78 76 78 76 78 76 78 76 78 76 78 Whistler Net Properties NET_TYPE NET_TYPE B FB_B0_CLK_P FB_B0_CLK_N FB_B1_CLK_P FB_B1_CLK_N FB_B0_A FB_B1_A FB_B0_ABI_L FB_B1_ABI_L FB_B0_RAS_L FB_B1_RAS_L FB_B0_CAS_L FB_B1_CAS_L FB_B0_WE_L FB_B1_WE_L FB_B0_CKE_L FB_B1_CKE_L FB_B0_CS_L FB_B1_CS_L FB_B0_EDC FB_B0_EDC FB_B0_EDC FB_B0_EDC FB_B1_EDC FB_B1_EDC FB_B1_EDC FB_B1_EDC FB_B0_DBI_L FB_B0_DBI_L FB_B0_DBI_L FB_B0_DBI_L FB_B1_DBI_L FB_B1_DBI_L FB_B1_DBI_L FB_B1_DBI_L FB_B0_WCLK_P FB_B0_WCLK_N FB_B0_WCLK_P FB_B0_WCLK_N FB_B1_WCLK_P FB_B1_WCLK_N FB_B1_WCLK_P FB_B1_WCLK_N FB_B0_DQ FB_B0_DQ FB_B0_DQ FB_B0_DQ FB_B1_DQ FB_B1_DQ FB_B1_DQ FB_B1_DQ 76 77 78 MUXGFX Net Properties ELECTRICAL_CONSTRAINT_SET SPACING GDDR5_CLK GDDR5_CLK GDDR5_CLK GDDR5_CLK GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_EDC GDDR5_EDC GDDR5_EDC GDDR5_EDC GDDR5_EDC GDDR5_EDC GDDR5_EDC GDDR5_EDC GDDR5_DATA GDDR5_DATA GDDR5_DATA GDDR5_DATA GDDR5_DATA GDDR5_DATA GDDR5_DATA GDDR5_DATA GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_DATA GDDR5_DATA GDDR5_DATA GDDR5_DATA GDDR5_DATA GDDR5_DATA GDDR5_DATA GDDR5_DATA PHYSICAL ELECTRICAL_CONSTRAINT_SET SPACING LVDS_85D LVDS_85D LVDS_85D LVDS_85D LVDS_85D LVDS_85D LVDS_85D LVDS_85D LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS_A_CLK_P LVDS_A_CLK_N LVDS_A_DATA_P LVDS_A_DATA_N LVDS_B_CLK_P LVDS_B_CLK_N LVDS_B_DATA_P LVDS_B_DATA_N LVDS_85D LVDS_85D LVDS_85D LVDS_85D LVDS_85D LVDS_85D LVDS_85D LVDS_85D LVDS_85D LVDS_85D LVDS_85D LVDS_85D LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS_CONN_A_CLK_F_P LVDS_CONN_A_CLK_F_N LVDS_CONN_B_CLK_F_P LVDS_CONN_B_CLK_F_N LVDS_CONN_A_CLK_P LVDS_CONN_A_CLK_N LVDS_CONN_A_DATA_P LVDS_CONN_A_DATA_N LVDS_CONN_B_CLK_P LVDS_CONN_B_CLK_N LVDS_CONN_B_DATA_P LVDS_CONN_B_DATA_N 84 88 84 88 84 88 84 88 84 88 84 88 84 88 84 88 83 83 83 PHYSICAL GPU_CLK27M GPU_CLK100M LVDS_EG_A_CLK LVDS_EG_A_CLK LVDS_EG_A_DATA LVDS_EG_A_DATA LVDS_EG_A_DATA3 LVDS_EG_A_DATA3 LVDS_EG_B_DATA LVDS_EG_B_DATA LVDS_EG_B_DATA3 LVDS_EG_B_DATA3 CLK_SLOW_55S CLK_SLOW_55S LVDS_85D LVDS_85D LVDS_85D LVDS_85D LVDS_85D LVDS_85D LVDS_85D LVDS_85D LVDS_85D LVDS_85D DP_ML DP_85D DP_85D DP_85D DP_85D DP_85D DP_85D B SPACING CLK_SLOW CLK_SLOW LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS GPU_CLK27M GPU_CLK100M LVDS_EG_A_CLK_P LVDS_EG_A_CLK_N LVDS_EG_A_DATA_P LVDS_EG_A_DATA_N NC_LVDS_EG_A_DATA_P NC_LVDS_EG_A_DATA_N LVDS_EG_B_DATA_P LVDS_EG_B_DATA_N NC_LVDS_EG_B_DATA_P NC_LVDS_EG_B_DATA_N 79 80 79 80 79 88 79 88 79 88 79 88 79 80 79 80 79 88 79 88 79 80 79 80 83 83 84 83 84 83 84 DP_AUX_CH 83 84 83 84 DP_AUX_CH 83 84 DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DP_EXTA_ML_C_P DP_EXTA_ML_C_N DP_EXTA_AUXCH_C_P DP_EXTA_AUXCH_C_N DP_EG_AUX_CH_P DP_EG_AUX_CH_N 79 85 79 85 84 85 84 85 79 84 79 84 83 84 83 84 A SYNC_MASTER=K91_MLB SYNC_DATE=07/21/2010 PAGE TITLE GPU (Whistler) CONSTRAINTS DRAWING NUMBER Apple Inc SIZE D REVISION R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED BRANCH PAGE 107 OF 132 SHEET 99 OF 105 A K92 Specific Net Properties TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP K92 Specific Net Properties NET_TYPE ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING NET_TYPE TABLE_PHYSICAL_RULE_ITEM SENSE_1TO1_55S * =55_OHM_SE =1:1_DIFFPAIR =55_OHM_SE =55_OHM_SE =1:1_DIFFPAIR =1:1_DIFFPAIR TABLE_PHYSICAL_RULE_ITEM THERM_1TO1_55S * =55_OHM_SE =1:1_DIFFPAIR =55_OHM_SE =55_OHM_SE =1:1_DIFFPAIR * =1:1_DIFFPAIR AUDIODIFF * =1:1_DIFFPAIR ENETCONN ENET_100D ENETCONN =1:1_DIFFPAIR =1:1_DIFFPAIR =1:1_DIFFPAIR 10 MM 0.1 MM 0.1 MM 0.1 MM SENSE_DIFFPAIR SENSE_1TO1_55S SENSE SENSE_DIFFPAIR SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET SENSE_DIFFPAIR WEIGHT TABLE_SPACING_ASSIGNMENT_ITEM CPU_COMP TABLE_SPACING_RULE_ITEM D SENSE * =2:1_SPACING GND * GND_P2MM ? SENSE_DIFFPAIR TABLE_SPACING_ASSIGNMENT_ITEM CPU_VCCSENSE TABLE_SPACING_RULE_ITEM THERM * =2:1_SPACING GND * GND_P2MM ? SENSE_DIFFPAIR TABLE_SPACING_RULE_ITEM AUDIO * ? =2:1_SPACING SENSE_DIFFPAIR SENSE_DIFFPAIR TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_ASSIGNMENT_HEAD TABLE_SPACING_RULE_ITEM ENETCONN * 25 MILS NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET ENET_MDI GND * GND_P2MM SENSE_DIFFPAIR ? TABLE_SPACING_ASSIGNMENT_ITEM I249 TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT GND * =STANDARD SENSE_DIFFPAIR I250 TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_HEAD ? NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET CLK_PCIE GND * GND_P2MM PCIE GND * GND_P2MM SATA GND * GND_P2MM I252 SENSE_DIFFPAIR I251 TABLE_SPACING_ASSIGNMENT_ITEM I256 SENSE_DIFFPAIR TABLE_SPACING_ASSIGNMENT_ITEM I255 TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT I281 TABLE_SPACING_ASSIGNMENT_ITEM * 0.20 MM 1000 PWR_P2MM * 0.20 MM 1000 TABLE_SPACING_ASSIGNMENT_ITEM USB GND * GND_P2MM CLK_PCIE SB_POWER * PWR_P2MM SENSE_DIFFPAIR I282 TABLE_SPACING_RULE_ITEM GND_P2MM I283 SENSE_DIFFPAIR TABLE_SPACING_RULE_ITEM I284 TABLE_SPACING_ASSIGNMENT_ITEM I285 SENSE_DIFFPAIR TABLE_SPACING_ASSIGNMENT_ITEM SATA TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SB_POWER * I286 PWR_P2MM TABLE_SPACING_ASSIGNMENT_ITEM USB MEM_CLK GND * SB_POWER * I369 PWR_P2MM GND_P2MM MEM_CMD GND * GND_P2MM GND * GND_P2MM MEM_DATA GND * GND_P2MM I372 SENSE_DIFFPAIR I371 TABLE_SPACING_ASSIGNMENT_ITEM C SENSE_DIFFPAIR I370 TABLE_SPACING_ASSIGNMENT_ITEM MEM_CTRL I374 SENSE_DIFFPAIR TABLE_SPACING_ASSIGNMENT_ITEM I373 TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET I375 TABLE_SPACING_ASSIGNMENT_ITEM MEM_DQS GND * GND_P2MM SENSE_DIFFPAIR TABLE_SPACING_ASSIGNMENT_ITEM LVDS GND * I376 GND_P2MM I377 SENSE_DIFFPAIR I378 TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM MEM_40S * OVERRIDE OVERRIDE OVERRIDE OVERRIDE 0.09 MM 100 MIL OVERRIDE OVERRIDE OVERRIDE TABLE_PHYSICAL_RULE_ITEM MEM_72D * OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE 0.09 MM 100 MIL OVERRIDE OVERRIDE OVERRIDE * OVERRIDE OVERRIDE 0.09 MM 10 mm OVERRIDE OVERRIDE OVERRIDE OVERRIDE USB_85D TOP OVERRIDE OVERRIDE CPU_27P4S BOTTOM OVERRIDE OVERRIDE OVERRIDE OVERRIDE 0.1 MM 500 MIL OVERRIDE OVERRIDE 0.23 MM 100 MIL OVERRIDE OVERRIDE OVERRIDE TABLE_PHYSICAL_RULE_ITEM OVERRIDE OVERRIDE OVERRIDE SENSE_DIFFPAIR I385 SENSE_DIFFPAIR I396 I398 OVERRIDE SENSE_DIFFPAIR I384 I395 OVERRIDE SENSE_DIFFPAIR I383 I386 TABLE_PHYSICAL_RULE_ITEM SENSE_DIFFPAIR I380 I382 OVERRIDE TABLE_PHYSICAL_RULE_ITEM PCIE_85D I379 I381 OVERRIDE VCCSAS0_CS_P VCCSAS0_CS_N VCCSAISNS_R_P VCCSAISNS_R_N ISNS_1V5_S3_R_P ISNS_1V5_S3_R_N CPUVCCIOS0_CS_P CPUVCCIOS0_CS_N CPUVCCIOISNS_R_P CPUVCCIOISNS_R_N GPUISENS_N GPUISENS_P ISNS_1V5_S3_N ISNS_1V5_S3_P ISNS_AIRPORT_P ISNS_AIRPORT_N ISNS_PP1V0_S0GPU_P ISNS_PP1V0_S0GPU_N ISNS_PP1V8_S0GPU_P ISNS_PP1V8_S0GPU_N ISNS_HDD_N ISNS_HDD_P ISNS_PP1V5_S0GPU_P ISNS_PP1V5_S0GPU_N ISNS_LCDBKLT_N ISNS_LCDBKLT_P ISNS_ODD_N ISNS_ODD_P 49 65 SENSE_DIFFPAIR I397 I400 SENSE_DIFFPAIR SENSE_DIFFPAIR I387 I390 SENSE_DIFFPAIR SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE SENSE_DIFFPAIR I392 SENSE SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE SENSE_1TO1_55S I389 I391 SENSE SENSE_1TO1_55S I399 I388 SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE ISNS_HS_COMPUTING_P ISNS_HS_COMPUTING_N ISNS_HS_GPU_P ISNS_HS_GPU_N ISNS_HS_OTHER_P ISNS_HS_OTHER_N CPUIMVP_ISNS1_P CPUIMVP_ISNS1_N CPUIMVP_ISUM_R_P CPUIMVP_ISUM_R_N CPUIMVP_ISNS_P CPUIMVP_ISNS_N CPUIMVP_ISNS1G_P CPUIMVP_ISNS1G_N CPUIMVP_ISUMG_R_P CPUIMVP_ISUMG_R_N CPUIMVP_ISNS1G_R_P CPUIMVP_ISNS1G_R_N ISNS_PP1V0_S0GPU_R_P ISNS_PP1V0_S0GPU_R_N ISNS_PP1V8_S0GPU_R_P ISNS_PP1V8_S0GPU_R_N ISNS_PP1V5_S0GPU_R_P ISNS_PP1V5_S0GPU_R_N ISNS_AIRPORT_R_P ISNS_AIRPORT_R_N ISNS_HDD_R_P ISNS_HDD_R_N ISNS_ODD_R_P ISNS_ODD_R_N PCIE_EXCARD_R2D I350 49 65 I351 49 I352 49 I354 49 I353 49 I356 49 70 I355 PCIE_EXCARD_D2R PCIE_EXCARD_R2D PCIE_CLK100M_EXCARD SPACING PHYSICAL PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE_85D CLK_PCIE_90D CLK_PCIE_90D PCIE PCIE PCIE PCIE PCIE PCIE CLK_PCIE CLK_PCIE PCIE_EXCARD_R2D_P 32 PCIE_EXCARD_R2D_N 32 PCIE_EXCARD_D2R_P 16 32 PCIE_EXCARD_D2R_N 16 32 PCIE_EXCARD_R2D_C_P 16 32 PCIE_EXCARD_R2D_C_N 16 32 PCIE_CLK100M_EXCARD_CONN_P 32 PCIE_CLK100M_EXCARD_CONN_N 32 D 49 70 49 49 I361 49 I362 PCIE_CLK100M_AP 49 49 67 49 67 31 103 (USB_EXTA) (USB_EXTA) (USB_EXTA) (USB_EXTA) CLK_PCIE_90D CLK_PCIE CLK_PCIE_90D CLK_PCIE 1TO1_DIFFPAIR 1TO1_DIFFPAIR 1TO1_DIFFPAIR 1TO1_DIFFPAIR USB_85D USB USB_85D USB USB_85D USB USB_85D USB 103 USB_85D USB 41 103 USB_85D USB USB_85D USB USB_85D USB USB_85D USB USB_85D USB USB_85D USB USB_85D USB USB_85D USB USB_85D USB USB_85D USB USB_85D USB 31 103 103 103 103 (USB_EXTB) 41 103 103 103 I358 89 103 I357 89 103 I359 41 103 I360 41 103 I363 SPACING_RULE_SET TABLE_SPACING_ASSIGNMENT_ITEM ELECTRICAL_CONSTRAINT_SET 37 I349 TABLE_PHYSICAL_RULE_ITEM 0.1 MM 37 =1:1_DIFFPAIR TABLE_PHYSICAL_RULE_ITEM DIFFPAIR ENET_100D ENETCONN_P ENETCONN_N 50 USB_EXCARD USB_EXCARD (USB_EXTC) I364 50 50 PCIE_CLK100M_AP_CONN_P PCIE_CLK100M_AP_CONN_N CHGR_CSI_R_P CHGR_CSI_R_N CHGR_CSO_R_P CHGR_CSO_R_N USB2_EXTA_MUXED_P USB2_EXTA_MUXED_N USB2_LT1_P USB2_LT1_N CONN_USB2_BT_P CONN_USB2_BT_N USB_LT2_P USB_LT2_N USB_EXCARD_P USB_EXCARD_N USB2_EXCARD_CONN_P USB2_EXCARD_CONN_N 31 31 64 64 50 64 50 64 42 42 42 42 42 42 24 32 24 32 32 32 USB_LT3_P USB_LT3_N 43 43 USB_TPAD_R_P USB_TPAD_R_N 53 53 50 C 50 50 50 68 69 SB_POWER 50 69 SB_POWER 50 SB_POWER 50 GND 48 56 71 72 73 83 86 91 102 104 17 19 20 22 23 24 25 29 46 PP3V3_S5 PP3V3_S0 PP1V5_S3RS0 61 62 72 73 80 83 84 85 88 89 12 23 25 26 28 32 35 36 39 40 41 46 48 49 50 51 52 54 57 91 102 72 104 GND 50 50 50 69 50 69 50 50 NET_TYPE 50 50 ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING 103 SENSE_DIFFPAIR THERM_1TO1_55S THERM THERM_1TO1_55S THERM THERM_1TO1_55S THERM THERM_1TO1_55S THERM THERM_1TO1_55S THERM THERM_1TO1_55S THERM THERM_1TO1_55S THERM THERM_1TO1_55S THERM THERM_1TO1_55S THERM THERM_1TO1_55S THERM 103 103 I287 SENSE_DIFFPAIR 103 I288 103 SENSE_DIFFPAIR 103 103 SENSE_DIFFPAIR 103 103 I367 SENSE_DIFFPAIR 103 I368 CPUTHMSNS_D2_P CPUTHMSNS_D2_N 51 51 CPU_THERMD_P CPU_THERMD_N GPUTHMSNS_D_P GPUTHMSNS_D_N GPU_TDIODE_P GPU_TDIODE_N T29_THERMD_P T29_THERMD_N 51 51 51 51 51 79 51 79 33 51 51 103 103 B B SENSE_DIFFPAIR I402 AUDIO_DIFFPAIR AUDIODIFF AUDIO I401 I312 AUDIO_DIFFPAIR AUDIODIFF I311 I314 AUDIO_DIFFPAIR I313 I316 AUDIO_DIFFPAIR I315 Graphics ,SATA Constraint Relaxations I329 AUDIO_DIFFPAIR I330 I331 Alternate diffpair width/gap through BGA fanout areas (95-ohm diff) NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET LVDS_85D BGA LVDS_85D AUDIO_DIFFPAIR I332 TABLE_PHYSICAL_ASSIGNMENT_HEAD I333 AUDIO_DIFFPAIR TABLE_PHYSICAL_ASSIGNMENT_ITEM I334 I317 TABLE_PHYSICAL_ASSIGNMENT_ITEM DP_85D BGA 100_DIFF_BGA SATA_90D BGA I319 100_DIFF_BGA BGA AUDIO_DIFFPAIR I320 TABLE_PHYSICAL_ASSIGNMENT_ITEM CLK_PCIE_90D AUDIO_DIFFPAIR I318 TABLE_PHYSICAL_ASSIGNMENT_ITEM 100_DIFF_BGA I321 AUDIO_DIFFPAIR I322 I340 A Memory Constraint Relaxations TABLE_PHYSICAL_RULE_HEAD LAYER MEM_72D BOTTOM ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH 0.127 MM 6.35 MM DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP I338 I342 TABLE_PHYSICAL_RULE_ITEM TOP 0.1 MM 6.35 MM AUDIO_DIFFPAIR I337 TABLE_PHYSICAL_RULE_ITEM MEM_85D AUDIO_DIFFPAIR I336 Allow 0.127 mm necks for >0.127 mm lines for ARD fanout PHYSICAL_RULE_SET AUDIO_DIFFPAIR I339 I335 AUDIO_DIFFPAIR I341 I344 AUDIO_DIFFPAIR I343 I346 AUDIO_DIFFPAIR I345 I348 AUDIO_DIFFPAIR I347 AUDIODIFF AUDIO AUDIO AUDIODIFF AUDIO AUDIODIFF AUDIO AUDIODIFF AUDIO AUDIODIFF AUDIO AUDIODIFF AUDIO AUDIODIFF AUDIO AUDIODIFF AUDIO AUDIODIFF AUDIO AUDIODIFF AUDIO AUDIODIFF AUDIO AUDIODIFF AUDIO AUDIODIFF AUDIO AUDIODIFF AUDIO AUDIODIFF AUDIO AUDIODIFF AUDIO AUDIODIFF AUDIO AUDIODIFF AUDIO AUDIODIFF AUDIO AUDIODIFF AUDIO AUDIODIFF AUDIO AUDIODIFF AUDIO AUDIODIFF AUDIO AUDIODIFF AUDIO AUDIODIFF AUDIO AUDIODIFF AUDIO AUDIODIFF AUDIO AUDIODIFF AUDIO AUDIODIFF AUDIO AUDIODIFF AUDIO AUDIODIFF AUDIO BI_MIC_P BI_MIC_N AUD_LO1_R_P AUD_LO1_R_N AUD_LO2_R_P AUD_LO2_R_N AUD_LO3_R_P AUD_LO3_R_N AUD_LO3_L_P AUD_LO3_L_N AUD_MIC_INR_P AUD_MIC_INR_N AUD_MIC_INL_P AUD_MIC_INL_N SPKRAMP_BL_IN_L_P SPKRAMP_BL_IN_L_N SPKRAMP_FL_IN_L_P SPKRAMP_FL_IN_L_N SPKRAMP_BR_IN_L_P SPKRAMP_BR_IN_L_N SPKRAMP_FR_IN_L_P SPKRAMP_FR_IN_L_N SPKRAMP_LFE_IN_L_P SPKRAMP_LFE_IN_L_N SSM2375BL_IN_P SSM2375BL_IN_N SSM2375FL_IN_P SSM2375FL_IN_N SSM2375BR_IN_P SSM2375BR_IN_N SSM2375FR_IN_P SSM2375FR_IN_N SSM2375LFE_IN_P SSM2375LFE_IN_N 60 SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE 61 62 I292 SENSE_DIFFPAIR 61 62 I291 58 60 I299 SENSE_DIFFPAIR 58 60 I300 57 60 I301 SENSE_DIFFPAIR 57 60 I302 57 60 I303 SENSE_DIFFPAIR 57 60 I304 57 60 I305 SENSE_DIFFPAIR 57 60 I306 K92 Specific Net Properties K91 does not have ISNS_PP3V3_S3_P 104 ISNS_PP3V3_S3_N ISNS_PP3V3_S5_N ISNS_PP3V3_S5_P 104 104 104 ISNS_PP5V_S3_N ISNS_PP5V_S3_P 104 104 ISNS_PP1V05_S0PCH_N ISNS_PP1V05_S0PCH_P ISNS_PP5V_S0_N ISNS_PP5V_S0_P ISNS_CPU_DDR_N ISNS_CPU_DDR_P 104 104 104 104 104 104 57 62 57 62 57 62 57 62 60 60 60 60 60 60 60 60 SYNC_MASTER=K91_MLB 60 SYNC_DATE=07/22/2010 PAGE TITLE 60 Project Specific Constraints 60 DRAWING NUMBER 60 60 Apple Inc 60 SIZE D REVISION R 60 NOTICE OF PROPRIETARY PROPERTY: 60 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED 60 60 60 BRANCH PAGE 108 OF 132 SHEET 100 OF 105 A K92 Board-Specific Spacing & Physical Constraints TABLE_BOARD_INFO BOARD LAYERS BOARD AREAS BOARD UNITS (MIL or MM) ALLEGRO VERSION TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM NO_TYPE,BGA MM 15.5.1 TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_PHYSICAL_RULE_ITEM DEFAULT * Y =50_OHM_SE =50_OHM_SE 10 MM MM MM DEFAULT * 0.1 MM * Y =DEFAULT =DEFAULT 10 MM =DEFAULT =DEFAULT NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET * * BGA P072_SPACE TABLE_SPACING_ASSIGNMENT_ITEM ? TABLE_PHYSICAL_RULE_ITEM STANDARD TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM STANDARD * =DEFAULT ? BGA_P1MM * =DEFAULT ? BGA_P2MM * =DEFAULT ? P072_SPACE * 0.071 MM ? TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD D PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH 27P4_OHM_SE TOP,BOTTOM Y 0.310 MM 0.095 MM MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP D TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM 27P4_OHM_SE * Y 0.250 MM 0.1 MM =STANDARD =STANDARD =STANDARD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 37_OHM_SE TOP,BOTTOM Y 0.185 MM 0.095 MM 37_OHM_SE * Y 0.155 MM 0.090 MM TABLE_SPACING_RULE_HEAD LINE-TO-LINE SPACING WEIGHT 2X_DIELECTRIC SPACING_RULE_SET LAYER * 0.140 MM ? 3X_DIELECTRIC * 0.210 MM ? 4X_DIELECTRIC * 0.280 MM ? 5X_DIELECTRIC * 0.350 MM ? 7X_DIELECTRIC * 0.490 MM ? TABLE_PHYSICAL_RULE_HEAD TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_PHYSICAL_RULE_ITEM =STANDARD =STANDARD =STANDARD TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM 1.5:1_SPACING * 0.15 MM ? 2:1_SPACING * 0.2 MM ? 2.5:1_SPACING * 0.25 MM ? 3:1_SPACING * 0.3 MM ? 4:1_SPACING * 0.4 MM ? TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM 40_OHM_SE TOP,BOTTOM Y 0.165 MM 0.095 MM TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM 40_OHM_SE * Y 0.135 MM 0.090 MM =STANDARD =STANDARD =STANDARD TABLE_SPACING_RULE_ITEM NOTE: Based on K92 mlb stackup TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH 45_OHM_SE TOP,BOTTOM Y 0.13 MM 0.13 MM 45_OHM_SE * Y 0.099 MM 0.099 MM =STANDARD =STANDARD =STANDARD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 50_OHM_SE TOP,BOTTOM Y 0.110 MM 0.095 MM MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP 5:1_SPACING * ? 0.5 MM DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 1:1_DIFFPAIR * Y =STANDARD =STANDARD =STANDARD 0.1 MM 0.1 MM TABLE_PHYSICAL_RULE_ITEM C 50_OHM_SE * Y 0.090 MM 0.090 MM =STANDARD =STANDARD =STANDARD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 55_OHM_SE TOP,BOTTOM Y 0.090 MM 0.090 MM 55_OHM_SE * Y 0.076 MM 0.076 MM =STANDARD =STANDARD =STANDARD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 72_OHM_DIFF * N =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD 72_OHM_DIFF ISL3,ISL4 Y 0.154 MM 0.154 MM 0.200 MM 0.200 MM 72_OHM_DIFF ISL9,ISL10 Y 0.154 MM 0.154 MM 0.200 MM 0.200 MM 72_OHM_DIFF ISL2,ISL11 Y 0.154 MM 0.154 MM 0.200 MM 0.200 MM 72_OHM_DIFF TOP,BOTTOM Y 0.175 MM 0.175 MM 0.200 MM 0.200 MM PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 80_OHM_DIFF * N =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD 80_OHM_DIFF ISL3,ISL4,ISL9,ISL10 Y 0.105 MM 0.105 MM 0.120 MM 0.120 MM 80_OHM_DIFF ISL2,ISL11 Y 0.105 MM 0.105 MM 0.120 MM 0.120 MM 80_OHM_DIFF TOP,BOTTOM Y 0.135 MM 0.135 MM 0.160 MM 0.160 MM PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 85_OHM_DIFF * N =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD 85_OHM_DIFF ISL3,ISL4 Y 0.110 MM 0.090 MM 0.180 MM 0.180 MM TABLE_PHYSICAL_RULE_ITEM C TABLE_PHYSICAL_RULE_HEAD TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD TABLE_PHYSICAL_RULE_ITEM B B TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM 85_OHM_DIFF ISL9,ISL10 Y 0.110 MM 0.090 MM 0.180 MM 0.180 MM 85_OHM_DIFF ISL2,ISL11 Y 0.110 MM 0.090 MM 0.180 MM 0.180 MM 85_OHM_DIFF TOP,BOTTOM Y 0.125 MM 0.090 MM 0.190 MM 0.190 MM PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 90_OHM_DIFF * N =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD 90_OHM_DIFF ISL3,ISL4 Y 0.102 MM 0.090 MM 0.220 MM 0.220 MM 90_OHM_DIFF ISL9,ISL10 Y 0.102 MM 0.090 MM 0.220 MM 0.220 MM 90_OHM_DIFF ISL2,ISL11 Y 0.102 MM 0.090 MM 0.220 MM 0.220 MM 90_OHM_DIFF TOP,BOTTOM Y 0.115 MM 0.090 MM 0.230 MM 0.230 MM PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 100_OHM_DIFF * N =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD 100_OHM_DIFF ISL3,ISL4 Y 0.080 MM 0.080 MM 0.200 MM 0.200 MM 100_OHM_DIFF ISL9,ISL10 Y 0.080 MM 0.080 MM 0.200 MM 0.200 MM 100_OHM_DIFF ISL2,ISL11 Y 0.080 MM 0.080 MM 0.200 MM 0.200 MM 100_OHM_DIFF TOP,BOTTOM Y 0.089 MM 0.089 MM 0.220 MM 0.220 MM PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP =STANDARD =STANDARD =STANDARD 0.200 MM 0.200 MM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM A TABLE_PHYSICAL_RULE_ITEM SYNC_MASTER=K17_MLB SYNC_DATE=05/14/2010 PAGE TITLE PCB Rule Definitions TABLE_PHYSICAL_RULE_HEAD DRAWING NUMBER TABLE_PHYSICAL_RULE_ITEM 110_OHM_DIFF * N =STANDARD =STANDARD 110_OHM_DIFF ISL3,ISL4 Y 0.065 MM 0.065 MM TABLE_PHYSICAL_RULE_ITEM LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP ISL9,ISL10 Y 0.065 MM 0.065 MM 0.200 MM 0.200 MM 110_OHM_DIFF ISL2,ISL11 Y 0.065 MM 0.065 MM 0.200 MM 0.200 MM 100_DIFF_BGA * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF 100_DIFF_BGA ISL3,ISL4 Y 0.075 MM 0.075 MM =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF 0.125 MM 0.125 MM Y 0.075 MM 0.075 MM 0.330 MM 0.330 MM TABLE_PHYSICAL_RULE_ITEM 100_DIFF_BGA ISL9,ISL10 Y 0.075 MM 0.075 MM 0.125 MM NOTE: 100_DIFF_BGA is 100-ohms differential impedance on outer layers and 95-ohms on inner layers NOTICE OF PROPRIETARY PROPERTY: BRANCH TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TOP,BOTTOM D TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM 110_OHM_DIFF SIZE REVISION R TABLE_PHYSICAL_RULE_ITEM 110_OHM_DIFF Apple Inc TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET 0.125 MM THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED PAGE 109 OF 132 SHEET 101 OF 105 A PCH "S0" Rails D 73 70 68 45 39 35 23 14 13 12 10 105 104 102 PP1V05_S0 104 102 22 20 17 16 PPVCCIO_S0_PCH PPVCCIO_S0_PCH PCH "S5" Rail 71 56 48 46 29 25 24 23 22 20 19 17 104 102 100 91 86 83 73 72 PP1V05_S0 D PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 10 12 13 14 23 35 39 45 68 70 73 102 104 105 17 19 20 22 23 24 25 29 46 48 56 71 72 73 83 86 91 100 102 104 17 19 20 22 23 24 25 29 46 48 56 71 72 73 83 86 91 100 102 104 17 19 20 22 23 24 25 29 46 48 56 71 72 73 83 86 91 100 102 104 16 17 20 22 102 104 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.11 mm VOLTAGE=1.05V MAKE_BASE=TRUE PPVCCIO_S0_PCH PPVCCIO_S0_PCH PPVCCIO_S0_PCH PPVCCIO_S0_PCH PPVCCIO_S0_PCH PPVCCIO_S0_PCH PPVCCIO_S0_PCH PPVCCIO_S0_PCH PPVCCIO_S0_PCH PPVCCIO_S0_PCH PPVCCIO_S0_PCH PPVCCIO_S0_PCH PPVCCIO_S0_PCH PPVCCIO_S0_PCH PPVCCIO_S0_PCH PPVCCIO_S0_PCH PPVCCIO_S0_PCH C 16 17 20 22 102 104 16 17 20 22 102 104 16 17 20 22 102 104 16 17 20 22 102 104 16 17 20 22 102 104 16 17 20 22 102 104 16 17 20 22 102 104 16 17 20 22 102 104 16 17 20 22 102 104 16 17 20 22 102 104 C 16 17 20 22 102 104 16 17 20 22 102 104 16 17 20 22 102 104 16 17 20 22 102 104 16 17 20 22 102 104 16 17 20 22 102 104 16 17 20 22 102 104 OMIT RC100 88 72 71 25 20 14 PP1V8_S0 102 22 20 17 SHORT NONE NONE NONE 603 PP1V8_S0_PCH MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.8V MAKE_BASE=TRUE PP1V8_S0_PCH PP1V8_S0_PCH 17 20 22 102 17 20 22 102 OMIT RC101 100 91 89 88 85 84 46 41 40 39 36 35 32 28 26 25 23 12 83 80 73 72 62 61 57 54 52 51 50 49 48 PP3V3_S0 102 22 20 19 18 17 16 SHORT NONE NONE NONE 603 PP3V3_S0_PCH MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V MAKE_BASE=TRUE PP3V3_S0_PCH PP3V3_S0_PCH PP3V3_S0_PCH PP3V3_S0_PCH PP3V3_S0_PCH PP3V3_S0_PCH PP3V3_S0_PCH PP3V3_S0_PCH PP3V3_S0_PCH PP3V3_S0_PCH PP3V3_S0_PCH PP3V3_S0_PCH B 16 17 18 19 20 22 102 B 16 17 18 19 20 22 102 16 17 18 19 20 22 102 16 17 18 19 20 22 102 16 17 18 19 20 22 102 16 17 18 19 20 22 102 16 17 18 19 20 22 102 16 17 18 19 20 22 102 16 17 18 19 20 22 102 16 17 18 19 20 22 102 16 17 18 19 20 22 102 16 17 18 19 20 22 102 A SYNC_MASTER=K17_MLB SYNC_DATE=04/27/2010 PAGE TITLE PCH Power Aliases DRAWING NUMBER Apple Inc SIZE D REVISION R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED BRANCH PAGE 121 OF 132 SHEET 102 OF 105 A DEBUG_ADC RD103 DEBUG_ADC V+ 100 89 D 100 89 IN- ISNS_LCDBKLT_N IN DEBUG_ADC 4.53K OUT ISNS_LCDBKLT_IOUT SC70 IN+ ISNS_LCDBKLT_P IN PLACE_NEAR=UD100.22:5mm RD150 INA214 EDP Current: 0.715A 1M UD120 Sense Resistor 0.025 Ohm RD156 ADC_CH0 1% 1/16W MF-LF 402 CD145 0.22UF ADC_CH7 1% 1/16W MF-LF 402 0.1UF 20% 6.3V X5R 603 20% 10V CERM 402 RD157 CD152 2.2UF 1% 1/16W MF-LF 402 10% 6.3V X5R 402 105 PLACE_NEAR=UD100.5:5mm DIVIDER: ~ 1/22 103 22 103 23 ADC_CH0 ADC_CH1 103 ADC_CH2 103 ADC_CH3 103 ADC_CH4 103 ADC_CH5 103 ADC_CH6 103 ADC_CH7 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM 24 DVDD PP5V_S5 54 66 72 103 104 10UF RD101 QFN DEBUG_ADC 11 10 AD0 AD1 14 SDA SCL 17 33 15 SMBUS_SMC_MGMT_SDA RD102 ADC_VREF REFCOMP ADC_REFCOMP DEBUG_ADC DEBUG_ADC CD104 0.1UF SMBUS_SMC_MGMT_SCL IN 45 48 98 104 5% 1/16W MF-LF 402 VREF LSB: 0.001V 45 48 98 104 PLACE_NEAR=U4900.E4:10mm 33 1 BI DEBUG_ADC ADC_SDA ADC_SCL 16 D PLACE_NEAR=U4900.F1:10mm 5% 1/16W MF-LF 402 THRM PAD GND ADC RANGE: 0V TO 4.096V 20% 6.3V X5R 603 DEBUG_ADC LTC2309 I2C ADDRESS: 0X10 / 0X11 CD103 UD100 DEBUG_ADC DEBUG_ADC CD102 10UF 103 PLACE_NEAR=UD100.22:5mm 20% 6.3V X5R 402 GAIN: 100X CD101 20% 10V CERM 402 AVDD 226K 46.4K DEBUG_ADC GND 0.1UF RD158 DEBUG_ADC CD100 DEBUG_ADC DEBUG_ADC VOUT_S0_LCDBKLT_DIV 103 1% 1/16W MF-LF 402 REF PLACE_NEAR=UD100.5:5mm DEBUG_ADC 12 DEBUG_ADC 20% 10V CERM 402 5% 1/16W MF-LF 402 21 VOUT_S0_LCDBKLT_XW 0.1UF MIN_NECK_WIDTH=0.2 MM VOLTAGE=5V 25 89 83 DEBUG_ADC 10 PP5V_S5_DEBUG_ADC_DVDD_FILT MIN_LINE_WIDTH=0.3MM 20 CD144 104 MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=5V 5% 1/16W MF-LF 402 SM PP5V_S5_DEBUG_ADC_AVDD_FILT 13 PPVOUT_S0_LCDBKLT 19 DEBUG_ADC 104 XWD150 PP5V_S5 104 103 72 66 54 RD104 10 PP5V_S5 104 103 72 66 54 18 LCD BKLT Voltage Sense LCD BKLT Current Sense DEBUG_ADC DEBUG_ADC CD105 CD106 10UF 20% 10V CERM 402 2.2UF 20% 6.3V X5R 603 20% 6.3V CERM 402-LF AIRPORT Current Sense 104 103 72 66 54 PP5V_S5 104 103 72 66 54 DEBUG_ADC CD130 RD130 EDP Current: 1.06A C 100 31 2.61K ISNS_AIRPORT_P IN 100 ISNS_AIRPORT_R_P THRM 2.61K ISNS_AIRPORT_N 100 ISNS_AIRPORT_R_N ADC_CH2 1% 1/16W MF-LF 402 ISNS_ODD_R_P CD131 100 41 ISNS_ODD_N IN GAIN: 383X V+ 100 RD155 226K ISNS_ODD_IOUT ISNS_ODD_R_N 1% 1/16W MF-LF 402 GAIN: 226X NOSTUFF RD153 RD154 1M 1% 1/16W MF-LF 402 1% 1/16W MF-LF 402 10% 6.3V X5R 402 DEBUG_ADC DEBUG_ADC SIGNAL_MODEL=EMPTY CD150 PLACE_NEAR=UD100.1:5mm PLACE_NEAR=UD100.24:5mm 103 105 2.2UF 1% 1/16W MF-LF 402 10% 6.3V X5R 402 ADC_CH3 VTHRM C NOSTUFF OPA2333 DFN 1M 1M 1% 1/16W MF-LF 402 PLACE_NEAR=UD100.1:5mm UD140 RD152 4.42K 20% 10V CERM 402 DEBUG_ADC RD133 1M 100 DEBUG_ADC 103 DEBUG_ADC 2.2UF DEBUG_ADC 226K ISNS_AIRPORT_IOUT 1% 1/16W MF-LF 402 RD132 4.42K 1% 1/16W MF-LF 402 DEBUG_ADC 1 RD134 V- ISNS_ODD_P IN DEBUG_ADC DFN RD131 100 41 PLACE_NEAR=UD100.1:5mm OPA2333 DEBUG_ADC IN RD151 UD130 V+ 100 31 DEBUG_ADC 1% 1/16W MF-LF 402 CD151 0.1UF DEBUG_ADC EDP Current: 1.8A 20% 10V CERM 402 DEBUG_ADC DEBUG_ADC Sense Resistor 0.005 Ohm 0.1UF Sense Resistor 0.005 Ohm PP5V_S5 ODD Current Sense SIGNAL_MODEL=EMPTY 1% 1/16W MF-LF 402 SIGNAL_MODEL=EMPTY SIGNAL_MODEL=EMPTY GPU 1.0V Current Sense HDD Current Sense EDP Current: 2.846A 87 DEBUG_ADC IN PP1V0_S0GPU_ISNS_R 100 ISNS_PP1V0_S0GPU_P 4.22K 81 79 75 74 100 100 ISNS_PP1V0_S0GPU_N DEBUG_ADC 4.22K 1% 1/16W MF-LF 402 ISNS_1V0_GPU_IOUT VTHRM RD141 OUT PP1V0_S0GPU RD144 DFN V+ 226K 1% 1/16W MF-LF 402 100 41 ADC_CH4 2.94K CD142 100 41 ISNS_HDD_N IN RD143 1% 1/16W MF-LF 2.94K V+ 100 RD164 ISNS_HDD_IOUT VTHRM DEBUG_ADC OPA2333 DFN ISNS_HDD_R_N 226K ADC_CH5 1% 1/16W MF-LF 402 PLACE_NEAR=UD100.3:5mm 10% 6.3V X5R 402 DEBUG_ADC SIGNAL_MODEL=EMPTY DEBUG_ADC RD162 RD163 1M 1M 1% 1/16W MF-LF 402 GAIN: 237X CD140 2.2UF GAIN: 340X SIGNAL_MODEL=EMPTY B 103 DEBUG_ADC 1% 1/16W MF-LF 402 402 PLACE_NEAR=UD100.3:5mm UD140 1% 1/16W MF-LF 402 DEBUG_ADC 1M ISNS_HDD_R_P RD161 PLACE_NEAR=UD100.2:8mm 1M 100 DEBUG_ADC 402 RD142 1% 1/16W MF-LF 402 103 X5R ISNS_PP1V0_S0GPU_R_N DEBUG_ADC RD160 ISNS_HDD_P IN 2.2UF 10% 6.3V DEBUG_ADC 100 Sense Resistor 0.005 Ohm EDP Current: 1.2A DEBUG_ADC OPA2333 ISNS_PP1V0_S0GPU_R_P 1% 1/16W MF-LF 402 0.003 B RD145 0612 MF 1W 1% UD130 RD140 DEBUG_ADC PLACE_NEAR=UD100.2:8mm SIGNAL_MODEL=EMPTY 1% 1/16W MF-LF 402 SIGNAL_MODEL=EMPTY GPU 1.8V Current Sense 104 103 72 66 54 PP5V_S5 EDP Current: 2.4065A 72 IN PP1V8_S0GPU_ISNS_R DEBUG_ADC UD180 RD187 RD186 ISNS_PP1V8_S0GPU_P 0.005 1% 1W MF 0612 A OUT PP1V8_S0GPU ISNS_PP1V8_S0GPU_R_P 1% 1/16W MF-LF 402 100 79 75 81 5.90K ISNS_PP1V8_S0GPU_N OPA2333 1.5V FB Current Sense 20% 10V EDP Current: 7.8A CERM PLACE_NEAR=UD.23:5mm 402 ISNS_1V8_S0GPU_IOUT V- 4.53K 100 ADC_CH1 MF-LF Gain: 169x RD180 RD189 1% 1W MF 0612 0.22UF 20% 6.3V DEBUG_ADC 1% 1/16W MF-LF 402 SIGNAL_MODEL=EMPTY 78 77 76 75 OUT 1M ISNS_PP1V5_S0GPU_P UD180 7.68K ISNS_PP1V5_S0GPU_R_P OUT 103 SYNC_MASTER=K92_DINESH 402 100 ISNS_PP1V5_S0GPU_R_N Gain: 130x 20% 6.3V DEBUG_ADC DRAWING NUMBER Apple Inc X5R RD183 1% 1/16W MF-LF 402 NOTICE OF PROPRIETARY PROPERTY: DEBUG_ADC RD184 1M 1M THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED SIGNAL_MODEL=EMPTY 1% 1/16W MF-LF 402 SIZE D REVISION R PLACE_NEAR=UD100.4:5mm DEBUG_ADC 0.22UF DEBUG SENSORS AND ADC CD181 402 SYNC_DATE=09/07/2010 PAGE TITLE DEBUG_ADC SIGNAL_MODEL=EMPTY ADC_CH6 1% MF-LF 1% 1/16W DEBUG_ADCMF-LF 402 1% 1/16W MF-LF 402 4.53K ISNS_1V5_S0GPU_IOUT 1/16W THRM 7.68K RD185 V- SIGNAL_MODEL=EMPTY V+ RD182 PLACE_NEAR=UD100.4:5mm OPA2333 DFN 1% 1/16W MF-LF 402 100 ISNS_PP1V5_S0GPU_N PP1V5R1V35_GPU_FB_ISNS RD190 1 X5R DEBUG_ADC 1M DEBUG_ADC DEBUG_ADC 0.002 402 PLACE_NEAR=UD.23:5mm DEBUG_ADC PP1V5_S0GPU_ISNS_R 103 CD182 402 DEBUG_ADC 1% 1/16W MF-LF 402 OUT 1% ISNS_PP1V8_S0GPU_R_N IN RD181 1/16W THRM 87 RD191 DFN V+ RD188 5.90K CD180 0.1UF DEBUG_ADC DEBUG_ADC BRANCH PAGE 130 OF 132 SHEET 103 OF 105 A DEBUG_ADC RD201 DEBUG_ADC CD201 1 CD202 20% 6.3V X5R 603 12 AVDD 10UF 20% 6.3V X5R 603 23 ADC2_CH0 ADC2_CH1 104 ADC2_CH2 104 ADC2_CH3 104 ADC2_CH4 104 ADC2_CH5 104 ADC2_CH6 104 ADC2_CH7 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM 24 DVDD DEBUG_ADC AD0 AD1 14 15 NC SDA SCL 17 ADC2_SDA ADC2_SCL 33 CRITICAL EDP Current: 13.286A 16 SMBUS_SMC_MGMT_SDA DEBUG_ADC PP5V_S3 RD202 33 ADC2_VREF REFCOMP ADC2_REFCOMP DEBUG_ADC 66 IN ISNS_PP5V_S3_N INA213 IN- SC70 RD221 4.53K OUT ISNS_5V_S3_IOUT1 IN+ ISNS_PP5V_S3_P REF PP5V_S3_ISNS_R ADC2_CH3 1% 1/16W MF-LF 402 GND OUT 104 D DEBUG_ADC CD221 0.22UF PLACE_NEAR=UD210.1:5mm 20% 6.3V X5R 402 Gain: 50x PLACE_NEAR=U4900.E4:8mm SMBUS_SMC_MGMT_SCL DEBUG_ADC CD205 0.1UF IN 45 48 98 103 DEBUG_ADC CD206 CD207 10UF 20% 10V CERM 402 45 48 98 103 5% 1/16W MF-LF 402 LSB: 0.001V BI PLACE_NEAR=UD210.1:10mm DEBUG_ADC UD221 CRITICAL 1% 1W 100 MF 0612 DEBUG_ADC VREF 20 OUT PLACE_NEAR=U4900.F1:8mm 1 0.1UF 20% 10V CERM 402 V+ 5% 1/16W MF-LF 402 THRM PAD 19 18 11 10 DEBUG_ADC RD220 0.003 RD203 PP5V_S5 CD220 DEBUG_ADC QFN GND ADC RANGE: 0V TO 4.096V 104 103 72 66 54 100 LTC2309 I2C ADDRESS: 0X32 / 0X33 54 66 72 103 104 72 67 46 44 43 42 31 29 82 25 22 104 CD204 20% 10V CERM 402 UD210 104 0.1UF PP5V_S5 5% 1/16W MF-LF 402 DEBUG_ADC CD203 10UF 20% 10V CERM 402 DEBUG_ADC DEBUG_ADC 0.1UF MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=5V 21 10 PP5V_S5_DEBUG_ADC_DVDD_FILT 103 MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=5V PP5V_S5_DEBUG_ADC_AVDD_FILT 5% 1/16W MF-LF 402 D PP5V_S3 Current Sense 2 13 RD204 10 103 54 PP5V_S5 72 66 104 DEBUG_ADC 2.2UF 20% 6.3V X5R 603 PCH VCore Current Sense 20% 6.3V CERM 104 103 72 66 54 PP5V_S5 DEBUG_ADC 402-LF CD270 0.1UF DEBUG_ADC EDP:5A PP5V ODD Voltage Sense 0612 MF 1W 1% SM 5V_SW_ODD_XW RD222 73 70 68 45 39 35 23 14 13 12 10 105 102 1% 1/16W MF-LF 402 226K ADC2_CH7 1% 1/16W MF-LF 402 100 2.2UF 1 6.81K ISNS_PP5V_S0_P DEBUG_ADC CRITICAL UD220 1% 1/16W MF-LF 402 ISNS_PP5V_S0_N 87 73 70 69 68 65 54 52 47 41 22 105 8.45K ISNS_3V3_S3_R_N UD260 GAIN: 118X 104 CD261 2.2UF 10% 6.3V X5R 402 280K SIGNAL_MODEL=EMPTY 1% 1/16W MF-LF 402 B SIGNAL_MODEL=EMPTY 104 CD230 2.2UF DEBUG_ADC OUT GAIN: 41X OUT DEBUG_ADC RD264 226K ADC2_CH4 DEBUG_ADC ADC2_CH1 DEBUG_ADC 1% 1/16W MF-LF 402 1% 1/16W MF-LF 402 280K 226K PLACE_NEAR=UD210.23:5mm DEBUG_ADC 1% 1/16W MF-LF 402 PLACE_NEAR=UD210.2:5mm RD265 PLACE_NEAR=UD210.23:5mm ISNS_PP5V_S0_IOUT VTHRM RD263 ISNS_3V3_S3_IOUT V+ ISNS_PP5V_S0_R_N RD235 DEBUG_ADC DFN 2 20% 10V CERM 402 OPA2333 ISNS_PP5V_S0_R_P DEBUG_ADC V- - 1% 1/16W MF-LF 402 6.81K 1% 1/16W MF-LF 402 20% 10V CERM 402 SC70-5 V+ DEBUG_ADC RD262 OUT PP5V_S0 CD260 0.1UF OPA333DCKG4 ISNS_3V3_S3_R_P + RD232 100 CD231 8.45K DEBUG_ADC DEBUG_ADC 0.1UF RD231 OUT PP3V3_S3 PLACE_NEAR=UD210.3:10mm X5R 402 1% 1/16W MF-LF 402 DEBUG_ADC ISNS_PP3V3_S3_N 20% 6.3V RD261 IN PP5V_S0_ISNS_R 0612 MF 1W 1% PP3V3_S3 Current Sense 100 CD271 0.22UF 104 103 72 66 54 DEBUG_ADC 55 8848 5029 3124 3018 4925 7332 54 MF-LF DEBUG_ADC PP5V_S5 104 103 72 66 54 0.005 REF PP5V_S5 10% 6.3V PLACE_NEAR=UD210.5:8mm X5R 402 CRITICAL 0.005 RD230 104 PP5V_S0 Current Sense CD222 100 B OUT C IN+ 402 RD260 0612 MF 1W 1% ADC2_CH5 DEBUG_ADC 104 DIVIDER: ~ 2/5 ISNS_PP3V3_S3_P ISNS_PP1V05_S0PCH_P GND EDP Current: 9.865A 100 PLACE_NEAR=UD210.3:10mm DEBUG_ADC 72 CRITICAL 4.53K GAIN: 200X RD223 IN PP3V3_S3_ISNS_R ISNS_PCHCORE_IOUT RD224 1% 1/16W MF-LF 402 72 1/16W PP1V05_S0 IN RD270 OUT SC70 DEBUG_ADC 681K EDP:3.413A IN- PLACE_NEAR=UD210.5:8mm 5V_SW_ODD_DIV DEBUG_ADC CRITICAL ISNS_PP1V05_S0PCH_N 1% RD271 1M C 100 0.002 DEBUG_ADC DEBUG_ADC INA210 PP5V_SW_ODD CERM UD275 XWD220 41 20% 10V 402 V+ OUT PPVCCIO_S0_PCH 102 22 20 17 16 CRITICAL 10% 6.3V X5R 402 PLACE_NEAR=UD210.2:5mm DEBUG_ADC EDP:5.006A RD234 1M CPU DDR Current Sense DEBUG_ADC RD233 1M 1% 1/16W MF-LF 402 SIGNAL_MODEL=EMPTY 100 72 PP1V5_S3RS0 IN 1% 1/16W MF-LF 402 DEBUG_ADC RD281 CRITICAL RD280 ISNS_CPU_DDR_P 0.005 SIGNAL_MODEL=EMPTY 1% 1W 100 MF 0612 12.4K UD260 ISNS_CPU_DDR_R_P 1% 1/16W MF-LF 402 ISNS_CPU_DDR_N V+ OUT PP1V5_S3RS0_CPUDDR PP3V3_S5 Current Sense 53 48 47 46 45 44 42 25 73 64 63 THRM CRITICAL PP3V3_S5 RD245 0612 CERM ISNS_PP3V3_S5_N IN- SC70 DEBUG_ADC ISNS_3V3_S5_IOUT 4.53K IN OUT IN+ REF 1 MF-LF 402 GND CD241 0.22UF PLACE_NEAR=UD210.24:5mm X5R 402 RD226 1% 1/16W MF-LF 402 ADC2_CH6 104 CD281 10% 6.3V X5R DEBUG_ADC RD284 1M SIGNAL_MODEL=EMPTY 1% 1/16W MF-LF 402 DEBUG SENSORS AND ADC DRAWING NUMBER Apple Inc CD223 2.2UF 1% 1/16W MF-LF 402 PLACE_NEAR=UD210.4:8mm 10% 6.3V X5R 402 SIZE D REVISION R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED SYNC_DATE=07/28/2010 PAGE TITLE 104 DEBUG_ADC DIVIDER: ~ 606 SYNC_MASTER=K92_DINESH RD227PLACE_NEAR=UD210.4:8mm 1M 20% 6.3V Gain: 100x DEBUG_ADC 3V3_WLAN_F_DIV DEBUG_ADC DEBUG_ADC 1% ISNS_PP3V3_S5_P OUT 2.2UF PLACE_NEAR=UD210.22:5mm 226K 104 1/16W 100 66 ADC2_CH2 ADC2_CH0 DEBUG_ADC SIGNAL_MODEL=EMPTY 1% 1/16W MF-LF 402 RD246 1% 1/16W MF-LF 402 PP3V3 WLAN Voltage Sense RD225 PLACE_NEAR=UD210.22:5mm 1% 1/16W MF-LF 402 649K DEBUG_ADC OUT 0.002 CRITICAL PP3V3_S5_ISNS_R 3V3_WLAN_F_XW INA214 100 PLACE_NEAR=UD210.24:5mm UD245 MF 1W 1% PP3V3_WLAN_F1 402 V+ OUT 20% 10V A 100 71 24 20 46 83 31 DEBUG_ADC 1M SM 0.1UF 226K 402 DEBUG_ADC XWD200 CD240 ISNS_CPU_DDR_R_N RD283 DEBUG_ADC ISNS_CPU_DDR_IOUT GAIN: 81X DEBUG_ADC 102 73 72 29 25 19 17 23 22 56 48 91 86 1% 1/16W MF-LF 402 PP3V42_G3H EDP Current: 9.98A 12.4K RD285 V- RD282 73 29 15 13 10 DEBUG_ADC OPA2333 DFN BRANCH PAGE 131 OF 132 SHEET 104 OF 105 A D D CPURIPPLE_ENG LD300 FERR-120-OHM-0.3A PP5V_S0 87 73 70 69 68 65 54 52 47 41 22 104 PP5V_S0_RMC_FLT MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=5V 0402 CPURIPPLE_ENG PLACE_NEAR=RD305.1:5MM PLACE_NEAR=CD310.1:2MM CD310 XWD300 SM 69 49 14 12 IN PPVCORE_S0_CPU 1 MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.1V CD300 10UF 1UF PPVCORE_S0_RMC CPURIPPLE_ENG CPU_VCORE_C 20% 6.3V CERM-X5R 0402-1 CPURIPPLE_ENG RD306 10% 16V X5R 402 CPURIPPLE_ENG 10.2 0.1% 1/16W TF 402 RD300 PP1V05_S0 73 70 68 45 39 35 23 14 13 12 10 104 102 100 5% 1/16W MF-LF 402 PP1V05_S0_RMC_R CPURIPPLE_ENG MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V DD300 SOD-523 C C BAT54XV2T1 CPURIPPLE_ENG CPURIPPLE_ENG CD304 RD301 11K 10UF 20% 6.3V CERM-X5R 0402-1 0.1% 1/16W MF 402 CPURIPPLE_ENG CPURIPPLE_ENG 1 RD303 CD301 0.1UF 1.0K 10% 16V X5R 402-1 0.1% 1/16W TF 402 1V05_S0_RMC_DIV CPURIPPLE_ENG NO_TEST=TRUE V+ CPURIPPLE_ENG UD300 CPURIPPLE_ENG OPA2365 DD301 SOD-523 SO-8 RD305 10.2 CPURIPPLE_ENG RD3021 CPURIPPLE_ENG CD305 0.1UF 11K 0.1% 1/16W MF 402 CPURIPPLE_ENG RD304 0.1% 1/16W TF 402 COMP_CPU_VCORE_RMC UD300 CPU_VCORE_RMC_P NO_TEST=TRUE CPU_VCORE_RMC_DIV V- NO_TEST=TRUE OPA2365 SO-8 V+ BAT54XV2T1 VSNS_CPU_VCORE_RMC_OUT NO_TEST=TRUE CPU_VCORE_RMC_N V- NO_TEST=TRUE 1.0K CPURIPPLE_ENG RD320 4.53K2 ADC_CH3 1% 1/16W MF-LF 402 OUT 103 CPURIPPLE_ENG CD320 0.22UF 0.1% 1/16W TF 402 10% 10V CERM 402 10% 16V X5R 402-1 CPURIPPLE_ENG PLACE_NEAR=RD305.1:5MM CPURIPPLE_ENG RD308 RD307 10 1K 2 1% 1/16W MF-LF 402 5% 1/16W MF-LF 402 B B A SYNC_MASTER=K92_DINESH SYNC_DATE=08/23/2010 PAGE TITLE Power Supplies BIST DRAWING NUMBER Apple Inc SIZE D REVISION R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED BRANCH PAGE 132 OF 132 SHEET 105 OF 105 A ... BOOTROM_PROG:PROTO0 CRITICAL BOOTROM_PROG:PROTO1 CRITICAL BOOTROM_PROG:PROTO2 CRITICAL BOOTROM_PROG:EVT CRITICAL BOOTROM_PROG:DVT CRITICAL BOOTROM_PROG:PVT B Ethernet PART NUMBER REFERENCE DES IC,EEPROM,SERIAL,8KB,SOIC... IC,SMC,DEVELOPMENT-PROTO ,K92 341S2855 IC,SMC,DEVELOPMENT-PROTO1 ,K92 341S2995 IC,SMC,DEVELOPMENT-PROTO2 ,K92 341S2862 IC,SMC,DEVELOPMENT-EVT ,K92 341S2865 IC,SMC,DEVELOPMENT-DVT ,K92 341S2868 IC,SMC,DEVELOPMENT-PVT ,K92. .. 341S2939 IC,PROGRAMMED MCU,32B,LPC1112A,16KB/2KB,HVQFN25 CRITICAL BOM OPTION CRITICAL SMC_BLANK CRITICAL SMC_PROG:PROTO0 CRITICAL SMC_PROG:PROTO1 CRITICAL SMC_PROG:PROTO2 CRITICAL SMC_PROG:EVT CRITICAL