apple macbook m88 mbp17

8 D Page TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM C TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM B TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM 1 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 37 38 39 40 41 42 43 44 46 47 49 REV SCHEM,MLB,MBP17 PVT TABLE_TABLEOFCONTENTS_HEAD CK APPD ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5% ALL CAPACITANCE VALUES ARE IN MICROFARADS ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ (.csa) Date Contents Page N/A TABLE_TABLEOFCONTENTS_HEAD N/A (MASTER) TABLE_TABLEOFCONTENTS_ITEM (MASTER) (MASTER) TABLE_TABLEOFCONTENTS_ITEM (MASTER) N/A TABLE_TABLEOFCONTENTS_ITEM N/A N/A TABLE_TABLEOFCONTENTS_ITEM N/A N/A TABLE_TABLEOFCONTENTS_ITEM N/A MASTER TABLE_TABLEOFCONTENTS_ITEM MASTER (MASTER) TABLE_TABLEOFCONTENTS_ITEM (MASTER) MASTER TABLE_TABLEOFCONTENTS_ITEM MASTER 08/28/2007 TABLE_TABLEOFCONTENTS_ITEM M87_MLB 08/28/2007 TABLE_TABLEOFCONTENTS_ITEM M87_MLB 08/28/2007 TABLE_TABLEOFCONTENTS_ITEM M87_MLB 01/22/2007 TABLE_TABLEOFCONTENTS_ITEM T9_NOME 01/25/2007 TABLE_TABLEOFCONTENTS_ITEM T9_NOME 03/19/2007 TABLE_TABLEOFCONTENTS_ITEM T9_NOME 01/25/2007 TABLE_TABLEOFCONTENTS_ITEM T9_NOME 01/25/2007 TABLE_TABLEOFCONTENTS_ITEM T9_NOME 01/25/2007 TABLE_TABLEOFCONTENTS_ITEM T9_NOME 01/25/2007 TABLE_TABLEOFCONTENTS_ITEM T9_NOME 01/25/2007 TABLE_TABLEOFCONTENTS_ITEM T9_NOME MASTER TABLE_TABLEOFCONTENTS_ITEM MASTER 08/28/2007 TABLE_TABLEOFCONTENTS_ITEM M87_MLB 01/25/2007 TABLE_TABLEOFCONTENTS_ITEM T9_NOME 08/28/2007 TABLE_TABLEOFCONTENTS_ITEM M87_MLB 08/28/2007 TABLE_TABLEOFCONTENTS_ITEM M87_MLB 01/25/2007 TABLE_TABLEOFCONTENTS_ITEM T9_NOME MASTER TABLE_TABLEOFCONTENTS_ITEM MASTER 08/28/2007 TABLE_TABLEOFCONTENTS_ITEM M87_MLB 01/25/2007 TABLE_TABLEOFCONTENTS_ITEM T9_NOME 08/28/2007 TABLE_TABLEOFCONTENTS_ITEM M87_MLB 08/28/2007 TABLE_TABLEOFCONTENTS_ITEM M87_MLB 08/28/2007 TABLE_TABLEOFCONTENTS_ITEM M87_MLB (MASTER) TABLE_TABLEOFCONTENTS_ITEM (MASTER) (MASTER) TABLE_TABLEOFCONTENTS_ITEM (MASTER) 01/25/2007 TABLE_TABLEOFCONTENTS_ITEM T9_NOME 03/19/2007 TABLE_TABLEOFCONTENTS_ITEM T9_NOME 08/28/2007 TABLE_TABLEOFCONTENTS_ITEM M87_MLB 08/28/2007 TABLE_TABLEOFCONTENTS_ITEM M87_MLB 08/28/2007 TABLE_TABLEOFCONTENTS_ITEM M87_MLB 08/28/2007 TABLE_TABLEOFCONTENTS_ITEM M87_MLB 08/28/2007 TABLE_TABLEOFCONTENTS_ITEM M87_MLB MASTER TABLE_TABLEOFCONTENTS_ITEM MASTER MASTER TABLE_TABLEOFCONTENTS_ITEM MASTER 08/28/2007 TABLE_TABLEOFCONTENTS_ITEM M87_MLB 08/28/2007 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 50 51 52 53 54 55 56 57 58 59 61 69 70 71 73 74 75 76 77 78 79 80 81 82 84 85 86 87 88 89 90 91 92 93 94 96 98 100 101 102 103 104 105 106 ECN ENG APPD DESCRIPTION OF CHANGE DATE 521911 0.1 Proto Release ? DATE ? 12/18/2007 (.csa) Sync Table of Contents System Block Diagram Power Block Diagram Power Block Diagram BOM Configuration Revision History Functional / ICT Test Power Aliases Signal Aliases CPU FSB CPU Power & Ground CPU Decoupling & VID eXtended Debug Port (XDP) NB CPU Interface NB PEG / Video Interfaces NB Misc Interfaces NB DDR2 Interfaces NB Power NB Power NB Grounds NB Standard Decoupling NB Graphics Decoupling SB Enet, Disk, FSB, LPC SB PCI, PCIe, DMI, USB SB Pwr Mgt, GPIO, Clink SB Power & Ground SB Decoupling SB Misc Clock (CK505) Clock Termination DDR2 SO-DIMM Connector A DDR2 SO-DIMM Connector B Memory Active Termination Left I/O Board Connector Ethernet (Yukon) Yukon Power Control Ethernet Connector FireWire Link (TSB83AA22) FireWire PHY (TSB83AA22) FireWire Port Power FireWire Ports PATA Connector External USB Connector Left Clutch Barrel Interconnect SMC ZONE D Date Contents Sync SMC Support LPC+ Debug Connector SMBus Connections Current & Voltage Sensing Current Sensing Thermal Sensors Fan Connectors Current & Thermal Sensors ALS Support Sudden Motion Sensor (SMS) SPI BootROM DC-In & Battery Connectors Power FETs IMVP6 CPU VCore Regulator 5V / 3.3V Power Supply 1.25V / 1.05V Power Supply 1.8V DDR2 Supply 1.5V Power Supply FW PHY Power Supplies 3.425V G3Hot Supply & Power Control PBus Supply & Batt Charger NV G84M PCI-E NV G84M Core/FB Power NV G84M Frame Buffer I/F GDDR3 Frame Buffer A (Top) GDDR3 Frame Buffer B (Top) NV G84M GPIO/MIO/Misc GPU Straps NV G84M Video Interfaces GPU (G84M) Core Supply LVDS Display Connector GDDR3 Frame Buffer A (Bot) GDDR3 Frame Buffer B (Bot) 1.8V FB Power Supply DVI Display Connector Project Specific Connectors LCD Backlight Support CPU/FSB Constraints NB Constraints Memory Constraints SB Constraints (1 of 2) SB Constraints (2 of 2) Clock & SMC Constraints FireWire Constraints 10/15/2007 (.csa) Page TABLE_TABLEOFCONTENTS_HEAD M87_MLB 08/28/2007 TABLE_TABLEOFCONTENTS_ITEM M87_MLB (MASTER) TABLE_TABLEOFCONTENTS_ITEM (MASTER) 08/28/2007 90 91 92 107 108 109 Date Contents Sync 10/02/2007 GPU (G84M) Constraints Project Specific Constraints PCB Rule Definitions M87_MLB 08/28/2007 M87_MLB 10/03/2007 M87_MLB TABLE_TABLEOFCONTENTS_ITEM M87_MLB MASTER MASTER 08/28/2007 M87_MLB 08/28/2007 M87_MLB 11/06/2007 M87_LIO 08/28/2007 M87_MLB 08/28/2007 M87_MLB 01/25/2007 T9_NOME (MASTER) (MASTER) 08/28/2007 M87_MLB MASTER MASTER MASTER MASTER C 08/28/2007 M87_MLB 08/28/2007 M87_MLB MASTER MASTER 08/28/2007 M87_MLB 09/26/2007 M87_MLB MASTER MASTER 08/28/2007 M87_MLB 08/28/2007 M87_MLB 08/28/2007 M87_MLB 08/28/2007 M87_MLB 08/28/2007 M87_MLB 08/28/2007 M87_MLB 08/28/2007 M87_MLB 08/28/2007 M87_MLB 09/26/2007 M87_MLB MASTER MASTER 08/28/2007 M87_MLB 08/28/2007 B M87_MLB MASTER MASTER MASTER MASTER (MASTER) (MASTER) 12/06/2007 M87_LIO 01/25/2007 T9_NOME 01/25/2007 T9_NOME 01/25/2007 T9_NOME 01/25/2007 T9_NOME 01/25/2007 T9_NOME 08/28/2007 M87_MLB 01/25/2007 T9_NOME TABLE_TABLEOFCONTENTS_ITEM M87_MLB TABLE_TABLEOFCONTENTS_ITEM ALIASES RESOLVED A Schematic / PCB #’s PART NUMBER DIMENSIONS ARE IN MILLIMETERS APPLE INC METRIC XX X.XX DRAFTER THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING ENG APPD MFG APPD QA APPD DESIGNER RELEASE SCALE I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART ANGLES QTY DESCRIPTION REFERENCE DES CRITICAL 051-7431 SCHEM,MLB,MBP17 SCH CRITICAL 820-2262 PCBF,MLB,MBP17 PCB CRITICAL A NOTICE OF PROPRIETARY PROPERTY DESIGN CK X.XXX BOM OPTION TITLE DO NOT SCALE DRAWING SCHEM,MLB,MBP17 NONE DRAWING SIZE TITLE=MLB ABBREV=DRAWING LAST_MODIFIED=Tue Dec 18 15:43:01 2007 THIRD ANGLE PROJECTION MATERIAL/FINISH NOTED AS APPLICABLE D DRAWING NUMBER REV 051-7431 SHT 1 A.0.0 OF 92 U1000 CPU U2900 CK 505 2.? GHz U9100,U9150,U9200,U9250 U8400,U8450,U8500,U8550 Core ~1.2V GDDR3 FRAME BUFFER A/B (BOT) GDDR3 FRAME BUFFER A/B (TOP) PG 11,12 J1300 PG 10 PG 77,78 Clocks TERMS PG 29 PG 30 ITP/XDP CONN PG 71,72 PG 13 FSB D J6990/50 64-Bit 800/1066? MHz NB-GMCH Core PG 15 PG 74 Supply PG 57 PG 66 U5805 1.05 - 1.25V ALS SENS PG 54 DIMM DDR2 - Dual Channel Temp Sense 1.8V - 64 Bits CPU U5570 Pg 51 GPU U5500 Pg 51 Right Side U5550 Pg 51 533/667/800? MHz TV Out VIDEO INTERFACES SDVO D Power DC/Batt Conn J3100 J3200 U1400 PG 16/17 Core 1.26V - 1.05V PG 14 x16 PCI-E Main Memory PG 80 NV G84M PCI-E DVI-INTERFACE DVI DISPLAY CONN PG 67 PG 69 U8000 J9400 PCI-EBUS INTERFACE NV G84M FRAME BUFFER I/F PG31,32 PG 74 RGB Misc PG 16 LVDS PG 18~22 U5900 PG 15 DMI CLnk PG 16 PG 16 SUDDEN MOTION SENSOR PG 55 POWER SENSE PG 49-50 J5650/60 J9000/10 U6100 FAN CONN SPI Boot ROM LVDS DISP Conn PG 52 x4 DMI C PG 56 C 2.5 GHz PG 77 A B,0 BSA BSB ADC Fan Ser J5100 Prt SMC LPC Conn SATA Conn CLnk SPI PG 24 PG 25 PG 24 LPC SATA-0 1.2 V / 1.5 GHz J9660 DMI PG 47 Pg 46 PG 23 U4900 U2300 SATA J4400 J9660 PG 25 USB CONN SB-ICH8 SATA-2 IR J9600 LEFT CLUTCH BARREL INTERCONN Geyser Bluetooth WWAN CAMERA PG 44 PG 44 Trackpad/Keyboard PG 43 EXT-A PG 81 PG 81 PG 81 Core 1.05V PATA J4731 J9610 J4600 GPIOs SATA-1 PG 23 PG 81 Conn 3.3 V PCI-E Ln5 PG 25 B SMB Ln4 PG 24 Ln3 B Ln2 USB Ln1 PG 24 IDE PG 23 100 MHz Pg 42 Core Pg 25 Ln6 E-NET CLnk PCI AZALIA PG 23 PG 25 PG 24 PG 23 - X1 DIMM’s CLK CHIP J3100 U2900 LEFT I/O J3400 J3200 2.5 GHz 33 MHz 32-Bit U4000 TSB83BA22 FW-Link Pg 38 U3700 EXPRESS CARD A PG 34 EXT-C EXT-B USB CONNS PG 34 Mini PCI-E AirPort PG 34 U6200 ETHERNET Audio Codec (YUKON ULTRA) Pg 59 Pg 35 System Block Diagram 100 MHz 8-Bit SYNC_MASTER=(MASTER) U4000 FW-PHY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING J3900 Pg 39 LIO BOARD SYNC_DATE=(MASTER) NOTICE OF PROPRIETARY PROPERTY TSB83AA22 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE E-NET Conn II NOT TO REPRODUCE OR COPY IT J4300 J4310 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART Pg 37 SIZE FireWire Conn DRAWING NUMBER D APPLE INC Pg 41 SCALE SHT NONE REV 051-7431 A.0.0 OF 92 A M88 POWER SYSTEM ARCHITECTURE (0.2A MAX CURRENT) VIN PPDCIN_G3H J6990 SHDN* CRITICAL 87438-0832 PP3V42_G3H VOUT 3.425V"G3HOT" Energy Star LDO V U7950 PBUS_LDO_EN SHDN* D RN5VD30A-F U5000 (PAGE 46) Q5315 (4.5A MAX CURRENT) PP1V5_S0 PM_SLP_S3_DELAY_L VIN PP18V5_G3H_CHGR Q6950 U7900 (PAGE 66) SMC_BC_ACOK (PAGE 57) J6950 ISL6257 LIO_DCIN_ISENSE CHGR_EN CRITICAL 87438-1043 EN_PSV VOUT PGOOD VOUT Q7970 8A FUSE PPVBATT_G3H_FET_F BATTERY CHARGE U5400 A FET PPVBATT_G3H_FET VIN LIO_BATT_ISENSE VOUT CPUVCORE PPVBAT_G3H_CHGR_OUT U5495 VIN PM_GPUVCORE_EN EN_PSV ISL6263B U8900 (PAGE 75) PPVCORE_S0_NB_R A P1V8S3_PGOOD V ICH8M A U2830 VR_PWRGD_CLKEN PPVCORE_SO_CPU VR_ON 27 U2300 (44A MAX CURRENT) CPUVCORE_IOUT PLT_RST_L PLTRST* U2840 VR_PWRGD_CLKEN_L IMVP_VR_ON PWRBTN* VRMPWRGD RSMRST* CLKEN# PM_SB_PWROK PPVCORE_GPU CPU_PWRGD PGOOD PWROK CPUPWRGD(GPIO49) CLPWROK VR_PWRGOOD_DELAY (18A MAX CURRENT) (PAGE 59) 26 GPUVCORE_IOUT R=47K C=68NF C PGOOD P5VS3_SS GPUVCORE_PGOOD VIN DELAY SMC_PM_G2_EN U7858 R=100K P3V3S3_SS C=33NF EN1 DELAY P1V8S3_EN EN2 PP5V_S3 RESET* P5VS3_SS (5.5A MAX) CURRENT) TPS51120 U7300 (PAGE 60) PWRGOOD PP3V3_S5 PP3V3_S5 VOUT2 3.3V EN2 CPU Q7000 PP5V_S5 (8A MAX CURRENT) VOUT1 5V PP3V42_G3H U7859 R=10K C=0.47UF V A VOUT DELAY Q7012 ISL9504 U7100 SMC_GPU_VSENSE 518S0457 C U5420 NBCORE_IOUT SMC_CPU_VSENSE (PAGE 66) Q7002 PP1V05_S0 (10A MAX CURRENT) VOUT TPS51117 U7450 (PAGE 61)PGOOD U5715 BATT_POS VIN ENABLES SMC_ADAPTER_EN D 1.05V EN_PSV TPS51117 U7600 (PAGE 63) VIN VIN INRUSH LIMITER 1.5V PM_SLP_S3_DELAY_L PBUS SUPPLY / BATTERY CHARGER A VOUT VOUT (PAGE 66) VIN U5705 SMC_RESET_L SMC RESET "BUTTON" PPBUS_G3H VOUT 518S0456 LT3470 U7800 (PAGE 65) SMC_PBUS_VSENSE MAX8719 PP18V5_DCIN Q7030 U1000 Q7020 PP3V3_S0 PP5V_S0 EN2 PGOOD MCH 28 PM_S4_STATE_L RSMRST_PWRGD P3V3S0_SS P5VS0_SS Q7070 ICH8M PWROK FSB_CPURST_L PP5V_S5 PP3V3_GPU U2300 HCPURST* U1400 S4_STATE* Q7851 Q7851 VIN PM_GPUVCORE_EN PP0V9_S0 VOUT1 U7880 (10mA MAX CURRENT) S3_VTT_EN P1V8S3_EN S5_EN GPUVCORE_PGOOD B Q7850 PP1V9_ENET PP1V8_S3 IN 1.8V (12A MAX CURRENT) Q7850 P3V3ENET_SS U5440 PM_P1V8_S0GPU_EN Q4261 PP3V3_S3 Q3800 Q3801 WOL_EN PM_ENET_EN EN_PSV PM_P3V3GPU_EN DELAY SIGNAL DELAY TIME IMVP_VR_ON S0PWRGD_OK VR_PWRGOOD_DELAY VCC P1V25_S0_IOUT RSTIN RST* PP1V25_S0 TP1V25ENET_PGOOD (UNUSED) U7850 P1V25S0_SS PM_SLP_S3_DELAY_L VIN PP3V3_S5 PM_P1V8_S0GPU_EN VOUT EN (10A MAX CURRENT) PP1V8_S0GPU ISL6269 U9300 (PAGE 79) A Q7002 DELAY R=47K C=68NF Q7012 PGOOD P5VS0_SS PP1V8_S0GPU_ISNS VIN SHDN* LT3470 PM_SLP_S4_L(P94) PM_SLP_S3_L(P93) 99ms 200ms 7ms PWR/RST STATUS G3H POWER ON S5 POWER ON S3 POWER ON S0 SYSTEM POWER ON S0 CPU POWER ON PLATFORM,CPU RESET U4900 (PAGE 45) STEP 01-04 01,05-09 10-13 14-18 17,19-24 25-27 NO AC/BATTERY BATTERY ONLY ACIN WITH/WITHOUT BATTERY BATTERY ONLY,PRESS PWR BUTTON 27.11UF U7700 (PAGE 64) P1V8_S0GPU_IOUT PM_SLP_S3_L PM_SLP_S5_L(P95) STEP 06 (S5 POWER STATUS)TRUTH TABLE VOUT TP_P1V8_S0GPU_PGOOD (UNUSED) L(S5 L(S5 H(S5 H(S5 Power Block Diagram OFF) OFF) ON) ON) SYNC_MASTER=(MASTER) Q4260 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING Q7096 1.5A FUSE PPVIN_FW_3V3FW DELAY R=100K C=1UF I TO MAINTAIN THE DOCUMENT IN CONFIDENCE PP1V95_FW PPBUS_FW_FWPWRSW_F P1V25S0_SS VIN EN II NOT TO REPRODUCE OR COPY IT VOUT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART TPS799195 4.2UF U7720 SIZE FWPWR_EN_L_DIV DRAWING NUMBER D (PAGE 64) APPLE INC REV 051-7431 SCALE SHT NONE SYNC_DATE=(MASTER) NOTICE OF PROPRIETARY PROPERTY PPVP_FW DELAY R=100K P3V3S0_SS C=33NF Q7096 PP3V3_FW (0.2A MAX CURRENT) U5410 A : 08-1 POWER ON SEQUENCE LIST U7860 MAX6838 (PAGE 65) Q7095 PGOOD R=100K P3V3ENET_SS C=33NF ADAPTER IN PM_S4_STATE_L A PP1V25_ENET VOUT TPS51117 U7400 (PAGE 61) B RST* DELAY R=100K P3V3GPU_SS C=1UF PM_PWRBTN_L P17(BTN_OUT) BATTERY ONLY: 05 LTC2900 V3(1.8V) U7870 (PAGE 66) PP1V25_S0_ISNS (6A MAX CURRENT) VIN PM_ENET_EN Q3801 PWR_BUTTON(P90) PM_SLP_S5_L U5430 IMVP_VR_ON PLT_RST* SMC_ONOFF_L Q7072 1V8S3_PGOOD 99ms DLY IMVP_VR_ON(P16) PM_RSMRST_L RSMRST_IN(P13) V4(1.25V) P3V3S3_SS PGOOD FWPWR_EN_L_DIV SMC_ADAPTER_EN RSMRST_PWRGD VOUT U3850 TPS79501 (PAGE 36) Q7010 PWRGD(P12) S0PGOOD_PWROK V2(3.3V) PP1V8_S3_ISNS P1V8_S3_IOUT TPS511160 U7500 (PAGE 62) RST* EN A VOUT2 RSMRST_OUT(P15) ALL_SYS_PWRGD PP3V3_ENET V1(5V) PM_SLP_S3_LS5V SMC P1V8P1V5P1V05S0_PGOOD Q3810 PM_SLP_S3_L PM_SLP_S3_L SLP_S3* 10 P3V3GPU_SS 0.9V A.0.0 OF 92 A D D C C B B Power Block Diagram SYNC_MASTER=N/A A SYNC_DATE=N/A NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC SCALE SHT NONE REV 051-7431 A.0.0 OF 92 A BOM Variants TABLE_BOMGROUP_HEAD BOM NUMBER BOM NAME BOM OPTIONS 630-9092 PCBA,2.6GHZ,512VRAM-HY,M88 M88_COMMON,CPU_2_6GHZ,FB_512_HYNIX,EEE_Z3K 630-9093 PCBA,2.6GHZ,512VRAM-SAM,M88 M88_COMMON,CPU_2_6GHZ,FB_512_SAMSUNG,EEE_Z3L 630-9225 PCBA,2.5GHZ,512VRAM-HY,M88 M88_COMMON,CPU_2_5GHZ,FB_512_HYNIX,EEE_ZVW 630-9228 PCBA,2.5GHZ,512VRAM-SAM,M88 M88_COMMON,CPU_2_5GHZ,FB_512_SAMSUNG,EEE_ZVX TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM D D BOM Groups TABLE_BOMGROUP_HEAD BOM GROUP BOM OPTIONS M88_COMMON COMMON,ALTERNATE,M88_COMMON1,M88_COMMON2,M88_DEBUG,M88_PROGPARTS M88_COMMON1 BKLT_5V_PWR,ISL9504B,ONEWIRE_PU,GPUVID_1P23V M88_COMMON2 P1V8S3_1V8,SMS_MOT_DIS,YUKON_ULTRA,VGA_TERM_CONN M88_DEBUG SMC_DEBUG_NO,XDP,LPCPLUS M88_PROGPARTS BOOTROM_PROG,SMC_PROG BOM GROUP BOM OPTIONS FB_256_SAMSUNG VRAM4,VRAM_16M,VRAM_SAMSUNG,VRAM_256_SAMSUNG FB_256_HYNIX VRAM4,VRAM_16M,VRAM_HYNIX,VRAM_256_HYNIX FB_512_SAMSUNG VRAM8,VRAM_16M,VRAM_SAMSUNG,VRAM_512_SAMSUNG FB_512_HYNIX VRAM8,VRAM_16M,VRAM_HYNIX,VRAM_512_HYNIX TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_HEAD TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM Bar Code Labels / EEE #’s C PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL 826-4393 LBL,P/N LABEL,PCB,28MM X MM [EEE:Z3K] CRITICAL BOM OPTION EEE_Z3K 826-4393 LBL,P/N LABEL,PCB,28MM X MM [EEE:Z3L] CRITICAL EEE_Z3L 826-4393 LBL,P/N LABEL,PCB,28MM X MM [EEE:ZVW] CRITICAL EEE_ZVW 826-4393 LBL,P/N LABEL,PCB,28MM X MM [EEE:ZVX] CRITICAL EEE_ZVX C Module Parts B PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL 337S3559 IC,PDC,SR,PRQ,2.6G,35W,800FSB,6M,BGA U1000 CRITICAL BOM OPTION CPU_2_6GHZ 337S3560 IC,PDC,SR,PRQ,2.5G,35W,800FSB,6M,BGA U1000 CRITICAL CPU_2_5GHZ 338S0509 IC,GPU,NV,G84M,BGA U8000 CRITICAL 338S0432 IC,NB,CRESTLINE,GM,C0,PRQ,ROHS-SPECIAL,965PM U1400 CRITICAL 338S0434 IC,SB,ICH8M,B1,PRQ,BGA U2300 CRITICAL 353S1651 IC,ISL9504B,2PH IMVP6 REG,PMON,QFN48 U7100 CRITICAL 359S0130 IC,SLG2AP101,LW PWR CLK GEN,CK505,QFN68 U2900 CRITICAL 338S0386 IC,88E8058,GIGABIT ENET XCVR,64P QFN U3700 CRITICAL ISL9504B 338S0274 IC,SMC,HS8/2116 U4900 CRITICAL 341S2194 IC,SMC,DEVELOPMENT,M88 U4900 CRITICAL SMC_PROG 335S0384 IC,16MBIT 8-PIN SPI SERIAL FLASH,SOIC8 U6100 CRITICAL BOOTROM_BLANK 341S2192 IC,EFI ROM,DEVELOPMENT,M87 U6100 CRITICAL BOOTROM_PROG 333S0423 IC,SGRAM,GDDR3,16MX32,800MHZ,136 FBGA U8400,U8450,U8500,U8550 CRITICAL VRAM_256_SAMSUNG 333S0423 IC,SGRAM,GDDR3,16MX32,800MHZ,136 FBGA U8400,U8450,U8500,U8550,U9100,U9150,U9200,U9250 CRITICAL VRAM_512_SAMSUNG 333S0424 IC,SGRAM,GDDR3,16MX32,900MHZ,136 FBGA U8400,U8450,U8500,U8550 CRITICAL VRAM_256_HYNIX 333S0424 IC,SGRAM,GDDR3,16MX32,900MHZ,136 FBGA U8400,U8450,U8500,U8550,U9100,U9150,U9200,U9250 CRITICAL VRAM_512_HYNIX SMC_BLANK B Alternate Parts TABLE_ALT_HEAD PART NUMBER ALTERNATE FOR PART NUMBER 157S0011 BOM OPTION REF DES COMMENTS: 157S0030 ALL E&E alt to TDK/BiTech magnetics 138S0603 138S0602 ALL Murata alt to Samsung 22uF acoustic caps 353S1681 353S1294 ALL TI alternate to National 376S0543 376S0466 ALL AOS alternate to Siliconix Si4413 TABLE_ALT_ITEM TABLE_ALT_ITEM TABLE_ALT_ITEM TABLE_ALT_ITEM TABLE_ALT_ITEM 152S0683 152S0276 ALL Mag Layers alternate to Dale/Vishay 104S0024 104S0017 ALL Panasonic alternate to Cyntec 128S0083 128S0165 ALL alternate to halogen free Sanyo 330uF C2 tant 128S0113 128S0160 ALL alternate to halogen free Sanyo 220uF 35 mohm tant 128S0115 128S0150 ALL alternate to halogen free Sanyo 150uF tant 128S0122 128S0157 ALL alternate to Halogen free Sanyo 220uF 15 mohm tant 128S0057 128S0147 ALL alternate to Halogen free Sanyo 100uF tant BOM Configuration TABLE_ALT_ITEM TABLE_ALT_ITEM A SYNC_MASTER=N/A SYNC_DATE=N/A TABLE_ALT_ITEM NOTICE OF PROPRIETARY PROPERTY TABLE_ALT_ITEM THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING TABLE_ALT_ITEM I TO MAINTAIN THE DOCUMENT IN CONFIDENCE TABLE_ALT_ITEM II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART TABLE_ALT_ITEM 128S0056 128S0175 ALL alternate to Halogen free Sanyo 330uf D3 tant 376S0448 376S0445 ALL Si7806ADN for FSM6296 SIZE TABLE_ALT_ITEM DRAWING NUMBER D APPLE INC SCALE SHT NONE REV 051-7431 A.0.0 OF 92 A Proto: DVT (cont): See earlier schematics for info about releases 0.0.1 - 4.0.0 14.0.0: 10/12/07 10/12/07 10/12/07 10/12/07 10/12/07 14.1.0: 10/19/07 10/19/07 14.5.0: 10/24/07 10/24/07 10/24/07 16.0.0: 11/01/07 11/01/07 17.0.0: 11/06/07 11/06/07 EVT: D 5.0.0: 08/03/07 Page 5: Removed Q4690 BOM table entry BOM table is on CSA pg 46 6.0.0 & 5.1.0: 08/10/07 Synced to M87 MLB label 4.3.0 08/10/07 Page 3: Revised power block diagram 08/10/07 Page 10-12: Updated U1000 CPU part number to reflect latest Penryn pin-out 08/10/07 Page 37: T3900,T3901 magnetics changed to 157S0053 08/10/07 Page 65: Changed L7810 3.425V G3 Hot inductor to 152S0301 R7070 changed from 100K to 10K 6.1.0: 08/14/07 Synced to M87 MLB label 5.1.0 08/14/07 Page 49: Changed Q5322 to SOT23 part same as M87 08/14/07 Page 75: Changed GPU VID pull up/downs to 2.2K ohms 6.2.0: 08/16/07 Removed Rev B Silego clock chip as alternate 08/16/07 Page 51: Temp Sensors: Changed U5500 and U5570 to EMC1043-1 APN 353S1947 7.0.0: 08/17/07 Page 48: Changed SMBus SMC "A" pull ups R5270 and R5271 to 3.3K to improve rise time on SCL 7.1.0: 08/22/07 Page 9,34: Added GPIOs to support iPhone headset ICH8 GPIO 22 IPHS_SW_BIAS_EN_L routes to JJ3400.63 18.0.0: 08/22/07 Page 9,34: Removed R3410 and R3411 ICH8 GPIO IPHS_SW_INT routes to JJ3400.65 12/10/07 08/22/07 Synced M87 MLB label 6.2.0 18.1.0: 08/22/07 Page 51: Temp sensors: Added R5501,R5502,R5571,R5572 pull ups on U5500 and U5570 12/12/07 08/22/07 Page 61: R7455 changed to 7.5K to change max load current margin on PP1V05 12/12/07 08/22/07 Page 90: Changed frame buffer net physical type to GDDR3_50SE 12/12/07 08/22/07 Synced M87 LIO label 1.5.0 18.2.0: 08/22/07 Page 66: U7901 voltage follower changed from OPA333 to OPA705 12/13/07 08/22/07 Page 82: Changed L9891,L9893,L9894 to 155S0220 18.3.0: 7.2.0: 12/16/07 08/23/07 Page 5: Changed CPU parts to ES2, B1 for EVT A.0.0: 08/23/07 Page 9: IPHS_SW_BIAS_EN_L now connected to SB_SLOAD (GPIO 38) 12/18/07 08/23/07 Synced M87 MLB label 6.5.0 08/23/07 Page 50: Current Sensors: Changed U5410 and U5440 to MAX4245 Changed R5413 and R5443 to 0.005 ohm resistors 08/23/07 Page 91: Added diff pair properties to new current sensor pairs 08/23/07 Synced M87 LIO label 1.7.0 08/23/07 Page 66: Changed U7901 to MAX4245 Changed F7902 to 740S0055 08/23/07 Page 82: Add BOMOPTION OMIT to RX9892 8.0.0: 08/24/07 Page 25: Added NO STUFF to R2552 (was pull up on SB GPIO38 which is now used on IPHS) 08/24/07 Page 59: CPU Vcore supply changes per characterization Changed L7100 and L7101 to 152S0624 Changed C7134 to 0.01uF 132S0042 8.1.0: 08/24/07 Synced M87 MLB label 8.2.0 Page 5,75: Changed BOM option to GPUVID_1P23V Page 73: Changed R5491 and R5493 to 6.81K to allow full resolution of GPUVCORE current sense Page 50: Adding C5411,C5412,C5441,C5442 feedback caps for current sense op amps Page 66: Changed R7920 to halogen free 107S0110 8.2.0: 08/29/07 Synced m87_mlb CSA pgs Major release label name : m87_mlb_051-7413_8.2.0 08/29/07 Changed net physical and net spacing to CRT_50S on these signals NB_CLK100M_DPLSS_P/N NB_CLK96M_DOT_P/N 8.3.0: 08/29/07 Changed the following filters to 155S0371 for supply issues: pg 43 L4600 pg 44 FL4735 pg 76 L9010,L9011 08/29/07 pg 80 L9460,L9464,L9468,L9476,L9480,L9484 8.4.0: 08/30/07 Changed the orientation on these filters to match layout: pg 43 L4600 pg 76 L9010,L9011 9.0.0: 08/30/07 RFA 529050 EVT Release of Schematic BOM and PCBF 9.1.0: BOM Changes only 09/04/07 Page 5: Added alternate sources for these parts: 09/04/07 152S0683 is the Mag layers alternate for Dale/Vishay inductors Page 81: Added FL9600 155S0372 to multi-touch trackpad power and GND Synced M87_MLB label: 12.1.0 Page 46: Changed to new Sleep LED circuit Deleted, Q5032,R5032,R5030 Added, C5030 Synced M*&_LIO label: 10.0.0 Changed R9807 to 5.1k Changed C9807 to 0.1uF Changed R9809 to 200k Changed Q5030 to new LED Driver IC Synced M87_MLB label: 12.2.0 Page 50: Named unnamed net on Q5030 Page 69: NO STUFF battery positive terminal varistor DZ6960 D Page 43: Changed L4605 ferrite bead to 155S0329 for lower DCR Page 57: Changed DZ6960-DZ6963 to 377S0068 These are NO STUFFs Page 90: Graphics constraints Changed all GDDR3_46SE constraints back to GDDR3_50SE Page 53: Changed U5750 TMP102 to RevE part 353S2039 with old part 353S1807 as alternate Page 59: CPU Vcore power supplychange C7134 to 0.022uF 132S0102 per Dayu Page 25: Removed NO STUFF BOM option from R2552, pull up on SB GPIO38 Synced M87_LIO label 14.0.0 pg 82 Changed C9805 to 2.2uF for LED power sequencing PVT: C B 09/04/07 09/04/07 09/04/07 10.0.0: 09/06/07 11.0.0: 09/11/07 09/11/07 09/11/07 09/11/07 09/11/07 09/11/07 09/11/07 Page 98: Changed R9808 to 200K, R9809 to 100K, C9802 to 0.033uF, C9807 to 0.33uF to improve Q9806 Vgs and sequencing Page 5: Updated CPUs to PRQ parts, removed XDP_CONN and GPU_TMP401 bom options and changed to SMC_DEBUG_NO for PVT Page 50: Removed ST SIL driver and returned to EVT’s BJT-driven current source Page 98: Changed C9805 to actual 2.2uF part (removed table entry) Page 13: NO STUFFed R1330/R1331 since the LVDS_CTRL_DATA/CLK lines are grounded Page 54: Added C8992/R8992 to provide differential sense option Release as Rev A C 128S0164 is the Kemet alternate to Sanyo caps 104S0023 is the Panasonic alternate to Cyntec resistors Page 50: Changed R5425 and R5435 to 104S0023 B HF capacitor substitution, with halogen parts as alternates pg Alternates BOM table updates Page 57: Removed NO STUFF from DZ6960 (377S0044), ESD diode on BATT_POS per Page 5: Removed alternate to 128S0164 Kemet 220uF tantalum cap at C7540 and Added BOM variants and EEE codes for 2.5GHz: 630-9225: ZVW PCBA,2.5GHZ,512VRAM-HY,M88 630-9228: ZVX PCBA,2.5GHZ,512VRAM-SAM,M88 Page 62: Removed OMIT property and BOM option table to make C7540 and C7541 Page 82: LCD Backlight Added OMIT properties and BOM option table to change Chris C7541 only 128S0073 these beads to 155S0220: L9891,L9893,L9894 DVT: A 11.1.0: 09/12/07 Page 66: Swapped U7901 pins and signals (positive and negative inputs) 11.2.0: 09/26/07 Synced M*& MLB label 10.2.0 09/26/07 Page 50 & 75: GPUVCORE: Current sense to use IMVP6 IMON + Non-inverting Opamp removed R8992,C8992 09/26/07 Page 65: Changed C7860 to 0.0047uF (radar://5468257 12.0.0: 09/28/07 Removed BOM tables and OMIT BOM options from HF capacitor substitution, with halogen parts as alternates 09/28/07 Synced M87 MLB label 10.3.0 09/28/07 Page 50: updating GPUVcore current sense resistor values for gain of 4.83 12.0.0: 10/01/07 Synced M87 LIO label 9.0.0 Added R9810 10/01/07 Synced M87 LIO label 7.0.0 10/01/07 M87/M88 MLB/LED: LED driver current mirror can not be disabled + power sequencing issue TASK: M87 LIO changes to support LED board 10/01/07 Page 5: Added 376S0448 as alternate for 376S0445 13.0.0: 10/05/07 Page 5: Removed HDCP ROM Removed U8770, R8770,R871, C8770 10/05/07 Page 75: GPU Vcore supply: Changed L8920 from 152S0525 to 152S0697.Dale 0.9uH 27A inductor has smaller pad size than Vishay IHLP4040 13.1.0: 10/09/07 Synced m87_MLB label Change 72968 Page 5: Changed Module parts for new Penryn APNs 10/09/07 Page 93: M87/88 1V8 FB DC converter transient response improve/BOM change 10/09/07 R9308 change to 40.2k, 0402, 1%; C9308 change to 680pF, 0402, 10V, 10% C9307 change to 68pF, 0402, 10V, 10% Revision History SYNC_MASTER=N/A SYNC_DATE=N/A NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC SCALE SHT NONE REV 051-7431 A.0.0 OF 92 A Functional Test Points ICT Test Points Fan Connectors Battery Digital Connector FUNC_TEST I498 I497 I496 D PP5V_S0 TRUE TRUE FAN_LT_PWM FAN_LT_TACH 27 42 47 49 52 54 58 59 65 80 81 82 I509 I507 52 I506 52 I531 TRUE TRUE I495 I494 FAN_RT_PWM FAN_RT_TACH 52 I530 I529 I492 I493 I424 I423 I422 I421 I420 I419 I418 I417 I416 I415 I414 I413 I412 I411 C I410 I409 I408 I407 I406 I405 I404 SMC_BS_ALRT_L SMBUS_SMC_BSA_SCL SMBUS_SMC_BSA_SDA BATT_POS GND TRUE GND MAKE_ BASE TRUE TRUE PP3V42_G3H PP5V_S0 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE LPC_AD LPC_AD LPC_FRAME_L PM_CLKRUN_L PCI_FW_GNT_L SMC_TMS DEBUG_RESET_L SMC_TRST_L SMC_TDO SMC_MD1 SMC_TX_L FWH_INIT_L PCI_CLK33M_LPCPLUS LPC_AD LPC_AD INT_SERIRQ PM_SUS_STAT_L SMC_TDI SMC_TCK SMC_RESET_L SMC_NMI SMC_RX_L LINDACARD_GPIO 28 43 45 46 47 48 57 65 66 81 I436 27 42 47 49 52 54 58 59 65 80 81 82 FUNC_TEST TRUE TRUE TRUE 45 48 57 88 I558 45 48 57 88 I557 57 66 I556 I555 I554 (HOST_DETECT_L) I552 I553 I550 I551 PP18V5_DCIN PPBUS_G3H GND 57 82 40 49 57 58 59 Request for test points Request for test points 60 61 62 63 66 75 79 I548 I544 Request for at least 10 GND test points I546 23 45 47 25 45 47 NOTE: 10 additional GND test points are called out separately in these notes I571 28 47 45 46 47 I519 45 47 I442 I520 I521 B I569 I570 TRUE TRUE 16 TRUE NC_NB_NC TP_NB_NC 16 TRUE NC_NB_RSVD TRUE NC_NB_RSVD TP_NB_RSVD TP_NB_RSVD 16 10 14 83 10 14 83 10 14 83 10 14 83 10 14 83 10 14 83 10 14 83 10 14 83 10 14 83 10 14 83 10 14 83 NC_CPU_RSVD5 10 TRUE TRUE PPVBATT_G3_RTC GND 28 Current Sense Calibration 47 Backlight Connector FUNC_TEST 23 45 47 23 45 47 I431 25 45 47 I430 FUNC_TEST TRUE TRUE ISENSE_CAL_EN PP5V_S0 TRUE TRUE PPVCORE_S0_CPU PPVCORE_GPU 25 45 46 47 45 49 I533 27 42 47 49 52 54 58 59 65 80 81 82 I534 I536 45 46 47 I427 45 46 47 I426 11 12 49 59 49 68 75 45 46 47 TPs per I535 TRUE TRUE TRUE TRUE TRUE BKLT_PWR BKLT_GND BKLT_P5V_EN BKLT_PWM GND 81 82 81 82 C 81 82 81 82 GND TRUE TPs, with each of above TP pairs 45 47 43 45 46 47 25 47 IR & Sleep LED Connector FUNC_TEST I516 I515 ALS_GAIN LTALS_OUT GND TRUE TRUE TRUE FUNC_TEST PP5V_S3_CAMERA_F USB_CAMERA_F_N USB_CAMERA_F_P 44 I539 44 91 I540 44 91 I542 34 45 54 I541 34 54 TRUE TRUE TRUE TRUE TRUE PP5V_S3 USB_IR_N USB_IR_P SYS_LED_ANODE GND 44 46 58 81 24 81 86 24 81 86 46 81 Other Func Test Points FUNC_TEST HSTHMSNS_D_P HSTHMSNS_D_N RSFSTHMSNS_D_P RSFSTHMSNS_D_N CPUTHMSNS_D2_P CPUTHMSNS_D2_N 51 91 I432 TRUE TRUE PM_SYSRST_L SMC_ONOFF_L 25 28 45 45 46 81 51 91 51 91 51 91 51 91 51 91 B System Validation TPs FUNC_TEST TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE I561 FUNC_TEST CPU_PWRGD CPU_DPSLP_L PM_DPRSLPVR CPU_DPSLP_L PM_LAN_ENABLE PCI_RST_L PM_RSMRST_L PM_SB_PWROK SB_RTC_RST_L PM_STPCPU_L PM_STPPCI_L VR_PWRGD_CLKEN VR_PWRGOOD_DELAY FSB_CPURST_L FSB_CPUSLP_L FSB_DPWR_L NB_SB_SYNC_L PM_BMBUSY_L 10 13 23 83 10 23 83 16 25 59 83 10 23 83 25 45 24 28 25 45 25 28 23 28 25 29 30 25 29 30 25 28 16 28 59 10 13 14 83 10 14 83 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE IMVP_VR_ON IMVP_DPRSLPVR PM_SLP_S3_L PM_S4_STATE_L PM_SLP_S5_L PM_ENET_EN P1V8P1V5P1V05S0_PGOOD CPU_DPRSTP_L IMVP6_VID FSB_CLK_CPU_N FSB_CLK_CPU_P PLT_RST_L NB_RESET_L GPU_RESET_L SMC_LRESET_L TRUE TRUE TRUE TRUE TRUE TRUE CPU_STPCLK_L FSB_CLK_NB_P FSB_CLK_NB_N NB_CLKREQ_L NB_CLK100M_PCIE_P NB_CLK100M_PCIE_N 45 59 59 83 25 35 36 40 45 49 58 62 65 25 34 43 45 58 65 25 45 46 36 61 65 61 62 63 65 10 16 23 59 83 12 59 83 10 29 30 88 10 29 30 88 24 28 82 16 28 28 67 28 45 10 14 83 16 25 16 25 A 10 23 83 14 29 30 88 14 29 30 88 Functional / ICT Test 16 29 16 29 30 88 SYNC_MASTER=MASTER 16 29 30 88 SYNC_DATE=MASTER NOTICE OF PROPRIETARY PROPERTY TRUE CPU_THERMTRIP_R 23 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC REV 051-7431 SCALE SHT NONE D 10 14 83 43 45 46 47 I433 I443 I559 10 14 83 30 47 88 FUNC_TEST I567 TRUE NC_CPU_RSVD5 10 14 83 10 14 83 FUNC_TEST Thermal Diode Connectors TRUE TRUE TRUE TRUE TRUE TRUE FSB_A_L FSB_ADS_L FSB_ADSTB_L FSB_BNR_L FSB_BREQ0_L FSB_D_L FSB_DBSY_L FSB_DINV_L FSB_DRDY_L FSB_DSTB_L_N FSB_DSTB_L_P FSB_HIT_L FSB_HITM_L FSB_LOCK_L FSB_REQ_L 45 47 I517 I568 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE RTC Battery Connector 45 46 47 FUNC_TEST TRUE TRUE TRUE NO_TEST 24 38 47 87 Left Clutch Barrel Connector I447 I547 I545 Left ALS I448 I549 23 45 47 23 45 47 NB NO_TESTs MAKE_ BASE NO_TEST 45 46 57 Left I/O Power Connector FUNC_TEST I491 TRUE TRUE TRUE TRUE TRUE 52 LPC+ Debug Connector I490 CPU FSB NO_TESTs FUNC_TEST TRUE A.0.0 OF 92 A 82 79 75 61 60 59 40 58 57 49 66 63 62 "G3Hot" (Always-Present) Rails PPBUS_G3H D 40 49 57 58 59 60 61 62 63 66 75 79 82 40 49 57 58 59 60 61 62 63 66 75 79 82 40 49 57 58 59 60 61 62 63 66 75 79 82 40 49 57 58 59 60 61 62 63 66 75 79 82 40 49 57 58 59 60 61 62 63 66 75 79 82 40 49 57 58 59 60 61 62 63 66 75 79 82 40 49 57 58 59 60 61 62 63 66 75 79 82 40 49 57 58 59 60 61 62 63 66 75 79 82 40 49 57 58 59 60 61 62 63 66 75 79 82 40 49 57 58 59 60 61 62 63 66 75 79 82 40 49 57 58 59 60 61 62 63 66 75 79 82 40 49 57 58 59 60 61 62 63 66 75 79 82 40 49 57 58 59 60 61 62 63 66 75 79 82 40 49 57 58 59 60 61 62 63 66 75 79 82 40 49 57 58 59 60 61 62 63 66 75 79 82 PPDCIN_G3H PPDCIN_G3H MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=18.5V MAKE_BASE=TRUE PP3V42_G3H 65 58 55 54 51 50 48 38 36 81 PP3V3_S3 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 50 38 32 31 91 62 57 65 66 PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H 28 43 45 46 47 48 57 65 66 81 28 43 45 46 47 48 57 65 66 81 28 43 45 46 47 48 57 65 66 81 28 43 45 46 47 48 57 65 66 81 28 43 45 46 47 48 57 65 66 81 28 43 45 46 47 48 57 65 66 81 28 43 45 46 47 48 57 65 66 81 28 43 45 46 47 48 57 65 66 81 MAX I = ?.??A PP5V_S5 36 38 48 50 51 54 55 58 65 81 PP3V3_S0 PP5V_S5 PP5V_S5 PP5V_S3 27 42 43 58 60 61 62 63 65 75 79 27 42 43 58 60 61 62 63 65 75 79 27 42 43 58 60 61 62 63 65 75 79 27 42 43 58 60 61 62 63 65 75 79 27 42 43 58 60 61 62 63 65 75 79 27 42 43 58 60 61 62 63 65 75 79 27 42 43 58 60 61 62 63 65 75 79 27 42 43 58 60 61 62 63 65 75 79 27 42 43 58 60 61 62 63 65 75 79 27 42 43 58 60 61 62 63 65 75 79 27 42 43 58 60 61 62 63 65 75 79 27 42 43 58 60 61 62 63 65 75 79 PP5V_S3 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5V MAKE_BASE=TRUE PP5V_S3 PP5V_S3 B 44 46 58 81 44 46 58 81 PP5V_S3 PP5V_S3 82 58 54 27 49 47 80 65 81 52 42 59 PP5V_S0 44 46 58 81 44 46 58 81 PP5V_S0 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5V MAKE_BASE=TRUE PP5V_S0 27 42 47 49 52 54 58 59 65 80 81 82 27 42 47 49 52 54 58 59 65 80 81 82 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 A 44 46 58 81 27 42 47 49 52 54 58 59 65 80 81 82 27 42 47 49 52 54 58 59 65 80 81 82 27 42 47 49 52 54 58 59 65 80 81 82 27 42 47 49 52 54 58 59 65 80 81 82 27 42 47 49 52 54 58 59 65 80 81 82 27 42 47 49 52 54 58 59 65 80 81 82 27 42 47 49 52 54 58 59 65 80 81 82 27 42 47 49 52 54 58 59 65 80 81 82 27 42 47 49 52 54 58 59 65 80 81 82 27 42 47 49 52 54 58 59 65 80 81 82 27 42 47 49 52 54 58 59 65 80 81 82 PPVCORE_S0_CPU PPVCORE_S0_CPU MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.3 mm VOLTAGE=1.25V MAKE_BASE=TRUE PPVCORE_S0_CPU 39 40 64 39 40 64 PPVP_FW_PORTA_UF 39 40 64 D PPVP_FW_PORTA_UF 40 41 PPVP_FW_PORTB_UF 40 41 PP3V3_FW 39 40 41 64 MAKE_BASE=TRUE 16 18 41 40 21 50 16 18 21 50 PPVP_FW_PORTB_UF MAKE_BASE=TRUE PP3V3_FW MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V MAKE_BASE=TRUE 11 12 22 26 27 34 63 91 MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.25mm VOLTAGE=1.5V MAKE_BASE=TRUE PP3V3_FW PP3V3_FW PP3V3_FW PP3V3_FW 11 12 22 26 27 34 63 91 11 12 22 26 27 34 63 91 11 12 22 26 27 34 63 91 39 40 41 64 39 40 41 64 39 40 41 64 39 40 41 64 11 12 22 26 27 34 63 91 PP1V95_FW PP1V95_FW 11 12 22 26 27 34 63 91 11 12 22 26 27 34 63 91 39 64 MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.95V MAKE_BASE=TRUE 11 12 22 26 27 34 63 91 PP1V95_FW PP1V95_FW 11 12 22 26 27 34 63 91 11 12 22 26 27 34 63 91 39 64 39 64 "GPU" Rails 36 38 48 50 51 54 55 58 65 81 81 36 38 48 50 51 54 55 58 65 36 38 48 50 51 54 55 58 65 81 80 76 75 74 73 72 65 58 48 PP1V25_S0_ISNS 36 38 48 50 51 54 55 58 65 81 36 38 48 50 51 54 55 58 65 81 36 38 48 50 51 54 55 58 65 81 36 38 48 50 51 54 55 58 65 81 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 52 53 58 59 65 82 91 13 16 19 21 23 24 25 26 27 28 29 30 31 32 42 46 47 48 50 51 52 53 58 59 65 82 91 13 16 19 21 23 24 25 26 27 28 29 30 31 32 42 46 47 48 50 51 53 58 59 65 82 91 21 23 24 25 26 27 28 29 30 31 32 42 46 47 48 50 51 52 16 91 13 28 29 30 31 32 42 46 47 48 19 13 16 19 21 23 24 25 26 27 50 51 52 53 58 59 65 82 65 82 91 32 42 46 47 48 50 51 52 53 58 13 16 19 21 23 24 25 26 27 28 29 30 31 59 52 53 58 59 65 82 91 13 16 19 21 23 24 25 26 27 28 29 30 31 32 42 46 47 48 50 51 PP1V05_S0 62 32 31 16 8 19 21 26 27 50 65 67 69 72 PP3V3_S0GPU 19 21 26 27 50 65 67 69 72 19 21 26 27 50 65 67 69 72 19 21 26 27 50 65 67 69 72 19 21 26 27 50 65 67 69 72 19 21 26 27 50 65 67 69 72 PP0V9_S0 48 58 65 75 76 80 48 58 65 75 76 80 48 58 65 75 76 80 48 58 65 75 76 80 48 58 65 75 76 80 72 73 74 72 73 74 72 73 74 PP3V3_S0GPU_TMDS 72 73 74 48 58 65 72 73 74 75 76 80 48 58 65 72 73 74 75 76 80 48 58 65 72 73 74 75 76 80 PP3V3_S0GPU_TMDS 30 46 50 61 10 11 12 13 14 18 19 21 23 26 27 PP3V3_S0GPU_TMDS PP3V3_S0GPU_TMDS PP1V8_S0GPU 10 11 12 13 14 18 27 30 46 50 61 10 11 12 13 14 18 27 30 46 50 61 30 46 10 11 12 13 14 18 19 21 23 26 27 10 11 12 13 14 18 27 30 46 50 61 10 11 12 13 14 18 27 30 46 50 61 PP1V8_S0GPU 16 31 32 62 75 68 49 PP0V9_S3_MEM_VREF PP0V9_S3_MEM_VREF PP0V9_S3_MEM_VREF PP0V9_S3_MEM_VREF 16 31 32 62 PP0V9_S0 33 62 50 79 19 21 23 26 50 61 PP1V8_S0GPU_ISNS 50 65 68 69 70 71 74 77 78 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.8V MAKE_BASE=TRUE 19 21 23 26 19 21 23 26 PP1V8_S0GPU_ISNS PP1V8_S0GPU_ISNS PP1V8_S0GPU_ISNS PP1V8_S0GPU_ISNS PP1V8_S0GPU_ISNS 18 21 50 PP0V9_S3_MEM_VREF 50 79 19 21 23 26 10 11 12 13 14 18 19 21 23 26 27 30 46 50 61 10 11 12 13 14 18 19 21 23 26 27 30 46 50 61 18 21 50 73 74 80 PP1V8_S0GPU PP1V8_S0GPU_ISNS PPVCORE_S0_NB_R 73 74 80 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.8V MAKE_BASE=TRUE 10 11 12 13 14 18 19 21 23 26 27 30 46 50 61 10 11 12 13 14 18 19 21 23 26 27 30 46 50 61 10 11 12 13 14 18 19 21 23 26 27 30 46 50 61 PPVCORE_S0_NB_R 73 74 80 MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V MAKE_BASE=TRUE 10 11 12 13 14 18 19 21 23 26 27 30 46 50 61 PPVCORE_GPU 50 65 68 69 70 71 74 77 78 50 65 68 69 70 71 74 77 78 PPVCORE_GPU 49 68 75 PPVCORE_GPU 16 31 32 62 49 68 75 16 31 32 62 PP0V9_S0 33 62 "ENET" Rails PP3V3_ENET PP3V3_ENET 35 36 MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V MAKE_BASE=TRUE Power Aliases PP3V3_ENET PP3V3_ENET 35 36 NOTICE OF PROPRIETARY PROPERTY 35 36 MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.9V MAKE_BASE=TRUE GND Yukon EC will not be supported SYNC_DATE=(MASTER) 35 36 PP1V9_ENET PP1V9_ENET SYNC_MASTER=(MASTER) THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING PP1V9_ENET I TO MAINTAIN THE DOCUMENT IN CONFIDENCE 35 36 11 12 49 59 II NOT TO REPRODUCE OR COPY IT PP1V25_S0 PP1V25_S0 61 58 35 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.25V MAKE_BASE=TRUE GND PP1V25_S0 PP1V25_ENET III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART PP1V25_ENET 35 58 61 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.25V MAKE_BASE=TRUE SIZE PP1V25_ENET PP1V25_ENET 50 58 35 58 61 DRAWING NUMBER D 35 58 61 APPLE INC REV 051-7431 SCALE SHT NONE B 50 65 68 69 70 71 74 77 78 50 65 68 69 70 71 74 77 78 50 65 68 69 70 71 74 77 78 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.2V MAKE_BASE=TRUE 16 31 32 62 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0.9V MAKE_BASE=TRUE 11 12 49 59 58 50 C 72 73 74 19 21 26 27 50 65 67 69 72 MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0.9V MAKE_BASE=TRUE 82 91 47 48 50 51 52 53 58 59 65 21 23 24 25 26 27 28 29 30 31 32 42 46 16 53 58 59 65 82 91 13 28 29 30 31 32 42 46 47 48 19 13 16 19 21 23 24 25 26 27 50 51 52 32 42 46 47 48 50 51 52 23 24 25 26 27 28 29 30 31 53 58 59 65 82 91 21 19 82 91 16 48 50 51 52 53 58 59 65 27 28 29 30 31 32 42 46 47 13 23 24 25 26 13 16 19 21 91 36 35 65 82 32 42 46 47 48 50 51 52 53 58 13 16 19 21 23 24 25 26 27 28 29 30 31 59 52 53 58 59 65 82 91 13 16 19 21 23 24 25 26 27 28 29 30 31 32 42 46 47 48 50 51 48 58 65 72 73 74 75 76 80 48 58 65 72 73 74 75 76 80 48 58 65 72 73 74 75 76 80 19 21 26 27 50 65 67 69 72 MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0.9V MAKE_BASE=TRUE 65 82 91 46 47 48 50 51 52 53 58 59 21 23 24 25 26 27 28 29 30 31 32 42 16 52 53 58 59 65 82 91 13 28 29 30 31 32 42 46 47 48 19 13 16 19 21 23 24 25 26 27 50 51 50 51 52 53 58 59 65 82 91 25 26 27 28 29 30 31 32 42 46 13 16 19 21 23 24 47 48 62 33 48 58 65 72 73 74 75 76 80 19 21 26 27 50 65 67 69 72 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP0V9_S3_MEM_VREF 48 58 65 72 73 74 75 76 80 PP3V3_S0GPU PP3V3_S0GPU PP3V3_S0GPU 19 21 26 27 50 65 67 69 72 19 21 26 27 50 65 67 69 72 PP1V05_S0 65 82 91 32 42 46 47 48 50 51 52 53 58 13 16 19 21 23 24 25 26 27 28 29 30 31 59 52 53 58 59 65 82 91 13 16 19 21 23 24 25 26 27 28 29 30 31 32 42 46 47 48 50 51 36 35 8 19 21 26 27 50 65 67 69 72 PP3V3_S0GPU PP3V3_S0GPU PP3V3_S0GPU PP3V3_S0GPU PP3V3_S0GPU PP3V3_S0GPU PP3V3_S0GPU PP3V3_S0GPU 19 21 26 27 50 65 67 69 72 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V MAKE_BASE=TRUE PPVCORE_S0_NB_R PP3V3_S0GPU MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V MAKE_BASE=TRUE 19 21 26 27 50 65 67 69 72 80 74 73 23 21 19 18 14 13 12 11 10 61 50 46 30 27 26 91 28 29 30 31 32 42 46 47 48 13 16 19 21 23 24 25 26 27 50 51 52 53 58 59 65 82 65 82 91 32 42 46 47 48 50 51 52 53 58 13 16 19 21 23 24 25 26 27 28 29 30 31 59 52 53 58 59 65 82 91 13 16 19 21 23 24 25 26 27 28 29 30 31 32 42 46 47 48 50 51 91 28 29 30 31 32 42 46 47 48 13 16 19 21 23 24 25 26 27 50 51 52 53 58 59 65 82 65 82 91 32 42 46 47 48 50 51 52 53 58 13 16 19 21 23 24 25 26 27 28 29 30 31 59 52 53 58 59 65 82 91 13 16 19 21 23 24 25 26 27 28 29 30 31 32 42 46 47 48 50 51 53 58 59 65 82 91 21 23 24 25 26 27 28 29 30 31 32 42 46 47 48 50 51 52 16 91 13 28 29 30 31 32 42 46 47 48 19 13 16 19 21 23 24 25 26 27 50 51 52 53 58 59 65 82 65 82 91 32 42 46 47 48 50 51 52 53 58 13 16 19 21 23 24 25 26 27 28 29 30 31 59 52 53 58 59 65 82 91 13 16 19 21 23 24 25 26 27 28 29 30 31 32 42 46 47 48 50 51 65 82 91 42 46 47 48 50 51 52 53 58 59 23 24 25 26 27 28 29 30 31 32 13 16 19 21 52 50 21 18 8 13 16 19 21 23 24 25 26 27 28 29 30 31 32 42 46 47 48 50 51 53 58 59 65 82 91 65 82 91 32 42 46 47 48 50 51 52 53 58 13 16 19 21 23 24 25 26 27 28 29 30 31 59 52 53 58 59 65 82 91 13 16 19 21 23 24 25 26 27 28 29 30 31 32 42 46 47 48 50 51 PP3V3_S0GPU 19 21 26 27 50 65 67 69 72 PP1V25_S0_ISNS PP1V25_S0_ISNS PP1V25_S0_ISNS PP1V25_S0_ISNS PP1V25_S0_ISNS PP1V25_S0_ISNS PP1V25_S0_ISNS PP1V25_S0_ISNS PP1V25_S0_ISNS PP1V25_S0_ISNS PP1V25_S0_ISNS PP1V25_S0_ISNS PP1V25_S0_ISNS PP1V25_S0_ISNS 36 38 48 50 51 54 55 58 65 81 PP3V3_S0 PP1V25_S0_ISNS MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.25V MAKE_BASE=TRUE 36 38 48 50 51 54 55 58 65 81 Chipset "VCore" Rails 11 59 49 12 PPVP_FW PPVP_FW PPVP_FW 36 38 48 50 51 54 55 58 65 81 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V MAKE_BASE=TRUE 27 42 43 58 60 61 62 63 65 75 79 PP5V_S5 PP5V_S5 PP5V_S5 PP5V_S5 PP5V_S5 PP5V_S5 PP5V_S5 PP5V_S5 PP5V_S5 PP5V_S5 PP5V_S5 PP5V_S5 44 81 58 46 27 42 43 58 60 61 62 63 65 75 79 39 40 64 36 38 48 50 51 54 55 58 65 81 28 43 45 46 47 48 57 65 66 81 28 43 45 46 47 48 57 65 66 81 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5V MAKE_BASE=TRUE 41 40 PP1V5_S0 PP1V5_S0 PP1V5_S0 PP1V5_S0 PP1V5_S0 PP1V5_S0 PP1V5_S0 PP1V5_S0 PP1V5_S0 36 38 48 50 51 54 55 58 65 81 40 64 PPVP_FW 16 18 21 50 PP1V5_S0 24 25 26 27 28 46 48 56 58 60 65 76 91 24 25 26 27 28 46 48 56 58 60 65 76 91 24 25 26 27 28 46 48 56 58 60 65 76 91 PPBUS_FW_FWPWRSW_F MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.3 mm VOLTAGE=33V MAKE_BASE=TRUE 31 32 38 50 62 91 64 41 40 39 PP1V5_S0 91 63 34 27 26 22 12 11 8 24 25 26 27 28 46 48 56 58 60 65 76 91 24 25 26 27 28 46 48 56 58 60 65 76 91 PPVP_FW 31 32 38 50 62 91 PP1V8_S3_ISNS PP1V8_S3_ISNS 24 25 26 27 28 46 48 56 58 60 65 76 91 24 25 26 27 28 46 48 56 58 60 65 76 91 PPBUS_FW_FWPWRSW_F MAKE_BASE=TRUE 31 32 38 50 62 91 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.8V MAKE_BASE=TRUE 5V Rails 63 62 61 42 27 60 58 43 79 75 65 31 32 38 50 62 91 PP1V8_S3_ISNS PP1V8_S3_ISNS 24 25 26 27 28 46 48 56 58 60 65 76 91 24 25 26 27 28 46 48 56 58 60 65 76 91 24 25 26 27 28 46 48 56 58 60 65 76 91 PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3 64 40 PP1V8_S3 PP1V8_S3 PP1V8_S3 PP1V8_S3 24 25 26 27 28 46 48 56 58 60 65 76 91 24 25 26 27 28 46 48 56 58 60 65 76 91 60 65 76 91 24 25 26 27 28 46 48 56 58 PP3V3_S3 31 32 38 50 62 91 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.8V MAKE_BASE=TRUE 24 25 26 27 28 46 48 56 58 60 65 76 91 24 25 26 27 28 46 48 56 58 60 65 76 91 "FW" (FireWire) Rails PP1V8_S3 PP1V8_S3 24 25 26 27 28 46 48 56 58 60 65 76 91 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V MAKE_BASE=TRUE 57 65 66 MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.42V MAKE_BASE=TRUE C 1.8V-0.9V Rails PP3V3_S5 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V MAKE_BASE=TRUE 57 65 66 PPDCIN_G3H PPDCIN_G3H 57 48 47 28 46 45 43 81 66 65 40 49 57 58 59 60 61 62 63 66 75 79 82 3.3V-2.5V Rails PP3V3_S5 PPBUS_G3H MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.6V MAKE_BASE=TRUE PPBUS_G3H PPBUS_G3H PPBUS_G3H PPBUS_G3H PPBUS_G3H PPBUS_G3H PPBUS_G3H PPBUS_G3H PPBUS_G3H PPBUS_G3H PPBUS_G3H PPBUS_G3H PPBUS_G3H PPBUS_G3H PPBUS_G3H 65 57 66 A.0.0 OF 92 A 86 24 TP_USB_EXTDN TP_USB_EXTDN BI 24 86 86 24 TP_USB_EXTDP TP_USB_EXTDP BI 24 86 28 25 59 28 16 MAKE_BASE=TRUE MAKE_BASE=TRUE PM_SB_PWROK PM_SB_PWROK 25 28 VR_PWRGOOD_DELAY 16 28 59 PEG_CLK100M_GPU_P 29 30 67 88 PEG_CLK100M_GPU_N 29 30 67 88 SMC_SMS_INT 45 55 TP_EXTGPU_PWR_EN 23 MAKE_BASE=TRUE VR_PWRGOOD_DELAY MAKE_BASE=TRUE D D 88 67 30 29 PEG_CLK100M_GPU_P MAKE_BASE=TRUE 88 67 30 29 PEG_CLK100M_GPU_N MAKE_BASE=TRUE 55 45 23 SMC_SMS_INT MAKE_BASE=TRUE TP_EXTGPU_PWR_EN MAKE_BASE=TRUE 34 25 IPHS_SW_BIAS_EN_L 34 24 IPHS_SW_INT 66 46 45 31 IPHS_SW_BIAS_EN_L 25 34 IPHS_SW_INT 24 34 MAKE_BASE=TRUE MAKE_BASE=TRUE SMC_ENRGYSTR_LDO_EN SMC_ENRGYSTR_LDO_EN 45 46 66 TP_MEM_A_A TP_MEM_A_A 31 TP_MEM_B_A 32 MAKE_BASE=TRUE 32 TP_MEM_B_A MAKE_BASE=TRUE C C 82 28 24 82 73 72 82 73 72 Thermal Module Holes 24 28 82 72 73 82 72 73 82 GND_CHASSIS_RIGHT_FAN_NOTCH (to the left of small well on lower board edge near USB) GND_CHASSIS_BATTCONN_HOLE (to the left of DIMM cutout near board edge) ZT0985 Add blind vias per side to GND PLT_RST_L GPU_BL_PWM GPU_BKLT_EN All holes are plated through holes with two exceptions: Top Right GPU TM Hole Top CPU TM "Hole" PLT_RST_L GPU_BL_PWM GPU_BKLT_EN 195R106 ZT0975 ZT0970 195R106 195R106 Chassis GNDs ZT0901 195R106 Left CPU TM Hole GND 1 Right CPU TM Hole ZT0980 195R106 Bottom Left GPU TM Hole B B ZT0900 195R106 GND Frame holes GND MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.25mm VOLTAGE=0V Digital Ground GND MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.25mm VOLTAGE=0V GND MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.25mm VOLTAGE=0V GND MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.25mm VOLTAGE=0V RAM door (Torx) holes ZT0955 195R106 235R126 GND Chassis connection to be made at the mounting hole east of the LVDS connector A Signal Aliases MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.25mm VOLTAGE=0V GND GND SYNC_MASTER=MASTER MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.25mm VOLTAGE=0V MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.25mm VOLTAGE=0V MAKE_BASE=TRUE 1 GND MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.25mm VOLTAGE=0V GND MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.25mm VOLTAGE=0V GND THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING 195R106 235R126 SYNC_DATE=MASTER NOTICE OF PROPRIETARY PROPERTY ZT0965 ZT0935 GND MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.25mm VOLTAGE=0V ZT0930 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART GND SIZE SH0925 DRAWING NUMBER D OG-503040 REV 051-7431 A.0.0 SHLD-SM-LF APPLE INC SCALE SHT NONE OF 92 A OMIT 83 14 BI 83 14 BI 83 14 BI 83 14 BI 83 14 BI 83 14 BI 83 14 BI 83 14 BI 83 14 BI 83 14 BI 83 14 BI 83 14 BI 83 14 BI 83 14 BI 83 14 BI 83 14 BI 83 14 C BI 83 14 BI 83 14 BI 83 14 BI 83 14 BI 83 14 BI 83 14 BI 83 14 BI 83 14 BI 83 14 BI 83 14 BI 83 14 BI 83 14 BI 83 14 BI 83 14 BI 83 14 BI 83 14 BI 83 23 IN 83 23 OUT 83 23 IN 83 23 IN 83 23 IN 83 23 83 23 K3 H2 K2 J3 L1 REQ0* REQ1* REQ2* REQ3* REQ4* FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_ADSTB_L BI 83 14 FSB_REQ_L FSB_REQ_L FSB_REQ_L FSB_REQ_L FSB_REQ_L IN IN Y2 U5 R3 W6 U4 Y5 U1 R4 T5 T3 W2 W5 Y4 U2 V4 W3 AA4 AB2 AA3 V1 A6 A20M* A5 FERR* C4 IGNNE* CPU_STPCLK_L CPU_INTR CPU_NMI CPU_SMI_L D5 C6 B4 A3 M4 N5 T2 V3 B2 F6 D2 D22 D3 BR0* FSB_DEFER_L FSB_DRDY_L FSB_DBSY_L F1 FSB_BREQ0_L CPU_IERR_L CPU_INIT_L IN BI 14 83 BI 14 83 PP1V05_S0 IERR* INIT* D20 B3 LOCK* H4 FSB_LOCK_L RESET* RS0* RS1* RS2* TRDY* C1 F3 F4 G3 G2 FSB_CPURST_L FSB_RS_L FSB_RS_L FSB_RS_L FSB_TRDY_L HIT* HITM* G6 E4 FSB_HIT_L FSB_HITM_L BPM0* BPM1* BPM2* BPM3* PRDY* PREQ* TCK TDI TDO TMS TRST* DBR* AD4 AD3 AD1 AC4 AC2 AC1 AC5 AA6 AB3 AB5 AB6 C20 XDP_BPM_L XDP_BPM_L XDP_BPM_L XDP_BPM_L XDP_BPM_L XDP_BPM_L XDP_TCK XDP_TDI XDP_TDO XDP_TMS XDP_TRST_L XDP_DBRESET_L 83 14 83 BI BI 14 83 BI 14 83 BI 14 83 BI 14 83 10 11 12 13 14 18 19 21 23 26 27 30 46 50 61 R1002 PLACE TESTPOINT ON FSB_IERR_L WITH A GND 0.1" AWAY 54.9 1% 1/16W MF-LF 402 D 23 47 83 14 83 IN 13 14 83 IN 14 83 IN 14 83 IN 14 83 IN 14 83 OMIT A17* A18* A19* A20* A21* A22* A23* A24* A25* A26* A27* A28* A29* A30* A31* A32* A33* A34* A35* ADSTB1* CPU_A20M_L CPU_FERR_L CPU_IGNNE_L TP_CPU_RSVD0 TP_CPU_RSVD1 TP_CPU_RSVD2 TP_CPU_RSVD3 TP_CPU_RSVD4 NC_CPU_RSVD5 TP_CPU_RSVD6 TP_CPU_RSVD7 TP_CPU_RSVD8 DEFER* DRDY* DBSY* H5 F21 E1 BI STPCLK* LINT0 LINT1 SMI* BI 14 83 BI 14 83 BI 13 83 BI 13 83 BI 13 83 BI 13 83 BI 13 83 PP1V05_S0 10 11 12 13 14 18 19 21 23 26 27 30 46 50 61 R10031 83 14 BI 83 14 BI 1% 1/16W MF-LF 402 83 14 BI 83 14 BI 83 14 BI 83 14 BI 54.9 13 83 10 13 83 83 14 BI IN 10 13 83 83 14 BI OUT 10 13 83 83 14 BI IN 10 13 83 83 14 BI IN 10 13 83 83 14 BI 83 14 BI 83 14 BI 83 14 BI 83 14 BI 83 14 BI 83 14 BI OUT 13 28 R1004 68 5% 1/16W MF-LF 402 THERMAL PROCHOT* THERMDA THERMDC THERMTRIP* RSVD0 RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 RSVD6 RSVD7 RSVD8 D21 A24 B25 CPU_PROCHOT_L CPU_THERMD_P CPU_THERMD_N C7 PM_THRMTRIP_L OUT OUT 51 91 OUT 51 91 OUT 16 23 46 83 H CLK BCLK0 BCLK1 A22 A21 FSB_CLK_CPU_P FSB_CLK_CPU_N IN 29 30 88 IN 29 30 88 23 21 19 18 14 13 12 11 10 61 50 46 30 27 26 46 59 83 PM_THRMTRIP# SHOULD CONNECT TO ICH AND GMCH WITHOUT T (NO STUB) PP1V05_S0 R1005 1K 1% 1/16W MF-LF 402 R1020 83 13 10 XDP_TDI D16* D17* D18* D19* D20* D21* D22* D23* D24* D25* D26* D27* D28* D29* D30* D31* DSTBN1* DSTBP1* DINV1* BI R10061 XDP_TMS N22 FSB_D_L K25 FSB_D_L P26 FSB_D_L 83 14 BI R23 FSB_D_L 83 14 BI L23 FSB_D_L 83 14 BI M24 FSB_D_L 83 14 BI L22 FSB_D_L 83 14 BI M23 FSB_D_L 83 14 BI P25 FSB_D_L 83 14 BI P23 FSB_D_L 83 14 BI P22 FSB_D_L 83 14 BI T24 FSB_D_L 83 14 BI R24 FSB_D_L 83 14 BI L25 FSB_D_L 83 14 BI T25 FSB_D_L 83 14 BI N25 FSB_D_L 83 14 BI FSB_DSTB_L_N L26 83 14 BI FSB_DSTB_L_P M26 83 14 BI N24 FSB_DINV_L 83 14 BI 0.5" MAX LENGTH FOR CPU_GTLREF AD26 83 CPU_GTLREF C23 CPU_TEST1 D25 CPU_TEST2 C24 TP_CPU_TEST3 AF26 CPU_TEST4 AF1 TP_CPU_TEST5 NOSTUFF A26 TP_CPU_TEST6 C1000 0.1uF C3 TP_CPU_TEST7 10% 16V B22 CPU_BSEL 83 30 OUT X5R 402 B23 CPU_BSEL 83 30 OUT C21 CPU_BSEL 83 30 OUT BI IN B 83 13 10 D0* D1* D2* D3* D4* D5* D6* D7* D8* D9* D10* D11* D12* D13* D14* D15* DSTBN0* DSTBP0* DINV0* 83 14 BI 54.9 R1021 54.9 2.0K PP1V05_S0 10 11 12 13 14 18 19 21 23 26 27 30 46 50 61 1% 1/16W MF-LF 402 1% 1/16W MF-LF 402 1% 1/16W MF-LF 402 PLACE C1000 CLOSE TO CPU_TEST4 PIN MAKE SURE CPU_TEST4 IS REFERENCED TO GND R1024 54.9 XDP_TDO 83 13 10 1% PLACEMENT_NOTE=Place R1024 near ITP connector (if present) 1/16W FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_DSTB_L_N FSB_DSTB_L_P FSB_DINV_L E22 F24 E26 G22 F23 G25 E25 E23 K24 G24 J24 J23 H22 F26 K22 H23 J26 H26 H25 83 14 83 14 BI 83 14 BI 83 13 10 XDP_TRST_L 649 OF MISC Y22 AB24 V24 V26 V23 T22 U25 U23 Y25 W22 Y23 W24 W25 AA23 AA24 AB25 Y26 AA26 U22 FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_DSTB_L_N FSB_DSTB_L_P FSB_DINV_L D48* D49* D50* D51* D52* D53* D54* D55* D56* D57* D58* D59* D60* D61* D62* D63* DSTBN3* DSTBP3* DINV3* AE24 AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21 AC22 AD23 AF22 AC23 AE25 FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_DSTB_L_N FSB_DSTB_L_P FSB_DINV_L AF24 AC20 COMP0 COMP1 COMP2 COMP3 R26 U26 AA1 Y1 DPRSTP* DPSLP* DPWR* PWRGOOD SLP* PSI* E5 B5 D24 D6 D7 AE6 83 83 83 83 BI 14 83 BI 14 83 BI 14 83 BI 14 83 BI 14 83 BI 14 83 BI 14 83 BI 14 83 BI 14 83 BI 14 83 BI 14 83 BI 14 83 BI 14 83 BI 14 83 BI 14 83 BI 14 83 BI 14 83 BI 14 83 BI 14 83 BI 14 83 BI 14 83 BI 14 83 BI 14 83 BI 14 83 BI 14 83 BI 14 83 BI 14 83 BI 14 83 BI 14 83 BI 14 83 BI 14 83 BI 14 83 BI 14 83 BI 14 83 BI 14 83 BI 14 83 BI 14 83 BI 14 83 C LAYOUT NOTE: COMP0,2 CONNECT WITH ZO=27.4OHM, MAKE TRACE LENGTH SHORTER THAN 0.5" COMP1,3 CONNECT WITH ZO=55OHM, MAKE TRACE LENGTH SHORTER THAN 0.5" R1016 27.4 1% 1/16W MF-LF 402 1% 1/16W MF-LF 402 R1018 R1019 1% 1/16W MF-LF 402 54.9 CPU_COMP CPU_COMP CPU_COMP CPU_COMP CPU_DPRSTP_L CPU_DPSLP_L FSB_DPWR_L CPU_PWRGD FSB_CPUSLP_L CPU_PSI_L R1017 54.9 IN 16 23 59 83 IN 23 83 IN 14 83 IN 13 23 83 IN 14 83 OUT B 27.4 1% 1/16W MF-LF 402 28 59 54.9 R1023 FCBGA D32* D33* D34* D35* D36* D37* D38* D39* D40* D41* D42* D43* D44* D45* D46* D47* DSTBN2* DSTBP2* DINV2* R1030 R1022 XDP_TCK PENRYN NOSTUFF MF-LF 402 83 13 10 GTLREF TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 TEST7 BSEL0 BSEL1 BSEL2 U1000 DATA GRP BI FSB_ADS_L FSB_BNR_L FSB_BPRI_L DATA GRP BI 83 14 H1 E2 G5 DATA GRP 83 14 ADS* BNR* BPRI* DATA GRP BI CONTROL 83 14 XDP/ITP SIGNALS BI A3* A4* PENRYN FCBGA A5* OF A6* A7* A8* A9* A10* A11* A12* A13* A14* A15* A16* ADSTB0* ADDR GROUP0 83 14 U1000 FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_ADSTB_L ADDR GROUP1 BI ICH BI 83 14 RESERVED D 83 14 J4 L5 L4 K5 M3 N2 J1 N3 P5 P2 L2 P4 P1 R1 M1 NOSTUFF R10121 1% 1/16W MF-LF 402 1K 5% 1/16W MF-LF 402 1% 1/16W MF-LF 402 5% 1/16W MF-LF 402 NOSTUFF R1007 1K 5% 1/16W MF-LF 402 CPU FSB SYNC_MASTER=M87_MLB A SYNC_DATE=08/28/2007 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC SCALE SHT NONE REV 051-7431 A.0.0 OF 10 92 A C9200 C9201 10UF 0.1uF 10% 16V X5R 402 20% 6.3V X5R 603 VRAM8 VRAM8 C9202 0.1uF VRAM8 C9203 0.1uF 10% 16V X5R 402 C9204 0.1uF 10% 16V X5R 402 10% 16V X5R 402 A2 VDD0 A11 VDD1 F1 VDD2 F12 VDD3 M1 VDD4 M12 VDD5 V2 VDD6 V11 VDD7 K1 VDDA0 K12 VDDA1 D VRAM8 VRAM8 C9210 0.1uF Connect to designated pin, then GND 70 69 68 65 50 78 77 74 71 C9215 0.1uF 10% 16V X5R 402 U8500.J1 10% 16V X5R 402 U8500.J12 PP1V8_S0GPU_ISNS VRAM8 C9220 10UF 20% 6.3V X5R 603 VRAM8 VRAM8 C9221 0.1uF VRAM8 C9222 0.1uF 10% 16V X5R 402 C9223 0.1uF 10% 16V X5R 402 10% 16V X5R 402 VRAM8 VRAM8 C9224 0.1uF VRAM8 C9225 0.1uF C9226 0.1uF 10% 16V X5R 402 10% 16V X5R 402 10% 16V X5R 402 A1 VDDQ0 A12 VDDQ1 C1 VDDQ2 C4 VDDQ3 C9 VDDQ4 C12 VDDQ5 E1 VDDQ6 E4 VDDQ7 E9 VDDQ8 E12 VDDQ9 J4 VDDQ10 J9 VDDQ11 N1 VDDQ12 N4 VDDQ13 N9 VDDQ14 N12 VDDQ15 R1 VDDQ16 R4 VDDQ17 R9 VDDQ18 R12 VDDQ19 V1 VDDQ20 V12 C 71 IN 71 IN FB_B2_VREF FB_B0_VREF U9200 FBGA (2 OF 2) VSS0 A3 VSS1 A10 VSS2 G1 VRAM8 VRAM8 C9250 VSS3 G12 VSS4 L1 VSS5 L12 C9251 10UF 0.1uF VRAM8 C9252 0.1uF 10% 16V X5R 402 20% 6.3V X5R 603 VRAM8 VRAM8 C9253 0.1uF 0.1uF 10% 16V X5R 402 10% 16V X5R 402 C9254 10% 16V X5R 402 K1 VDDA0 K12 VDDA1 VSSA0 J1 VSSA1 J12 VRAM8 VSSQ0 B1 VSSQ1 B4 VSSQ2 B9 VRAM8 C9260 0.1uF VSSQ3 B12 VSSQ4 D1 VSSQ5 D4 VSSQ6 D9 VSSQ7 D12 VSSQ8 G2 Connect to designated pin, then GND 77 74 71 70 69 68 65 50 78 C9270 10UF 20% 6.3V X5R 603 VSSQ12 P1 VSSQ13 P4 VSSQ14 P9 10% 16V X5R 402 U8500.J12 PP1V8_S0GPU_ISNS VRAM8 VSSQ9 G11 VSSQ10 L2 VSSQ11 L11 C9265 0.1uF 10% 16V X5R 402 U8500.J1 VRAM8 VRAM8 C9271 0.1uF VRAM8 C9272 0.1uF 10% 16V X5R 402 C9273 0.1uF 10% 16V X5R 402 10% 16V X5R 402 VRAM8 VRAM8 C9274 0.1uF VRAM8 C9275 0.1uF 10% 16V X5R 402 10% 16V X5R 402 VSSQ15 P12 VSSQ16 T1 VSSQ17 T4 VSSQ18 T9 VSSQ19 T12 V12 71 IN 71 IN FB_B3_VREF FB_B1_VREF 78 71 69 90 78 71 69 90 78 71 69 90 IN 78 71 69 90 78 71 69 90 IN IN IN 78 71 69 90 90 71 69 IN 90 71 69 IN 78 71 69 IN IN 78 71 69 90 78 71 69 90 IN 78 71 69 90 IN 78 71 69 90 90 71 69 IN IN OUT OUT 90 71 69 OUT OUT 90 71 69 IN 90 71 69 IN 90 71 69 IN 90 71 69 IN 78 71 69 90 IN 78 71 69 90 IN 78 71 69 90 IN N10 DQ0 B2 B3 H11 K10 L9 K11 M9 K2 L4 FB_B_CKE FB_B_CLK_P FB_B_CLK_N FB_B_CS1_L FB_B_WE_L FB_B_CAS_L FB_B_RAS_L H4 J11 J10 F9 H9 F4 H3 A4 FB_B2_ZQ FB_B2_MF FB_B2_SEN 90 71 69 90 71 69 A IN DM2 DM3 A9 V4 V9 FB_B_DRAM_RST FB_B_RDQS FB_B_RDQS FB_B_RDQS FB_B_RDQS D3 D10 P10 P3 FB_B_WDQS FB_B_WDQS FB_B_WDQS FB_B_WDQS R9240 1K 5% 1/16W MF-LF 402 VRAM8 R9248 243 1% 1/16W MF-LF 402 R9249 100 NC NC A9 A10 A11 CKE CK CK* DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 CS* WE* CAS* DQ12 DQ13 RAS* DQ14 ZQ MF DQ15 DQ16 SEN DQ17 RESET RDQS0 RDQS1 RDQS2 RDQS3 DQ18 DQ19 DQ20 DQ21 DQ22 WDQS0 D11 P11 WDQS1 DQ25 WDQS2 WDQS3 DQ26 DQ27 H10 VRAM8 A7 A8/AP DQ1 DQ2 D2 G4 G9 VRAM8 A6 DQ23 DQ24 P2 FB_B_BA FB_B_BA FB_B_BA A4 A5 BA0 BA1 BA2 J2 RFU1 J3 RFU2 DQ28 DQ29 DQ30 DQ31 E3 E10 N3 C2 C3 E2 F3 F2 G3 B11 B10 C11 C10 E11 F10 F11 G10 M11 L10 N11 M10 R11 R10 T11 T10 M2 L3 N2 M3 R2 R3 T2 T3 FB_B_DQM_L FB_B_DQM_L FB_B_DQM_L FB_B_DQM_L FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ IN 69 71 90 69 90 78 71 69 71 90 69 90 78 71 IN 69 71 90 69 90 71 IN IN 69 71 90 69 90 71 IN 90 71 69 69 71 90 IN 90 69 71 90 78 71 69 69 71 90 IN IN BI BI BI BI BI BI 69 71 90 78 71 69 90 78 71 69 90 IN IN IN IN IN IN IN BI 78 71 69 90 78 71 69 90 69 71 90 78 71 69 90 90 71 69 BI 90 71 69 IN BI BI BI IN IN IN BI 78 71 69 BI 78 71 69 90 78 71 69 90 IN 78 71 69 90 IN BI BI BI 69 71 90 BI 69 71 90 BI 69 71 90 IN IN FBGA (2 OF 2) VSS0 A3 VSS1 VSS2 A10 G1 VSS3 VSS4 G12 VSS5 VSS6 VSS7 V3 VSSA0 J1 VSSA1 J12 VSSQ0 B1 VSSQ1 VSSQ2 B4 B9 VSSQ3 VSSQ4 B12 VSSQ5 VSSQ6 VSSQ7 D9 VSSQ9 VSSQ10 G11 L2 VSSQ11 L11 VSSQ12 VSSQ13 P1 P4 VSSQ14 VSSQ15 P9 VSSQ19 D D1 D4 D12 G2 VSSQ17 VSSQ18 BOM options provided by this page: (NONE) V10 VSSQ8 VSSQ16 Signal aliases required by this page: (NONE) L1 L12 P12 T1 T4 T9 T12 VDDQ21 H1 VREF0 H12 VREF1 BI BI 90 71 69 IN BI 90 71 69 IN BI 90 71 69 IN BI 90 71 69 IN BI 69 71 90 78 71 69 90 IN 78 71 69 90 IN 78 71 69 90 69 71 90 IN BI BI BI BI BI BI BI IN OUT OUT OUT OUT A0 U9250 DM0 A1 FBGA DM1 K3 A2 A3 (1 OF 2) DM2 DM3 N10 DQ0 B2 B3 H11 K10 L9 K11 M9 K2 L4 FB_B_CKE FB_B_CLK_P FB_B_CLK_N FB_B_CS1_L FB_B_WE_L FB_B_CAS_L FB_B_RAS_L H4 J11 J10 F9 H9 F4 H3 A4 A9 V4 V9 FB_B_DRAM_RST FB_B_RDQS FB_B_RDQS FB_B_RDQS FB_B_RDQS D3 D10 P10 P3 FB_B_WDQS FB_B_WDQS FB_B_WDQS FB_B_WDQS FB_B_BA FB_B_BA FB_B_BA R9290 1K 5% 1/16W MF-LF 402 VRAM8 R9298 243 1% 1/16W MF-LF 402 R9299 100 NC NC A7 A8/AP A9 A10 A11 CKE DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 CK CK* DQ9 DQ10 DQ11 CS* WE* CAS* DQ12 DQ13 RAS* DQ14 ZQ MF DQ15 DQ16 SEN DQ17 RESET DQ18 DQ19 RDQS0 RDQS1 DQ20 DQ21 RDQS2 RDQS3 DQ22 WDQS0 D11 P11 WDQS1 DQ25 WDQS2 WDQS3 DQ26 DQ27 H10 VRAM8 A6 D2 G4 G9 A4 A5 DQ23 DQ24 P2 VRAM8 5% 1/16W MF-LF 402 K4 H2 M4 K9 FB_B3_ZQ FB_B3_MF FB_B3_SEN 78 71 69 90 69 71 90 90 71 69 69 71 90 90 71 69 69 71 90 90 71 69 69 71 90 90 71 69 69 71 90 BI FB_B_MA FB_B_MA FB_B_UMA FB_B_UMA FB_B_UMA FB_B_UMA FB_B_MA FB_B_MA FB_B_MA FB_B_MA FB_B_MA FB_B_MA MFLOW IN DM1 (1 OF 2) MFLOW IN 78 71 69 90 DM0 FBGA A2 A3 BA0 BA1 BA2 J2 RFU1 J3 RFU2 DQ28 MFLOW IN U9200 A1 K4J52324QC-BC20 90 71 69 90 71 69 J4 VDDQ10 J9 VDDQ11 N1 VDDQ12 U9250 Power aliases required by this page: - =PP1V8_S0_FB_VDD - =PP1V8_S0_FB_VDDQ C CRITICAL OMIT A0 M4 K9 C12 VDDQ5 E1 VDDQ6 E4 VDDQ7 E9 VDDQ8 E12 VDDQ9 R1 VDDQ16 R4 VDDQ17 R9 VDDQ18 R12 VDDQ19 V1 VDDQ20 VDDQ21 K3 MFLOW IN A1 VDDQ0 A12 VDDQ1 C1 VDDQ2 C4 VDDQ3 C9 VDDQ4 N4 VDDQ13 N9 VDDQ14 N12 VDDQ15 H1 VREF0 H12 VREF1 K4 H2 16MX32-GDDR3-500MHZ IN 90 71 69 FB_B_MA FB_B_MA FB_B_LMA FB_B_LMA FB_B_LMA FB_B_LMA FB_B_MA FB_B_MA FB_B_MA FB_B_MA FB_B_MA FB_B_MA MFLOW IN MFLOW B IN 78 71 69 90 90 71 69 C9276 0.1uF 10% 16V X5R 402 CRITICAL OMIT 78 71 69 90 A2 VDD0 A11 VDD1 F1 VDD2 F12 VDD3 M1 VDD4 M12 VDD5 V2 VDD6 V11 VDD7 VSS6 V3 VSS7 V10 K4J52324QC-BC20 VRAM8 K4J52324QC-BC20 VRAM8 Page Notes CRITICAL OMIT PP1V8_S0GPU_ISNS K4J52324QC-BC20 78 77 74 71 70 69 68 65 50 16MX32-GDDR3-500MHZ CRITICAL OMIT PP1V8_S0GPU_ISNS 16MX32-GDDR3-500MHZ 70 69 68 65 50 78 77 74 71 16MX32-GDDR3-500MHZ DQ29 DQ30 DQ31 E3 E10 N3 C2 C3 E2 F3 F2 G3 B11 B10 C11 C10 E11 F10 F11 G10 M11 L10 N11 M10 R11 R10 T11 T10 M2 L3 N2 M3 R2 R3 T2 T3 FB_B_DQM_L FB_B_DQM_L FB_B_DQM_L FB_B_DQM_L FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ IN 69 71 90 IN 69 71 90 IN 69 71 90 IN 69 71 90 BI 69 71 90 BI 69 71 90 BI 69 71 90 BI 69 71 90 BI 69 71 90 BI 69 71 90 BI 69 71 90 BI 69 71 90 BI 69 71 90 BI 69 71 90 BI 69 71 90 BI 69 71 90 BI 69 71 90 BI 69 71 90 BI 69 71 90 BI 69 71 90 BI 69 71 90 BI 69 71 90 BI 69 71 90 BI 69 71 90 BI 69 71 90 BI 69 71 90 BI 69 71 90 BI 69 71 90 BI 69 71 90 B GDDR3 Frame Buffer B (Bot) BI BI 69 71 90 BI 69 71 90 BI 69 71 90 BI 69 71 90 BI 69 71 90 BI 69 71 90 SYNC_MASTER=M87_MLB THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT 5% 1/16W MF-LF 402 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC REV 051-7431 SCALE SHT NONE SYNC_DATE=08/28/2007 NOTICE OF PROPRIETARY PROPERTY A.0.0 OF 78 92 A D D 1.8V Frame Buffer Regulator 65 63 62 61 60 58 43 42 27 75 62 61 60 59 58 57 49 40 82 75 66 63 PP5V_S5 PPBUS_G3H C9301 1UF 10% 25V X5R 603 C9300 1 R9300 2.2UF 10 10% 16V X5R 603 5% 1/16W MF-LF 402 C C9303 1 CRITICAL C9330 1UF 22UF 10% 25V X5R 603 20% 25V POLY CASE-D2-LF C PP5V_S5_1V8GPU_VCC MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm 12 PVCC C9302 2.2UF 75 65 65 PM_P1V8_S0GPU_EN C9309 0.22UF 10% 16V X7R 603 ISL6269BCRZ VIN P1V8FB_FSET VCC U9300 10% 16V X5R 603 QFN CRITICAL UG 14 FSET P1V8FB_UG TP_P1V8_S0GPU_PGOOD P1V8FB_COMP C9306 0.01UF 10% 16V CERM 402 BOOT 13 PHASE 15 ISEN EN FCCM PGOOD COMP R9306 30.1K 1% 1/16W MF-LF 402 LG 11 R9308 40.2K 1% 1/16W MF-LF 402 C9307 P1V8FB_FB 68PF FB SI7110DN PWRPK-1212-8 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm SWITCH_NODE=TRUE P1V8FB_ISEN 1.0UH-22A R93211 IHLP2525CZ-SM R9310 5.62K2 2.0K 1% 1/16W MF-LF 402 P1V8FB_LG 1% 1/16W MF-LF 402 CRITICAL D Q9321 PWRPK-1212-8 R93221 1K C9340 10UF 5% 1/16W MF-LF 402 C9342 330UF 20% 6.3V X5R 603 50 Vout = 1.8V 10A max output 20% 2.5V POLY CASE-C2S-HF C9341 1 10UF CRITICAL C9343 330UF 20% 6.3V X5R 603 20% POLY CASE-C2S-HF 2.5V B 1% 1/16W MF-LF 402 XW9300 SM 0.0047uF 10% 25V CERM 402 10% 50V CERM 402 GND_P1V8FB_SGND C9320 R9320 680PF B NO STUFF S C9308 PP1V8_S0GPU CRITICAL NO STUFF P1V8FB_FB_RC SI7108DNS G MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm P3V3S5_COMP_R L9320 P1V8FB_PHASE PGND 10 THRML PAD 17 CRITICAL S MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm VO 5% 50V CERM 402-1 Q9320 G MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm P1V8FB_BOOT 16 CRITICAL D Vout = 0.6V * (1 + Ra / Rb) 1.8V FB Power Supply SYNC_MASTER=MASTER A SYNC_DATE=MASTER NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC SCALE SHT NONE REV 051-7431 A.0.0 OF 79 92 A TMDS Filtering (Place close to GPU) 90 74 IN NO STUFF 80 74 73 C9462 1% 1/16W MF-LF 402 SIGNAL_MODEL=EMPTY 10% 16V CERM 402 R9463 90 74 IN TMDS_DATA_P 90 74 IN TMDS_DATA_N 1% C9466 90 74 IN IN 1% TMDS_DATA_F_N TMDS_DATA_F_P 80 91 80 76 75 74 73 72 65 58 48 C 90 74 IN IN GPU_VGA_HSYNC U9451 C9451 TMDS_DATA_F_N 80 91 TMDS_DATA_F_P 80 91 80 74 73 PP3V3_S0GPU_TMDS R9474 49.9 10% 16V CERM 402 TMDS_CLK_R_N IN 80 74 73 L9410 NO STUFF 0.01UF 10% 16V CERM 402 TMDS_CLK_F_N 90 74 IN TMDS_DATA_P 90 74 IN TMDS_DATA_N TMDS_CLK_F_P 0.01UF 10% 16V CERM 402 1% 1/16W MF-LF 402 SIGNAL_MODEL=EMPTY PP3V3_S0GPU_TMDS NO STUFF R9479 80 74 73 IN TMDS_DATA_P IN TMDS_DATA_N L9476 NO STUFF 0.01UF 10% 16V CERM 402 IN R9483 1% TMDS_DATA_P TMDS_DATA_F_N TMDS_DATA_F_N 20 TMDS_DATA_F_P TMDS_DATA_F_P 21 80 91 91 80 23 TMDS_CLK_F_P 80 91 PLACEMENT_NOTE=Place close to connector 91 80 24 TMDS_CLK_F_N 91 80 VGA_B 91 80 VGA_HSYNC MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=5V 4.7K 5% 1/16W MF-LF 402 C3 C5B C4 R9445 L9480 90-OHM-100MA R9412 TMDS_DATA_F_N TMDS_DATA_F_N TMDS_DATA_F_P TMDS_DATA_F_P C1 C5A C2 VGA_R 80 91 VGA_G 80 91 32 1% 1/16W MF-LF 402 SYM_VER-1 TMDS_DATA_F_N 80 91 TMDS_DATA_F_P 80 91 R9420 5% 1/16W MF-LF 402 Q9411 TMDS_DATA_F_N TMDS_DATA_F_N TMDS_DATA_F_P TMDS_DATA_F_P DVI_DDC_CLK_R (PP5V_S0_DDC) DVI_DDC_DATA_R VGA_VSYNC DVI_HPD_R 80 91 1% 1/16W MF-LF 402 514-0278 5% 1/16W MF-LF 402 2N7002DW-X-F 100 G SOT-363 D DVI_DDC_CLK S GPU_DVI_DDC_CLK 80 91 80 91 100pF G SOT-363 D DVI_DDC_DATA S GPU_DVI_DDC_DATA 5% 1/16W MF-LF 402 80 91 80 91 B 80 91 C9413 R9422 100pF 5% 50V CERM 402 80 91 100K Q9414 5% 1/16W MF-LF 402 2N7002DW-X-F R9414 100 G SOT-363 DVI_HPD 5% 1/16W MF-LF 402 D GPU_HPD S OUT 72 73 R9415 20K C9414 VGA_TERM_CONN 100pF 1 5% 50V CERM 402 150 1% 1/16W MF-LF 402 5% 1/16W MF-LF 402 R9416 24 DVI_HOTPLUG_DET 10K 5% 1/16W MF-LF 402 PLACEMENT_NOTE=Place close to connector 49.9 1/16W MF-LF 402 DVI Display Connector CRITICAL L9484 R94861 PP3V3_S0GPU_TMDS NO STUFF R9487 1% SYM_VER-1 TMDS_DATA_F_N 80 91 TMDS_DATA_F_P 80 91 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT PLACEMENT_NOTE=Place close to connector III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART 49.9 SIZE DRAWING NUMBER D 1/16W MF-LF 402 REV 051-7431 SCALE SHT NONE SYNC_DATE=MASTER NOTICE OF PROPRIETARY PROPERTY 90-OHM-100MA DLP11S 49.9 1% 1/16W MF-LF 402 SIGNAL_MODEL=EMPTY SYNC_MASTER=MASTER APPLE INC 73 74 5% 1/16W MF-LF 402 2N7002DW-X-F R9413 80 91 OUT 10K Q9411 73 74 R9421 C9411 100 OUT 80 91 R9443 R9444 150 10K 5% 1/16W MF-LF 402 5% 50V CERM 402 150 DLP11S 4.7K 1 10 11 12 13 14 15 16 PP3V3_S0GPU 31 VGA_TERM_CONN 34 80 76 75 74 73 72 65 58 48 R9411 VGA_TERM_CONN CRITICAL 49.9 PP3V3_S0GPU_TMDS NO STUFF TMDS_DATA_F_P 18 22 49.9 1% 1/16W MF-LF 402 SIGNAL_MODEL=EMPTY 17 GPU Isolation / Level-Shift PP5V_S0_DDC_PULLUPS B0530WXF QH11121-RIG02-4F TMDS_DATA_F_N SYM_VER-1 R9482 90 74 J9400 33 91 80 90-OHM-100MA DLP11S PP3V3_S0GPU_TMDS C9486 MIN_LINE_WIDTH=0.38 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=5V SM-1 R94101 CRITICAL NO STUFF A PP5V_S0_DDC CRITICAL 19 1/16W MF-LF 402 90 74 C F-RT-TH-DVI 80 91 91 80 49.9 PP3V3_S0GPU_TMDS NO STUFF 90 74 20% 50V CERM 603 TMDS_CLK_R_P R94781 1% 3.3pF D9410 SOD-123 0.01uF 91 80 91 NO STUFF C9482 MIN_LINE_WIDTH=0.38 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=5V 80 91 91 80 80 74 73 PP5V_S0_DDC_F C9410 TMDS_DATA_N C9478 SM R9473 PP3V3_S0GPU_TMDS C9442 0.25% 50V CERM 402 Isolation required for DVI->ADC Adapter CRITICAL SYM_VER-1 1 150 400-OHM-EMI PLACEMENT_NOTE=Place close to connector 1% 1/16W MF-LF 402 VGA_R 80 91 (DACB TV C) R94421 80 91 R9475 TMDS_CLK_P 3.3pF MEA2010P-SM 1% 1/16W MF-LF 402 L9472 370-OHM NO STUFF B SM-LF 5% 1/16W MF-LF 402 90 74 PP5V_S0 CRITICAL NO STUFF 49.9 IN 91 PP3V3_S0GPU_TMDS 0.01UF 90 74 1% 1/16W MF-LF 402 SIGNAL_MODEL=EMPTY NO STUFF C9474 59 58 54 52 49 47 42 27 82 81 65 5% 1/16W MF-LF 402 C9441 0.25% 50V CERM 402 210MHZ (55mA requirement per DVI spec) R9472 NO STUFF DVI DDC Current Limit CRITICAL VGA_G 80 91 (DACB TV Y) DVI INTERFACE PLACEMENT_NOTE=Place close to connector 1/16W MF-LF 402 TMDS_CLK_N SYM_VER-1 R9471 1% DLP11S PP3V3_S0GPU_TMDS NO STUFF TMDS_DATA_P 20% 10V CERM 402 L9468 90-OHM-100MA 1% 1/16W MF-LF 402 SIGNAL_MODEL=EMPTY GPU_TV_C_VGA_R VGA_TERM_FILTER 0.1uF CRITICAL F9410 IN IN 5% 1/16W MF-LF 402 0.5AMP-13.2V 90 74 90 73 R9451 49.9 90 74 PLACEMENT_NOTE=Place close to connector MC74VHC1G08 SC70 33 91 VGA_HSYNC_R VGA_HSYNC 80 91 49.9 49.9 0.25% 50V CERM 402 1% 1/16W MF-LF 402 PP3V3_S0GPU PLACEMENT_NOTE=Place close to connector R9470 FL9440 150 D C9440 3.3pF GPU_TV_Y_VGA_G IN CRITICAL 150 1% 1/16W MF-LF 402 R94411 1/16W MF-LF 402 PP3V3_S0GPU_TMDS 10% 16V CERM 402 R94401 SYM_VER-1 VGA_B 80 91 (DACB TV COMP) VGA_TERM_FILTER L9464 0.01UF GPU_TV_COMP_VGA_B IN VGA_TERM_FILTER TMDS_DATA_N 90 73 90-OHM-100MA DLP11S R9467 TMDS_DATA_P C9470 C9450 80 91 5% 1/16W MF-LF 402 90 73 PP3V3_S0GPU_TMDS NO STUFF NO STUFF U9450 CRITICAL NO STUFF 80 74 73 IN 1/16W MF-LF 402 90 74 80 91 GPU_VGA_VSYNC 20% 10V CERM 402 1% 1/16W MF-LF 402 SIGNAL_MODEL=EMPTY 90 74 0.1uF 49.9 10% 16V CERM 402 TMDS_DATA_F_P R9450 80 91 PLACEMENT_NOTE=Place close to connector R94661 0.01UF TMDS_DATA_F_N 49.9 PP3V3_S0GPU_TMDS NO STUFF NO STUFF 80 74 73 PLACEMENT_NOTE=Place close to connector MC74VHC1G08 SC70 33 91 VGA_VSYNC_R VGA_VSYNC SYM_VER-1 PP3V3_S0GPU_TMDS NO STUFF 0.01UF D 90-OHM-100MA DLP11S 49.9 PP3V3_S0GPU L9460 R94621 NO STUFF 80 76 75 74 73 72 65 58 48 CRITICAL ANALOG FILTERING PLACE CLOSE TO CONNECTOR VGA SYNC Buffers (Place close to connector) TMDS_DATA_N PP3V3_S0GPU_TMDS A.0.0 OF 80 92 A D D Top-Case Connector 65 58 55 54 51 50 48 38 36 81 65 57 48 47 46 45 43 28 66 Backlight Connector PP3V3_S3 PP3V42_G3H CRITICAL J9650 J9600 SM04B-ACH QT500166-L020 CRITICAL FL9600 46 45 0.01H-0.3A-80V SM SYM_VER-1 81 58 46 44 PP5V_S3 PP5V_S3_TOPCASE_F MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM TPAD_GND MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM SMC_LID SMC_ONOFF_L VOLTAGE=5V 46 45 OUT M-ST-SM 10 11 12 13 14 15 16 OUT 86 24 BI 86 24 BI USB_TPAD_P USB_TPAD_N CRITICAL M-RT-SM GND KBDLED_ANODE OUT IN SMBUS_SMC_A_S3_SDA SMBUS_SMC_A_S3_SCL 82 IN 82 OUT 54 BI 34 45 48 51 88 BI 34 45 48 51 88 82 IN 82 IN BKLT_PWR BKLT_GND BKLT_P5V_EN BKLT_PWM NC NC Classic Inverter/ LED Backlight PBUS GND +5V/EN PWM D9600 SC-75 C C 518S0369 516S0350 RCLAMP0502B IR & Sleep LED Connector CRITICAL J9610 HS8806F-B M-RT-SM PP5V_S3 44 46 58 81 USB_IR_N USB_IR_P BI BI 24 86 24 86 Bluetooth (M13P) & SATA HDD Flex Connector B PLACEMENT_NOTE=Place C9660 close to southbridge PLACEMENT_NOTE=Place C9661 next to C9660 FL9660 C9660 86 23 IN SATA_A_R2D_C_P C9661 0.0047uF 86 23 86 23 IN OUT SATA_A_R2D_C_N 1 91 SATA_A_R2D_UF_P 90-OHM-100MA 1210-4SM1 SYM_VER-1 SATA_A_D2R_N 91 SATA_A_R2D_UF_N FL9665 C9666 90-OHM-100MA 1210-4SM1 SYM_VER-1 0.0047uF 91 SATA_A_D2R_UF_N C9665 86 23 OUT B CRITICAL J9660 M-ST-SM 10% 25V CERM 402 46 QT500166-L020 86 86 10% 25V CERM 402 IN 518S0474 PLACEMENT_NOTE=Place FL9660 close to J9660 CRITICAL 0.0047uF SYS_LED_ANODE 0.0047uF SATA_A_D2R_P 91 SATA_A_D2R_UF_P CRITICAL PLACEMENT_NOTE=Place FL9665 close to southbridge 10% 25V CERM 402 SATA_A_R2D_P SATA_A_R2D_N SATA_A_D2R_A_N SATA_A_D2R_A_P 55 54 38 36 51 50 48 81 65 58 PP3V3_S3 10 12 11 14 13 16 15 PP5V_S0 27 42 47 49 52 54 58 59 65 80 82 NC USB_BT_N USB_BT_P BI 24 86 BI 24 86 10% 25V CERM 402 PLACEMENT_NOTE=Place C9666 next to C9665 PLACEMENT_NOTE=Place C9666 close to J9660 516S0350 Project Specific Connectors SYNC_MASTER=(MASTER) A SYNC_DATE=(MASTER) NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC SCALE SHT NONE REV 051-7431 A.0.0 OF 81 92 A Q9806 FDMA530PZ MICROFET PPBUS_S0_LCDBKLT_FUSED MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.251mm VOLTAGE=12.6V R9808 603 C9802 200K 0.033UF 5% 1/16W MF-LF 2402 D 10% 16V X5R D PPBUS_G3H F9800 2AMP-32V-44MOHM 62 61 60 59 58 57 49 40 79 75 66 63 402 PPBUS_S0_LCDBKLT_EN_DIV R9809 100K OMIT 5% 1/16W MF-LF RX9892 2402 SHORT2 BKLT_GND PPBUS_S0_LCDBKLT_EN_L MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=0V 603 Q9807 SSM3K15FV IN 81 OUT 81 D SOD-VESM CRITICAL L9891 FERR-120-OHM-1.5A G PPBUS_S0_LCDBKLT_SW S MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.6V BKLT_PWR MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.6V 0402 Q9805 C FERR-120-OHM-1.5A C9805 2.2UF 1% 1/16W MF-LF 402 6.3V CERM BKLT_P5V_EN MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=5V 0402 L9894 FERR-120-OHM-1.5A 402-LF LCDBKLT_PWREN_L LCDBKLT_PWM OUT 81 OUT 81 C9893 0.001uF CRITICAL 20% MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=5V P-CHN 51.1K G R9805 PP5V_SW_LCDBKLT D S C L9893 SOT-563 BKLT_5V_PWR 20% 50V CERM 402 CRITICAL NTZD3155C PP5V_S0 27 81 80 65 59 58 54 52 49 47 42 BKLT_5V_PWR C9892 0.001uF BKLT_5V_PWR 20% 50V CERM 402 BKLT_PWM 0402 BKLT_5V_PWR 1 R9810 20% 50V CERM 402 1% 1/16W MF-LF 2402 BKLT_3V_SIG BKLT_3V_SIG R98071 5.1K LCDBKLT_PWREN_SW_L C9894 0.001uF 51.1K C9807 0.33UF 5% 1/16W MF-LF 4022 10% 6.3V CERM-X5R 402 R9807 is top end of resistor divider Bottom end is on LED board B B Q9805 NTZD3155C SOT-563 N-CHN BKLT_5V_PWR D 73 72 IN GPU_BKLT_EN G S BKLT_5V_PWR R9806 100K 5% 1/16W MF-LF 402 PP3V3_S0 91 65 59 58 53 52 51 50 27 26 25 24 23 21 19 16 13 48 47 46 42 32 31 30 29 28 PLT_RST_L input ensures backlight PWM does not glitch during RESET 28 24 A 73 72 IN IN PLT_RST_L GPU_BL_PWM C9800 MC74VHC1G08 SC70 U9800 LCDBKLT_PWM_RSTGATED LCD Backlight Support MC74VHC1G08 SC70 U9801 SYNC_MASTER=M87_LIO THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING 0.1uF 20% 10V CERM 402 SYNC_DATE=12/06/2007 NOTICE OF PROPRIETARY PROPERTY C9801 0.1uF 20% 10V CERM 402 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART LCDBKLT_PWREN input ensures backlight PWM does not run if backlight is not powered/enabled SIZE DRAWING NUMBER D APPLE INC SCALE SHT NONE REV 051-7431 A.0.0 OF 82 92 A FSB (Front-Side Bus) Constraints CPU / FSB Net Properties TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP FSB_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD FSB_DSTB_55S * =1:1_DIFFPAIR =55_OHM_SE =55_OHM_SE =55_OHM_SE =1:1_DIFFPAIR =1:1_DIFFPAIR ELECTRICAL_CONSTRAINT_SET NET_TYPE PHYSICAL SPACING TABLE_PHYSICAL_RULE_ITEM FSB_COMMON FSB_COMMON FSB_COMMON FSB_COMMON FSB_COMMON FSB_COMMON FSB_COMMON FSB_COMMON FSB_COMMON FSB_COMMON FSB_COMMON FSB_COMMON FSB_COMMON FSB_CPURST_L FSB_55S FSB_55S FSB_55S FSB_55S FSB_55S FSB_55S FSB_55S FSB_55S FSB_55S FSB_55S FSB_55S FSB_55S FSB_55S FSB_55S FSB_COMMON FSB_COMMON FSB_COMMON FSB_COMMON FSB_COMMON FSB_COMMON FSB_COMMON FSB_COMMON FSB_COMMON FSB_COMMON FSB_COMMON FSB_COMMON FSB_COMMON FSB_COMMON FSB_ADS_L FSB_BNR_L FSB_BPRI_L FSB_BREQ0_L FSB_DBSY_L FSB_DEFER_L FSB_DPWR_L FSB_DRDY_L FSB_HIT_L FSB_HITM_L FSB_LOCK_L FSB_RS_L FSB_TRDY_L FSB_CPURST_L FSB_DATA_GROUP0 FSB_DATA_GROUP0 FSB_DSTB0 FSB_55S FSB_55S FSB_DSTB_55S FSB_DSTB_55S FSB_DATA FSB_DATA FSB_DSTB FSB_DSTB FSB_D_L FSB_DINV_L FSB_DSTB_L_P FSB_DSTB_L_N FSB_DATA_GROUP1 FSB_DATA_GROUP1 FSB_DSTB1 FSB_55S FSB_55S FSB_DSTB_55S FSB_DSTB_55S FSB_DATA FSB_DATA FSB_DSTB FSB_DSTB FSB_D_L FSB_DINV_L FSB_DSTB_L_P FSB_DSTB_L_N All FSB signals with impedance requirements are 55-ohm single-ended Worst-case spacing is 2:1 within Addr bus, with 3:1 spacing to the ADSTBs Worst-case spacing is 2:1 within Data bus, with 3:1 spacing to the DSTBs DSTB complementary pairs are spaced 1:1 and routed as differential pairs FSB_DATA_GROUP2 FSB_DATA_GROUP2 FSB_DSTB2 FSB_55S FSB_55S FSB_DSTB_55S FSB_DSTB_55S FSB_DATA FSB_DATA FSB_DSTB FSB_DSTB FSB_D_L FSB_DINV_L FSB_DSTB_L_P FSB_DSTB_L_N Design Guide recommends each strobe/signal group is routed on the same layer Design Guide recommends FSB signals be routed only on internal layers FSB_DATA_GROUP3 FSB_DATA_GROUP3 FSB_DSTB3 FSB_55S FSB_55S FSB_DSTB_55S FSB_DSTB_55S FSB_DATA FSB_DATA FSB_DSTB FSB_DSTB FSB_D_L FSB_DINV_L FSB_DSTB_L_P FSB_DSTB_L_N FSB_ADDR_GROUP0 FSB_ADDR_GROUP0 FSB_ADSTB0 FSB_55S FSB_55S FSB_55S FSB_ADDR FSB_ADDR FSB_ADSTB FSB_A_L FSB_REQ_L FSB_ADSTB_L FSB_ADDR_GROUP1 FSB_ADSTB1 FSB_55S FSB_55S FSB_ADDR FSB_ADSTB FSB_A_L FSB_ADSTB_L CPU_IERR_L CPU_FERR_L CPU_PROCHOT_L CPU_PWRGD CPU_FROM_SB CPU_FROM_SB CPU_FROM_SB CPU_FROM_SB CPU_FROM_SB CPU_INIT_L CPU_FROM_SB CPU_FROM_SB PM_THRMTRIP_L FSB_CPUSLP_L PM_DPRSLPVR CPU_DPRSTP_L CPU_55S CPU_55S CPU_55S CPU_55S CPU_55S CPU_55S CPU_55S CPU_55S CPU_55S CPU_55S CPU_55S CPU_55S CPU_55S CPU_55S CPU_55S CPU_55S CPU_55S CPU_55S CPU_55S CPU_55S CPU_55S CPU_55S CPU_55S CPU_GTLREF CPU_COMP CPU_COMP CPU_COMP CPU_COMP XDP_TDI XDP_TDO XDP_TMS XDP_TCK XDP_TRST_L XDP_BPM_L XDP_BPM_L5 TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING TABLE_SPACING_RULE_HEAD WEIGHT SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM FSB_ADDR * TABLE_SPACING_RULE_ITEM ? =3:1_SPACING FSB_DATA * =3:1_SPACING ? TABLE_SPACING_RULE_ITEM D FSB_ADDR2ADDR * =2:1_SPACING ? FSB_ADSTB * =3:1_SPACING ? TABLE_SPACING_RULE_ITEM FSB_DATA2DATA * =2:1_SPACING ? FSB_DSTB * =3:1_SPACING ? TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM FSB_ADDR2ADSTB * TABLE_SPACING_RULE_ITEM ? =3:1_SPACING FSB_DATA2DSTB * =3:1_SPACING ? TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM FSB_COMMON * ? =2:1_SPACING TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET FSB_ADDR FSB_ADDR * FSB_ADDR2ADDR TABLE_SPACING_ASSIGNMENT_ITEM 10 14 10 14 10 14 10 14 10 14 10 14 10 14 10 14 D 10 14 10 14 10 14 10 14 10 14 10 13 14 10 14 10 14 10 14 10 14 TABLE_SPACING_ASSIGNMENT_ITEM FSB_ADDR FSB_ADSTB * FSB_ADDR2ADSTB FSB_DATA FSB_DATA * FSB_DATA2DATA FSB_DATA FSB_DSTB * FSB_DATA2DSTB TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM NOTE: Design Guide does not indicate FSB spacing to other signals, assumed 3:1 NOTE: Design Guide allows closer spacing if signal lengths can be shortened SOURCE: Santa Rosa Platform DG, Rev 0.9 (#20517), Sections 4.2 & 4.3 C CPU Signal Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP CPU_27P4S * Y =27P4_OHM_SE =27P4_OHM_SE =27P4_OHM_SE MIL MIL CPU_55S * Y =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD SPACING_RULE_SET LAYER 10 14 10 14 10 14 10 14 10 14 10 14 10 14 10 14 10 14 10 14 10 14 10 14 10 14 10 14 C 10 14 10 14 10 14 TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM NOTE: mil gap is for VCCSense pair, which Intel says to route with mil spacing without specifying a target differential impedance TABLE_SPACING_RULE_HEAD LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM CPU_2TO1 * =2:1_SPACING ? CPU_COMP * 25 MIL ? TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM CPU_GTLREF * 25 MIL ? DG recommends at least 25 mils, >50 mils preferred TABLE_SPACING_RULE_ITEM CPU_ITP * =2:1_SPACING ? TABLE_SPACING_RULE_ITEM CPU_VCCSENSE * 25 MIL ? Most CPU signals with impedance requirements are 55-ohm single-ended Some signals require 27.4-ohm single-ended impedance (See above) SOURCE: Santa Rosa Platform DG, Rev 0.9 (#20517), Sections 4.4 & 5.8.2.4 CPU_BSEL0 (See above) CPU_BSEL1 (See above) CPU_BSEL2 (See above) B (FSB_CPURST_L) CPU_VCCSENSE CPU_VCCSENSE CPU_2TO1 CPU_2TO1 CPU_2TO1 CPU_2TO1 CPU_2TO1 CPU_2TO1 CPU_2TO1 CPU_2TO1 CPU_2TO1 CPU_IERR_L CPU_FERR_L CPU_PROCHOT_L CPU_PWRGD CPU_INTR CPU_NMI CPU_A20M_L CPU_DPSLP_L CPU_IGNNE_L CPU_INIT_L CPU_SMI_L CPU_STPCLK_L PM_THRMTRIP_L FSB_CPUSLP_L PM_DPRSLPVR IMVP_DPRSLPVR CPU_BSEL NB_BSEL CPU_BSEL NB_BSEL CPU_BSEL NB_BSEL CPU_DPRSTP_L CPU_55S CPU_55S CPU_27P4S CPU_55S CPU_27P4S CPU_GTLREF CPU_COMP CPU_COMP CPU_COMP CPU_COMP CPU_GTLREF CPU_COMP CPU_COMP CPU_COMP CPU_COMP CPU_55S CPU_55S CPU_55S CPU_55S CPU_55S CPU_55S CPU_55S CLK_FSB_100D CLK_FSB_100D CPU_55S CPU_ITP CPU_ITP CPU_ITP CPU_ITP CPU_ITP CPU_ITP CPU_ITP CLK_FSB CLK_FSB CPU_ITP XDP_TDI XDP_TDO XDP_TMS XDP_TCK XDP_TRST_L XDP_BPM_L XDP_BPM_L XDP_CLK_P XDP_CLK_N XDP_CPURST_L CPU_55S CPU_55S CPU_27P4S CPU_27P4S CPU_27P4S CPU_27P4S CPU_2TO1 CPU_2TO1 CPU_VCCSENSE CPU_VCCSENSE CPU_VCCSENSE CPU_VCCSENSE CPU_VID IMVP6_VID CPU_VCCSENSE_P CPU_VCCSENSE_N IMVP6_VSEN_P IMVP6_VSEN_N CPU_2TO1 CPU_2TO1 10 10 23 10 46 59 10 13 23 10 23 10 23 10 23 10 23 10 23 10 23 47 10 23 10 23 10 16 23 46 10 14 16 25 59 59 10 30 13 16 30 10 30 13 16 30 10 30 13 16 30 B 10 16 23 59 10 10 10 10 10 10 13 10 13 10 13 10 13 10 13 10 13 10 13 13 29 30 88 13 29 30 88 13 11 12 12 59 11 59 11 59 59 59 CPU/FSB Constraints SYNC_MASTER=T9_NOME A SYNC_DATE=01/25/2007 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC SCALE SHT NONE REV 051-7431 A.0.0 OF 83 92 A PCI-Express / DMI Bus Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP PCIE_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF DMI_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF ELECTRICAL_CONSTRAINT_SET NET_TYPE PHYSICAL SPACING TABLE_PHYSICAL_RULE_ITEM PEG_R2D TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT PEG_D2R TABLE_SPACING_RULE_ITEM PCIE * ? 20 MIL TABLE_SPACING_RULE_ITEM DMI D * ? 20 MIL SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Sections 7.2, 9.2 & 10.5 DMI_N2S Video Signal Constraints DMI_S2N TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP LVDS_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF CRT_50S * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD LVDS_A_CLK LVDS_A_CLK LVDS_A_DATA LVDS_A_DATA LVDS_A_DATA3 LVDS_A_DATA3 LVDS_B_CLK LVDS_B_CLK LVDS_B_DATA LVDS_B_DATA LVDS_B_DATA3 LVDS_B_DATA3 LVDS_IBG TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM CRT_55S * =55_OHM_SE SPACING_RULE_SET LAYER =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD TABLE_SPACING_RULE_HEAD LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM LVDS * 20 MIL ? CRT * 25 MIL ? TABLE_SPACING_RULE_ITEM DG Says 40 mil spacing minimum TABLE_SPACING_RULE_ITEM CRT_2CRT * 20 MIL ? CRT_SYNC * 25 MIL ? CRT_SYNC2SYNC * 20 MIL ? TVDAC * 25 MIL ? TVDAC_2TVDAC * 20 MIL ? TABLE_SPACING_RULE_ITEM DG Says 30 mil spacing minimum PCIE_100D PCIE_100D PCIE_100D PCIE_100D PCIE_100D PCIE_100D PCIE_100D PCIE_100D PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PEG_R2D_P PEG_R2D_N PEG_R2D_C_P PEG_R2D_C_N PEG_D2R_P PEG_D2R_N PEG_D2R_C_P PEG_D2R_C_N DMI_100D DMI_100D DMI_100D DMI_100D DMI DMI DMI DMI DMI_N2S_P DMI_N2S_N DMI_S2N_P DMI_S2N_N LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS NC_LVDS_A_CLKP NC_LVDS_A_CLKN LVDS_A_DATA_P LVDS_A_DATA_N LVDS_A_DATA_P LVDS_A_DATA_N NC_LVDS_B_CLKP NC_LVDS_B_CLKN LVDS_B_DATA_P LVDS_B_DATA_N LVDS_B_DATA_P LVDS_B_DATA_N NC_LVDS_IBG CRT CRT CRT CRT CRT_SYNC CRT_SYNC TVDAC TVDAC TVDAC CRT_TVO_IREF CRT_RED CRT_GREEN CRT_BLUE CRT_HSYNC_R CRT_VSYNC_R TV_A_DAC TV_B_DAC TV_C_DAC 67 67 15 67 15 67 15 67 15 67 67 67 D 16 24 16 24 16 24 16 24 15 22 15 22 15 22 15 22 15 22 15 22 15 22 15 22 15 22 TABLE_SPACING_RULE_ITEM CRT_TVO_IREF CRT_RED CRT_GREEN CRT_BLUE CRT_SYNC CRT_SYNC TV_A_DAC TV_B_DAC TV_C_DAC TABLE_SPACING_RULE_ITEM DG Says 40 mil spacing minimum TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET TABLE_SPACING_ASSIGNMENT_ITEM C CRT CRT * CRT_2CRT CRT_SYNC CRT_SYNC * CRT_SYNC2SYNC TVDAC TVDAC * TVDAC_2TVDAC TABLE_SPACING_ASSIGNMENT_ITEM CRT_50S CRT_50S CRT_50S CRT_55S CRT_55S CRT_50S CRT_50S CRT_50S C TABLE_SPACING_ASSIGNMENT_ITEM LVDS signals are 100-ohm +/- 20% differential impedence CRT & TVDAC signal single-ended impedence varies by location: - 37.5-ohm +/- 15% from GMCH to first termination resistor - 50-ohm +/- 15% from first to second termination resistor - 55-ohm +/- 15% from second termination resistor to connector CRT_HSYNC/CRT_VSYNC signals are 55-ohm +/- 15% single-ended impedence SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Sections 8.1 - 8.3 B B NB Constraints SYNC_MASTER=T9_NOME A SYNC_DATE=01/25/2007 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC SCALE SHT NONE REV 051-7431 A.0.0 OF 84 92 A DDR2 Memory Bus Constraints Memory Net Properties TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP MEM_45S * =45_OHM_SE =45_OHM_SE =45_OHM_SE =45_OHM_SE =STANDARD =STANDARD MEM_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD ELECTRICAL_CONSTRAINT_SET NET_TYPE PHYSICAL SPACING TABLE_PHYSICAL_RULE_ITEM MEM_A_CLK MEM_70D MEM_70D MEM_CLK MEM_CLK MEM_CLK_P MEM_CLK_N MEM_A_CNTL MEM_A_CNTL MEM_A_CNTL MEM_45S MEM_45S MEM_45S MEM_CTRL MEM_CTRL MEM_CTRL MEM_CKE MEM_CS_L MEM_ODT MEM_A_CMD MEM_A_CMD MEM_A_CMD MEM_A_CMD MEM_A_CMD MEM_55S MEM_55S MEM_55S MEM_55S MEM_55S MEM_CMD MEM_CMD MEM_CMD MEM_CMD MEM_CMD MEM_A_A MEM_A_BS MEM_A_RAS_L MEM_A_CAS_L MEM_A_WE_L MEM_A_DQ_BYTE0 MEM_A_DQ_BYTE1 MEM_A_DQ_BYTE2 MEM_A_DQ_BYTE3 MEM_A_DQ_BYTE4 MEM_A_DQ_BYTE5 MEM_A_DQ_BYTE6 MEM_A_DQ_BYTE7 MEM_55S MEM_55S MEM_55S MEM_55S MEM_55S MEM_55S MEM_55S MEM_55S MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DM0 MEM_A_DM1 MEM_A_DM2 MEM_A_DM3 MEM_A_DM4 MEM_A_DM5 MEM_A_DM6 MEM_A_DM7 MEM_55S MEM_55S MEM_55S MEM_55S MEM_55S MEM_55S MEM_55S MEM_55S MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_A_DM MEM_A_DM MEM_A_DM MEM_A_DM MEM_A_DM MEM_A_DM MEM_A_DM MEM_A_DM MEM_A_DQS0 MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_B_CLK MEM_70D MEM_70D MEM_CLK MEM_CLK MEM_CLK_P MEM_CLK_N MEM_B_CNTL MEM_B_CNTL MEM_B_CNTL MEM_45S MEM_45S MEM_45S MEM_CTRL MEM_CTRL MEM_CTRL MEM_CKE MEM_CS_L MEM_ODT MEM_B_CMD MEM_B_CMD MEM_B_CMD MEM_B_CMD MEM_B_CMD MEM_55S MEM_55S MEM_55S MEM_55S MEM_55S MEM_CMD MEM_CMD MEM_CMD MEM_CMD MEM_CMD MEM_B_A MEM_B_BS MEM_B_RAS_L MEM_B_CAS_L MEM_B_WE_L MEM_B_DQ_BYTE0 MEM_B_DQ_BYTE1 MEM_B_DQ_BYTE2 MEM_B_DQ_BYTE3 MEM_B_DQ_BYTE4 MEM_B_DQ_BYTE5 MEM_B_DQ_BYTE6 MEM_B_DQ_BYTE7 MEM_55S MEM_55S MEM_55S MEM_55S MEM_55S MEM_55S MEM_55S MEM_55S MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DM0 MEM_B_DM1 MEM_B_DM2 MEM_B_DM3 MEM_B_DM4 MEM_B_DM5 MEM_B_DM6 MEM_B_DM7 MEM_55S MEM_55S MEM_55S MEM_55S MEM_55S MEM_55S MEM_55S MEM_55S MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_B_DM MEM_B_DM MEM_B_DM MEM_B_DM MEM_B_DM MEM_B_DM MEM_B_DM MEM_B_DM MEM_B_DQS0 MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N TABLE_PHYSICAL_RULE_ITEM 16 31 16 31 TABLE_PHYSICAL_RULE_ITEM MEM_70D * =70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF MEM_85D * =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF SPACING_RULE_SET LAYER TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_HEAD D LINE-TO-LINE SPACING WEIGHT =4:1_SPACING ? TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET MEM_CLK MEM_CLK * MEM_CLK2MEM TABLE_SPACING_RULE_ITEM MEM_CLK2MEM * TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_RULE_ITEM MEM_CTRL2CTRL * TABLE_SPACING_ASSIGNMENT_ITEM ? =2:1_SPACING MEM_CLK MEM_CTRL * MEM_CLK2MEM TABLE_SPACING_RULE_ITEM MEM_CTRL2MEM * MEM_CLK MEM_CMD * MEM_CLK2MEM MEM_CLK MEM_DATA * MEM_CLK2MEM TABLE_SPACING_RULE_ITEM MEM_CMD2CMD * =1.5:1_SPACING TABLE_SPACING_ASSIGNMENT_ITEM ? TABLE_SPACING_RULE_ITEM MEM_CMD2MEM * TABLE_SPACING_ASSIGNMENT_ITEM ? =3:1_SPACING MEM_CLK MEM_DQS * MEM_CLK2MEM TABLE_SPACING_RULE_ITEM MEM_DATA2DATA * =1.5:1_SPACING ? TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 TABLE_SPACING_RULE_ITEM MEM_DATA2MEM * =3:1_SPACING ? NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET TABLE_SPACING_ASSIGNMENT_ITEM MEM_CMD TABLE_SPACING_RULE_ITEM MEM_DQS2MEM * =3:1_SPACING 16 31 33 16 31 33 16 17 31 33 17 31 33 D 17 31 33 17 31 33 17 31 33 TABLE_SPACING_ASSIGNMENT_ITEM ? =3:1_SPACING 16 31 33 ? MEM_CLK * MEM_CMD2MEM 17 31 17 31 17 31 17 31 17 31 17 31 17 31 17 31 TABLE_SPACING_ASSIGNMENT_ITEM MEM_CMD TABLE_SPACING_RULE_ITEM MEM_2OTHER * 25 MIL ? MEM_CTRL * MEM_CMD2MEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CMD MEM_CMD * MEM_CMD2CMD TABLE_SPACING_ASSIGNMENT_ITEM MEM_CMD MEM_DATA * MEM_CMD2MEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CMD MEM_DQS * MEM_CMD2MEM TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET MEM_CTRL MEM_CLK * MEM_CTRL2MEM 17 31 17 31 17 31 17 31 17 31 17 31 17 31 17 31 TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CTRL MEM_CTRL * MEM_CTRL2CTRL MEM_A_DQS1 TABLE_SPACING_ASSIGNMENT_ITEM MEM_CTRL MEM_CMD * MEM_CTRL2MEM MEM_CTRL MEM_DATA * MEM_CTRL2MEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_A_DQS2 TABLE_SPACING_ASSIGNMENT_ITEM C MEM_CTRL MEM_DQS * MEM_CTRL2MEM NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET MEM_DATA MEM_CLK * MEM_DATA2MEM MEM_DATA MEM_CTRL * MEM_DATA2MEM MEM_A_DQS3 TABLE_SPACING_ASSIGNMENT_HEAD MEM_A_DQS4 TABLE_SPACING_ASSIGNMENT_ITEM MEM_A_DQS5 TABLE_SPACING_ASSIGNMENT_ITEM MEM_A_DQS6 TABLE_SPACING_ASSIGNMENT_ITEM MEM_DATA MEM_CMD * MEM_DATA2MEM MEM_DATA MEM_DATA * MEM_DATA2DATA TABLE_SPACING_ASSIGNMENT_ITEM MEM_A_DQS7 TABLE_SPACING_ASSIGNMENT_ITEM MEM_DATA MEM_DQS * MEM_DATA2MEM TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE MEM_CLK * * MEM_2OTHER * * MEM_2OTHER TABLE_SPACING_ASSIGNMENT_ITEM MEM_DQS MEM_CLK * MEM_DQS2MEM MEM_DQS MEM_CTRL * MEM_DQS2MEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CMD * * MEM_2OTHER MEM_DATA * * MEM_2OTHER MEM_DQS * * MEM_2OTHER 17 31 17 31 17 31 17 31 17 31 C 17 31 17 31 17 31 17 31 17 31 17 31 17 31 17 31 17 31 17 31 16 32 16 32 SPACING_RULE_SET TABLE_SPACING_ASSIGNMENT_ITEM MEM_CTRL 17 31 16 32 33 16 32 33 16 32 33 TABLE_SPACING_ASSIGNMENT_ITEM MEM_DQS MEM_CMD * MEM_DQS2MEM MEM_DQS MEM_DATA * MEM_DQS2MEM MEM_DQS MEM_DQS * MEM_DQS2MEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM Need to support MEM_*-style wildcards! SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Section 6.2 B MEM_B_DQS1 MEM_B_DQS2 MEM_B_DQS3 MEM_B_DQS4 MEM_B_DQS5 MEM_B_DQS6 A MEM_B_DQS7 16 17 32 33 17 32 33 17 32 33 17 32 33 17 32 33 17 32 17 32 17 32 17 32 B 17 32 17 32 17 32 17 32 17 32 17 32 17 32 17 32 17 32 17 32 17 32 17 32 17 32 17 32 17 32 17 32 17 32 17 32 17 32 17 32 17 32 17 32 17 32 Memory Constraints 17 32 17 32 SYNC_MASTER=T9_NOME SYNC_DATE=01/25/2007 17 32 NOTICE OF PROPRIETARY PROPERTY 17 32 17 32 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC SCALE SHT NONE REV 051-7431 A.0.0 OF 85 92 A Disk Interface Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP IDE_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD SATA_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD ELECTRICAL_CONSTRAINT_SET NET_TYPE PHYSICAL SPACING TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM SATA_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM D IDE * =1.8:1_SPACING ? SATA * 20 MIL ? TABLE_SPACING_RULE_ITEM SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Sections 10.7 & 10.9 HD Audio Interface Constraints IDE_PDD IDE_PDA IDE_PDCS IDE_PDCS IDE_CNTL IDE_PDIOR_L IDE_CNTL IDE_CNTL IDE_PDIORDY IDE_IRQ14 IDE_RST_L IDE_55S IDE_55S IDE_55S IDE_55S IDE_55S IDE_55S IDE_55S IDE_55S IDE_55S IDE_55S IDE_55S IDE IDE IDE IDE IDE IDE IDE IDE IDE IDE IDE IDE_PDD IDE_PDA IDE_PDCS1_L IDE_PDCS3_L IDE_PDIOW_L IDE_PDIOR_L IDE_PDDACK_L IDE_PDDREQ IDE_PDIORDY IDE_IRQ14 ODD_RST_5VTOL_L SATA_A_R2D SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D SATA_55S SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA_A_R2D_C_P SATA_A_R2D_C_N SATA_A_R2D_P SATA_A_R2D_N SATA_A_D2R_P SATA_A_D2R_N SATA_A_D2R_C_P SATA_A_D2R_C_N TP_SATA_B_R2DP TP_SATA_B_R2DN SATA_B_R2D_P SATA_B_R2D_N TP_SATA_B_D2RP TP_SATA_B_D2RN SATA_B_D2R_C_P SATA_B_D2R_C_N TP_SATA_C_R2DP TP_SATA_C_R2DN SATA_C_R2D_P SATA_C_R2D_N TP_SATA_C_D2RP TP_SATA_C_D2RN SATA_C_D2R_C_P SATA_C_D2R_C_N SATA_RBIAS HDA_55S HDA_55S HDA_55S HDA_55S HDA_55S HDA_55S HDA_55S HDA_55S HDA_55S HDA_55S HDA HDA HDA HDA HDA HDA HDA HDA HDA HDA HDA_BIT_CLK HDA_BIT_CLK_R HDA_SYNC HDA_SYNC_R HDA_RST_L HDA_RST_L_R HDA_SDIN0 HDA_SDIN_CODEC HDA_SDOUT HDA_SDOUT_R USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB_RBIAS USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_60S USB_EXTA_P USB_EXTA_N USB_EXTA_MUXED_P USB_EXTA_MUXED_N USB_MINI_P USB_MINI_N TP_USB_EXTDP TP_USB_EXTDN USB_CAMERA_P USB_CAMERA_N USB_BT_P USB_BT_N USB_TPAD_P USB_TPAD_N USB_IR_P USB_IR_N USB_EXTB_P USB_EXTB_N USB_EXCARD_P USB_EXCARD_N USB_EXTC_P USB_EXTC_N USB_RBIAS SMB_SB_SCL SMB_SB_SDA SMB_SB_ME_SCL SMB_SB_ME_SDA SMB_55S SMB_55S SMB_55S SMB_55S SMB SMB SMB SMB SMBUS_SB_SCL SMBUS_SB_SDA SMBUS_SB_ME_SCL SMBUS_SB_ME_SDA SPI_SCLK SPI_55S SPI_55S SPI_55S SPI_55S SPI_55S SPI_55S SPI_55S SPI_55S SPI_55S SPI_55S SPI_55S SPI_55S SPI_55S SPI_55S SPI_55S SPI_55S SPI SPI SPI SPI SPI SPI SPI SPI SPI SPI SPI SPI SPI SPI SPI SPI SPI_SCLK_R SPI_SCLK SPI_A_SCLK_R SPI_B_SCLK_R SPI_SI_R SPI_SI SPI_A_SI_R SPI_B_SI_R SPI_SO SPI_A_SO_R SPI_B_SO SPI_B_SO_R SPI_CE_R_L SPI_CE_L SPI_CE_R_L SPI_CE_L TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM HDA_55S * SPACING_RULE_SET LAYER =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD SATA_A_D2R TABLE_SPACING_RULE_HEAD LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM HDA * =1.8:1_SPACING ? SATA_B_R2D SOURCE: Napa Platform DG, Rev 0.9 (#17978), Section 10.9.1 USB 2.0 Interface Constraints SATA_B_D2R TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM USB_60S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD USB_90D * =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF SATA_C_R2D TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT 20 MIL ? SATA_C_D2R TABLE_SPACING_RULE_ITEM USB * TABLE_SPACING_RULE_ITEM C USB_2CLK * DG says minimum spacing 50 mils to clocks ? 25 MIL SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Section 10.13.2 SATA_RBIAS HDA_BIT_CLK Internal Interface Constraints HDA_SYNC TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM SMB_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD HDA_RST_L TABLE_PHYSICAL_RULE_ITEM SPI_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD HDA_SDIN0 TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT =3:1_SPACING ? HDA_SDOUT TABLE_SPACING_RULE_ITEM SMB * USB_EXTA TABLE_SPACING_RULE_ITEM SPI * =1.8:1_SPACING ? SOURCE: Santa Platform DG, Rev 1.0 (#21112), Section 10.17 USB_MINI USB_EXTD USB_CAMERA USB_BT USB_TPAD B USB_IR USB_EXTB USB_EXCARD USB_EXTC SPI_SI SPI_SO A SPI_CE_L0 SPI_CE_L1 23 42 23 42 23 42 23 42 23 42 23 42 23 42 23 42 D 23 42 23 42 24 42 23 81 23 81 81 81 23 81 23 81 23 42 23 42 23 42 23 42 23 42 23 42 23 42 23 42 C 23 42 23 34 23 23 34 23 23 34 23 23 34 23 34 23 24 43 24 43 24 34 24 34 24 24 24 44 24 44 24 81 24 81 24 81 B 24 81 24 81 24 81 24 34 24 34 24 34 24 34 24 34 24 34 24 25 29 31 32 34 48 25 29 31 32 34 48 25 48 25 48 24 56 56 24 56 56 24 56 SB Constraints (1 of 2) 56 SYNC_MASTER=T9_NOME SYNC_DATE=01/25/2007 NOTICE OF PROPRIETARY PROPERTY 24 56 56 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC SCALE SHT NONE REV 051-7431 A.0.0 OF 86 92 A PCI Bus Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP PCI_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD ELECTRICAL_CONSTRAINT_SET NET_TYPE PHYSICAL SPACING TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM PCI * ? =2:1_SPACING SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Sections 10.18.1 & 10.19 D Controller Link (AMT) Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM CLINK_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD CLINK_12MIL * =STANDARD 12 MILS MILS 300 MILS =STANDARD =STANDARD TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM CLINK * =1.8:1_SPACING ? CLINK_VREF * 12 MILS ? TABLE_SPACING_RULE_ITEM SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Sections 10.27.1.5-7, 10.29 & 10.30 Ethernet (Yukon) Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? ENET_100D * =100_OHM_DIFF MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF PCI_AD PCI_AD19 PCI_AD20 PCI_AD PCI_AD PCI_C_BE_L PCI_CNTL PCI_CNTL PCI_CNTL PCI_LOCK_L PCI_CNTL PCI_CNTL PCI_CNTL PCI_CNTL PCI_FW_REQ_L PCI_FW_GNT_L PCI_REQ1_L PCI_GNT1_L PCI_REQ2_L PCI_GNT2_L INT_PIRQA_L INT_PIRQB_L INT_PIRQC_L INT_PIRQD_L PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI_AD PCI_AD PCI_AD PCI_AD PCI_PAR PCI_C_BE_L PCI_IRDY_L PCI_DEVSEL_L PCI_PERR_L PCI_LOCK_L PCI_SERR_L PCI_STOP_L PCI_TRDY_L PCI_FRAME_L PCI_FW_REQ_L PCI_FW_GNT_L PCI_REQ1_L PCI_GNT1_L PCI_REQ2_L PCI_GNT2_L INT_PIRQA_L INT_PIRQB_L INT_PIRQC_L INT_PIRQD_L INT_PIRQF_L PCI_55S PCI INT_PIRQF_L PCIE_A_R2D PCIE_100D PCIE_100D PCIE_100D PCIE_100D PCIE_100D PCIE_100D PCIE_100D PCIE_100D PCIE_100D PCIE_100D PCIE_100D PCIE_100D PCIE_100D PCIE_100D PCIE_100D PCIE_100D PCIE_100D PCIE_100D PCIE_100D PCIE_100D PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE_A_R2D_C_P PCIE_A_R2D_C_N PCIE_A_D2R_P PCIE_A_D2R_N PCIE_B_R2D_C_P PCIE_B_R2D_C_N PCIE_B_D2R_P PCIE_B_D2R_N PCIE_EXCARD_R2D_C_P PCIE_EXCARD_R2D_C_N PCIE_EXCARD_D2R_P PCIE_EXCARD_D2R_N PCIE_FW_R2D_C_P PCIE_FW_R2D_C_N PCIE_FW_D2R_P PCIE_FW_D2R_N PCIE_MINI_R2D_C_P PCIE_MINI_R2D_C_N PCIE_MINI_D2R_P PCIE_MINI_D2R_N 24 38 24 38 24 38 24 38 24 38 24 38 24 38 24 38 D 24 38 24 24 38 24 38 24 38 24 38 24 38 24 38 47 24 24 24 24 24 24 38 TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT 25 MILS ? TABLE_SPACING_RULE_ITEM ENET_MDI * PCIE_A_D2R SOURCE: Based on Santa Rosa Platform DG, Rev 1.0 (#21112), Sections 10.27.1.5-7, 10.29 & 10.30 PCIE_B_R2D PCIE_B_D2R C PCIE_EXCARD_R2D PCIE_EXCARD_D2R PCIE_FW_R2D PCIE_FW_D2R PCIE_MINI_R2D PCIE_MINI_D2R GLAN_COMP GLAN_COMP CLINK_NB CLINK_NB CLINK_NB_RESET_L CLINK_WLAN CLINK_WLAN CLINK_WLAN_RESET_L NB_CLINK_VREF SB_CLINK_VREF0 SB_CLINK_VREF1 CLINK_55S CLINK_55S CLINK_55S CLINK_55S CLINK_55S CLINK_55S CLINK_12MIL CLINK_12MIL CLINK_12MIL CLINK CLINK CLINK CLINK CLINK CLINK CLINK_VREF CLINK_VREF CLINK_VREF CLINK_NB_CLK CLINK_NB_DATA CLINK_NB_RESET_L CLINK_WLAN_CLK CLINK_WLAN_DATA CLINK_WLAN_RESET_L NB_CLINK_VREF SB_CLINK_VREF0 SB_CLINK_VREF1 PCIE_ENET_R2D PCIE_100D PCIE_100D PCIE_100D PCIE_100D PCIE_100D PCIE_100D PCIE_100D PCIE_100D PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE_ENET_R2D_C_P PCIE_ENET_R2D_C_N PCIE_ENET_R2D_P PCIE_ENET_R2D_N PCIE_ENET_D2R_P PCIE_ENET_D2R_N PCIE_ENET_D2R_C_P PCIE_ENET_D2R_C_N ENET_100D ENET_100D ENET_100D ENET_100D ENET_100D ENET_100D ENET_100D ENET_100D ENET_MDI ENET_MDI ENET_MDI ENET_MDI ENET_MDI ENET_MDI ENET_MDI ENET_MDI ENET_MDI_P ENET_MDI_N ENET_MDI_P ENET_MDI_N ENET_MDI_P ENET_MDI_N ENET_MDI_P ENET_MDI_N B PCIE_ENET_D2R ENET_MDI ENET_MDI ENET_MDI ENET_MDI 24 C 24 34 24 34 24 34 24 34 24 34 24 34 24 34 24 34 23 16 25 16 25 16 25 16 25 25 24 35 24 35 35 B 35 24 35 24 35 35 35 35 37 35 37 35 37 35 37 35 37 35 37 35 37 35 37 SB Constraints (2 of 2) SYNC_MASTER=T9_NOME A SYNC_DATE=01/25/2007 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC SCALE SHT NONE REV 051-7431 A.0.0 OF 87 92 A Clock Signal Constraints Clock Net Properties TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP CLK_FSB_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF CLK_PCIE_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF ELECTRICAL_CONSTRAINT_SET NET_TYPE PHYSICAL SPACING TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM CLK_MED_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD CLK_SLOW_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD TABLE_PHYSICAL_RULE_ITEM CK505_CPU CK505_CPU CK505_NB CK505_NB CK505_ITP CK505_ITP CLK_FSB_100D CLK_FSB_100D CLK_FSB_100D CLK_FSB_100D CLK_FSB_100D CLK_FSB_100D CLK_FSB CLK_FSB CLK_FSB CLK_FSB CLK_FSB CLK_FSB FSB_CLK_CPU_P FSB_CLK_CPU_N FSB_CLK_NB_P FSB_CLK_NB_N XDP_CLK_P XDP_CLK_N CK505_PCIF0 CK505_PCIF1 CK505_PCI1 CK505_PCI2 CK505_PCI3 CK505_PCI4 CK505_PCI5 CLK_MED_55S CLK_MED_55S CLK_MED_55S CLK_MED_55S CLK_MED_55S CLK_MED_55S CLK_MED_55S CLK_MED CLK_MED CLK_MED CLK_MED CLK_MED CLK_MED CLK_MED CK505_PCIF0_CLK_ITPEN CK505_PCIF1_CLK CK505_PCI1_CLK TP_CK505_PCI2_CLK CK505_PCI3_CLK TP_CK505_PCI4_CLK CK505_PCI5_CLK_FCTSEL (CPU_BSEL0) (CPU_BSEL2) CLK_MED_55S CLK_MED_55S CLK_MED CLK_MED CK505_48M_FSA CK505_REF0_FSC CK505_DOT96 CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CK505_CLK27M CK505_CLK27M_SS TP_NB_CLK100M_DPLLSS_P TP_NB_CLK100M_DPLLSS_N PEG_CLK100M_GPU_P PEG_CLK100M_GPU_N SB_CLK100M_DMI_P SB_CLK100M_DMI_N PCIE_CLK100M_EXCARD_P PCIE_CLK100M_EXCARD_N SB_CLK100M_SATA_P SB_CLK100M_SATA_N NB_CLK100M_PCIE_P NB_CLK100M_PCIE_N PCIE_CLK100M_MINI_P PCIE_CLK100M_MINI_N TP_PCIE_CLK100M_SRC7P TP_PCIE_CLK100M_SRC7N PCIE_CLK100M_ENET_P PCIE_CLK100M_ENET_N (CK505_CPU) (CK505_CPU) (CK505_NB) (CK505_NB) (CK505_ITP) (CK505_ITP) CLK_FSB_100D CLK_FSB_100D CLK_FSB_100D CLK_FSB_100D CLK_FSB_100D CLK_FSB_100D CLK_FSB CLK_FSB CLK_FSB CLK_FSB CLK_FSB CLK_FSB FSB_CLK_CPU_P FSB_CLK_CPU_N FSB_CLK_NB_P FSB_CLK_NB_N XDP_CLK_P XDP_CLK_N (CK505_PCIF0) (CK505_PCIF1) (CK505_PCI1) (CK505_PCI2) (CK505_PCI3) CLK_MED_55S CLK_MED_55S CLK_MED_55S CLK_MED_55S CLK_MED_55S CLK_MED CLK_MED CLK_MED CLK_MED CLK_MED PCI_CLK33M_LPCPLUS 30 47 PCI_CLK33M_SB 24 30 PCI_CLK33M_FW 30 38 PCI_CLK33M_TPM PCI_CLK33M_SMC 30 45 CK505 PCI4 is project-specific CK505 PCI5 is project-specific (CPU_BSEL0) (CPU_BSEL2) CLK_MED_55S CLK_MED_55S CLK_MED CLK_MED SB_CLK48M_USBCTLR SB_CLK14P3M_TIMER (CPU_BSEL0) (CPU_BSEL2) CLK_MED_55S CLK_MED_55S CLK_MED CLK_MED CK505_FSA CK505_FSC (CK505_DOT96) (CK505_DOT96) (CK505_LVDS) (CK505_LVDS) (CK505_SRC1) (CK505_SRC1) (CK505_SRC2) (CK505_SRC2) (CK505_SRC3) (CK505_SRC3) (CK505_SRC4) (CK505_SRC4) (CK505_SRC5) (CK505_SRC5) (CK505_SRC6) (CK505_SRC6) CRT_50S CRT_50S CRT_50S CRT_50S CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D GND GND GND GND CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE NB_CLK96M_DOT_P NB_CLK96M_DOT_N NB_CLK100M_DPLLSS_P NB_CLK100M_DPLLSS_N PEG_CLK100M_GPU_P PEG_CLK100M_GPU_N SB_CLK100M_DMI_P SB_CLK100M_DMI_N PCIE_CLK100M_EXCARD_P PCIE_CLK100M_EXCARD_N SB_CLK100M_SATA_P SB_CLK100M_SATA_N NB_CLK100M_PCIE_P NB_CLK100M_PCIE_N PCIE_CLK100M_MINI_P PCIE_CLK100M_MINI_N 10 29 30 88 10 29 30 88 14 29 30 88 14 29 30 88 13 29 30 83 88 13 29 30 83 88 TABLE_SPACING_RULE_HEAD SPACING_RULE_SET D LAYER LINE-TO-LINE SPACING WEIGHT 25 MIL ? TABLE_SPACING_RULE_ITEM CLK_FSB * TABLE_SPACING_RULE_ITEM CLK_PCIE * 20 MIL ? CLK_MED * 20 MIL ? TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM CLK_SLOW * 10 MIL ? SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Sections 14.1 - 14.6 CK505_LVDS CK505_SRC1 CK505_SRC2 CK505_SRC3 CK505_SRC4 CK505_SRC5 CK505_SRC6 CK505_SRC7 C CK505_SRC8 B 29 30 D 29 30 29 30 29 30 29 30 29 30 29 30 29 30 29 30 29 30 29 30 29 30 29 30 29 30 67 88 29 30 67 88 24 29 30 88 24 29 30 88 29 30 34 88 29 30 34 88 23 29 30 88 23 29 30 88 16 29 30 88 16 29 30 88 29 30 34 88 29 30 34 88 29 30 29 30 C 29 30 35 88 29 30 35 88 10 29 30 88 10 29 30 88 14 29 30 88 14 29 30 88 13 29 30 83 88 13 29 30 83 88 25 30 25 30 30 30 B 29 30 67 88 29 30 67 88 24 29 30 88 24 29 30 88 29 30 34 88 29 30 34 88 23 29 30 88 23 29 30 88 16 29 30 88 16 29 30 88 29 30 34 88 29 30 34 88 CK505 SRC7 is project-specific (CK505_SRC8) (CK505_SRC8) CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE CLK_PCIE PCIE_CLK100M_ENET_P PCIE_CLK100M_ENET_N 29 30 35 88 29 30 35 88 SMC SMBus Net Properties ELECTRICAL_CONSTRAINT_SET SMBUS_SMC_A_S3_SCL SMBUS_SMC_A_S3_SDA SMBUS_SMC_B_S0_SCL SMBUS_SMC_B_S0_SDA SMBUS_SMC_0_S0_SCL SMBUS_SMC_0_S0_SDA SMBUS_SMC_BSA_SCL SMBUS_SMC_BSA_SDA SMBUS_SMC_MGMT_SCL SMBUS_SMC_MGMT_SDA A NET_TYPE PHYSICAL SPACING SMB_55S SMB_55S SMB_55S SMB_55S SMB_55S SMB_55S SMB_55S SMB_55S SMB_55S SMB_55S SMB SMB SMB SMB SMB SMB SMB SMB SMB SMB SMBUS_SMC_A_S3_SCL SMBUS_SMC_A_S3_SDA SMBUS_SMC_B_S0_SCL SMBUS_SMC_B_S0_SDA SMBUS_SMC_0_S0_SCL SMBUS_SMC_0_S0_SDA SMBUS_SMC_BSA_SCL SMBUS_SMC_BSA_SDA SMBUS_SMC_MGMT_SCL SMBUS_SMC_MGMT_SDA 34 45 48 51 81 34 45 48 51 81 45 48 51 53 45 48 51 53 45 48 51 74 Clock & SMC Constraints SYNC_MASTER=M87_MLB SYNC_DATE=08/28/2007 45 48 51 74 NOTICE OF PROPRIETARY PROPERTY 45 48 57 45 48 57 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING 45 48 55 45 48 55 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC SCALE SHT NONE REV 051-7431 A.0.0 OF 88 92 A FireWire Interface Constraints FireWire Net Properties TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP FW_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD FW_110D * =110_OHM_DIFF =110_OHM_DIFF =110_OHM_DIFF =110_OHM_DIFF =110_OHM_DIFF =110_OHM_DIFF SPACING_RULE_SET LAYER ELECTRICAL_CONSTRAINT_SET NET_TYPE SPACING PHYSICAL TABLE_PHYSICAL_RULE_ITEM FW_55S FW_55S CLK_MED_55S CLK_MED_55S CLK_MED_55S CLK_MED_55S FW_55S FW_55S FW_55S FW_55S FW_55S FW FW CLK_MED CLK_MED CLK_MED CLK_MED FW FW FW FW FW FW_LINK FW_CTL CLKFW_LINK_LCLK CLKFW_PHY_LCLK CLKFW_LINK_PCLK CLKFW_PHY_PCLK FW_LKON FW_LKON_R FW_LPS FW_LREQ FW_PINT FWPHY_CLK98P304M_XI CLK_MED_55S CLK_MED_55S CLK_MED CLK_MED CLK98P304M_FW_XI_R CLK98P304M_FW_XI FW_0_TPA FW_0_TPA FW_0_TPB FW_0_TPB FW_1_TPA FW_1_TPA FW_1_TPB FW_1_TPB FW_110D FW_110D FW_110D FW_110D FW_110D FW_110D FW_110D FW_110D FW_TP FW_TP FW_TP FW_TP FW_TP FW_TP FW_TP FW_TP FW_PORT0_TPA_P FW_PORT0_TPA_N FW_PORT0_TPB_P FW_PORT0_TPB_N FW_PORT1_TPA_P FW_PORT1_TPA_N FW_PORT1_TPB_P FW_PORT1_TPB_N FW_D_CTL FW_D_CTL FW_LCLK TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_HEAD LINE-TO-LINE SPACING WEIGHT FW_PCLK TABLE_SPACING_RULE_ITEM FW * =2:1_SPACING ? FW_LKON TABLE_SPACING_RULE_ITEM FW_TP * =3:1_SPACING ? D FW_LPS FW_LREQ FW_PINT 38 39 38 39 D 38 39 38 39 38 39 39 41 39 41 39 41 39 41 39 41 39 41 39 41 39 41 Port Not Used C C B B FireWire Constraints SYNC_MASTER=T9_NOME A SYNC_DATE=01/25/2007 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC SCALE SHT NONE REV 051-7431 A.0.0 OF 89 92 A TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP GDDR3 FB A/B Net Properties DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM GDDR3_40R55SE * =55_OHM_SE =40_OHM_SE =55_OHM_SE 12.7 MM =STANDARD =STANDARD GDDR3_50SE * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD ELECTRICAL_CONSTRAINT_SET GDDR3_80D * =80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF FB_A_CLK_P FB_A_CLK_N FB_A_CLK_P FB_A_CLK_N FB_AB_CMD FB_AB_CMD FB_AB_CMD FB_AB_CMD FB_AB_CMD FB_AB_CMD FB_AB_CMD_PD FB_AB_CS0 FB_AB_CMD_PD GDDR3_40R55SE GDDR3_40R55SE GDDR3_40R55SE GDDR3_40R55SE GDDR3_40R55SE GDDR3_40R55SE GDDR3_40R55SE GDDR3_40R55SE GDDR3_40R55SE GDDR3_CMD GDDR3_CMD GDDR3_CMD GDDR3_CMD GDDR3_CMD GDDR3_CMD GDDR3_CMD GDDR3_CMD GDDR3_CMD FB_A_MA FB_A_MA FB_A_BA FB_A_RAS_L FB_A_CAS_L FB_A_WE_L FB_A_CKE FB_A_CS0_L FB_A_DRAM_RST FB_A_CMD FB_B_CMD GDDR3_50SE GDDR3_50SE GDDR3_CMD GDDR3_CMD FB_A_LMA FB_A_UMA FB_A_WDQS0 FB_A_WDQS1 FB_A_WDQS2 FB_A_WDQS3 GDDR3_50SE GDDR3_50SE GDDR3_50SE GDDR3_50SE GDDR3_DQS GDDR3_DQS GDDR3_DQS GDDR3_DQS FB_A_WDQS FB_A_WDQS FB_A_WDQS FB_A_WDQS FB_A_RDQS0 FB_A_RDQS1 FB_A_RDQS2 FB_A_RDQS3 GDDR3_50SE GDDR3_50SE GDDR3_50SE GDDR3_50SE GDDR3_DQS GDDR3_DQS GDDR3_DQS GDDR3_DQS FB_A_RDQS FB_A_RDQS FB_A_RDQS FB_A_RDQS FB_A_DQ_BYTE0 FB_A_DQ_BYTE1 FB_A_DQ_BYTE2 FB_A_DQ_BYTE3 GDDR3_50SE GDDR3_50SE GDDR3_50SE GDDR3_50SE GDDR3_DATA GDDR3_DATA GDDR3_DATA GDDR3_DATA FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQM0 FB_A_DQM1 FB_A_DQM2 FB_A_DQM3 GDDR3_50SE GDDR3_50SE GDDR3_50SE GDDR3_50SE GDDR3_DATA GDDR3_DATA GDDR3_DATA GDDR3_DATA FB_A_DQM_L FB_A_DQM_L FB_A_DQM_L FB_A_DQM_L FB_B_WDQS0 FB_B_WDQS1 FB_B_WDQS2 FB_B_WDQS3 GDDR3_50SE GDDR3_50SE GDDR3_50SE GDDR3_50SE GDDR3_DQS GDDR3_DQS GDDR3_DQS GDDR3_DQS FB_A_WDQS FB_A_WDQS FB_A_WDQS FB_A_WDQS FB_B_RDQS0 FB_B_RDQS1 FB_B_RDQS2 FB_B_RDQS3 GDDR3_50SE GDDR3_50SE GDDR3_50SE GDDR3_50SE GDDR3_DQS GDDR3_DQS GDDR3_DQS GDDR3_DQS FB_A_RDQS FB_A_RDQS FB_A_RDQS FB_A_RDQS FB_B_DQ_BYTE0 FB_B_DQ_BYTE1 FB_B_DQ_BYTE2 FB_B_DQ_BYTE3 GDDR3_50SE GDDR3_50SE GDDR3_50SE GDDR3_50SE GDDR3_DATA GDDR3_DATA GDDR3_DATA GDDR3_DATA FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_B_DQM0 FB_B_DQM1 FB_B_DQM2 FB_B_DQM3 GDDR3_50SE GDDR3_50SE GDDR3_50SE GDDR3_50SE GDDR3_DATA GDDR3_DATA GDDR3_DATA GDDR3_DATA FB_A_DQM_L FB_A_DQM_L FB_A_DQM_L FB_A_DQM_L FB_B_CLK_P TABLE_SPACING_RULE_HEAD SPACING_RULE_SET D LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM GDDR3_CLK * =2.5:1_SPACING ? TABLE_SPACING_RULE_ITEM GDDR3_CMD * =2.5:1_SPACING ? GDDR3_DATA * =2.5:1_SPACING ? TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM GDDR3_DQS * =2.5:1_SPACING ? Video Signal Constraints ELECTRICAL_CONSTRAINT_SET GDDR3_CLK GDDR3_CLK GDDR3_CLK GDDR3_CLK TABLE_PHYSICAL_RULE_ITEM GDDR3 FB C/D Net Properties NET_TYPE PHYSICAL SPACING GDDR3_80D GDDR3_80D GDDR3_80D GDDR3_80D FB_A_CLK_P TABLE_PHYSICAL_RULE_ITEM GDDR3 Frame Buffer Signal Constraints GDDR3_80D GDDR3_80D GDDR3_80D GDDR3_80D GDDR3_CLK GDDR3_CLK GDDR3_CLK GDDR3_CLK FB_B_CLK_P FB_B_CLK_N FB_B_CLK_P FB_B_CLK_N FB_CD_CMD FB_CD_CMD FB_CD_CMD FB_CD_CMD FB_CD_CMD FB_CD_CMD FB_CD_CMD_PD FB_CD_CS0 FB_CD_CMD_PD GDDR3_40R55SE GDDR3_40R55SE GDDR3_40R55SE GDDR3_40R55SE GDDR3_40R55SE GDDR3_40R55SE GDDR3_40R55SE GDDR3_40R55SE GDDR3_40R55SE GDDR3_CMD GDDR3_CMD GDDR3_CMD GDDR3_CMD GDDR3_CMD GDDR3_CMD GDDR3_CMD GDDR3_CMD GDDR3_CMD FB_B_MA FB_B_MA FB_B_BA FB_B_RAS_L FB_B_CAS_L FB_B_WE_L FB_B_CKE FB_B_CS0_L FB_B_DRAM_RST FB_C_CMD FB_D_CMD GDDR3_50SE GDDR3_50SE GDDR3_CMD GDDR3_CMD FB_B_LMA FB_B_UMA FB_C_WDQS0 FB_C_WDQS1 FB_C_WDQS2 FB_C_WDQS3 GDDR3_50SE GDDR3_50SE GDDR3_50SE GDDR3_50SE GDDR3_DQS GDDR3_DQS GDDR3_DQS GDDR3_DQS FB_B_WDQS FB_B_WDQS FB_B_WDQS FB_B_WDQS FB_C_RDQS0 FB_C_RDQS1 FB_C_RDQS2 FB_C_RDQS3 GDDR3_50SE GDDR3_50SE GDDR3_50SE GDDR3_50SE GDDR3_DQS GDDR3_DQS GDDR3_DQS GDDR3_DQS FB_B_RDQS FB_B_RDQS FB_B_RDQS FB_B_RDQS FB_C_DQ_BYTE0 FB_C_DQ_BYTE1 FB_C_DQ_BYTE2 FB_C_DQ_BYTE3 GDDR3_50SE GDDR3_50SE GDDR3_50SE GDDR3_50SE GDDR3_DATA GDDR3_DATA GDDR3_DATA GDDR3_DATA FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_C_DQM0 FB_C_DQM1 FB_C_DQM2 FB_C_DQM3 GDDR3_50SE GDDR3_50SE GDDR3_50SE GDDR3_50SE GDDR3_DATA GDDR3_DATA GDDR3_DATA GDDR3_DATA FB_B_DQM_L FB_B_DQM_L FB_B_DQM_L FB_B_DQM_L FB_D_WDQS0 FB_D_WDQS1 FB_D_WDQS2 FB_D_WDQS3 GDDR3_50SE GDDR3_50SE GDDR3_50SE GDDR3_50SE GDDR3_DQS GDDR3_DQS GDDR3_DQS GDDR3_DQS FB_B_WDQS FB_B_WDQS FB_B_WDQS FB_B_WDQS FB_D_RDQS0 FB_D_RDQS1 FB_D_RDQS2 FB_D_RDQS3 GDDR3_50SE GDDR3_50SE GDDR3_50SE GDDR3_50SE GDDR3_DQS GDDR3_DQS GDDR3_DQS GDDR3_DQS FB_B_RDQS FB_B_RDQS FB_B_RDQS FB_B_RDQS FB_D_DQ_BYTE0 FB_D_DQ_BYTE1 FB_D_DQ_BYTE2 FB_D_DQ_BYTE3 GDDR3_50SE GDDR3_50SE GDDR3_50SE GDDR3_50SE GDDR3_DATA GDDR3_DATA GDDR3_DATA GDDR3_DATA FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_D_DQM0 FB_D_DQM1 FB_D_DQM2 FB_D_DQM3 GDDR3_50SE GDDR3_50SE GDDR3_50SE GDDR3_50SE GDDR3_DATA GDDR3_DATA GDDR3_DATA GDDR3_DATA FB_B_DQM_L FB_B_DQM_L FB_B_DQM_L FB_B_DQM_L FB_C_CLK_P 69 70 77 69 70 77 FB_D_CLK_P 69 70 77 69 70 77 69 70 77 69 70 77 69 70 77 69 70 77 69 70 77 69 70 77 69 70 77 69 70 69 70 77 69 70 77 69 70 77 NET_TYPE PHYSICAL SPACING 69 71 78 69 71 78 69 71 78 69 71 78 69 71 78 69 71 78 69 71 78 D 69 71 78 69 71 78 69 71 78 69 71 78 69 71 69 71 78 69 71 78 69 71 78 TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TMDS_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM VGA_50S * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD 69 70 77 69 70 77 69 70 77 69 70 77 69 71 78 69 71 78 69 71 78 69 71 78 TABLE_PHYSICAL_RULE_ITEM VGA_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT 20 MIL ? 69 70 77 69 70 77 69 70 77 69 70 77 69 71 78 69 71 78 69 71 78 69 71 78 TABLE_SPACING_RULE_ITEM TMDS * TABLE_SPACING_RULE_ITEM VGA * 20 MIL ? TABLE_SPACING_RULE_ITEM VGA_SYNC * 20 MIL ? C 69 70 77 69 70 77 69 70 77 69 70 77 69 70 77 69 70 77 69 70 77 69 70 77 69 70 77 69 70 77 69 70 77 69 70 77 69 70 77 69 70 77 69 70 77 69 70 77 69 70 77 69 70 77 69 70 77 69 70 77 69 70 77 69 70 77 69 70 77 69 70 77 69 71 78 69 71 78 69 71 78 69 71 78 69 71 78 69 71 78 69 71 78 69 71 78 C 69 71 78 69 71 78 69 71 78 69 71 78 69 71 78 69 71 78 69 71 78 69 71 78 69 71 78 69 71 78 69 71 78 69 71 78 69 71 78 69 71 78 69 71 78 69 71 78 G84M Net Properties ELECTRICAL_CONSTRAINT_SET B (CK505_DOT96) CK505_CLK27MSS CLK_SLOW_55S CLK_SLOW_55S CLK_SLOW CLK_SLOW GPU_CLK27M GPU_CLK27M_SS LVDS_L_CLK LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS_L_CLK_P LVDS_L_CLK_N LVDS_L_DATA_P LVDS_L_DATA_N NC_LVDS_L_DATAP NC_LVDS_L_DATAN LVDS_U_CLK_P LVDS_U_CLK_N LVDS_U_DATA_P LVDS_U_DATA_N NC_LVDS_U_DATAP NC_LVDS_U_DATAN TMDS_CLK TMDS_CLK TMDS_DATA TMDS_DATA TMDS_100D TMDS_100D TMDS_100D TMDS_100D TMDS TMDS TMDS TMDS TMDS_CLK_P TMDS_CLK_N TMDS_DATA_P TMDS_DATA_N VGA_R_TV_C VGA_G_TV_Y VGA_B_TV_COMP VGA_50S VGA_50S VGA_50S VGA_50S VGA_50S VGA_50S VGA_50S VGA_50S VGA_50S VGA VGA VGA VGA VGA VGA VGA VGA VGA GPU_TV_C_VGA_R GPU_TV_Y_VGA_G GPU_TV_COMP_VGA_B GPU_VGA_R GPU_VGA_G GPU_VGA_B GPU_TV_C GPU_TV_Y GPU_TV_COMP VGA_55S VGA_55S VGA_SYNC VGA_SYNC GPU_VGA_HSYNC GPU_VGA_VSYNC LVDS_L_DATA I127 I126 LVDS_U_CLK LVDS_U_DATA I128 I129 A NET_TYPE PHYSICAL SPACING VGA_SYNC VGA_SYNC 30 72 73 30 72 73 74 76 B 74 76 74 76 74 76 73 74 73 74 74 76 74 76 74 76 74 76 73 74 73 74 74 80 74 80 74 80 74 80 73 80 73 80 73 80 73 74 73 74 73 74 73 74 GPU (G84M) Constraints 73 74 73 74 SYNC_MASTER=M87_MLB 74 80 SYNC_DATE=10/02/2007 NOTICE OF PROPRIETARY PROPERTY 74 80 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC SCALE SHT NONE REV 051-7431 A.0.0 OF 90 92 A ALLOW ROUTE ON LAYER? LAYER MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP ELECTRICAL_CONSTRAINT_SET TABLE_PHYSICAL_RULE_ITEM SENSE_1TO1_55S * =1:1_DIFFPAIR =55_OHM_SE =55_OHM_SE =55_OHM_SE =1:1_DIFFPAIR =1:1_DIFFPAIR THERM_1TO1_55S * =1:1_DIFFPAIR =55_OHM_SE =55_OHM_SE =55_OHM_SE =1:1_DIFFPAIR =1:1_DIFFPAIR SPACING_RULE_SET LAYER TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_HEAD LINE-TO-LINE SPACING WEIGHT =2:1_SPACING ? M87 Specific Net Properties TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET NET_TYPE PHYSICAL SPACING (PCIE_EXCARD) (PCIE_EXCARD) PCIE_100D PCIE_100D PCIE PCIE PCIE_EXCARD_R2D_P PCIE_EXCARD_R2D_N (PCIE_MINI) (PCIE_MINI) PCIE_100D PCIE_100D PCIE PCIE PCIE_MINI_R2D_P PCIE_MINI_R2D_N ENET_100D ENET_100D ENET_100D ENET_100D ENET_MDI ENET_MDI ENETCONN ENETCONN ENET_MDI_R_P ENET_MDI_R_N ENETCONN_P ENETCONN_N FW_110D FW_110D FW_110D FW_110D FW_TP FW_TP FW_TP FW_TP FW_PORT0_TPA_FL_P FW_PORT0_TPA_FL_N FW_PORT0_TPB_FL_P FW_PORT0_TPB_FL_N (SATA_A_R2D) (SATA_A_R2D) SATA_100D SATA_100D SATA SATA SATA_A_R2D_UF_P SATA_A_R2D_UF_N (SATA_A_D2R) (SATA_A_D2R) SATA_100D SATA_100D SATA SATA SATA_A_D2R_UF_P SATA_A_D2R_UF_N (USB_EXTA) (USB_EXTA) (USB_EXTA) (USB_EXTA) (USB_EXTD) (USB_EXTD) (USB_CAMERA) (USB_CAMERA) USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB USB USB USB USB USB USB USB USB2_EXTA_MUXED_P USB2_EXTA_MUXED_N USB2_RT_P USB2_RT_N USB_WWAN_F_P USB_WWAN_F_N USB_CAMERA_F_P USB_CAMERA_F_N SENSE_DIFFPAIR SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE GFXIMVP6_VSEN_P GFXIMVP6_VSEN_N NBCOREISNS_P NBCOREISNS_N P1V8ISNS_P P1V8ISNS_N P1V25ISNS_P P1V25ISNS_N THERM_1TO1_55S THERM_1TO1_55S THERM_1TO1_55S THERM_1TO1_55S THERM_1TO1_55S THERM_1TO1_55S THERM_1TO1_55S THERM_1TO1_55S THERM_1TO1_55S THERM_1TO1_55S THERM_1TO1_55S THERM_1TO1_55S THERM THERM THERM THERM THERM THERM THERM THERM THERM THERM THERM THERM CPUTHMSNS_D2_P CPUTHMSNS_D2_N CPU_THERMD_P CPU_THERMD_N GPUTHMSNS_D_P GPUTHMSNS_D_N GPU_TDIODE_P GPU_TDIODE_N HSTHMSNS_D_P HSTHMSNS_D_N RSFSTHMSNS_D_P RSFSTHMSNS_D_N LVDS_100D LVDS_100D LVDS LVDS LVDS_L_CLK_CONN_F_P LVDS_L_CLK_CONN_F_N SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE SENSE SENSE SENSE P1V8ISNS_R_P P1V8ISNS_R_N P1V8GPUISNS_R_P P1V8GPUISNS_R_N TMDS_100D TMDS_100D TMDS_100D TMDS_100D TMDS_100D TMDS_100D TMDS TMDS TMDS TMDS TMDS TMDS TMDS_CLK_R_P TMDS_CLK_R_N TMDS_CLK_F_P TMDS_CLK_F_N TMDS_DATA_F_P TMDS_DATA_F_N (VGA_R_TV_Y) (VGA_G_TV_C) (VGA_B_TV_COMP) VGA_50S VGA_50S VGA_50S VGA VGA VGA VGA_R VGA_G VGA_B (VGA_SYNC) (VGA_SYNC) (VGA_SYNC) (VGA_SYNC) VGA_55S VGA_55S VGA_55S VGA_55S VGA_SYNC VGA_SYNC VGA_SYNC VGA_SYNC VGA_HSYNC_R VGA_VSYNC_R VGA_HSYNC VGA_VSYNC 34 34 34 34 TABLE_SPACING_RULE_ITEM SENSE * TABLE_SPACING_RULE_ITEM THERM D =2:1_SPACING ? LINE-TO-LINE SPACING WEIGHT 25 MILS ? * TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER TABLE_SPACING_RULE_ITEM ENETCONN * TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT 37 D 37 41 41 41 41 TABLE_SPACING_RULE_ITEM GND * =STANDARD ? PP1V8_MEM * =STANDARD ? TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM GND_P2MM * 0.20 MM 1000 PWR_P2MM * 0.20 MM 1000 TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET MEM_CLK GND * GND_P2MM MEM_CMD GND * GND_P2MM MEM_CTRL GND * GND_P2MM MEM_DATA GND * GND_P2MM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM SENSE_DIFFPAIR TABLE_SPACING_ASSIGNMENT_ITEM MEM_DQS GND * GND_P2MM MEM_CLK PP1V8_MEM * PWR_P2MM I120 TABLE_SPACING_ASSIGNMENT_ITEM I121 TABLE_SPACING_ASSIGNMENT_ITEM C MEM_CMD PP1V8_MEM * PWR_P2MM MEM_CTRL PP1V8_MEM * PWR_P2MM I122 I124 TABLE_SPACING_ASSIGNMENT_ITEM PP1V8_MEM * PWR_P2MM MEM_DQS PP1V8_MEM * PWR_P2MM SENSE_DIFFPAIR I123 TABLE_SPACING_ASSIGNMENT_ITEM MEM_DATA SENSE_DIFFPAIR THERM_DIFFPAIR I125 TABLE_SPACING_ASSIGNMENT_ITEM I127 THERM_DIFFPAIR I126 TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET TABLE_SPACING_ASSIGNMENT_ITEM CLINK_VREF GND * GND_P2MM CLK_FSB GND * CLK_MED GND * GND_P2MM GND * GND_P2MM DMI GND * GND_P2MM CPU_COMP GND * GND_P2MM CPU_GTLREF GND * GND_P2MM CPU_VCCSENSE GND * GND_P2MM GND_P2MM SATA GND * GND_P2MM THERM_DIFFPAIR TABLE_SPACING_ASSIGNMENT_ITEM THERM_DIFFPAIR TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM * THERM_DIFFPAIR TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM GND I129 GND_P2MM TABLE_SPACING_ASSIGNMENT_ITEM PCIE THERM_DIFFPAIR I130 TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM CLK_PCIE I128 TABLE_SPACING_ASSIGNMENT_HEAD 81 81 81 81 43 43 43 43 44 44 75 75 50 50 50 50 50 C 50 51 51 10 51 10 51 51 51 51 72 73 51 72 73 51 51 51 51 TABLE_SPACING_ASSIGNMENT_ITEM FSB_DSTB GND * GND_P2MM TABLE_SPACING_ASSIGNMENT_ITEM 76 76 TABLE_SPACING_ASSIGNMENT_HEAD TABLE_SPACING_ASSIGNMENT_ITEM USB GND * GND_P2MM CLK_PCIE SB_POWER * PWR_P2MM NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET ENET_MDI GND * GND_P2MM I136 TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM DMI SB_POWER * PWR_P2MM ENET_MDI ENET_POWER * SENSE_DIFFPAIR I135 TABLE_SPACING_ASSIGNMENT_ITEM I134 PWR_P2MM SENSE_DIFFPAIR I133 50 50 50 50 TABLE_SPACING_ASSIGNMENT_ITEM SATA SB_POWER * PWR_P2MM TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET CLK_MED FW_POWER * GND_P2MM TABLE_SPACING_ASSIGNMENT_ITEM USB SB_POWER * PWR_P2MM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_HEAD B NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET TABLE_SPACING_ASSIGNMENT_ITEM LVDS GND * GND_P2MM Memory Constraint Relaxations Allow 0.127 mm necks for >0.127 mm lines for GMCH fanout TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM MEM_70D BOTTOM 0.127 MM 6.35 MM Allow 0.1 mm necks for >0.1 mm lines between thru-hole SO-DIMM pins 80 80 B 80 80 80 80 80 80 80 80 80 80 80 TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM MEM_45S * OVERRIDE OVERRIDE MEM_70D MEM_85D 0.100 MM OVERRIDE OVERRIDE 2.54 MM OVERRIDE OVERRIDE ISL10 0.100 MM 2.54 MM ISL4,ISL10 0.100 MM 2.54 MM OVERRIDE PP1V8_MEM PP1V8_MEM GND ENET_POWER SB_POWER SB_POWER SB_POWER SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE FW_POWER OVERRIDE TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM Graphics ,SATA Constraint Relaxations I131 Alternate diffpair width/gap through BGA fanout areas (95-ohm diff) SENSE_DIFFPAIR I132 TABLE_PHYSICAL_ASSIGNMENT_HEAD NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET LVDS_100D BGA 100_DIFF_BGA TMDS_100D BGA 100_DIFF_BGA SATA_100D BGA 100_DIFF_BGA PP1V8_S3 PP1V8_S3 GND 31 32 38 50 62 91 31 32 38 50 62 91 PP3V3_S5 PP3V3_S0 PP1V5_S0 P1V8GPUISNS_P P1V8GPUISNS_N 24 25 26 27 28 46 48 56 58 60 65 76 52 53 58 59 65 82 13 16 19 21 23 24 25 26 27 28 29 30 31 32 42 46 47 48 50 51 11 12 22 26 27 34 63 50 50 Project Specific Constraints TABLE_PHYSICAL_ASSIGNMENT_ITEM A SYNC_MASTER=M87_MLB SYNC_DATE=08/28/2007 TABLE_PHYSICAL_ASSIGNMENT_ITEM NOTICE OF PROPRIETARY PROPERTY TABLE_PHYSICAL_ASSIGNMENT_ITEM THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER D APPLE INC SCALE SHT NONE REV 051-7431 A.0.0 OF 91 92 A M75 Board-Specific Spacing & Physical Constraints TABLE_BOARD_INFO BOARD LAYERS BOARD AREAS BOARD UNITS (MIL or MM) ALLEGRO VERSION TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM NO_TYPE,BGA MM 15.5.1 TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_PHYSICAL_RULE_ITEM DEFAULT * Y =55_OHM_SE =55_OHM_SE 30 MM MM MM DEFAULT * * Y =DEFAULT =DEFAULT 12.7 MM =DEFAULT =DEFAULT NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET * * BGA BGA_P1MM MEM_CLK * BGA BGA_P2MM CLK_FSB * BGA BGA_P2MM CLK_PCIE * BGA BGA_P2MM CLK_MED * BGA BGA_P2MM CLK_SLOW * BGA BGA_P2MM FSB_DSTB FSB_DSTB BGA BGA_P3MM TABLE_SPACING_ASSIGNMENT_ITEM ? 0.1 MM TABLE_PHYSICAL_RULE_ITEM STANDARD TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM STANDARD * =DEFAULT ? BGA_P1MM * =DEFAULT ? TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_PHYSICAL_RULE_HEAD D PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH 55_OHM_SE TOP,BOTTOM Y 0.100 MM 0.100 MM MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_SPACING_RULE_ITEM BGA_P2MM * D TABLE_SPACING_ASSIGNMENT_ITEM ? =DEFAULT TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_ITEM BGA_P3MM * =DEFAULT ? LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_ASSIGNMENT_ITEM TABLE_PHYSICAL_RULE_ITEM 55_OHM_SE ISL2,ISL11 Y 0.250 MM 0.076 MM 55_OHM_SE * Y 0.076 MM 0.076 MM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_PHYSICAL_RULE_ITEM =STANDARD =STANDARD =STANDARD TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH 50_OHM_SE TOP,BOTTOM Y 0.125 MM 0.125 MM MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP 1.5:1_SPACING * 0.15 MM ? 1.8:1_SPACING * 0.18 MM ? 2:1_SPACING * 0.2 MM ? 2.5:1_SPACING * 0.25 MM ? 3:1_SPACING * 0.3 MM ? 4:1_SPACING * 0.4 MM ? DIFFPAIR NECK GAP TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM 50_OHM_SE * Y 0.090 MM 0.090 MM PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH 46_OHM_SE TOP,BOTTOM Y 0.126 MM 0.126 MM =STANDARD =STANDARD =STANDARD TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM 46_OHM_SE * Y 0.100 MM 0.100 MM =STANDARD =STANDARD =STANDARD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 45_OHM_SE TOP,BOTTOM Y 0.150 MM 0.150 MM 45_OHM_SE * Y 0.105 MM 0.105 MM =STANDARD =STANDARD =STANDARD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 40_OHM_SE TOP,BOTTOM Y 0.185 MM 0.185 MM 40_OHM_SE * Y 0.131 MM 0.131 MM =STANDARD =STANDARD =STANDARD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 27P4_OHM_SE TOP,BOTTOM Y 0.335 MM 0.335 MM 27P4_OHM_SE * Y 0.240 MM 0.240 MM =STANDARD =STANDARD =STANDARD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 70_OHM_DIFF * N =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD TABLE_PHYSICAL_RULE_HEAD TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM C C TABLE_PHYSICAL_RULE_HEAD TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 1:1_DIFFPAIR * Y =STANDARD =STANDARD =STANDARD 0.1 MM 0.1 MM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM 70_OHM_DIFF ISL3,ISL4 Y 0.149 MM 0.149 MM 0.125 MM 0.125 MM 70_OHM_DIFF ISL9,ISL10 Y 0.149 MM 0.149 MM 0.125 MM 0.125 MM 70_OHM_DIFF ISL2,ISL11 Y 0.185 MM 0.185 MM 0.125 MM 0.125 MM 70_OHM_DIFF TOP,BOTTOM Y 0.185 MM 0.185 MM 0.125 MM 0.125 MM PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 80_OHM_DIFF * N =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD 80_OHM_DIFF ISL3,ISL4 Y 0.115 MM 0.115 MM 0.125 MM 0.125 MM 80_OHM_DIFF ISL9,ISL10 Y 0.115 MM 0.115 MM 0.125 MM 0.125 MM 80_OHM_DIFF ISL2,ISL11 Y 0.140 MM 0.140 MM 0.125 MM 0.125 MM 80_OHM_DIFF TOP,BOTTOM Y 0.140 MM 0.140 MM 0.125 MM 0.125 MM PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 85_OHM_DIFF * N =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD B B TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM 85_OHM_DIFF ISL3,ISL4 Y 0.101 MM 0.101 MM 0.125 MM 0.125 MM 85_OHM_DIFF ISL9,ISL10 Y 0.101 MM 0.101 MM 0.125 MM 0.125 MM 85_OHM_DIFF ISL2,ISL11 Y 0.125 MM 0.125 MM 0.125 MM 0.125 MM 85_OHM_DIFF TOP,BOTTOM Y 0.125 MM 0.125 MM 0.125 MM 0.125 MM PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 90_OHM_DIFF * N =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD 90_OHM_DIFF ISL3,ISL4 Y 0.102 MM 0.102 MM 0.220 MM 0.220 MM 90_OHM_DIFF ISL9,ISL10 Y 0.102 MM 0.102 MM 0.220 MM 0.220 MM 90_OHM_DIFF ISL2,ISL11 Y 0.130 MM 0.130 MM 0.220 MM 0.220 MM 90_OHM_DIFF TOP,BOTTOM Y 0.130 MM 0.130 MM 0.220 MM 0.220 MM PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD MAXIMUM NECK LENGTH TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 100_DIFF_BGA * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF 100_DIFF_BGA ISL3,ISL4 Y 0.075 MM 0.075 MM 0.125 MM 0.125 MM 100_DIFF_BGA ISL9,ISL10 Y 0.075 MM 0.075 MM 0.125 MM 0.125 MM TABLE_PHYSICAL_RULE_ITEM 100_OHM_DIFF * N =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM 100_OHM_DIFF ISL3,ISL4 Y 0.080 MM 0.200 MM 0.080 MM 0.200 MM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM 100_OHM_DIFF A ISL9,ISL10 Y 0.080 MM 0.200 MM 0.080 MM 0.200 MM PCB Rule Definitions TABLE_PHYSICAL_RULE_ITEM SYNC_MASTER=M87_MLB TABLE_PHYSICAL_RULE_ITEM 100_OHM_DIFF ISL2,ISL11 Y 0.099 MM 0.200 MM 0.099 MM 0.200 MM NOTE: 100_DIFF_BGA is 100-ohms differential impedance on outer layers and 95-ohms on inner layers 100_OHM_DIFF TOP,BOTTOM Y 0.099 MM 0.200 MM 0.099 MM 0.200 MM THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSSESSOR AGREES TO THE FOLLOWING TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 110_OHM_DIFF * N =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD SYNC_DATE=10/03/2007 NOTICE OF PROPRIETARY PROPERTY TABLE_PHYSICAL_RULE_ITEM I TO MAINTAIN THE DOCUMENT IN CONFIDENCE TABLE_PHYSICAL_RULE_ITEM II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART TABLE_PHYSICAL_RULE_ITEM 110_OHM_DIFF ISL3,ISL4 Y 0.077 MM 0.077 MM 0.330 MM 0.330 MM 110_OHM_DIFF ISL9,ISL10 Y 0.077 MM 0.077 MM 0.330 MM 0.330 MM 110_OHM_DIFF ISL2,ISL11 Y 0.089 MM 0.089 MM 0.330 MM 0.330 MM SIZE TABLE_PHYSICAL_RULE_ITEM APPLE INC TABLE_PHYSICAL_RULE_ITEM 110_OHM_DIFF TOP,BOTTOM Y 0.089 MM 0.089 MM 0.330 MM DRAWING NUMBER D TABLE_PHYSICAL_RULE_ITEM 0.330 MM SCALE SHT NONE REV 051-7431 A.0.0 OF 92 92 A ... TABLE_BOMGROUP_HEAD BOM GROUP BOM OPTIONS M88_ COMMON COMMON,ALTERNATE ,M88_ COMMON1 ,M88_ COMMON2 ,M88_ DEBUG ,M88_ PROGPARTS M88_ COMMON1 BKLT_5V_PWR,ISL9504B,ONEWIRE_PU,GPUVID_1P23V M88_ COMMON2 P1V8S3_1V8,SMS_MOT_DIS,YUKON_ULTRA,VGA_TERM_CONN... PCBA,2.6GHZ,512VRAM-SAM ,M88 M88_COMMON,CPU_2_6GHZ,FB_512_SAMSUNG,EEE_Z3L 630-9225 PCBA,2.5GHZ,512VRAM-HY ,M88 M88_COMMON,CPU_2_5GHZ,FB_512_HYNIX,EEE_ZVW 630-9228 PCBA,2.5GHZ,512VRAM-SAM ,M88 M88_COMMON,CPU_2_5GHZ,FB_512_SAMSUNG,EEE_ZVX... SIZE DRAWING NUMBER D APPLE INC SCALE SHT NONE REV 051-7431 A.0.0 OF 92 A BOM Variants TABLE_BOMGROUP_HEAD BOM NUMBER BOM NAME BOM OPTIONS 630-9092 PCBA,2.6GHZ,512VRAM-HY ,M88 M88_COMMON,CPU_2_6GHZ,FB_512_HYNIX,EEE_Z3K