A B C D E 1 Compal Confidential 2 NAV70 Schematics Document Intel Pineview Processor with Tigerpoint + DDRII 2010-04-29 3 l.c om REV: 2.0 Title Date: A B C D SCHEMATICS in THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Document Number MB A5651 xa 2007/8/18 Deciphered Date Rev D 401793 Friday, May 21, 2010 he 2006/08/18 f@ Compal Electronics, Inc Compal Secret Data Security Classification Issued Date ho tm E Sheet of 32 A B C D E Clock Generator CK505 page Compal Confidential Model Name : NAV70 File Name : LA-5651P CRT Conn page 10 1 ZZZ RGB DA60000E420 LVDS LCD Conn DDRII-SO-DIMM page 1.8V DDRII 667 22x22mm page Thermal Sensor Memory BUS(DDRII) Pineview FCBGA 559 PCB page 4,5,6 EMC1402 page DMI X2 mode GEN1 USB HDA Tigerpoint PCI-Express USB Port X2 PCBGA360 BlueTooth 17x17mm page 15 SATA page 11,12,13,14 MINI Card x1 3G page 15 To I/O Board WLAN page 20 page 20 CMOS CAM To I/O Board 10/100 Ethernet page HDD AR8132L 3G page 16 page 20 page 15 LPC BUS USB Port x1 To I/O Board Conn Transfermer Power ON/OFF ALC272 RJ45 DC/DC Interface page 20 Conn to I/O Board Aralia Codec To I/O board Card Reader ENE6252 page 20 page 25 I/O Board page 18 ENE KBC KB926page 3VALW/5VALW page 26 DC IN page 23 BATT IN 0.89VP/1.5VP 0.9VSP/2.5VSP CHARGER 1.8V/VCCP page 20 SPI 17 AMP & INT Speaker page 28 page 24 Int.KBD page 25 SPI ROM page 19 HeadPhone & MIC Jack SD/MMC/MS CONN I/O Board page19 page 27 page 17 Touch Pad INT MIC CPU_CORE page 29 2006/08/18 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2007/8/18 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C D SCHEMATICS MB A5651 Document Number Rev 401793 Sheet Friday, May 21, 2010 E D of 32 A B C D E 1 Voltage Rails External PCI Devices DEVICE Power Plane Description S1 S3 S5 VIN Adapter power supply (19V) N/A N/A N/A B+ AC or battery power rail for power circuit N/A N/A N/A +CPU_CORE Core voltage for CPU ON OFF OFF OFF +0.9VS 0.9V switched power rail for DDR terminator ON OFF +VCCP VCCP switched power rail ON OFF OFF +1.5VS 1.5V switched power rail ON OFF OFF +1.8V 1.8V power rail for DDR ON ON OFF +0.89V Graphic core power rail ON OFF OFF +3VALW 3.3V always on power rail ON ON ON* +3VS 3.3V switched power rail ON OFF OFF +5VALW 5V always on power rail ON ON ON* +5VS 5V switched power rail ON OFF OFF +VSB VSB always on power rail ON ON ON* +RTCVCC RTC power ON ON ON SIGNAL SLP_S3# SLP_S4# SLP_S5# REQ/GNT # PIRQ No PCI Device EC SM Bus1 address Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF STATE IDSEL # +VALW +V +VS Full ON HIGH HIGH HIGH ON ON ON ON S1(Power On Suspend) EC SM Bus2 address Device Address Device Address Smart Battery 0001 011X b EMC1402 100_1100 Clock HIGH HIGH HIGH ON ON ON LOW S3 (Suspend to RAM) LOW HIGH HIGH ON ON OFF OFF S4 (Suspend to Disk) LOW LOW HIGH ON OFF OFF OFF S5 (Soft OFF) LOW LOW LOW ON OFF OFF OFF ICH7M SM Bus address BOARD ID Table(Page 17) VCC Ra 3.3V 100K ID BRD ID NAV60 R01 (EVT) R02 (DVT) R03 (PVT) R10A (MP) R01 (EVT) R02 (DVT) R03 (PVT) R10A (MP) Vab-Min Vab-Typ Vab-Max 8.2K 18K 33K 56K 100K 200K NC 0V 0.216V 0.436V 0.712V 1.036V 1.453V 1.935V 2.500V 0V 0.250V 0.503V 0.819V 1.185V 1.650V 2.200V 3.3V 0V 0.289V 0.538V 0.875V 1.264V 1.759V 2.341V 3.3V Address Clock Generator (SLG8SP556VTR) 1101 001Xb DDR DIMMA 1010 000Xb l.c om NAV50 Rb Device Title Date: A B C D SCHEMATICS in THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Document Number MB A5651 xa 2007/8/18 Deciphered Date Rev D 401793 Friday, May 21, 2010 he 2006/08/18 f@ Compal Electronics, Inc Compal Secret Data Security Classification Issued Date ho tm E Sheet of 32 (7) DDR_A_DQS#[0 7] PINEVIEW_M (7) DDR_A_D[0 63] PINEVIEW_M U71B U71A REV = 1.1 (7) DDR_A_DM[0 7] REV = 1.1 F3 F2 H4 G3 DMI_RXP_0 DMI_RXN_0 DMI_RXP_1 DMI_RXN_1 N7 N6 EXP_CLKINN EXP_CLKINP DMI_TXP_0 DMI_TXN_0 DMI_TXP_1 DMI_TXN_1 G2 G1 H3 J2 DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 (7) DDR_A_DQS[0 7] DMI_TX0 (13) DMI_TX#0 (13) DMI_TX1 (13) DMI_TX#1 (13) (7) DDR_A_MA[0 14] DMI DMI_RX0_R DMI_RX#0_R DMI_RX1_R DMI_RX#1_R D (8) CLK_CPU_EXP# (8) CLK_CPU_EXP R10 R9 N10 N9 EXP_RCOMPO EXP_ICOMPI EXP_RBIAS L10 L9 L8 RSVD_TP RSVD_TP N11 P11 EXP_TCLKINN EXP_TCLKINP RSVD RSVD K2 J1 M4 L3 RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD R162 R203 49.9_0402_1% 750_0402_1% T38 T39 (5) (5) (13) DMI_RX#0 C435 C436 DMI_RX0_R 0.1U_0402_10V7K DMI_RX#0_R 0.1U_0402_10V7K DMI_RX1_R 0.1U_0402_10V7K C (13) (13) DMI_RX1 DMI_RX#1 C437 C438 (7) DDR_A_WE# (7) DDR_A_CAS# (7) DDR_A_RAS# K3 L2 M2 N2 (7) DDR_A_BS0 (7) DDR_A_BS1 (7) DDR_A_BS2 XDP_PREQ# XDP_PRDY# XDP_BPM#3 XDP_BPM#2 XDP_BPM#3 XDP_BPM#2 (5) (5) XDP_BPM#1 XDP_BPM#0 XDP_BPM#1 XDP_BPM#0 R354 @ R347 @ CPU_ITP CPU_ITP# 1K_0402_5% 1K_0402_5% PLTRST# R348 @ 1K_0402_1% (8) (8) +VCCP (5,13,15,17,20) PLTRST# (5) (5) (5) (5) Close to CPU XDP_PREQ# XDP_PRDY# (5) (5) (5,13) H_PWRGD (13) SLPIOVR# DMI_RX#1_R 0.1U_0402_10V7K DDR_A_WE# DDR_A_CAS# DDR_A_RAS# AK22 AJ22 AK21 DDR_A_WE# DDR_A_CAS# DDR_A_RAS# DDR_A_BS0 DDR_A_BS1 DDR_A_BS2 AJ20 AH20 AK11 DDR_A_BS_0 DDR_A_BS_1 DDR_A_BS_2 DDR_CS#0 DDR_CS#1 AH22 AK25 AJ21 AJ25 DDR_A_CS#_0 DDR_A_CS#_1 DDR_A_CS#_2 DDR_A_CS#_3 DDR_CKE0 DDR_CKE1 AH10 AH9 AK10 AJ8 DDR_A_CKE_0 DDR_A_CKE_1 DDR_A_CKE_2 DDR_A_CKE_3 M_ODT0 M_ODT1 AK24 AH26 AH24 AK27 DDR_A_ODT_0 DDR_A_ODT_1 DDR_A_ODT_2 DDR_A_ODT_3 Must be placed within 500 mils from Pineview-M pins (7) DDR_CS#0 (7) DDR_CS#1 JP16 DMI_RX0 DDR_A_MA_0 DDR_A_MA_1 DDR_A_MA_2 DDR_A_MA_3 DDR_A_MA_4 DDR_A_MA_5 DDR_A_MA_6 DDR_A_MA_7 DDR_A_MA_8 DDR_A_MA_9 DDR_A_MA_10 DDR_A_MA_11 DDR_A_MA_12 DDR_A_MA_13 DDR_A_MA_14 XDP_TDO XDP_TRST# XDP_TDI XDP_TMS (5) XDP_TCK XDP_TDO XDP_TRST# XDP_TDI XDP_TMS XDP_TCK 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 CONN@ 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 G1 G2 (7) DDR_CKE0 (7) DDR_CKE1 (7) M_ODT0 (7) M_ODT1 (7) (7) (7) (7) M_CLK_DDR0 M_CLK_DDR#0 M_CLK_DDR1 M_CLK_DDR#1 ACES_87151-24051 M_CLK_DDR0 M_CLK_DDR#0 M_CLK_DDR1 M_CLK_DDR#1 DDR_A_CK_0 DDR_A_CK_0# DDR_A_CK_1 DDR_A_CK_1# AC15 AD15 AF13 AG13 DDR_A_CK_3 DDR_A_CK_3# DDR_A_CK_4 DDR_A_CK_4# AD17 AC17 AB15 AB17 RSVD RSVD RSVD RSVD AB4 AK8 RSVD RSVD R369 10K_0402_5% +VCCP R341 51 +-1% 0402 XDP_TMS R342 51 +-1% 0402 XDP_TDO R343 51 +-1% 0402 XDP_PREQ# R344 51 +-1% 0402 +1.8V +1.8V XDP_TDI R370 10K_0402_5% @ T40 AB11 AB13 T41 R50 1K_0402_1% B +5VS AG15 AF15 AD13 AC13 +1.8V XDP Reserve FAN1 Conn XDP_TRST# R345 51 +-1% 0402 XDP_TCK R346 51 +-1% 0402 R142 R243 R242 80.6_0402_1% 80.6_0402_1% 1K_0402_1% RSVD_TP RSVD_TP AL28 AK28 AJ26 DDR_VREF DDR_RPD DDR_RPU AK29 RSVD Modify follow KAV60 schematic 06/12 DDR_A Modify D38 D39 D40 Pin define 2 C314 D40 R256 10K_0402_5% 40mil +VCC_FAN1 (17) FAN_SPEED1 C311 100P_0402_50V8J JP12 3 G1 G2 ACES_85204-03001 CONN@ C1150 1000P_0402_50V7K A 4.7U_0603_6.3V6K C1151 +3VS 0.01U_0402_16V7K PJDLC05C_SOT23-3 XDP_TRST# XDP_TDI PJDLC05C_SOT23-3 4.7U_0603_6.3V6K C313 D39 1 APL5607KI-TRG_SO8 D38 EN_FAN1 GND GND GND GND (17) +VCC_FAN1 R47 330_0402_5% EN VIN VOUT VSET XDP_PREQ# XDP_TDO U12 08/13 XDP_TMS XDP_TCK D19@ DAN217_SC59 2 PJDLC05C_SOT23-3 2.2U_0603_10V6K +5VS C312 AD3 AD2 AD4 DDR_A_DQS0 DDR_A_DQS#0 DDR_A_DM0 DDR_A_DQ_0 DDR_A_DQ_1 DDR_A_DQ_2 DDR_A_DQ_3 DDR_A_DQ_4 DDR_A_DQ_5 DDR_A_DQ_6 DDR_A_DQ_7 AC4 AC1 AF4 AG2 AB2 AB3 AE2 AE3 DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_DQS_1 DDR_A_DQS#_1 DDR_A_DM_1 AB8 AD7 AA9 DDR_A_DQS1 DDR_A_DQS#1 DDR_A_DM1 DDR_A_DQ_8 DDR_A_DQ_9 DDR_A_DQ_10 DDR_A_DQ_11 DDR_A_DQ_12 DDR_A_DQ_13 DDR_A_DQ_14 DDR_A_DQ_15 AB6 AB7 AE5 AG5 AA5 AB5 AB9 AD6 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_DQS_2 DDR_A_DQS#_2 DDR_A_DM_2 AD8 AD10 AE8 DDR_A_DQS2 DDR_A_DQS#2 DDR_A_DM2 DDR_A_DQ_16 DDR_A_DQ_17 DDR_A_DQ_18 DDR_A_DQ_19 DDR_A_DQ_20 DDR_A_DQ_21 DDR_A_DQ_22 DDR_A_DQ_23 AG8 AG7 AF10 AG11 AF7 AF8 AD11 AE10 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_DQS_3 DDR_A_DQS#_3 DDR_A_DM_3 AK5 AK3 AJ3 DDR_A_DQS3 DDR_A_DQS#3 DDR_A_DM3 DDR_A_DQ_24 DDR_A_DQ_25 DDR_A_DQ_26 DDR_A_DQ_27 DDR_A_DQ_28 DDR_A_DQ_29 DDR_A_DQ_30 DDR_A_DQ_31 AH1 AJ2 AK6 AJ7 AF3 AH2 AL5 AJ6 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_DQS_4 DDR_A_DQS#_4 DDR_A_DM_4 AG22 AG21 AD19 DDR_A_DQS4 DDR_A_DQS#4 DDR_A_DM4 DDR_A_DQ_32 DDR_A_DQ_33 DDR_A_DQ_34 DDR_A_DQ_35 DDR_A_DQ_36 DDR_A_DQ_37 DDR_A_DQ_38 DDR_A_DQ_39 AE19 AG19 AF22 AD22 AG17 AF19 AE21 AD21 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_DQS_5 DDR_A_DQS#_5 DDR_A_DM_5 AE26 AG27 AJ27 DDR_A_DQS5 DDR_A_DQS#5 DDR_A_DM5 DDR_A_DQ_40 DDR_A_DQ_41 DDR_A_DQ_42 DDR_A_DQ_43 DDR_A_DQ_44 DDR_A_DQ_45 DDR_A_DQ_46 DDR_A_DQ_47 AE24 AG25 AD25 AD24 AC22 AG24 AD27 AE27 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_DQS_6 DDR_A_DQS#_6 DDR_A_DM_6 AE30 AF29 AF30 DDR_A_DQS6 DDR_A_DQS#6 DDR_A_DM6 DDR_A_DQ_48 DDR_A_DQ_49 DDR_A_DQ_50 DDR_A_DQ_51 DDR_A_DQ_52 DDR_A_DQ_53 DDR_A_DQ_54 DDR_A_DQ_55 AG31 AG30 AD30 AD29 AJ30 AJ29 AE29 AD28 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_DQS_7 DDR_A_DQS#_7 DDR_A_DM_7 AB27 AA27 AB26 DDR_A_DQS7 DDR_A_DQS#7 DDR_A_DM7 DDR_A_DQ_56 DDR_A_DQ_57 DDR_A_DQ_58 DDR_A_DQ_59 DDR_A_DQ_60 DDR_A_DQ_61 DDR_A_DQ_62 DDR_A_DQ_63 AA24 AB25 W24 W22 AB24 AB23 AA23 W27 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63 C B A OF Add 2009-6-17 2006/08/18 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2007/8/18 Deciphered Date Title Date: D PINEVIEW-M_FCBGA8559 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC DDR_A_DQS_0 DDR_A_DQS#_0 DDR_A_DM_0 OF PINEVIEW-M_FCBGA8559 (13) AH19 AJ18 AK18 AK16 AJ14 AH14 AK14 AJ12 AH13 AK12 AK20 AH12 AJ11 AJ24 AJ10 SCHEMATICS MB A5651 Rev D 401793 Sheet Friday, May 21, 2010 of 32 Add 470PF on H_SMI# for known issue 07/08 PINEVIEW_M U71C CRT_HSYNC CRT_VSYNC M30 M29 CRT_RED CRT_GREEN CRT_BLUE CRT_IRTN N31 P30 P29 N30 CRT_DDC_DATA CRT_DDC_CLK L31 L30 DAC_IREF P28 Y30 Y29 AA30 AA31 REFCLKINP REFCLKINN REFSSCLKINP REFSSCLKINN K29 J30 L5 AA3 W8 W9 HPL_CLKINN HPL_CLKINP C T22 T23 T24 T25 AA21 W21 T21 V21 RSVD_TP RSVD_TP RSVD_TP RSVD_TP (9) (9) (9) (9) (9) (9) (9) (9) PM_EXTTS#1 PM_EXTTS#0 H_PWROK PLTRST# LVDS_ACLK# LVDS_ACLK LVDS_A0# LVDS_A0 LVDS_A1# LVDS_A1 LVDS_A2# LVDS_A2 R151 2.37K_0402_1% CPU_DREFCLK (8) CPU_DREFCLK# (8) CPU_SSCDREFCLK (8) CPU_SSCDREFCLK# (8) Add INVT_PWM (9) 0_0402_5% R200 GMCH_ENBKL (17) GMCH_ENBKL (9,17) INVT_PWM 0_0402_5% R213 @ 05/11 LVDS_SCL (9) LVDS_SDA (9) GMCH_ENVDD PM_DPRSLPVR (13) U25 U26 R23 R24 N26 N27 R26 R27 LA_CLKN LA_CLKP LA_DATAN_0 LA_DATAP_0 LA_DATAN_1 LA_DATAP_1 LA_DATAN_2 LA_DATAP_2 R22 J28 N22 N23 L27 L26 L23 K25 K23 K24 H26 LIBG LVBG LVREFH LVREFL LBKLT_EN LBKLT_CTL LCTLA_CLK LCTLB_DATA LDDC_CLK LDDC_DATA LVDD_EN 470P_0402_50V7K REV = 1.1 GMCH_CRT_R (10) GMCH_CRT_G (10) GMCH_CRT_B (10) CPU_DREFCLK CPU_DREFCLK# CPU_SSCDREFCLK CPU_SSCDREFCLK# PINEVIEW_M U71D GMCH_CRT_DATA (10) GMCH_CRT_CLK (10) R201 665_0402_1% PM_EXTTS#0 (7) SMI# A20M# FERR# LINT0 LINT1 IGNNE# STPCLK# E7 H7 H6 F10 F11 E5 F8 H_SMI# H_A20M# H_FERR# H_INTR H_NMI H_IGNNE# H_STPCLK# DPRSTP# DPSLP# INIT# PRDY# PREQ# G6 G10 G8 E11 F15 H_DPRSTP# H_DPSLP# H_INIT# XDP_PRDY# XDP_PREQ# THERMTRIP# E13 H_THERMTRIP# PROCHOT# CPUPWRGOOD C18 W1 H_PROCHOT# H_PWRGD GTLREF VSS A13 H27 H_GTLREF RSVD RSVD L6 E17 BCLKN BCLKP H10 J10 BSEL_0 BSEL_1 BSEL_2 K5 H5 K6 CPU_BSEL0 CPU_BSEL1 CPU_BSEL2 VID_0 VID_1 VID_2 VID_3 VID_4 VID_5 VID_6 H30 H29 H28 G30 G29 F29 E29 CPU_VID0 CPU_VID1 CPU_VID2 CPU_VID3 CPU_VID4 CPU_VID5 CPU_VID6 RSVD RSVD RSVD RSVD L7 D20 H13 D18 RSVD_TP RSVD_TP EXTBGREF K9 D19 K7 H_DPRSTP# (13) H_DPSLP# (13) H_INIT# (12) XDP_PRDY# (4) XDP_PREQ# (4) H_THERMTRIP# (12) H_PWRGD (4,13) CLK_CPU_HPLCLK# (8) CLK_CPU_HPLCLK (8) Del R323 05/11 C Modify 08/04 RSVD_TP RSVD_TP RSVD_TP RSVD_TP @ 0_0402_5% R306 0_0402_5% H_PWROK (4) (4) (4) (4) R305 VGATE (8,13,17,29) G11 E15 G13 F13 XDP_BPM#0 XDP_BPM#1 XDP_BPM#2 XDP_BPM#3 T48 T49 T50 T51 PCH_POK (13,17) (4) (4) (4) (4) (4) XDP_TDI XDP_TDO XDP_TCK XDP_TMS XDP_TRST# T55 XDP_TDI XDP_TDO XDP_TCK XDP_TMS XDP_TRST# H_THERMDA H_THERMDC B Place closed to chipset OF GMCH_CRT_R PINEVIEW-M_FCBGA8559 GMCH_CRT_G GMCH_CRT_B GMCH_ENBKL R307 150_0402_1% R308 150_0402_1% R309 150_0402_1% R34 100K_0402_5% T58 XDP_TCK T59 XDP_TDI T60 XDP_TDO T61 XDP_TMS T62 XDP_TRST# T63 H_PWRGD BPM_1_0# BPM_1_1# BPM_1_2# BPM_1_3# B18 B20 C20 B21 BPM_2_0#/RSVD BPM_2_1#/RSVD BPM_2_2#/RSVD BPM_2_3#/RSVD G5 D14 D13 B14 C14 C16 RSVD TDI TDO TCK TMS TRST# D30 E30 THRMDA_1 THRMDC_1 C30 D31 CLK_CPU_BCLK# CLK_CPU_BCLK CLK_CPU_BCLK# (8) CLK_CPU_BCLK (8) CPU_BSEL0 (8) CPU_BSEL1 (8) CPU_BSEL2 (8) CPU_VID0 CPU_VID1 CPU_VID2 CPU_VID3 CPU_VID4 CPU_VID5 CPU_VID6 (29) (29) (29) (29) (29) (29) (29) T26 T27 H_EXTBGREF B THRMDA_2/RSVD THRMDC_2/RSVD OF PINEVIEW-M_FCBGA8559 +VCCP +VCCP H_THERMDA, H_THERMDC routing together Trace width / Spacing = 10 / 10 mil THERM# EC_SMB_DA2 ALERT# GND EC_SMB_DA2 (17) R58 10K_0402_5% 2006/08/18 Issued Date Deciphered Date 2007/8/18 Date: @ C940 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC EMC1402-1-ACZL-TR MSOP 8P SENSOR Address:100_1100 1U_0603_10V6K Compal Electronics, Inc Compal Secret Data Security Classification placed within 0.5" of processor pin placed within 0.5" of processor pin +3VS l.c om SMDATA DN R156 3.3K_0402_1% tm DP EC_SMB_CK2 (17) ho EC_SMB_CK2 2 f@ H_THERMDA H_THERMDC 2200P_0402_50V7K SMCLK Close to Processor pin R155 2K_0402_1% SCHEMATICS Document Number in VDD PM_EXTTS#0 Close to Processor pin MB A5651 Rev xa @ C939 U2 H_PROCHOT# 1U_0603_10V6K C80 D 401793 Friday, May 21, 2010 he H_GTLREF R202 68_0402_5% R143 10K_0402_5% C79 H_EXTBGREF CPU THERMAL SENSOR 0.1U_0402_16V4Z A R244 976_0402_1% R144 1K_0402_1% +VCCP +3VS +3VS D H_SMI# (12) H_A20M# (12) H_FERR# (12) H_INTR (12) H_NMI (12) H_IGNNE# (12) H_STPCLK# (12) PLTRST# (4,13,15,17,20) CLK_CPU_HPLCLK# CLK_CPU_HPLCLK MISC AA7 AA6 R5 R6 GMCH_CRT_R GMCH_CRT_G GMCH_CRT_B (10) (10) RSVD PM_EXTTS#_1/DPRSLPVR PM_EXTTS#_0 PWROK RSTIN# T18 T19 T20 T21 GMCH_CRT_HSYNC GMCH_CRT_VSYNC ICH R1378 REV = 1.1 CPU L11 D C1171 XDP_RSVD_00 XDP_RSVD_01 XDP_RSVD_02 XDP_RSVD_03 XDP_RSVD_04 XDP_RSVD_05 XDP_RSVD_06 XDP_RSVD_07 XDP_RSVD_08 XDP_RSVD_09 XDP_RSVD_10 XDP_RSVD_11 XDP_RSVD_12 XDP_RSVD_13 XDP_RSVD_14 XDP_RSVD_15 XDP_RSVD_16 XDP_RSVD_17 LVDS T37 T2 T12 T3 T4 T13 T5 T6 T7 T14 VGA T8 1K_0402_5% T15 T9 T16 T10 T17 T11 T28 D12 A7 D6 C5 C7 C6 D8 B7 A9 D9 C8 B8 C10 D10 B11 B10 B12 C11 Sheet of 32 A U71F +CPU_CORE U71E GFX supply current: 1.38A Sustained GFX supply current: 1.05A PINEVIEW_M +0.89V VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCCGFX VCCGFX VCCGFX VCCGFX VCCGFX VCCGFX VCCGFX VCCGFX VCCGFX VCCGFX VCCGFX CPU T13 T14 T16 T18 T19 V13 V19 W14 W16 W18 W19 GFX/MCH REV = 1.1 D DDR supply current 2.27A +1.8V 2.2U_0603_10V6K2.2U_0603_10V6K 2 C188 C187 AK13 AK19 AK9 AL11 AL16 AL21 AL25 C186 C85 1 1 2.2U_0603_10V6K 2.2U_0603_10V6K +1.8V VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM AK7 AL7 +VCCP VCCCK_DDR VCCCK_DDR C428 1U_0402_6.3V6K C429 2 C430 22UF 6.3V M X5R 0805 C431 C1154 C1152 1U_0402_6.3V6K 2 22UF 6.3V M X5R 0805 C243 1U_0603_10V6K 4.7U_0603_6.3V6K C236 AA10 AA11 Display PLL SFR and CRT DAC supply current: 0.154A AA19 + C278 C1160 0.1U_0402_10V6K 1 2 Close U71.D4 +RING_EAST 0_0603_5% VCCSENSE VSSSENSE +RING_WEST 0_0603_5% D4 VCCP VCCP B4 B3 2 C241 1U_0603_10V6K +VCC_DMI 1 1U_0603_10V6K C68 C237 1U_0603_10V6K 2 VCCSENSE (29) VSSSENSE (29) +1.5VS +VCCPProcessor VCCP C242 1U_0603_10V6K R21 C29 B29 Y2 C1161 0.1U_0402_10V6K R20 R28 0_0805_5% VCCSENSE VSSSENSE VCCA +VCCP C64 1U_0603_10V6K VCCACK_DDR VCCACK_DDR 330U 2.5V Y PLACE IN CAVITY POWER C55 VCCA_DDR VCCA_DDR VCCA_DDR VCCA_DDR VCCA_DDR VCCA_DDR VCCA_DDR VCCA_DDR VCCA_DDR VCCA_DDR VCCA_DDR C275 330U 2.5V Y 22UF 6.3V M X5R 0805 DDR U10 U5 U6 U7 U8 U9 V2 V3 V4 W10 W11 C1153 + 1U_0402_6.3V6K x 330uF(9mohm/2) DDR analog supply current: 1.32A 22UF 6.3V M X5R 0805 C267 22UF 6.3V M X5R 0805 C +CPU_CORE 1U_0402_6.3V6K A23 A25 A27 B23 B24 B25 B26 B27 C24 C26 D23 D24 D26 D28 E22 E24 E27 F21 F22 F25 G19 G21 G24 H17 H19 H22 H24 J17 J19 J21 J22 K15 K17 K21 L14 L16 L19 L21 N14 N16 N19 N21 A11 A16 A19 A29 A3 A30 A4 AA13 AA14 AA16 AA18 AA2 AA22 AA25 AA26 AA29 AA8 AB19 AB21 AB28 AB29 AB30 AC10 AC11 AC19 AC2 AC21 AC28 AC30 AD26 AD5 AE1 AE11 AE13 AE15 AE17 AE22 AE31 AF11 AF17 AF21 AF24 AF28 AG10 AG3 AH18 AH23 AH28 AH4 AH6 AH8 AJ1 AJ16 AJ31 AK1 AK2 AK23 AK30 AK31 AL13 AL19 AL2 AL23 AL29 AL3 AL30 AL9 B13 B16 B19 B22 B30 B31 B5 B9 C1 C12 C21 C22 C25 C31 D22 E1 E10 E19 E21 E25 E8 F17 F19 Core analog supply current: 0.08A C391 0.01U_0402_16V7K VCCD_AB_DPL B AC31 +VCC_CRT_DAC T30 VCCACRTDAC +3VS GIO supply current: 0.006A T31 +RING_EAST +RING_WEST J31 C3 B2 C2 A21 +VCCP +1.8VS VCCSFR_AB_DPL VCC_GIO VCCRING_EAST VCCRING_WEST VCCRING_WEST VCCRING_WEST VCC_LGI VCCALVDS VCCDLVDS V30 W31 VCCA_DMI VCCA_DMI VCCA_DMI T1 T2 T3 +VCC_ALVD +VCC_DLVD R25 +VCC_CRT_DAC MBK1608601YZF_2P LVDS supply current: 0.06A LVDS 0_0603_5% VCCD_HMPLL DMI C192 1U_0603_10V6K R321 C189 1U_0603_10V6K V11 EXP\CRT\PLL +1.8VS RSVD VCCSFR_DMIHMPLL VCCP DAC, GIO, LVDS, & LGIO, DPLL, HMPLL supply current: 0.33A OF PINEVIEW-M_FCBGA8559 P2 AA1 +VCC_DMI DMI analog supply current: 0.48A +DMI_HMPLL +DMI_HMPLL R18 0_0603_5% T56 SFR & DMIHMPLL supply current: 0.104A E2 R26 100NH +-5% LL1608-FSLR10J +VCCP C1162 C239 1U_0603_10V6K 2 C69 1U_0603_10V6K H1.25 22UF 6.3V M X5R 0805 REV = 1.1 VSS VSS VSS RSVD_NCTF RSVD_NCTF RSVD_NCTF RSVD_NCTF VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS RSVD_NCTF VSS RSVD_NCTF RSVD_NCTF RSVD_NCTF VSS RSVD_NCTF RSVD_NCTF VSS VSS RSVD_NCTF VSS RSVD_NCTF RSVD_NCTF RSVD_NCTF VSS VSS VSS VSS VSS RSVD_NCTF RSVD_NCTF VSS VSS RSVD_NCTF VSS VSS VSS VSS RSVD_NCTF VSS RSVD_NCTF VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS F24 F28 F4 G15 G17 G22 G27 G31 H11 H15 H2 H21 H25 H8 J11 J13 J15 J4 K11 K13 K19 K26 K27 K28 K30 K4 K8 L1 L13 L18 L22 L24 L25 L29 M28 M3 N1 N13 N18 N24 N25 N28 N4 N5 N8 P13 P14 P16 P18 P19 P21 P3 P4 R25 R7 R8 T11 U22 U23 U24 U27 V14 V16 V18 V28 V29 W13 W2 W23 W25 W26 W28 W30 W4 W5 W6 W7 Y28 Y3 Y4 VSS T29 D C B OF PINEVIEW-M_FCBGA8559 +VCC_ALVD C56 0.1U_0402_10V6K +0.89V PINEVIEW_M GND C1155 1U_0603_10V6K Follow Intel check list change to 22uF 06/06 Modify to 2.2U 2 C77 C78 1 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K C75 1U_0402_6.3V6K C76 1U_0402_6.3V6K C71 1 1U_0402_6.3V6K C70 C81 2.2U_0603_10V6K C74 A R27 0_0603_5% +VCC_DLVD +CPU_CORE VCCSENSE VSSSENSE Close Chipset pin 05/11 R32 A C235 1U_0603_10V6K 100_0402_1% R31 100_0402_1% 2006/08/18 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2007/8/18 Deciphered Date Title SCHEMATICS THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: MB A5651 Rev D 401793 Sheet Friday, May 21, 2010 of 32 (4) DDR_A_DQS#[0 7] +1.8V (4) DDR_A_D[0 63] 1 (4) DDR_A_DM[0 7] CONN@ C112 2.2U 6.3V M X5R 0402 +DIMM_VREF R62 Share +DIMM_VREF for 1.DDRII VREF 2.GMCH SM_VREF_0 SM_VREF_1 1K_0402_1% DDR_A_DQS#1 DDR_A_DQS1 DDR_A_D10 DDR_A_D11 2 C107 0.1U_0402_16V4Z C108 0.1U_0402_16V4Z C105 0.1U_0402_16V4Z C106 0.1U_0402_16V4Z C94 220U_B2_2.5VM_R35 @ + DDR_A_D16 DDR_A_D17 DDR_A_DQS#2 DDR_A_DQS2 DDR_A_D24 DDR_A_D25 DDR_A_DM3 DDR_A_D26 DDR_A_D27 (4) C DDR_CKE0 (4) DDR_A_BS2 DDR_CKE0 DDR_A_BS2 DDR_A_MA12 DDR_A_MA9 DDR_A_MA8 DDR_A_MA5 DDR_A_MA3 DDR_A_MA1 Layout Note: Place one cap close to every pullup resistors terminated to +0.9VS (4) DDR_A_BS0 (4) DDR_A_WE# DDR_A_MA10 DDR_A_BS0 DDR_A_WE# (4) DDR_A_CAS# (4) DDR_CS#1 DDR_A_CAS# DDR_CS#1 (4) M_ODT1 M_ODT1 +0.9VS DDR_A_D32 DDR_A_D33 2 2 C446 0.1U_0402_16V4Z C445 0.1U_0402_16V4Z C444 0.1U_0402_16V4Z C443 0.1U_0402_16V4Z C442 0.1U_0402_16V4Z C441 0.1U_0402_16V4Z C440 0.1U_0402_16V4Z C439 0.1U_0402_16V4Z C89 0.1U_0402_16V4Z C118 0.1U_0402_16V4Z C120 0.1U_0402_16V4Z C90 0.1U_0402_16V4Z C91 0.1U_0402_16V4Z C115 0.1U_0402_16V4Z C122 0.1U_0402_16V4Z C88 0.1U_0402_16V4Z C87 0.1U_0402_16V4Z C121 0.1U_0402_16V4Z C86 0.1U_0402_16V4Z C117 0.1U_0402_16V4Z DDR_A_D34 DDR_A_D35 DDR_A_D40 DDR_A_D41 DDR_A_DM5 DDR_A_D42 DDR_A_D43 DDR_A_D48 DDR_A_D49 DDR_A_DQS#6 DDR_A_DQS6 +0.9VS DDR_A_D50 DDR_A_D51 RP5 47_0804_8P4R_5% RP2 8 DDR_A_BS1 DDR_A_MA0 DDR_A_MA2 DDR_A_MA4 DDR_A_BS0 DDR_A_MA10 DDR_A_MA1 DDR_A_MA3 47_0804_8P4R_5% RP4 DDR_A_MA6 DDR_A_MA7 DDR_A_MA11 DDR_A_MA14 47_0804_8P4R_5% RP3 M_ODT1 DDR_CS#1 DDR_A_CAS# DDR_A_WE# 47_0804_8P4R_5% RP1 DDR_A_MA5 DDR_A_MA8 DDR_A_MA9 DDR_A_MA12 DDR_A_D56 DDR_A_D57 Layout Note: Place these resistor closely DIMMA,all trace length