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A B C D E 1 Compal Confidential 2 B3ZMS MB Schematic Document LA-D591P 3 Rev: 2.0 2016.02.24 4 DAX1 Part Number DAA000C2000 B3ZMS_PCB_REV01 Description Compal Secret Data Security Classification PCB 1JL LA-D591P REV0 MB 2015/10/21 Issued Date Deciphered Date 2016/06/21 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Cover Sheet Size Document Number Custom B C D Rev 2.0 B3ZMS LA-D591P Date: A Compal Electronics, Inc Sheet W ednesday, February 24, 2016 E of 45 A B HDMI Conn C D E eDP Memory Bus page 21 CH_A 1.2V lpddr3 1600MHz LPDDR3 Memory down P.18 HDMI PS8407A eDP Intel Skylake U CH_B page 22 LPDDR3 Memory down P.19 DDI2 HDMI x lanes DDI Skylake U Skylake PCH-LP(MCP) (SKL-U_2+2) USB 3.0 Type-C x1 USB 3.0 conn x2 BlueTooth CMOS Camera USB port 3,4 USB port 1,2 USB port USB port Processor page 26 page 25 NGFF WLAN USB port PCIe 1.0 2.5GT/s Dual Core + GT2 port Flexible IO page 24 PCIe 1.0 2.5GT/s SATA3.0 port 6.0 Gb/s USBx8 port (SATA0) Card Reader RTS5220 3.3V 24MHz 15W 1356pin BGA page 23 page 21 48MHz HD Audio NGFF2280 SSD page 26 page 26 HDA Codec ALC255 SPI page 06~17 page 26 Card Reader in (SD) LPC/eSPI BUS SPI ROM x2 CLK=24MHz page 26 page ENE KB9022/9032 page 26 UAJ on Sub/B page 26 page 26 Sub Board page 14 LS-D592P IO/B Power On/Off CKT Int.KBD Touch Pad PS2 (from EC) / I2C (from SOC) Fan Control page 26 page 29 page 39 page 28 page 28 Int MIC iTPM page 27 RTC CKT Int Speaker DC/DC Interface CKT page 42 Com pal Electronics, Inc Compal Secret Data Security Classif ication Power Circuit DC/DC /1 /2 Issu ssue ed Date Deciphered Date /0 /2 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC page 43~55 Title B C D Rev 2.0 B3Z 3ZM MS LA LA-D591P Date: A Block ock D Diiagram agram amss Size Document Number Custom Sheet W ednesday, February 24, 2016 E of 45 A B C D E Board ID Table for AD channel Vcc Ra Board ID 1 3.3V +/- 5% 100K +/- 5% Rb 12K +/- 1% 15K +/- 1% 20K +/- 1% 27K +/- 1% 33K +/- 1% 43K +/- 1% 56K +/- 1% BOARD ID Table Power State V BID 0.347 0.423 0.541 0.691 0.807 0.978 1.169 V V V V V V V V V BID typ V 0.345 V 0.430 V 0.550 V 0.702 V 0.819 V 0.992 V 1.185 V V BID max 0.300 V 0.360 V 0.438 V 0.559 V 0.713 V 0.831 V 1.006 V 1.200 V EC 0x00 0x0C 0x1D 0x27 0x31 0x3C 0x47 0x55 AD3 - 0x0B - 0x1C - 0x26 - 0x30 - 0x3B - 0x46 - 0x54 - 0x64 SIGNAL STATE SLP_S3# SLP_S4# SLP_S5# S0 (Full ON) HIGH S3 (Suspend to RAM) S4 (Suspend to Disk) S5 (Soft OFF) +VALW +V +VS Board ID Clock HIGH HIGH ON ON ON ON LOW HIGH HIGH ON ON OFF OFF LOW LOW HIGH ON OFF OFF OFF LOW LOW LOW ON OFF OFF OFF PCB Revision 0.1(Skylake) 0.2(Skylake) 1.0(Skylake) 2.0(Skylake) 2.0(Kabylake) BOM Structure Table BOM Option Table Item BOM Structure Unpop @ Connector CONN@ EMC requirement EMC@ EMC requirement depop @EMC@ LPC MODE for EC LPC@ ESPI MODE for EC ESPI@ For Acer IOAC IOAC@ No Acer IOAC NIOAC@ For Skylake-U SKL@ For Kabylake-U KBL@ SPI ROM 8M*1 8M_SINGLE@ TPM TPM@ DMIC*1 1DMIC@ For ES Sampel Only ES@ Keyboard backlight KB@ Finger Print FP@ Voltage Rails BOM Option Table Item CODEC(ALC255) CODEC(ALC283) DRAM BOM Select BOM Structure 255@ 283@ X76@/X7601@ ~ X7614@ CPU Code QS:QJ8Q@,QJKK@, QJKR@,QJKP@ MP:SR2EU@,SR2EY@ I2C Address Table BUS Device I2C_0 (+3VS) I2C_1 (+3VS) Address(7 bit) Reserved (Touch Panel) TM-P2969-001 (TP) SB8787-1200 (TP-ELAN) DIMM1 DIMM2 LIS3DHTR(G-Sensor) N16S-GT (VGA) PCH-LP (SOC) BQ24780 (Charger IC) BATTERY PACK SOC_SMBCLK +3VS SOC_SML1CLK +3VS EC_SMB_CK1 +3VLP Power Plane Description +19V_VIN Adapter power supply S0 N/A S3 N/A S4/S5 N/A +17.4V_BATT Battery power supply N/A N/A N/A +19VB AC or battery power rail for power circuit N/A N/A N/A +VCC_CORE Processor IA Cores Power Rail ON OFF OFF +VCC_GT Processor Graphics Power Rails ON OFF OFF +VCC_SA System Agent power rail ON OFF OFF +0.6VS_VTT DDR +0.675VS power rail for DDR terminator ON OFF OFF +1.0VALW_PRIM +1.0V Always power rail ON ON ON*1 +1.0V_VCCSTU Sustain voltage for processor in Standby modes ON ON OFF +VCCIO CPU IO power rail ON OFF OFF +1.0VS_VCCSTG +1.0VALW_PRIM Gated version of VCCST ON OFF OFF +1.2V_VDDQ DDRIIIL +1.35V Power Rail ON ON OFF +1.8VALW_PRIM +1.8V Always power rail ON ON ON*1 +1.5VS System +1.8V power rail ON OFF OFF +3VLP +19VB to +3VLP power rail for suspend power ON ON ON +3VALW System +3VALW always on power rail ON ON ON*1 +3VS System +3V power rail ON OFF OFF +5VALW +5V Always power rail ON ON ON +5VS System +5V power rail ON OFF OFF +RTCVCC RTC Battery Power ON ON ON Address(8bit) Write Read 0x2C 0x15 0xA0 0xA4 0x30 0x9E 0x90 0x12 0x16 Note : ON*1 means power plane is ON only when WOL enable and RTC wake at BIOS setting, otherwise it is OFF Skylake CPU 43 level BOM table 43 Level Description UC1 UC1 UC1 UC1 PMD4405 QJ8Q D0 2.1G BGA SR2EX@ SA000094270 i3-6100U SR2EU D1 2.3G BGA SR2EU@ SA000092NB0 i5-6200U SR2EY D1 2.3G BGA SR2EY@ SA000092OB0 i7-6500U SR2EZ D1 2.5G BGA SR2EZ@ SA000092P90 BOM Structure 431A1MBOL06 PCBA MB AD591 B3ZMS I36100U SR2EU 4G HDMI 8M_SINGLE@/EMC@/SKL@/KB@/LPC@/IOAC@/SR2EU@ 431A1MBOL07 PCBA MB AD591 B3ZMS I56200U SR2EY 4GHDMI 8M_SINGLE@/EMC@/SKL@/KB@/LPC@/IOAC@/SR2EY@ 431A1MBOL08 PCBA MB AD591 B3ZMS I56200U SR2EY 8GHDMI 8M_SINGLE@/EMC@/SKL@/KB@/LPC@/IOAC@/SR2EY@ 431A1MBOL09 431A1MBOL10 PCBA MB AD591 B3ZMS I76500U SR2EZ 4GHDMI 8M_SINGLE@/EMC@/SKL@/KB@/LPC@/IOAC@/SR2EZ@ PCBA MB AD591 B3ZMS I76500U SR2EZ 8GHDMI 8M_SINGLE@/EMC@/SKL@/KB@/LPC@/IOAC@/SR2EZ@ 431A1MBOL11 SMT MB AD591 B3ZMS PMD4405USR2EX 4G 8M_SINGLE@/EMC@/SKL@/KB@/LPC@/IOAC@/SR2EX@ Kabylake CPU UC1 UC1 QKKQ G0 1.7G FCBGA QKKQ@ SA00009QM10 QKKS G0 2.4G BGA QKKS@ SA00009PJ30 4 Compal Secret Data Security Classification Issued Date 2015/10/21 Deciphered Date 2016/06/21 Title Compal Electronics, Inc Notes List THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Rev 2.0 B3ZMS LA-D591P Date: A B C D Wednesday, February 24, 2016 E Sheet of 45 D D C C B B A A Compal Secret Data Security Classification 2015/10/21 Issued Date Deciphered Date 2016/06/21 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Power Map Rev 2.0 B3ZMS LA-D591P Date: Compal Electronics, Inc Size Document Number Custom Wednesday, February 24, 2016 Sheet of 45 A B C D E PWR Sequence_SKL-U2+2_DDR3L_Value_NON CS +RTCVCC tPCH01_Min : ms SOC_RTCRST# +19VB +3VLP 1 EC_ON tPCH04_Min : ms +5VALW/+3VALW(+3VALW_DSW ) SPOK tPCH34_Max : 20 ms tPCH06_Min : 200 us (+3VALW stable (@95% of full value) to +1.0VALW_PRIM starting to ramp) +1.8VALW_PRIM +1.8VALW_PG +VCCPRIM_CORE/+1.0VALW_PRIM tPCH03_Min : 10 ms EC_RSMRST# ON/OFF PBTN_OUT# tPCH43_Min : 95 ms Minimum duration of PWRBTN# assertion = 16mS PWRBTN# can assert before or after RSMRST# PM_SLP_S5# tPCH18_Min : 90 us ESPI_RST# PM_SLP_S4# SYSON +1.0V_VCCSTU +1.2V_VDDQ PM_SLP_S3# SUSP# tCPU04 Min : 100 ns +1.0VS_VCCSTG tCPU10 Min : ms +VCCIO 3 +5VS/+3VS/+1.5VS tCPU00 Min : ms EC_VCCST_PG VR_ON tCPU19 Max : 100 ns SM_PG_CTRL tCPU18 Max : 35 us +0.6VS_VTT tCPU09 Min : ms +VCC_SA VR_PWRGD tCPU16 Min : ns tPLT05 Min : Platform dependent PCH_PWROK (SYS_PWROK) H_CPUPWRGD PLT_RST# 4 +VCC_CORE / +VCC_GT Compal Secret Data Security Classification 2015/10/21 Issued Date Deciphered Date 2016/06/21 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Power Sequence Size Document Number Custom B C D Rev 2.0 B3ZMS LA-D591P Date: A Compal Electronics, Inc Sheet W ednesday, February 24, 2016 E of 45 SOC_DP1_CTRL_DATA(Internal Pull Down): Display Port B Detected = Port B is not detected SKL-U UC1A = Port B is detected Rev_1.0 E55 F55 E58 F58 F53 G53 F56 G56 D SOC_DP2_CTRL_DATA(Internal Pull Down): Display Port C Detected = Port C is not detected = Port C is detected C50 D50 C52 D52 A50 B50 D51 C51 SOC_DP2_N0 SOC_DP2_P0 SOC_DP2_N1 SOC_DP2_P1 SOC_DP2_N2 SOC_DP2_P2 SOC_DP2_N3 SOC_DP2_P3 SOC_DP2_N0 SOC_DP2_P0 SOC_DP2_N1 SOC_DP2_P1 SOC_DP2_N2 SOC_DP2_P2 SOC_DP2_N3 SOC_DP2_P3 DDI1_TXN[0] DDI1_TXP[0] DDI1_TXN[1] DDI1_TXP[1] DDI1_TXN[2] DDI1_TXP[2] DDI1_TXN[3] DDI1_TXP[3] DDI2_TXN[0] DDI2_TXP[0] DDI2_TXN[1] DDI2_TXP[1] DDI2_TXN[2] DDI2_TXP[2] DDI2_TXN[3] DDI2_TXP[3] EDP_TXN[0] EDP_TXP[0] EDP_TXN[1] EDP_TXP[1] EDP_TXN[2] EDP_TXP[2] EDP_TXN[3] EDP_TXP[3] DDI EDP_AUXN EDP_AUXP EDP EDP_DISP_UTIL DDI1_AUXN DDI1_AUXP DDI2_AUXN DDI2_AUXP RSVD RSVD DISPLAY SIDEBANDS +1.0V_VCCST RC1 L13 L12 SOC_DP2_CTRL_CLK SOC_DP2_CTRL_DATA SOC_DP2_CTRL_CLK SOC_DP2_CTRL_DATA 1K_0402_5% H_THERMTRIP# N7 N8 N11 N12 E52 EDP_COMP C GPP_E18/DDPB_CTRLCLK GPP_E19/DDPB_CTRLDATA GPP_E13/DDPB_HPD0 GPP_E14/DDPC_HPD1 GPP_E15/DDPD_HPD2 GPP_E16/DDPE_HPD3 GPP_E17/EDP_HPD GPP_E20/DDPC_CTRLCLK GPP_E21/DDPC_CTRLDATA GPP_E22 GPP_E23 EDP_BKLTEN EDP_BKLTCTL EDP_VDDEN OF 20 EDP_RCOMP C47 C46 D46 C45 A45 B45 A47 B47 EDP_TXN0 EDP_TXP0 EDP_TXN1 EDP_TXP1 EDP_TXN2 EDP_TXP2 EDP_TXN3 EDP_TXP3 EDP_TXN0 EDP_TXP0 EDP_TXN1 EDP_TXP1 EDP_TXN2 EDP_TXP2 EDP_TXN3 EDP_TXP3 E45 F45 EDP_AUXN EDP_AUXP EDP_AUXN EDP_AUXP B52 D TP@ T1 G50 F50 E48 F48 G46 F46 L9 L7 L6 N9 L10 R12 R11 U13 SOC_DP2_HPD SOC_DP2_HPD EC_SCI# EDP_HPD EC_SCI# EDP_HPD ENBKL SOC_BKL_PW M SOC_ENVDD ENBKL SOC_BKL_PW M SOC_ENVDD From HDMI From eDP C SKL-U_BGA1356 COMPENSATION PU FOR eDP +3VS +1.0VS_VCCIO RC3 24.9_0402_1% EDP_COMP EC_SCI# RC159 @ 10K_0402_5% CAD note: Trace width=20 mils,Spacing=25mil,Max length=100mils +1.0VS_VCCSTG +1.0VS_VCCSTG B DCI@ 51_0402_5% DCI@ 51_0402_5% SOC_XDP_TDI RC8 DCI@ 100_0402_1% SOC_XDP_TDO @ 1K_0402_5% 100K_0402_5% EDP_HPD 0.1U_0402_16V7K SOC_XDP_TRST# CPU_XDP_TCK0 H_PROCHOT# Rev_1.0 RC11 TP@ H_PECI 499_0402_1% CC2 10P_0402_50V8J @ESD@ RC12 @ 51_0402_5% XDP_PREQ# XDP_PREQ# RC13 @ 1K_0402_5% XDP_ITP_PMODE XDP_ITP_PMODE EC_TP_INT# RC149 +3VS RC18 @ RC19 DCI@ 51_0402_1% RC20 @ 51_0402_5% PCH_JTAG_TCK1 RC21 @ 0_0402_5% CFG3 H_PECI H_PROCHOT#_R H_THERMTRIP# D63 A54 C65 C63 A65 2 TP@ TP@ TP@ TP@ XDP_BPM#0 XDP_BPM#1 XDP_BPM#2 XDP_BPM#3 C55 D55 B54 C56 I2C_TS_INT# I2C_TS_INT# A6 A7 BA5 AY5 @ 0_0402_5% RC14 RC15 RC16 RC17 2 2 1 1 T9 TP_INT# SOC_GPIOB4 TP@ 49.9_0402_1% 49.9_0402_1% 49.9_0402_1% 49.9_0402_1% AT16 CPU_POPIRCOMP AU16 PCH_OPIRCOMP EDRAM_OPIO_RCOMP H66 H65 EOPIO_RCOMP B CATERR# PECI PROCHOT# THERMTRIP# SKTOCC# JTAG CPU MISC PROC_TCK PROC_TDI PROC_TDO PROC_TMS PROC_TRST# BPM#[0] BPM#[1] BPM#[2] BPM#[3] GPP_E3/CPU_GP0 GPP_E7/CPU_GP1 GPP_B3/CPU_GP2 GPP_B4/CPU_GP3 PCH_JTAG_TCK PCH_JTAG_TDI PCH_JTAG_TDO PCH_JTAG_TMS PCH_TRST# JTAGX PROC_POPIRCOMP PCH_OPIRCOMP OPCE_RCOMP OPC_RCOMP SOC_XDP_TRST# T5 T6 T7 T8 D22 RB751V-40_SOD323-2 SKL-U UC1D T3 +1.0V_PRIM CPU_XDP_TCK0 SOC_XDP_TDI SOC_XDP_TDO SOC_XDP_TMS SOC_XDP_TRST# B56 D59 A56 C59 C61 A59 PCH_JTAG_TCK1 SOC_XDP_TDI SOC_XDP_TDO SOC_XDP_TMS SOC_XDP_TRST# CPU_XDP_TCK0 SKL-U_BGA1356 H_PECI I2C_TS_INT# +3VS CC56 10P_0402_50V8J @ESD@ A ESD request CFG3 B61 D60 A61 C60 B59 OF 20 RC42 100K_0402_5% CPU_XDP_TCK0 RC47 100K_0402_5% TP_INT# Compal Electronics, Inc Compal Secret Data Security Classification 2015/10/21 Issued Date Deciphered Date 2016/06/21 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title SKL-U(1/12))DDI,MSIC,XDP,EDP Size Document Number Custom Date: RC5 @ESD@ A 100K_0402_5% ENBKL CC1 RC9 1K_0402_5% H_PROCHOT# 51_0402_5% 100K_0402_5% SOC_ENVDD SOC_XDP_TMS RC7 RC10 RC4 2 RC6 RC2 Rev 2.0 B3ZMS LA-D591P W ednesday, February 24, 2016 Sheet of 45 non-Interleaved non-Interleaved D D SKL-U UC1C UC1B SKL-U Rev_1.0 Rev_1.0 DDR_A_D[0 15] DDR_A_D[32 47] C DDR_B_D[0 15] DDR_B_D[32 47] B DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 AL71 AL68 AN68 AN69 AL70 AL69 AN70 AN71 AR70 AR68 AU71 AU68 AR71 AR69 AU70 AU69 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 BB65 AW65 AW63 AY63 BA65 AY65 BA63 BB63 BA61 AW61 BB59 AW59 BB61 AY61 BA59 AY59 AY39 AW39 AY37 AW37 BB39 BA39 BA37 BB37 AY35 AW35 AY33 AW33 BB35 BA35 BA33 BB33 AY31 AW31 AY29 AW29 BB31 BA31 BA29 BB29 AY27 AW27 AY25 AW25 BB27 BA27 BA25 BB25 DDR0_DQ[0] DDR0_DQ[1] DDR0_DQ[2] DDR0_DQ[3] DDR0_DQ[4] DDR0_DQ[5] DDR0_DQ[6] DDR0_DQ[7] DDR0_DQ[8] DDR0_DQ[9] DDR0_DQ[10] DDR0_DQ[11] DDR0_DQ[12] DDR0_DQ[13] DDR0_DQ[14] DDR0_DQ[15] Interleave / Non-Interleaved DDR0_DQ[16]/DDR0_DQ[32] DDR0_DQ[17]/DDR0_DQ[33] DDR0_DQ[18]/DDR0_DQ[34] DDR0_DQ[19]/DDR0_DQ[35] DDR0_DQ[20]/DDR0_DQ[36] DDR0_DQ[21]/DDR0_DQ[37] DDR0_DQ[22]/DDR0_DQ[38] DDR0_DQ[23]/DDR0_DQ[39] DDR0_DQ[24]/DDR0_DQ[40] DDR0_DQ[25]/DDR0_DQ[41] DDR0_DQ[26]/DDR0_DQ[42] DDR0_DQ[27]/DDR0_DQ[43] DDR0_DQ[28]/DDR0_DQ[44] DDR0_DQ[29]/DDR0_DQ[45] DDR0_DQ[30]/DDR0_DQ[46] DDR0_DQ[31]/DDR0_DQ[47] DDR0_DQ[32]/DDR1_DQ[0] DDR0_DQ[33]/DDR1_DQ[1] DDR0_DQ[34]/DDR1_DQ[2] DDR0_DQ[35]/DDR1_DQ[3] DDR0_DQ[36]/DDR1_DQ[4] DDR0_DQ[37]/DDR1_DQ[5] DDR0_DQ[38]/DDR1_DQ[6] DDR0_DQ[39]/DDR1_DQ[7] DDR0_DQ[40]/DDR1_DQ[8] DDR0_DQ[41]/DDR1_DQ[9] DDR0_DQ[42]/DDR1_DQ[10] DDR0_DQ[43]/DDR1_DQ[11] DDR0_DQ[44]/DDR1_DQ[12] DDR0_DQ[45]/DDR1_DQ[13] DDR0_DQ[46]/DDR1_DQ[14] DDR0_DQ[47]/DDR1_DQ[15] DDR0_DQ[48]/DDR1_DQ[32] DDR0_DQ[49]/DDR1_DQ[33] DDR0_DQ[50]/DDR1_DQ[34] DDR0_DQ[51]/DDR1_DQ[35] DDR0_DQ[52]/DDR1_DQ[36] DDR0_DQ[53]/DDR1_DQ[37] DDR0_DQ[54]/DDR1_DQ[38] DDR0_DQ[55]/DDR1_DQ[39] DDR0_DQ[56]/DDR1_DQ[40] DDR0_DQ[57]/DDR1_DQ[41] DDR0_DQ[58]/DDR1_DQ[42] DDR0_DQ[59]/DDR1_DQ[43] DDR0_DQ[60]/DDR1_DQ[44] DDR0_DQ[61]/DDR1_DQ[45] DDR0_DQ[62]/DDR1_DQ[46] DDR0_DQ[63]/DDR1_DQ[47] DDR0_CKN[0] DDR0_CKP[0] DDR0_CKN[1] DDR0_CKP[1] DDR0_CKE[0] DDR0_CKE[1] DDR0_CKE[2] DDR0_CKE[3] DDR0_CS#[0] DDR0_CS#[1] DDR0_ODT[0] DDR0_ODT[1] DDR3L / LPDDR3 / DDR4 DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7] DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11] DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1] DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13] DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15] DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14] DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16] DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0] DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2] DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1] DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10] DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0] DDR0_MA[3] DDR0_MA[4] DDR0_DQSN[0] DDR0_DQSP[0] DDR0_DQSN[1] DDR0_DQSP[1] Interleave / Non-Interleaved DDR0_DQSN[2]/DDR0_DQSN[4] DDR0_DQSP[2]/DDR0_DQSP[4] DDR0_DQSN[3]/DDR0_DQSN[5] DDR0_DQSP[3]/DDR0_DQSP[5] DDR0_DQSN[4]/DDR1_DQSN[0] DDR0_DQSP[4]/DDR1_DQSP[0] DDR0_DQSN[5]/DDR1_DQSN[1] DDR0_DQSP[5]/DDR1_DQSP[1] DDR0_DQSN[6]/DDR1_DQSN[4] DDR0_DQSP[6]/DDR1_DQSP[4] DDR0_DQSN[7]/DDR1_DQSN[5] DDR0_DQSP[7]/DDR1_DQSP[5] DDR0_ALERT# DDR0_PAR DDR CH - A OF 20 DDR_VREF_CA DDR0_VREF_DQ DDR1_VREF_DQ DDR_VTT_CNTL SKL-U_BGA1356 DDR_A_D[16 31] AU53 AT53 AU55 AT55 M_CLK_A_DDR#0 M_CLK_A_DDR0 M_CLK_A_DDR#1 M_CLK_A_DDR1 M_CLK_A_DDR#0 M_CLK_A_DDR0 M_CLK_A_DDR#1 M_CLK_A_DDR1 BA56 BB56 AW56 AY56 DDR_A_CKE0 DDR_A_CKE1 DDR_A_CKE2 DDR_A_CKE3 DDR_A_CKE0 DDR_A_CKE1 DDR_A_CKE2 DDR_A_CKE3 AU45 AU43 AT45 AT43 DDR_A_CS0# DDR_A_CS1# DDR_A_ODT0 DDR_A_CS0# DDR_A_CS1# DDR_A_ODT0 BA51 BB54 BA52 AY52 AW52 AY55 AW54 BA54 BA55 AY54 AU46 AU48 AT46 AU50 AU52 AY51 AT48 AT50 BB50 AY50 DDR_A_CAA_0 DDR_A_CAA_1 DDR_A_CAA_2 DDR_A_CAA_3 DDR_A_CAA_4 DDR_A_CAA_5 DDR_A_CAA_6 DDR_A_CAA_7 DDR_A_CAA_8 DDR_A_CAA_9 DDR_A_CAB_0 DDR_A_CAB_1 DDR_A_CAB_2 DDR_A_CAB_3 DDR_A_CAB_4 DDR_A_CAB_5 DDR_A_CAB_6 DDR_A_CAB_7 DDR_A_CAB_8 DDR_A_CAB_9 BA50 BB52 AM70 AM69 AT69 AT70 DDR_A_DQS#0 DDR_A_DQS0 DDR_A_DQS#1 DDR_A_DQS1 DDR_A_DQS#0 DDR_A_DQS0 DDR_A_DQS#1 DDR_A_DQS1 BA64 AY64 AY60 BA60 BA38 AY38 AY34 BA34 BA30 AY30 AY26 BA26 DDR_A_DQS#4 DDR_A_DQS4 DDR_A_DQS#5 DDR_A_DQS5 DDR_B_DQS#0 DDR_B_DQS0 DDR_B_DQS#1 DDR_B_DQS1 DDR_B_DQS#4 DDR_B_DQS4 DDR_B_DQS#5 DDR_B_DQS5 DDR_A_DQS#4 DDR_A_DQS4 DDR_A_DQS#5 DDR_A_DQS5 DDR_B_DQS#0 DDR_B_DQS0 DDR_B_DQS#1 DDR_B_DQS1 DDR_B_DQS#4 DDR_B_DQS4 DDR_B_DQS#5 DDR_B_DQS5 AW50 AT52 AY67 AY68 BA67 AW67 DDR_A_D[48 63] DDR_A_CAA_0 DDR_A_CAA_1 DDR_A_CAA_2 DDR_A_CAA_3 DDR_A_CAA_4 DDR_A_CAA_5 DDR_A_CAA_6 DDR_A_CAA_7 DDR_A_CAA_8 DDR_A_CAA_9 DDR_A_CAB_0 DDR_A_CAB_1 DDR_A_CAB_2 DDR_A_CAB_3 DDR_A_CAB_4 DDR_A_CAB_5 DDR_A_CAB_6 DDR_A_CAB_7 DDR_A_CAB_8 DDR_A_CAB_9 DDR_B_D[16 31] DDR_B_D[48 63] TP@ T10 TP@ T12 +VREF_CA_C +V_DDR_REFA_C +V_DDR_REFB_C +VREF_CA_C +V_DDR_REFA_C +V_DDR_REFB_C Trace width/Spacing >= 20mils DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 AF65 AF64 AK65 AK64 AF66 AF67 AK67 AK66 AF70 AF68 AH71 AH68 AF71 AF69 AH70 AH69 AT66 AU66 AP65 AN65 AN66 AP66 AT65 AU65 AT61 AU61 AP60 AN60 AN61 AP61 AT60 AU60 AU40 AT40 AT37 AU37 AR40 AP40 AP37 AR37 AT33 AU33 AU30 AT30 AR33 AP33 AR30 AP30 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63 AU27 AT27 AT25 AU25 AP27 AN27 AN25 AP25 AT22 AU22 AU21 AT21 AN22 AP22 AP21 AN21 DDR_PG_CTRL Interleave / Non-Interleaved DDR1_DQ[0]/DDR0_DQ[16] DDR1_DQ[1]/DDR0_DQ[17] DDR1_DQ[2]/DDR0_DQ[18] DDR1_DQ[3]/DDR0_DQ[19] DDR1_DQ[4]/DDR0_DQ[20] DDR1_DQ[5]/DDR0_DQ[21] DDR1_DQ[6]/DDR0_DQ[22] DDR1_DQ[7]/DDR0_DQ[23] DDR1_DQ[8]/DDR0_DQ[24] DDR1_DQ[9]/DDR0_DQ[25] DDR1_DQ[10]/DDR0_DQ[26] DDR1_DQ[11]/DDR0_DQ[27] DDR1_DQ[12]/DDR0_DQ[28] DDR1_DQ[13]/DDR0_DQ[29] DDR1_DQ[14]/DDR0_DQ[30] DDR1_DQ[15]/DDR0_DQ[31] DDR1_DQ[16]/DDR0_DQ[48] DDR1_DQ[17]/DDR0_DQ[49] DDR1_DQ[18]/DDR0_DQ[50] DDR1_DQ[19]/DDR0_DQ[51] DDR1_DQ[20]/DDR0_DQ[52] DDR1_DQ[21]/DDR0_DQ[53] DDR1_DQ[22]/DDR0_DQ[54] DDR1_DQ[23]/DDR0_DQ[55] DDR1_DQ[24]/DDR0_DQ[56] DDR1_DQ[25]/DDR0_DQ[57] DDR1_DQ[26]/DDR0_DQ[58] DDR1_DQ[27]/DDR0_DQ[59] DDR1_DQ[28]/DDR0_DQ[60] DDR1_DQ[29]/DDR0_DQ[61] DDR1_DQ[30]/DDR0_DQ[62] DDR1_DQ[31]/DDR0_DQ[63] DDR1_DQ[32]/DDR1_DQ[16] DDR1_DQ[33]/DDR1_DQ[17] DDR1_DQ[34]/DDR1_DQ[18] DDR1_DQ[35]/DDR1_DQ[19] DDR1_DQ[36]/DDR1_DQ[20] DDR1_DQ[37]/DDR1_DQ[21] DDR1_DQ[38]/DDR1_DQ[22] DDR1_DQ[39]/DDR1_DQ[23] DDR1_DQ[40]/DDR1_DQ[24] DDR1_DQ[41]/DDR1_DQ[25] DDR1_DQ[42]/DDR1_DQ[26] DDR1_DQ[43]/DDR1_DQ[27] DDR1_DQ[44]/DDR1_DQ[28] DDR1_DQ[45]/DDR1_DQ[29] DDR1_DQ[46]/DDR1_DQ[30] DDR1_DQ[47]/DDR1_DQ[31] DDR1_CKN[0] DDR1_CKN[1] DDR1_CKP[0] DDR1_CKP[1] DDR1_CKE[0] DDR1_CKE[1] DDR1_CKE[2] DDR1_CKE[3] DDR1_CS#[0] DDR1_CS#[1] DDR1_ODT[0] DDR1_ODT[1] DDR3L / LPDDR3 / DDR4 DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7] DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11] DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT# DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1] DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13] DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15] DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14] DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16] DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0] DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2] DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10] DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0] DDR1_MA[3] DDR1_MA[4] Interleave / Non-Interleaved DDR1_DQSN[0]/DDR0_DQSN[2] DDR1_DQSP[0]/DDR0_DQSP[2] DDR1_DQSN[1]/DDR0_DQSN[3] DDR1_DQSP[1]/DDR0_DQSP[3] DDR1_DQSN[2]/DDR0_DQSN[6] DDR1_DQSP[2]/DDR0_DQSP[6] DDR1_DQSN[3]/DDR0_DQSN[7] DDR1_DQSP[3]/DDR0_DQSP[7] DDR1_DQSN[4]/DDR1_DQSN[2] DDR1_DQSP[4]/DDR1_DQSP[2] DDR1_DQSN[5]/DDR1_DQSN[3] DDR1_DQSP[5]/DDR1_DQSP[3] DDR1_DQ[48] DDR1_DQ[49] DDR1_DQ[50] DDR1_DQ[51] DDR1_DQ[52] DDR1_DQ[53] DDR1_DQ[54] DDR1_DQ[55] DDR1_DQ[56] DDR1_DQ[57] DDR1_DQ[58] DDR1_DQ[59] DDR1_DQ[60] DDR1_DQ[61] DDR1_DQ[62] DDR1_DQ[63] DDR1_DQSN[6] DDR1_DQSP[6] DDR1_DQSN[7] DDR1_DQSP[7] DDR1_ALERT# DDR1_PAR DRAM_RESET# DDR_RCOMP[0] DDR_RCOMP[1] DDR_RCOMP[2] DDR CH - B OF 20 AN45 AN46 AP45 AP46 M_CLK_B_DDR#0 M_CLK_B_DDR#1 M_CLK_B_DDR0 M_CLK_B_DDR1 M_CLK_B_DDR#0 M_CLK_B_DDR#1 M_CLK_B_DDR0 M_CLK_B_DDR1 AN56 AP55 AN55 AP53 DDR_B_CKE0 DDR_B_CKE1 DDR_B_CKE2 DDR_B_CKE3 DDR_B_CKE0 DDR_B_CKE1 DDR_B_CKE2 DDR_B_CKE3 BB42 AY42 BA42 AW42 DDR_B_CS0# DDR_B_CS1# DDR_B_ODT0 DDR_B_CS0# DDR_B_CS1# DDR_B_ODT0 AY48 AP50 BA48 BB48 AP48 AP52 AN50 AN48 AN53 AN52 BA43 AY43 AY44 AW44 BB44 AY47 BA44 AW46 AY46 BA46 DDR_B_CAA_0 DDR_B_CAA_1 DDR_B_CAA_2 DDR_B_CAA_3 DDR_B_CAA_4 DDR_B_CAA_5 DDR_B_CAA_6 DDR_B_CAA_7 DDR_B_CAA_8 DDR_B_CAA_9 DDR_B_CAB_0 DDR_B_CAB_1 DDR_B_CAB_2 DDR_B_CAB_3 DDR_B_CAB_4 DDR_B_CAB_5 DDR_B_CAB_6 DDR_B_CAB_7 DDR_B_CAB_8 DDR_B_CAB_9 DDR_B_CAA_0 DDR_B_CAA_1 DDR_B_CAA_2 DDR_B_CAA_3 DDR_B_CAA_4 DDR_B_CAA_5 DDR_B_CAA_6 DDR_B_CAA_7 DDR_B_CAA_8 DDR_B_CAA_9 DDR_B_CAB_0 DDR_B_CAB_1 DDR_B_CAB_2 DDR_B_CAB_3 DDR_B_CAB_4 DDR_B_CAB_5 DDR_B_CAB_6 DDR_B_CAB_7 DDR_B_CAB_8 DDR_B_CAB_9 C BB46 BA47 AH66 AH65 AG69 AG70 AR66 AR65 AR61 AR60 AT38 AR38 AT32 AR32 DDR_A_DQS#2 DDR_A_DQS2 DDR_A_DQS#3 DDR_A_DQS3 DDR_A_DQS#6 DDR_A_DQS6 DDR_A_DQS#7 DDR_A_DQS7 DDR_B_DQS#2 DDR_B_DQS2 DDR_B_DQS#3 DDR_B_DQS3 AR25 AR27 AR22 AR21 AN43 AP43 AT13 AR18 AT18 AU18 DDR_B_DQS#6 DDR_B_DQS6 DDR_B_DQS#7 DDR_B_DQS7 DDR3_DRAMRST# SM_RCOMP0 SM_RCOMP1 SM_RCOMP2 DDR_A_DQS#2 DDR_A_DQS2 DDR_A_DQS#3 DDR_A_DQS3 DDR_A_DQS#6 DDR_A_DQS6 DDR_A_DQS#7 DDR_A_DQS7 DDR_B_DQS#2 DDR_B_DQS2 DDR_B_DQS#3 DDR_B_DQS3 DDR_B_DQS#6 DDR_B_DQS6 DDR_B_DQS#7 DDR_B_DQS7 TP@ T11 TP@ T13 TP@ T14 RC22 RC23 RC24 200_0402_1% 80.6_0402_1% 162_0402_1% B SKL-U_BGA1356 Buffer with Open Drain output For VTT power control +1.2V_VDDQ +3VS 0.1U_0201_10V6K CC4 @ESD@ 0.1U_0402_16V7K DDR3_DRAMRST# UC2 SM_PG_CTRL CC3 RC25 100K_0402_5% SM_PG_CTRL VCC NC A Y GND DDR_PG_CTRL 74AUP1G07GW_TSSOP5 SA00007UR00 A A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2015/10/21 Deciphered Date 2016/06/21 Title SLK-U(2/12)LPDDR3 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: Rev 2.0 B3ZMS LA-D591P Wednesday, February 24, 2016 Sheet of 45 SML0ALERT# (Internal Pull Down): eSPI or LPC = LPC is selected for EC > For KB9022/9032 Use = eSPI is selected for EC > For KB9032 Only SKL-U UC1E +3V_PRIM Rev_1.0 SPI - FLASH AV2 AW3 AV3 AW2 AU4 AU3 AU2 AU1 SOC_SPI_CLK SOC_SPI_SO SOC_SPI_SI SOC_SPI_IO2 SOC_SPI_IO3 SOC_SPI_CS#0 D SMBUS, SMLINK SPI0_CLK SPI0_MISO SPI0_MOSI SPI0_IO2 SPI0_IO3 SPI0_CS0# SPI0_CS1# SPI0_CS2# GPP_C0/SMBCLK GPP_C1/SMBDATA GPP_C2/SMBALERT# GPP_C3/SML0CLK GPP_C4/SML0DATA GPP_C5/SML0ALERT# GPP_C6/SML1CLK GPP_C7/SML1DATA GPP_B23/SML1ALERT#/PCHHOT# SPI - TOUCH M2 M3 J4 V1 V2 M1 GPP_D1/SPI1_CLK GPP_D2/SPI1_MISO GPP_D3/SPI1_MOSI GPP_D21/SPI1_IO2 GPP_D22/SPI1_IO3 GPP_D0/SPI1_CS# EC_KBRST#_R To TPM EC_SERIRQ AW13 EC_KBRST#_R AY11 EC_SERIRQ SMBCLK SMBDATA SMBALERT# R9 W2 W1 SML0CLK SML0DATA SML0ALERT# W3 V3 AM7 SOC_SML1CLK SOC_SML1DATA SML1ALERT# AY13 BA13 BB13 AY12 BA12 BA11 LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 LPC_FRAME# ESPI_RST# AW9 AY9 AW11 ESPI_CLK RC31 CLK_PCI1 RC32 PM_CLKRUN# SMB SMBALERT# RC26 @ 10K_0402_5% SML1ALERT# RC27 @ 150K_0402_1% SML0ALERT# RC28 RC29 1 @ 10K_0402_5% 1K_0402_5% (Link to XDP, DDR, TP) TP@ T15 LPC CL_CLK CL_DATA CL_RST# GPP_A9/CLKOUT_LPC0/ESPI_CLK GPP_A10/CLKOUT_LPC1 GPP_A8/CLKRUN# GPP_A0/RCIN# GPP_A6/SERIRQ SOC_SML1CLK SML1 SOC_SML1DATA (Link to EC, Thermal Sensor) TP@ T16 LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 LPC_FRAME# ESPI_RST# LPC@ TPM@ EC_KBRST#_R RC30 22_0402_5% 22_0402_5% @RF@ CC5 22P_0201_25V8 LPC Mode SKL-U_BGA1356 C @ 10K_0402_5% +3V_PRIM ESPI_CLK_R CK_LPC_TPM PM_CLKRUN# OF 20 1 2 SML0CLK RC33 SML0DATA RC34 @RF@ CC6 22P_0201_25V8 499_0402_1% 499_0402_1% RPC1 SOC_SML1CLK SOC_SML1DATA SMBDATA SMBCLK C 2.2K_0804_8P4R_5% 2015MOW06 no need PU1K on SPI_IO2/IO3 +3VALW _SPI SOC_SPI_IO2 RC37 +3VS 1K_0402_1% @ PM_CLKRUN# 2 RC36 EC_SERIRQ 8.2K_0402_5% RC38 SOC_SPI_IO3 D +3VS GPP_A1/LAD0/ESPI_IO0 GPP_A2/LAD1/ESPI_IO1 GPP_A3/LAD2/ESPI_IO2 GPP_A4/LAD3/ESPI_IO3 GPP_A5/LFRAME#/ESPI_CS# GPP_A14/SUS_STAT#/ESPI_RESET# C LINK G3 G2 G1 R7 R8 R10 RC39 @ RC40 ES@ 1K_0402_1% 8.2K_0402_5% 1K_0402_1% Follow 543016_SKL_U_Y_PDG_0_9 MOW36 add PD 1K depop PH 1K only for SKL U ES sample +3VS Single SPI ROM_CS0# B SOC_SML1CLK RPC3 and RC41 are close UC4 B EC_SMB_CK2 To SPI ROM SOC_SPI_IO3 SOC_SPI_SI SOC_SPI_CLK SOC_SPI_SO QC1A DMN66D0LDW -7_SOT363-6 SOC_SML1DATA 15_0804_8P4R_5% 8M_SINGLE@ SOC_SPI_IO2_0_R RC41 8M_SINGLE@ +3VALW _SPI UC4 /CS DO(IO1) /WP(IO2) GND EC_SMB_DA2 QC1B DMN66D0LDW -7_SOT363-6 SOC_SPI_IO2 15_0402_5% SPI ROM ( 8MByte ) SOC_SPI_CS#0 SOC_SPI_SO_0_R SOC_SPI_IO2_0_R RPC3 SOC_SPI_IO3_0_R SOC_SPI_SI_0_R SOC_SPI_CLK_0_R SOC_SPI_SO_0_R CC7 0.1U_0201_10V6K VCC /HOLD(IO3) CLK DI(IO0) SOC_SPI_IO3_0_R SOC_SPI_CLK_0_R SOC_SPI_SI_0_R W 25Q64FVSSIQ_SO8 8M_SINGLE@ RC43 SOC_SPI_CLK_0_R @EMC@2 0_0402_5% CC9 @EMC@ 10P_0402_50V8J A A Compal El Ele ectronics, Inc Compal Secret Data Security Classif ication /1 /2 Issue ssued Date Deciphered Date /0 /2 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title SK SKL L-U(3/12)SP SPII,ESP SPII,SMB, SMB,LPC Size Document Number Custom Date: Rev 2.0 B3ZMS LA-D591P W ednesday, February 24, 2016 Sheet of 45 SKL-U UC1G Rev_1.0 AUDIO HDA_SDIN0 T17 TP@ HDA_SYNC HDA_BIT_CLK HDA_SDOUT HDA_SDIN0 HDA_RST# D T18 T19 TP@ TP@ SOC_GPIOF1 SOC_GPIOF0 BA22 AY22 BB22 BA21 AY21 AW22 J5 AY20 AW20 AK7 AK6 AK9 AK10 H5 D7 D8 C8 SPKR SPKR AW5 HDA_SYNC/I2S0_SFRM HDA_BLK/I2S0_SCLK HDA_SDO/I2S0_TXD HDA_SDI0/I2S0_RXD HDA_SDI1/I2S1_RXD HDA_RST#/I2S1_SCLK GPP_D23/I2S_MCLK I2S1_SFRM I2S1_TXD SDIO / SDXC GPP_G0/SD_CMD GPP_G1/SD_DATA0 GPP_G2/SD_DATA1 GPP_G3/SD_DATA2 GPP_G4/SD_DATA3 GPP_G5/SD_CD# GPP_G6/SD_CLK GPP_G7/SD_WP GPP_F1/I2S2_SFRM GPP_F0/I2S2_SCLK GPP_F2/I2S2_TXD GPP_F3/I2S2_RXD GPP_A17/SD_PWR_EN#/ISH_GP7 GPP_A16/SD_1P8_SEL GPP_D19/DMIC_CLK0 GPP_D20/DMIC_DATA0 SD_RCOMP GPP_D17/DMIC_CLK1 GPP_D18/DMIC_DATA1 GPP_F23 AB11 AB13 AB12 W12 W11 W10 W8 W7 D BA9 BB9 AB7 SD_RCOMP RC44 AF13 T20 200_0402_1% TP@ GPP_B14/SPKR OF 20 SKL-U_BGA1356 HDA for AUDIO RPC5 C HDA_SYNC_R HDA_SDOUT_R HDA_RST#_R C HDA_SYNC HDA_SDOUT HDA_RST# 33_0804_8P4R_5% HDA_BIT_CLK_R ME_EN ME_EN RC49 @ 0_0402_5% HDA_SDOUT RC54 EMC@ HDA_BIT_CLK 33_0402_5% UC1I SKL-U Rev_1.0 CSI-2 A36 B36 C38 D38 C36 D36 A38 B38 B C31 D31 C33 D33 A31 B31 A33 B33 A29 B29 C28 D28 A27 B27 C27 D27 CSI2_DN0 CSI2_DP0 CSI2_DN1 CSI2_DP1 CSI2_DN2 CSI2_DP2 CSI2_DN3 CSI2_DP3 CSI2_CLKN0 CSI2_CLKP0 CSI2_CLKN1 CSI2_CLKP1 CSI2_CLKN2 CSI2_CLKP2 CSI2_CLKN3 CSI2_CLKP3 CSI2_DN4 CSI2_DP4 CSI2_DN5 CSI2_DP5 CSI2_DN6 CSI2_DP6 CSI2_DN7 CSI2_DP7 CSI2_COMP GPP_D4/FLASHTRIG C37 D37 C32 D32 C29 D29 B26 A26 B E13 CSI2_COMP B7 RC63 T21 TP@ 100_0402_1% EMMC GPP_F13/EMMC_DATA0 GPP_F14/EMMC_DATA1 GPP_F15/EMMC_DATA2 GPP_F16/EMMC_DATA3 GPP_F17/EMMC_DATA4 GPP_F18/EMMC_DATA5 GPP_F19/EMMC_DATA6 GPP_F20/EMMC_DATA7 CSI2_DN8 CSI2_DP8 CSI2_DN9 CSI2_DP9 CSI2_DN10 CSI2_DP10 CSI2_DN11 CSI2_DP11 GPP_F21/EMMC_RCLK GPP_F22/EMMC_CLK GPP_F12/EMMC_CMD OF 20 EMMC_RCOMP AP2 AP1 AP3 AN3 AN1 AN2 AM4 AM1 AM2 AM3 AP4 AT1 EMMC_RCOMP RC64 200_0402_1% SKL-U_BGA1356 A A Compal Electronics, Inc Compal Secret Data Security Classification 2015/10/21 Issued Date Deciphered Date 2016/06/21 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title SKL-U(4/12)HDA,EMMC,SD Size Document Number Custom Date: Rev 2.0 B3ZMS LA-D591P W ednesday, February 24, 2016 Sheet of 45 +RTCVCC UC1J SKL-U Rev_1.0 RC66 20K_0402_5% CC11 PCH_SRTCRST# CLOCK SIGNALS 1U_0402_6.3V6K RC65 D 20K_0402_5% CC12 CC120 @1 CLKREQ_PCIE#1 B42 A42 AT7 CLK_PCIE_WLAN# CLK_PCIE_WLAN WLAN_CLKREQ# D41 C41 AT8 PCH_RTCRST# 1U_0402_6.3V6K 10U_0603_6.3V6M RC67 D42 C42 AR10 CLK_PCIE_NGFF# CLK_PCIE_NGFF NGFF_CLKREQ# CLK_PCIE_NGFF# CLK_PCIE_NGFF NGFF_CLKREQ# NGFF SSD 1M_0402_5% CLR CMOS CLK_PCIE_WLAN# CLK_PCIE_WLAN WLAN_CLKREQ# WLAN SM_INTRUDER# CLK_PCIE_Card# CLK_PCIE_Card Card_CLKREQ# CardReader +3VS CLK_PCIE_Card# CLK_PCIE_Card Card_CLKREQ# D40 C40 AT10 CLKREQ_PCIE#4 B40 A40 AU8 CLKREQ_PCIE#5 E40 E38 AU7 From 545659_SKL_PCH_U_Y_EDS_R0_7 CLKREQ_PCIE#4 10K_0402_5% CLKREQ_PCIE#5 10K_0402_5% RC69 RC70 CLKOUT_PCIE_N0 CLKOUT_PCIE_P0 GPP_B5/SRCCLKREQ0# CLKOUT_PCIE_N1 CLKOUT_PCIE_P1 GPP_B6/SRCCLKREQ1# F43 E43 CLKOUT_ITPXDP_N CLKOUT_ITPXDP_P CLKOUT_PCIE_N2 CLKOUT_PCIE_P2 GPP_B7/SRCCLKREQ2# GPD8/SUSCLK XTAL24_IN XTAL24_OUT CLKOUT_PCIE_N3 CLKOUT_PCIE_P3 GPP_B8/SRCCLKREQ3# XCLK_BIASREF RTCX1 RTCX2 CLKOUT_PCIE_N4 CLKOUT_PCIE_P4 GPP_B9/SRCCLKREQ4# SRTCRST# RTCRST# BA17 SUSCLK E37 E35 PCH_XTAL24_IN PCH_XTAL24_OUT E42 XCLK_BIASREF AM18 AM20 PCH_RTCX1 PCH_RTCX2 AN18 AM16 PCH_SRTCRST# PCH_RTCRST# SUSCLK RC68 1 RC158 @ D 2.7K_0402_1% 60.4_0402_1% +1.0V_CLK5_F24NS CLKOUT_PCIE_N5 CLKOUT_PCIE_P5 GPP_B10/SRCCLKREQ5# 10 OF 20 SKL-U_BGA1356 RPC6 NGFF_CLKREQ# WLAN_CLKREQ# CLKREQ_PCIE#1 Card_CLKREQ# PCH_XTAL24_IN 10K_0804_8P4R_5% PCH_RTCX2 PCH PLTRST Buffer RC71 0_0402_5% @ RC72 PCH_XTAL24_OUT 1M_0402_5% RC73 PCH_RTCX1 10M_0402_5% +3VALW_DSW +3VS RPC7 PLT_RST_BUF# PLT_RST_BUF# UC6 SN74AHC1G08DCKR_SC70-5 RC53 100K_0402_5% CC20 0.1U_0402_16V7K @ESD@ O IN2 IN1 SYS_PWROK 0.1U_0402_16V7K RC74 RC75 UC1K 2 C Rev_1.0 EC_RSMRST# T23 TP@ RC76 @ 8.2K_0402_5% PM_BATLOW# RC78 1K_0402_5% WAKE# 1K_0402_5% RC79 SYS_PWROK PCH_PWROK 10K_0402_5% AC_PRESENT_R SUSPWRDNACK CC23 B AN10 B5 AY17 PLT_RST# SYS_RESET# EC_RSMRST# Only For Power Sequence Debug RC77 @ESD@ 0.1U_0402_16V7K H_CPUPWRGD H_CPUPWRGD EC_VCCST_PG A68 B65 SYS_PWROK PCH_PWROK PCH_DPWROK B6 BA20 BB20 SUSPWRDNACK SUSACK#_R AR13 AP11 BB15 AM15 AW17 AT15 WAKE# LAN_WAKE# +3V_PRIM T28 @ 10K_0402_5% SOC_VRALERT# @ 100K_0402_5% PBTN_OUT#_R SKL-U SYSTEM POWER MANAGEMENT +3VALW_DSW RC80 SJ10000DI00 32.768KHZ_9PF_CM7V-T1A9.0PF20PPM SJ10000L000 SYS_RESET# 0.1U_0402_16V7K PLT_RST# @ GND 32M use these part (SJ10000NM00, SJ10000MH00) just can meet 20m ohm SD00000S120 +19VB S Vgs = 20V Vds = 60V Id = 115mA D Protection for reverse input **Design Notes** #For 65 /90W system, 3S1P/3S2P battery Maximum Charging current 3.5A Battery discharge power 55W #Register Setting 0X12 bit8 set (default 1) to disable IFAULT HI if add ISN choke 0X12 bit3 set (default 0) to enable turbo boost function Disable turbo when AC only #Circuit Design ACOK,ILIM pull high voltage need base on 3/5V enable control Use 10X10 choke and 3X3 H/L side MOSFET Charge current 3.5A Power loss : 1.82W Power density : 0.81 (15X15) If use 4S per cell 4.35V battery, need additional circuit for ACDET(PR218/PR220/PR222 change to 0.1%, parallel resistors with PR222 for ACDET setting) PC223 2200p is for quick response when AC plug out For hybrid design, need double check PQ202,PQ203,PQ204,PQ205 component rating #Protect function ACOVP : ACDET voltage > 3.14V Charger timeout : No communication within 175s(default) ACOC : 3.33 X Input current DAC setting(default) CHGOCP : 3/4.5/6A based on current current setting BATOVP : 103-106% BATLOWV : 2.5V TSHUT : 155C IFAULT HI : 750mV (default) IFAULT LOW : 110mV (default) Close EC chip SB301150200 >X1 SB000011K00 LMUN5236T1G NPN SOT323-3 SB00000RM00 LTC015EUBFS8TL_UMT3F Vin Dectector L >H H >L Min 17.16V 16.76V Typ 17.63V 17.22V Max 18.12V 17.70V VILIM = 20*ILIM*Rsr ILIM = 3.3*100/(100+107)/20/0.02 = 3.986 A 4 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2015/1/15 Deciphered Date 2017/10/09 Title CHARGER THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Rev 2.0 LA-C482P Date: A B C Sheet D 34 of 43 B C EN1 and EN2 dont't floating PU401 SY8286BRAC_QFN20_3X3 PL402 2.2UH_PCMB061H-2R2MS_6A_20% LX_3V PC412 PR406 1000P_0402_25V8J 1K_0402_5% 2 3V_FB @ PC409 22U_0603_6.3V6M PC408 22U_0603_6.3V6M 1 PC407 22U_0603_6.3V6M 13V_SN @EMI@ 3.3V LDO 150mA~300mA SPOK PC411 NC 21 PC410 4.7U_0603_6.3V6M 15 PR404 +3VLP 16 4.7_1206_5% @EMI@ 17 GND ENLDO_3V5V +3VALWP 19 18 NC 20 LDO NC 11 7*7*1.8 DCR=31~35m ohm SH00000A900 680P_0603_50V7K GND PG PR405 100K_0402_5% +19VB PC401 BS IN GND EN2 LX OUT 10 GND 14 +3VALWP LX FF PR402 499K_0402_1% 0.1U_0603_25V7K LX 13 IN LX_3V IN IN EN1 @ PR401 0_0603_5% BST_3V 12 @ PJ403 JUMP_43X39 +19VB_3V PC405 10U_0805_25V6K @EMI@ PC403 0.1U_0402_25V6 +19VB EMI@ PC404 2200P_0402_50V7K @EMI@ PL401 HCB2012KF-121T50_0805 D PR403 150K_0402_1% ENLDO_3V5V PC406 22U_0603_6.3V6M A Vout is 3.234V~3.366V 3V_EN +3VALWP @ PJ401 JUMP_43X79 2 +3VALW @ PJ402 +5VALWP 2 +5VALW JUMP_43X118 +19VB +19VB_5V BS PL404 2.2UH_PCMB061H-2R2MS_6A_20% LX_5V PC427 1000P_0402_25V8J 5V_FB PC424 22U_0603_6.3V6M PC423 22U_0603_6.3V6M PC422 22U_0603_6.3V6M PC421 22U_0603_6.3V6M 1 PC426 15V_SN VL 5V LDO 150mA~300mA PC420 22U_0603_6.3V6M 21 16 PR408 17 4.7U_0603_6.3V6M PC419 22U_0603_6.3V6M @ PC418 @EMI@ PC425 4.7U_0603_6.3V6M 15 14 13 12 +5VALWP 18 4.7_1206_5% NC GND 19 680P_0603_50V7K 7*7*1.8 DCR=31~35m ohm SH00000A900 (2.2uH) 20 EN2 5V_EN 1 VCC ENLDO_3V5V 2 Vout is 4.998V~5.202V PR412 1K_0402_5% PC428 4.7U_0402_6.3V6M PR413 1M_0402_1% IN PG 5V_EN IN GND EC_ON MAINPWON SPOK GND 11 PR409 @ 0_0402_5% PR410 2.2K_0402_5% @ PR411 0_0402_5% LX NC PC413 @EMI@ 10 LX GND LDO @ PR407 0_0603_5% BST_5V 0.1U_0603_25V7K LX OUT EN1 IN IN LX_5V 1SPOK_R @EMI@ PC417 0.1U_0402_25V6 EMI@ PC416 2200P_0402_50V7K PC414 10U_0805_25V6K @ PJ404 JUMP_43X79 2 SY8286CRAC_QFN20_3X3 PU402 FF @EMI@ PL403 HCB2012KF-121T50_0805 4 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2015/1/15 Deciphered Date 2017/10/09 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title 3VALW/5VALW Size C Document Number B C Rev 2.0 LA-C482P Date: A Sheet D 35 of 43 @EMI@ PL501 5A_Z120_25M_0805_2P +0.6VSP UG_DDR PR508 470K_0402_1% +19VB_DDR @ PJ502 1 2 20 SYSON VLDOIN BOOT VTT FB +1.2VP FB_DDR PR501 0_0402_5% +0.6VS_VTT PC517 0.033U_0402_16V7K PR507 6.19K_0402_1% +1.2VP PR509 10K_0402_1% JUMP_43X39 C 19 PR506 5.1_0603_5% S3 VTTREF_DDR VDDQ S5 VDD JUMP_43X118 +0.6VSP 17 PHASE +1.2V_VDDQ VTTREF GND @ PC501 0.1U_0402_10V7K 1 @ PJ501 VDDP +5VALW PC518 1U_0402_6.3V6K 11 VDD_DDR PU501 RT8207PGQW _W QFN20_3X3 CS +5VALW PR505 5.1_0603_5% VTTSNS 10 @EMI@ PC515 680P_0402_50V7K 21 PAD VTTGND PGND EN_0.675VSP 14 PR504 7.32K_0402_1% 13 CS_DDR PC516 1U_0402_6.3V6K VDDP_DDR 12 1SNB_DDR 2 C 18 16 @EMI@ PR503 4.7_1206_5% LGATE PGOOD LG_DDR 15 PC514 22U_0603_6.3V6M PC513 22U_0603_6.3V6M PC512 22U_0603_6.3V6M PC511 22U_0603_6.3V6M PC510 22U_0603_6.3V6M PC509 22U_0603_6.3V6M 1 +1.2VP LX_DDR PL502 1UH_PCMB061H-1R0MS_7A_20% PC508 10U_0603_6.3V6M LG_DDR PC507 10U_0603_6.3V6M UGATE 7*7*1.8 DCR=14.5~17m ohm SH00000AA00 G2 +1.2VP TON G1 S2 BST_DDR D1 S2 UG_DDR1 D1 S2 EN_DDR D1 PC506 PR502 0.1U_0603_25V7K 2.2_0603_5% BST_DDR_R TON_DDR D2/S1 D1 10 D PQ501 AON7934_DFN3X3A8-10 PC505 10U_0805_25V6K PC504 10U_0805_25V6K @EMI@ PC503 2200P_0402_50V7K D +1.2VP +19VB_DDR @ PJ503 JUMP_43X79 2 @EMI@ PC502 0.1U_0402_25V6 +19VB Switching Frequency:540kHz Iocp : 7.16A OVP : 113%~120% B @ SUSP# SM_PG_CTRL B PR511 0_0402_5% +0.6VS_VTT TDC 0.7A Peak Current 1A PR510 0_0402_5% 2 @ PC519 0.1U_0402_10V7K A A Compal Secret Data Security Classification Issued Date 2015/1/15 Deciphered Date 2017/10/09 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title 1.2V/0.6VS Size Document Number Custom Date: Compal Electronics, Inc Rev 2.0 LA-C482P Wednesday, February 24, 2016 Sheet 36 of 43 Module model information SYX196D_V3.mdd EN pin don't floating If have pull down resistor at HW side, pls delete PR702 +19VB_1VALW 11 EN_1VALW 13 ILMT_1VALW 0_0402_5% 15 +3VALW EN NC ILMT NC BYP NC PAD 10 12 PC612 2.2U_0402_6.3V6M FB = 0.6V 2 @ PC616 22U_0603_6.3V6M @ PC615 22U_0603_6.3V6M 1 1 PC611 22U_0603_6.3V6M Rup LDO_3V PC610 22U_0603_6.3V6M FB_1VALW @ PR607 16 Rdown 21 20K_0402_1% SY8288RAC_QFN20_3X3 The current limit is set to 6A, 8A or 12A when this pin is pull low, floating or pull high 14 17 VCC +1.0VALWP PC609 22U_0603_6.3V6M GND 5*5*1.8 DCR=15~17m ohm SH000014Y00 20 +1.0V_PRIM PL602 1UH_PCMB051H-1R0MS_8A_20% 2 FB +1.0VALWP PC608 22U_0603_6.3V6M LX GND LX_1VALW 19 GND PC601 0.1U_0603_25V7K BST_1VALW_R LX @ PR601 0_0603_5% PC607 22U_0603_6.3V6M @ PR606 change PL601 SM01000C000 to comm part SM01000P200 LX IN BST_1VALW 18 IN PC606 330P_0402_50V7K BS PG IN PR605 14.3K_0402_1% IN @ PJ601 JUMP_43X79 2 0_0402_5% ILMT_1VALW @ PR604 PC605 10U_0805_25V6K 1 LDO_3V PU601 +19VB_1VALW @EMI@ PC604 0.1U_0402_25V6 @ PJ602 JUMP_43X79 2 @EMI@ PC602 680P_0603_50V7K SNUB_1VALW @EMI@ PL601 HCB2012KF-121T50_0805 EMI@ PC603 2200P_0402_50V7K +19VB D @EMI@ PR603 4.7_1206_5% 2 D Pin BYP is for CS Common NB can delete PC613 1U_0402_6.3V6K +3VALW and PC15 Vout=0.6V* (1+Rup/Rdown) =0.6*(1+(13.7/20)) Vout=1.011V C @ PR608 0_0402_5% PR609 10K_0402_1% +1.8VALW_PG C @ 1 EN_1VALW +3VALW @ PC614 PR610 0.22U_0402_10V6K 1M_0402_1% B B A A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2015/1/15 Deciphered Date 2017/10/09 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title 1.0V_PRIM Size Rev 2.0 LA-C482P Date: Document Number Wednesday, February 24, 2016 Sheet 37 of 43 A B C D +3VALW Note: When design Vin=5V, please stuff snubber to prevent Vin damage 1 +3VALW PC701 1U_0402_6.3V6K 2 PJ701 JUMP_43X39 @ PJ702 VIN_1.5VS Current limit = 4.7A(min) 0.4% continuous 0.5A Ipeak= 0.75A FB_1.5VS +1.5VSP Rup G971ADJF11U_SO8 @ PC703 0.1U_0402_16V7K VO ADJ PC704 0.01U_0402_25V7K VEN PR701 1M_0402_5% @ PR710 0_0402_5% GND EN_1.5VS SUSP# +1.5VS VO 2 VIN_1.5VS TPAD PR702 1K_0402_1% POK VIN JUMP_43X39 @ VPP 4.7U_0603_6.3V6K PU701 PC702 VIN_1.5VS 1 +1.5VSP PC705 22U_0603_6.3V6M PR703 1.13K_0402_1% Rdown @EMI@ PR704 @EMI@ PC706 4.7_0603_5% 680P_0402_50V7K 2SNB_1.8V 2 PU702 SY8032ABC_SOT23-6 PJ703 JUMP_43X39 +3VALW @ PR705 100K_0402_5% IN LX PG GND FB EN LX_1.8V +1.8VALW_PG PR707 0_0402_5% EN_1.8V FB_1.8V PJ704 +1.8VALWP 2 +1.8V_PRIM JUMP_43X39 @ continuous 0.3A Ipeak= 0.4A PR709 10K_0402_1% @ PC711 0.1U_0402_16V7K PR708 1M_0402_1% SPOK +1.8VALWP PC710 22U_0603_6.3V6M PC709 22U_0603_6.3V6M 2 1 2.5*2*1.2 DCR=45~59m ohm SH00001100S00 common part PR706 20K_0402_1% +3VALW PL701 1UH_2.3A_+-20% PC708 68P_0402_50V8J PC707 22U_0603_6.3V6M 2 3 4 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2015/1/15 Deciphered Date 2017/10/09 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title 1.8V_PRIM / 1.8V_MEM Size B C Rev 2.0 LA-C482P Date: A Document Number W ednesday, February 24, 2016 D Sheet 38 of 43 PC8102 8200P_0402_25VX7R 1 2 PR8105 19.6K_0402_1% 2 PC8133 1000P_0402_50V7K 1 10K_0402_1% PR8161 PR8127 110_0402_1% PC8120 4700P_0402_16V7K PC8121 1000P_0402_50V7K PC8114 1U_0402_16V7K C SW_1a 15K_0402_1% place close to L1 PH804 Common part SL200002H00 PH804 100K_0402_1%_NCP15WF104F03RC 110_0402_1% 100_0402_1% PR8126 45.3_0402_1% PC8129 15P_0402_50V8J VSSSENSE PC8130 1000P_0402_50V7K @ PR8153 0_0402_5% 2 @ PR8156 0_0402_5% VCCSENSE PR8155 100_0402_1% PR8147 100_0402_1% 2 PR8143 8.66K_0402_1% @ PR8146 0_0402_5% 2 1 PR8154 576_0402_1% PR8160 15.8K_0402_1% 15.8K_0402_1% 1 PC8132 1000P_0402_50V7K PR8159 90.9K_0402_1% PR8137 PC8128 1500P_0402_50V7K PR8145 499_0402_1% VSP_1a PR8158 48.7K_0402_1% PC8119 470P_0402_50V7K 2 VSN_1a PR8152 576_0402_1% Load line@GT= 3.1m RPH@GT=280K ->PR8130 Load line= (RCS2+(RCS1*Rth/(RCS1+Rth))) *IOUTTOTAL * DCR/RPH=92.95?? SOC_SVID_CLK SOC_SVID_ALERT#_R SOC_SVID_DAT 100_0402_1% NCP81208-MNTXG_QFN48_6X6 PC81272200P_0402_50V7K PWM_1a Iout@GT= 31A RIOUT@GT=26.1K ->PR8122 RIOUT= 2* RLIM /(10 *IOUTICCMAX * Load line) =25K?? @ PR8132 CSN_1a PC8131 1U_0603_10V6K Iccmax@GT=31A RICCMAX2PH=48.7 >PR8158 RIccMAX2ph= (IccMAX2Ph+32)*200K ohm/ 127 =100K?? PR8128 8.25K_0603_1% VR_HOT# PU8101 36 35 34 33 32 31 30 29 28 27 26 25 PR8125 PWM_1b DRVON SCLK ALERT# SDIO VR_HOT# IOUT_1a CSP_1a CSN_1a ILIM_1a COMP_1a VSN_1a PR8124 49 IOUT_2ph DIFFOUT_2ph FB_2ph COMP_2ph ILIM_2ph CSCOMP_2ph CSSUM_2ph CSREF_2ph CSP2_2ph CSP1_2ph TSENSE_2ph VRMP PR8129 49.9_0402_1% @ PR8134 0_0402_5% SCLK PR8136 ALERT# 10_0402_1% SDIO PR8138 VSN_2ph VSP_2ph PSYS VSP_1b VSN_1b COMP_1b ILIM_1b CSN_1b CSP_1b IOUT_1b VR_RDY EN 48 47 46 45 44 43 42 41 40 39 38 37 DRVON close to the longer distance phase(81208 or 81210) Alert,Data,Clk VR_ON PWM_1b PC8125 1000P_0402_50V7K PR8148 2.49K_0402_1% +VCC_CORE Imax=21A Ipeak=29A Iocp=35A LL=2.4mV/A RDRPSP@VCORE=590?? ->PR8152 RDRPSP= Load line*(RPHSP+Rth+RCSSP) /(gm * DCR) /(Rth+RCSSP) PH801 Common part SL200002H00 PH801 100K_0402_1%_NCP15WF104F03RC PR8163 2_0402_1% PR8115 10K_0402_1% 2 PR8157 61.9K_0402_1% +5VALW +3VS SW_1b +5VS Rlim=Ioutlimit*Loadline/10 -> PR8135=12.4K B 2 PC8124 1000P_0402_50V7K @ PR8149 2_0402_1% TAB PR8141 1K_0402_1% 1 +19VB 10 11 12 Load line@SA= 10.3m RDRPSP@SA=1.5K?? ->PR8104 RDRPSP= Load line*(RPHSP+Rth+RCSSP) /(gm * DCR) /(Rth+RCSSP) VR_PWRGD @ PR8120 0_0402_5% PR8150 33.2K_0402_1% 100℃ place close to U2 PH805 Common part SL200002H00 PR8112 8.25K_0603_1% D +1.0V_VCCST VCC ROSC_COREGT RSOC_SAUS PWM1_2ph PWM2_2ph ICCMAX_2ph ICCMAX_1a ICCMAX_1b ADDR_VBOOT PWM_1a TSENSE_1ph VSP_1a 2 0_0402_5% @ PR8140 PR8142 61.9K_0402_1% OCP@GT Imax=18A Ipeak=31A Iocp=40A LL=3.1mV/A PR8144 2.26K_0402_1% 1 PC8123 0.022U_0402_16V7K PC8116 2200P_0402_25V7K 0_0402_5% PH805 100K_0402_1%_NCP15WF104F03RC SWN_GT1 2 1 +5VS @ PR8139 PC8122 0.33U_0402_10V6K PR8135 12.4K_0402_1% CSN_GT1 @ PC8118 1000P_0402_50V7K 1 PR8131 75K_0402_1% PC8117 330P_0402_50V7K PR8133 165K_0402_1% 2 PR8130 309K_0603_1% PR8123 4.75K_0402_1% Rcs1 SWN_GT1 1 PC8115 15P_0402_50V8J Rcs2 PC8112 680P_0402_50V7K PH803 THERM_ 220K 5% 0402 C VSN_2ph IOUTSP@SA= 5A RIOUTSP@SA=69.8K ?? ->PR8114 RIOUTSP= 2V/(gm*(Rth+RCSSP)*ICCMAX*DCR /(RPHSP+Rth+RCSSP)) OCP@SA= 9.5A RLIMSP@SA=19.6K?? ->PR8105 RLIMSP= 1.3V/(gm*(Rth+RCSSP)*IoutLIMIT*DCR /(RPHSP+Rth+RCSSP)) PC8110 470P_0402_50V7K PC8111 1000P_0402_50V7K place PH803 close Common part to L2 SL200002I00 Rth RIccMAX@SA= 15.8K ->PR8160 RIccMAX@SA= IccMAX*2V/10uA/64A PH802 Common part SL200002H00 place close to L4 0_0402_5% @ PR8116 PR8119 49.9_0402_1% PR8122 24K_0402_1% PR8118 100_0402_1% PR8121 499_0402_1% GT Imax=18A Ipeak=31A Iocp=40A LL=3.1mV/A PR8109 15K_0402_1% PR8114 54.9K_0402_1% PC8109 PR8117 1000P_0402_50V7K 1K_0402_1% VSNN_2ph @ VSP_2ph Imax=4A Ipeak=4.5A Iocp=9.5A LL=10.3mV/A IccMAX@SA= 5A CSN_1b PH802 100K_0402_1%_NCP15WF104F03RC PR8111 20K_0402_1% 0_0402_5% VSSGT_SENSE PC8108 2200P_0402_50V7K 13 14 15 16 17 18 19 20 21 22 23 24 @ PR8162 PR8151 24K_0402_1% 2 100_0402_1% VCCGT_SENSE PR8106499_0402_1% VSN_1b VSNN_1b PR8110 +VCC_GT 0_0402_5% @ PR8113 PC8113 470P_0402_50V7K 100_0402_1% 1 PR8108 PC8126 0.01U_0402_50V7K VSSSA_SENSE VSPP_1b VCCSA_SENSE PR8104 1.43K_0402_1% VSP_1b @ PR8103 0_0402_5% PC8105 1000P_0402_50V7K 100_0402_1% 2 PR8102 +VCC_SA VCORE Imax=21A Ipeak=29A Iocp=35A LL=2.4mV/A PC8103 15P_0402_50V8J PC8104 1000P_0402_50V7K PC8101 1000P_0402_50V7K VCCSA Imax=4A Ipeak=4.5A Iocp=9.5A LL=10.3mV/A PR8101 1.5K_0402_1% 2 D PC8106 0.01U_0402_25VX7R PC8107 4700P_0402_25V7K B IccMAX@VCORE= 28A RIccMAX@VCORE= 90.9K??(應應應87.6K) ->PR8159 RIccMAX@VCORE= IccMAX*2V/10uA/64A place close to U1 ADDR_VBOOT 10K VCC:0V VCCGT:0V VCCSA:1.05V IOUTSP@VCORE= 28A RIOUTSP@VCORE=17.8K?? ->PR8137 RIOUTSP= 2V/(gm*(Rth+RCSSP)*ICCMAX*DCR /(RPHSP+Rth+RCSSP)) OCP@VCORE= 35A RLIMSP@VCORE=8.66K?? ->PR8143 RLIMSP= 1.3V/(gm*(Rth+RCSSP)*IoutLIMIT*DCR /(RPHSP+Rth+RCSSP)) PWM1_2ph A A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2015/1/15 Deciphered Date 2017/10/09 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title CPU Power rail Size Rev 2.0 LA-C482P Date: Document Number Wednesday, February 24, 2016 Sheet 39 of 43 @ PJ8201 JUMP_43X79 2 A +19VB A +19VB_CPU @EMI@ PL8202 5A_Z120_25M_0805_2P @EMI@ PC8205 2200P_0402_50V7K 0.22UH_PCMB061H-R22MS4R305_14A_20% GT Imax=18A Ipeak=31A Iocp=40A LL=3.1mV/A CSN_1a VCCSA Imax=4A Ipeak=4.5A Iocp=9.5A LL=10.3mV/A Choke Size：7*7*1.8 DCR=4.3m ohm +-5% SH000012200 D1 +19VB_CPU 2 @EMI@ PC8222 2200P_0402_50V7K 1 @EMI@ PC8221 0.1U_0402_25V6 2 PC8220 4.7U_0603_25V6K PC8219 4.7U_0603_25V6K PC8215 10U_0805_25V6K PC8214 10U_0805_25V6K @EMI@ PC8213 2200P_0402_50V7K 1 S2 LG_GT + PC8216 33U_D2_25VM_R60M +VCC_GT PL8204 SW_GT D2/S1 PC8218 4.7U_0603_6.3V6K PQ8201 AON6992_DFN5X6D-8-7 B G1 SW_GT S2 GND DRVL UG_GT 1 VCC SW EN DRVH S2 +5VS PWM G2 DRVON PWM1_2ph PC8228 4.7U_0603_25V6K PR8201 PC8211 2.2_0603_5% 0.22U_0603_16V7K 2 PU8202 NCP81151MNTBG_DFN8_2X2 BST FLAG PR8206 PC8223 2.2_0603_5% 0.22U_0603_16V7K 2 @ PJ8202 JUMP_43X79 2 +19VB_GT AON6992 L/S Rds(on)=2.5mΩ (max) C +19VB @EMI@ PR8205 4.7_1206_5% B @EMI@ PC8210 680P_0603_50V7K SW_1a @EMI@ PC8201 680P_0603_50V7K @EMI@ PR8203 4.7_1206_5% S2 S2 PC8209 4.7U_0603_6.3V6K VCORE Imax=21A Ipeak=29A Iocp=35A LL=2.4mV/A PC8227 4.7U_0603_25V6K D1 G1 LG_VCORE PC8226 33U_D2_25VM_R60M PL8203 S2 + +VCC_CORE LX_VCORE D2/S1 DRVL VCC LX_VCORE PAD GND PQ8202 AON6992_DFN5X6D-8-7 G2 SW EN +5VS DRVH PWM DRVON UG_VCORE BST PWM_1a PU8201 NCP81253MNTBG_DFN8_2X2 @EMI@ PC8204 0.1U_0402_25V6 PR8202 PC8202 2.2_0603_5% 0.22U_0603_16V7K 2 PC8208 10U_0805_25V6K PC8203 10U_0805_25V6K H=1.9 0.22UH_PCMB061H-R22MS4R305_14A_20% CSN_GT1 PR8204 10_0402_1% SWN_GT1 Choke Size：7*7*1.8 DCR=4.3m ohm +-5% SH000012200 C AON6992 L/S Rds(on)=2.5mΩ (max) G1 G2 S2 SW_SA PC8224 4.7U_0603_6.3V6K D LG_SA AON7934 L/S Rds(on)=11.6mΩ (max) @EMI@ PR8207 4.7_1206_5% D2/S1 SW_SA @EMI@ PC8225 680P_0603_50V7K D1 D1 D1 PL8205 0.47U_PCMB061H-R47MS_11A_20% S2 GND DRVL VCC S2 SW EN 10 PQ8203 AON7934_DFN3X3A8-10 +5VS PWM DRVH DRVON BST PAD PWM_1b D1 PU8203 NCP81253MNTBG_DFN8_2X2 HG_SA +VCC_SA CSN_1b D SW_1b Choke Size：7*7*1.8 DCR=7.3 ~8.4mohm SH00000PX00 (0.47uH) Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2015/1/15 Deciphered Date 2017/10/09 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title CPU Poer Stages Size Rev 2.0 LA-C482P Date: Document Number Wednesday, February 24, 2016 Sheet 40 of 43 A @ 2 @ 2 2 @ 2 2 2 2 2 @ @ +VCC_SA @ PC9187 1U_0402_6.3V6K @ +VCC_SA PC9174 1U_0402_6.3V6K PC9173 1U_0402_6.3V6K PC9172 1U_0402_6.3V6K PC9171 1U_0402_6.3V6K PC9170 0.47U_0402_6.3V6K PC9169 0.47U_0402_6.3V6K PC9168 1U_0402_6.3V6K PC9167 1U_0402_6.3V6K PC9166 1U_0402_6.3V6K PC9165 1U_0402_6.3V6K 2 PC9164 22U_0603_6.3V6M PC9163 22U_0603_6.3V6M +VCC_GT PC9162 22U_0603_6.3V6M PC9186 0.47U_0402_6.3V6K PC9161 22U_0603_6.3V6M PC9151 22U_0603_6.3V6M PC9152 22U_0603_6.3V6M PC9153 22U_0603_6.3V6M PC9154 22U_0603_6.3V6M PC9139 22U_0603_6.3V6M PC9140 22U_0603_6.3V6M PC9141 22U_0603_6.3V6M PC9142 22U_0603_6.3V6M PC9143 22U_0603_6.3V6M PC9144 22U_0603_6.3V6M PC9145 22U_0603_6.3V6M PC9146 22U_0603_6.3V6M PC9185 22U_0603_6.3V6M PC9160 22U_0603_6.3V6M PC9184 22U_0603_6.3V6M PC9159 22U_0603_6.3V6M PC9150 22U_0603_6.3V6M PC9138 22U_0603_6.3V6M @ PC9197 22U_0603_6.3V6M PC9183 22U_0603_6.3V6M 1 PC9196 22U_0603_6.3V6M PC9182 22U_0603_6.3V6M 2 PC9195 22U_0603_6.3V6M PC9181 22U_0603_6.3V6M PC9194 22U_0603_6.3V6M PC9180 22U_0603_6.3V6M 1 PC9220 1U_0402_6.3V6K 2 PC9219 1U_0402_6.3V6K 2 1 PC9123 22U_0603_6.3V6M PC9124 22U_0603_6.3V6M PC9125 22U_0603_6.3V6M PC9126 22U_0603_6.3V6M PC9127 22U_0603_6.3V6M PC9128 22U_0603_6.3V6M PC9129 22U_0603_6.3V6M PC9130 22U_0603_6.3V6M PC9136 1U_0402_6.3V6K PC9135 1U_0402_6.3V6K PC9134 1U_0402_6.3V6K PC9133 1U_0402_6.3V6K PC9132 1U_0402_6.3V6K 2 PC9131 22U_0603_6.3V6M PC9218 1U_0402_6.3V6K 2 @ PC9217 1U_0402_6.3V6K 1 2 1 PC9103 22U_0603_6.3V6M PC9104 22U_0603_6.3V6M PC9105 22U_0603_6.3V6M PC9106 22U_0603_6.3V6M PC9107 22U_0603_6.3V6M PC9108 22U_0603_6.3V6M PC9109 22U_0603_6.3V6M PC9110 22U_0603_6.3V6M PC9121 1U_0402_6.3V6K PC9120 1U_0402_6.3V6K PC9119 1U_0402_6.3V6K PC9118 1U_0402_6.3V6K PC9117 1U_0402_6.3V6K PC9116 1U_0402_6.3V6K PC9115 1U_0402_6.3V6K PC9114 1U_0402_6.3V6K PC9113 1U_0402_6.3V6K PC9112 1U_0402_6.3V6K 2 PC9111 22U_0603_6.3V6M @ PC9216 1U_0402_6.3V6K @ 1 2 PC9215 1U_0402_6.3V6K 2 2 @ PC9214 1U_0402_6.3V6K 1 1 PC9193 22U_0603_6.3V6M 2 PC9192 22U_0603_6.3V6M PC9158 22U_0603_6.3V6M PC9179 22U_0603_6.3V6M PC9149 22U_0603_6.3V6M @ 2 1 @ 2 2 PC9213 22U_0603_6.3V6M 1 @ PC9212 22U_0603_6.3V6M PC9157 22U_0603_6.3V6M PC9148 22U_0603_6.3V6M @ PC9191 22U_0603_6.3V6M PC9178 22U_0603_6.3V6M 2 PC9211 22U_0603_6.3V6M 2 2 PC9210 22U_0603_6.3V6M 1 1 PC9203 22U_0603_6.3V6M 2 PC9202 22U_0603_6.3V6M 1 PC9201 22U_0603_6.3V6M 2 PC9190 22U_0603_6.3V6M 1 PC9200 22U_0603_6.3V6M PC9156 22U_0603_6.3V6M @ PC9209 22U_0603_6.3V6M 2 PC9208 22U_0603_6.3V6M 1 PC9206 22U_0603_6.3V6M 2 PC9223 22U_0603_6.3V6M 1 +VCC_CORE + +VCC_GT + Issued Date 220U_D2_2V_Y PC9102 22U_0603_6.3V6M PC9175 PC9177 22U_0603_6.3V6M PC9189 22U_0603_6.3V6M PC9199 22U_0603_6.3V6M C PC9122 22U_0603_6.3V6M @ PC9205 22U_0603_6.3V6M PC9137 22U_0603_6.3V6M @ PC9222 22U_0603_6.3V6M PC9147 22U_0603_6.3V6M PC9155 22U_0603_6.3V6M PC9176 22U_0603_6.3V6M PC9188 22U_0603_6.3V6M PC9198 22U_0603_6.3V6M PC9204 22U_0603_6.3V6M PC9221 22U_0603_6.3V6M +VCC_CORE +VCC_CORE Security Classification 2015/1/15 Deciphered Date PC9101 220U_D2_2V_Y H=1.9 D D @ +VCC_GT C H=1.9 B B 330U_D3_2.5VY_R6M >H=1.4 SGA00006A00 A 330U_D2_2V_Y >H=1.9 SGA00009S00 2015/09/15 2015/10/21 VCORE Output Cap： 22U 6.3V X5R 0603 * 38 1U 6.3V X5R 0402 * 15 330U 2.5V D2 ESR6M * VCORE Output Cap： Backside Primary 22U 6.3V X5R 0603 * 13 22U 6.3V X5R 0603 * 16 1U 6.3V X5R 0402 * 15 VCCGT Output Cap： 22U 6.3V X5R 0603 * 36 1U 6.3V X5R 0402 * 12 330U 2.5V D2 ESR6M * VCCGT Output Cap： Primary Backside 22U 6.3V X5R 0603 * 13 22U 6.3V X5R 0603 * 20 220U 2V D2 * 1U 6.3V X5R 0402 * 0.47U 6.3V X5R 0402 * VCCSA Output Cap： 22U 6.3V X5R 0603 * 13 1U 6.3V X5R 0402 * VCCSA Output Cap： Backside Primary 22U 6.3V X5R 0603 * 22U 6.3V X5R 0603 * 1U 6.3V X5R 0402 * Compal Secret Data 2017/10/09 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Compal Electronics, Inc Size Date: Document Number CPU DECOULPING Wednesday, February 24, 2016 LA-C482P Sheet 41 of 43 2.0 Rev Version Change List ( P I R List ) Item Page# B Date Request Owner Issue Description Solution Description change P36 change P37 change 11/19 Jims_Liu avoid material shortage 11/19 Jims_Liu avoid material shortage 11/19 Jims_Liu for power efficient P41 POP 11/19 Jims_Liu for CPU trancient P41 non-POP 11/19 Jims_Liu for CPU trancient P41 change 11/19 Jims_Liu for CPU trancient PC9101 change from SGA00009S00_330uF to SGA20221D40_220uF and SMT P39 non-POP 11/19 Jims_Liu for CPU trancient PR8130 change from SD014280380_280Kohm to SD014309380_309Kohm P39 change 11/19 Jims_Liu for CPU trancient PR8122 change form SD034261280_26.1Kohm to SD034240280_24Kohm P39 change 11/19 Jims_Liu for CPU trancient PR8123 change from SD034523180_5.23Kohm to SD034475180_4.75Kohm 10 11 P39 change 11/19 Jims_Liu for CPU trancient PC8116 change from SE075472K80_4700pF to SE075222K80_2200pF P39 change 11/19 Jims_Liu for CPU trancient PR8114 change from SD034590280_59Kohm to SD00000H880_54.9Kohm 12 P39 change 11/19 Jims_Liu for CPU trancient PC8106 change from SE000000680_8200pF to SE068103K80_0.01uF 13 P39 change 11/19 Jims_Liu for CPU trancient PR8137 change from SD034178280_17.8Kohm to SD034158280_15.8Kohm 14 P39 change 11/19 Jims_Liu for CPU trancient PR8152 change from SD00000CO80_590ohm to SD034576080_576ohm 15 P39 change 16 17 P38 change PR8154 change from SD00000JJ00_665ohm to SD034576080_576ohm 11/19 Jims_Liu for CPU trancient 11/19 Jims_Liu change to common part PL701 change from SH00000XB00 to SH000011S00 P34 change 11/19 Jims_Liu follow HW 2nd source PQ301、PQ308 change from SB000009Q80 to SB00000ST00 18 P39 change 11/24 Jims_Liu Save production time PR8139、PR8120 change from ohm to R_short 19 P37 change 11/24 Jims_Liu for HW require PR605 change from SD034137280_13.7K to SD00000QM80_14.3K 20 P37 change 11/24 Jims_Liu for audio noise PC8219, PC8220 change from SE00000QK00_10uF to SE000013880_4.7uF 21 P38 change 11/25 Jims_Liu for PU701 pull high PR701 change from SD028470280_47Kohm to SD028100480_1Mohm 22 P39 change 11/27 Jims_Liu co-lay add PR8163_SD000005V00 co-lay 5Valw PR8194_SD000005V00 change to unpop 23 P37 change 11/30 Jims_Liu more place for CPU_GT PJ601 change from JUMP_43X118 to JUMP_43X79 24 P35 change 12/08 Jims_Liu for efficiency PL402 change from SH00000LT00_2.2uH_H1.5 to SH00000A900_2.2uH_H1.8 25 P40 change 12/08 Jims_Liu for efficiency PL8205 change from SH000018B00_.47uH_H1.5 to SH00000PX00_.47uH_H1.8 change 01/11 Jims_Liu for EMI request remove unpop PL301(SH00000PB00) & PJ301 change 01/13 Jims_Liu for power debug 26 27 P34 P34 Rev P36 D C Title Page PL502 change SH000015N00 to SH00000AA00 PU501 change SA000096O00 to SA00007IH00 D PL602 change SH00000TV00 to SH000014Y00 22uF (PC9107、PC9131、PC9140、PC9198、PC9199、 PC9200) change unpop to SMT 22uF (PC9190、PC9164、PC9185、PC9111,PC9145, PC9104,PC9108,PC9122,PC9123) change SMT to unpop C B add PJ301 A A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2015/1/15 Deciphered Date 2017/10/09 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title PWR-PIR Size D Document Number Rev 2.0 LA-C482P Date: Wednesday, February 24, 2016 Sheet 42 of 43 Version Change List ( P I R List ) Item Page# D C B A Function Date Request Owner Page 1/3 for HW Issue Description power schematic 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 ALL P.20 ALL P.24,25 P.29 P.23,26 P.23 ALL P.26 P.28 P.26 P.9,11 P.9,11 P.8 P.12 ALL P.23 P.10 P.10 P.10 P.11 P.13 P.14 P.21 P.23 P.8 P.25,28 P.28 P.29 P.30 ALL P.25,28 P.29 P.25 P.25 P.27 ALL P.26 ALL P.25 ALL P.27 P.26 ALL P.14 P.28 ALL PWR HW HW HW HW HW HW HW HW HW HW HW HW HW HW HW HW HW HW HW HW HW HW HW HW HW HW HW HW HW PWR HW HW HW HW HW HW HW PWR HW PWR HW HW HW HW HW HW 9/14 9/14 9/14 9/30 9/30 10/1 10/1 10/1 10/2 10/5 10/5 10/5 10/5 10/7 10/7 10/7 10/7 10/7 10/7 10/7 10/7 10/7 10/7 10/7 10/7 10/7 10/7 10/7 10/7 10/7 10/8 10/8 10/12 10/13 10/13 10/14 10/15 10/15 10/15 10/15 10/15 10/16 10/16 10/19 10/19 10/19 10/19 combine 0914 remove DDR cap Compare connector list USB cap change to B2 remove for assembly change JUMP change to R-short for placemant SATA cap chagne size for placement swap pin for layout routing USB3 re-driver update P/N for new version For KB/B debug update FPC pin define change Project_ID&RAM_ID pin Change USB30 ESD part for ESD request EC schematic checklist for layout request For DFX/EMI request For layout co-lay Remove ME reset pad Add 60.4 PD for XTAL_BIASREF update Crystal P/N Combine net to RPC8 Add Cap for load switch output Non-DS3 sequence Reduce 0ohm part count Change SSD power cap value Combine parts Combine parts modify KB schematic modify FAN schematic Add Cap for load switch output Combine power schematic 1008 Combine parts update screw hole combine USB into ESD diode Change Type-C cap volt (6.3V&16V -> 25V) Add BT_ON on EC pin120 For EMI request update JSB1 pin define Combine power schematic 1015 update Type-C schematic Combine power schematic 1015B update EC pin define for KB backlight update JSB1 pin define remove test point add cap to +3VALW_DSW remove 0ohm Change 0-ohm to R-short for part count 48 49 50 51 ALL ALL P.13 P.14 PWR PWR PWR PWR 10/19 10/20 10/21 10/21 Combine power schematic 1019 Combine power schematic 1020 BOM update BOM update Solution Description schematic 0914 Rev combine power remove CD150,CD151 Compare connector list CS12,CS25 chagne to SGA00009M00 Remove SW3,SW4 J1,J17 change to RM2,RA2 CM7,CM8,CM9,CM10 change from 0402 to 0201 Swap LY1,LY2,LY3 LY4 ,LS5,LS4,LS12,RPC5 US5 change from SA00005OR00 to SA00005OR30 Add RK15,RK16 update JSB1 pin define pin_U1-4 for RAM_ID , pin_P1-4 for Project_ID Add DS5,DS6,DS8,DS10 RPC1 chagne from 1k to 2.2k Swap RPC9,RPC10 Change LX2,LS4-LS12 from 0805 to 0504 Add RM16,RM17 Remove CC119,CLRP3 Reserve RC158 update YC1,YC2 Combine DGPU_PWR_EN to RPC8 Add CC51 Pop RC135 ; unpop RC137 Remove RX2,RX7 CM5 change from 4.7uF to 10uF QC1 change to SB00000DH00 QG1,QS2 change to SB00000S700 (SOT323) RK14 change to 1K , remove RK12,RK13 Remove RF3 Add CC53,CC55 Combine power schematic 1008 QG1,QS2 change to SB00000ST00 H24,H25,H26 change to PTH delete DS7,DS9 , USB into DS5,DS6,DS8,DS10 Change CS26,CS29 to 25V Add BT_ON on EC pin120 Remove CC10,CG2,CS8,LY1,LY2,LY3,LY4 USB_OC0# change to BT_ON Combine power schematic 1015 Remove CS26 , update JUSB2 pin define Combine power schematic 1015B pin27 pin72 delete one GND pin , add +3VS_WLAN CFG10-15,T30,T6 Add CC86 remove RK10 RM11,RC122,RC124,RS12,RQ1,RQ2,RC49,RC81,RC83,RC111,RC115, RC113,RC114,RC125,RC127,RC128,RC131,RC132,RC134,RC136,RC144, RC145,RC118,RC119,RC123,RC126,RC133 Combine power schematic 1019 Combine power schematic 1020 pop RC112 , unpop UC8,CC49,CC43,CC45 pop RC129 , unpop RC130 Compal Electronics, Inc Compal Secret Data Security Classification Issued Date 2015/10/21 2016/06/21 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC HW P.I.R (1/3) Rev 2.0 B3ZMS LA-D591P Date: Wednesday, February 24, 2016 Sheet 43 of 45 D C B A Item Page# D C B A 52 53 54 55 56 57 58 59 60 61 62 63 10/21 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 Function Date ALL P.10 P.13 P.21 P.28 P.8,9 P.11,18,19 P.3 P.27 ALL P.11,12 P.25 A gerber P.7 P.26 P.28 P.25 P.25 P.26 P.26 P.26 P.26 P.25 P.8,28 P.25 P.11 P.6 ALL PWR HW HW HW HW HW HW HW HW HW HW HW 10/21 HW HW HW HW HW HW HW HW HW HW HW HW HW HW HW 10/22 10/22 10/22 10/22 10/22 10/22 10/22 10/22 10/22 10/23 10/23 10/23 A gerber 11/11 11/11 11/11 11/11 11/12 11/16 11/16 11/16 11/17 11/17 11/17 11/17 11/17 11/17 11/18 P.26 P.28 P.27 P.27 P.27 P.7 P.8 P.9,26 P.30 P.13 ALL P.26 P.26 ALL P.6 P.26 P.6 P.26 ALL P.10 P.26 P.29 P.27 P.28 HW HW HW HW HW HW HW HW HW HW HW HW HW PWR HW HW HW HW PWR HW HW HW HW HW 11/18 11/18 11/18 11/18 11/18 11/19 11/19 11/19 11/19 11/19 11/19 11/25 11/26 11/26 11/26 11/26 11/26 11/27 11/30 12/1 12/2 12/2 12/2 12/2 Version Change List ( P I R List Owner ) Request Issue Page 2/3 for HW Solution Description schematic 1021C Description power schematic Rev combine 1021C combine power part count unpop RC85 power source cap added pop CC45,CC49 use USB interface touchscreen unpop RX10,RX11 LED interface update pop RG5 ; unpop RG6,QG1 update BOM config RC31 -> LPC@ , RC32 -> TPM@ , RC54 -> EMC@ update BOM config -> X76@ UV1-4,RC150-157 update BOM config -> CPU QJ8Q@,SR2EU@,SR2EY@,QJKK@ update Board ID RB6 change to 0ohm 2.2uF change Part Number to SD000008880 CC54,CC60,CD28,CD53,CD51,CD22,CD48,CD37,CD46,CD24,CD44,CD42 Part count reduce unpop RC50,RC51,RC92,RC93,CC24,CC25,CC26,CC27,CC28,CC29,CC30,CC31 Part count reduce unpop CS19,CW6,CC109,CC110 10/21 A gerber 10/21 A gerber 10/21 A gerber 10/21 A gerber UC2 X1 code UC2 change from SA00005U600 to SA00007UR00 US5 change symbol to TI (small thermal pad) US5 change symbol to TI (small thermal pad) LED pin error swap LED1,LED2 Type-C schematic update for CC_UFP# QS2 change from singal-N to dual-N Type-C schematic update for VCC CS29 change from 10uF to 0.1uF move U3 redriver to S/B remove US5 from M/B Change BTB CONN for cost JSB1 vendor change to ENTERY WLAN_PME# PU at M/B side RM6 desgin in M/B side update JSB1 pin define reduce +5VALW*1 , add +VDDA*1 Combine BOM DS12 change to SCA00002M00 (same as S/B) Remove TPM schematic Remove TPM schematic update Type-C schematic Replace RS36 by J17 ; unpop QS1,QS2,RS34,RS56 remove SCI Pull-up Remove RPC8 pin1 SOC_OCC# connect to GND SOC_OCC# connect to GND part count reduce RC129,RB17,RC112,RA11,RA12,RC35,RS30,RS31,RS32,RG3,RG11,RC84, RC104,RC106,RX4,RC140,RS22,RS23,RF1,RC110,RC135,RX12,RX13 part count reduce RA13 remove unpop test power button unpop SW1 Board ID update RB6 change from 0-ohm to 12KOhm update EC GPIO table KBL_EN change from pin27 to pin25 update EC GPIO table remove EC_LID_OUT# change net[SM_PG_CTRL] PU power RC25 PU change from +3VALW to +3VS part count reduce unpop RC26,RC27,RC30 remove PCH DMIC signal remove RA7,RA8,net[PCH_DMIC_CLK],net[PCH_DMIC_DATA] change to correct location by naming rule CC53,CC55 change to CQ5,CQ6 combine parts -> 0.1uF 0201 CC46 change from 0402 to 0201 combine parts -> 10uF 0603 CC106,CS19,CS20,CS37 Use dual U3 re-driver for U3 issue US5 group on M/B Add AC cap between 1st 8713 & 2nd 8713 Add CS33,CS34 Combine power schematic Combine power schematic Intel Debug RC6,RC7,RC8,RC19 change t DCI@ (unpop) update JSB1 pin define for EMI request pin8 pin60 reserve PU +3VS for EC_SCI# (for kabylake?) Reserve RC159 Vendor recomment : update REXT PD value RS53 change from 3.83k-ohm to 4.99k-ohm Combine power schematic Combine power schematic 1130 Add PD for PLT_RST_BUF# Add RC53 Remove U3 re-driver Remove US5 group Add PU for Thermal sensor SMBus Add RPF1 , remove RF5 Add BOM config for ENE request (PLT_RST# PD) RB5 100K for LPC@ , 47K for ESPI@ remove debug KB pin remove RK15,RK16 D C B A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2015/10/21 2016/06/21 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC HW P.I.R (2/3) Rev 2.0 B3ZMS LA-D591P Date: Wednesday, February 24, 2016 Sheet 44 of 45 Item Page# D C 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 Function P.13 ALL P.26 P.14 P.29 P.28 ALL P.13 P.28 P.3 P.27 P.29 P.27 P.29 P.28 P.28 P.28 P.29 P.27 HW PWR HW HW HW HW PWR HW HW HW HW HW HW HW HW HW HW HW HW Date Version Change List ( P I R List Owner ) Request Issue Page 2/3 for HW Description switch CT value 12/3 12/8 12/31 12/31 1/5 1/11 1/13 1/13 1/18 1/19 1/19 2/15 2/15 2/17 2/18 2/19 2/19 2/19 2/19 change load Combine power schematic 1208 Add PME PU on M/B Cost reduce Add POA schematic Change Battery LED power source to +5VALW Combine power schematic 0111 Factory issue LED R-value change Add Kabylake CPU P/N update project ID update screw hole update project ID reserve 0-ohm for FP USB signal Combine Part Number LED value change HDMI/HDCP test result update BOM config update BOM config Solution Description from 10pF to 470pF Rev CC39 change Combine power schematic 1208 Add RM6 unpop UC10,CC112 Add POA schematic unpop RG3 ; pop RG2 Combine power schematic 0111 unpop CC52 RG7->680ohm ; RG8->220ohm Add SA00009QM10,SA00009PJ30 RB6 change from 12K-ohm to 15K-ohm H4 change from 2P8 to 3P2 RB6 change from 15K-ohm to 20K-ohm reserve RK13,RK15 RG8 change from SD034220080 to SD028220080 RG1 1.1k -> 1.6k ; RG4 1.6k -> 1k RY11 change from 4.99k-ohm to 4.75k-ohm RK10 change to FP@ Add RB6=56K for Kabylake D C B B A A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2015/10/21 2016/06/21 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC HW P.I.R (2/3) Rev 2.0 B3ZMS LA-D591P Date: Wednesday, February 24, 2016 Sheet 45 of 45 ... +19VB_CPU 2 @EMI@ PC 822 2 22 00 P _04 02 _ 50V7K 1 @EMI@ PC 822 1 0. 1U _04 02 _ 25V6 2 PC 822 0 4.7U _06 03 _25 V6K PC 821 9 4.7U _06 03 _25 V6K PC 821 5 10U _08 05 _25 V6K PC 821 4 10U _08 05 _25 V6K @EMI@ PC 821 3 22 00 P _04 02 _ 50V7K 1 S2... PWM_1a PU 8 20 1 NCP8 125 3MNTBG_DFN8_2X2 @EMI@ PC 8 20 4 0. 1U _04 02 _ 25V6 PR 8 20 2 PC 8 20 2 2. 2 _06 03_5% 0 .22 U _06 03_16V7K 2 PC 8 20 8 10U _08 05 _25 V6K PC 8 20 3 10U _08 05 _25 V6K H=1.9 0 .22 UH_PCMB061H-R22MS4R 305 _14A _ 20 % CSN_GT1... 1UF * CD55 2. 2U _04 02 _ 6.3V6M 0. 1U_ 02 0 1_10V6K CD75 0. 1U_ 02 0 1_10V6K CD74 0. 1U_ 02 0 1_10V6K CD73 0. 1U_ 02 0 1_10V6K CD 72 0. 1U_ 02 0 1_10V6K CD71 0. 1U_ 02 0 1_10V6K CD 70 0.1U_ 02 0 1_10V6K CD69 0. 1U_ 02 0 1_10V6K CD68