NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.. NEITHER THIS SHEET NOR THE IN
Trang 11 1
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC
SCHEMATIC,A4491 Custom
Thursday, October 30, 2008
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC
SCHEMATIC,A4491 Custom
Thursday, October 30, 2008
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC
SCHEMATIC,A4491 Custom
Thursday, October 30, 2008
Compal Electronics, Inc.
Intel Penryn Processor with Cantiga + DDRII + ICH9M KAL90 M/B Schematics Document
REV:1.0 Compal Confidential
2008-10-30
Trang 21 1
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC
SCHEMATIC,A4491 B
Thursday, October 30, 2008
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC
SCHEMATIC,A4491 B
Thursday, October 30, 2008
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC
SCHEMATIC,A4491 B
Thursday, October 30, 2008
Compal Electronics, Inc.
Power On/Off CKT.
File Name : LA-4491P
Touch Pad
page 37
CRT Conn.
LPC BUS
page 38
Compal Confidential
uFCBGA-1329
page 23
MDC 1.5 Conn
page 39
Int.KBD
page 36
PCI-Express
BANK 0, 1, 2, 3
USB conn x3
667/800/1066MHz
ALC888S-VC
DMI
DC/DC Interface CKT.
Intel Penryn Processor
page 36
3.3V 48MHz
FSB
Clock Generator
ICS9LPRS387
page 35
EC I/O Buffer Fan Control
Power Circuit DC/DC
uPGA-478 Package
page 37
200pin DDRII-SO-DIMM X2
page 44
Intel Cantiga
BIOS
page 4
1.8V DDRII 533/667
page 4,5,6
page 36
HDA Codec
page 16
Memory BUS(DDRII)
BGA-676
HD Audio
page 40
page 7,8,9,10,11,12,13
Intel ICH9-M
Thermal Sensor
page 14,15
page 25,26,27,28
page 36
ENE KB926
Audio AMP
LCD Conn.
Conn
3.3V 24.576MHz/48Mhz
Phone Jack x3
Model Name : KAL90
page 22
Dual Channel
page 39
page 44,45,46,47,48 ,49,50,51 USB/B Conn.
page 24
HDMI Conn.
EMC 1402
FUN Conn.
page 37
CIR
USB port 1
LVDS LVDS
TMDS
C-Link
MINI Card x2
CMOS Camera
WLAN, Robson2
PCI-Express
page 17,18,19,20,21
page 33
USB port 0, 2, 5
USB
(Socket P)
E_KEY/B Conn.
16X
S-ATA
page 08
GMCH HDA
Finger Print
AES1610
RTC CKT.
page 37
page 34
Card Reader
JMB385
page 30
Media/B Conn.
LS-4494P
page 18
VGA HDA
LS-4498P LS-4493P
LS-4492P
LS-4495P
New Card Socket
page 34
LAN(GbE)
ATHEROS AR8121
page 31
RJ45
page 32
port 2
page 34
ESATA Conn.
CDROM Conn.
page 29
port 1 port 0
page 29
SATA HDD Conn.
POWER SW
Page 42
Trang 31 1
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC
SCHEMATIC,A4491 B
Thursday, October 30, 2008
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC
SCHEMATIC,A4491 B
Thursday, October 30, 2008
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC
SCHEMATIC,A4491 B
Thursday, October 30, 2008
Compal Electronics, Inc.
Voltage Rails
VIN
B+
+CPU_CORE
+1.05VS
Adapter power supply (19V)
AC or battery power rail for power circuit.
Core voltage for CPU
1.05V switched power rail
External PCI Devices
Device IDSEL# REQ#/GNT# Interrupts
EC SM Bus1 address
Device
ADI ADT7421
S1 S3 S5
ON OFF
ON OFF
N/A N/A N/A
N/A N/A N/A Power Plane Description
OFF OFF
ON OFF OFF
OFF ON
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
OFF ON
ON
ON ON OFF
ON*
OFF
OFF ON
EC SM Bus2 address Device
Smart Battery
ON
MEDIA CONSOLE
1001 100X b
0001 011X b
1010 000X b
ON OFF OFF
ICH9M SM Bus address
Device
Clock Generator
(ICS9LPRS387, SLG8SP556V)
Address
1101 001Xb
ON ON*
ON OFF OFF
Full ON S1(Power On Suspend) S3 (Suspend to RAM) S4 (Suspend to Disk) S5 (Soft OFF)
ON ON ON ON
ON ON
ON ON
ON
OFF OFF OFF
OFF OFF OFF OFF OFF
LOW
LOW LOW LOW LOW LOW LOW
HIGH HIGH HIGH HIGH HIGH HIGH
Board ID / SKU ID Table for AD channel ON
OFF OFF
100K +/- 5%
Ra/Rc/Re
Board ID Rb / Rd / Rf V min 0
1 2 3
0 8.2K +/- 5%
0 V
0.436 V 0.712 V
0.503 V 0.819 V
0.538 V 0.875 V
AD_BID VAD_BIDtyp VAD_BIDmax
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%
3.300 V
4 5 6
1.036 V
1.935 V 2.500 V
2.200 V 3.300 V
2.341 V
Board ID 0 1 2 3 4 5 6 7
PCB Revision 0.1
+0.9VS 0.9V switched power rail for DDR terminator
+RTCVCC RTC power
+1.5VS
+1.8VS 1.8V switched power rail
+1.1VS
+5VS
+3VS
+5VALW
+1.8V
1.1V switched power rail +3VALW
1.8V power rail for DDR
3.3V always on power rail
5V always on power rail 3.3V switched power rail
5V switched power rail +VSB VSB always on power rail ON ON*
ON ON ON ON 1.5V switched power rail
PM@
GM@
Discrete UMA
+1.25VS 1.25V switched power rail ON OFF OFF
+3V
+3V_LAN
3.3V power rail for SB 3.3V power rail for LAN
ON ON
ON ON
X X
0.2 0.3 1.0 1A
+1.5V 1.5V power rail for HDA ON ON OFF
ALC888VC ALC888VB
ALC268
888VC@
888VB@
268@
JAL90@
JAL90
JAW50@
JAW50
JAL90GM@
JAL90-UMA
GLPM@
JAW50 Discrete
KAL90-UMA
XXXXXXXXXX:JAL90GM@/JAL90@/GM@/888VC@/8121@/ESATA@
BOM Configuration Table
Core voltage for GPU
NB9M THERMAL SENSOR
Trang 4D D
H_A#[3 35]
H_REQ#[0 4]
H_RS#[0 2]
H_IERR#
XDP_BPM#5 XDP_TDI
XDP_TRST#
H_PROCHOT#
XDP_TMS
XDP_TCK
H_A#4 H_A#6 H_A#8 H_A#10 H_A#12
H_A#15 H_A#13
H_A#17 H_A#16
H_A#18 H_A#20 H_A#22 H_A#24 H_A#26 H_A#28 H_A#30
H_REQ#0 H_REQ#2 H_REQ#4
H_RESET#
H_IERR#
XDP_DBRESET#
XDP_TCK
XDP_TRST#
XDP_TDI XDP_TMS
H_THERMDA H_PROCHOT#
H_RS#0 H_RS#2
H_A#32 H_A#34
XDP_BPM#5
H_PROCHOT#
H_THERMDA
H_THERMDC
H_A#[3 35]
<7>
H_REQ#[0 4]
<7>
H_RS#[0 2]
<7>
H_ADSTB#0
<7>
H_ADSTB#1
<7>
H_RESET# <7>
H_ADS# <7>
H_BNR# <7>
H_BPRI# <7>
H_BR0# <7>
H_DEFER# <7>
H_DRDY# <7>
H_HIT# <7>
H_HITM# <7>
H_LOCK# <7>
CLK_CPU_BCLK# <16>
CLK_CPU_BCLK <16>
H_A20M#
<26>
H_INIT# <26>
H_IGNNE#
<26>
H_NMI
<26>
H_INTR
<26>
H_FERR#
<26>
H_STPCLK#
<26>
H_SMI#
<26>
H_DBSY# <7>
XDP_DBRESET# <27>
H_THERMTRIP# <8,26>
H_TRDY# <7>
EC_SMB_CK2 <18,35>
EC_SMB_DA2 <18,35>
OCP# <27>
+1.05VS
+3VS
+1.05VS
+3VS
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC
SCHEMATIC,A4491
B
Thursday, October 30, 2008
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC
SCHEMATIC,A4491
B
Thursday, October 30, 2008
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC
SCHEMATIC,A4491
B
Thursday, October 30, 2008
Compal Electronics, Inc.
Layout Note:
H_THERMDA&H_THERMDC Trace / Space = 10 / 10 mil
166
0 1
1
left NC if no ITP 39Ohm
0 1 0 200
0 0 0 266
R2 1 2 54.9_0402_1%
R1133 10K_0402_5%
R1133 10K_0402_5%
R8 1 2 54.9_0402_1%
Q1 MMBT3904_SOT23-3
@
Q1 MMBT3904_SOT23-3
@
C2 0.1U_0402_16V4Z C2 0.1U_0402_16V4Z
C3 2200P_0402_50V7K C3 2200P_0402_50V7K 1
2
U1
EMC1402-1-ACZL-TR_MSOP8 U1
EMC1402-1-ACZL-TR_MSOP8
DN
3
DP
2
VDD
1
THERM#
R17 56_0402_5%
@
R17 56_0402_5%
@
H CLK THERMAL
JCPU1A
Penryn CONN@
H CLK THERMAL
JCPU1A
Penryn CONN@
A[10]#
N3
A[11]#
P5
A[12]#
P2
A[13]#
L2
A[14]#
P4
A[15]#
P1
A[16]#
R1
A[17]#
Y2
A[18]#
U5
A[19]#
R3
A[20]#
W6
A[21]#
U4
A[22]#
Y5
A[23]#
U1
A[24]#
R4
A[25]#
T5
A[26]#
T3
A[27]#
W2
A[28]#
W5
A[29]#
Y4
A[3]#
J4
A[30]#
U2
A[31]#
V4
RSVD[01]
M4
RSVD[02]
N5
RSVD[03]
T2
RSVD[04]
V3
RSVD[05]
B2
RSVD[06]
D2
RSVD[07]
D22
A[4]#
L5
A[5]#
L4
A[6]#
K5
A[7]#
M3
A[8]#
N2
A[9]#
J1
A20M#
A6
ADSTB[0]#
M1
ADSTB[1]#
V1
RSVD[08]
D3
FERR#
A5
IGNNE#
C4
LINT0
C6
LINT1
B4
REQ[0]#
K3
REQ[1]#
H2
REQ[2]#
K2
REQ[3]#
J3
REQ[4]#
L1
SMI#
A3
STPCLK#
D5
A[32]#
W3
A[33]#
AA4
A[34]#
AB2
A[35]#
AA3
RSVD[09]
F6
@
@
R7 2 1 54.9_0402_1%
R3 1 2 54.9_0402_1%
Trang 5D D
H_D#[0 63]
H_PWRGOOD H_CPUSLP#
H_D#56
H_D#59
H_D#62
H_D#49 H_D#51 H_D#53 H_D#55
H_D#40
H_D#43 H_D#41
H_D#44 H_D#42
H_D#45 H_D#47
H_D#36 H_D#33 H_D#35 H_D#37 H_D#39 H_D#8
H_D#10 H_D#9
H_D#15 H_D#12 H_D#14
H_D#2 H_D#0
H_D#4
H_D#7 H_D#5
H_D#24
H_D#29 H_D#26 H_D#28 H_D#30
H_D#16
H_D#19 H_D#21 H_D#23
COMP1 COMP3
GTL_REF0 TEST1
TEST4 TEST6
VSSSENSE VCCSENSE
H_D#[0 63] <7>
H_DINV#3 <7>
H_DSTBN#1
H_DSTBP#1
H_DINV#2 <7>
H_DSTBP#0
H_DSTBN#0
H_DINV#1
<7>
H_DINV#0
<7>
PSI# <49>
CPU_BSEL0
<16>
CPU_BSEL1
<16>
CPU_BSEL2
<16>
H_DPRSTP# <8,26,49>
H_DPSLP# <26>
H_DPWR# <7>
H_PWRGOOD <26>
H_CPUSLP# <7>
CPU_VID0 <49>
CPU_VID1 <49>
CPU_VID2 <49>
CPU_VID3 <49>
CPU_VID4 <49>
CPU_VID5 <49>
CPU_VID6 <49>
VCCSENSE <49>
VSSSENSE <49>
+1.05VS
+CPU_CORE
+1.05VS +CPU_CORE
+1.5VS
+CPU_CORE
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC
SCHEMATIC,A4491
B
Thursday, October 30, 2008
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC
SCHEMATIC,A4491
B
Thursday, October 30, 2008
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC
SCHEMATIC,A4491
B
Thursday, October 30, 2008
Compal Electronics, Inc.
Width=4 mil ,
Spacing: 15mil
(55Ohm)
COMP0, COMP2 layout : Width 18mils and Space 25mils (27.4Ohms) COMP1, COMP3 layout : Width 4mils and Space 25mils (55Ohms)
TRACE CLOSELY CPU < 0.5'
20mils Trace Close CPU < 0.5'
C7 0.01U_0402_16V7K C7 0.01U_0402_16V7K 1
2
R30 100_0402_1%
R30 100_0402_1%
@
@ 1 2 T1 PAD
@ T1 PAD
@
R25 1 2 54.9_0402_1%
JCPU1C
Penryn
CONN@
JCPU1C
Penryn
CONN@
VCC[001]
A7
VCC[002]
A9
VCC[003]
A10
VCC[004]
A12
VCC[005]
A13
VCC[006]
A15
VCC[007]
A17
VCC[008]
A18
VCC[009]
A20
VCC[010]
B7
VCC[011]
B9
VCC[012]
B10
VCC[013]
B12
VCC[014]
B14
VCC[015]
B15
VCC[016]
B17
VCC[017]
B18
VCC[018]
B20
VCC[019]
C9
VCC[020]
C10
VCC[021]
C12
VCC[022]
C13
VCC[023]
C15
VCC[024]
C17
VCC[025]
C18
VCC[026]
D9
VCC[027]
D10
VCC[028]
D12
VCC[029]
D14
VCC[030]
D15
VCC[031]
D17
VCC[032]
D18
VCC[033]
E7
VCC[034]
E9
VCC[035]
E10
VCC[036]
E12
VCC[037]
E13
VCC[038]
E15
VCC[039]
E17
VCC[040]
E18
VCC[041]
E20
VCC[042]
F7
VCC[043]
F9
VCC[044]
F10
VCC[045]
F12
VCC[046]
F14
VCC[047]
F15
VCC[048]
F17
VCC[049]
F18
VCC[050]
F20
VCC[051]
AA7
VCC[052]
AA9
VCC[053]
AA10
VCC[054]
AA12
VCC[055]
AA13
VCC[056]
AA15
VCC[057]
AA17
VCC[058]
AA18
VCC[059]
AA20
VCC[060]
AB9
VCC[061]
AC10
VCC[062]
AB10
VCC[063]
AB12
VCC[064]
AB14
VCC[065]
AB15
VCC[066]
AB17
VCC[067]
AB18
C1477 0.1U_0402_16V4Z
@ C1477 0.1U_0402_16V4Z
@
R24 1 2 27.4_0402_1%
R28 100_0402_1%
R28 100_0402_1%
T2 PAD
@ T2 PAD
@
R26 1 2 27.4_0402_1%
C8
10U_0805_10V4Z C8
10U_0805_10V4Z
1
2
R29
2K_0402_1%
R29
2K_0402_1%
MISC
JCPU1B
Penryn CONN@
MISC
JCPU1B
Penryn CONN@
D[0]#
E22
D[1]#
F24
D[10]#
J24
D[11]#
J23
D[12]#
H22
D[13]#
F26
D[14]#
K22
D[15]#
H23
D[16]#
N22
D[17]#
K25
D[18]#
P26
D[19]#
R23
D[2]#
E26
D[20]#
L23
D[21]#
M24
D[22]#
L22
D[23]#
M23
D[24]#
P25
D[25]#
P23
D[26]#
P22
D[27]#
T24
D[28]#
R24
D[29]#
L25
D[3]#
G22
D[30]#
T25
D[31]#
N25
D[4]#
F23
D[5]#
G25
D[6]#
E25
D[7]#
E23
D[8]#
K24
D[9]#
G24
TEST5
AF1
DINV[0]#
H25
DINV[1]#
N24
DSTBN[0]#
J26
DSTBN[1]#
L26
DSTBP[0]#
H26
DSTBP[1]#
M26
GTLREF
AD26
TEST3
C24
BSEL[0]
B22
BSEL[1]
B23
BSEL[2]
C21
TEST2
D25
TEST4
AF26
TEST6
A26
TEST1
C23
TEST7
C3
R27
1K_0402_1%
R27
1K_0402_1%
R23 1 2 54.9_0402_1%
T3 PAD
@ T3 PAD
@
@
@ 1 2
Trang 6D D
+1.05VS
+CPU_CORE
+CPU_CORE
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC
SCHEMATIC,A4491
B
Thursday, October 30, 2008
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC
SCHEMATIC,A4491
B
Thursday, October 30, 2008
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC
SCHEMATIC,A4491
B
Thursday, October 30, 2008
Compal Electronics, Inc.
4X330uF 6m ohm/4 1.8nH/6
+CPU-CORE Decoupling
32X22uF 3m ohm/32 0.6nH/32
C,uF ESR, mohm ESL,nH SPCAP,Polymer
MLCC 0805 X5R
32X10uF 3m ohm/32 0.6nH/32
JCPU1D
Penryn
CONN@
JCPU1D
Penryn
CONN@
VSS[002]
A8
VSS[003]
A11
VSS[004]
A14
VSS[005]
A16
VSS[006]
A19
VSS[007]
A23
VSS[008]
AF2
VSS[009]
B6
VSS[010]
B8
VSS[011]
B11
VSS[012]
B13
VSS[013]
B16
VSS[014]
B19
VSS[015]
B21
VSS[016]
B24
VSS[017]
C5
VSS[018]
C8
VSS[019]
C11
VSS[020]
C14
VSS[021]
C16
VSS[022]
C19
VSS[023]
C2
VSS[024]
C22
VSS[025]
C25
VSS[026]
D1
VSS[027]
D4
VSS[028]
D8
VSS[029]
D11
VSS[030]
D13
VSS[031]
D16
VSS[032]
D19
VSS[033]
D23
VSS[034]
D26
VSS[035]
E3
VSS[036]
E6
VSS[037]
E8
VSS[038]
E11
VSS[039]
E14
VSS[040]
E16
VSS[041]
E19
VSS[042]
E21
VSS[043]
E24
VSS[044]
F5
VSS[045]
F8
VSS[046]
F11
VSS[047]
F13
VSS[048]
F16
VSS[049]
F19
VSS[050]
F2
VSS[051]
F22
VSS[052]
F25
VSS[053]
G4
VSS[054]
G1
VSS[055]
G23
VSS[056]
G26
VSS[057]
H3
VSS[058]
H6
VSS[059]
H21
VSS[060]
H24
VSS[061]
J2
VSS[062]
J5
VSS[063]
J22
VSS[064]
J25
VSS[065]
K1
VSS[066]
K4
VSS[067]
K23
VSS[068]
K26
VSS[069]
L3
VSS[070]
L6
VSS[071]
L21
VSS[072]
L24
VSS[073]
M2
VSS[074]
M5
VSS[075]
M22
VSS[076]
M25
VSS[077]
N1
VSS[078]
N4
VSS[079]
N23
VSS[080]
N26
VSS[081]
P3
VSS[001]
A4
C426
10U_0805_6.3V6M C426
10U_0805_6.3V6M
1
2
C430
10U_0805_6.3V6M C430
10U_0805_6.3V6M
1
2
C50 0.1U_0402_16V4Z C50 0.1U_0402_16V4Z 1
2 C49
0.1U_0402_16V4Z C49
0.1U_0402_16V4Z
1
2 C47
0.1U_0402_16V4Z C47
0.1U_0402_16V4Z
1
2
C429
10U_0805_6.3V6M C429
10U_0805_6.3V6M
1
2 C425
10U_0805_6.3V6M C425
10U_0805_6.3V6M
1
2
C45
0.1U_0402_16V4Z C45
0.1U_0402_16V4Z
1
2
C431
10U_0805_6.3V6M C431
10U_0805_6.3V6M
1
2
+ C55 900P_PFAF250E128MNTTE_2.5VM + C55
900P_PFAF250E128MNTTE_2.5VM 1
3 4 2
C427
10U_0805_6.3V6M C427
10U_0805_6.3V6M
1
2 C416
10U_0805_6.3V6M C416
10U_0805_6.3V6M
1
2
+ C1478 330U_D2E_2.5VM_R15 + C1478 330U_D2E_2.5VM_R15 1
2
C428
10U_0805_6.3V6M C428
10U_0805_6.3V6M
1
2
C48 0.1U_0402_16V4Z C48 0.1U_0402_16V4Z 1
2 C46
0.1U_0402_16V4Z C46 0.1U_0402_16V4Z 1
2
Trang 7D D
H_SWING
H_D#0 H_D#2 H_D#4 H_D#6
H_D#11 H_D#13 H_D#9
H_D#14 H_D#8
H_D#15 H_D#12 H_D#10
H_D#19 H_D#21 H_D#17
H_D#22 H_D#16
H_D#23 H_D#20 H_D#18
H_D#27 H_D#29 H_D#25
H_D#30 H_D#24
H_D#31 H_D#28 H_D#26
H_D#35 H_D#37 H_D#33
H_D#38 H_D#32
H_D#39 H_D#36 H_D#34
H_D#43 H_D#45 H_D#41
H_D#46 H_D#40
H_D#47 H_D#44 H_D#42
H_D#51 H_D#53 H_D#49
H_D#54
H_D#48
H_D#52 H_D#50
H_D#55
H_D#59 H_D#61 H_D#57
H_D#62 H_D#56
H_D#63 H_D#60 H_D#58
H_A#3 H_A#5 H_A#7
H_A#11 H_A#8 H_A#10 H_A#12 H_A#9
H_A#13 H_A#15 H_A#17 H_A#14
H_A#21 H_A#18 H_A#20 H_A#22 H_A#19
H_A#26 H_A#23 H_A#25 H_A#27 H_A#24
H_A#31 H_A#28 H_A#30
H_ADSTB#1
H_HIT#
H_BNR#
H_BPRI#
H_DPWR#
H_ADS#
H_ADSTB#0
H_LOCK#
H_DBSY#
H_BR0#
H_HITM#
H_DRDY#
H_DEFER#
H_TRDY#
H_A#16
CLK_MCH_BCLK#
CLK_MCH_BCLK
H_CPUSLP#
H_RESET#
H_RCOMP
H_RCOMP H_SWING
H_A#33 H_A#35
H_RS#0 H_REQ#0 H_DSTBP#0
H_REQ#4 H_REQ#2 H_DSTBP#2
H_REQ#3
H_DINV#2
H_REQ#1
H_DINV#0
H_DSTBP#3
H_DSTBN#3
H_DSTBP#1 H_DINV#3
H_RS#2 H_DSTBN#1
H_RS#1 H_DINV#1
H_AVREF
H_D#[0 63]
<5>
H_A#[3 35] <4>
H_ADSTB#1 <4>
H_RESET#
<4>
H_ADS# <4>
H_TRDY# <4>
H_DPWR# <5>
H_DRDY# <4>
H_DEFER# <4>
H_BR0# <4>
H_BNR# <4>
H_BPRI# <4>
H_DBSY# <4>
H_CPUSLP#
<5>
H_HITM# <4>
H_HIT# <4>
H_LOCK# <4>
CLK_MCH_BCLK# <16>
CLK_MCH_BCLK <16>
H_REQ#[0 4] <4>
H_DSTBP#0 <5>
H_DSTBN#0 <5>
H_DSTBP#1 <5>
H_DSTBN#1 <5>
H_DSTBP#2 <5>
H_DSTBN#2 <5>
H_DSTBP#3 <5>
H_DSTBN#3 <5>
H_DINV#0 <5>
H_DINV#1 <5>
H_DINV#2 <5>
H_DINV#3 <5>
H_RS#[0 2] <4>
+1.05VS
+1.05VS
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC
SCHEMATIC,A4491
B
Thursday, October 30, 2008
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC
SCHEMATIC,A4491
B
Thursday, October 30, 2008
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC
SCHEMATIC,A4491
B
Thursday, October 30, 2008
Compal Electronics, Inc.
width=10mil width=10mil
width:spacing=10mil:20mil (<0.5")
within 100mil to Ball A11,B11
R46 1K_0402_1%
R46 1K_0402_1%
U2A
CANTIGA ES_FCBGA1329 GM@
U2A
CANTIGA ES_FCBGA1329 GM@
H_D#_0
F2
H_D#_1
G8
H_D#_2
F8
H_D#_3
E6
H_D#_4
G2
H_D#_5
H6
H_D#_6
H2
H_D#_7
F6
H_D#_8
D4
H_D#_9
H3
H_D#_10
M9
H_D#_11
M11
H_D#_12
J1
H_D#_13
J2
H_D#_14
N12
H_D#_15
J6
H_D#_16
P2
H_D#_17
L2
H_D#_18
R2
H_D#_19
N9
H_D#_20
L6
H_D#_21
M5
H_D#_22
J3
H_D#_23
N2
H_D#_24
R1
H_D#_25
N5
H_D#_26
N6
H_D#_27
P13
H_D#_28
N8
H_D#_29
L7
H_D#_30
N10
H_D#_31
M3
H_D#_32
Y3
H_D#_33
AD14
H_D#_34
Y6
H_D#_35
Y10
H_D#_36
Y12
H_D#_37
Y14
H_D#_38
Y7
H_D#_39
W2
H_D#_40
AA8
H_D#_41
Y9
H_D#_42
AA13
H_D#_43
AA9
H_D#_44
AA11
H_D#_45
AD11
H_D#_46
AD10
H_D#_47
AD13
H_D#_48
AE12
H_D#_49
AE9
H_D#_50
AA2
H_D#_51
AD8
H_D#_52
AA3
H_D#_53
AD3
H_D#_54
AD7
H_D#_55
AE14
H_D#_56
AF3
H_D#_57
AC1
H_D#_58
AE3
H_D#_59
AC3
H_D#_60
AE11
H_D#_61
AE8
H_D#_62
AG2
H_D#_63
AD6
H_SWING
C5
H_RCOMP
E3
H_CPURST#
C12
H_CPUSLP#
E11
H_AVREF
A11
H_DVREF
B11
C59 0.1U_0402_16V4Z C59 0.1U_0402_16V4Z 1
2
R54 24.9_0402_1%
R54 24.9_0402_1%
R47 221_0402_1%
R47 221_0402_1%
R52 2K_0402_1%
R52 2K_0402_1%
C58 0.1U_0402_16V4Z
@
C58 0.1U_0402_16V4Z
@
1
2
R55 100_0402_1%
R55 100_0402_1%
Trang 8D D
MCH_CLKREQ#
SM_RCOMP_VOL SM_RCOMP_VOH
SM_RCOMP_VOH SM_RCOMP_VOL
CL_VREF
SM_RCOMP_VOH
ICH_PWROK
CLK_DREF_SSC CLK_DREF_SSC#
CLK_DREF_96M#
CLK_DREF_96M
MCH_CLKSEL1
MCH_CFG_5 MCH_CFG_7 MCH_CFG_9 MCH_CFG_10 MCH_CFG_12
MCH_CFG_19 MCH_CFG_16
PM_DPRSTP#_R
MCH_RSTIN#
DPRSLPVR_R THERMTRIP#_R
PM_EXTTS#0 GMCH_PWROK PM_SYNC#_R PM_EXTTS#1
MCH_TSATN#
DMI_ITX_MRX_N0
DMI_ITX_MRX_P1 DMI_ITX_MRX_P3
DMI_MTX_IRX_P1 DMI_MTX_IRX_P3
DMI_ITX_MRX_N3
DMI_MTX_IRX_N3 DMI_MTX_IRX_N1
DMI_ITX_MRX_N1
CLK_MCH_3GPLL CLK_MCH_3GPLL#
CLK_DREF_SSC CLK_DREF_SSC#
CLK_DREF_96M#
CLK_DREF_96M
SMRCOMP SMRCOMP#
SM_VREF SM_PWROK
SM_REXT
MCH_CFG_6
MCH_CFG_10
MCH_CFG_13
MCH_CFG_20
MCH_CFG_9
MCH_CFG_16 MCH_CFG_12
MCH_CFG_19
MCH_CFG_5
MCH_CFG_7
PM_EXTTS#0
MCH_CLKREQ#
PM_EXTTS#1
GMCH_PWROK ICH_PWROK
VGATE
MCH_TSATN#
MCH_CLKREQ# <16>
MCH_ICH_SYNC# <27>
CL_CLK0 <27>
CL_DATA0 <27>
CL_RST#0 <27>
MCH_CLKSEL2
<16>
MCH_CLKSEL0
<16>
MCH_CLKSEL1
<16>
H_DPRSTP#
<5,26,49>
PM_SYNC#
<27>
H_THERMTRIP#
<4,26>
PM_DPRSLPVR
<27,49>
PM_EXTTS#0
<14>
PM_EXTTS#1
<15>
PLT_RST#
<17,25,27,30,31,35>
DMI_ITX_MRX_N0 <27>
DMI_ITX_MRX_N2 <27>
DMI_ITX_MRX_P0 <27>
DMI_ITX_MRX_P2 <27>
DMI_MTX_IRX_N0 <27>
DMI_MTX_IRX_N2 <27>
DMI_MTX_IRX_P0 <27>
DMI_MTX_IRX_P2 <27>
CLK_MCH_3GPLL# <16>
CLK_MCH_3GPLL <16>
CLK_DREF_SSC <16>
CLK_DREF_SSC# <16>
CLK_DREF_96M <16>
CLK_DREF_96M# <16>
DDRA_CLK0 <14>
DDRB_CLK0 <15>
DDRA_CLK0# <14>
DDRB_CLK0# <15>
DDRA_CKE0 <14>
DDRB_CKE0 <15>
DDRA_SCS0# <14>
DDRB_SCS0# <15>
DDRA_ODT0 <14>
DDRB_ODT0 <15>
VGATE
<16,27,49>
ICH_PWROK
<27>
MCH_TSATN_EC# <35>
+1.8V
+1.05VS
+1.8V +1.8V
+DIMM_VREF
+3VS
+3VS
+1.05VS
+3VS +3VS
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC
SCHEMATIC,A4491 Custom
Thursday, October 30, 2008
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC
SCHEMATIC,A4491 Custom
Thursday, October 30, 2008
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC
SCHEMATIC,A4491 Custom
Thursday, October 30, 2008
Compal Electronics, Inc.
20mil
SM_DRAMRST# would be needed for DDR3 only
as close as possible to the related balls
All RSVD balls on GMCH should be left No Connect
Notice: Please check HDA power rail to select HDA controller
For Cantiga 80 Ohm
L_DDC_DATA 1 = LFP Card Present; PCIE disable 0 = LFP Disable * (Default) DDPC_CTRLDATA 1 = Digital DisplayPort Device Present 0 = Digital DisplayPort Disable * (Default)
CFG10 0 = PCIe Loopback Enable 1 = Disable * (Default)
1 = Normal Operation (Default)
0 = Lane Reversal Enable
* CFG6
000 = FSB1067
CFG[13:12]
1 = PCIE/SDVO are operating simu.
CFG19 CFG20
0 = DMI x 2
Strap Pin Table
*
01 = XOR Mode Enabled
(Default)
1 = iTPM Host Interface is Disabled CFG5
1 = DMI Lane Reversal Enable *
1 = Dynamic ODT Enabled (Default)
*
(Default)
00 = Reserved
*
1 = DMI x 4
(Default)
*
* (Default)
0 = Normal Operation
(Default)
0 = Only PCIE or SDVO is operational.
0 = Dynamic ODT Disabled
(PCIE/SDVO select)
10 = All Z Mode Enabled
010 = FSB800
CFG16
011 = FSB667
0 = iTPM Host Interface is enabled
CFG9 CFG[2:0]
11 = Normal Operation
SDVO_CTRLDATA 1 = SDVO Card Present 0 = No SDVO Card Present * (Default)
Use VGATE for GMCH_PWROK
R84 2.21K_0402_1%
@ R84 2.21K_0402_1%
@ 1 2
R1143 100_0402_5%
R11431 2 100_0402_5%
R39 10K_0402_5%
R391 210K_0402_5%
C54 2.2U_0603_6.3V6K C54 2.2U_0603_6.3V6K 1
2
R36 1 2 0_0402_5%
C56 0.1U_0402_16V4Z C56 0.1U_0402_16V4Z 1
2
U2B
CANTIGA ES_FCBGA1329 GM@
U2B
CANTIGA ES_FCBGA1329 GM@
RSVD1
M36
RSVD2
N36
RSVD3
R33
RSVD4
T33
RSVD5
AH9
RSVD6
AH10
RSVD7
AH12
RSVD8
AH13
RSVD9
K12
RSVD10
AL34
RSVD11
AK34
RSVD12
AN35
RSVD13
AM35
RSVD14
T24
RSVD15
B31
RSVD17
M1
RSVD20
AY21
RSVD22
BG23
RSVD23
BF23
RSVD24
BH18
CFG_0
T25
CFG_1
R25
CFG_2
P25
CFG_3
P20
CFG_4
P24
CFG_5
C25
CFG_6
N24
CFG_7
M24
CFG_8
E21
CFG_9
C23
CFG_10
C24
CFG_11
N21
CFG_12
P21
CFG_13
T21
CFG_14
R20
CFG_15
M20
CFG_16
L21
CFG_17
H21
CFG_18
P29
CFG_19
R28
CFG_20
T28
PM_SYNC#
R29
PM_DPRSTP#
B7
PM_EXT_TS#_0
N33
PM_EXT_TS#_1
P32
PWROK
AT40
RSTIN#
AT11
THERMTRIP#
T20
DPRSLPVR
R32
NC_1
BG48
NC_2
BF48
NC_3
BD48
NC_4
BC48
NC_5
BH47
NC_6
BG47
NC_7
BE47
NC_8
BH46
NC_9
BF46
NC_10
BG45
NC_11
BH44
NC_12
BH43
NC_13
BH6
NC_14
BH5
NC_15
BG4
NC_16
BH3
NC_17
BF3
NC_18
BH2
NC_19
BG2
NC_20
BE2
NC_21
BG1
NC_22
BF1
NC_23
BD1
NC_24
BC1
NC_25
F1
RSVD16
B2
RSVD25
BF18
NC_26
A47
PM@
PM@
C53 0.01U_0402_16V7K C53 0.01U_0402_16V7K 1
2
R1147 1K_0402_5%
R1147 1K_0402_5%
R34 1 280.6_0402_1%
R1139 0_0402_5%
@ R1139 0_0402_5%
@
R45 1K_0402_1%
@
R45 1K_0402_1%
@
E B C
Q75 MMBT3904_SOT23-3
E B C
Q75 MMBT3904_SOT23-3 2
R1152
330_0402_5%
R1152
330_0402_5%
R1144 0_0402_5%
R11441 2 0_0402_5%
R75 4.02K_0402_1%
@ R75 4.02K_0402_1%
@ 1 2
R1145 0_0402_5%
R11451 2 0_0402_5%
R1149 2.21K_0402_1%
@ R1149 2.21K_0402_1%
@ 1 2
R77 2.21K_0402_1%
@ R77 2.21K_0402_1%
@ 1 2
C52 2.2U_0603_6.3V6K C52 2.2U_0603_6.3V6K 1
2
R79 4.02K_0402_1%
@ R79 4.02K_0402_1%
@ 1 2
E B C
Q76 MMBT3904_SOT23-3
E B C
Q76 MMBT3904_SOT23-3 2
R38 10K_0402_5%
R381 210K_0402_5%
R73 4.02K_0402_1%
@ R73 4.02K_0402_1%
@ 1 2
T34 PAD
@ T34 PAD
@
R40 10K_0402_5%
R401 210K_0402_5%
R1148 1K_0402_5%
R1148 1K_0402_5%
R37 1 2 499_0402_1%
R1141 0_0402_5%
R11411 2 0_0402_5%
R43 1K_0402_1%
R43 1K_0402_1%
R33 1K_0402_1%
R33 1K_0402_1%
R48 1K_0402_1%
@
R48 1K_0402_1%
@
R78 2.21K_0402_1%
@ R78 2.21K_0402_1%
@ 1 2
R32 3.01K_0402_1%
R32 3.01K_0402_1%
R44 511_0402_1%R44 511_0402_1%
T35 PAD
@ T35 PAD
@ R86 2.21K_0402_1%
@ 1 2
R81 2.21K_0402_1%
@ R81 2.21K_0402_1%
@ 1 2
PM@
PM@
R35 1 280.6_0402_1%
C57 0.1U_0402_16V4Z C57 0.1U_0402_16V4Z 1
2
PM@
PM@
C51 0.01U_0402_16V7K C51 0.01U_0402_16V7K 1
2
R1140 0_0402_5%
R11401 20_0402_5%
R1135 0_0402_5%
R1135 0_0402_5%
R1146 2.21K_0402_1%
@ R1146 2.21K_0402_1%
@ 1 2
R31 1K_0402_1%
R31 1K_0402_1%
PM@
PM@
R1142 0_0402_5%
R11421 2 0_0402_5%
R1150
54.9_0402_1%
R1150
54.9_0402_1%
Trang 9D D
DDRB_SDQ2 DDRB_SDQ0
DDRB_SDQ7 DDRB_SDQ5
DDRB_SDQ40 DDRB_SDQ42 DDRB_SDQ44 DDRB_SDQ46
DDRB_SDQ12 DDRB_SDQ14
DDRB_SDQ8 DDRB_SDQ10
DDRB_SDQ48 DDRB_SDQ50 DDRB_SDQ52 DDRB_SDQ54
DDRB_SDQ22 DDRB_SDQ17
DDRB_SDQ23
DDRB_SDQ16
DDRB_SDQ19
DDRB_SDQ56 DDRB_SDQ58 DDRB_SDQ60 DDRB_SDQ62
DDRB_SDQ27 DDRB_SDQ29 DDRB_SDQ31
DDRB_SDQ24
DDRB_SDQ28
DDRB_SDQ32 DDRB_SDQ34 DDRB_SDQ36 DDRB_SDQ38
DDRB_SDQ[0 63]
DDRB_SMA[0 14]
DDRB_SDM[0 7]
DDRA_SDQ[0 63]
DDRA_SMA[0 14]
DDRA_SDM[0 7]
DDRA_SDQ2 DDRA_SDQ0
DDRA_SDQ7 DDRA_SDQ5
DDRA_SDQ40 DDRA_SDQ42 DDRA_SDQ44 DDRA_SDQ46
DDRA_SDQ12 DDRA_SDQ14
DDRA_SDQ8 DDRA_SDQ10
DDRA_SDQ48 DDRA_SDQ50 DDRA_SDQ52 DDRA_SDQ54
DDRA_SDQ22 DDRA_SDQ17
DDRA_SDQ23
DDRA_SDQ16
DDRA_SDQ19
DDRA_SDQ56 DDRA_SDQ58 DDRA_SDQ60 DDRA_SDQ62
DDRA_SDQ27 DDRA_SDQ29 DDRA_SDQ31
DDRA_SDQ24
DDRA_SDQ28
DDRA_SDQ32 DDRA_SDQ34 DDRA_SDQ36 DDRA_SDQ38
DDRA_SMA3
DDRA_SMA7
DDRA_SMA0 DDRA_SMA2
DDRA_SMA10
DDRA_SMA1
DDRA_SMA6
DDRA_SMA12
DDRA_SMA4
DDRA_SMA8
DDRA_SMA13
DDRA_SDQS5#
DDRA_SDQS0#
DDRA_SDQS4#
DDRA_SDQS7#
DDRA_SDQS2#
DDRA_SDQS6#
DDRA_SDQS1#
DDRA_SDQS5 DDRA_SDQS0
DDRA_SDQS4
DDRA_SDQS7 DDRA_SDQS2
DDRA_SDQS6 DDRA_SDQS1 DDRA_SDM6
DDRA_SDM0
DDRA_SDM4
DDRA_SDM7
DDRA_SDM1 DDRA_SDM3
DDRB_SMA3
DDRB_SMA7
DDRB_SMA0 DDRB_SMA2
DDRB_SMA10
DDRB_SMA1
DDRB_SMA6
DDRB_SMA12
DDRB_SMA4
DDRB_SMA8
DDRB_SMA13
DDRB_SDQS5#
DDRB_SDQS0#
DDRB_SDQS4#
DDRB_SDQS7#
DDRB_SDQS2#
DDRB_SDQS6#
DDRB_SDQS1#
DDRB_SDQS0
DDRB_SDQS5 DDRB_SDQS3
DDRB_SDQS7 DDRB_SDQS2
DDRB_SDQS6 DDRB_SDQS1 DDRB_SDM6 DDRB_SDM1
DDRB_SDM5 DDRB_SDM0
DDRB_SDM4
DDRB_SDM7 DDRB_SDM2
DDRA_SBS2# <14>
DDRA_SBS0# <14>
DDRA_SDQ[0 63]
<14>
DDRA_SMA[0 14]
<14>
DDRA_SDM[0 7]
<14>
DDRB_SDQ[0 63]
<15>
DDRB_SMA[0 14]
<15>
DDRB_SDM[0 7]
<15>
DDRA_SDQS6# <14>
DDRA_SDQS3# <14>
DDRA_SDQS7# <14>
DDRA_SDQS5# <14>
DDRA_SDQS0# <14>
DDRA_SDQS4# <14>
DDRA_SDQS1# <14>
DDRA_SDQS2# <14>
DDRA_SDQS6 <14>
DDRA_SDQS3 <14>
DDRA_SDQS7 <14>
DDRA_SDQS5 <14>
DDRA_SDQS0 <14>
DDRA_SDQS4 <14>
DDRA_SDQS1 <14>
DDRA_SDQS2 <14>
DDRA_SCAS# <14>
DDRA_SWE# <14>
DDRA_SRAS# <14>
DDRB_SBS2# <15>
DDRB_SBS0# <15>
DDRB_SCAS# <15>
DDRB_SDQS6# <15>
DDRB_SDQS3# <15>
DDRB_SDQS7# <15>
DDRB_SDQS5# <15>
DDRB_SDQS0# <15>
DDRB_SDQS4# <15>
DDRB_SDQS1# <15>
DDRB_SDQS2# <15>
DDRB_SDQS6 <15>
DDRB_SDQS3 <15>
DDRB_SDQS7 <15>
DDRB_SDQS5 <15>
DDRB_SDQS0 <15>
DDRB_SDQS4 <15>
DDRB_SDQS1 <15>
DDRB_SDQS2 <15>
DDRB_SRAS# <15>
DDRB_SWE# <15>
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC
SCHEMATIC,A4491
B
Thursday, October 30, 2008
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC
SCHEMATIC,A4491
B
Thursday, October 30, 2008
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC
SCHEMATIC,A4491
B
Thursday, October 30, 2008
Compal Electronics, Inc.
U2D
CANTIGA ES_FCBGA1329 GM@
U2D
CANTIGA ES_FCBGA1329 GM@
SA_DQ_0
AJ38
SA_DQ_1
AJ41
SA_DQ_2
AN38
SA_DQ_3
AM38
SA_DQ_4
AJ36
SA_DQ_5
AJ40
SA_DQ_6
AM44
SA_DQ_7
AM42
SA_DQ_8
AN43
SA_DQ_9
AN44
SA_DQ_10
AU40
SA_DQ_11
AT38
SA_DQ_12
AN41
SA_DQ_13
AN39
SA_DQ_14
AU44
SA_DQ_15
AU42
SA_DQ_16
AV39
SA_DQ_17
AY44
SA_DQ_18
BA40
SA_DQ_19
BD43
SA_DQ_20
AV41
SA_DQ_21
AY43
SA_DQ_22
BB41
SA_DQ_23
BC40
SA_DQ_24
AY37
SA_DQ_25
BD38
SA_DQ_26
AV37
SA_DQ_27
AT36
SA_DQ_28
AY38
SA_DQ_29
BB38
SA_DQ_30
AV36
SA_DQ_31
AW36
SA_DQ_32
BD13
SA_DQ_33
AU11
SA_DQ_34
BC11
SA_DQ_35
BA12
SA_DQ_36
AU13
SA_DQ_37
AV13
SA_DQ_38
BD12
SA_DQ_39
BC12
SA_DQ_40
BB9
SA_DQ_41
BA9
SA_DQ_42
AU10
SA_DQ_43
AV9
SA_DQ_44
BA11
SA_DQ_45
BD9
SA_DQ_46
AY8
SA_DQ_47
BA6
SA_DQ_48
AV5
SA_DQ_49
AV7
SA_DQ_50
AT9
SA_DQ_51
AN8
SA_DQ_52
AU5
SA_DQ_53
AU6
SA_DQ_54
AT5
SA_DQ_55
AN10
SA_DQ_56
AM11
SA_DQ_57
AM5
SA_DQ_58
AJ9
SA_DQ_59
AJ8
SA_DQ_60
AN12
SA_DQ_61
AM13
SA_DQ_62
AJ11
SA_DQ_63
AJ12
U2E
CANTIGA ES_FCBGA1329 GM@
U2E
CANTIGA ES_FCBGA1329 GM@
SB_DQ_0
AK47
SB_DQ_1
AH46
SB_DQ_2
AP47
SB_DQ_3
AP46
SB_DQ_4
AJ46
SB_DQ_5
AJ48
SB_DQ_6
AM48
SB_DQ_7
AP48
SB_DQ_8
AU47
SB_DQ_9
AU46
SB_DQ_10
BA48
SB_DQ_11
AY48
SB_DQ_12
AT47
SB_DQ_13
AR47
SB_DQ_14
BA47
SB_DQ_15
BC47
SB_DQ_16
BC46
SB_DQ_17
BC44
SB_DQ_18
BG43
SB_DQ_19
BF43
SB_DQ_20
BE45
SB_DQ_21
BC41
SB_DQ_22
BF40
SB_DQ_23
BF41
SB_DQ_24
BG38
SB_DQ_25
BF38
SB_DQ_26
BH35
SB_DQ_27
BG35
SB_DQ_28
BH40
SB_DQ_29
BG39
SB_DQ_30
BG34
SB_DQ_31
BH34
SB_DQ_32
BH14
SB_DQ_33
BG12
SB_DQ_34
BH11
SB_DQ_35
BG8
SB_DQ_36
BH12
SB_DQ_37
BF11
SB_DQ_38
BF8
SB_DQ_39
BG7
SB_DQ_40
BC5
SB_DQ_41
BC6
SB_DQ_42
AY3
SB_DQ_43
AY1
SB_DQ_44
BF6
SB_DQ_45
BF5
SB_DQ_46
BA1
SB_DQ_47
BD3
SB_DQ_48
AV2
SB_DQ_49
AU3
SB_DQ_50
AR3
SB_DQ_51
AN2
SB_DQ_52
AY2
SB_DQ_53
AV1
SB_DQ_54
AP3
SB_DQ_55
AR1
SB_DQ_56
AL1
SB_DQ_57
AL2
SB_DQ_58
AJ1
SB_DQ_59
AH1
SB_DQ_60
AM2
SB_DQ_61
AM3
SB_DQ_62
AH3
SB_DQ_63
AJ3
Trang 10D D
LVDS_IBG
GMCH_CRT_CLK GMCH_CRT_DATA
GMCH_LCD_CLK GMCH_LCD_DATA LCTLB_DATA LCTLA_CLK
LBKLT_EN
PEG_COMP
GMCH_CRT_DATA GMCH_CRT_CLK TV_DCONSEL_1
GMCH_TXOUT1-GMCH_TXOUT0+
GMCH_TXOUT2+
GMCH_TXOUT0-GMCH_TXOUT1+
GMCH_TXCLK-GMCH_TXCLK+
GMCH_LCD_CLK GMCH_LCD_DATA
LBKLT_EN LCTLB_DATA LCTLA_CLK
CRT_IREF
PCIE_GTX_C_MRX_N11 PCIE_GTX_C_MRX_N8 PCIE_GTX_C_MRX_N10 PCIE_GTX_C_MRX_N9 PCIE_GTX_C_MRX_N5
PCIE_GTX_C_MRX_N14 PCIE_GTX_C_MRX_N12
PCIE_GTX_C_MRX_N15
PCIE_GTX_C_MRX_N1 PCIE_GTX_C_MRX_N3
PCIE_GTX_C_MRX_N7
PCIE_GTX_C_MRX_N2 PCIE_GTX_C_MRX_N4 PCIE_GTX_C_MRX_N6
PCIE_GTX_C_MRX_N0
PCIE_MTX_C_GRX_P[0 15]
PCIE_MTX_C_GRX_N[0 15]
PCIE_GTX_C_MRX_N[0 15]
PCIE_GTX_C_MRX_P[0 15]
PCIE_MTX_GRX_N2 PCIE_MTX_GRX_N0
PCIE_MTX_GRX_N4
PCIE_MTX_GRX_N7
PCIE_MTX_GRX_N3 PCIE_MTX_GRX_N5
PCIE_MTX_GRX_N8 PCIE_MTX_GRX_N10 PCIE_MTX_GRX_N6
PCIE_MTX_GRX_N11
PCIE_MTX_GRX_N15 PCIE_MTX_GRX_N13
PCIE_MTX_C_GRX_N7
PCIE_MTX_C_GRX_N1
PCIE_MTX_C_GRX_N4
PCIE_MTX_C_GRX_N8 PCIE_MTX_C_GRX_N10 PCIE_MTX_C_GRX_N0
PCIE_MTX_C_GRX_N9 PCIE_MTX_C_GRX_N5 PCIE_MTX_C_GRX_N3
PCIE_MTX_C_GRX_N12 PCIE_MTX_C_GRX_N14
PCIE_MTX_C_GRX_N6
PCIE_MTX_C_GRX_N11
PCIE_MTX_C_GRX_N15 PCIE_MTX_C_GRX_N13
PCIE_MTX_GRX_P1
PCIE_MTX_GRX_P7
PCIE_MTX_GRX_P2 PCIE_MTX_GRX_P0
PCIE_MTX_GRX_P4
PCIE_MTX_GRX_P8
PCIE_MTX_GRX_P11 PCIE_MTX_GRX_P9 PCIE_MTX_GRX_P6
PCIE_MTX_GRX_P15 PCIE_MTX_GRX_P13
PCIE_MTX_C_GRX_P7
PCIE_MTX_C_GRX_P1
PCIE_MTX_C_GRX_P5
PCIE_MTX_C_GRX_P0
PCIE_MTX_C_GRX_P3
PCIE_MTX_C_GRX_P15
PCIE_MTX_C_GRX_P9 PCIE_MTX_C_GRX_P6
PCIE_MTX_C_GRX_P10 PCIE_MTX_C_GRX_P8
PCIE_MTX_C_GRX_P12 PCIE_MTX_C_GRX_P14
PCIE_GTX_C_MRX_P11 PCIE_GTX_C_MRX_P9
PCIE_GTX_C_MRX_P3 PCIE_GTX_C_MRX_P1
PCIE_GTX_C_MRX_P10 PCIE_GTX_C_MRX_P7
PCIE_GTX_C_MRX_P12 PCIE_GTX_C_MRX_P4
PCIE_GTX_C_MRX_P14 PCIE_GTX_C_MRX_P6
PCIE_GTX_C_MRX_P15 PCIE_GTX_C_MRX_P13
PCIE_GTX_C_MRX_P5
PCIE_GTX_C_MRX_P0 PCIE_GTX_C_MRX_P2
GMCH_TV_LUMA GMCH_TV_CRMA
GMCH_TV_COMPS
GMCH_CRT_HSYNC
<23>
GMCH_CRT_CLK
<23>
GMCH_CRT_DATA
<23>
GMCH_TXOUT1-<22>
GMCH_TXOUT1+
<22>
GMCH_TXOUT2-<22>
GMCH_TXOUT2+
<22>
GMCH_TXOUT0-<22>
GMCH_TXOUT0+
<22>
GMCH_TXCLK+
<22>
GMCH_TXCLK-<22>
GMCH_ENVDD
<22>
GMCH_LCD_DATA
<22>
GMCH_LCD_CLK
<22>
ENBKL
<18,35> <22>DPST_PWM
GMCH_CRT_VSYNC
<23>
GMCH_CRT_R
<23>
GMCH_CRT_B
<23>
GMCH_CRT_G
<23>
PCIE_MTX_C_GRX_N[0 15] <17>
PCIE_GTX_C_MRX_P[0 15] <17>
PCIE_GTX_C_MRX_N[0 15] <17>
PCIE_MTX_C_GRX_P[0 15] <17>
+3VS
+1.05VS
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC
SCHEMATIC,A4491
Custom
Thursday, October 30, 2008
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC
SCHEMATIC,A4491
Custom
Thursday, October 30, 2008
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC
SCHEMATIC,A4491
Custom
Thursday, October 30, 2008
Compal Electronics, Inc.
10mils
Change to 0Ohm when use PM chip Change to 0Ohm when use PM chip
R571 249.9_0402_1%
R1165 1.02K_0402_1%
GM@
R1165 1.02K_0402_1%
GM@
R1154 0_0402_5%
GM@
R1154 0_0402_5%
GM@
C1291 0.1U_0402_16V7K PM@
C1291 0.1U_0402_16V7K PM@
U2C
CANTIGA ES_FCBGA1329 GM@
U2C
CANTIGA ES_FCBGA1329 GM@
L_BKLT_CTRL
L32
L_BKLT_EN
G32
L_CTRL_CLK
M32
L_CTRL_DATA
M33
L_DDC_CLK
K33
L_DDC_DATA
J33
L_VDD_EN
M29
LVDS_IBG
C44
LVDS_VBG
B43
LVDS_VREFH
E37
LVDS_VREFL
E38
LVDSA_CLK#
C41
LVDSA_CLK
C40
LVDSB_CLK#
B37
LVDSB_CLK
A37
LVDSA_DATA#_0
H47
LVDSA_DATA#_1
E46
LVDSA_DATA#_2
G40
LVDSA_DATA#_3
A40
LVDSA_DATA_0
H48
LVDSA_DATA_1
D45
LVDSA_DATA_2
F40
LVDSA_DATA_3
B40
LVDSB_DATA#_0
A41
LVDSB_DATA#_1
H38
LVDSB_DATA#_2
G37
LVDSB_DATA#_3
J37
LVDSB_DATA_0
B42
LVDSB_DATA_1
G38
LVDSB_DATA_2
F37
LVDSB_DATA_3
K37
TVA_DAC
F25
TVB_DAC
H25
TVC_DAC
K25
TV_RTN
H24
TV_DCONSEL_0
C31
TV_DCONSEL_1
E32
CRT_BLUE
E28
CRT_GREEN
G28
CRT_RED
J28
CRT_IRTN
G29
CRT_DDC_CLK
H32
CRT_DDC_DATA
J32
CRT_HSYNC
J29
CRT_TVO_IREF
E29
CRT_VSYNC
L29
C1320 0.1U_0402_16V7K PM@
C1320 0.1U_0402_16V7K PM@
R1161 150_0402_1%
GM@
R1161 150_0402_1%
GM@
1 2
GM@
GM@
C1289 0.1U_0402_16V7K PM@
C1289 0.1U_0402_16V7K PM@
R1153 0_0402_5%
GM@
R1153 0_0402_5%
GM@
1 2
C1303 0.1U_0402_16V7K PM@
C1303 0.1U_0402_16V7K PM@
C1304 0.1U_0402_16V7K PM@
C1304 0.1U_0402_16V7K PM@
C1311 0.1U_0402_16V7K PM@
C1311 0.1U_0402_16V7K PM@
C1317 0.1U_0402_16V7K PM@
C1317 0.1U_0402_16V7K PM@
C1313 0.1U_0402_16V7K PM@
C1313 0.1U_0402_16V7K PM@
C1299 0.1U_0402_16V7K PM@
C1299 0.1U_0402_16V7K PM@
C1302 0.1U_0402_16V7K PM@
C1302 0.1U_0402_16V7K PM@
C1290 0.1U_0402_16V7K PM@
C1290 0.1U_0402_16V7K PM@
C1306 0.1U_0402_16V7K PM@
C1306 0.1U_0402_16V7K PM@
C1309 0.1U_0402_16V7K PM@
C1309 0.1U_0402_16V7K PM@
C1310 0.1U_0402_16V7K PM@
C1310 0.1U_0402_16V7K PM@
C1316 0.1U_0402_16V7K PM@
C1316 0.1U_0402_16V7K PM@
R93
75_0402_1%
GM@
R93
75_0402_1%
GM@
PM@
C1294 0.1U_0402_16V7K PM@
R1159 150_0402_1%
GM@
R1159 150_0402_1%
GM@
1 2
GM@
GM@
C1305 0.1U_0402_16V7K PM@
C1305 0.1U_0402_16V7K PM@
C1297 0.1U_0402_16V7K PM@
C1297 0.1U_0402_16V7K PM@
GM@
GM@
C1312 0.1U_0402_16V7K PM@
C1312 0.1U_0402_16V7K PM@
C1293 0.1U_0402_16V7K PM@
C1293 0.1U_0402_16V7K PM@
GM@
GM@
C1300 0.1U_0402_16V7K PM@
C1300 0.1U_0402_16V7K PM@
R107
75_0402_1%
GM@
R107
75_0402_1%
GM@
C1319 0.1U_0402_16V7K PM@
C1319 0.1U_0402_16V7K PM@
C1292 0.1U_0402_16V7K PM@
C1292 0.1U_0402_16V7K PM@
R1160 150_0402_1%
GM@
R1160 150_0402_1%
GM@
1 2
GM@
GM@
C1296 0.1U_0402_16V7K PM@
C1296 0.1U_0402_16V7K PM@
C1314 0.1U_0402_16V7K PM@
C1314 0.1U_0402_16V7K PM@
C1315 0.1U_0402_16V7K PM@
C1315 0.1U_0402_16V7K PM@
R11731 2 100K_0402_5%
C1308 0.1U_0402_16V7K PM@
C1308 0.1U_0402_16V7K PM@
R1155 2.37K_0402_1%
GM@
R1155 2.37K_0402_1%
GM@
GM@
GM@
PM@
PM@
1 2
R108
75_0402_1%
GM@
R108
75_0402_1%
GM@
C1307 0.1U_0402_16V7K PM@
C1307 0.1U_0402_16V7K PM@
C1318 0.1U_0402_16V7K PM@
C1318 0.1U_0402_16V7K PM@
PM@
PM@
1 2
C1301 0.1U_0402_16V7K PM@
C1301 0.1U_0402_16V7K PM@
C1298 0.1U_0402_16V7K PM@
C1298 0.1U_0402_16V7K PM@
C1295 0.1U_0402_16V7K PM@
C1295 0.1U_0402_16V7K PM@