A B C D E 1 Compal Confidential 2 HCW50 Schematics Document AMD/Sempron/ATI RX485/SB460 W/s M52/54/56P 2006 / 02 / 28 Rev:0.3 (For PVT) 3 4 Compal Secret Data Security Classification 2005/05/09 Issued Date Deciphered Date 2006/03/08 B C Compal Electronics, inc SCHEMATIC, M/B LA-3151P THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A Title D Size Document Number Custom 401412 Date: , 09, 2006 Rev B Sheet E of 55 Compal confidential Project Code: HCW50 File Name : LA-3151P Thermal Sensor ADM1032ARM AMD Turion/Sempron CPU Socket S1 638P Clock Generator ICS951462 DDRII DDRII-SO-DIMM X2 page 9,10 page 5,6,7,8 page D Dual Channel DDR-II page 15 D H_A#(3 31) H_D#(0 63) HT 16x16 800MHZ DVI-D Conn LCD CONN page 30 page 29 CRT & TV-OUT ATI-RX485M page 28 465 BGA page 11,12,13,14 A-Link Express x PCIE PCI-Express ATI M52PG/M54P/M56P USB conn x / New card USB 2.0 with 64/128/256MB VRAM C page 39 page 16,17,18,19,20,21 ATI-SB460 BT Conn USB 2.0 page 34 549 BGA PCI BUS Audio CKT ALC883 AC-LINK Mini PCI Socket Mini card / CAM page 36 page 22,23,24,25,26 Realtek RTL8100CL RTL8110SCL ENE Controller CB714 page 31 1394 Controller VT6311S page 32 B 6in1 CardReader page 38 Slot page 38 page 45 MDC Conn page 34 page 40 page 37 Slot AMP & Audio Jack page 44 SATA HDD Conn SATA RJ45 CONN C page 27 LPC BUS 1394 Conn B page 40 PATA One Channel HDD Conn CDROM Conn page 27 Power On/Off CKT / LID switch / Power OK CKT page 42 DC/DC Interface CKT page 46 SMsC LPC47N207 CIR/LED RTC CKT page 43 ENE KB910 page 41 page 33 page 22 Power Circuit DC/DC Int KBD FIR module page 34 page 41 page 46~ Touch Pad CONN.page 34 BIOS page 35 A Compal Secret Data Security Classification 2005/03/08 Issued Date 2006/03/08 Deciphered Date Title Compal Electronics, inc SCHEMATIC, M/B LA-3151P THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A Size Document Number Custom 401412 Date: , R ev B Sheet 09, 2006 of 55 SIGNAL STATE Voltage Rails D C Full ON SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock HIGH HIGH HIGH HIGH ON ON ON ON Power Plane Description S0 S3 S5 S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW VIN Adapter power supply (19V) N/A N/A N/A S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF B+ AC or battery power rail for power circuit N/A N/A N/A +CPU_CORE Core voltage for CPU ON OFF OFF S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF +0.9V 0.9V switched power rail for DDRII terminator ON ON OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF +1.2V_HT 1.2V switched power rail ON OFF OFF +1.5VS 1.5V switched power rail ON OFF OFF +1.8V 1.8V power rail for DDRII ON ON OFF +1.8VS 1.8V switched power rail ON OFF OFF +2.5VS 2.5V switched power rail ON OFF OFF Vcc Ra/Rc/Re +3VALW 3.3V always on power rail ON ON ON* Board ID +3VS 3.3V switched power rail ON OFF OFF +5VALW 5V always on power rail ON ON ON* +5VS 5V switched power rail ON OFF OFF +VSB VSB always on power rail ON ON ON* +RTCVCC RTC power ON ON ON* +1.2VS 1.2V switched power rail for PCIE ON OFF OFF +0.9VS 0.9V switched power rail for VRAM terminator ON OFF OFF +1.8VALW 1.8V switched power rail ON ON ON* +VDD_CORE 1.0~1.2V switched power rail for VGA ON OFF OFF D Board ID / SKU ID Table for AD channel Board ID External PCI Devices IDSEL# Ca rdBus(SD) REQ#/GNT# Interrupts AD20 PIRQE/PIRQH 394 AD16 PIRQE LAN(10/100) AD17 PIRQF Mini-PCI(WLAN/TV-Tuner) AD18 PIRQG/PORQH V AD_BID V 0.216 V 0.436 V 0.712 V 1.036 V 1.453 V 1.935 V 2.500 V V AD_BID typ V 0.250 V 0.503 V 0.819 V 1.185 V 1.650 V 2.200 V 3.300 V BOARD ID Table Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF Device 3.3V +/- 5% 100K +/- 5% Rb / Rd / Rf 8.2K +/- 5% 18K +/- 5% 33K +/- 5% 56K +/- 5% 100K +/- 5% 200K +/- 5% NC PCB Revision 0.1 BTO Item VGA UMA UMA's DVI LAN(10/100) LAN(GIGA) MINI CARD1 MINI CARD2 SATA-to-IDE PATA GRAPEVINE G72MV Only G73 Only VRAM VRAM 64M VRAM 128M VRAM 256M MEDIA/B CIR FIR GENEVA LCM Sub-woofer Device Address Smart Battery 0001 011X b EEPROM(24C16/02) 1010 000X b GMT G781-1 1001 101X b SKU ID Table EC SM Bus2 address Device Fintek F75383M SKU ID Address 1001 100X b SB460 SM Bus address A Device Address Clock Generator (ICS9LPRS325AKLFT_MLF72) 1101 001Xb DDR DIMM0 1001 000Xb DDR DIMM2 1001 010Xb SKU PM GM BOM Structure B A Compal Secret Data Security Classification 2005/03/08 Issued Date 2006/03/08 Deciphered Date Title Compal Electronics, inc SCHEMATIC, M/B LA-3151P THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC C BTO Option Table B EC SM Bus1 address V AD_BID max V 0.289 V 0.538 V 0.875 V 1.264 V 1.759 V 2.341 V 3.300 V Size Document Number Custom 401412 Date: , R ev B Sheet 09, 2006 of 55 +5V BATTERY CHARGER BATTERY +3.3VSUS_NTB +VDC MAIN PWR SW REGULATOR VCCA 2.5V 12V +/-5% +5V_NTB +VIN_MEM +5VSUS 5VSB +/-5% +5VALW_ATX POWER SWITCH SWITCH CPU PWR 12V +/-5% SWITCH +3.3V_NTB +3.3VALW NB CORE 10A +VIN PCIE&SB SW REGULATOR VDDA_1V2(S0, S1) PCI-E CORE &PCI-E IO 3.5A HTPLL (1.8V) 200mA +5V 1.8V SW REGULATOR +1.8V(S0, S1) PLL & DAC-Q(1.8V) 200mA TRANSFORMER 400mA DAC 300mA +3.3V +5V +3.3V AVDD (S0, S1) +5VDUAL_ATX SW +5V_ATX +3.3VALW LDO REGULATOR +5VSUS DDRII SODIMMX2 +VIN +3.3VALW_ATX +5V +3.3VDUAL_ATX SW CPU_VDDIO_SUS (S0, S1, S3) 1.8V VDD&VTT SW REGULATOR +5VSUS VDD MEM 4A CPU_VTT_SUS (S0, S1,S3) VCC_SB (S0, S1) 5V +/-5% D NB RS485 VCC_NB (S0, S1) NB CORE SW REGULATOR +5V +5VALW 3.3V +/-5% VLDT 1.2V 3A HT VLDT 1.2V 1A +VIN +3.3VSUS VDDCORE 0.375-1.500V 30A VLDT_RUN (S0, S1) VLDT 1.2V SW REGULATOR +5V ATX POWER SUPPLY CPU_VDD_RUN (S0, S1) SW REGULATOR +VIN +5VSUS_NTB D +3.3V_ATX -12V +/-5% C AMD CPU +VIN +5V +5VALW_NTB SW CPU_VDDA_RUN (S0, S1) 1.5V SW REGULATOR +3.3VALW_NTB VTT_MEM 0.5A C SB SB600 X4 PCI-E 0.8A ATA I/O 0.2A ATA PLL 0.01A PCI-E PVDD 80mA SB CORE 0.6A CONTROL SIGNAL: +3.3VALW 1.2V LDO REGULATOR +1.2VALW 1.2V S5 PW 0.22A MOBILE: BATTERY +3.3V DESKTOP: ATX +3.3VALW 3.3V S5 PW 0.01A +5V USB CORE I/O 0.2A B 3.3V I/O 0.45A MINI PCI SLOT GBIT ENTHENET +3.3V 3.3V(S0, S1)1.5A +5V 5V (S0, S1) 0.1A 3.3V 0.5A (S0, S1, S3, S4, S5) +3.3VALW 3.3V(S3, S5) 0.2A +VIN B PCI-E CARD 1.5V (S0, S1) 0.7A 3.3V (S3, S5) 0.3A +3.3V 3.3V (S0, S1) 1.3A +5V PCI Slot (per slot) 5V 5.0A 3.3V 7.6A 12V 0.5A 3.3Vaux 0.375A -12V 0.1A X1 PCIE per 3.3V 12V 3.0A 0.5A 3.3Vaux 0.1A X16 PCIE 3.3V 12V 3.0A 5.5A SUPER I/O +5VALW CNR CONNECTOR +3.3VDUAL (S3) 0.01A 5V 1.0A 3.3V 1.0A 12V 0.5A VDD VDD 3.3Vaux 1.0A 5VDual 5VDual -12V 0.1A 3.5A 1.0A 5VDual 0.5A USB X7 FR USB X2 RL +3.3V (S0, S1) 0.01A 2XPS/2 +5V (S0, S1) 0.1A 5VDual HD CODEC 1.0A 3.3V CORE 0.3A 5V ANALOG 0.1A A A Compal Secret Data Security Classification 2005/03/08 Issued Date 2006/03/08 Deciphered Date Compal Electronics, inc SCHEMATIC, M/B LA-3151P THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Size Document Number Custom 401412 Date: , R ev B Sheet 09, 2006 of 55 H_CADIP[0 15] H_CADIN[0 15] H_CADIP[0 15] H_CADIN[0 15] H_CADOP[0 15] H_CADON[0 15] H_CADOP[0 15] H_CADON[0 15] PROCESSOR HYPERTRANSPORT INTERFACE D D VLDT_Ax AND VLDT_Bx ARE CONNECTED TO THE LDT_RUN POWER SUPPLY THROUGH THE PACKAGE OR ON THE DIE IT IS ONLY CONNECTED ON THE BOARD TO DECOUPLING NEAR THE CPU PACKAGE FAN1 Conn +1.2V_HT JP72A VLDT_A3 VLDT_A2 VLDT_A1 VLDT_A0 H_CADIP15 H_CADIN15 H_CADIP14 H_CADIN14 H_CADIP13 H_CADIN13 H_CADIP12 H_CADIN12 H_CADIP11 H_CADIN11 H_CADIP10 H_CADIN10 H_CADIP9 H_CADIN9 H_CADIP8 H_CADIN8 H_CADIP7 H_CADIN7 H_CADIP6 H_CADIN6 H_CADIP5 H_CADIN5 H_CADIP4 H_CADIN4 H_CADIP3 H_CADIN3 H_CADIP2 H_CADIN2 H_CADIP1 H_CADIN1 H_CADIP0 H_CADIN0 N5 P5 M3 M4 L5 M5 K3 K4 H3 H4 G5 H5 F3 F4 E5 F5 N3 N2 L1 M1 L3 L2 J1 K1 G1 H1 G3 G2 E1 F1 E3 E2 L0_CADIN_H15 L0_CADIN_L15 L0_CADIN_H14 L0_CADIN_L14 L0_CADIN_H13 L0_CADIN_L13 L0_CADIN_H12 L0_CADIN_L12 L0_CADIN_H11 L0_CADIN_L11 L0_CADIN_H10 L0_CADIN_L10 L0_CADIN_H9 L0_CADIN_L9 L0_CADIN_H8 L0_CADIN_L8 L0_CADIN_H7 L0_CADIN_L7 L0_CADIN_H6 L0_CADIN_L6 L0_CADIN_H5 L0_CADIN_L5 L0_CADIN_H4 L0_CADIN_L4 L0_CADIN_H3 L0_CADIN_L3 L0_CADIN_H2 L0_CADIN_L2 L0_CADIN_H1 L0_CADIN_L1 L0_CADIN_H0 L0_CADIN_L0 H_CLKIP1 H_CLKIN1 H_CLKIP0 H_CLKIN0 J5 K5 J3 J2 L0_CLKIN_H1 L0_CLKIN_L1 L0_CLKIN_H0 L0_CLKIN_L0 H_CTLIP1 H_CTLIN1 P3 P4 H_CTLIP0 H_CTLIN0 N1 P1 C1 4.7U_0805_10V4Z VLDT_B3 VLDT_B2 VLDT_B1 VLDT_B0 AE5 AE4 AE3 AE2 L0_CADOUT_H15 L0_CADOUT_L15 L0_CADOUT_H14 L0_CADOUT_L14 L0_CADOUT_H13 L0_CADOUT_L13 L0_CADOUT_H12 L0_CADOUT_L12 L0_CADOUT_H11 L0_CADOUT_L11 L0_CADOUT_H10 L0_CADOUT_L10 L0_CADOUT_H9 L0_CADOUT_L9 L0_CADOUT_H8 L0_CADOUT_L8 L0_CADOUT_H7 L0_CADOUT_L7 L0_CADOUT_H6 L0_CADOUT_L6 L0_CADOUT_H5 L0_CADOUT_L5 L0_CADOUT_H4 L0_CADOUT_L4 L0_CADOUT_H3 L0_CADOUT_L3 L0_CADOUT_H2 L0_CADOUT_L2 L0_CADOUT_H1 L0_CADOUT_L1 L0_CADOUT_H0 L0_CADOUT_L0 T4 T3 V5 U5 V4 V3 Y5 W5 AB5 AA5 AB4 AB3 AD5 AC5 AD4 AD3 T1 R1 U2 U3 V1 U1 W2 W3 AA2 AA3 AB1 AA1 AC2 AC3 AD1 AC1 H_CADOP15 H_CADON15 H_CADOP14 H_CADON14 H_CADOP13 H_CADON13 H_CADOP12 H_CADON12 H_CADOP11 H_CADON11 H_CADOP10 H_CADON10 H_CADOP9 H_CADON9 H_CADOP8 H_CADON8 H_CADOP7 H_CADON7 H_CADOP6 H_CADON6 H_CADOP5 H_CADON5 H_CADOP4 H_CADON4 H_CADOP3 H_CADON3 H_CADOP2 H_CADON2 H_CADOP1 H_CADON1 H_CADOP0 H_CADON0 L0_CLKOUT_H1 L0_CLKOUT_L1 L0_CLKOUT_H0 L0_CLKOUT_L0 Y4 Y3 Y1 W1 H_CLKOP1 H_CLKON1 H_CLKOP0 H_CLKON0 H_CLKOP1 H_CLKON1 H_CLKOP0 H_CLKON0 L0_CTLIN_H1 L0_CTLIN_L1 L0_CTLOUT_H1 L0_CTLOUT_L1 T5 R5 L0_CTLIN_H0 L0_CTLIN_L0 L0_CTLOUT_H0 L0_CTLOUT_L0 R2 R3 H_CTLOP0 H_CTLON0 H_CTLOP0 H_CTLON0 +5VS C2 +5VS 10U_0805_10V4Z D4 D3 D2 D1 +1.2V_HT R2 R3 H_CLKIP1 H_CLKIN1 H_CLKIP0 H_CLKIN0 51_0402_1% 51_0402_1% H_CTLIP0 H_CTLIN0 B EN_DFAN1 GND GND GND GND D1 1SS355_SOD323 +VCC_FAN1 EN_DFAN1 VEN VIN VO VSET G993P1UF_SOP8 D2 1N4148_SOT23 C3 10U_0805_10V4Z +3VS C4 1000P_0402_50V7K C R1 10K_0402_5% 40mil C U2 JP73 +VCC_FAN1 FAN_SPEED1 C5 1000P_0402_50V7K ACES_85205-03001 B Athlon 64 S1 Processor Socket +1.2V_HT C6 C8 10U_0805_10V4Z C9 C10 2 0.22U_0603_10V7K 180P_0402_50V8J 0.22U_0603_10V7K C11 180P_0402_50V8J LAYOUT: Place bypass cap on topside of board NEAR HT POWER PINS THAT ARE NOT CONNECTED DIRECTLY TO DOWNSTREAM HT DEVICE, BUT CONNECTED INTERNALLY TO OTHER HT POWER PINS PLACE CLOSE TO VLDT0 POWER PINS A A Compal Secret Data Security Classification 2005/10/11 Issued Date 2006/10/11 Deciphered Date Compal Electronics, inc SCHEMATIC, M/B LA-3151P THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Size Document Number Custom 401412 Date: , R ev B Sheet 09, 2006 of 55 B C DDR_A_MA[0 15] DDR_A_MA[0 15] DDR_B_DQS#[0 7] DDR_B_DQS#[0 7] DDR_B_D[0 63] JP72C +0.9VREF_CPU +0.9V JP72B AE10 AF10 VTT_SENSE M_ZN M_ZP R5 39.2_0402_1%~D DDR_CS3_DIMMA# DDR_CS2_DIMMA# DDR_CS1_DIMMA# DDR_CS0_DIMMA# VTT1 VTT2 VTT3 VTT4 VTT5 VTT6 VTT7 VTT8 VTT9 D10 C10 B10 AD10 W10 AC10 AB10 AA10 A10 DDR_A_CLK2 DDR_A_CLK#2 DDR_A_CLK1 DDR_A_CLK#1 V19 J22 V22 T19 MA0_CS_L3 MA0_CS_L2 MA0_CS_L1 MA0_CS_L0 MA0_CLK_H2 MA0_CLK_L2 MA0_CLK_H1 MA0_CLK_L1 Y16 AA16 E16 F16 DDR_CS3_DIMMB# DDR_CS2_DIMMB# DDR_CS1_DIMMB# DDR_CS3_DIMMB# Y26 DDR_CS2_DIMMB# J24 DDR_CS1_DIMMB# W24 DDR_CS0_DIMMB# U23 MB0_CS_L3 MB0_CS_L2 MB0_CS_L1 MB0_CS_L0 MB0_CLK_H2 MB0_CLK_L2 MB0_CLK_H1 MB0_CLK_L1 AF18 DDR_B_CLK2 AF17 DDR_B_CLK#2 A17 DDR_B_CLK1 A18 DDR_B_CLK#1 DDR_CKE1_DIMMB DDR_CKE0_DIMMB DDR_CKE1_DIMMA DDR_CKE0_DIMMA H26 J23 J20 J21 MB_CKE1 MB_CKE0 MA_CKE1 MA_CKE0 MB0_ODT1 MB0_ODT0 MA0_ODT1 MA0_ODT0 W23 W26 V20 U19 DDR_B_ODT1 DDR_B_ODT0 DDR_A_ODT1 DDR_A_ODT0 DDR_A_MA15 DDR_A_MA14 DDR_A_MA13 DDR_A_MA12 DDR_A_MA11 DDR_A_MA10 DDR_A_MA9 DDR_A_MA8 DDR_A_MA7 DDR_A_MA6 DDR_A_MA5 DDR_A_MA4 DDR_A_MA3 DDR_A_MA2 DDR_A_MA1 DDR_A_MA0 K19 K20 V24 K24 L20 R19 L19 L22 L21 M19 M20 M24 M22 N22 N21 R21 MA_ADD15 MA_ADD14 MA_ADD13 MA_ADD12 MA_ADD11 MA_ADD10 MA_ADD9 MA_ADD8 MA_ADD7 MA_ADD6 MA_ADD5 MA_ADD4 MA_ADD3 MA_ADD2 MA_ADD1 MA_ADD0 MB_ADD15 MB_ADD14 MB_ADD13 MB_ADD12 MB_ADD11 MB_ADD10 MB_ADD9 MB_ADD8 MB_ADD7 MB_ADD6 MB_ADD5 MB_ADD4 MB_ADD3 MB_ADD2 MB_ADD1 MB_ADD0 J25 J26 W25 L23 L25 U25 L24 M26 L26 N23 N24 N25 N26 P24 P26 T24 DDR_B_MA15 DDR_B_MA14 DDR_B_MA13 DDR_B_MA12 DDR_B_MA11 DDR_B_MA10 DDR_B_MA9 DDR_B_MA8 DDR_B_MA7 DDR_B_MA6 DDR_B_MA5 DDR_B_MA4 DDR_B_MA3 DDR_B_MA2 DDR_B_MA1 DDR_B_MA0 DDR_A_BS#2 DDR_A_BS#1 DDR_A_BS#0 DDR_A_BS#2 DDR_A_BS#1 DDR_A_BS#0 K22 R20 T22 MA_BANK2 MA_BANK1 MA_BANK0 MB_BANK2 MB_BANK1 MB_BANK0 K26 DDR_B_BS#2 T26 DDR_B_BS#1 U26 DDR_B_BS#0 DDR_B_BS#2 DDR_B_BS#1 DDR_B_BS#0 DDR_A_RAS# DDR_A_CAS# DDR_A_WE# DDR_A_RAS# DDR_A_CAS# DDR_A_WE# T20 U20 U21 MB_RAS_L MB_CAS_L MB_WE_L U24 DDR_B_RAS# V26 DDR_B_CAS# U22 DDR_B_WE# DDR_B_RAS# DDR_B_CAS# DDR_B_WE# 2 Y10 M_ZN M_ZP M_VREF DDR_CS3_DIMMA# DDR_CS2_DIMMA# DDR_CS1_DIMMA# DDR_CS0_DIMMA# PLACE THEM CLOSE TO DDR_CS0_DIMMB# CPU WITHIN 1" DDR_CKE1_DIMMB DDR_CKE0_DIMMB DDR_CKE1_DIMMA DDR_CKE0_DIMMA MA_RAS_L MA_CAS_L MA_WE_L DDR_A_CLK2 DDR_A_CLK#2 DDR_A_CLK1 DDR_A_CLK#1 DDR_B_CLK2 DDR_B_CLK#2 DDR_B_CLK1 DDR_B_CLK#1 DDR_B_ODT1 DDR_B_ODT0 DDR_A_ODT1 DDR_A_ODT0 DDR_B_MA[0 15] Athlon 64 S1 Processor Socket DDR_B_DM[0 7] DDR_A_CLK2 DDR_B_CLK2 DDR_A_CLK#2 C12 1.5P_0402_50V8C DDR_B_CLK#2 DDR_A_CLK1 C13 1.5P_0402_50V8C C14 1.5P_0402_50V8C DDR_B_CLK#1 PLACE CLOSE TO PROCESSOR WITHIN 1.5 INCH 2 DDR_B_CLK1 DDR_A_CLK#1 To reverse SODIMM socket W17 R4 39.2_0402_1%~D DDR_A_DQS[0 7] DDR_A_DQS[0 7] DDR_A_DQS#[0 7] DDR_A_DQS#[0 7] +1.8V E Processor DDR2 Memory Interface DDR_B_DQS[0 7] DDR_B_DQS[0 7] VDD_VTT_SUS_CPU IS CONNECTED TO THE VDD_VTT_SUS POWER SUPPLY THROUGH THE PACKAGE OR ON THE DIE IT IS ONLY CONNECTED ON THE BOARD TO DECOUPLING NEAR THE CPU PACKAGE D C15 1.5P_0402_50V8C PLACE CLOSE TO PROCESSOR WITHIN 1.5 INCH DDR_B_D63 DDR_B_D62 DDR_B_D61 DDR_B_D60 DDR_B_D59 DDR_B_D58 DDR_B_D57 DDR_B_D56 DDR_B_D55 DDR_B_D54 DDR_B_D53 DDR_B_D52 DDR_B_D51 DDR_B_D50 DDR_B_D49 DDR_B_D48 DDR_B_D47 DDR_B_D46 DDR_B_D45 DDR_B_D44 DDR_B_D43 DDR_B_D42 DDR_B_D41 DDR_B_D40 DDR_B_D39 DDR_B_D38 DDR_B_D37 DDR_B_D36 DDR_B_D35 DDR_B_D34 DDR_B_D33 DDR_B_D32 DDR_B_D31 DDR_B_D30 DDR_B_D29 DDR_B_D28 DDR_B_D27 DDR_B_D26 DDR_B_D25 DDR_B_D24 DDR_B_D23 DDR_B_D22 DDR_B_D21 DDR_B_D20 DDR_B_D19 DDR_B_D18 DDR_B_D17 DDR_B_D16 DDR_B_D15 DDR_B_D14 DDR_B_D13 DDR_B_D12 DDR_B_D11 DDR_B_D10 DDR_B_D9 DDR_B_D8 DDR_B_D7 DDR_B_D6 DDR_B_D5 DDR_B_D4 DDR_B_D3 DDR_B_D2 DDR_B_D1 DDR_B_D0 AD11 AF11 AF14 AE14 Y11 AB11 AC12 AF13 AF15 AF16 AC18 AF19 AD14 AC14 AE18 AD18 AD20 AC20 AF23 AF24 AF20 AE20 AD22 AC22 AE25 AD26 AA25 AA26 AE24 AD24 AA23 AA24 G24 G23 D26 C26 G26 G25 E24 E23 C24 B24 C20 B20 C25 D24 A21 D20 D18 C18 D14 C14 A20 A19 A16 A15 A13 D12 E11 G11 B14 A14 A11 C11 MB_DATA63 MB_DATA62 MB_DATA61 MB_DATA60 MB_DATA59 MB_DATA58 MB_DATA57 MB_DATA56 MB_DATA55 MB_DATA54 MB_DATA53 MB_DATA52 MB_DATA51 MB_DATA50 MB_DATA49 MB_DATA48 MB_DATA47 MB_DATA46 MB_DATA45 MB_DATA44 MB_DATA43 MB_DATA42 MB_DATA41 MB_DATA40 MB_DATA39 MB_DATA38 MB_DATA37 MB_DATA36 MB_DATA35 MB_DATA34 MB_DATA33 MB_DATA32 MB_DATA31 MB_DATA30 MB_DATA29 MB_DATA28 MB_DATA27 MB_DATA26 MB_DATA25 MB_DATA24 MB_DATA23 MB_DATA22 MB_DATA21 MB_DATA20 MB_DATA19 MB_DATA18 MB_DATA17 MB_DATA16 MB_DATA15 MB_DATA14 MB_DATA13 MB_DATA12 MB_DATA11 MB_DATA10 MB_DATA9 MB_DATA8 MB_DATA7 MB_DATA6 MB_DATA5 MB_DATA4 MB_DATA3 MB_DATA2 MB_DATA1 MB_DATA0 DDR_B_DM7 DDR_B_DM6 DDR_B_DM5 DDR_B_DM4 DDR_B_DM3 DDR_B_DM2 DDR_B_DM1 DDR_B_DM0 AD12 AC16 AE22 AB26 E25 A22 B16 A12 MB_DM7 MB_DM6 MB_DM5 MB_DM4 MB_DM3 MB_DM2 MB_DM1 MB_DM0 DDR_B_DQS7 DDR_B_DQS#7 DDR_B_DQS6 DDR_B_DQS#6 DDR_B_DQS5 DDR_B_DQS#5 DDR_B_DQS4 DDR_B_DQS#4 DDR_B_DQS3 DDR_B_DQS#3 DDR_B_DQS2 DDR_B_DQS#2 DDR_B_DQS1 DDR_B_DQS#1 DDR_B_DQS0 DDR_B_DQS#0 AF12 AE12 AE16 AD16 AF21 AF22 AC25 AC26 F26 E26 A24 A23 D16 C16 C12 B12 MB_DQS_H7 MB_DQS_L7 MB_DQS_H6 MB_DQS_L6 MB_DQS_H5 MB_DQS_L5 MB_DQS_H4 MB_DQS_L4 MB_DQS_H3 MB_DQS_L3 MB_DQS_H2 MB_DQS_L2 MB_DQS_H1 MB_DQS_L1 MB_DQS_H0 MB_DQS_L0 MA_DATA63 MA_DATA62 MA_DATA61 MA_DATA60 MA_DATA59 MA_DATA58 MA_DATA57 MA_DATA56 MA_DATA55 MA_DATA54 MA_DATA53 MA_DATA52 MA_DATA51 MA_DATA50 MA_DATA49 MA_DATA48 MA_DATA47 MA_DATA46 MA_DATA45 MA_DATA44 MA_DATA43 MA_DATA42 MA_DATA41 MA_DATA40 MA_DATA39 MA_DATA38 MA_DATA37 MA_DATA36 MA_DATA35 MA_DATA34 MA_DATA33 MA_DATA32 MA_DATA31 MA_DATA30 MA_DATA29 MA_DATA28 MA_DATA27 MA_DATA26 MA_DATA25 MA_DATA24 MA_DATA23 MA_DATA22 MA_DATA21 MA_DATA20 MA_DATA19 MA_DATA18 MA_DATA17 MA_DATA16 MA_DATA15 MA_DATA14 MA_DATA13 MA_DATA12 MA_DATA11 MA_DATA10 MA_DATA9 MA_DATA8 MA_DATA7 MA_DATA6 MA_DATA5 MA_DATA4 MA_DATA3 MA_DATA2 MA_DATA1 MA_DATA0 AA12 AB12 AA14 AB14 W11 Y12 AD13 AB13 AD15 AB15 AB17 Y17 Y14 W14 W16 AD17 Y18 AD19 AD21 AB21 AB18 AA18 AA20 Y20 AA22 Y22 W21 W22 AA21 AB22 AB24 Y24 H22 H20 E22 E21 J19 H24 F22 F20 C23 B22 F18 E18 E20 D22 C19 G18 G17 C17 F14 E14 H17 E17 E15 H15 E13 C13 H12 H11 G14 H14 F12 G12 DDR_A_D63 DDR_A_D62 DDR_A_D61 DDR_A_D60 DDR_A_D59 DDR_A_D58 DDR_A_D57 DDR_A_D56 DDR_A_D55 DDR_A_D54 DDR_A_D53 DDR_A_D52 DDR_A_D51 DDR_A_D50 DDR_A_D49 DDR_A_D48 DDR_A_D47 DDR_A_D46 DDR_A_D45 DDR_A_D44 DDR_A_D43 DDR_A_D42 DDR_A_D41 DDR_A_D40 DDR_A_D39 DDR_A_D38 DDR_A_D37 DDR_A_D36 DDR_A_D35 DDR_A_D34 DDR_A_D33 DDR_A_D32 DDR_A_D31 DDR_A_D30 DDR_A_D29 DDR_A_D28 DDR_A_D27 DDR_A_D26 DDR_A_D25 DDR_A_D24 DDR_A_D23 DDR_A_D22 DDR_A_D21 DDR_A_D20 DDR_A_D19 DDR_A_D18 DDR_A_D17 DDR_A_D16 DDR_A_D15 DDR_A_D14 DDR_A_D13 DDR_A_D12 DDR_A_D11 DDR_A_D10 DDR_A_D9 DDR_A_D8 DDR_A_D7 DDR_A_D6 DDR_A_D5 DDR_A_D4 DDR_A_D3 DDR_A_D2 DDR_A_D1 DDR_A_D0 MA_DM7 MA_DM6 MA_DM5 MA_DM4 MA_DM3 MA_DM2 MA_DM1 MA_DM0 Y13 AB16 Y19 AC24 F24 E19 C15 E12 DDR_A_DM7 DDR_A_DM6 DDR_A_DM5 DDR_A_DM4 DDR_A_DM3 DDR_A_DM2 DDR_A_DM1 DDR_A_DM0 MA_DQS_H7 MA_DQS_L7 MA_DQS_H6 MA_DQS_L6 MA_DQS_H5 MA_DQS_L5 MA_DQS_H4 MA_DQS_L4 MA_DQS_H3 MA_DQS_L3 MA_DQS_H2 MA_DQS_L2 MA_DQS_H1 MA_DQS_L1 MA_DQS_H0 MA_DQS_L0 W12 W13 Y15 W15 AB19 AB20 AD23 AC23 G22 G21 C22 C21 G16 G15 G13 H13 DDR_A_DQS7 DDR_A_DQS#7 DDR_A_DQS6 DDR_A_DQS#6 DDR_A_DQS5 DDR_A_DQS#5 DDR_A_DQS4 DDR_A_DQS#4 DDR_A_DQS3 DDR_A_DQS#3 DDR_A_DQS2 DDR_A_DQS#2 DDR_A_DQS1 DDR_A_DQS#1 DDR_A_DQS0 DDR_A_DQS#0 DDR_A_D[0 63] To normal SODIMM socket A DDR_A_DM[0 7] DDR: DATA Athlon 64 S1 Processor Socket ATI check ,Use +0.9V PWR , can delete or not A1 A26 +1.8V Athlon 64 S1g1 R6 1K_0402_1% uPGA638 +0.9VREF_CPU Top View 1 +0.9VREF_CPU 1000P_0402_50V7K C16 C18 1 2 C19 C20 AF1 R7 1K_0402_1% 0.1U_0402_16V4Z 1U_0402_6.3V4Z 1000P_0402_50V7K VDD_VREF_SUS_CPU LAYOUT:PLACE CLOSE TO CPU Compal Secret Data Security Classification Issued Date 2005/10/11 Deciphered Date 2006/10/11 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C D Title Compal Electronics, inc SCHEMATIC, M/B LA-3151P Size Document Number Custom 401412 Date: , Rev B 09, 2006 Sheet E of 55 ATHLON Control and Debug +1.8V LAYOUT: ROUTE VDDA TRACE APPROX 50 mils WIDE (USE 2x25 mil TRACES TO EXIT BALL FIELD) AND 500 mils LONG R8 +2.5VS 1 C22 4.7U_0805_10V4Z D F8 F9 C23 0.22U_0603_10V7K CPU_HT_RESET# CPU_ALL_PWROK CPU_LDTSTOP# C24 3300P_0402_50V7K R10 SB460 ONLY R12 R13 +1.2V_HT CPU_SIC_R 300_0402_5% 1 CPU_HTREF1 CPU_HTREF0 44.2_0603_1% 44.2_0603_1% place them to CPU within 1" +1.8VS +1.8V PAD PAD R15 P A C27 CPUCLK# G CPU_PWRGD CPU_ALL_PWROK Y NC7SZ08P5X_NL_SC70-5 R806 VDDIOFB_H VDDIOFB_L T1 T2 CPU_CLKIN_SC_P CPU_CLKIN_SC_N 3900P_0402_50V7K R16 169_0402_1% 0.1U_0402_16V4Z 4.7K_0402_5% U49 @ B C25 CPUCLK C26 R14 300_0402_5% +3VS CPU_VCC_SENSE CPU_VSS_SENSE CPU_VCC_SENSE CPU_VSS_SENSE A B 0.1U_0402_16V4Z T13 T15 T17 T19 T20 CPU_LDTSTOP# G Y PAD PAD T23 T25 PAD PAD T28 T30 CPU_THERMDC CPU_THERMDA NC7SZ08P5X_NL_SC70-5 @ 0_0402_5% C29 AC6 CPU_PRESENT# A3 PSI# D PSI# DBREQ_L E10 CPU_DBREQ# TDO AE9 CPU_TDO C9 C8 Place within 0.5" from CPU 25mil/6mil/6mil/6mil/25mil CPU_TEST29_H_FBCLKOUT_P CPU_TEST29_L_FBCLKOUT_N TEST25_H TEST25_L TEST19 TEST18 TEST13 TEST9 TEST17 TEST16 TEST15 TEST14 TEST12 TEST29_H TEST29_L TEST24 TEST23 TEST22 TEST21 TEST20 AE7 AD7 AE8 AB8 AF7 T14 PAD T16 PAD T18 PAD CPU_TEST21_SCANEN C3 AA6 W7 W8 Y6 AB6 TEST7 TEST6 THERMDC THERMDA TEST3 TEST2 TEST28_H TEST28_L TEST27 TEST26 TEST10 TEST8 J7 H8 AF8 AE6 K8 C4 T24 PAD T26 PAD T27 PAD CPU_TEST26_BURNIN# P20 P19 N20 N19 RSVD0 RSVD1 RSVD2 RSVD3 RSVD8 RSVD9 H16 B18 RSVD10 RSVD11 B3 C1 RSVD12 RSVD13 RSVD14 H6 G6 D5 RSVD15 RSVD16 RSVD17 RSVD18 RSVD19 RSVD20 R24 W18 R23 AA8 H18 H19 R17 80.6_0402_1% ROUTE AS 80 Ohm DIFFERENTIAL PAIR PLACE IT CLOSE TO CPU WITHIN 1" T21 PAD C T29 PAD T31 PAD LDT_RST# E Q47 NC7SZ08P5X_NL_SC70-5 B A R845 @ 4.7K_0402_5% @ 10K_0402_5% CPU_HT_RESET# R26 R25 P22 R22 Y LDT_RST# 0.1U_0402_16V4Z P B R844 G U51 VID5 VID4 VID3 VID2 VID1 VID0 E9 E8 G9 H10 AA7 C2 D7 E7 F7 C7 AC8 +3VS +1.8V R19 300_0402_5% +1.8VS PSI_L VID5 VID4 VID3 VID2 VID1 VID0 A5 C6 A6 A4 C5 B5 CLKIN_H CLKIN_L TMS TCK TRST_L TDI PAD PAD PAD PAD PAD VID5 VID4 VID3 VID2 VID1 VID0 AF6 H_THERMTRIP_S# AC7 CPU_PROCHOT#_1.8 VDDIO_FB_H VDDIO_FB_L DBRDY CPU_TEST25_H_BYPASSCLK_H CPU_TEST25_L_BYPASSCLK_L CPU_TEST19_PLLTEST0 CPU_TEST18_PLLTEST1 +1.8VS 0_0402_5% SB_PWROK_R W9 Y9 THERMTRIP_L PROCHOT_L CPU_PRESENT_L AA9 AC9 AD9 AF9 Modify 11/22 VDD_FB_H VDD_FB_L CPU_TMS CPU_TCK CPU_TRST# CPU_TDI R807 R8041 HTREF1 HTREF0 F6 E6 P U50 P6 R6 A9 A8 C28 LDT_STOP# SIC SID G10 +1.8V AF4 AF5 C PU_DBRDY +1.8VS R18 300_0402_5% RESET_L PWROK LDTSTOP_L 3900P_0402_50V7K @ 0_0402_5% VDDA2 VDDA1 B7 A7 F10 +VDDA_25V 1 300_0402_5% JP72D 50mil width(600mA) FBM-L11-321611-260-LMT_1206 SB_PWRGD R9 300_0402_5% L1 C RSVD4 RSVD5 RSVD6 RSVD7 3V_LDT_RST# C @ MMBT3904_SOT23 R808 AMD NPT S1 SOCKET Processor Socket @ 0_0402_5% +3VALW +3VALW Q1 1H_THERMTRIP# MMBT3904_SOT23 Q2 @ MMBT3904_SOT23 MAINPWON +1.8V H_THERMTRIP_S# B 10K_0402_5% H_THERMTRIP# R29 10K_0402_5% +3VS +1.8V 300_0402_5% CPU_PRESENT# R33 CPU_TEST25_H_BYPASSCLK_H R34 1 1K_0402_5% 510_0402_5% CPU_TEST25_L_BYPASSCLK_L CPU_TEST19_PLLTEST0 CPU_TEST18_PLLTEST1 CPU_TEST21_SCANEN 1 1 2 2 CPU_PROCHOT#_1.8 MMBT3904_SOT23 EC_THERM# C E R32 B Q3 CPU_TEST26_BURNIN# R30 4.7K_0402_5% @ SAMTEC_ASP-68200-07 CPU_PH_G 3V_LDT_RST# NOTE: HDT TERMINATION IS REQUIRED FOR REV Ax SILICON ONLY 300_0402_5% 10 12 14 16 18 20 22 24 26 R23 11 13 15 17 19 21 23 R21 @ 1K_0402_5% 1K_0402_5% R22 JP74 +1.8V 1 R20 2 +1.8V R28 1@ 220_0402_5% R27 1@ 220_0402_5% R26 1@ 220_0402_5% R25 1@ 220_0402_5% +1.8V HDT Connector 2 CPU_DBREQ# C PU_DBRDY CPU_TCK CPU_TMS CPU_TDI CPU_TRST# CPU_TDO B R24 1@ 220_0402_5% +1.8V +3VS C30 0.1U_0402_16V4Z C31 2200P_0402_50V7K A U4 1 CPU_THERMDA CPU_THERMDC SCLK EC_SMB_CK2 D+ SDATA EC_SMB_DA2 D- ALERT# GND VDD THERM# R42 R43 R44 R35 510_0402_5% 300_0402_5% 300_0402_5% 300_0402_5% A ADM1032ARMZ-2REEL_MSOP8 F75383M_MSOP8 SMBus Address: 1001110X (b) Compal Secret Data Security Classification Issued Date 2005/03/08 Deciphered Date 2006/03/08 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Compal Electronics, inc SCHEMATIC, M/B LA-3151P Size C Document Number Date: , Rev B 401412 09, 2006 Sheet of 55 D D BOTTOMSIDE DECOUPLING +CPU_CORE JP72F C +CPU_CORE JP72E AC4 VDD1 AD2 VDD2 G4 VDD3 H2 VDD4 J9 VDD5 J11 VDD6 J13 VDD7 K6 VDD8 K10 VDD9 K12 VDD10 K14 VDD11 L4 VDD12 L7 VDD13 L9 VDD14 L11 VDD15 L13 VDD16 M2 VDD17 M6 VDD18 M8 VDD19 M10 VDD20 N7 VDD21 N9 VDD22 N11 VDD23 P8 VDD24 P10 VDD25 R4 VDD26 R7 VDD27 R9 VDD28 R11 VDD29 T2 VDD30 T6 VDD31 T8 VDD32 T10 VDD33 T12 VDD34 T14 VDD35 U7 VDD36 U9 VDD37 U11 VDD38 U13 VDD39 V6 VDD40 V8 VDD41 V10 VDD42 AA4 AA11 AA13 AA15 AA17 AA19 AB2 AB7 AB9 AB23 AB25 AC11 AC13 AC15 AC17 AC19 AC21 AD6 AD8 AD25 AE11 AE13 AE15 AE17 AE19 AE21 AE23 B4 B6 B8 B9 B11 B13 B15 B17 B19 B21 B23 B25 D6 D8 D9 D11 D13 D15 D17 D19 D21 D23 D25 E4 F2 F11 F13 F15 F17 F19 F21 F23 F25 H7 H9 H21 H23 J4 +CPU_CORE VDD43 VDD44 VDD45 VDD46 VDD47 VDD48 VDD49 VDD50 VDD51 VDD52 VDD53 VDD54 V12 V14 W4 Y2 J15 K16 L15 M16 P16 T16 U15 V16 VDDIO1 VDDIO2 VDDIO3 VDDIO4 VDDIO5 VDDIO6 VDDIO7 VDDIO8 VDDIO9 VDDIO10 VDDIO11 VDDIO12 VDDIO13 VDDIO14 VDDIO15 VDDIO16 VDDIO17 VDDIO18 VDDIO19 VDDIO20 VDDIO21 VDDIO22 VDDIO23 VDDIO24 VDDIO25 VDDIO26 VDDIO27 H25 J17 K18 K21 K23 K25 L17 M18 M21 M23 M25 N17 P18 P21 P23 P25 R17 T18 T21 T23 T25 U17 V18 V21 V23 V25 Y25 +1.8V Athlon 64 S1 Processor Socket B VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98 VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 J6 J8 J10 J12 J14 J16 J18 K2 K7 K9 K11 K13 K15 K17 L6 L8 L10 L12 L14 L16 L18 M7 M9 M11 M17 N4 N8 N10 N16 N18 P2 P7 P9 P11 P17 R8 R10 R16 R18 T7 T9 T11 T13 T15 T17 U4 U6 U8 U10 U12 U14 U16 U18 V2 V7 V9 V11 V13 V15 V17 W6 Y21 Y23 N6 C32 10U_0805_10V4Z C33 10U_0805_10V4Z C34 10U_0805_10V4Z C35 10U_0805_10V4Z C36 10U_0805_10V4Z +CPU_CORE 2 0.22U_0603_10V7K 0.01U_0402_16V7K C37 22U_0805_6.3V6M C38 22U_0805_6.3V6M C39 22U_0805_6.3V6M C40 22U_0805_6.3V6M +1.8V C41 C923 2 C42 0.22U_0603_10V7K C43 0.22U_0603_10V7K C44 0.22U_0603_10V7K C45 22U_0805_6.3V6M C46 22U_0805_6.3V6M 2 C47 0.22U_0603_10V7K C48 0.22U_0603_10V7K C924 180P_0402_50V8J C DECOUPLING BETWEEN PROCESSOR AND DIMMs PLACE CLOSE TO PROCESSOR AS POSSIBLE +1.8V C49 4.7U_0805_10V4Z C50 4.7U_0805_10V4Z C51 4.7U_0805_10V4Z C52 4.7U_0805_10V4Z C53 0.22U_0603_10V7K C54 0.22U_0603_10V7K C55 0.22U_0603_10V7K 1 C56 0.22U_0603_10V7K CPU C57 0.01U_0402_16V7K C58 0.01U_0402_16V7K C59 180P_0402_50V8J left-hand side + C795 C60 180P_0402_50V8J 220U_D2_4VM CPU right-hand side +0.9V +0.9V B C61 4.7U_0805_10V4Z C68 0.22U_0603_10V7K C63 4.7U_0805_10V4Z C65 0.22U_0603_10V7K +CPU_CORE 1 + C796 45@ + C797 Athlon 64 S1 Processor Socket + C798 820U_E9_2.5V_M_R7 820U_E9_2.5V_M_R7 330U_D2E_2.5VM_R9 C69 1 C74 C71 C76 + C799 45@ 2 330U_D2E_2.5VM_R9 A1 1000P_0402_50V7K 180P_0402_50V8J 1000P_0402_50V7K 180P_0402_50V8J A26 PROCESSOR POWER AND GROUND Athlon 64 S1g1 uPGA638 Top View A A AF1 Compal Secret Data Security Classification Issued Date 2005/03/08 Deciphered Date 2006/03/08 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Compal Electronics, inc SCHEMATIC, M/B LA-3151P Size C Document Number Date: , Rev B 401412 09, 2006 Sheet of 55 +1.8V +1.8V +DIMM_VREF +1.8V DDR_A_D[0 63] DDR_A_D8 DDR_A_D9 DDR_A_DQS#1 DDR_A_DQS1 DDR_A_D10 DDR_A_D11 4.7U_0805_10V4Z 1 + C802 C88 C87 C86 220U_D2_4VM 2 1 + C925 150U_D2_6.3VM C103 C102 C101 C100 C99 C98 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 DDR_A_ODT0 +0.9V DDR_CS3_DIMMA# DDR_CS3_DIMMA# DDR_A_D36 DDR_A_D37 DDR_CKE1_DIMMA DDR_CKE0_DIMMA R69 R70 1 47_0402_5% 47_0402_5% DDR_A_D60 DDR_A_D61 DDR_CS3_DIMMA# DDR_CS2_DIMMA# DDR_CS1_DIMMA# DDR_CS0_DIMMA# R71 R72 R73 R74 1 1 2 2 DDR_A_ODT1 DDR_A_ODT0 R75 R76 1 47_0402_5% 47_0402_5% DDR_A_DQS#7 DDR_A_DQS7 DDR_A_D62 DDR_A_D63 R77 R78 1 10K_0402_5% 10K_0402_5% 2005/10/11 2 Layout Note: Place one 0.1uF cap close to every pullup resistors terminated to +0.9V 47_0402_5% 47_0402_5% 47_0402_5% 47_0402_5% A Compal Secret Data Security Classification C933 DDR_A_D54 DDR_A_D55 C932 47_0402_5% 47_0402_5% 47_0402_5% 0.1U_0402_16V4Z 1 DDR_A_CLK2 DDR_A_CLK#2 C931 R66 R67 R68 DDR_A_CLK2 DDR_A_CLK#2 0.1U_0402_16V4Z DDR_A_DM6 DDR_A_CAS# DDR_A_WE# DDR_A_RAS# DDR_A_D52 DDR_A_D53 +0.9V C930 47_0402_5% 47_0402_5% 47_0402_5% DDR_A_D46 DDR_A_D47 +1.8V 0.1U_0402_16V4Z 1 DDR_A_DQS#5 DDR_A_DQS5 11/3 Modify C929 R63 R64 R65 DDR_A_D44 DDR_A_D45 0.1U_0402_16V4Z DDR_A_BS#2 DDR_A_BS#1 DDR_A_BS#0 DDR_A_D38 DDR_A_D39 B C928 2 2 2 2 2 2 2 2 0.1U_0402_16V4Z 1 1 1 1 1 1 1 1 DDR_A_DM4 47_0402_5% 47_0402_5% 47_0402_5% 47_0402_5% 47_0402_5% 47_0402_5% 47_0402_5% 47_0402_5% 47_0402_5% 47_0402_5% 47_0402_5% 47_0402_5% 47_0402_5% 47_0402_5% 47_0402_5% 47_0402_5% C927 R47 R48 R49 R50 R51 R52 R53 R54 R55 R56 R57 R58 R59 R60 R61 R62 0.1U_0402_16V4Z DDR_A_MA15 DDR_A_MA14 DDR_A_MA13 DDR_A_MA12 DDR_A_MA11 DDR_A_MA10 DDR_A_MA9 DDR_A_MA8 DDR_A_MA7 DDR_A_MA6 DDR_A_MA5 DDR_A_MA4 DDR_A_MA3 DDR_A_MA2 DDR_A_MA1 DDR_A_MA0 2006/10/11 Deciphered Date Title Compal Electronics, inc SCHEMATIC, M/B LA-3151P THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC 4.7U_0805_10V4Z C97 C 0.1U_0402_16V4Z 0.1U_0402_16V4Z Layout Note: Place one cap close to every pullup resistors terminated to +0.9V DDR_A_BS#1 DDR_A_RAS# DDR_CS0_DIMMA# Issued Date P-TWO_A5692C-A0G16 C85 C104 4.7U_0805_10V4Z C926 SB_CK_SDAT SB_CK_SCLK +3VS 0.1U_0402_16V4Z SB_CK_SDAT SB_CK_SCLK 0.1U_0402_16V4Z DDR_A_D58 DDR_A_D59 0.1U_0402_16V4Z A C96 DDR_A_DM7 4.7U_0805_10V4Z DDR_A_D56 DDR_A_D57 DDR_A_ODT0 DDR_A_MA13 C95 DDR_A_D50 DDR_A_D51 DDR_A_BS#1 DDR_A_RAS# DDR_CS0_DIMMA# 0.1U_0402_16V4Z DDR_A_DQS#6 DDR_A_DQS6 C84 DDR_A_D48 DDR_A_D49 4.7U_0805_10V4Z DDR_A_D42 DDR_A_D43 DDR_A_MA4 DDR_A_MA2 DDR_A_MA0 C94 DDR_A_DM5 DDR_A_MA11 DDR_A_MA7 DDR_A_MA6 0.1U_0402_16V4Z DDR_A_D40 DDR_A_D41 C83 DDR_A_D34 DDR_A_D35 11/01 modify DDR_CKE1_DIMMA DDR_A_MA15 DDR_A_MA14 C93 DDR_A_DQS#4 DDR_A_DQS4 +0.9V 0.1U_0402_16V4Z B C82 DDR_A_D32 DDR_A_D33 4.7U_0805_10V4Z DDR_A_ODT1 DDR_CKE1_DIMMA C92 DDR_A_ODT1 DDR_A_D30 DDR_A_D31 0.1U_0402_16V4Z DDR_A_CAS# DDR_CS1_DIMMA# DDR_A_DQS#3 DDR_A_DQS3 C91 DDR_A_CAS# DDR_CS1_DIMMA# Layout Note: Place one cap close to every pullup resistors terminated to +0.9V DDR_A_D28 DDR_A_D29 C90 DDR_A_MA10 DDR_A_BS#0 DDR_A_WE# DDR_A_BS#0 DDR_A_WE# DDR_A_D22 DDR_A_D23 C89 DDR_A_MA5 DDR_A_MA3 DDR_A_MA1 0.1U_0402_16V4Z DDR_A_MA12 DDR_A_MA9 DDR_A_MA8 DDR_A_DM2 0.1U_0402_16V4Z DDR_CS2_DIMMA# DDR_A_BS#2 DDR_A_D20 DDR_A_D21 0.1U_0402_16V4Z DDR_CS2_DIMMA# DDR_A_BS#2 +1.8V DDR_A_CLK1 DDR_A_CLK#1 DDR_A_D14 DDR_A_D15 0.1U_0402_16V4Z DDR_CKE0_DIMMA DDR_CKE0_DIMMA 1K_0402_1% C81 DDR_A_D26 DDR_A_D27 D 4.7U_0805_10V4Z DDR_A_DM3 DDR_A_DQS#[0 7] R46 4.7U_0805_10V4Z C DDR_A_MA[0 15] DDR_A_DQS#[0 7] DDR_A_DM1 DDR_A_CLK1 DDR_A_CLK#1 DDR_A_DQS[0 7] DDR_A_MA[0 15] C80 DDR_A_D24 DDR_A_D25 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 VSS DQ20 DQ21 VSS NC DM2 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DQS3# DQS3 VSS DQ30 DQ31 VSS NC/CKE1 VDD NC/A15 NC/A14 VDD A11 A7 A6 VDD A4 A2 A0 VDD BA1 RAS# S0# VDD ODT0 NC/A13 VDD NC VSS DQ36 DQ37 VSS DM4 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DQS5# DQS5 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS CK1 CK1# VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS7# DQS7 VSS DQ62 DQ63 VSS SAO SA1 DDR_A_D12 DDR_A_D13 1K_0402_1% 4.7U_0805_10V4Z DDR_A_D18 DDR_A_D19 VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 NC VSS DQ26 DQ27 VSS CKE0 VDD NC BA2 VDD A12 A9 A8 VDD A5 A3 A1 VDD A10/AP BA0 WE# VDD CAS# NC/S1# VDD NC/ODT1 VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS NC,TEST VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SDA SCL VDDSPD DDR_A_D6 DDR_A_D7 C79 DDR_A_DQS#2 DDR_A_DQS2 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 DDR_A_DM0 4.7U_0805_10V4Z DDR_A_D16 DDR_A_D17 DDR_A_D4 DDR_A_D5 R45 DDR_A_D2 DDR_A_D3 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 VSS DQ4 DQ5 VSS DM0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 VSS CK0 CK0# VSS DQ14 DQ15 VSS 4.7U_0805_10V4Z DDR_A_DQS#0 DDR_A_DQS0 VREF VSS DQ0 DQ1 VSS DQS0# DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS DQ10 DQ11 VSS DDR_A_DM[0 7] DDR_A_DM[0 7] DDR_A_DQS[0 7] C78 D 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 0.1U_0402_16V4Z DDR_A_D0 DDR_A_D1 C77 DDR_A_D[0 63] JP1 Size Document Number Custom 401412 Date: , Rev B Sheet 09, 2006 of 55 +1.8V +1.8V +DIMM_VREF DDR_B_D[0 63] DDR_B_D[0 63] DDR_B_D2 DDR_B_D3 DDR_B_D8 DDR_B_D9 DDR_B_DQS#1 DDR_B_DQS1 DDR_B_D10 DDR_B_D11 C116 4.7U_0805_10V4Z C115 2 2 2 C131 C130 C129 C128 C127 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z +0.9V DDR_CS3_DIMMB# DDR_B_D38 DDR_B_D39 47_0402_5% 47_0402_5% R103 R104 R105 R106 DDR_B_D60 DDR_B_D61 2 2 DDR_B_DQS#7 DDR_B_DQS7 DDR_B_ODT1 DDR_B_ODT0 R107 R108 DDR_B_D62 DDR_B_D63 1 1 2 C941 R101 R102 DDR_CS3_DIMMB# DDR_CS2_DIMMB# DDR_CS1_DIMMB# DDR_CS0_DIMMB# C940 DDR_CKE1_DIMMB DDR_CKE0_DIMMB 0.1U_0402_16V4Z DDR_B_D54 DDR_B_D55 C939 47_0402_5% 47_0402_5% 47_0402_5% 0.1U_0402_16V4Z R98 R99 R100 C938 DDR_B_CAS# DDR_B_WE# DDR_B_RAS# +0.9V 0.1U_0402_16V4Z 47_0402_5% 47_0402_5% 47_0402_5% +1.8V C937 1 11/3 Modify 0.1U_0402_16V4Z R95 R96 R97 B C936 DDR_B_BS#2 DDR_B_BS#1 DDR_B_BS#0 DDR_B_DM6 47_0402_5% 47_0402_5% 47_0402_5% 47_0402_5% 47_0402_5% 47_0402_5% 47_0402_5% 47_0402_5% 47_0402_5% 47_0402_5% 47_0402_5% 47_0402_5% 47_0402_5% 47_0402_5% 47_0402_5% 47_0402_5% C935 DDR_B_CLK2 DDR_B_CLK#2 2 2 2 2 2 2 2 2 C934 DDR_B_D52 DDR_B_D53 1 1 1 1 1 1 1 1 0.1U_0402_16V4Z DDR_B_D46 DDR_B_D47 R79 R80 R81 R82 R83 R84 R85 R86 R87 R88 R89 R90 R91 R92 R93 R94 0.1U_0402_16V4Z DDR_B_DQS#5 DDR_B_DQS5 DDR_B_MA15 DDR_B_MA14 DDR_B_MA13 DDR_B_MA12 DDR_B_MA11 DDR_B_MA10 DDR_B_MA9 DDR_B_MA8 DDR_B_MA7 DDR_B_MA6 DDR_B_MA5 DDR_B_MA4 DDR_B_MA3 DDR_B_MA2 DDR_B_MA1 DDR_B_MA0 0.1U_0402_16V4Z DDR_B_D44 DDR_B_D45 10K_0402_5% 10K_0402_5% DDR_B_ODT0 DDR_B_DM4 R109 R110 Layout Note: Place one cap close to every pullup resistors terminated to +0.9V DDR_B_BS#1 DDR_B_RAS# DDR_CS0_DIMMB# DDR_B_D36 DDR_B_D37 DDR_B_CLK2 DDR_B_CLK#2 0.1U_0402_16V4Z DDR_CS3_DIMMB# Layout Note: Place one 0.1uF cap close to every pullup resistors terminated to +0.9V 47_0402_5% 47_0402_5% 47_0402_5% 47_0402_5% A 47_0402_5% 47_0402_5% +3VS Compal Secret Data Security Classification 2005/10/11 2006/10/11 Deciphered Date Title Compal Electronics, inc SCHEMATIC, M/B LA-3151P THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC 4.7U_0805_10V4Z DDR_B_ODT0 DDR_B_MA13 0.1U_0402_16V4Z DDR_B_BS#1 DDR_B_RAS# DDR_CS0_DIMMB# 0.1U_0402_16V4Z 0.1U_0402_16V4Z C114 DDR_B_MA4 DDR_B_MA2 DDR_B_MA0 C126 DDR_B_MA11 DDR_B_MA7 DDR_B_MA6 C125 DDR_CKE1_DIMMB DDR_B_MA15 DDR_B_MA14 Issued Date P-TWO_A5652C-A0G16 C 0.1U_0402_16V4Z C132 C113 4.7U_0805_10V4Z SB_CK_SDAT SB_CK_SCLK +3VS +0.9V C124 SB_CK_SDAT SB_CK_SCLK 0.1U_0402_16V4Z DDR_B_D58 DDR_B_D59 4.7U_0805_10V4Z DDR_B_DM7 A DDR_CKE1_DIMMB C123 DDR_B_D56 DDR_B_D57 0.1U_0402_16V4Z DDR_B_D50 DDR_B_D51 C112 DDR_B_DQS#6 DDR_B_DQS6 4.7U_0805_10V4Z DDR_B_D48 DDR_B_D49 DDR_B_D30 DDR_B_D31 C122 DDR_B_D42 DDR_B_D43 DDR_B_DQS#3 DDR_B_DQS3 0.1U_0402_16V4Z DDR_B_DM5 C111 DDR_B_D40 DDR_B_D41 Layout Note: Place one cap close to every pullup resistors terminated to +0.9V DDR_B_D28 DDR_B_D29 C121 DDR_B_D34 DDR_B_D35 0.1U_0402_16V4Z DDR_B_DQS#4 DDR_B_DQS4 C110 DDR_B_D32 DDR_B_D33 B 4.7U_0805_10V4Z DDR_B_ODT1 C120 DDR_B_ODT1 0.1U_0402_16V4Z DDR_B_CAS# DDR_CS1_DIMMB# C119 DDR_B_CAS# DDR_CS1_DIMMB# DDR_B_D22 DDR_B_D23 C118 DDR_B_MA10 DDR_B_BS#0 DDR_B_WE# DDR_B_BS#0 DDR_B_WE# C117 DDR_B_MA5 DDR_B_MA3 DDR_B_MA1 DDR_B_DM2 0.1U_0402_16V4Z DDR_B_MA12 DDR_B_MA9 DDR_B_MA8 DDR_B_D20 DDR_B_D21 0.1U_0402_16V4Z DDR_CS2_DIMMB# DDR_B_BS#2 +1.8V DDR_B_CLK1 DDR_B_CLK#1 DDR_B_D14 DDR_B_D15 0.1U_0402_16V4Z DDR_CS2_DIMMB# DDR_B_BS#2 DDR_B_CLK1 DDR_B_CLK#1 0.1U_0402_16V4Z DDR_CKE0_DIMMB DDR_CKE0_DIMMB D DDR_B_DM1 C109 DDR_B_D26 DDR_B_D27 DDR_B_DQS#[0 7] DDR_B_D12 DDR_B_D13 4.7U_0805_10V4Z DDR_B_DM3 DDR_B_MA[0 15] DDR_B_DQS#[0 7] 4.7U_0805_10V4Z C DDR_B_DQS[0 7] DDR_B_MA[0 15] C108 DDR_B_D24 DDR_B_D25 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 VSS DQ20 DQ21 VSS NC DM2 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DQS3# DQS3 VSS DQ30 DQ31 VSS NC/CKE1 VDD NC/A15 NC/A14 VDD A11 A7 A6 VDD A4 A2 A0 VDD BA1 RAS# S0# VDD ODT0 NC/A13 VDD NC VSS DQ36 DQ37 VSS DM4 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DQS5# DQS5 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS CK1 CK1# VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS7# DQS7 VSS DQ62 DQ63 VSS SAO SA1 DDR_B_DM[0 7] DDR_B_DQS[0 7] 4.7U_0805_10V4Z DDR_B_D18 DDR_B_D19 VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 NC VSS DQ26 DQ27 VSS CKE0 VDD NC BA2 VDD A12 A9 A8 VDD A5 A3 A1 VDD A10/AP BA0 WE# VDD CAS# NC/S1# VDD NC/ODT1 VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS NC,TEST VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SDA SCL VDDSPD DDR_B_D6 DDR_B_D7 C107 DDR_B_DQS#2 DDR_B_DQS2 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 DDR_B_DM0 4.7U_0805_10V4Z DDR_B_D16 DDR_B_D17 DDR_B_D4 DDR_B_D5 C106 DDR_B_DQS#0 DDR_B_DQS0 VSS DQ4 DQ5 VSS DM0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 VSS CK0 CK0# VSS DQ14 DQ15 VSS C105 D VREF VSS DQ0 DQ1 VSS DQS0# DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS DQ10 DQ11 VSS 0.1U_0402_16V4Z DDR_B_D0 DDR_B_D1 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 4.7U_0805_10V4Z JP2 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 DDR_B_DM[0 7] Size Document Number Custom 401412 Date: , Rev B Sheet 09, 2006 10 of 55 SUPER I/O SMsC LPC47N207 +3VS 0.1U_0402_16V4Z 1 C716 FIR@ C717 FIR@ 2 C718 FIR@ 0.1U_0402_16V4Z 0.1U_0402_16V4Z DLAD0 DLAD1 DLAD2 DLAD3 11 13 15 18 26 DLPC_CLK_33 DLDRQ1# DLFRAME# DCLKRUN# DSER_IRQ DSIO_14M VTR U65 14 22 10K_0402_5% 10K_0402_5% LPC_FRAME# LPC_DRQ#0 LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 RXD1 TXD1 DRSR1# RTS1#/SYSOPT0 CTS1# DTR1#/SYSOPT1 RI1# DCD1# 52 53 54 55 56 57 58 59 RXD1 TXD1 DSR#1 RTS#1 CTS#1 DTR#1 RI#1 DCD#1 IRTX2 IRRX2 IRMODE/IRRX3 49 50 51 IRTXOUT IRRX IRMODE R549 @ R550 @ 10K_0402_5% 10K_0402_5% R802 R803 +3VS VCC VCC VCC LFRAME# LDRQ# LAD0 LAD1 LAD2 LAD3 NB_RST# PCI_RESET# SIO_PD# 10 LPCPD# PM_CLKRUN# 11 CLKRUN# SERIRQ 13 SER_IRQ CLK_PCI_SIO 12 PCI_CLK CLK_14M_SIO CLOCKI BASE_ADDRESS 18 GPIO/SYSOPT1 @ 10K_0402_5% 10K_0402_5% SIO2@ Base I/O Address * = 004Eh R551 FIR@ 10K_0402_5% IRRX IRTX IRMODE/ALT_IRRX 15 16 17 INIT# SLCTIN# PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 SLCT PE BUSY ACK# ERROR# ALF# STROBE# 19 20 21 23 24 25 26 27 28 29 30 31 32 33 34 35 36 VSS 37 FIR PARALLEL I/F R545 @ R546 @ GROUND PAD IRRX IRTXOUT IRMODE SIO1036-AEZG_QFN36 SIO2@ LPC47N207-JN_STQFP64 @ RTS#1 Base I/O Address * = 02Eh = 04Eh CLK_PCI_SIO CLK_14M_SIO R553 @ 33_0402_5% R552 @ 10_0402_5% 20 29 37 45 62 GND0 GND1 GND2 GND3 GND4 GND5 63 GPIO LPC_CLK_33 LDRQ1# LDRQ0# LFRAME# CLKRUN# SERIRQ PCI_CLK PCIRST# SIO_14M LPCPD# IO_PME# +3VS 27 28 30 32 33 34 35 36 38 39 40 41 43 44 46 61 SERIAL I/F 10 12 24 14 16 19 21 22 23 25 47 +3VS GPIO10 GPIO11 GPIO12/IO_SMI# GPIO13/IRQIN1 GPIO14/IRQIN2 GPIO15 GPIO16 GPIO17 GPIO30 GPIO31 GPIO32 GPIO33 GPIO34 GPIO35 GPIO36 GPIO37 IR LPC_DRQ#0 LPC_FRAME# PM_CLKRUN# SERIRQ CLK_PCI_SIO NB_RST# CLK_14M_SIO SIO_PD# SIO_PME# LPC_DRQ#0 LPC_FRAME# PM_CLKRUN# SERIRQ CLK_PCI_SIO NB_RST# CLK_14M_SIO +3VS R547 210K_0402_5% +3VS R548 @ 10K_0402_5% LAD0 LAD1 LAD2 LAD3 LPC I/F 64 LPC I/F LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 DLPC I/F 3.3V 3.3V 3.3V 3.3V 3.3V U38 48 17 31 42 60 +3VS C719 @ 15P_0402_50V8J +IR_ANODE C720 @ 22P_0402_50V8J FIR@ R554 0_1206_5% FIR@ R555 0_1206_5% +3VS C721 FIR@ FIR Module 4.7U_0805_10V4Z W=60mil Place on the BOT side(near MINIPCI conn.) IR1 +5VS +IR_3VS JP28 RXD1 TXD1 DSR#1 RTS#1 CTS#1 DTR#1 RI#1 DCD#1 10 +3VS RP10 DCD#1 RI#1 CTS#1 DSR#1 +3VS FIR@ R556 47_1206_5% 4.7K_1206_8P4R_5% FIR@ IRRX +IR_3VS W=40mil C722 C723 FIR@ FIR@ 10U_0805_10V4Z 0.1U_0402_16V4Z 2 IRED_C RXD VCC GND IRED_A TXD SD/MODE MODE T = 12mil T = 12mil IRTXOUT IRMODE TFDU6102-TR3_8P FIR@ @ ACES_85201-10051 For SW debug use when no seial port Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2005/06/20 Deciphered Date 2006/06/20 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title SCHEMATIC, M/B LA-3151P Size B Document Number Date: , Rev B 401412 09, 2006 Sheet 41 of 55 A B C D E Power ON Circuit +3VALW +3VALW C724 0.1U_0402_16V4Z +3VALW +3VALW C726 0.47U_0603_16V7K 14 O I U39C SN74LVC14APWLE_TSSOP14 O R559 10_0402_5% P 14 P I G O U39B SN74LVC14APWLE_TSSOP14 G 14 I 7 U39A SN74LVC14APWLE_TSSOP14 C725 0.1U_0402_16V4Z R558 200K_0402_5% SB_PWRGD U39D SN74LVC14APWLE_TSSOP14 2 R560 10K_0402_5% G O G I P P R557 470K_0402_5% VLDT_EN VLDT_EN 14 1 R561 10_0402_5% note:T1 minimum 15ms,T2 minimum 33ms/maximum 500ms, SUSP# goes to low after SB_PWRGD goes to low for power down NB_PWRGD T1 VLDT_EN NB_PWRGD SB_PWRGD T2 SUSP# 2 +1.8VS ON/OFF switch TOP Side J2 J3 2 @ JOPEN @ JOPEN +3VALW Bottom Side Power Button +3VALW R562 100K_0402_5% 2 ON/OFF 51ON# Change P/N : SN111000207 51ON# DAN202U_SC70 SW7 LID_SW# 3 ON/OFFBTN# ON/OFFBTN# R563 100K_0402_5% Lid Switch D25 D27 R564 D EC_ON EC_ON S 2N7002_SOT23 D26 @ PSOT24C_SOT23 RLZ20A_LL34 2005/09/04 1000P_0402_50V7K MPU-101-81_4P C727 Q44 G 10K_0402_5% Compal Secret Data Security Classification 2005/03/08 Issued Date Deciphered Date 2006/03/08 B C Compal Electronics, inc SCHEMATIC, M/B LA-3151P THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A Title D Size B Date: Document Number Rev B 401412 , 09, 2006 Sheet E 42 of 55 +5VS PWR_LED# R565 300_0402_5% LED1 PWR_LED# 1 D HT-110UYG_1204 S Q45 2N7002_SOT23 G PWR_LED +5VALW R566 300_0402_5% LED2 PWR_SUSP_LED# PWR_SUSP_LED# BATT_GRN_LED# BATT_GRN_LED# HT-110UD_1204 +5VS +5VALW 1 +5VS R568 R569 300_0402_5% 300_0402_5% R567 300_0402_5% +5VALW LED3 1 C728 + To LED/B Conn LED5 HT-110NBQA_BULE_1204 R570 300_0402_5% 1 +5VALW WL_LED# WL_LED# BT_LED# JP29 BATT_AMB_LED# BATT_AMB_LED# PWR_LED# MEDIA_LED# CAPS_LED# NUM_LED# E-MAIL_LED# ON/OFFBTN# E-MAIL_BTN# IE_BTN# USER_BTN# EMPWR_BTN# HT-110UD_1204 BT_LED# 3 4 BTSW_EN# BTSW_EN# SW8 HSS110_4P 2005/09/12 2 3 4 WLSW_EN# 10 12 14 16 18 20 22 24 26 28 30 +5VALW USB20_N3 USB20_P3 USB20_N6 USB20_P6 USB20_N3 USB20_P3 USB20_N6 USB20_P6 USB_EN# AUDIO_INL AUDIO_INR ACES_88018-304G +3VALW Update Part Number to SCR36236000 CIR C730 CIR@ 4.7U_0805_10V4Z IR2 Vs GND OUT GND RCIRRX CIR@ TSOP36236TR_4P 2 2005/09/04 RCIRRX C731 CIR@ 1000P_0402_50V7K Grapevine KSO16 KSO17 KSI0 VOL_UP LEFT KSI1 RIGHT VOL_DOWN KSI2 PLAY ENTER KSI3 STOP KSI3 STOP VOL_UP KSI4 NEXT KSI4 NEXT VOL_DOWN KSI5 REV KSI5 REV ARCADE_TV RECORD 10 12 14 16 18 20 22 24 26 28 30 WLSW_EN# SW9 HSS110_4P KSI6 11 13 15 17 19 21 23 25 27 29 2005/09/12 R571 100_0805_5% CIR@ Geneva 11 13 15 17 19 21 23 25 27 29 31 32 33 34 35 36 WL_SW 6 5 BT_SW 150U_D_6.3VM +5VS LED6 CVBS_IN S_YIN S_CIN GND GND GND GND GND GND LED4 HT-110UD_1204 C729 0.1U_0402_16V4Z 3 2 HT-110UYG_1204 KSO16 KSI2 KSO17 PLAY Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2005/06/20 Deciphered Date 2006/06/20 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title SCHEMATIC, M/B LA-3151P Size B Document Number Date: , Rev B 401412 09, 2006 Sheet 43 of 55 A B C D E F G H +VDDA 28.7K for Module Design (VDDA = 4.702) +5VAMP R689 10K_0402_5% C542 1U_0603_10V4Z R688 10K_0402_5% 1 R433 C 2 B E R438 ERROR SD SENSE or ADJ CNOISE GND +VDDA DELAY 40mil R452 30K_0402_1% 4.85V C558 10U_0805_10V4Z C548 C535 MONO_IN R451 10K_0402_1% 0.1U_0402_16V4Z 1U_0402_6.3V4Z Q19 R687 2SC2411K_SC59 2.4K_0402_5% 560_0402_5% C533 1U_0402_6.3V4Z 560_0402_5% SB_SPKR C528 1U_0402_6.3V4Z 1 L33 C550 C553 KC FBM-L11-201209-221LMAT_0805 10U_0805_10V4Z 2 0.1U_0402_16V4Z VOUT SI9182DH-AD_MSOP8 560_0402_5% PCM_SPK# VIN R430 U34 C527 1U_0402_6.3V4Z BEEP# (output = 250 mA) 60mil L32 KC FBM-L11-201209-221LMAT_0805 1 +5VS D16 RB751V_SOD323 2 R442 10K_0402_5% HD Audio Codec Modify 11/07 for EMI +AVDD_AC97 C556 LINE_R LINE_R C557 C543 C546 C544 MIC1_L MIC1_L C547 MIC1_R MIC1_R Modify 11/07 for EMI C554 2 2 2 2 0_0603_5% R589 R590 R592 0_0603_5% 35 AMP_LEFT FRONT_OUT_R 36 AMP_RIGHT 16 MIC2_L SURR_OUT_L 39 17 MIC2_R SURR_OUT_R 41 LINE1_L SIDESURR_OUT_L 45 LINE1_R SIDESURR_OUT_R 46 CD_L CEN_OUT 43 CD_R LFE_OUT 44 BIT_CLK SDATA_IN NBA_PLUG 0_0603_5% 0_0603_5% EAPD L75 FBM-L11-160808-800LMT_0603 SPDIF MIC1_R PCBEEP PIN37_VREFO 37 LINE1_VREFO 29 LINE2_VREFO 31 RESET# SYNC MIC1_VREFO_L 28 MIC1_VREFO_R 32 MIC2_VREFO 30 SDATA_OUT 47 SPDIFI/EAPD VREF 27 JDREF 40 VAUX 33 SPDIFO AVSS1 AVSS2 26 42 DVSS1 DVSS2 DGND GNDA 22P_0402_50V8J ICH_BITCLK_AUDIO R443 33_0402_5% ICH_AC_SDIN0 10mil MIC1_VREFO_L MIC1_VREFO_R AC97_VREF 10mil R445 20K_0402_1% @ ALC883-LF_LQFP48 GND AMP_RIGHT MIC1_L GPIO0 GPIO1 SENSE A SENSE B 48 10U_0805_10V4Z AMP_LEFT C538 CD_GND 13 34 0_0603_5% FRONT_OUT_L LINE2_R 10 ICH_SDOUT_AUDIO LINE2_L 15 11 ICH_RST_AUDIO# 0.1U_0402_16V4Z 14 LINE_C_L 23 1U_0603_10V4Z LINE_C_R 24 1U_0603_10V4Z CD_L_RC 18 @ 1U_0603_10V4Z C D_R_RC 20 @ 1U_0603_10V4Z CD_AGND_RC19 @ 1U_0603_10V4Z MIC1_C_L 21 1U_0603_10V4Z MIC1_C_R 22 1U_0603_10V4Z MONO_IN 12 ICH_SYNC_AUDIO R827 +3VS C532 1 R826 DVDD2 U33 2005/09/12 C539 C559 0.1U_0402_16V4Z 1 C537 C561 10U_0805_10V4Z LINE_L LINE_L DVDD1 L74 FBM-L11-160808-800LMT_0603 0.1U_0402_16V4Z 40mil 38 C549 10U_0805_10V4Z 0.1U_0402_16V4Z C545 25 AVDD2 L34 FBM-L11-160808-800LMT_0603 AVDD1 +VDDA 20mil AGND 4 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2005/06/20 2006/06/20 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C D E F Title SCHEMATIC, M/B LA-3151P Size Document Number Custom Rev B 401412 , Date: G 09, 2006 Sheet 44 H of 55 A B C D E JP12 SPKL+ SPKLSPKR+ SPKR- +5VAMP R462 R464 R466 R469 20mil R458 1 1 2 2 0_0603_5% 0_0603_5% 0_0603_5% 0_0603_5% SPK_L+ SPK_LSPK_R+ SPK_R- ACES_85204-0400 Speaker Conn 10K_0402_5% AMP_LEFT AMP_RIGHT C566 C568 VOLMAX 0_0402_5% NBA_PLUG 1U_0402_6.3V4Z 1U_0402_6.3V4Z VOLMAX 13 SE/BTL# BYPASS 20mil NBA_PLUG NBA_PLUG EC_MUTE SPDIF_PLUG# Q22 SI2301BDS_SOT23 D LOUT- SPKL- 16 SPKR- LOUT+ 11 SPKL+ ROUT+ 14 SPKR+ GND GND 12 LINRINBYPASS EC_MUTE ROUT- VOLUME AMP_LEFT_C AMP_RIGHT_C SPDIF_PLUG# G Q21 2N7002_SOT23 S +5VSPDIF 20mil APA2068KAI-TRL_SOP16 MUTE SHUTDOWN# R698 100K_0402_5% VOL_AMP R690 VDD VDD +5VAMP R468 100K_0402_5% 1 0.1U_0402_16V4Z 10 15 +5VAMP R467 100K_0402_5% U56 C882 2 C892 4.7U_0805_10V4Z 2 2 S C881 0.1U_0402_16V4Z 1 1 SPDIF_PLUG# Q20 G 2N7002_SOT23 @ D R457 1.5K_0402_1% +5VAMP W=40mil D R455 @ 5.1K_0402_1% +5VAMP S VOL_AMP (0.65V -> 10dB ) G C886 4.7U_0805_10V4Z C563 330P_0402_50V7K 2 1 C562 S/PDIF Out JACK 330P_0402_50V7K + C891 SPKR+ C888 + JP40 SPKL+ HPOUT_L_1 150U_D_6.3VM R702 2HPOUT_R_1 150U_D_6.3VM R699 HPOUT_L_2 47_0603_5% HPOUT_R_2 47_0603_5% 1 +5VAMP SPDIF SPDIF +5VSPDIF R652 @ 1K_0402_1% 10 2 R651 @ 1K_0402_1% HPOUT_L_3 FBM-11-160808-700T_0603 HPOUT_R_3 FBM-11-160808-700T_0603 SPDIF_PLUG# R456 100K_0402_5% L51 L50 ACES_20234-0101 LINE-IN JACK JP41 LINE_R LINE_L LINE_R LINE_L L48 FBM-11-160808-700T_0603 L49 FBM-11-160808-700T_0603 C885 220P_0402_50V7K LINE_R_R LINE_L_R R775 2.2K_0402_5% 15mil INT_MIC_L MIC1_R MIC1_L ACES_85204-0200 C569 220P_0402_50V7K 1 C876 220P_0402_50V7K SUYIN_010164FR006G118ZL Compal Electronics, Inc Compal Secret Data Security Classification 2005/06/20 Issued Date MIC1_R_1 MIC1_L_1 FBM-11-160808-700T_0603 JP42 R776 2.2K_0402_5% FBM-11-160808-700T_0603 L54 L35 MIC JACK 1 MIC1_VREFO_R JP13 SUYIN_010164FR006G118ZL C884 220P_0402_50V7K MIC1_VREFO_L Int MIC Conn 3 1 2006/06/20 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C D Title SCHEMATIC, M/B LA-3151P Size Document Number Custom Rev B 401412 Date: , Sheet 09, 2006 E 45 of 55 A B C D E +VDD_CORE R843 470_0402_5% SUSP G Q46 2N7002_SOT23 D R610 470_0402_5% 1U_0603_10V4Z SUSP G Q32 2N7002_SOT23 S 1 R611 100K_0402_5% SUSP G Q29 2N7002_SOT23 1U_0402_6.3V4Z 11/17 modify R609 470_0402_5% +VSB +1.8V D C777 0.1U_0603_25V7K S SYSON# G Q30 2N7002_SOT23 R613 470_0402_5% 1 S R612 100K_0402_5% +3VS 0.1U_0603_25V7K 4.7U_0805_10V4Z S C773 +VSB D C776 C772 C775 4.7U_0805_10V4Z 5VS_GATE0 S +1.8V S S S G SI4800DY_SO8 C774 4.7U_0805_10V4Z D D D D SUSP G Q28 2N7002_SOT23 4.7U_0805_10V4Z D C771 5VS_GATE3 C770 D +1.8VALW TO +1.8V 1 SI4800DY_SO8 S S S G D D D D +1.8VALW U44 U43 +5VALW TO +5VS +5VS R614 470_0402_5% +5VALW 1 +5VS 2 +1.8VS +1.8VALW 1U_0402_6.3V4Z U45 D 0.22U_0603_16V7K S +1.8VS SI4800DY_SO8 R617 @ 1M_0402_1% 10U_0805_10V4Z C784 2 C783 S S S G SUSP G Q33 2N7002_SOT23 C782 4.7U_0805_10V4Z 5VS_GATE4 D D D D C780 4.7U_0805_10V4Z 2 1U_0402_6.3V4Z R619 100K_0402_5% +VSB D C785 SUSP SUSP D SUSP G Q34 2N7002_SOT23 0.22U_0603_16V7K S 2 47K_0402_5% R616 10K_0402_5% R620 470_0402_5% 1 +0.9VS C781 R618 +5VALW +VSB 5VS_GATE1 R615 100K_0402_5% SI4800DY_SO8 C779 S SUSP SUSP# G Q36 2N7002_SOT23 100K DTC115EKA_SOT23 Q35 100K 3 S S S G 2 +1.2VS TO +1.2V_HT +1.2V_HT D S VLDT_EN# G Q40 2N7002_SOT23 +1.2V_HT 1U_0402_6.3V4Z R627 100K_0402_5% 5VS_GATE5 R622 10K_0402_5% R623 470_0402_5% +VSB C793 10U_0805_10V4Z @ C794 R628 @ 1M_0402_1% D SYSON# SYSON# 0.22U_0603_16V7K S D SUSP G Q41 2N7002_SOT23 S VLDT_EN# G Q39 2N7002_SOT23 SYSON SYSON 100K DTC115EKA_SOT23 Q38 100K 0.1U_0603_25V7K C789 1 S S S G +5VALW C792 SI4800DY_SO8 R621 10K_0402_5% +VSB D D D D R624 100K_0402_5% 5VS_GATE2 +5VALW 10U_0805_10V4Z 1U_0402_6.3V4Z 2 4.7U_0805_10V4Z C788 4.7U_0805_10V4Z C791 U48 C787 1 C786 SI4800DY_SO8 1 +0.9V 1 S S S G D D D D +0.9VS +0.9V TO +0.9VS U47 +1.2VS D D D D 10U_0805_10V4Z SYSON# G Q31 2N7002_SOT23 +3VS S U46 C778 D29 D30 D31 CH751H-40_SC76 CH751H-40_SC76 CH751H-40_SC76 2 1 +3VALW S SUSP G Q27 2N7002_SOT23 +3VALW TO +3VS +3VS D +1.8VALW TO +1.8VS D 4 VLDT_EN VLDT_EN 100K DTC115EKA_SOT23 Q37 Compal Secret Data Security Classification 100K 2005/03/08 Issued Date Deciphered Date 2006/03/08 B C Compal Electronics, inc SCHEMATIC, M/B LA-3151P THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A Title D Size Document Number Custom 401412 Date: , 09, 2006 Rev B Sheet E 46 of 55 A B PL1 VIN PR1 10_1206_5% PR2 1K_1206_5% 2 PD1 RLZ24B_LL34 2 PR7 1K_1206_5% B+ PR4 1K_1206_5% 1 RLS4148_LLDS2 100K_0402_5% PQ1 TP0610K-T1-E3_SOT23 PR3 1K_1206_5% PD2 VIN PR6 560P_0402_50V7K PC4 12P_0402_50V8J PC3 12P_0402_50V8J PC2 2 PC1 560P_0402_50V7K G G 1 FBMA-L18-453215-900LMA90T_1812 PR5 ADPIN D 100K_0402_5% PJP1 SINGA_2DC-G756-I06 C PR9 33_1206_5% PQ4 TP0610K-T1-E3_SOT23 VS 2 PC6 0.1U_0603_25V7K 2 PR10 100K_0402_5% PC5 0.22U_1206_25V7K PQ3 DTC115EUA_SC70 CHGRTCP B+ PR12 2.2M_0402_5% VL 51ON# ACOFF 1 PR11 22K_0402_5% PQ2 DTC115EUA_SC70 2 PR8 100K_0402_5% PD3 RLS4148_LLDS2 PD4 RB751V_SOD323 BATT+ VIN PR13 499K_0402_1% ACIN B 2005/0926 PC9 0.01U_0402_25V7K 2 PR21 47K_0402_5% PACIN PQ6 DTC115EUA_SC70 @ PR22 66.5K_0402_1% +5VALW Deciphered Date Compal Electronics, Inc 2006/0926 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A 1 G Compal Secret Data Security Classification Issued Date D S BATT ONLY Precharge detector Min typ Max H >L 6.138V 6.214V 6.359V L >H 7.196V 7.349V 7.505V PQ5 MF2N7002W-G_SOT323-3 PR20 34K_0402_1% RTCVREF PR19 499K_0402_1% Precharge detector Min typ Max H >L 14.589V 14.84V 15.243V L >H 15.562V 15.97V 16.388V PR18 191K_0402_1% PC10 0.1U_0603_25V7K PRG++ 2 32.3 RB715F_SOT323 - PC7 1U_0805_25V4Z + O PC11 1000P_0402_50V7K 1 GND P ACON G MAINPWON PU2A LM393DR_SO8 IN OUT PD5 2 560_0603_5% 2 PC8 +CHGRTC 4.7U_0805_6.3V6K PR16 PR17 560_0603_5% PR15 200_0805_5% PU1 G920AT24U_SOT89 PR14 100K_0402_1% RTCVREF 3.3V 1 VS C Title SCHEMATIC, M/B LA-3151P Size B Document Number Date: , Rev B 401412 Sheet 09, 2006 D 47 of 55 A B C D BST5B PC12 0.1U_0603_25V7K B+++ 1 PC18 4.7U_1206_25V6K 2 D2 G2 D2 D1/S2/K G1 D1/S2/K S1/A D1/S2/K AO4916_SO8 2 PR30 100K_0402_1% LX3 PR31 0_0603_5% PR33 499K_0402_1% 2 DL3 PL4 10UH_SIL104R-100PF_4.4A_30% 28 26 24 27 22 DH3 +3VALWP PC25 150U_D_6.3VM PR42 0_0402_5% @ PR39 3.57K_0402_1% VCC 3HG BST3A PRO# LDO3 SPOK PR41 0_0402_5% 4.7U_0805_10V4Z 10 PR43 47K_0402_5% PC26 0.22U_0603_16V7K 0_0402_5% 2 PC24 0.047U_0603_16V7K REF GND PR38 25 12 2VREF_19998 PZD1 PR37 RLZ5.1B_LL34 47K_0402_5% 2 PR40 100K_0402_5% PR36 0_0402_5% 2 PR35 0_0402_5% PC27 1 VS @ 11 LX5 DL5 ILIM5 OUT5 PU3 FB5 BST3 N.C.MAX8734AEEI+_QSOP28 DH3 DL3 SHDN# LX3 ON5 OUT3 ON3 FB3 SKIP# PGOOD 2 PR29 499K_0402_1% 100K_0402_1% 15 19 21 ILIM3 PR32 DH5 PC20 1U_0805_16V7K 17 13 BST5 16 PQ8 PC17 2200P_0402_50V7K 2 PR26 4.7_1206_5% 2 14 23 PR34 10.2K_0402_1% + PC23 150U_D_6.3VM BST5A PR28 0_0603_5% +5VALWP B+++ PC16 0.1U_0603_25V7K 2VREF_1999 TON PL3 10UH_SIL104R-100PF_4.4A_30% 18 PC21 4.7U_0805_10V4Z VL PC22 0.1U_0603_25V7K LX5 @ 20 DH5 V+ 5HG PR27 0_0603_5% PR24 47_0402_5% B+++ 1U_1206_25V7K PR23 0_0603_5% AO4916_SO8 LD05 DL5 PR25 PC19 4.7_1206_5% 2 G2 D2 D1/S2/K D2 D1/S2/K G1 D1/S2/K S1/A VL 4.7U_1206_25V6K PC15 PC13 0.1U_0603_25V7K BST3B PD6 CHP202UPT_SOT323-3 30.6 PQ7 PC14 2200P_0402_50V7K 1 PL2 FBM-L11-322513-151LMAT_1210 B+ + 3 Imax=3.5A Ipeak=4.5A PC28 0.047U_0603_16V7K +3.3V Iocp =5.36A ~ 9.03A Imax=3.5A Ipeak=4.5A +5V Iocp = 5.35A ~8.65 A PC29 1U_0603_16V6K MAINPWON 4 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2005/09/26 Deciphered Date 2006/09/26 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C Title SCHEMATIC, M/B LA-3151P Size Document Number Custom Date: , Rev B 401412 Sheet 09, 2006 D 48 of 55 A B C D E Charger Iadp=0~4.5A(90W) P2 DHI 25 LX 23 PR48 10K_0402_1% PR52 0.015_2512_1% G S S S charger_LX 10UH_SIL104R-100PF_4.4A_30% charger_DLO VCTL ICTL 11 10 ACOK# SHDN# ACIN ICHG BST 24 charger_BST DLOV 22 charger_DLOV 28 IINP CCV PR56 0_0402_5% PC41 0.1U_0603_25V7K PL6 21 DLO 15 13 REFIN 12 charger_DHI PR57 33_1206_5% PC46 1U_0603_10V6K MAX1908ETI+T_QFN28 20 14 19 18 16 PGND GND CCS CCI PC49 0.01U_0402_25V7K ACON CSIP CSIN BATT PD10 1SS355_SOD323 2 PC47 1U_0805_25V4Z MAX1908-CCS PC50 0.1U_0402_16V7K 1 PR61 22K_0402_5% 2 1908LDO PR60 10K_0402_1% PR59 100K_0402_1% LDO BATT+ PC44 4.7U_1206_25V6K CLS PC43 4.7U_1206_25V6K REF @ PC39 1000P_0402_50V7K PC42 4.7U_1206_25V6K 26 CSSN ACOFF 29 ACOFF 2 PQ17 SI4810BDY-T1-E3_SO8 TP D D D D 27 PR54 15K_0402_1% PR58 24.9K_0402_1% PQ19 MF2N7002W-G_SOT323-3 IREF PD11 1N4148_SOD80 ACOFF# PACIN ACOFF# PR53 9.31K_0402_1% VIN G S S S 1 PR55 90.9K_0402_0.1% S PC40 0.1U_0402_16V7K D G CSSP CELLS 1908LDO PC45 0.01U_0402_25V7K S 17 @ PR49 0_0402_5% 10K_0402_0.1% PR50 PR51 150K_0402_5% PQ18 MF2N7002W-G_SOT323-3 G CSIP CSIN 3 BATT+ FSTCHG Charge voltage BATT+ VS 4S CC-CV MODE : 16.8V 1 D PR69 200K_0402_1% PC53 0.01U_0402_25V7Z PQ20 MF2N7002W-G_SOT323-3 G S D - PR67 10K_0402_5% + S 4 - LM358ADR_SO8 PU5B P G 2P4S:4800mAH/cell 0.8C=3.84A PR68 511K_0402_1% BATT_OVP PU5A + VS G P IREF=0.73~3.3V +3VALW PR66 300K_0603_0.1% IREF=0.832*Icharge PR65 845K_0603_1% BATT-OVP=0.111*BATT+ PC52 0.01U_0402_25V7Z 1 PC51 0.1U_0402_16V7K 2 PR63 100K_0402_5% LI-4S :17.8V BATT-OVP=1.9758V PR64 10K_0402_5% Iinput=(90.0K/100.9K)*(75/15)=4.504A CP Point: PR62 0_0402_5% DCIN 1 D PQ16 DTC115EUA_SC70 D PQ12 SI4810BDY-T1-E3_SO8 D D D D PU4 S PC38 1U_0603_10V6K PR45 47K_0402_1% PQ14 DTC115EUA_SC70 PQ15 SI2301DS_SOT23~D CSSP 6C/8C# G PC37 0.1U_0603_25V7K PC33 2200P_0402_25V7K 1 PC35 0.1U_0603_25V7K PC32 0.1U_0603_25V7K PQ11 AO4407L_SO8~N CSSN PD9 1SS355_SOD323 VIN 47K PC48 0.01U_0402_25V7K 2 2 PQ13 DTA144EUA_SC70 47K PR47 47K_0402_5% PR46 200K_0402_1% PC36 0.1U_0603_25V7K 1 PC34 0.1U_0603_25V7K PC31 4.7U_1206_25V6K CHG_B+ PL5 FBMA-L18-453215-900LMA90T_1812 1 1 B+ PR44 0.015_2512_1% P3 VIN PQ10 AO4407L_SO8~N PC30 4.7U_1206_25V6K PQ9 AO4407L_SO8~N LM358ADR_SO8 6C/8C# G PQ21 MF2N7002W-G_SOT323-3 OVP voltage : LI-3S :17.8V BATT-OVP=1.9758V BATT-OVP=0.111*BATT+ 2005/09/26 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2006/09/26 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C D Title SCHEMATIC, M/B LA-3151P Size Document Number Custom Rev B 401412 Date: , Sheet 09, 2006 E 49 of 55 A B BATT+ BATT++ PR70 100K_0402_5% FBMA-L18-453215-900LMA90T_1812 PH1 under CPU botten side : CPU thermal protection at 90 degree C Recovery at 70 degree C 6C/8C# BATT++ VL 2 PR77 82.5K_0603_1% PC57 1000P_0402_50V7K PR81 100_0402_5% +3VALWP EC_SMB_DA1 PR83 100_0402_5% + - PU2B P O MAINPWON LM393DR_SO8 PH1 100K_0603_1%_TH11-4H104FT TM_REF1 SUYIN_200275MR007G161ZL PJP2 PR73 150K_0402_1% G PR78 1K_0402_5% PR79 6.49K_0402_1% PR76 442K_0603_1% 1 BATT_TEMP PC56 0.1U_0603_25V7K PR74 9.76K_0402_1% PR80 150K_0402_1% VL PR82 150K_0402_1% EC_SMB_CK1 2 SM ART Batter y: GND SMC 3.SMD 4.TS B/I ID BA TT+ 1 PR75 1K_0402_5% BATT_TEMP 1 @PR72 1K_0402_5% PJP2 battery connector VL VS PC54 0.01U_0402_25V7Z PC55 1000P_0402_50V7K 1 PC58 1U_0805_16V7K BATT+ D +3VALWP PR71 1K_0402_5% PL7 C +VSBP PR84 PU6A LM393DR_SO8 PZD2 RLZ4.3B_LL34 PR95 10K_0402_5% + - RTCVREF PU6B P PACIN PR94 10K_0402_5% PC62 0.1U_0603_25V7K PACIN G O - ACIN + AC IN P PR89 10K_0402_5% PR87 10K_0402_5% 2 S PR92 20K_0402_1% PC61 1000P_0402_50V7K PQ23 MF2N7002W-G_SOT323-3 @ PC63 0.1U_0402_16V7K D G 1 PR93 0_0402_5% PR91 22K_0402_5% 2 2 SPOK VS PR86 84.5K_0402_1% PR90 100K_0402_5% VIN PC60 0.1U_0603_25V7K 1M_0402_1% PC59 0.22U_1206_25V7K VIN 2 PR88 22K_0402_5% VL PR85 100K_0402_5% 1 1 PQ22 TP0610K-T1-E3_SOT23 B+ Vin Detector Min typ Max H >L 16.976V 17.257V 17.728V L >H 17.430V 17.901V 18.384V G O LM393DR_SO8 4 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2005/09/26 Deciphered Date 2006/09/26 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C Title SCHEMATIC, M/B LA-3151P Size Document Number Custom Rev B 401412 Date: , Sheet 09, 2006 D 50 of 55 D D PHASE_6269 PR96 1K_0402_1% 6269_VCC UG_6269 PR97 0_0603_5% PC65 0.1U_0603_25V7K +5VS BOOT PVCC 2.2U_0603_6.3V6K PGND 10 ISEN_6269 + G S S S PC68 330U_D2E_2.5VM 2 VO PR102 15.4K_0402_1% +1.2VSP PL9 PQ25 SI4810BDY-T1-E3_SO8 PR103 49.9K_0402_1% 1.8UH_SIL104R-1R8PF_9.5A_30% PC70 0.01U_0402_25V7K B PC72 6800P_0402_25V7K PR105 3K_0402_1% 2 PC71 22P_0402_50V8J FSET ISEN COMP EN PC69 0.22U_0603_16V7K B ISL6269CRZ-T_QFN16 FCCM C LG_6269 11 D D D D FB PC67 2.2U_0603_6.3V6K LG PU7 SUSP# PR101 100K_0402_5% VCC PR104 57.6K_0402_1% 1 PR100 0_0402_5% SI4800BDY-T1-E3_SO8 6269_VCC PQ24 G S S S 12 UG PHASE VIN PGOOD GND C 6269_VCC PC66 D D D D @PR98 4.7_0603_5% PR99 4.7_0603_5% 13 14 15 17 16 BOOT_6269 1 PL8 FBM-L11-322513-151LMAT_1210 PC64 10U_1206_25VAK B+ PR106 3K_0402_1% Ipeak=VGA_1.2V+(+1.2V_HT)=2.1A+6.067A=8.167A Imax=5.7A Iocmin=9.23A Iocmax=19.23A A A Compal Electronics, Inc Compal Secret Data Security Classification 2005/09/26 Issued Date Deciphered Date 2006/09/26 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title SCHEMATIC, M/B LA-3151P Size Document Number Custom Rev B 401412 Date: , 09, 2006 Sheet 51 of 55 1 +3VALW PJP3 JUMP_43X79 1 PC73 4.7U_1206_25V6K 2 +1.8VALW PJP4 JUMP_43X79 +1.8V 2 D D +5VALW RTCVREF PU9 CM8562IS_PSOP8 NC TP AGND VTT VCCA VTT REFEN D C PR109 60.4K_0402_1% 1 PC79 22U_1206_10V6M 1 +0.9VSP PC77 4.7U_1206_25V6K APL5331KAC-TRL_SO8 @ PC78 0.1U_0402_16V7K S G PQ26 MF2N7002W-G_SOT323-3 PR111 1K_0402_1% 1 D SYSON# @ PR110 0_0402_5% VFB +2.5VSP PC76 1U_0603_16V6K VOUT PC75 1U_0603_6.3V6M PC80 0.047U_0402_16V7K PGND NC VIN PR112 200K_0402_1% VREF PR107 1K_0402_1% AGND +3VALW PR108 10_0603_1% NC PC81 0.1U_0603_25V7K VCNTL GND VIN 2 PC74 10U_1206_25VAK 1 PU8 PQ27 PR113 MF2N7002W-G_SOT323-3 100K_0402_5% 2 G SUSP C S PC135 0.047U_0603_16V7K +1.8VALW PJP6 1 +1.8VALW JUMP_43X113 JUMP_43X113 PJP8 PJP9 PJP10 +1.2VSP B +0.9VSP 2 1 +2.5VS JUMP_43X113 PJP11 1 +1.2VS +1.5VSP 2 1 +1.5VS JUMP_43X113 JUMP_43X113 PJP12 PJP14 1 +0.9V +VSBP 1 JUMP_43X113 1 +VDD_CORE +VGA_CORE_P 1 +VDD_CORE JUMP_43X113 VIN PGND VFB AGND RTCVREF VTT VCCA VTT REFEN B PR115 60.4K_0402_1% PQ28 MF2N7002W-G_SOT323-3 2 G PR117 100K_0402_5% 1 JUMP_43X113 2 PC84 4.7U_1206_25V6K 2 +VGA_CORE_P PJP15 PJP13 +1.5VSP +VSB JUMP_43X113 +5VALW PU10 CM8562IS_PSOP8 PC83 1U_0603_16V6K 2 PC85 0.047U_0402_16V7K +2.5VSP PR116 51K_0402_1% +5VALW 1 PC82 4.7U_1206_25V6K 2 JUMP_43X113 2 +5VALWP PJP7 JUMP_43X79 AGND +1.8VALWP +3VALW PR114 10_0603_1% PC86 0.1U_0603_25V7K 1 +3VALWP PJP5 D SUSP S PC136 0.047U_0603_16V7K A A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2005/09/26 2006/09/26 Deciphered Date SCHEMATIC, M/B LA-3151P THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Size Document Number Custom Rev B 401412 Date: |, 09, 2006 Sheet 52 of 55 PL10 FBM-L11-322513-151LMAT_1210 PC91 10U_1206_25VAK 2 +5VALW 1 UGATE2 24 DH_1.8V PHASE2 25 LX_1.8V PHASE1 ISEN2 22 ISE_1.8V DL_1.8V D D D D VCC PU11 ISL6227CA-T_SSOP28 ISEN1 LGATE1 LGATE2 27 PGND1 PGND2 26 10 15 VOUT1 VSEN1 EN1 PG1 VOUT2 VSEN2 EN2 PG2/REF 20 19 21 16 OCSET2 18 +1.8VALWP PL12 1.8U_SIL104R-1R8_9.5A_30% PR126 1.5K_0402_1% PQ32 SI4810BDY-T1-E3_SO8 + PC104 0.01U_0402_25V7Z PC103 220U_D2_4VM_R15 UGATE1 C G S S S DL_VGA 23 PR125 1.5K_0402_1% ISE_VGA BOOT2 PQ30 SI4800BDY-T1-E3_SO8 PR127 0_0402_5% LX_VGA BOOT1 PC99 0.1U_0402_16V7K 1 2BST_VGA-16 PR120 0_0603_5% PR121 0_0603_5% BST_1.8V-1 SOFT2 S S S G 28 14 VIN SOFT1 0.01U_0402_25V7Z PC97 4700P_0402_25V7K 17 D D D D D D D D S S S G S S S G 12 PR128 10K_0402_1% Ipeak=16.40A @ PR134 0_0402_5% PR133 10K_0402_1% PR140 10K_0402_5% +3VALW +5VALW B PR139 110K_0402_1% 10K_0402_1% 2 PR138 56.2K_0402_1% PC105 0.1U_0402_16V7K 1@PR130 DDR VSE_1.8V 13 SUSP# OCSET1 PR136 0_0402_5% PR135 18.2K_0402_1% 2 PR137 100K_0402_5% 11 S PQ33 MF2N7002W-G_SOT323-3 @ PC107 0.01U_0402_25V7Z S G POWER_SEL D PR141 10K_0402_5% PQ34 MF2N7002W-G_SOT323-3 PC134 0.01U_0402_25V7Z B 10K_0402_1% D PR182 10K_0402_5% 22 G @ PR129 PC106 0.1U_0402_16V7K PR132 5.9K_0402_1% 1 PR131 10K_0402_5% VSE_VGA +3VS GND 2 @ +5VALW D D D D PR124 @ 0_0402_5% PC96 DH_VGA PQ31 FDS6676AS_SO8 PQ44 FDS6676AS_SO8 @ PC102 680P_0603_50V7K 1 2 PC101 0.01U_0402_25V7Z PR123 1K_0402_1% PR122 4.7_1206_5% + PC98 0.1U_0402_16V7K 2 PC100 330U_D2E_2.5VM BST_VGA 1.4U_SSF-13056-1R4_15.5A_20% C BST_1.8V +VGA_CORE_P PC95 2.2U_0805_10V6K PR119 2.2_0603_5% PC94 0.1U_0603_25V7K PD12 DAP202U_SOT323 PL11 D PC92 2200P_0402_25V7K 1 PC90 2200P_0402_25V7K PC89 10U_1206_25VAK 1 PC93 4.7U_0805_6.3V6K PQ29 SI7840DP-T1-E3_SO8 PR118 51_1206_5% B+ PC87 10U_1206_25VAK D PC88 10U_1206_25VAK ISL6227B+ Ipeak=8.5A For VGA chipset type, that should be dynamic change by everytime load BOM Imax=6A M52PG M54P M56P PR123=1K PR123=1K PR135=18.2K PR135=8.87K PR135=18.2K PR132=8.87K PR132=5.9K PR132=17.8K Iocpmin=8.76A Iocpmax=13.46A PR123=1K Imax=12.25A Iocpmin=22.07A L=1.000V L=1.102V L=1.102V H=0.949V H=1.001V H=0.949V Iocpmax=38.67A A A Compal Secret Data Security Classification 2005/09/26 Issued Date Deciphered Date 2006/09/26 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Compal Electronics, inc SCHEMATIC, M/B LA-3151P Size Document Number Custom Date: , Rev B 401412 09, 2006 Sheet 53 of 55 B+ CPU_B+ +5VS PGND1 27 PWRGD CSP1 16 17 PHASEGD CSN1 15 37 TWO-PH GND 18 38 SHDN# IC 40 @ @ DH2 21 TON LX2 22 LX2 OFS DL2 24 DL2 PGND2 23 CSP2 13 CSN2 14 PQ42 FDS6676AS_SO8 G D S D S D S D PQ41 S FDV301N_NL 1N SOT23-3 PR178 10_0402_5% PSI# @ PC132 4700P_0402_25V7K CPU_VSS_SENSE PC112 100U_25V_M PC110 0.01U_0402_25V7K PC111 2200P_0402_50V7K CPU_VCC_SENSE B PL15 0.56UH_ETQP4LR56WFC_21A_20% @ PR177 15K_0402_1% PR179 15K_0402_1% @ SKS30-04AT_TSMA 2 G PC128 0.01U_0402_25V7K PQ40 MF2N7002W-G_SOT323-3 PR175 0_0603_5% 1 D PQ39 SI7840DP-T1-E3_SO8 PD14 PR171 PR173 10_0402_1% PC129 4700P_0603_50V7K PR174 200K_0402_1% PR172 200K_0402_1% CPU_B+ 1 B MAX8774GTL+_TQFN40 PC130 +3VS C CSP2 SKIP# PR157 10_0402_5% PR166 0_0402_5% 2200P_0402_50V7K PC126 4.7U_1206_25V6K PC127 4.7U_1206_25V6K VRHOT# PC120 0.033U_0603_25V7K PC125 2 1 0_0402_5% PR176 4.7_1206_5% PR164 PQ43 FDS6676AS_SO8 G D S D S D S D REF 39 20 DH2 10 BST2 PH2 10KB_0603_ERTJ1VR103J PR156 15K_0402_1% POUT S G PR170 0_0402_5% GNDS 1 D PR169 169K_0603_1% 200K_0402_1% 12 CPU_B+ MAX8774_REF PR168 31.6K_0402_1% 11 CCI 0_0603_5% PC124 PR167 MAX8774_REF 0.1U_0603_16V7K FB CCV EP PC123 0.1U_0402_16V7K 150P_0402_50V8J TIME POUT PR161 PC119 2.55K_0603_1% 4700P_0402_25V7K FB PR163 20K_0402_1% 2 PC122 470P_0402_50V8J 0.22U_0603_16V7K 100K_0402_5% PR165 10K_0402_1% 71.5K_0402_1% PC121 1 PR160 2 @ PR159 PR162 10_0402_1% AGND @ PC131 680P_0603_50V8J For EC ATE D5 DL1 36 SHORT PADS PD13 SKS30-04AT_TSMA PR154 15K_0402_1% LX1 26 28 DL1 PC108 4.7U_1206_25V6K PC109 4.7U_1206_25V6K LX1 D4 D3 35 PL14 0.56UH_ETQP4LR56WFC_21A_20% 2 34 D +CPU_CORE FDS6676AS_SO8 DH1 29 DH1 41 VR_ON D2 MAX8774_VCC PQ38 MF2N7002W-G_SOT323-3 C BST1 33 + PR148 0_0603_5% PC118 PR151 680P_0603_50V8J 4.7_1206_5% 1 +3VS PR158 0_0402_5% D1 30 FDS6676AS_SO8 PQ37 G D S D S D S D VGATE J1 PR146 0_0603_5% 32 D D D D VID5 PQ36 VID4 25 THRM G S S S VID3 VDD D0 VID2 VCC PQ35 SI7840DP-T1-E3_SO8 PC117 4700P_0402_25V7K VID1 31 PC116 0.22U_0603_16V7K MAX8774_VCC 19 PR144 0_0402_5% PR145 0_0402_5% PR147 0_0402_5% PR149 0_0402_5% PR150 0_0402_5% PR152 0_0402_5% PR153 0_0402_5% PR155 100K_0402_1% VID0 PC115 0.01U_0402_25V7K PC114 2.2U_0603_10V6K PU12 @ PR143 10K_0402_5% PC113 2.2U_0603_6.3V6K PR142 10_0402_5% +3VS D PL13 FBMA-L18-453215-900LMA90T_1812 PH3 10KB_0603_ERTJ1VR103J PC133 0.033U_0603_25V7K CSP2 PR180 0_0603_5% AGND1 PR181 A A 0_0402_5% 2005/09/26 Issued Date Deciphered Date 2006/09/26 Title SCHEMATIC, M/B LA-3151P THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Compal Electronics, inc Compal Secret Data Security Classification Size Document Number Custom Rev B 401412 Date: , 09, 2006 Sheet 54 of 55 Version change list (P.I.R List) Item D Fixed Issue Reason for change Rev PG# Modify List Page of for PWR VER Phase D C C 10 11 B B A A Compal Electronics, Inc Title SCHEMATIC, M/B LA-3151P Size Document Number Rev B 401412 Date: |, 09, 2006 Sheet 55 of 55 ... FS1 FS0 CPU SRCCLK [2:1] 0 Hi-Z 100 .00 0 X 100 .00 1 80. 00 100 .00 1 2 20. 00 100 .00 0 100 .00 1 1 COMMENT PCI USB Hi-Z Hi-Z 48 .00 Reserved X /3 X/6 48 .00 Reserved 60. 00 30 . 00 48 .00 Reserved 36 .56 73. 12... SERIRQ R299 R 30 0 R 30 1 R 30 2 R 30 4 R 30 5 R 30 6 1 1 1 2 2 2 2 1 Modify 11 /07 C942 15P _04 02_50V8J A @ JUMP_43X39 10K _04 02_5% 10K _04 02_5% 100 K _04 02_5% 100 K _04 02_5% 100 K _04 02_5% 100 K _04 02_5% 10K _04 02_5% Please... C326 0. 1U _04 02_16V4Z +3VS C 331 0. 1U _04 02_16V4Z 400 mA 22U _08 05_6.3V6M C 337 2 0. 1U _04 02_16V4Z 0. 1U _04 02_16V4Z C 339 C3 40 50mA 0. 1U _04 02_16V4Z 0. 1U _04 02_16V4Z C345 C346 0. 1U _04 02_16V4Z 100 mA 0. 1U _04 02_16V4Z