A B C D E 1 Compal Confidential 2 PAV70 Schematics Document Intel Pineview Processor with Tigerpoint + DDRII 2010-07-01 3 REV: 1.0 4 2006/08/18 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2007/8/18 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C D Title Cover Page Size B Date: Document Number Rev 1.0 LA-6221P Friday, July 02, 2010 Sheet E of 39 A B C D E Clock Generator CK505 page Compal Confidential Model Name : File Name : LA-6221P CRT Conn page 10 1 ZZZ RGB PCB PAV70@ DAZ0F300201 LVDS LCD Conn DDRII-SO-DIMM page 1.8V DDRII 667 22x22mm page Thermal Sensor Memory BUS(DDRII) Pineview FCBGA 559 page 4,5,6 ZZZ EMC1402 page DMI X2 mode GEN1 PCB PAV50@ DAZ0F000300 USB HDA Tigerpoint PCI-Express USB Port X3 page 15 PCBGA360 BlueTooth 17x17mm page 23 SATA page 11,12,13,14 CMOS CAM page MINI Card x1 3G MINI Card x1 WLAN 10/100 Ethernet page 17 page 18 page 16 HDD AR8152L 3G page 15 page 17 LPC BUS Transfermer WLAN 3 page 18 Aralia Codec Power ON/OFF ALC272 RJ45 DC/DC Interface Card Reader ENE6252 page 19 page 27 page 26 ENE KBC KB926page 3VALW/5VALW page 27 DC IN page 27 page 22 SPI 24 0.89VP/1.5VP BATT IN 0.9VSP/2.5VSP page 32 page 29 CHARGER 、33 Int.KBD page 30 SPI ROM page 25 1.8V/VCCP page 25 Touch Pad page 32 AMP & INT Speaker INT MIC HeadPhone & MIC Jack SD/MMC/MS CONN I/O Board page 25 CPU_CORE page 34 2006/08/18 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2007/8/18 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C D Title Block Diagrams Size B Date: Document Number Rev 1.0 LA-6221P Thursday, July 01, 2010 Sheet E of 39 A B C D E Voltage Rails External PCI Devices Power Plane Description S1 S3 S5 VIN Adapter power supply (19V) ON ON ON B+ AC or battery power rail for power circuit ON ON ON +CPU_CORE Core voltage for CPU ON OFF OFF +0.9VS 0.9V switched power rail for DDR terminator ON OFF OFF +VCCP VCCP switched power rail ON OFF OFF +1.5VS 1.5V switched power rail ON OFF OFF OFF DEVICE IDSEL # REQ/GNT # PIRQ No PCI Device +1.8V 1.8V power rail for DDR ON ON +0.89V Graphic core power rail ON OFF OFF +3VALW 3.3V always on power rail ON ON ON* +3VS 3.3V switched power rail ON OFF OFF Device Address Device Address +5VALW 5V always on power rail ON ON ON* Smart Battery 0001 011X b EMC1402 100_1100 +5VS 5V switched power rail ON OFF OFF +VSB VSB always on power rail ON ON ON* +RTCVCC RTC power ON ON ON EC SM Bus1 address EC SM Bus2 address Tiger Point SM Bus address Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF 2 SIGNAL STATE Full ON SLP_S3# SLP_S4# SLP_S5# HIGH S1(Power On Suspend) HIGH HIGH HIGH S3 (Suspend to RAM) LOW S4 (Suspend to Disk) LOW S5 (Soft OFF) LOW HIGH +VALW +V +VS Clock ON ON ON ON HIGH ON ON ON LOW HIGH HIGH LOW HIGH ON ON OFF OFF ON OFF OFF OFF LOW LOW ON OFF OFF OFF Device Address Clock Generator (SLG8SP556VTR) 1101 001Xb DDR DIMMA 1010 000Xb UHCI1 EHCI1 UHCI2 BOARD ID Table(Page 17) UHCI3 Vcc Ra/Rc/Re UHCI4 3.3V +/- 5% 100K +/- 5% Rb / Rd / Rf 8.2K +/- 5% 18K +/- 5% 33K +/- 5% 56K +/- 5% 100K +/- 5% 200K +/- 5% NC Board ID 0(EVT) 1(DVT) 2(PVT) 3(MP) V AD_BID V 0.216 V 0.436 V 0.712 V 1.036 V 1.453 V 1.935 V 2.500 V V AD_BID typ V 0.250 V 0.503 V 0.819 V 1.185 V 1.650 V 2.200 V 3.300 V PCIE table USB table V AD_BID max V 0.289 V 0.538 V 0.875 V 1.264 V 1.759 V 2.341 V 3.300 V EHCI2 UHCI5 UHCI6 Port0 Port1 Port2 Port3 Port4 Port5 Port6 Port7 Port8 Port9 Port10 Port11 MB USB Conn1 MB USB Conn2 MB USB Conn3 CMOS Card Reader WWAN BT WLAN PCIE port1 LAN PCIE port2 Wireless Card PCIE port3 3G PCIE port4 PCIE port5 SATA table SATA port0 SATA port2 SATA port3 PCB Revision 0.1 0.2 SATA port4 SATA port5 2006/08/18 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2007/8/18 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A HDD SATA port1 BOARD ID Table Board ID PCIE port6 B C D Title Notes List Size B Date: Document Number Rev 1.0 LA-6221P Thursday, July 01, 2010 Sheet E of 39 (7) DDR_A_DQS#[0 7] PINEVIEW_M (7) DDR_A_D[0 63] PINEVIEW_M U71A U71B REV = 1.1 (7) DDR_A_DM[0 7] REV = 1.1 F3 F2 H4 G3 DMI_RXP_0 DMI_RXN_0 DMI_RXP_1 DMI_RXN_1 N7 N6 EXP_CLKINN EXP_CLKINP DMI_TXP_0 DMI_TXN_0 DMI_TXP_1 DMI_TXN_1 G2 G1 H3 J2 DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 (7) DDR_A_DQS[0 7] DMI_TX0 (12) DMI_TX#0 (12) DMI_TX1 (12) DMI_TX#1 (12) (7) DDR_A_MA[0 14] DMI DMI_RX0_C DMI_RX#0_C DMI_RX1_C DMI_RX#1_C D (8) CLK_CPU_EXP# (8) CLK_CPU_EXP R10 R9 N10 N9 EXP_RCOMPO EXP_ICOMPI EXP_RBIAS L10 L9 L8 RSVD_TP RSVD_TP N11 P11 EXP_TCLKINN EXP_TCLKINP RSVD RSVD K2 J1 M4 L3 RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD R162 R203 49.9_0402_1% 750_0402_1% T38 T39 (5) (5) (7) DDR_A_WE# (7) DDR_A_CAS# (7) DDR_A_RAS# K3 L2 M2 N2 XDP_PREQ# XDP_PRDY# (5) (5) DMI_RX0 (12) DMI_RX#0 C436 0.1U_0402_10V7K DMI_RX#0_C 0.1U_0402_10V7K DMI_RX1_C 0.1U_0402_10V7K C (12) (12) DMI_RX1 DMI_RX#1 C437 C438 DMI_RX0_C 1 (7) DDR_A_BS0 (7) DDR_A_BS1 (7) DDR_A_BS2 (5) (5) XDP_BPM#3 XDP_BPM#2 XDP_BPM#1 XDP_BPM#0 XDP_BPM#1 XDP_BPM#0 (8) (8) +VCCP (5,13,16,17,18,24,26) PLTRST# Close to CPU R354 R347 CPU_ITP CPU_ITP# PLTRST# R348 (5) (5) (5) (5) XDP_PREQ# XDP_PRDY# XDP_BPM#3 XDP_BPM#2 (5,13) H_PWRGD (13) SLPIOVR# DMI_RX#1_C 0.1U_0402_10V7K DDR_A_WE# DDR_A_CAS# DDR_A_RAS# AK22 AJ22 AK21 DDR_A_WE# DDR_A_CAS# DDR_A_RAS# DDR_A_BS0 DDR_A_BS1 DDR_A_BS2 AJ20 AH20 AK11 DDR_A_BS_0 DDR_A_BS_1 DDR_A_BS_2 DDR_CS#0 DDR_CS#1 AH22 AK25 AJ21 AJ25 DDR_A_CS#_0 DDR_A_CS#_1 DDR_A_CS#_2 DDR_A_CS#_3 DDR_CKE0 DDR_CKE1 AH10 AH9 AK10 AJ8 DDR_A_CKE_0 DDR_A_CKE_1 DDR_A_CKE_2 DDR_A_CKE_3 M_ODT0 M_ODT1 AK24 AH26 AH24 AK27 DDR_A_ODT_0 DDR_A_ODT_1 DDR_A_ODT_2 DDR_A_ODT_3 Must be placed within 500 mils from Pineview-M pins (7) DDR_CS#0 (7) DDR_CS#1 JP16 (12) DDR_A_MA_0 DDR_A_MA_1 DDR_A_MA_2 DDR_A_MA_3 DDR_A_MA_4 DDR_A_MA_5 DDR_A_MA_6 DDR_A_MA_7 DDR_A_MA_8 DDR_A_MA_9 DDR_A_MA_10 DDR_A_MA_11 DDR_A_MA_12 DDR_A_MA_13 DDR_A_MA_14 XDP_TDO XDP_TRST# XDP_TDI XDP_TMS (5) XDP_TCK 1K_0402_5% 1K_0402_5% 1K_0402_1% XDP_TDO XDP_TRST# XDP_TDI XDP_TMS XDP_TCK 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 CONN@ 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 G1 G2 (7) DDR_CKE0 (7) DDR_CKE1 (7) M_ODT0 (7) M_ODT1 (7) (7) (7) (7) M_CLK_DDR0 M_CLK_DDR#0 M_CLK_DDR1 M_CLK_DDR#1 M_CLK_DDR0 M_CLK_DDR#0 M_CLK_DDR1 M_CLK_DDR#1 ACES_87151-24051 51 +-1% 0402 R342 51 +-1% 0402 XDP_TDO R343 51 +-1% 0402 XDP_PREQ# R344 51 +-1% 0402 +1.8V R341 XDP_TMS DDR_A_CK_0 DDR_A_CK_0# DDR_A_CK_1 DDR_A_CK_1# AC15 AD15 AF13 AG13 DDR_A_CK_3 DDR_A_CK_3# DDR_A_CK_4 DDR_A_CK_4# AD17 AC17 AB15 AB17 RSVD RSVD RSVD RSVD AB4 AK8 RSVD RSVD R370 10K_0402_5% @ T40 AB11 AB13 T41 R50 1K_0402_1% B DDR_RPD DDR_RPU XDP_TRST# R345 51 +-1% 0402 XDP_TCK R346 51 +-1% 0402 R142 1K_0402_1% Modify follow KAV60 schematic 06/12 2.2U_0603_10V6K APL5607KI-TRG_SO8 C1221 0.1U_0402_16V4Z R242 D38 R256 10K_0402_5% +VCC_FAN1 (24) FAN_SPEED1 C311 100P_0402_50V8J JP12 3 40mil G1 G2 ACES_85204-03001 CONN@ AL28 AK28 AJ26 AK29 DDR_VREF DDR_RPD DDR_RPU RSVD DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 AD8 AD10 AE8 DDR_A_DQS2 DDR_A_DQS#2 DDR_A_DM2 AG8 AG7 AF10 AG11 AF7 AF8 AD11 AE10 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 AK5 AK3 AJ3 DDR_A_DQS3 DDR_A_DQS#3 DDR_A_DM3 AH1 AJ2 AK6 AJ7 AF3 AH2 AL5 AJ6 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 AG22 AG21 AD19 DDR_A_DQS4 DDR_A_DQS#4 DDR_A_DM4 AE19 AG19 AF22 AD22 AG17 AF19 AE21 AD21 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_DQS_5 DDR_A_DQS#_5 DDR_A_DM_5 AE26 AG27 AJ27 DDR_A_DQS5 DDR_A_DQS#5 DDR_A_DM5 DDR_A_DQ_40 DDR_A_DQ_41 DDR_A_DQ_42 DDR_A_DQ_43 DDR_A_DQ_44 DDR_A_DQ_45 DDR_A_DQ_46 DDR_A_DQ_47 AE24 AG25 AD25 AD24 AC22 AG24 AD27 AE27 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 AE30 AF29 AF30 DDR_A_DQS6 DDR_A_DQS#6 DDR_A_DM6 AG31 AG30 AD30 AD29 AJ30 AJ29 AE29 AD28 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 AB27 AA27 AB26 DDR_A_DQS7 DDR_A_DQS#7 DDR_A_DM7 AA24 AB25 W24 W22 AB24 AB23 AA23 W27 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63 DDR_A_DQS_6 DDR_A_DQS#_6 DDR_A_DM_6 DDR_A_DQ_48 DDR_A_DQ_49 DDR_A_DQ_50 DDR_A_DQ_51 DDR_A_DQ_52 DDR_A_DQ_53 DDR_A_DQ_54 DDR_A_DQ_55 DDR_RPU 80.6_0402_1% DDR_A_DQS_7 DDR_A_DQS#_7 DDR_A_DM_7 R243 DDR_A_DQ_56 DDR_A_DQ_57 DDR_A_DQ_58 DDR_A_DQ_59 DDR_A_DQ_60 DDR_A_DQ_61 DDR_A_DQ_62 DDR_A_DQ_63 DDR_RPD 80.6_0402_1% D C B A OF PINEVIEW-M_FCBGA8559 Add 2009-6-17 2006/08/18 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2007/8/18 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC AB6 AB7 AE5 AG5 AA5 AB5 AB9 AD6 DDR_A_DQ_32 DDR_A_DQ_33 DDR_A_DQ_34 DDR_A_DQ_35 DDR_A_DQ_36 DDR_A_DQ_37 DDR_A_DQ_38 DDR_A_DQ_39 C1222 0.01U_0402_16V7K PJDLC05C_SOT23-3 D40 PJDLC05C_SOT23-3 C1150 1000P_0402_50V7K A 4.7U_0603_6.3V6K +3VS XDP_TRST# XDP_TDI PJDLC05C_SOT23-3 4.7U_0603_6.3V6K C313 1 D39 C1151 0.01U_0402_16V7K DDR_A_DQS1 DDR_A_DQS#1 DDR_A_DM1 DDR_A_DQS_4 DDR_A_DQS#_4 DDR_A_DM_4 08/13 XDP_PREQ# XDP_TDO C314 1 GND GND GND GND AB8 AD7 AA9 DDR_A_DQ_24 DDR_A_DQ_25 DDR_A_DQ_26 DDR_A_DQ_27 DDR_A_DQ_28 DDR_A_DQ_29 DDR_A_DQ_30 DDR_A_DQ_31 2 EN VIN VOUT VSET +VCC_FAN1 R47 330_0402_5% DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_DQS_3 DDR_A_DQS#_3 DDR_A_DM_3 XDP_TMS XDP_TCK D19@ DAN217_SC59 EN_FAN1 Modify D38 D39 D40 Pin define (24) AC4 AC1 AF4 AG2 AB2 AB3 AE2 AE3 DDR_A_DQ_16 DDR_A_DQ_17 DDR_A_DQ_18 DDR_A_DQ_19 DDR_A_DQ_20 DDR_A_DQ_21 DDR_A_DQ_22 DDR_A_DQ_23 +1.8V U12 DDR_A_DQ_0 DDR_A_DQ_1 DDR_A_DQ_2 DDR_A_DQ_3 DDR_A_DQ_4 DDR_A_DQ_5 DDR_A_DQ_6 DDR_A_DQ_7 DDR_A_DQS_2 DDR_A_DQS#_2 DDR_A_DM_2 DDR_A DDR_A_DQS0 DDR_A_DQS#0 DDR_A_DM0 DDR_A_DQ_8 DDR_A_DQ_9 DDR_A_DQ_10 DDR_A_DQ_11 DDR_A_DQ_12 DDR_A_DQ_13 DDR_A_DQ_14 DDR_A_DQ_15 RSVD_TP RSVD_TP +5VS C312 AD3 AD2 AD4 DDR_A_DQS_1 DDR_A_DQS#_1 DDR_A_DM_1 R369 10K_0402_5% +VCCP XDP_TDI +5VS AG15 AF15 AD13 AC13 +1.8V XDP Reserve FAN1 Conn DDR_A_DQS_0 DDR_A_DQS#_0 DDR_A_DM_0 OF PINEVIEW-M_FCBGA8559 C435 AH19 AJ18 AK18 AK16 AJ14 AH14 AK14 AJ12 AH13 AK12 AK20 AH12 AJ11 AJ24 AJ10 Title Pineview(1/3) Size Document Number Custom Date: Rev 1.0 LA-6221P Friday, July 02, 2010 Sheet of 39 CRT_RED CRT_GREEN CRT_BLUE CRT_IRTN N31 P30 P29 N30 CRT_DDC_DATA CRT_DDC_CLK L31 L30 DAC_IREF P28 10_0402_5% 10_0402_5% GMCH_CRT_R GMCH_CRT_G GMCH_CRT_B REFCLKINP REFCLKINN REFSSCLKINP REFSSCLKINN LVDS_ACLK# LVDS_ACLK LVDS_A0# LVDS_A0 LVDS_A1# LVDS_A1 LVDS_A2# LVDS_A2 RSVD_TP RSVD_TP RSVD_TP RSVD_TP U25 U26 R23 R24 N26 N27 R26 R27 LA_CLKN LA_CLKP LA_DATAN_0 LA_DATAP_0 LA_DATAN_1 LA_DATAP_1 LA_DATAN_2 LA_DATAP_2 R22 J28 N22 N23 L27 L26 L23 K25 K23 K24 H26 LIBG LVBG LVREFH LVREFL LBKLT_EN LBKLT_CTL LCTLA_CLK LCTLB_DATA LDDC_CLK LDDC_DATA LVDD_EN SMI# A20M# FERR# LINT0 LINT1 IGNNE# STPCLK# E7 H7 H6 F10 F11 E5 F8 H_SMI# H_A20M# H_FERR# H_INTR H_NMI H_IGNNE# H_STPCLK# DPRSTP# DPSLP# INIT# PRDY# PREQ# G6 G10 G8 E11 F15 H_DPRSTP# H_DPSLP# H_INIT# XDP_PRDY# XDP_PREQ# THERMTRIP# E13 H_THERMTRIP# PROCHOT# CPUPWRGOOD C18 W1 H_PROCHOT# H_PW RGD GTLREF VSS A13 H27 H_GTLREF RSVD RSVD L6 E17 BCLKN BCLKP H10 J10 BSEL_0 BSEL_1 BSEL_2 K5 H5 K6 CPU_BSEL0 CPU_BSEL1 CPU_BSEL2 VID_0 VID_1 VID_2 VID_3 VID_4 VID_5 VID_6 H30 H29 H28 G30 G29 F29 E29 CPU_VID0 CPU_VID1 CPU_VID2 CPU_VID3 CPU_VID4 CPU_VID5 CPU_VID6 RSVD RSVD RSVD RSVD L7 D20 H13 D18 RSVD_TP RSVD_TP EXTBGREF K9 D19 K7 R151 be placed U71.R22 R151 2.37K_0402_1% CPU_DREFCLK (8) CPU_DREFCLK# (8) CPU_SSCDREFCLK (8) CPU_SSCDREFCLK# (8) GMCH_ENBKL (24) GMCH_ENBKL (9) DPST_PW M (9) LVDS_SCL (9) LVDS_SDA (9) GMCH_ENVDD 0_0402_5% R200 PM_DPRSLPVR (13) PM_EXTTS#0 (7) H_DPRSTP# (13) H_DPSLP# (13) H_INIT# (11) XDP_PRDY# (4) XDP_PREQ# (4) H_THERMTRIP# (11) H_PW RGD (4,13) CLK_CPU_HPLCLK# (8) CLK_CPU_HPLCLK (8) C Modify 08/04 RSVD_TP RSVD_TP RSVD_TP RSVD_TP H_PW ROK R305 @ VGATE 0_0402_5% R306 (4) (4) (4) (4) (8,13,24,35) G11 E15 G13 F13 XDP_BPM#0 XDP_BPM#1 XDP_BPM#2 XDP_BPM#3 T48 T49 T50 T51 EC_PW ROK (13,24) 0_0402_5% (4) (4) (4) (4) (4) To be placed