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E D C B A schematic-laptop.blogspot.com Compal Confidential Model Name : Q1VZC File Name :LA-8941P BOM P/N:43 ZZZ1 ZZZ2 ZZZ3 ZZZ4 LA-8941P DA2@ LS-8941P DA2@ LS-8942P DA2@ LS-8943P DA2@ ZZZ5 PCB DAZ@ Compal Confidential 2 Q1VZC M/B Schematics Document Intel Sandy Bridge ULV Processor + Panther Point PCH 2012-04-19 3 REV:1.0 4 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2011/11/22 2012/11/22 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Cover Page Rev 1.0 Q1VZC M/B LA-8941P Schematic Date: A B C D Friday, April 20, 2012 Sheet E of 45 E D C B A schematic-laptop.blogspot.com Compal Confidential Model Name : Q1VZC File Name :LA-8941P Memory BUS(DDRIII) 204pin DDRIII-SO-DIMM X2 Intel Sandy Bridge ULV page 11,12 BANK 0, 1, 2, Dual Channel 1.5V DDRIII 1066/1333 Processor BGA1023 17W eDP(UMA) page 4~10 FDI x8 CRT Conn page 24 HDMI Conn LVDS/eDP Conn page 23 CLK=100MHz page 22 DMI x4 CLK=100MHz 2.7GT/s USB 2.0 conn x1(Option for USB3.0) page 34 2.5GB/s x4 TMDS(UMA) RGB(UMA) Intel HD Audio Broadcom 57785page MINI Card WLAN 25 page 36 Port PCI-Express x (PCIE2.0 5GT/s) 100MHz PCH Port 10 Port Port 3.3V 24MHz page 22 Port 2,3 LAN(GbE)/CardReader Panther Point-M CMOS Camera page 30 Port USBx14 3.3V 48MHz LVDS(UMA) USB 2.0 conn x2 SPI SATA x (GEN2 3.0GT/S ,GEN3 6GT/S) HDA Codec 100MHz ALC271X-VB6 989pin BGA page 31 page 13~21 Int Speaker page 31 SPI ROM x2 LPC BUS page 13 GEN3 Port LS-8941P SATA HDD Conn LED/B LS-8942P CLK=33MHz IO/B ENE KB9012 RTC CKT page 30 page 24 page 28 page 29 LS-8943P page 13 HDD/B page 24 Power On/Off CKT Touch Pad page 36 Int.KBD page 30 page 30 TPM page 30 DC/DC Interface CKT page 33 2011/11/22 Issued Date page 34~43 Compal Electronics, Inc Compal Secret Data Security Classification Power Circuit DC/DC Deciphered Date 2012/11/22 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title B C D Rev 1.0 Q1VZC M/B LA-8941P Schematic Date: A Block Diagrams Size Document Number Custom Friday, April 20, 2012 Sheet E of 45 E D C B A schematic-laptop.blogspot.com SIGNAL STATE Voltage Rails Power Plane Full ON Description S1 S3 S5 N/A VIN Adapter power supply (19V) N/A N/A BATT+ Battery power supply (12.6V) N/A N/A N/A B+ AC or battery power rail for power circuit N/A N/A N/A +CPU_CORE Core voltage for CPU ON OFF OFF +VGFX_CORE Core voltage for UMA graphic ON OFF OFF OFF OFF OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF Board ID / SKU ID Table for AD channel +1.5VS +1.5V to +1.5VS switched power rail ON OFF OFF Board ID +1.8VS (+5VALW or +3VALW) to 1.8V switched power rail to PCH & GPU ON OFF OFF ON* ON* +5VALWP to +5VALW power rail ON ON +5VALW to +5VREF_SUS power rail for PCH (Short resister) ON ON ON* +5VS +5VALW to +5VS switched power rail ON OFF OFF +VSB +VSBP to +VSB always on power rail for sequence control ON ON ON* +RTCVCC RTC power ON ON ON LOW OFF Vcc Ra/Rc/Re +5VALW ON OFF OFF +5VREF_SUS ON ON ON ON* ON ON ON OFF HIGH ON +1.5VP to +1.5V power rail for DDRIII OFF HIGH HIGH +1.5V ON HIGH HIGH OFF +3VALW to +3VS power rail ON LOW LOW OFF +3VS Clock HIGH OFF ON ON LOW OFF ON ON LOW ON ON ON LOW ON ON HIGH LOW +0.75VP to +0.75VS switched power rail for DDR terminator +3VALW to +VCCSUS3_3 power rail for PCH (Short Jump) +VS HIGH S4 (Suspend to Disk) +1.05VS_VTTP to +1.05VS_VTT switched power rail for CPU +3VALW always on power rail +V HIGH S3 (Suspend to RAM) +0.75VS +3VALW +VALW HIGH S1(Power On Suspend) +1.05VS_VTT +VCCSUS3_3 SLP_S1# SLP_S3# SLP_S4# SLP_S5# 3.3V +/- 5% 100K +/- 5% Rb / Rd / Rf 8.2K +/- 5% 18K +/- 5% 33K +/- 5% 56K +/- 5% 100K +/- 5% 200K +/- 5% NC V AD_BID V 0.216 V 0.436 V 0.712 V 1.036 V 1.453 V 1.935 V 2.500 V V AD_BID typ V 0.250 V 0.503 V 0.819 V 1.185 V 1.650 V 2.200 V 3.300 V V AD_BID max V 0.289 V 0.538 V 0.875 V 1.264 V 1.759 V 2.341 V 3.300 V BOARD ID Table Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF EC SM Bus1 address Device Address Smart Battery 0001 011X b PCH SM Bus address Device ChannelA ChannelB A0 B0 1010 000X 1010 010X BTO Option Table PCB Revision 0.1 0.2 0.3 1.0 BTO Item BOM Structure Celeron 867 C867@ Pentium 977 P977@ Unpop @ eDP Panel EDP@ LVDS Panel LVDS@ Connector CONN@ USB3 Only USB3@ Deep S3 DS3@ Normal S3 S3@ Intel i5/i7 CPU only I57@ Celeron/Pentium/i3 CP3@ CPU only USB Port Table USB 2.0 USB 1.1 Port Address DIMM0 DIMM0 Board ID JDIMM1(STD) JDIMM2(REV) UHCI0 UHCI1 EHCI1 UHCI2 UHCI3 UHCI4 EHCI2 UHCI5 UHCI6 10 11 12 13 External USB Port USB 2.0(Options for USB3.0) USB port(Left 2.0) USB Port(Left 2.0) USB 3.0 Port XHCI Mini Card(WLAN) Camera USB Port(Right 3.0) 4 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2011/11/22 2012/11/22 Deciphered Date Title Notes List THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Rev 1.0 Q1VZC M/B LA-8941P Schematic Date: A B C D Friday, April 20, 2012 Sheet E of 45 B A C D E schematic-laptop.blogspot.com +1.05VS_VTT R1 24.9_0402_1% UCPU1A DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3 DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3 U7 W11 W1 AA6 W6 V4 Y2 AC9 FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7 U6 W10 W3 AA7 W7 T4 AA3 AC8 FDI_FSYNC0 FDI_FSYNC1 FDI_INT FDI_LSYNC0 FDI_LSYNC1 EDP_HPD# U11 AA10 AG8 EDP_AUXN EDP_AUXP EDP_TXN0 EDP_TXN1 EDP_TXP0 EDP_TXP1 AG4 AF4 AC3 AC4 AE11 AE7 AF3 AD2 AG11 AC1 AA4 AE10 AE6 EDP_HPD# PEG_RX#[0] PEG_RX#[1] PEG_RX#[2] PEG_RX#[3] PEG_RX#[4] PEG_RX#[5] PEG_RX#[6] PEG_RX#[7] PEG_RX#[8] PEG_RX#[9] PEG_RX#[10] PEG_RX#[11] PEG_RX#[12] PEG_RX#[13] PEG_RX#[14] PEG_RX#[15] DMI_TX#[0] DMI_TX#[1] DMI_TX#[2] DMI_TX#[3] DMI_TX[0] DMI_TX[1] DMI_TX[2] DMI_TX[3] FDI0_TX#[0] FDI0_TX#[1] FDI0_TX#[2] FDI0_TX#[3] FDI1_TX#[0] FDI1_TX#[1] FDI1_TX#[2] FDI1_TX#[3] FDI0_TX[0] FDI0_TX[1] FDI0_TX[2] FDI0_TX[3] FDI1_TX[0] FDI1_TX[1] FDI1_TX[2] FDI1_TX[3] FDI0_FSYNC FDI1_FSYNC FDI_INT FDI0_LSYNC FDI1_LSYNC eDP_COMPIO eDP_ICOMPO eDP_HPD# eDP_AUX# eDP_AUX eDP_TX#[0] eDP_TX#[1] eDP_TX#[2] eDP_TX#[3] PEG_RX[0] PEG_RX[1] PEG_RX[2] PEG_RX[3] PEG_RX[4] PEG_RX[5] PEG_RX[6] PEG_RX[7] PEG_RX[8] PEG_RX[9] PEG_RX[10] PEG_RX[11] PEG_RX[12] PEG_RX[13] PEG_RX[14] PEG_RX[15] PEG_TX#[0] PEG_TX#[1] PEG_TX#[2] PEG_TX#[3] PEG_TX#[4] PEG_TX#[5] PEG_TX#[6] PEG_TX#[7] PEG_TX#[8] PEG_TX#[9] PEG_TX#[10] PEG_TX#[11] PEG_TX#[12] PEG_TX#[13] PEG_TX#[14] PEG_TX#[15] PEG_TX[0] PEG_TX[1] PEG_TX[2] PEG_TX[3] PEG_TX[4] PEG_TX[5] PEG_TX[6] PEG_TX[7] PEG_TX[8] PEG_TX[9] PEG_TX[10] PEG_TX[11] PEG_TX[12] PEG_TX[13] PEG_TX[14] PEG_TX[15] eDP EDP_HPD# AA11 AC12 DMI_RX[0] DMI_RX[1] DMI_RX[2] DMI_RX[3] W=12mil L=500mil S=15mil K3 M7 P4 T3 FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7 EDP_COMP R3 1K_0402_5% EDP@ K1 M8 N4 R2 R2 24.9_0402_1% +1.05VS_VTT N3 P7 P3 P11 PCI EXPRESS GRAPHICS DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 DMI_CRX_PTX_P3 eDP_COMPIO and ICOMPO signals should be shorted near balls and routed with typical impedance
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