A B C D E ZZZ DAZ@ DAZ08400100 1 KAV60 LA-5141P LS-5141P/5142P/5143P ZZZ DA2@ DA60000BO10 LA-5141P REV1 M/B ZZZ DA2@ DA20000FM10 LS-5141P REV1 PWR/B Compal Confidential ZZZ DA2@ DA60000BU10 2 LS-5142P REV1 SDIO/B ZZZ DA2@ DA60000BT10 KAV60 Schematics Document LS-5143P REV1 CARDREADER/B www.manuals.clan.su Intel Diamondville Processor with Calistoga(945GSE) + DDRII + ICH7M 2009-03-06 3 REV: 1.0 4 2006/08/18 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2007/8/18 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C D SCHEMATIC,MB A5141 Document Number Rev B 401690 Sheet Tuesday, March 10, 2009 E of 40 A B C E Diamondville SC Compal Confidential D FCBGA8 437Pins Model Name : KAV60 File Name : LA-5141P P/N : DA60000BO00 22x22mm CRT Conn page 4,5 FSB 400/533MHz H_A#(3 31) Clock Generator CK505 page 12 H_D#(0 63) page 14 RGB DDRII-SO-DIMM page 11 1.8V DDRII 400/533 LVDS LCD Conn Thermal Sensor Memory BUS(DDRII) Calistoga GSE FCBGA998 27x27mm page 13 page 6,7,8,9,10 EMC1402 page DMI X2 mode USB Port X1 page 28 USB HDA ICH7M BGA652 PCI-Express I/O Board X2 to I/O board CONN RTS5159E 31x31mm page 22 page 15,16,17,18 SATA 10/100 Ethernet www.manuals.clan.su SDIO CONN MINI Card x2 to I/OBoard CONN page JP7 AR8114A page 27 page 19 page 22 page 24 BlueToothX1 page19 22 Aralia Codec CMOS CAM page13 ALC272 LPC BUS page 20 WLANX1 Transfermer page19 page 24 3 WWANX1 page19 Power ON/OFF & LED CONN RJ45 DC/DC Interface page 24 page 29 AMP & INT Speaker page 21 page 26 ENE KBC KB926page 3VALW/5VALW page 33 DC IN page 31 BATT IN 1.5VS/0.9VS/ 2.5VS CHARGER 1.8V/VCCP page 32 HeadPhone & MIC Jack INT DMIC CONN page 21 page 13 SPI 25 I/O board SATA CONN page 36 Int.KBD page 34 SPI ROM page 27 page 35 USB Port X2 page 25 Touch Pad page 27 USB Card Reader x1 RTS5159E CPU_CORE page 37 2006/08/18 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2007/8/18 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C D SCHEMATIC,MB A5141 Document Number Rev B 401690 Sheet Tuesday, March 10, 2009 E of 40 A B C D E 1 Voltage Rails External PCI Devices Power Plane Description S1 S3 S5 VIN Adapter power supply (19V) N/A N/A N/A B+ AC or battery power rail for power circuit N/A N/A N/A +CPU_CORE Core voltage for CPU ON OFF OFF +0.9VS 0.9V switched power rail for DDR terminator ON OFF OFF +VCCP VCCP switched power rail ON OFF OFF +1.5VS 1.5V switched power rail ON OFF OFF +1.8V 1.8V power rail for DDR ON ON OFF +2.5VS 2.5V switched power rail ON OFF OFF +3VALW 3.3V always on power rail ON ON ON* +3VS 3.3V switched power rail ON OFF OFF +5VALW 5V always on power rail ON ON ON* +5VS 5V switched power rail ON OFF OFF +VSB VSB always on power rail ON ON ON* +RTCVCC RTC power ON ON ON DEVICE SIGNAL SLP_S3# SLP_S4# SLP_S5# +VALW +V HIGH HIGH ON ON HIGH HIGH HIGH ON LOW HIGH HIGH ON S4 (Suspend to Disk) LOW LOW HIGH S5 (Soft OFF) LOW LOW LOW S1(Power On Suspend) S3 (Suspend to RAM) +VS PIRQ EC SM Bus1 address EC SM Bus2 address Device Address Device Address Smart Battery 0001 011X b EMC1402 1001 100X b EEPROM(24C16/02) 1010 000X b Clock www.manuals.clan.su HIGH Full ON REQ/ GNT# No PCI Device Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF STATE IDSEL# ON ON ON ON LOW ON OFF OFF ON OFF OFF OFF ON OFF OFF OFF ICH7M SM Bus address BOARD ID Table(Page 25) ID BRD ID Ra R01 (EVT) R02 (DVT) R03 (PVT) R10A (MP) NC 100K 100K 100K Rb 8.2K 18K NC Vab 0V 0.25V 0.50V 3.3V Device Address Clock Generator (SLG8SP556VTR) 1101 001Xb DDR DIMMA 1010 000Xb 4 2006/08/18 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2007/8/18 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C D SCHEMATIC,MB A5141 Document Number Rev B 401690 Sheet Tuesday, March 10, 2009 E of 40 T7 (16) (16) (16) (16) (16) (16) (16) H_A20M# H_FERR# H_IGNNE# H_STPCLK# H_INTR H_NMI H_SMI# H_DEFER# (6) H_DRDY# (6) H_DBSY# (6) BR0# T20 H_BR0# IERR# INIT# F16 V16 H_IERR# H_INIT#_R LOCK# W20 H_LOCK# RESET# RS[0]# RS[1]# RS[2]# TRDY# D15 W18 Y17 U20 W19 H_RESET# H_RS#0 H_RS#1 H_RS#2 H_TRDY# AA17 V20 H_HIT# H_HITM# HIT# HITM# R201 56_0402_5% H_BR0# R27 330_0402_5% (6) R33 1K_0402_5% H_LOCK# (6) H_INIT# (16) Close to CPU H_RESET# (6) H_RS#[0 2] (6) H_HIT# H_HITM# BPM[0]# BPM[1]# BPM[2]# BPM[3]# PRDY# PREQ# TCK TDI TDO TMS TRST# BR1# K17 J18 H15 J15 K18 J16 M17 N16 M16 L17 K16 V15 PROCHOT# THRMDA THRMDC G17 E4 E5 H_PROCHOT#_R H_THERMDA H_THERMDC THERMTRIP# H17 H_THERMTRIP# (6) (6) U5 BCLK[0] BCLK[1] H_DSTBN#0 H_DSTBP#0 H_DINV#0 (6) H_D#[16 31] N280@ R202 22_0402_5% (6) (6) (6) H_PROCHOT# (37) Close to CPU CLK_CPU_BCLK CLK_CPU_BCLK# Y11 W10 Y12 AA14 AA11 W12 AA16 Y10 Y9 Y13 W15 AA13 Y16 W13 AA9 W9 Y14 Y15 W16 V9 D[0]# D[1]# D[2]# D[3]# D[4]# D[5]# D[6]# D[7]# D[8]# D[9]# D[10]# D[11]# D[12]# D[13]# D[14]# D[15]# DSTBN[0]# DSTBP[0]# DINV[0]# DP#0 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_DSTBN#1 H_DSTBP#1 H_DINV#1 H_DP#1 AA5 Y8 W3 U1 W7 W6 Y7 AA6 Y3 W2 V3 U2 T3 AA8 V2 W4 Y4 Y5 Y6 R4 D[16]# D[17]# D[18]# D[19]# D[20]# D[21]# D[22]# D[23]# D[24]# D[25]# D[26]# D[27]# D[28]# D[29]# D[30]# D[31]# DSTBN[1]# DSTBP[1]# DINV[1]# DP#1 A7 U5 V5 T17 R6 M6 N15 N6 P17 T6 J6 H5 G5 GTLREF ACLKPH DCLKPH BINIT# MISC EDM EXTBGREF FORCEPR# HFPLL MCERR# RSP# BSEL[0] BSEL[1] BSEL[2] T10 PAD CPU N280 PREQ# ITP_TCK ITP_TDI ITP_TDO ITP_TMS ITP_TRST# H_DSTBN#1 H_DSTBP#1 H_DINV#1 T13 PAD H_THERMTRIP# (6,16) +CPU_GTLREF V11 V12 (6) (6) (6) H_TRDY# (6) H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_DSTBN#0 H_DSTBP#0 H_DINV#0 H_DP#0 CLK_CPU_BCLK (12) CLK_CPU_BCLK# (12) R240 R239 @ @ 1K_0402_5% 1K_0402_5% ACLKPH DCLKPH +CPU_EXTBGREF C21 C1 A3 RSVD3 RSVD2 RSVD1 (12) (12) (12) CPU_BSEL0 CPU_BSEL1 CPU_BSEL2 CPU_BSEL0 CPU_BSEL1 CPU_BSEL2 R3 R2 P1 N1 M2 P2 J3 N3 G3 H2 N2 L2 M3 J2 H1 J1 K2 K3 L1 M4 D[48]# D[49]# D[50]# D[51]# D[52]# D[53]# D[54]# D[55]# D[56]# D[57]# D[58]# D[59]# D[60]# D[61]# D[62]# D[63]# DSTBN[3]# DSTBP[3]# DINV[3]# DP#3 C2 G2 F1 D3 B4 E1 A5 C3 A6 F2 C6 B6 B3 C4 C7 D2 E2 F3 C5 D4 COMP[0] COMP[1] COMP[2] COMP[3] DPRSTP# DPSLP# DPWR# PWRGOOD SLP# CORE_DET CMREF[1] H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_DSTBN#2 H_DSTBP#2 H_DINV#2 H_DP#2 PAD H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 H_DSTBN#3 H_DSTBP#3 H_DINV#3 H_DP#3 PAD COMP0 COMP1 COMP2 COMP3 T1 T2 F20 F21 D H_DSTBN#2 (6) H_DSTBP#2 (6) H_DINV#2 (6) T15 H_D#[48 63] (6) H_DSTBN#3 (6) H_DSTBP#3 (6) H_DINV#3 (6) T12 R57 R58 R208 R209 27.4_0402_1% 54.9_0402_1% 27.4_0402_1% 54.9_0402_1% 2 1 H_DPRSTP# H_DPSLP# H_DPWR# H_PWRGOOD H_CPUSLP# R18 R17 U4 V17 N18 A13 B7 (6) C H_DPRSTP# (16,37) H_DPSLP# (16) H_DPWR# (6) H_PWRGOOD (16) H_CPUSLP# (6) +CPU_CMREF AU80586GE025512_FCBGA437 N270@ www.manuals.clan.su Layout note: COMP0,2 connect with trace length shorter COMP1,3 connect with trace length shorter AU80586GE025512_FCBGA437 2 1K_0402_5% H_A20M# 1K_0402_5% H_IGNNE# C62 0.1U_0402_16V4Z 2 change BOM structure 11/14 1 R48 2K_0402_1% C342 1U_0402_6.3V4Z R238 2K_0402_1% C65 0.1U_0402_16V4Z @ @ B R51 1K_0402_1% +CPU_CMREF +VCCP R234 1K_0402_1% +CPU_EXTBGREF R47 1K_0402_1% +CPU_GTLREF Zo=27.4ohm +/-15%, make than 0.5" Zo=55ohm +/-15%, make than0.5" H_A#32 H_A#33 H_A#34 H_A#35 1 1K_0402_5% 1K_0402_5% 1K_0402_5% 1K_0402_5% +VCCP R28 R32 2 2 1 1 +VCCP R34 R30 R31 R29 +VCCP B R49 2K_0402_1% 2 +VCCP +VCCP D[32]# D[33]# D[34]# D[35]# D[36]# D[37]# D[38]# D[39]# D[40]# D[41]# D[42]# D[43]# D[44]# D[45]# D[46]# D[47]# DSTBN[2]# DSTBP[2]# DINV[2]# DP#2 DATA GRP NC1 NC2 NC3 NC4 NC5 NC6 NC7 H_DEFER# H_DRDY# H_DBSY# H_D#[32 47] U5B D6 G6 H6 K4 K5 M15 L16 T21 T19 Y18 H_D#[0 15] +VCCP A20M# FERR# IGNNE# STPCLK# LINT0 LINT1 SMI# DEFER# DRDY# DBSY# (6) (6) (6) U18 T16 J4 R16 T15 R15 U17 H_ADS# H_BNR# H_BPRI# H_A20M# H_FERR# H_IGNNE# H_STPCLK# H_INTR H_NMI H_SMI# PAD H_ADS# H_BNR# H_BPRI# CONTROL A[17]# A[18]# A[19]# A[20]# A[21]# A[22]# A[23]# A[24]# A[25]# A[26]# A[27]# A[28]# A[29]# A[30]# A[31]# A[32]# A[33]# A[34]# A[35]# ADSTB[1]# AP1 V19 Y19 U21 DATA GRP H_ADSTB#1 C19 F19 E21 A16 D19 C14 C18 C20 E20 D20 B18 C15 B16 B17 C16 A17 B14 B15 A14 B19 M18 ADDR GROUP (6) H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35 H_ADSTB#1 H_AP1 +VCCP ADS# BNR# BPRI# DATA GRP H_A#[17 31] THERM XDP/ITP SIGNALS (6) A[3]# A[4]# A[5]# A[6]# A[7]# A[8]# A[9]# A[10]# A[11]# A[12]# A[13]# A[14]# A[15]# A[16]# ADSTB[0]# AP0 REQ[0]# REQ[1]# REQ[2]# REQ[3]# REQ[4]# DATA GRP H_ADSTB#0 H_REQ#[0 4] (6) N270@ P21 H20 N20 R20 J19 N19 G20 M19 H21 L20 M20 K19 J20 L21 K20 D17 N21 J21 G19 P20 R19 ADDR GROUP H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_ADSTB#0 T5 H_AP0 PAD H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 D C H CLK U5A (6) (6) H_A#[3 16] NC (6) This shall place near CPU R200 R198 R206 R199 R205 1 1 56_0402_5% 56_0402_5% 2@ 56_0402_5% 56_0402_5% 68_0402_5% ITP_TMS ITP_TDI PREQ# ITP_TDO H_PROCHOT# Close to CPU pin within 500mils Zo=55ohm Close to CPU pin within 500mils Zo=55ohm Close to CPU pin within 500mils Zo=55ohm H_THERMDA, H_THERMDC routing together Trace width / Spacing = 10 / 10 mil Modify schematic by 10/21 56_0402_5% 56_0402_5% +3VS ITP_TCK ITP_TRST# 0.1U_0402_16V4Z R213 R218 C351 CPU THERMAL SENSOR C352 U17 VDD SMCLK EC_SMB_CK2 H_THERMDA DP SMDATA EC_SMB_DA2 H_THERMDC 2200P_0402_50V7K DN ALERT# THERM# GND EC_SMB_CK2 (25) EC_SMB_DA2 (25) R304 10K_0402_5% +3VS A A EMC1402-1-ACZL-TR_MSOP8 Address:100_1100 2006/08/18 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2007/8/18 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: SCHEMATIC,MB A5141 Rev B 401690 Sheet Tuesday, March 10, 2009 of 40 U5D B N5 N7 N9 N13 N17 P3 P4 P5 P6 P7 P9 P13 P15 P16 P18 P19 R1 R5 R7 R9 R13 R21 T4 T5 T7 T9 T10 T11 T12 T13 T18 U3 U6 U7 U15 U16 U19 V1 V4 V6 V7 V8 V13 V14 V18 V21 W1 W5 W8 W11 W14 W17 W21 Y1 Y2 Y20 Y21 AA2 AA3 AA4 AA7 AA10 AA12 AA15 AA18 AA19 AA20 VTT1 VTT2 VTT3 VTT4 VTT5 VTT6 VTT7 VTT8 VTT9 VTT10 VTT11 VTT12 VTT13 VTT14 VTT15 VTT16 VTT17 VTT18 VTT19 VTT20 VTT21 VTT22 VTT23 VTT24 VTT25 VTT26 VTT27 VTT28 VTT29 VTT30 VTT31 VTT32 C9 D9 E9 F8 F9 G8 G14 H8 H14 J8 J14 K8 K14 L8 L14 M8 M14 N8 N14 P8 P14 R8 R14 T8 T14 U8 U9 U10 U11 U12 U13 U14 VCCPC64 VCCPC63 VCCPC62 VCCPC61 F14 F13 E14 E13 +VCCP V10 A9 B9 VCCF VCCQ1 VCCQ2 +CPU_CORE A10 A11 A12 B10 B11 B12 C10 C11 C12 D10 D11 D12 E10 E11 E12 F10 F11 F12 G10 G11 G12 H10 H11 H12 J10 J11 J12 K10 K11 K12 L10 L11 L12 M10 M11 M12 N10 N11 N12 P10 P11 P12 R10 R11 R12 VCCP1 VCCP2 VCCP3 VCCP4 VCCP5 VCCP6 VCCP7 VCCP8 VCCP9 VCCP10 VCCP11 VCCP12 VCCP13 VCCP14 VCCP15 VCCP16 VCCP17 VCCP18 VCCP19 VCCP20 VCCP21 VCCP22 VCCP23 VCCP24 VCCP25 VCCP26 VCCP27 VCCP28 VCCP29 VCCP30 VCCP31 VCCP32 VCCP33 VCCP34 VCCP35 VCCP36 VCCP37 VCCP38 VCCP39 VCCP40 VCCP41 VCCP42 VCCP43 VCCP44 VCCP45 0.1U_0402_16V7K 1U_0402_6.3V6K C295 C307 C337 0.1U_0402_16V7K C341 + C57 1U_0402_6.3V6K 220U_B2_2.5VM_R35 D PLACE IN CAVITY C +1.5VS 130mA VCCA D7 +1.5VS VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6] F15 D16 E18 G15 G16 E17 G18 CPU_VID0 CPU_VID1 CPU_VID2 CPU_VID3 CPU_VID4 CPU_VID5 CPU_VID6 VCCSENSE C13 VCCSENSE VSSSENSE D13 VSSSENSE www.manuals.clan.su (37) (37) (37) (37) (37) (37) (37) C338 0.1U_0402_16V7K +CPU_CORE CPU_VID0 CPU_VID1 CPU_VID2 CPU_VID3 CPU_VID4 CPU_VID5 CPU_VID6 R221 100_0402_1% C VSS162 VSS161 VSS160 VSS159 VSS158 VSS157 VSS156 VSS155 VSS154 VSS153 VSS152 VSS151 VSS149 VSS148 VSS147 VSS146 VSS145 VSS144 VSS143 VSS142 VSS141 VSS140 VSS139 VSS138 VSS137 VSS136 VSS135 VSS134 VSS133 VSS132 VSS131 VSS130 VSS129 VSS128 VSS127 VSS126 VSS125 VSS124 VSS123 VSS122 VSS121 VSS120 VSS119 VSS118 VSS117 VSS116 VSS115 VSS114 VSS113 VSS112 VSS111 VSS110 VSS109 VSS108 VSS107 VSS106 VSS105 VSS104 VSS103 VSS102 VSS101 VSS100 VSS99 VSS98 VSS97 VSS96 VSS95 Length match within 25 mils The trace space mils, Zo=27.4ohm VCCSENSE (37) VSSSENSE (37) D +VCCP U5C VSS1 VSS2 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS41 VSS42 VSS45 VSS46 VSS48 VSS49 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 VSS81 VSS82 VSS83 VSS84 AU80586GE025512_FCBGA437 N270@ 100_0402_1% +CPU_CORE +CPU_CORE x 330uF(9mohm/2) PLACE IN CAVITY 1U_0402_6.3V6K C308 C309 C310 1U_0402_6.3V6K C311 C312 1U_0402_6.3V6K C313 C314 1U_0402_6.3V6K C320 C321 1U_0402_6.3V6K C322 C323 1U_0402_6.3V6K C324 C326 1U_0402_6.3V6K C327 C325 1U_0402_6.3V6K C315 1 + C51 + C331 330U_D2_2.5VY_R9M AU80586GE025512_FCBGA437 N270@ 1U_0402_6.3V6K C298 C299 10U_0805_10V4Z 1U_0402_6.3V6K 10U_0805_10V4Z A B R220 A2 A4 A8 A15 A18 A19 A20 B1 B2 B5 B8 B13 B20 B21 C8 C17 D1 D5 D8 D14 D18 D21 E3 E6 E7 E8 E15 E16 E19 F4 F5 F6 F7 F17 F18 G1 G4 G7 G9 G13 G21 H3 H4 H7 H9 H13 H16 H18 H19 J5 J7 J9 J13 J17 K1 K6 K7 K9 K13 K15 K21 L3 L4 L5 L6 L7 L9 L13 L15 L18 L19 M1 M5 M7 M9 M13 M21 N4 2 C300 10U_0805_10V4Z C301 10U_0805_10V4Z 1U_0402_6.3V6K C302 2 1U_0402_6.3V6K 10U_0805_10V4Z C46 2 10U_0805_10V4Z C304 10U_0805_10V4Z C303 C335 10U_0805_10V4Z 1U_0402_6.3V6K 10U_0805_10V4Z C47 2 10U_0805_10V4Z 1U_0402_6.3V6K C328 2 1U_0402_6.3V6K 2 330U_D2_2.5VY_R9M @ 1U_0402_6.3V6K 10U_0805_10V4Z C334 2 A 10U_0805_10V4Z PLACE IN CORRIDOR AND CLOSE TO CPU Compal Electronics, Inc Compal Secret Data Security Classification 2006/08/18 Issued Date Deciphered Date 2007/8/18 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: SCHEMATIC,MB A5141 Document Number Rev B 401690 Tuesday, March 10, 2009 Sheet of 40 H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_ADS# H_ADSTB#_0 H_ADSTB#_1 H_VREF0 H_BNR# H_BPRI# H_BREQ0# H_CPURST# H_VREF1 F10 C12 H16 E2 B9 C7 G8 B10 E1 H_ADS# H_ADSTB#0 H_ADSTB#1 +H_VREF H_BNR# H_BPRI# H_BR0# H_RESET# +H_VREF HCLKN HCLKP H_DBSY# H_DEFER# H_DINV#_0 H_DINV#_1 H_DINV#_2 H_DINV#_3 H_DPWR# H_DRDY# H_DSTBN#_0 H_DSTBN#_1 H_DSTBN#_2 H_DSTBN#_3 H_DSTBP#_0 H_DSTBP#_1 H_DSTBP#_2 H_DSTBP#_3 AA6 AA5 C10 C6 H5 J6 T9 U6 G7 E6 F3 M8 T1 AA3 F4 M7 T2 AB3 CLK_MCH_BCLK# CLK_MCH_BCLK H_DBSY# H_DEFER# H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3 H_DPWR# H_DRDY# H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3 H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3 H_HIT# H_HITM# H_LOCK# H_REQ#_0 H_REQ#_1 H_REQ#_2 H_REQ#_3 H_REQ#_4 H_RS#_0 H_RS#_1 H_RS#_2 H_SLPCPU# H_TRDY# C8 B4 C5 G9 E9 G12 B8 F12 A5 B6 G10 E8 E10 H_HIT# H_HITM# H_LOCK# H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 H_RS#0 H_RS#1 H_RS#2 H_CPUSLP# H_TRDY# U1B (17) (17) (17) (17) DMI_TXN0 DMI_TXN1 DMI_TXP0 DMI_TXP1 (17) (17) (17) (17) DMI_RXN0 DMI_RXN1 DMI_RXP0 DMI_RXP1 (11) DDR_CKE0 (11) DDR_CKE1 (11) DDR_CS0# (11) DDR_CS1# CLK_MCH_BCLK# (12) CLK_MCH_BCLK (12) H_DBSY# (4) H_DEFER# (4) H_DINV#0 (4) H_DINV#1 (4) H_DINV#2 (4) H_DINV#3 (4) H_DPWR# (4) H_DRDY# (4) (11) (11) +1.8V R232 1 R228 M_ODT0 M_ODT1 80.6_0402_1% 80.6_0402_1% +DIMM_VREF DMI_RXN_0 DMI_RXN_1 DMI_RXP_0 DMI_RXP_1 DMI_RXN0 DMI_RXN1 DMI_RXP0 DMI_RXP1 V28 V31 V29 V32 DMI_TXN_0 DMI_TXN_1 DMI_TXP_0 DMI_TXP_1 AF33 AG1 SM_CK_0 SM_CK_1 AJ1 AM30 SM_CK_2 SM_CK_3 AG33 AF1 SM_CK#_0 SM_CK#_1 AK1 AN30 SM_CK#_2 SM_CK#_3 DDR_CKE0 DDR_CKE1 AN21 AN22 AF26 AF25 SM_CKE_0 SM_CKE_1 SM_CKE_2 SM_CKE_3 DDR_CS0# DDR_CS1# AG14 AF12 AK14 AH12 SM_CS#_0 SM_CS#_1 SM_CS#_2 SM_CS#_3 AJ21 AF11 SM_OCDCOMP_0 SM_OCDCOMP_1 M_ODT0 M_ODT1 AE12 AF14 AJ14 AJ12 SM_ODT_0 SM_ODT_1 SM_ODT_2 SM_ODT_3 SMRCOMPN SMRCOMPP AN12 AN14 AA33 AE1 SM_RCOMPN SM_RCOMPP SM_VREF_0 SM_VREF_1 M_CLK_DDR#0 M_CLK_DDR#1 (11) M_CLK_DDR#0 (11) M_CLK_DDR#1 H_BNR# (4) H_BPRI# (4) H_BR0# (4) H_RESET# (4) Y29 Y32 Y28 Y31 M_CLK_DDR0 M_CLK_DDR1 (11) M_CLK_DDR0 (11) M_CLK_DDR1 H_ADS# (4) H_ADSTB#0 (4) H_ADSTB#1 (4) DMI_TXN0 DMI_TXN1 DMI_TXP0 DMI_TXP1 10uA Layout Note: +DIMM_VREF trace width and spacing is 20/20 CFG/RSVD F8 D12 C13 A8 E13 E12 J12 B13 A13 G13 A12 D14 F14 J13 E17 H15 G15 G14 A15 B18 B15 E14 H13 C14 A17 E15 H17 D17 G17 CFG_0 CFG_1 CFG_2 CFG_3 CFG_5 CFG_6 C18 E18 G20 G18 J20 J18 RESERVED1 RESERVED2 RESERVED7 RESERVED8 RESERVED9 K32 K31 C17 F18 A3 DMI H_A#_3 H_A#_4 H_A#_5 H_A#_6 H_A#_7 H_A#_8 H_A#_9 H_A#_10 H_A#_11 H_A#_12 H_A#_13 H_A#_14 H_A#_15 H_A#_16 H_A#_17 H_A#_18 H_A#_19 H_A#_20 H_A#_21 H_A#_22 H_A#_23 H_A#_24 H_A#_25 H_A#_26 H_A#_27 H_A#_28 H_A#_29 H_A#_30 H_A#_31 DDR2 MUXING H_D#_0 H_D#_1 H_D#_2 H_D#_3 H_D#_4 H_D#_5 H_D#_6 H_D#_7 H_D#_8 H_D#_9 H_D#_10 H_D#_11 H_D#_12 H_D#_13 H_D#_14 H_D#_15 H_D#_16 H_D#_17 H_D#_18 H_D#_19 H_D#_20 H_D#_21 H_D#_22 H_D#_23 H_D#_24 H_D#_25 H_D#_26 H_D#_27 H_D#_28 H_D#_29 H_D#_30 H_D#_31 H_D#_32 H_D#_33 H_D#_34 H_D#_35 H_D#_36 H_D#_37 H_D#_38 H_D#_39 H_D#_40 H_D#_41 H_D#_42 H_D#_43 H_D#_44 H_D#_45 H_D#_46 H_D#_47 H_D#_48 H_D#_49 H_D#_50 H_D#_51 H_D#_52 H_D#_53 H_D#_54 H_D#_55 H_D#_56 H_D#_57 H_D#_58 H_D#_59 H_D#_60 H_D#_61 H_D#_62 H_D#_63 PM C C4 F6 H9 H6 F7 E3 C2 C3 K9 F5 J7 K7 H8 E5 K8 J8 J2 J3 N1 M5 K5 J5 H3 J4 N3 M4 M3 N8 N6 K3 N9 M1 V8 V9 R6 T8 R2 N5 N2 R5 U7 R8 T4 T7 R3 T5 V6 V3 W2 W1 V2 W4 W7 W5 V5 AB4 AB8 W8 AA9 AA8 AB1 AB7 AA2 AB5 H_A#[3 31] (4) U1A H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 D PM_ICHSYNC# PM_BMBUSY# PM_EXTTS#_0 PM_EXTTS#_1 THRMTRIP# PWROK RSTIN# E31 G21 F26 H26 J15 AB29 W27 D_REFCLKN D_REFCLKP D_REFSSCLKN D_REFSSCLKP CLKREQ# A27 A26 J33 H33 J22 MCH_CLKSEL0 MCH_CLKSEL1 MCH_CLKSEL2 CFG3 @ PAD T32 CFG5 CFG6 R181 @ PAD T33 MCH_CLKSEL0 (12) MCH_CLKSEL1 (12) MCH_CLKSEL2 (12) D 2.2K_0402_5% MCH_ICH_SYNC# (15) PM_BMBUSY# (17) PM_EXTTS#0 PM_EXTTS#0 (11) PM_EXTTS#12 PM_DPRSLPVR (17,37) R203 0_0402_5% H_THERMTRIP# H_THERMTRIP# (4,16) ICH_POK ICH_POK (17,25) PLTRST_R# PLTRST# (15,17,19,24,25,27) R211 100_0402_5% C CLK_MCH_DREFCLK# (12) CLK_MCH_DREFCLK (12) MCH_SSCDREFCLK# (12) MCH_SSCDREFCLK (12) MCH_CLKREQ# (12) www.manuals.clan.su R6 54.9_0402_1% +VCCP R175 54.9_0402_1% C53 0.1U_0402_16V4Z H_D#[0 63] HOST (4) CLK H_XRCOMP H_XSCOMP +H_SWNG0 H_YRCOMP H_YSCOMP +H_SWNG1 R182 24.9_0402_1% R7 24.9_0402_1% B A10 A6 C15 J1 K1 H1 H_DSTBN#[0 3] (4) Calistoga-GSE_FCBGA998 H_DSTBP#[0 3] (4) H_XRCOMP H_XSCOMP H_XSWING H_YRCOMP H_YSCOMP H_YSWING Strap Pin Table H_HIT# (4) H_HITM# (4) H_LOCK# (4) CFG5 Low = DMI x * High = DMI x B H_REQ#[0 4] (4) H_RS#[0 2] (4) H_CPUSLP# (4) H_TRDY# (4) Calistoga-GSE_FCBGA998 +3VS Layout Note: H_XRCOMP / H_YRCOMP / H_VREF / H_SWNG0 / H_SWNG1 trace width and spacing is 10/20 PM_EXTTS#0 R187 @ R188 PM_EXTTS#1 +VCCP 10K_0402_5% 10K_0402_5% +VCCP R180 221_0402_1% 221_0402_1% R167 100_0402_1% A +H_SWNG1 0.1U_0402_16V4Z C251 R178 2 100_0402_1% 0.1U_0402_16V4Z C240 100_0402_1% C50 be placed