A B C D E Model Name : A5WAM File Name : LA-B981P m se fix co Compal Confidential 2 ro EA51_BM DIS M/B Schematics Document w w w Intel Bay Trail M + N15V-GL/N15V-GM 2014-05-12 REV:0.1 4 PCB@ DAX PCB 15Y LA-B981P REV0 MB Part Number DA60019D000 Description PCB 15Y LA-B981P REV0 MB Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2014/03/19 2015/03/18 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C D Cover Page A5WAM_Bay Trail M_LA‐B981P Sheet Monday, May 12, 2014 E of Rev 0.1 47 A B HDMI Conn C D E eDP Conn Nvidia N15V-GL with DDR3 x4 204pin DDR3L-SO-DIMM X1 page 15~21 P.23 PCIe 2.0 x 5GT/s P.22 port port 1 P.13 port 0/1 Memory BUS 204pin DDR3L-SO-DIMM X1 Dual Channel P.14 1.35V DDR3L 1066/1333 DDI x2 CRT Conn VGA x1 USB2.0 x4 P.24 PCIE 2.0 x1 LAN(GbE) / Card Reader RTL8411B PCIE 2.0 x1 FCBGA 1170 Pin port USB HUB GL850G P.28 USB 3.0 Conn P.28 SOC P.25,26 port USB3.0 x1 port RJ45 Conn VALLEYVIEW-M port port HD Camera Conn Touch Panel Conn P.22 P.22 HUB port1 MINI CARD WLAN/BT port P.26 Card Reader in 1(SD) SATA 2.0 x2 P.27 port HD Audio P.27 HDA Codec page 05~12 port LPC BUS ALC283 P.31 SPI 3 EC ENE KB9022 SATA ODD Conn RTC CKT P.08 Power Circuit DC/DC P.33~P.44 LED/Power On/Off P.30 Speaker Combo Jack P.31 Int MIC P.31 P.31 P.08 P.29 SATA HDD Conn P.30 DC/DC Interface CKT P.32 SPI ROM 1.8V (8MB) P.30 Sub Board Touch Pad PS2/I2C LS_B161P PWR Int.KBD LS_B162P USB HUB port2,3 Fan Control Issued Date Compal Electronics, Inc Compal Secret Data Security Classification P.27 2014/03/19 2015/03/18 Deciphered Date Title Block Diagrams THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C D A5WAM_Bay Trail M_LA‐B981P Sheet Monday, May 12, 2014 E of 47 Rev 0.1 A B C Voltage Rails E Board ID / SKU ID Table for AD channel Power Plane D Description S0 S3 S4/S5 VIN 19V Adapter power supply ON ON ON BATT+ 12V Battery power supply ON ON ON B+ AC or battery power rail for power circuit (19V/12V) ON ON ON +RTCVCC RTC Battery Power ON ON ON +1.0VALW +1.0v Always power rail ON ON ON +1.8VALW +1.8v Always power rail ON ON ON +3VALW +3.3v Always power rail ON ON ON +5VALW +5.0v Always power rail ON ON ON +1.35V +1.35V power rail for DDR3L ON ON OFF +3V_PTP +3.3V power rail for PTP ON ON OFF +SOC_VCC Core voltage for SOC ON OFF OFF +SOC_VNN GFX voltage for SOC ON OFF OFF +0.675VS +0.675V power rail for DDR3L Terminator ON OFF OFF +1.0VS +1.0v system power rail ON OFF OFF +1.05VS +1.05v system power rail ON OFF OFF +1.35VS +1.35v system power rail ON OFF OFF +1.5VS +1.5v system power rail ON OFF OFF +1.8VS +1.8v system power rail ON OFF OFF +3VS +3.3v system power rail ON OFF OFF +5VS +5.0v system power rail ON OFF OFF 43 Level Description +3VSDGPU +3.3V dGPU power rail ON** OFF OFF 4319URBOL01 SMT MB AB212 A5WAM GM2G N3530 HDMI N3530@/9022@/DBG@/EMC@/PCB@/1DMIC@/NTPM@/VGA@/VGM@/X762G@ +VGA_CORE Core voltage for dGPU ON** OFF OFF 4319URBOL02 SMT MB AB212 A5WAM GL1G N2930 HDMI +1.5VSDGPU +1.5V dGPU power rail ON** OFF OFF 4319URBOL03 SMT MB AB212 A5WAM GL1G N2830 HDMI N2930@/9022@/DBG@/EMC@/PCB@/1DMIC@/NTPM@/VGA@/VGL@/X761G@ N2830@/9022@/DBG@/EMC@/PCB@/1DMIC@/NTPM@/VGA@/VGL@/X761G@ +1.05VSDGPU +1.05V dGPU power rail ON** OFF OFF 4319URBOL04 SMT MB AB212 A5WAM GL1G N3530 HDMI N3530@/9022@/DBG@/EMC@/PCB@/1DMIC@/NTPM@/VGA@/VGM@/X761G@ Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF 4319URBOL05 SMT MB AB212 A5WAM GM2G N2930 HDMI Note : ON** dGPU optimus on 4319URBOL06 SMT MB AB212 A5WAM GM2G N2830 HDMI N2930@/9022@/DBG@/EMC@/PCB@/1DMIC@/NTPM@/VGA@/VGL@/X762G@ N2830@/9022@/DBG@/EMC@/PCB@/1DMIC@/NTPM@/VGA@/VGL@/X762G@ BOARD ID Table_LA-B212 Board ID 10 11 43 level BOM table BOM Structure BOM Option Table +1.8VS 2.2K SOC PCU_SMB_CLK BG12 PCU_SMB_DATA BSS138 BSS138 2.2K 2.2K SCL1 SDA1 77 EC_SMB_CK1 78 EC_SMB_DA1 +3VALW 100 ohm 100 ohm BATTERY CONN 2.2K 2.2K KBC SCL2 79 EC_SMB_CK2 SDA2 80 EC_SMB_DA2 +3VS Item X76 1G VRAM X76 2G VRAM 2.2K SOC_I2C2_DATA BJ25 SOC_I2C2_CLK 202 DIMMA 202 SOC 30 32 BH28 SMBUS Address [A2h] 2.2K 2.2K WLAN BG28 I2CS_SDA Issued Date 2014/03/19 B SOC_I2C5_CLK Touch Panel I2C5_SCL_PNL BSS138 Compal Electronics, Inc 2015/03/18 Deciphered Date Title Notes List THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC C +TS_PWR BSS138 Date: A 2.2K I2C5_SDA_PNL Compal Secret Data Security Classification VGA Touch Pad 2.2K +1.8VS SOC_I2C5_DATA +3VSDGPU_AON I2CS_SCL 2N7002DW +3V_PTP I2C2_SCL_TP BSS138 2.2K DIMMB 2.2K BSS138 200 2.2K +1.8VS 2.2K SMBUS Address [A0h] I2C2_SDA_TP 200 KB9022 BOM Structure X761G@ X762G@ 1GHYN@ 1GFFR@ 1GSAM@ 2GAFR@ 2GSAM@ 2GMIC@ 2.2K Charger BG25 BOM Option Table Item BOM Structure Unpop @ Connector CONN@ EMC requirement EMC@ EMC requirement depop @EMC@ KB9012 9012@ KB9022 9022@ Touch Screen I2C TSI@ KB BL BL@ DMIC*1 1DMIC@ DMIC*2 2DMIC@ TPM TPM@ NTPM NTPM@ Debug SW DBG@ dGPU VGA@ N15V‐GL SKU VGL@ N15V‐GM SKU VGM@ 2.2K BH10 PCB Revision EVT_LA-B212PR01 PVT_LA-B981PR01 D A5WAM_Bay Trail M_LA‐B981P Sheet Monday, May 12, 2014 E of 47 Rev 0.1 A B C 12000mA VR_ON SPOK ISL95833HRTZ-T (PU801) 14000mA SY8208DQNC (PU601) 325mA RT8207MZQW (PU501) 5250mA D E +SOC_VNN +SOC_VCC +1.0VALWP SUSP ME4856-G (U60) 2750mA +1.0VS ADAPTER SYSON B+ CHARGER EC_ON SY8208BQNC (PU401) +1.35VP +3VALWP BATTERY SUSP# +0.675VSP SUSP# TPS22966DPUR (U59) 420mA SUSP# SY8003DFC_DFN8 (PU602) 958mA SUSP# APL5930KAI-TRG (PU701) 1000mA SPOK APL5930KAI-TRG (PU702) 110mA SUSP# TPS22966DPUR (U11) LAN_PWR_EN EC_ON SY8208BQNC (PU402) +5VALWP SUSP# +1.5VSP VGA_PWROK +1.05VSP +1.05VS +1.8VALWP TPS22966DPUR (U59) +3VS G5243AT11U (U67) TPS22966DPUR (U11) +1.35VS JP8 +1.05VSDGPU +1.8VS +3VS_WLAN ENVDD G5243AT11U (U8) +LCDVDD DGPU_PWR_EN G5243T11U (U12) +3VSDGPU_AON +3V_LAN 958mA +5VS J1 +VDDA ohm ohm USB_PWR_EN# AO4478L (U40) SY6288D10CAC (U25) +5VS_HDD +5VS_ODD +USB3_VCCA DGPU_PWR_EN VGA_PWROK RT8813AGQW (PU1201) +VGA_CORE TPS51212DSCR (PU1001) +1.5VSDGPU 4 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2014/03/19 2015/03/18 Deciphered Date Title Power Rail THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C D A5WAM_Bay Trail M_LA‐B981P Sheet Monday, May 12, 2014 E of Rev 0.1 47 DDR_A_D[0 63] 13 DDR_A_DQS[0 7] DDR_A_DQS#[0 7] DDR_B_D[0 63] 13 DDR_B_DQS[0 7] 13 DDR_A_MA[0 15] D 13 C DDR_A_DM[0 7] 13 13 13 DDR_A_RAS# DDR_A_CAS# DDR_A_WE# 13 13 13 DDR_A_BS0 DDR_A_BS1 DDR_A_BS2 13 DDR_A_CS0# 13 DDR_A_CS2# 13 DDR_A_CKE0 13 DDR_A_CKE2 13 DDR_A_ODT0 13 DDR_A_ODT2 13 13 DDR_A_CLK0 DDR_A_CLK0# 13 13 DDR_A_CLK2 DDR_A_CLK2# 13 DDR_A_RST# DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15 K45 H47 L41 H44 H50 G53 H49 D50 G52 E52 K48 E51 F47 J51 B49 B50 DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7 G36 B36 F38 B42 P51 V42 Y50 Y52 M45 M44 H51 K47 K44 D52 P44 P45 C47 D48 F44 E46 T41 P42 M50 M48 P50 P48 P41 AF44 +DDR_SOC_VREF 100K_0402_5% 100K_0402_5% R960 R961 DDR_TERMN0 DDR_TERMN1 AF42 AH42 AD42 AB42 DDR_PWROK DDR_CORE_PWROK 23.2_0402_1% 29.4_0402_1% 162_0402_1% R962 R963 R964 DDR_RCOMP0 DDR_RCOMP1 DDR_RCOMP2 Follow CRB v2.0 AD44 AF45 AD45 AF40 AF41 AD40 AD41 DDR_CORE_PWROK EMC@ C1159 0.047U_0402_16V4Z DRAM0_MA_0 DRAM0_MA_1 DRAM0_MA_2 DRAM0_MA_3 DRAM0_MA_4 DRAM0_MA_5 DRAM0_MA_6 DRAM0_MA_7 DRAM0_MA_8 DRAM0_MA_9 DRAM0_MA_10 DRAM0_MA_11 DRAM0_MA_12 DRAM0_MA_13 DRAM0_MA_14 DRAM0_MA_15 DRAM0_DQ_0 DRAM0_DQ_1 DRAM0_DQ_2 DRAM0_DQ_3 DRAM0_DQ_4 DRAM0_DQ_5 DRAM0_DQ_6 DRAM0_DQ_7 DRAM0_DQ_8 DRAM0_DQ_9 DRAM0_DQ_10 DRAM0_DQ_11 DRAM0_DQ_12 DRAM0_DQ_13 DRAM0_DQ_14 DRAM0_DQ_15 DRAM0_DQ_16 DRAM0_DQ_17 DRAM0_DQ_18 DRAM0_DQ_19 DRAM0_DQ_20 DRAM0_DQ_21 DRAM0_DQ_22 DRAM0_DQ_23 DRAM0_DQ_24 DRAM0_DQ_25 DRAM0_DQ_26 DRAM0_DQ_27 DRAM0_DQ_28 DRAM0_DQ_29 DRAM0_DQ_30 DRAM0_DQ_31 DRAM0_DQ_32 DRAM0_DQ_33 DRAM0_DQ_34 DRAM0_DQ_35 DRAM0_DQ_36 DRAM0_DQ_37 DRAM0_DQ_38 DRAM0_DQ_39 DRAM0_DQ_40 DRAM0_DQ_41 DRAM0_DQ_42 DRAM0_DQ_43 DRAM0_DQ_44 DRAM0_DQ_45 DRAM0_DQ_46 DRAM0_DQ_47 DRAM0_DQ_48 DRAM0_DQ_49 DRAM0_DQ_50 DRAM0_DQ_51 DRAM0_DQ_52 DRAM0_DQ_53 DRAM0_DQ_54 DRAM0_DQ_55 DRAM0_DQ_56 DRAM0_DQ_57 DRAM0_DQ_58 DRAM0_DQ_59 DRAM0_DQ_60 DRAM0_DQ_61 DRAM0_DQ_62 DRAM0_DQ_63 DRAM0_DM_0 DRAM0_DM_1 DRAM0_DM_2 DRAM0_DM_3 DRAM0_DM_4 DRAM0_DM_5 DRAM0_DM_6 DRAM0_DM_7 DRAM0_RAS# DRAM0_CAS# DRAM0_WE# DRAM0_BS_0 DRAM0_BS_1 DRAM0_BS_2 DRAM0_CS_0# DRAM0_CS_2# DRAM0_CKE_0 RESERVED_D48 DRAM0_CKE_2 RESERVED_E46 DRAM0_ODT_0 DRAM0_ODT_2 DRAM0_CKP_0 DRAM0_CKN_0 DRAM0_CKP_2 DRAM0_CKN_2 DRAM0_DRAMRST# 0.675V DRAM_VREF ICLK_DRAM_TERMN_AF42 ICLK_DRAM_TERMN_AH42 DRAM0_DQSP_0 DRAM0_DQSN_0 DRAM0_DQSP_1 DRAM0_DQSN_1 DRAM0_DQSP_2 DRAM0_DQSN_2 DRAM0_DQSP_3 DRAM0_DQSN_3 DRAM0_DQSP_4 DRAM0_DQSN_4 DRAM0_DQSP_5 DRAM0_DQSN_5 DRAM0_DQSP_6 DRAM0_DQSN_6 DRAM0_DQSP_7 DRAM0_DQSN_7 DRAM_VDD_S4_PWROK DRAM_CORE_PWROK DRAM_RCOMP_0 DRAM_RCOMP_1 DRAM_RCOMP_2 RESERVED_AF40 RESERVED_AF41 RESERVED_AD40 RESERVED_AD41 M36 J36 P40 M40 P36 N36 K40 K42 B32 C32 C36 A37 C33 A33 C37 B38 F36 G38 F42 J42 G40 C38 G44 D42 A41 C41 A45 B46 C40 B40 B48 B47 K52 K51 T52 T51 L51 L53 R51 R53 T47 T45 Y40 V41 T48 T50 Y42 AB40 V45 V47 AD48 AD50 V48 V50 AB44 Y45 V52 W51 AC53 AC51 W53 Y51 AD52 AD51 DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63 J38 K38 C35 B34 D40 F40 B44 C43 N53 M52 T42 T44 Y47 Y48 AB52 AA51 DDR_A_DQS0 DDR_A_DQS#0 DDR_A_DQS1 DDR_A_DQS#1 DDR_A_DQS2 DDR_A_DQS#2 DDR_A_DQS3 DDR_A_DQS#3 DDR_A_DQS4 DDR_A_DQS#4 DDR_A_DQS5 DDR_A_DQS#5 DDR_A_DQS6 DDR_A_DQS#6 DDR_A_DQS7 DDR_A_DQS#7 14 14 DDR_B_MA[0 15] 14 14 14 DDR_B_DM0 DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7 AV45 AV44 BB51 DDR_B_RAS# DDR_B_CAS# DDR_B_WE# 14 14 14 DDR_B_BS0 DDR_B_BS1 DDR_B_BS2 14 DDR_B_CS0# 14 DDR_B_CS2# 14 DDR_B_CKE0 14 DDR_B_CKE2 BD38 BH36 BC36 BH42 AT51 AM42 AK50 AK52 AY47 AY44 BF52 AT44 AT45 BG47 BE46 BD44 BF48 14 DDR_B_ODT0 14 DDR_B_ODT2 14 14 DDR_B_CLK0 DDR_B_CLK0# 14 14 DDR_B_CLK2 DDR_B_CLK2# 14 DDR_B_RST# AP41 AT42 AV50 AV48 AT50 AT48 AT41 DRAM1_MA_0 DRAM1_MA_1 DRAM1_MA_2 DRAM1_MA_3 DRAM1_MA_4 DRAM1_MA_5 DRAM1_MA_6 DRAM1_MA_7 DRAM1_MA_8 DRAM1_MA_9 DRAM1_MA_10 DRAM1_MA_11 DRAM1_MA_12 DRAM1_MA_13 DRAM1_MA_14 DRAM1_MA_15 DRAM1_RAS# DRAM1_CAS# DRAM1_WE# DRAM1_BS_0 DRAM1_BS_1 DRAM1_BS_2 DRAM1_CS_0# DRAM1_CS_2# DRAM1_CKE_0 RESERVED_BE46 DRAM1_CKE_2 RESERVED_BF48 DRAM1_ODT_0 DRAM1_ODT_2 DRAM1_CKP_0 DRAM1_CKN_0 DRAM1_CKP_2 DRAM1_CKN_2 DRAM1_DRAMRST# DRAM1_DQSP_0 DRAM1_DQSN_0 DRAM1_DQSP_1 DRAM1_DQSN_1 DRAM1_DQSP_2 DRAM1_DQSN_2 DRAM1_DQSP_3 DRAM1_DQSN_3 DRAM1_DQSP_4 DRAM1_DQSN_4 DRAM1_DQSP_5 DRAM1_DQSN_5 DRAM1_DQSP_6 DRAM1_DQSN_6 DRAM1_DQSP_7 DRAM1_DQSN_7 14 BG38 BC40 BA42 BD42 BC38 BD36 BF42 BC44 BH32 BG32 BG36 BJ37 BG33 BJ33 BG37 BH38 AU36 AT36 AV40 AT40 BA36 AV36 AY42 AY40 BJ41 BG41 BJ45 BH46 BG40 BH40 BH48 BH47 AY52 AY51 AP52 AP51 AW51 AW53 AR51 AR53 AP47 AP45 AK40 AM41 AP48 AP50 AK42 AH40 AM45 AM47 AF48 AF50 AM48 AM50 AH44 AK45 AM52 AL51 AG53 AG51 AL53 AK51 AF52 AF51 DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63 BF40 BD40 BG35 BH34 BA38 AY38 BH44 BG43 AU53 AV52 AP42 AP44 AK47 AK48 AH52 AJ51 DDR_B_DQS0 DDR_B_DQS#0 DDR_B_DQS1 DDR_B_DQS#1 DDR_B_DQS2 DDR_B_DQS#2 DDR_B_DQS3 DDR_B_DQS#3 DDR_B_DQS4 DDR_B_DQS#4 DDR_B_DQS5 DDR_B_DQS#5 DDR_B_DQS6 DDR_B_DQS#6 DDR_B_DQS7 DDR_B_DQS#7 D C B OF 13 FH8065301546401_FCBGA131170 B0@ Close To SOC Pin +DDR_SOC_VREF R965 4.7K_0402_1% USOC1 N3520@ DRAM1_DQ_0 DRAM1_DQ_1 DRAM1_DQ_2 DRAM1_DQ_3 DRAM1_DQ_4 DRAM1_DQ_5 DRAM1_DQ_6 DRAM1_DQ_7 DRAM1_DQ_8 DRAM1_DQ_9 DRAM1_DQ_10 DRAM1_DQ_11 DRAM1_DQ_12 DRAM1_DQ_13 DRAM1_DQ_14 DRAM1_DQ_15 DRAM1_DQ_16 DRAM1_DQ_17 DRAM1_DQ_18 DRAM1_DQ_19 DRAM1_DQ_20 DRAM1_DQ_21 DRAM1_DQ_22 DRAM1_DQ_23 DRAM1_DQ_24 DRAM1_DQ_25 DRAM1_DQ_26 DRAM1_DQ_27 DRAM1_DQ_28 DRAM1_DQ_29 DRAM1_DQ_30 DRAM1_DQ_31 DRAM1_DQ_32 DRAM1_DQ_33 DRAM1_DQ_34 DRAM1_DQ_35 DRAM1_DQ_36 DRAM1_DQ_37 DRAM1_DQ_38 DRAM1_DQ_39 DRAM1_DQ_40 DRAM1_DQ_41 DRAM1_DQ_42 DRAM1_DQ_43 DRAM1_DQ_44 DRAM1_DQ_45 DRAM1_DQ_46 DRAM1_DQ_47 DRAM1_DQ_48 DRAM1_DQ_49 DRAM1_DQ_50 DRAM1_DQ_51 DRAM1_DQ_52 DRAM1_DQ_53 DRAM1_DQ_54 DRAM1_DQ_55 DRAM1_DQ_56 DRAM1_DQ_57 DRAM1_DQ_58 DRAM1_DQ_59 DRAM1_DQ_60 DRAM1_DQ_61 DRAM1_DQ_62 DRAM1_DQ_63 DRAM1_DM_0 DRAM1_DM_1 DRAM1_DM_2 DRAM1_DM_3 DRAM1_DM_4 DRAM1_DM_5 DRAM1_DM_6 DRAM1_DM_7 OF 13 FH8065301546401_FCBGA131170 B0@ USOC1 N2920@ AY45 DDR_B_MA0 BB47 DDR_B_MA1 DDR_B_MA2 AW41 BB44 DDR_B_MA3 BB50 DDR_B_MA4 BC53 DDR_B_MA5 BB49 DDR_B_MA6 BF50 DDR_B_MA7 BC52 DDR_B_MA8 BE52 DDR_B_MA9 AY48 DDR_B_MA10 DDR_B_MA11 BE51 DDR_B_MA12 BD47 DDR_B_MA13 BA51 DDR_B_MA14 BH49 DDR_B_MA15 BH50 DDR_B_DM[0 7] +1.35V_L USOC1 N2820@ 14 USOC1B B 37 14 DDR_B_DQS#[0 7] USOC1A 13 R966 4.7K_0402_1% C1132 1U_0402_16V7K A A S IC FH8065301616602 QFW4 B3 2.13G ABO! SA00007EK80 USOC1 N2830@ S IC FH8065301616203 SR1SF B3 1.86G ABO! SA00007E840 USOC1 N2930@ S IC FH8065301616103 SR1SE B3 2.17G ABO! SA00007E970 USOC1 N3530@ Issued Date S IC FH8065301729602 SR1W4 C0 2.16G ABO! SA00007QRD0 S IC FH8065301729501 SR1W3 C0 1.83G ABO! SA00007RVB0 S IC FH8065301728501 SR1W2 C0 2.16G FCBGA 1170 SA00007QQB0 Compal Electronics, Inc Compal Secret Data Security Classification 2014/03/19 2015/03/18 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: VLV-M SOC Memory DDR3L A5WAM_Bay Trail M_LA‐B981P Sheet Monday, May 12, 2014 of 47 Rev 0.1 D D USOC1C C26 C28 B28 C27 B26 R968 DDI0_RCOMPP 402_0402_1% DDI0_RCOMPN Follow CRB v2.0 0ohm till to GND C AK12 AK13 AM14 AM13 AM3 AM2 DDI1_AUXP DDI1_AUXN DDI0_HPD 1.8V 1.8V DDI1_HPD DDI0_DDCDATA DDI0_DDCCLK 1.8V 1.8V 1.8V 1.8V DDI1_DDCDATA DDI1_DDCCLK 1.8V 1.8V 1.8V DDI1_VDDEN DDI1_BKLTEN DDI1_BKLTCTL DDI0_VDDEN DDI0_BKLTEN DDI0_BKLTCTL VSS_AH3 VSS_AH2 DDI0_RCOMP_P DDI0_RCOMP_N RESERVED_AM14 RESERVED_AM13 VSS_AM3 VSS_AM2 RESERVED_AH14 RESERVED_AH13 RESERVED_AF14 RESERVED_AF13 VGA_RED VGA_BLUE VGA_GREEN VGA_IREF VGA_IRTN +1.8VS @ R970 10K_0402_5% B @ T186 GPIO_NC12 RESERVED_T2 RESERVED_T3 RESERVED_AB3 RESERVED_AB2 RESERVED_Y3 RESERVED_Y2 RESERVED_W3 RESERVED_W1 RESERVED_V2 RESERVED_V3 RESERVED_R3 RESERVED_R1 RESERVED_AD6 RESERVED_AD4 RESERVED_AB9 RESERVED_AB7 RESERVED_Y4 RESERVED_Y6 RESERVED_V4 RESERVED_V6 GPIO_S0_NC_13 GPIO_S0_NC14 RESERVED_AB14 GPIO_S0_NC_12 RESERVED_C30 VGA_HSYNC VGA_VSYNC 3.3V 3.3V VGA_DDCCLK VGA_DDCDATA RESERVED_T7 RESERVED_T9 RESERVED_AB13 RESERVED_AB12 RESERVED_Y12 RESERVED_Y13 RESERVED_V10 RESERVED_V9 RESERVED_T12 RESERVED_T10 RESERVED_V14 RESERVED_V13 RESERVED_T14 RESERVED_T13 RESERVED_T6 RESERVED_T4 RESERVED_P14 GPIO_S0_NC_15 GPIO_S0_NC_16 GPIO_S0_NC_17 GPIO_S0_NC_18 GPIO_S0_NC_19 GPIO_S0_NC_20 GPIO_S0_NC_21 GPIO_S0_NC_22 GPIO_S0_NC_23 GPIO_S0_NC_24 GPIO_S0_NC_25 GPIO_S0_NC_26 @ T187 R971 10K_0402_5% GPIO_NC13 GPIO_NC14 T2 T3 AB3 AB2 Y3 Y2 W3 W1 V2 V3 R3 R1 AD6 AD4 AB9 AB7 Y4 Y6 V4 V6 A29 C29 AB14 B30 C30 3.3V 3.3V Follow CRB v2.0 OF 10 AG3 AG1 AF3 AF2 AD3 AD2 AC3 AC1 EDP_TXP0 EDP_TXN0 EDP_TXP1 EDP_TXN1 eDP Panel AK3 AK2 K30 P30 DDI1_ENABLE R967 G30 EDP_AUXP EDP_AUXN 22 22 EDP_HPD# 22 2.2K_0402_5% +1.8VS N30 DDI1_ENVDD J30 DDI1_ENBKL M30 DDI1_PWM AH3 AH2 Follow CRB v2.0 0ohm till to GND AH14 AH13 AF14 AF13 BA3 AY2 BA1 AW1 AY3 C CRT_R CRT_B CRT_G CRT_IREF R969 CRT_R CRT_B CRT_G 357_0402_1% BD2 CRT_HSYNC BF2 CRT_VSYNC T7 T9 AB13 AB12 Y12 Y13 V10 V9 T12 T10 V14 V13 T14 T13 T6 T4 P14 F34 M32 D28 J28 K34 D34 F32 F28 K28 J34 N32 D32 24 24 24 CRT_HSYNC CRT_VSYNC BC1 CRT_DDC_CLK BC2 CRT_DDC_DATA FH8065301546401_FCBGA131170 24 24 CRT CRT_R CRT_G CRT_B B DDI1_ENBKL U61 NC A +3VS 9012@ ENBKL 4.7K_0402_5% R1159 NC Y A ENVDD 22 RP45 U64 Y A INVT_PWM_SOC A NL17SZ07DFT2G_SC70-5 SA00004BV00 Compal Electronics, Inc 2015/03/18 Deciphered Date Title Date: 3 100K_0804_8P4R_5% 22 VLV-M SOC Display THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC P DDI1_ENBKL DDI1_ENVDD DDI1_PWM Compal Secret Data 2014/03/19 NL17SZ07DFT2G_SC70-5 SA00004BV00 NC 2 INVT_PWM_SOC 4.7K_0402_5% R1161 G 1 ENVDD 4.7K_0402_5% R1160 U62 +1.8VALW PVT modify Security Classification 29 RS@ 0_0402_5% DDI1_ENVDD DDI1_PWM ENBKL NL17SZ07DFT2G_SC70-5 SA00004BV00 9012@ +1.8VALW B0@ Straps Pin:MDSI_DDCDATA Y R1142 A RP43 150_0804_8P4R_1% +1.8VS eDP PVT modify Issued Date CRT 24 24 CRT_DDC_CLK CRT_DDC_DATA GPIO_S0_NC[13]: Multiplexed with Hardware 22 22 22 22 HDMI_DDCDATA HDMI_DDCCLK 1.0V 1.0V DDI0_AUXP DDI0_AUXN DDI1_TXP_0 DDI1_TXN_0 DDI1_TXP_1 DDI1_TXN_1 DDI1_TXP_2 DDI1_TXN_2 DDI1_TXP_3 DDI1_TXN_3 P HDMI_HPD# 23 23 1.0V G D27 23 1.0V AL3 AL1 DDI0_TXP_0 DDI0_TXN_0 DDI0_TXP_1 DDI0_TXN_1 DDI0_TXP_2 DDI0_TXN_2 DDI0_TXP_3 DDI0_TXN_3 P HDMI AV3 AV2 AT2 AT3 AR3 AR1 AP3 AP2 HDMI_TX2+ HDMI_TX2HDMI_TX1+ HDMI_TX1HDMI_TX0+ HDMI_TX0HDMI_CLK+ HDMI_CLK- G 23 23 23 23 23 23 23 23 A5WAM_Bay Trail M_LA‐B981P Sheet Monday, May 12, 2014 of 47 Rev 0.1 Follow ACER 2014 X86 HSIO DG V1.03 D D USOC1D HDD ODD 27 27 SATA_PTX_DRX_P0 SATA_PTX_DRX_N0 27 27 SATA_PRX_DTX_P0 SATA_PRX_DTX_N0 27 27 SATA_PTX_DRX_P1 SATA_PTX_DRX_N1 27 27 SATA_PRX_DTX_P1 SATA_PRX_DTX_N1 BF6 BG7 AU16 AV16 BD10 BF10 AY16 BA16 Follow CRB V2.0 0ohm till to GND SOC_SCI# @ T188 C SOC_SCI# DEVSLP_SOC R972 SATA_RCOMPP 402_0402_1% SATA_RCOMPN BB10 BC10 BA12 AY14 AY12 AU18 AT18 AT22 AV20 AU22 AV22 AT20 AY24 AU26 AT26 AU20 AV26 BA24 AY18 BA18 AY20 BD20 BA20 BD18 BC18 AY26 AT28 BD26 AU28 BA26 BC24 AV28 BF22 BD22 B BF26 SATA_TXP_0 SATA_TXN_0 PCIE_TXP_0 PCIE_TXN_0 SATA_RXP_0 SATA_RXN_0 PCIE_RXP_0 PCIE_RXN_0 SATA_TXP_1 SATA_TXN_1 PCIE_TXP_1 PCIE_TXN_1 SATA_RXP_1 SATA_RXN_1 PCIE_RXP_1 PCIE_RXN_1 VSS_BB10 VSS_BC10 PCIE_TXP_2 PCIE_TXN_2 SATA_GP0 / GPIO_S0_SC_0 SATA_GP1 / SATA_DEVSLP_0 / GPIO_S0_SC_1 SATA_LED# / GPIO_S0_SC_2 PCIE_RXP_2 PCIE_RXN_2 PCIE_TXP_3 PCIE_TXN_3 SATA_RCOMP_P SATA_RCOMP_N PCIE_RXP_3 PCIE_RXN_3 MMC1_CLK / GPIO_S0_SC_16 VSS_BB7 VSS_BB5 MMC1_D0 / GPIO_S0_SC_17 MMC1_D1 / GPIO_S0_SC_18 MMC1_D2 / GPIO_S0_SC_19 MMC1_D3 / GPIO_S0_SC_20 MMC1_D4 / GPIO_S0_SC_21 MMC1_D5 / GPIO_S0_SC_22 MMC1_D6 / GPIO_S0_SC_23 MMC1_D7 / GPIO_S0_SC_24 PCIE_CLKREQ_0# / GPIO_S0_SC_3 PCIE_CLKREQ_1# / GPIO_S0_SC_4 PCIE_CLKREQ_2# / GPIO_S0_SC_5 PCIE_CLKREQ_3# / GPIO_S0_SC_6 SD3_WP / GPIO_S0_SC_7 MMC1_CMD / GPIO_S0_SC_25 MMC1_RST# / SATA_DEVSLP_0 / GPIO_S0_SC_26 PCIE_RCOMP_P PCIE_RCOMP_N RESERVED_BB4 RESERVED_BB3 MMC1_RCOMP SD2_CLK / GPIO_S0_SC_27 SD2_D0 / GPIO_S0_SC_28 SD2_D1 / GPIO_S0_SC_29 SD2_D2 / GPIO_S0_SC_30 SD2_D3_CD# / GPIO_S0_SC_31 SD2_CMD / GPIO_S0_SC_32 RESERVED_AV10 RESERVED_AV9 HDA_LPE_RCOMP HDA_RST# / LPE_I2S0_CLK / GPIO_S0_SC_8 HDA_SYNC / LPE_I2S0_FRM / GPIO_S0_SC_9 HDA_CLK / LPE_I2S0_DATAOUT / GPIO_S0_SC_10 HDA_SDO / LPE_I2S0_DATAIN / GPIO_S0_SC_11 HDA_SDI0 / LPE_I2S1_CLK / GPIO_S0_SC_12 HDA_SDI1 / LPE_I2S1_FRM / GPIO_S0_SC_13 SD3_CLK / GPIO_S0_SC_33 HDA_DOCKRST# / LPE_I2S1_DATAOUT / GPIO_S0_SC_14 SD3_D0 / GPIO_S0_SC_34 HDA_DOCKEN# / LPE_I2S1_DATAIN / GPIO_S0_SC_15 SD3_D1 / GPIO_S0_SC_35 SD3_D2 / GPIO_S0_SC_36 LPE_I2S2_CLK / SATA_DEVSLP_1 / GPIO_S0_SC_62 SD3_D3 / GPIO_S0_SC_37 LPE_I2S2_FRM / GPIO_S0_SC_63 SD3_CD# / GPIO_S0_SC_38 LPE_I2S2_DATAIN / GPIO_S0_SC_64 SD3_CMD / GPIO_S0_SC_39 LPE_I2S2_DATAOUT / GPIO_S0_SC_65 SD3_1P8EN / GPIO_S0_SC_40 SD3_PWREN# / GPIO_S0_SC_41 RESERVED_P34 RESERVED_N34 SD3_RCOMP RESERVED_AK9 RESERVED_AK7 OF 10 PROCHOT# AY7 PEG_HTX_GRX_P0 AY6 PEG_HTX_GRX_N0 C76 C77 1 VGA@ 1U_0402_16V7K VGA@ 1U_0402_16V7K AT14 PEG_GTX_C_HRX_P0 AT13 PEG_GTX_C_HRX_N0 AV6 PEG_HTX_GRX_P1 AV4 PEG_HTX_GRX_N1 C78 C79 1 VGA@ 1U_0402_16V7K VGA@ 1U_0402_16V7K AT10 PEG_GTX_C_HRX_P1 AT9 PEG_GTX_C_HRX_N1 C1135 C1000 AT7 PCIE_PTX_DRX_P2 AT6 PCIE_PTX_DRX_N2 1U_0402_16V7K 1U_0402_16V7K 15 15 PEG_GTX_C_HRX_P0 PEG_GTX_C_HRX_N0 15 15 PEG_HTX_C_GRX_P1 PEG_HTX_C_GRX_N1 15 15 PEG_GTX_C_HRX_P1 PEG_GTX_C_HRX_N1 15 15 PCIE_PTX_C_DRX_P2 PCIE_PTX_C_DRX_N2 AP12 PCIE_PRX_DTX_P2 AP10 PCIE_PRX_DTX_N2 PCIE_PRX_DTX_P2 PCIE_PRX_DTX_N2 C1133 C1134 AP6 PCIE_PTX_DRX_P3 AP4 PCIE_PTX_DRX_N3 1U_0402_16V7K 1U_0402_16V7K 26 26 PCIE_PRX_DTX_P3 PCIE_PRX_DTX_N3 dGPU WLAN 26 26 PCIE_PTX_C_DRX_P3 PCIE_PTX_C_DRX_N3 AP9 PCIE_PRX_DTX_P3 AP7 PCIE_PRX_DTX_N3 BB7 BB5 PEG_HTX_C_GRX_P0 PEG_HTX_C_GRX_N0 25 25 C PCIE LAN 25 25 Follow CRB V2.0 0ohm till to GND BG3 BD7 BG5 BE3 BD5 VGA_CLKREQ# PCIE_CLKREQ_1# WLAN_CLKREQ# LAN_CLKREQ# AP14 AP13 PCIE_RCOMPP PCIE_RCOMPN VGA_CLKREQ# 15 WLAN_CLKREQ# LAN_CLKREQ# 26 25 +1.8VS RP51 VGA_CLKREQ# PCIE_CLKREQ_1# WLAN_CLKREQ# LAN_CLKREQ# 10K_0804_8P4R_5% RP46 HDA_SYNC HDA_SDOUT HDA_BIT_CLK HDA_RST# R975 402_0402_1% BB4 BB3 HDA_SYNC_AUDIO HDA_SDOUT_AUDIO HDA_BITCLK_AUDIO HDA_RST_AUDIO# 31 31 31 31 33_0804_8P4R_5% EMC@ AV10 AV9 BF20 BG22 BH20 BJ21 BG20 BG19 BG21 BH18 BG18 BF28 BA30 BD28 BC30 HDA_RCOMP HDA_RST# HDA_SYNC HDA_BIT_CLK HDA_SDOUT HDA_SDIN0 T189 T191 HDA_RCOMP R976 HDA_BITCLK_AUDIO C1001 49.9_0402_1% 22P_0402_50V8J @EMC@ HDA_SDIN0 @ 31 GPIO_S0_SC_14 @ Follow CRB v2.0 GPIO_S0_SC_65 P34 N34 R979 73.2_0402_1% AK9 AK7 C24 +1.8VS GPIO_S0_SC_63 R977 10K_0402_5% +1.0VS H_PROCHOT# Internal PD 2K B GPIO_S0_SC_63: BIOS Boot Selection 0 = LPC 1 = SPI GPIO_S0_SC_63 FH8065301546401_FCBGA131170 B0@ 29 GPIO_S0_SC_65: Security Flash Descriptors 0 = Override 1 = Normal Operation (Internal PU) @EMC@ C1002 10P_0402_50V8J +1.8VS DGPU_HOLD_RST#_SOC1.8V DGPU_HOLD_RST#_SOC1.8V R1175 0_0402_5% @ GPIO_S0_SC_14 A S Issued Date 2014/03/19 TXE_DBG G Q62 MESS138W-G_SOT323-3 2015/03/18 Deciphered Date Title VLV-M SOC SATA/PCI-E/HDA THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A 29 Compal Electronics, Inc Compal Secret Data Security Classification EC programing : "High"for Flash BIOS D 15,9 R978 10K_0402_5% GPIO_S0_SC_65 A5WAM_Bay Trail M_LA‐B981P Sheet Monday, May 12, 2014 of 47 Rev 0.1 +3VS +1.8VALW GND GND XTAL_25M_OUT ICLK_ICOMP ICLK_RCOMP AD10 AD12 C1004 10P_0402_50V8J dGPU 15 15 AF6 AF4 CLK_PEG_VGA# CLK_PEG_VGA 26 26 CLK_PCIE_WLAN# CLK_PCIE_WLAN LAN 25 25 CLK_PCIE_LAN# CLK_PCIE_LAN +1.8VALW R989 R1026 R1024 XDP_H_TDI XDP_H_TMS XDP_H_TCK XDP_H_TRST# XDP_H_TCK XDP_H_TRST# XDP_H_TMS XDP_H_TDI XDP_H_TDO XDP_H_PRDY# XDP_H_PREQ_BUF# 51_0804_8P4R_5% C @ T193 @T193 SOC_SPI_MISO SOC_SPI_MOSI SOC_SPI_CLK 22 30 TS_INT_R# TP_INT# D14 G12 F14 F12 G16 D18 F16 AT34 SOC_LID_OUT# SOC_SMI# SVID_ALERT# SVID_DATA SVID_CLK SIO_PWM_0 / GPIO_S0_SC_94 SIO_PWM_1 / GPIO_S0_SC_95 PMC_ACIN D40 BF34 BD34 BD32 BF32 2.2K_0402_5% +1.8VALW ACIN P Y PMC_PLTRST# A 29,35 3.3V PLT_RST_BUF# 15,25,26,29,30 NL17SZ07DFT2G_SC70-5 SA00004BV00 RB751V-40-YS_SOD323-2 PLT_RST# Buffer C1174 @EMC@ 0.01U_0402_16V7K PLT_RST_BUF# D26 G24 F18 F22 D22 J20 D20 F26 K26 J26 BG9 F20 J24 G18 T192@ 32.768k PMC_SUSCLK D +1.8VALW PMC_SLP_S4# PMC_SLP_S3# DGPU_PRSNT# PMC_ACIN PMC_PCIE_WAKE# PMC_BATLOW# PMC_PWRBTN# PMC_RSTBTN# PMC_PLTRST# GPIO_S5_17 PMC_SUS_STAT# GPIO_S5_22 GPIO_S5_23 GPIO_S5_24 GPIO_S5_25 GPIO_S5_26 GPIO_S5_27 GPIO_S5_28 GPIO_S5_29 GPIO_S5_30 GPIO_S5_8 GPIO_S5_9 GPIO_S5_10 OF 13 DGPU_PRSNT# T209@ 10K_0804_8P4R_5% UMA H DIS L* R485 T205@ T207@ 100K_0402_5% PMC_CORE_PWROK @EMC@ 0.047U_0402_25V7K C1007 DDR_CORE_PWROK EMC@ 0.01U_0402_16V7K C1158 PMC_PLTRST# EMC@ 1U_0402_16V7K C1006 C11 RTC_TEST# C12 RTC_RST# R990 EC_RSMRST# B10 B7 EC_RSMRST# PMC_CORE_PWROK C9 A9 B8 P22 ILB_RTC_X1 ILB_RTC_X2 ILB_RTC_EXTPAD EC_RSMRST# 29 100K_0402_5% EMC@ 1U_0402_16V7K C1155 C1008 1U_0402_16V7K +RTCVCC B24 VR_SVID_ALERT#_SOC R1065 A25 VR_SVID_DATA_SOC R1066 C25 RP55 PMC_SLP_S4# SOC_KBRST# SOC_LID_OUT#4 R1064 73.2_0402_1% 20_0402_1% 16.9_0402_1% VR_SVID_ALERT# 40 VR_SVID_DATA 40 VR_SVID_CLK 40 SIO_SPI_CS# / GPIO_S0_SC_66 SIO_SPI_MISO / GPIO_S0_SC_67 SIO_SPI_MOSI / GPIO_S0_SC_68 SIO_SPI_CLK / GPIO_S0_SC_69 C EC_SLP_S4# EC_KBRST# EC_LID_OUT# 0_0804_8P4R_5% 9022@ RP56 EC_SMI# EC_SCI# PBTN_OUT# 0_0804_8P4R_5% 9022@ +3VALW_EC 9012@ 19 VCCA VCCB +1.8VALW R994 10M_0402_5% K24 N24 M20 J18 M18 K18 K20 M22 M24 SOC_SMI# SOC_SCI# PMC_PWRBTN# AU32 AT32 U54 PMC_SLP_S3# PMC_SLP_S4# SOC_KBRST# SOC_LID_OUT# SOC_SERIRQ SOC_SMI# SOC_SCI# PMC_PWRBTN# 32.768KHZ_12.5PF_Q13FC135000040 Y8 1 GPIO_RCOMP PMC_PCIE_WAKE# PMC_BATLOW# DGPU_PRSNT# LS_OE output ILB_RTC_X1 ILB_RTC_X2 GPIO_S5_0 GPIO_S5_1 / PMC_WAKE_PCIE_1 GPIO_S5_2 / PMC_WAKE_PCIE_2 GPIO_S5_3 / PMC_WAKE_PCIE_3 GPIO_S5_4 GPIO_S5_5 / PMU_SUSCLK_1 GPIO_S5_6 / PMU_SUSCLK_2 GPIO_S5_7 / PMU_SUSCLK_3 N26 R983 +1.0VS RTC domain ILB_RTC_X1 ILB_RTC_X2 ILB_RTC_EXTPAD RTC_VCC_P22 GPIO_RCOMP PMC_RSMRST# PMC_CORE_PWROK PCU_SPI_CS_0# PCU_SPI_CS_1# / GPIO_S5_21 PCU_SPI_MISO PCU_SPI_MOSI PCU_SPI_CLK C13 A13 C19 B ILB_RTC_TEST# ILB_RTC_RST# TAP_TCK TAP_TRST# TAP_TMS TAP_TDI TAP_TDO TAP_PRDY# TAP_PREQ# RESERVED_AT34 B18 B16 C18 A17 C17 C16 B14 C15 SOC_KBRST# TS_INT#_CPU TP_INT#_CPU R1016 R1015 PMC_PLT_CLK_0 / GPIO_S0_SC_96 PMC_PLT_CLK_1 / GPIO_S0_SC_97 PMC_PLT_CLK_2 / GPIO_S0_SC_98 PMC_PLT_CLK_3 / GPIO_S0_SC_99 PMC_PLT_CLK_4 / GPIO_S0_SC_100 PMC_PLT_CLK_5 / GPIO_S0_SC_101 C23 C21 B22 A21 C22 SOC_SPI_CS0# 0_0402_5%1 TSI@ 0_0402_5%1 RS@ RESERVED_AM9 RESERVED_AM10 BH7 BH5 BH4 BH8 BH6 BJ9 RP52 PCIE_CLKN_3 PCIE_CLKP_3 AM9 AM10 51_0402_5% XDP_H_PRDY# 51_0402_5% XDP_H_TDO 200_0402_5% XDP_H_PREQ_BUF# PCIE_CLKN_2 PCIE_CLKP_2 AM4 AM6 For XDP use PMC_SUSPWRDNACK / GPIO_S5_11 PMC_SUSCLK_0 / GPIO_S5_12 PMC_SLP_S0IX# / GPIO_S5_13 PMC_SLP_S4# PMC_SLP_S3# GPIO_S5_14 PMC_ACPRESENT PMC_WAKE_PCIE_0# / GPIO_S5_15 PMC_BATLOW# PMC_PWRBTN# / GPIO_S5_16 PMC_RSTBTN# PMC_PLTRST# GPIO_S5_17 PMC_SUS_STAT# / GPIO_S5_18 PCIE_CLKN_1 PCIE_CLKP_1 AK4 AK6 AU34 AV34 BA34 AY34 RP47 PCIE_CLKN_0 PCIE_CLKP_0 4.02K_0402_1% ICLK_ICOMP 47.5_0402_1% ICLK_RCOMP WLAN SIO_UART2_RXD / GPIO_S0_SC_74 SIO_UART2_TXD / GPIO_S0_SC_75 SIO_UART2_RTS# / GPIO_S0_SC_76 SIO_UART2_CTS# / GPIO_S0_SC_77 RESERVED_AD10 RESERVED_AD12 AF9 AF7 R984 R985 RESERVED_AD9 AD14 AD13 ICLK_ICOMP ICLK_RCOMP SIO_UART1_RXD / GPIO_S0_SC_70 SIO_UART1_TXD / GPIO_S0_SC_71 SIO_UART1_RTS# / GPIO_S0_SC_72 SIO_UART1_CTS# / GPIO_S0_SC_73 R982 4.7K_0402_5% U53 NC AD9 ICLK_OSCIN ICLK_OSCOUT 1 C1003 10P_0402_50V8J D 1 AH12 AH10 XTAL_25M_IN XTAL_25M_OUT R981 1M_0402_5% Y7 25MHZ_10PF_7V25000014 1.8V USOC1E G XTAL_25M_IN PVT modify C1009 18P_0402_50V8J C1010 18P_0402_50V8J SOC_SERIRQ SOC_SCI# AV32 BA28 AY28 AY30 10 LS_OE A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 OE GND 20 18 17 16 15 14 13 12 EC_SLP_S3# EC_SLP_S4# EC_KBRST# EC_LID_OUT# EC_SERIRQ EC_SMI# 29 EC_SCI# 29 PBTN_OUT# 29 29 29 29 29,30 29 11 TXB0108PWR_TSSOP20 B FH8065301546401_FCBGA131170 B0@ SOC_SERIRQ R1021 NTPM@ 0_0402_5% EC_SERIRQ PMC_SLP_S3# R1025 NTPM@ 0_0402_5% EC_SLP_S3# R995 49.9_0402_1% +1.8VALW +3VALW_EC U71 SOC_SERIRQ C1013 1U_0402_16V7K RTC_TEST# PMC_SLP_S3# EC_SPICS# EC_MISO EC_MOSI EC_SPICLK +BIOS_SPI SPI_CS0# SPI_MISO SPI_MOSI SPI_CLK SPI_CS0# SPI_MISO SPI_WP# 4 SPI_CS0# SPI_MISO SPI_MOSI SPI_CLK 22_0804_8P4R_5% EMC@ +CHGRTC D22 CS# VCC DO(IO1) HOLD#(IO3) WP#(IO2) CLK GND DI(IO0) SPI_HOLD# SPI_CLK SPI_MOSI W25Q64DWSSIG_SO8 RP48 SOC_SPI_CS0# SOC_SPI_MISO SOC_SPI_MOSI SOC_SPI_CLK +RTCBATT C1012 1U_0402_6.3V6K U56 22_0804_8P4R_5% EMC@ A C1011 1U_0402_6.3V6K W=20mils RS@ RTC_TEST# 0_0402_5% R1088 @ RTC_RST# 0_0402_5% R1089 Clear CMOS Close to RAM door CLR_CMOS# @ JCMOS1 SHORT PADS CLR_CMOS# 29 +1.35VS +3VALW C151 1U_0402_16V7K 3.3V 29 PMC_CORE_PWROK Reserve for EMI(Near SPI ROM) @EMC@ R1002 33_0402_5% @EMC@ C1014 10P_0402_50V8J Issued Date 2014/03/19 2015/03/18 Deciphered Date Title NC Y A R993 10K_0402_5% U55 1.35V DDR_CORE_PWROK NL17SZ07DFT2G_SC70-5 SA00004BV00 VLV-M SOC CLK/PMU/SPI THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: Compal Electronics, Inc Compal Secret Data Security Classification SPI_CLK EC_SLP_S3# W=20mils +RTCVCC W=10mil BAS40-04_SOT23-3 1 RP53 TPM@ Q83 MESS138W-G_SOT323-3 From EC (For share ROM) 20K_0402_1% R997 P RTC_RST# G SPI_HOLD# 3.3K_0402_5% R1000 R1034 10K_0402_5% TPM@ D SPI_WP# R996 20K_0402_1% S 3.3K_0402_5% +RTCVCC 0_0402_5% 2 G R1001 +1.8VALW RS@ SPI_CS0# 2 3.3K_0402_5% R998 From CPU +1.8VALW EC_SERIRQ +BIOS_SPI R999 EC_SPICS# EC_MISO EC_MOSI EC_SPICLK VCCB EO B4 G2129TL1U_SC70-6 +BIOS_SPI 29 29 29 29 +1.8VALW TPM@ VCCA GND A4 A5WAM_Bay Trail M_LA‐B981P Sheet Monday, May 12, 2014 of 47 Rev 0.1 A N15V‐GL/GM GPIO GPIO_S0_SC_59 0_0402_5% R1173 @ R1174 VGA@ 0_0402_5% DGPU_PWR_EN_SOC1.8V DGPU_HOLD_RST#_SOC1.8V GPIO_S5_SC_32 GPIO_S5_SC_33 M3 L1 K2 K3 M2 N3 P2 L3 J3 P3 H3 B12 USB3.0 Port 28 28 USB20_P0 USB20_N0 USB Hub 28 28 USB20_P1 USB20_N1 Touch Panel 22 22 USB20_P2 USB20_N2 Camera +1.8VALW R1007 R1009 22 22 10K_0402_5% USB_OC0# 10K_0402_5% USB_OC1# M16 K16 J14 G14 K12 J12 K10 H10 USB20_P3 USB20_N3 1K_0402_1% 1K_0402_1% 1 R1004 ICLK_USB_TERMP R1005 ICLK_USB_TERMN D10 F10 C USB_OC0# USB_OC1# RESERVED_P6 RESERVED_P7 RESERVED_M7 USB3_REXT0 RESERVED_P10 RESERVED_P12 RESERVED_M4 RESERVED_M6 GPIO_S5_40 GPIO_S5_41 GPIO_S5_42 GPIO_S5_43 USB3_RXP0 USB3_RXN0 USB3_TXP0 USB3_TXN0 USB_DP0 USB_DN0 R1036 1K_0402_5% VGL@ P6 P7 GPIO_S0_SC_59 D R1003 M7 1.24K_0402_1% M12 USB3_REXT0 R1037 10K_0402_5% VGM@ P10 P12 M4 M6 D4 E3 PCH_USB3_RX0_P PCH_USB3_RX0_N K6 K7 PCH_USB3_TX0_P PCH_USB3_TX0_N 28 28 USB3 Port 0 28 28 USB_DP1 USB_DN1 BIOS/EFI Top Swap USB_DP2 USB_DN2 USB_DP3 USB_DN3 RESERVED_H8 RESERVED_H7 +1.8VS H8 H7 ICLK_USB_TERMP ICLK_USB_TERMN RESERVED_H4 RESERVED_H5 H4 H5 R1006 10K_0402_5% @ USB_OC_0# / GPIO_S5_19 USB_OC_1# / GPIO_S5_20 GPIO_S0_SC_56 C 28 C20 B20 GPIO_S5_32 GPIO_S5_33 GPIO_S5_34 GPIO_S5_35 GPIO_S5_36 GPIO_S5_37 GPIO_S5_38 GPIO_S5_39 L DGPU_PWR_EN_SOC1.8V DGPU_HOLD_RST#_SOC1.8V 15,7 N15V‐GM PH at dGPU side M10 M9 PH at dGPU side 32 RESERVED_M10 RESERVED_M9 +1.8VS D GPIO_S5_31 H USOC1F G2 PVT modify N15V‐GL USB_PLL_MON M13 B4 B5 NOTE: Ref checklist rev1.2 p.25 USB_HSIC_RCOMP must NOT float if they are not being used R1012 49.9_0402_1%1 +1.8VS RP49 B HSIC_RCOMP 45.3_0402_1% PCU_SMB_CLK PCU_SMB_DATA PCU_SMB_ALERT# 4.7K_0804_8P4R_5% +1.8VS 29,30 29,30 29,30 29,30 29,30 29 30 30 LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 LPC_FRAME# LPC_CLK_EC LPC_CLK_TPM LPC_CLKRUN# SOC_SERIRQ R1013 LPC_RCOMP 22_0402_5% EMC@ R1014 LPC_CLK_0 22_0402_5% TPM@ R1017 LPC_CLK_1 E2 D2 A7 BF18 BH16 BJ17 BJ13 BG14 BG17 BG15 BH14 BG16 BG13 USB_PLL_MON USB_HSIC0_DATA USB_HSIC0_STROBE ILB_8254_SPKR / GPIO_S0_SC_54 USB_HSIC1_DATA USB_HSIC1_STROBE SIO_I2C0_DATA / GPIO_S0_SC_78 SIO_I2C0_CLK / GPIO_S0_SC_79 BD12 BC12 BD14 BC14 BF14 BD16 BC16 BH12 R1011 10K_0402_5% @ GPIO_S0_SC_56 DBG_UART_TXD T203@ GPIO_S0_SC_55 GPIO_S0_SC_56 GPIO_S0_SC_57 / PCU_UART_TXD GPIO_S0_SC_58 GPIO_S0_SC_59 GPIO_S0_SC_60 GPIO_S0_SC_61 / PCU_UART_RXD GPIO_S0_SC_59 DBG_UART_RXD SOC_SPKR T204@ SOC_SPKR GPIO_S0_SC_56: Top Swap( A16 Override ) 0 = Top address bit is unchanged 1 = Top address bit is inverted Reference EDS2.0 Page 51 31 BH22 BG23 USB_HSIC_RCOMP SIO_I2C1_DATA / GPIO_S0_SC_80 SIO_I2C1_CLK / GPIO_S0_SC_81 LPC_RCOMP / VGA_RCOMP ILB_LPC_AD_0 / GPIO_S0_SC_42 ILB_LPC_AD_1 / GPIO_S0_SC_43 ILB_LPC_AD_2 / GPIO_S0_SC_44 ILB_LPC_AD_3 / GPIO_S0_SC_45 ILB_LPC_FRAME# / GPIO_S0_SC_46 ILB_LPC_CLK_0 / GPIO_S0_SC_47 ILB_LPC_CLK_1 / GPIO_S0_SC_48 ILB_LPC_CLKRUN# / GPIO_S0_SC_49 ILB_LPC_SERIRQ / GPIO_S0_SC_50 For Touch Screen BG24 BH24 +1.8VS SOC_I2C5_DATA R1143 SIO_I2C2_DATA / GPIO_S0_SC_82 SIO_I2C2_CLK / GPIO_S0_SC_83 BG25 BJ25 SOC_I2C2_DATA SOC_I2C2_CLK SOC_I2C5_CLK TSI@ 2.2K_0402_5% R1144 TSI@ 2.2K_0402_5% +1.8VS SIO_I2C3_DATA / GPIO_S0_SC_84 SIO_I2C3_CLK / GPIO_S0_SC_85 B BG26 BH26 USB_RCOMPO USB_RCOMPI BF27 BG27 TSI@ SOC_I2C5_DATA Q80A DMN63D8LDW-7_SOT363-6 I2C5_SDA_PNL 22 I2C5_SCL_PNL 22 BG12 PCU_SMB_DATA BH10 PCU_SMB_CLK PCU_SMB_ALERT# BG11 S PCU_SMB_CLK Q79A DMN63D8LDW-7_SOT363-6 PCU_SMB_DATA / GPIO_S0_SC_51 PCU_SMB_CLK / GPIO_S0_SC_52 PCU_SMB_ALERT# / GPIO_S0_SC_53 SIO_I2C6_DATA / GPIO_S0_SC_90 SIO_I2C6_CLK / GPIO_S0_SC_91 / SD3_WP G PCU_SMB_DATA S EC_SMB_DA2 D 13,14,15,26,29 Q79B DMN63D8LDW-7_SOT363-6 SIO_I2C5_DATA / GPIO_S0_SC_88 SIO_I2C5_CLK / GPIO_S0_SC_89 ILB_LPC_CLK_0 : Output Need Check with EC of 25MHz, GPIO_S0_SC_092 GPIO_S0_SC_093 OF 13 ILB_LPC_CLK_1 is for CLK_0 feedback.(Input) Set to Output for Normal Usage SOC_I2C5_DATA SOC_I2C5_CLK G BH28 BG28 TSI@ Q80B DMN63D8LDW-7_SOT363-6 SOC_I2C5_CLK D EC_SMB_CK2 D 13,14,15,26,29 G Pull High at EC side S SIO_I2C4_DATA / GPIO_S0_SC_86 SIO_I2C4_CLK / GPIO_S0_SC_87 G R1010 @ 0_0402_5% @EMC@ 10P_0402_50V8J LPC_CLK_0 D6 C7 USB_RCOMP D C1015 S R1008 45.3_0402_1% BJ29 BG29 BH30 BG30 GPIO_S0_SC_92 GPIO_S0_SC_93 For Touch Pad T202@ +1.8VS SOC_I2C2_DATA R1153 FH8065301546401_FCBGA131170 B0@ SOC_I2C2_CLK 2.2K_0402_5% R1152 2.2K_0402_5% +1.8VS R1176 VGA@ 0_0402_5% GPIO_S0_SC_92 G DGPU_PWR_EN_SOC1.8V PVT modify I2C2_SDA_TP 30 I2C2_SCL_TP 30 G A D SOC_I2C2_DATA Q81A DMN63D8LDW-7_SOT363-6 S PH at dGPU side Q81B DMN63D8LDW-7_SOT363-6 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2014/03/19 D S SOC_I2C2_CLK 2015/03/18 Deciphered Date Title VLV-M SOC USB/LPC/SMBus THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A5WAM_Bay Trail M_LA‐B981P Sheet Monday, May 12, 2014 of 47 Rev 0.1 A D D +1.35V_SOC USOC1G +SOC_VCC AA27 AA29 AA30 AC27 AC29 AC30 AD27 AD29 AD30 AF27 AF29 AG27 AG29 AG30 P26 P27 U27 U29 V27 V29 V30 Y27 Y29 Y30 T194 AA22 TP2_CORE_VCC_S0iX DRAM_VDD_S4_AD38 DRAM_VDD_S4_AF38 DRAM_VDD_S4_A48 DRAM_VDD_S4_AK38 DRAM_VDD_S4_AM38 DRAM_VDD_S4_AV41 DRAM_VDD_S4_AV42 DRAM_VDD_S4_BB46 DRAM_VDD_S4_BD49 DRAM_VDD_S4_BD52 DRAM_VDD_S4_BD53 DRAM_VDD_S4_BF44 DRAM_VDD_S4_BG51 DRAM_VDD_S4_BJ48 DRAM_VDD_S4_C51 DRAM_VDD_S4_D44 DRAM_VDD_S4_F49 DRAM_VDD_S4_F52 DRAM_VDD_S4_F53 DRAM_VDD_S4_H46 DRAM_VDD_S4_M41 DRAM_VDD_S4_M42 DRAM_VDD_S4_V38 DRAM_VDD_S4_Y38 CORE_VCC_S0IX_AD27 CORE_VCC_S0IX_AD29 CORE_VCC_S0IX_AD30 CORE_VCC_S0IX_AF27 CORE_VCC_S0IX_AF29 CORE_VCC_S0IX_AG27 CORE_VCC_S0IX_AG29 CORE_VCC_S0IX_AG30 CORE_VCC_S0IX_P26 CORE_VCC_S0IX_P27 CORE_VCC_S0IX_U27 CORE_VCC_S0IX_U29 CORE_VCC_S0IX_V27 CORE_VCC_S0IX_V29 CORE_VCC_S0IX_V30 CORE_VCC_S0IX_Y27 CORE_VCC_S0IX_Y29 CORE_VCC_S0IX_Y30 AD38 AF38 1 B BB8 P28 N28 VGFX_VSNS VCORE_VSNS VCORE_GSNS 1250mA C1019 C1020 C1021 C1022 1 1 C C1147 C1148 10U_0603_6.3V6M 10U_0603_6.3V6M JUMP_43X118 2.2U_0402_6.3V6M 2.2U_0402_6.3V6M 2.2U_0402_6.3V6M 2.2U_0402_6.3V6M JP3 short 0715 Add for CRT flicker ICLK_V1P35_S3_F2_AG18 ICLK_V1P35_S3_F1_AJ19 VGA_V1P35_S3_F1_BD1 AG18 AJ19 VGA_V1P35_S3_F1 DRAM_V1P35_S0IX_F1_AD36 UNCORE_V1P35_S0IX_F2_AG32 UNCORE_V1P35_S0IX_F3_V36 UNCORE_V1P35_S0IX_F4_U36 UNCORE_V1P35_S0IX_F5_AA25 VGA_V1P35_S3_F1 C1023 R1084 8.06K_0402_1% 10U_0603_6.3V6M AD36 AG32 V36 U36 OUT IN BYP SHDN G916T1UF_SOT23-5 C1179 1U_0402_6.3V6K R1085 100K_0402_1% B AA25 29,32,37,38,39 UNCORE_V1P35_S0IX_F6_AF19 UNCORE_VNN_SENSE UNCORE_V1P35_S0IX_F1_AG19 CORE_VCC_SENSE_P28 OF 13 CORE_VSS_SENSE_N28 GND BD1 UNCORE_VNN_S3_AM22 UNCORE_VNN_S3_AK32 UNCORE_VNN_S3_AK30 UNCORE_VNN_S3_AK29 UNCORE_VNN_S3_AK27 UNCORE_VNN_S3_AK25 UNCORE_VNN_S3_AK24 UNCORE_VNN_S3_AK22 UNCORE_VNN_S3_AJ24 UNCORE_VNN_S3_AJ22 UNCORE_VNN_S3_AG24 UNCORE_VNN_S3_AG22 UNCORE_VNN_S3_AF24 UNCORE_VNN_S3_AF22 UNCORE_VNN_S3_AD22 UNCORE_VNN_S3_AC24 UNCORE_VNN_S3_AC22 UNCORE_VNN_S3_AA24 UNCORE_VNN_S3_AD24 +3VALW U65 420mA C1024 C1025 C1026 C1027 C1028 C1029 C1030 C1031 C1032 C1033 AF19 AG19 FH8065301546401_FCBGA131170 R1020 100_0402_1% @EMC@ L63 HCB2012KF-121T50_2P JP3 JP@ 40 40 40 R1019 100_0402_1% R1018 100_0402_1% @EMC@ L62 HCB2012KF-121T50_2P +1.35VS AM22 AK32 AK30 AK29 AK27 AK25 AK24 AK22 AJ24 AJ22 AG24 AG22 AF24 AF22 AD22 AC24 AC22 AA24 AD24 +SOC_VCC 1U_0402_6.3V6K 1U_0402_16V7K TP2_CORE_VCC_S0IX 14A +SOC_VNN +SOC_VNN C1017 C1018 A48 AK38 AM38 AV41 AV42 BB46 BD49 BD52 BD53 BF44 BG51 BJ48 C51 D44 F49 F52 F53 H46 M41 M42 V38 Y38 @ CORE_VCC_S0IX_AA27 CORE_VCC_S0IX_AA29 CORE_VCC_S0IX_AA30 CORE_VCC_S0IX_AC27 CORE_VCC_S0IX_AC29 CORE_VCC_S0IX_AC30 +1.35V_L @EMC@ L61 HCB2012KF-121T50_2P C 20mil 12A B0@ 2 2 2 2 2 22U_0805_6.3V6M 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K VOUT R1087 36K_0402_5% SUSP# = 1.25 (1 + R1/R2) C1181 1U_0402_16V7K A A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2014/03/19 2015/03/18 Deciphered Date Title VLV-M SOC Power THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A5WAM_Bay Trail M_LA‐B981P Sheet Monday, May 12, 2014 10 of 47 Rev 0.1 A B @ PJP101 ACES_50305-00441-001_4P 1 DC_IN_S1 D VIN EMI@ PL101 HCB2012KF-121T50_0805 EMI@ PC102 100P_0603_50V8 2 GND GND C EMI@ PC103 1000P_0603_50V7K 2 3 @PR111 @ PR111 0_0402_5% +3VLP - PBJ101 @ + PR112 560_0603_5% PR113 560_0603_5% +CHGRTC +RTCBATT ML1220T13RE 4 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2014/03/19 Deciphered Date 2015/03/18 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C DCIN / RTC A5WAM_Bay Trail M_LA‐B981P Sheet Monday, May 12, 2014 D 33 of 47 Rev 0.1 A B C D +3VLP 1 @ PC202 0.1U_0603_25V7K @ PR211 0_0402_5% BI PR201 6.49K_0402_1% PR210 1K_0402_1% EC_SMB_CK1 29,35 @ PR204 10K_0402_1% @ PU201 @ PR206 100K_0402_1% +3VLP BATT_TEMP MAINPWON 29 VCC TMSNS1 GND RHYST1 OT1 TMSNS2 OT2 RHYST2 @ PR205 10K_0402_1% 29,35 @ PR207 47K_0402_1% TH EC_SMB_DA1 EC_SMCK 100_0402_1% PR208 100_0402_1% 2 PR209 EC_SMDA @ PJP201 OCTEK_BTJ-08KEAB_8P-T 10 GND GND 8 7 6 5 4 3 2 1 @ PH201 100K_0402_1%_NCP15WF104F03RC EMI@ PC201 1000P_0402_50V7K BATT_S1 EMI@ PL201 HCB2012KF-121T50_0805 EMI@ PL202 HCB2012KF-121T50_0805 2 G718TM1U_SOT23-8 BATT+ For KB9012 OTP -Battery_pin define PIN1 GND PIN2 GND PIN3 SMD PIN4 SMC PIN5 TS PIN6 B/I PIN7 Batt+ PIN8 Batt+ -Battery Con_pin define PIN8 GND PIN7 GND PIN6 SMD PIN5 SMC PIN4 TS PIN3 B/I PIN2 Batt+ PIN1 Batt+ For KB9022 OTP 92 1.2V 1.0V 56 1.2V 1.0V PR216 22.6K ohm32.4K ohm PR227 26.1K ohm30.9K ohm Need confirm the setting For KB9012 sense 10mΩ Active Recovery 65W 69.55W,0.73V 55.9W,0.59V 40W 42.8W,0.73V 34.4W,0.59V +EC_VCCA 9022@ PR216 16.9K_0402_1% 29,35 PR202 10K_0402_1% 2 9012@ PR216 22.6K_0402_1% 1 ADP_I 29 VCIN0_PH B+ @9012@ PR227 26.1K_0402_1% MAINPWON @9022@ PR227 30.9K_0402_1% @ PR223 162K_0402_1% @9022@ PR230 80.6K_0402_1% VCIN1_PROCHOT 29 H_PROCHOT#_EC 29 B value:4250K±1% 29 PH202 100K_0402_1%_NCP15WF104F03RC @9022@ 0.1U_0402_25V6 PR229 PR203 10K_0402_1% COMMON PART 10K_0402_1% @9022@ PC203 2 VCIN1_BATT_DROP @9022@ PR231 0_0402_5% 2 29,36 4 29 Compal Electronics, Inc Compal Secret Data Security Classification Issued Date ECAGND 2014/03/19 Deciphered Date 2015/03/18 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C BATTERY CONN / OTP A5WAM_Bay Trail M_LA‐B981P Monday, May 12, 2014 D Sheet 34 of 47 Rev 0.1 A B C D PQ301 Protection for reverse input G Vgs = 20V Vds = 60V Id = 250mA B+ S 2N7002KW_SOT323-3 PR302 SRP ACDRV SRN SCL 10 +3VALW @ PR320 @PR320 0_0402_5% 2 PC320 0.01U_0402_25V7K PR317 100K_0402_1% BQ24725A_IOUT BQ24725A_ACDET BQ24725A_ILIM PR316 316K_0402_1% EC_SMB_CK1 29,34 EC_SMB_DA1 29,34 ADP_I 29,34 VILIM = 20*ILIM*Rsr ILIM = 3.3*100/(100+316)/20/0.01 = 3.966 A PC322 100P_0402_50V8J 1 PR319 66.5K_0402_1% Max 18.12V 17.70V L >H H >L Typ 17.63V 17.22V PC321 0.22U_0402_16V7K Vin Dectector Min 17.16V 16.76V @ PC323 100P_0402_50V8J PC307 0.01U_0402_50V7K 2 PC315 10U_0805_25V6K BATT+ PC314 10U_0805_25V6K 2 CSON1 PC317 0.1U_0402_25V6 PR311 0.01_1206_1% CSOP1 CHG 1 2 PC316 0.1U_0402_25V6 PQ306 AON7408L_DFN8-5 PC318 0.1U_0603_16V7K ACIN PR318 422K_0402_1% BQ24725A_BATDRV VIN PQ305 AON7408L_DFN8-5 11 ILIM BATDRV SDA ACOK 12 PR313 10_0603_1% CSOP1 SRP1 PR314 6.8_0603_1% CSON1 SRN1 14 13 CMSRC DL_CHG Power loss: 0.32W for 3.5A CSR rating: 1W VSRP-VSRN spec < 81.28mV PL302 10UH_3.5A_20%_7X7X3_M GND 15 2BQ24725A_BATDRV_1 7X7X3 Isat: 3.8A @EMI@ PC319 @EMI@ PR312 680P_0402_50V7K 4.7_1206_5% @EMI@ PC306 0.1U_0402_25V6 PC313 1U_0603_25V6K ACP 29,8 PR315 PR305 4.12K_0603_1% BQ24725A_LX LODRV IOUT +3VLP 100K_0402_1% BQ24725A_REGN 16 BTST ACN ACDET BQ24725A_ACDRV PR308 0_0603_5% DH_CHG REGN DH_CHG PR307 2.2_0603_5% BQ24725A_BST2 17 PD302 RB751V-40_SOD323-2 BQ24725A_BATDRV 1 PQ304 AO4406AL_SO8 Rds(on) = 30mohm max Vgs = 20V Vds = 30V ID = 7A (Ta=70C) VF = 0.37V BQ24725ARGRR_QFN20_3P5X3P5 BQ24725A_CMSRC 2 PAD 18 PU301 2 1 1U_0603_25V6K PC311 0.047U_0402_25V7K HIDRV PC312 21 VF = 0.5V PD301 BAS40CW_SOT323-3 BQ24725A_VCC2 PR310 4.12K_0603_1% PC309 0.1U_0402_25V6 BQ24725A_ACN PR309 4.12K_0603_1% BQ24725A_ACP 2 1 PC308 0.1U_0402_25V6 BQ24725A_ACDRV_1 EMI@ PC305 2200P_0402_25V7K VIN PQ303 AO4406AL_SO8 Isat: 4A DCR: 27mohm PC304 10U_0805_25V6K 2 CHG_B+ EMI@ PL301 1UH_NRS4018T1R0NDGJ_3.2A_30% PR303 0.02_1206_1% PC303 10U_0805_25V6K PC302 0.1U_0402_25V6 @ PR304 0_0402_5% PQ302 AON6414AL_DFN8-5 PC301 2200P_0402_50V7K P2 PR306 10_1206_1% P1 BQ24725A_LX VIN Rds(on) = 35mohm max Vgs = 20V Vds = 30V ID = 7.7A (Ta=70C) max Power loss 0.22W for 90W;0.12W for 65W system CSR rating: 1W VACP-VACN spec < 80.64mV 19 3M_0402_5% 1M_0402_5% Need check the SOA for inrush PHASE Rds(on) typ = 35mohm max Vgs = 20V Vds = 30V ID = 7.7A (Ta=70C) 20 VCC PC310 0.1U_0402_25V6 PR301 D **Design Notes** #For 65 /90W system, 3S1P/3S2P battery Maximum Charging current 3.5A Maximum Battery discharge power 55W #Register Setting 0X12 bit8 set (default 1) to disable IFAULT HI if add ISN choke #Circuit Design ACOK,ILIM pull high voltage need base on 3/5V enable control Use 10X10 choke and 3X3 H/L Side MOSFET Charge current 3.5A Power loss : 1.82W Power density : 0.81 (15X15) If use 4S per cell 4.35V battery, need additional circuit for ACDET(PR218/PR220/PR222 change to 0.1%, parallel resistors with PR222 for ACDET setting) PC223 0.22U can't be changed (Wrong adapter concern) For the design, need double confirm PQ202,PQ203,PQ204 rating #Protect function ACOVP : ACDET voltage > 3.14V Charger timeout : No communication within 175s(default) ACOC : 3.33 X Input current DAC setting(default) CHGOCP : 3/4.5/6A based on current current setting BATOVP : 103-106% BATLOWV : 2.5V TSHUT : 155C IFAULT HI : 750mV (default) IFAULT LOW : 150mV (default) Close EC chip Compal Electronics, Inc Compal Secret Data Security Classification Issued Date 2014/03/19 Deciphered Date 2015/03/18 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C Charger A5WAM_Bay Trail M_LA‐B981P Monday, May 12, 2014 Sheet D 35 of 47 Rev 0.1 A B C D E 1 EN1 and EN2 dont't floating PR402 499K_0402_1% PU401 PC406 10U_0805_25V6K 3V_VIN EN2 IN EN1 FB BS 3V5V_EN BST_3V 3V_FB PR401 1_0603_5% PC402 0.022U_0402_25V7K PL402 3.3V LDO 150mA~300mA SPOK PC410 22U_0603_6.3V6M PC409 22U_0603_6.3V6M PC408 22U_0603_6.3V6M 1 PC411 4.7U_0603_6.3V6M PR412 100K_0402_5% +3VALWP @ PC407 22U_0603_6.3V6M +3VLP PR405 13V_SN LDO 680P_0603_50V7K 4.7_1206_5% PG @EMI@ OUT 1.5UH_PCMB053T-1R5MS_6A_20% PC412 2 GND LX_3V @EMI@ 10 SYX198BQNC_QFN10_3X3 29,38,39 B+ 0.1U_0603_25V7K LX @ +3VALWP PR403 1K_0402_5% PC403 PC405 10U_0805_25V6K EMI@ PC404 2200P_0402_50V7K EMI@ PL401 HCB2012KF-121T50_0805 @EMI@ PC401 0.1U_0402_25V6 B+ PR404 150K_0402_1% ENLDO_3V5V Vout is 3.234V~3.366V TDC=6A @ PJ401 +3VALWP 1 2 +3VALW JUMP_43X118 B+ EN1 and EN2 dont't floating EMI@ PL403 HCB2012KF-121T50_0805 5V_VIN @ PJ402 29,34 EC_ON MAINPWON 3V5V_EN 5V_FB PC416 0.1U_0603_25V7K LDO VL PC424 4.7U_0603_6.3V6M SYX198CQNC_QFN10_3X3 +5VALW TDC=6A +5VALWP 1.5UH_PCMB053T-1R5MS_6A_20% 680P_0603_50V7K 4.7_1206_5% PG PR408 OUT PL404 LX_5V PC425 15V_SN VCC 10 @EMI@ LX @EMI@ GND JUMP_43X118 PC423 22U_0603_6.3V6M PC422 22U_0603_6.3V6M BST_5V PC421 22U_0603_6.3V6M @ PR407 0_0603_5% PR409 2.2K_0402_5% 1 PC420 22U_0603_6.3V6M BS SPOK PC419 4.7U_0603_6.3V6M 29 EN FB VCC_3V IN Vout is 4.998V~5.202V PC413 PR406 6800P_0402_25V7K 1K_0402_5% 2 @EMI@ PC418 0.1U_0402_25V6 @ EMI@ PC417 2200P_0402_50V7K PC415 10U_0805_25V6K PC414 10U_0805_25V6K +5VALWP PU402 5V LDO 150mA~300mA @ PR410 0_0402_5% PC426 4.7U_0402_6.3V6M PR411 1M_0402_1% 3V5V_EN EC VDD0 is +3VL, PC13 UNPOP EC VDD0 is +3VALW, PC13 POP 4 2014/03/19 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2015/03/18 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C D 3VALW/5VALW A5WAM_Bay Trail M_LA‐B981P Sheet Monday, May 12, 2014 E 36 of 47 Rev 0.1 D D 1.35V_B+ PR501 2.2_0603_5% BOOT_1.35V Note: S3 - sleep ; S5 - power off PC507 10U_0805_6.3V6K C VTTREF_1.35V VTTREF 20 VTT 19 VLDOIN BOOT VDDP FB FB_1.35V +1.35VP B PR508 10K_0402_1% @ PC514 0.1U_0402_16V7K Choke: 7x7x3 Rdc=8.3mohm(Typ), 10mohm(Max) PC510 0.033U_0402_16V7K PR506 8.06K_0402_1% PR509 680K_0402_1% SYSON +1.35VP S3 S5 TON PR507 887K_0402_1% 1.35V_B+ 28,29 EN_0.675VSP 10 DDR_PWROK MOSFET: 3x3 DFN H/S Rds(on): 27mohm(Typ), 34mohm(Max) Idsm: 7.5A@Ta=25C, 5.5A@Ta=70C VDDQ EN_1.35V +5VALW VDD PR505 100K_0402_5% L/S Rds(on): 9.9mohm(Typ), 13mohm(Max) Idsm: 13.5A@Ta=25C, 11A@Ta=70C GND RT8207MZQW_WQFN20_3X3 TON_1.35V 11 VDD_1.35V +1.35VP AON7506_DFN33-8-5 18 1 PC513 1U_0603_10V6K PQ502 VTTSNS 21 Switching Frequency: 285kHz Ipeak=10A Iocp~13A OVP: 110%~120% VFB=0.75V, Vout=1.515V MOSFET footprint: SIS412DN SUSP# @ PJ501 10,29,32,38,39 PR510 200K_0402_1% 32 SUSP D S G PC515 +1.35VP 2 +1.35V JUMP_43X118 @ PJ502 2 0.1U_0402_16V7K VTTREF_1.35V off on on CS PAD +0.675VSP off off on 12 PU501 VTTGND PGND Level L L H @EMI@ PC512 680P_0402_50V7K +5VALW PR504 5.1_0603_5% 13 LGATE Co-Lay @EMI@ PR503 4.7_1206_5% + B Mode S5 S3 S0 PR502 9.1K_0402_1% CS_1.35V PC508 1U_0603_10V6K UGATE 15 17 16 DL_1.35V PHASE ESR=15m ohm COMMON PART H=4.5 PC509 330U_2.5V_ESR17M_6.3X4.5 SF000002Z00 PC506 10U_0805_6.3V6K SW_1.35V 14 +1.35VP +0.675VSP PC501 0.1U_0603_25V7K PQ501 AON7408L_DFN8-5 PL502 1UH_11A_20%_7X7X3_M +1.35VP DH_1.35V C COMMON PART 0.675Volt +/- 5% TDC 0.84A Peak Current 1.2A 1 PC505 10U_0805_25V6K PC504 10U_0805_25V6K EMI@ PC503 2200P_0402_50V7K @EMI@ PC502 0.1U_0402_25V6 BST_1.35V PGOOD B+ Pin19 need pull separate from +1.35VP If you have +1.35V and +0.675V sequence question, you can change from +1.35VP to +1.35VS EMI@ PL501 HCB2012KF-121T50_0805 JUMP_43X118 @ PQ503 2N7002KW_SOT323-3 @ PJ503 +0.675VSP 2 +0.675VS JUMP_43X39 A Compal Electronics, Inc Compal Secret Data Security Classification 2014/03/19 Issued Date Deciphered Date 2015/03/18 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A 1.35VP/0.675VSP A5WAM_Bay Trail M_LA‐B981P Monday, May 12, 2014 Sheet 37 of 47 Rev 0.1 D D EN pin don't floating If have pull down resistor at HW side, pls delete PR2 PR602 10K_0402_1% SPOK SPOK 29,36,39 C 1 C 2 PR603 1M_0402_1% PC602 0.1U_0402_16V7K PL602 1.5UH_PCMC063T-1R5MN_9A_20% SYX198DQNC_QFN10_3X3 FB = 0.6V 2 2 PR609 Rdown 20K_0402_1% 2 @ PR607 0_0402_5% Rup +3VALW PC612 22U_0603_6.3V6M LDO_3V PC611 22U_0603_6.3V6M LDO PC610 22U_0603_6.3V6M PG PC609 22U_0603_6.3V6M BYP ILMT +1.0VALWP PR608 10K_0402_5% +1.0V_PGOOD 2 LX_1.0V PC614 4.7U_0603_6.3V6K FB 10 PC608 330P_0402_50V7K LX TDC 8A @ PR601 PC601 0_0603_5% 0.1U_0603_25V7K 2 BST_1.0V 1 GND PR606 15.4K_0402_1% 1 EN BS ILMT_1.0V +3VALW ILMT_1.0V 10U_0805_25V6K PC607 @ IN PC613 4.7U_0603_6.3V6K @ PR605 0_0402_5% B+_1.0V 10U_0805_25V6K PC604 1 LDO_3V PU601 @EMI@ PC606 0.1U_0402_25V6 EMI@ PC605 2200P_0402_50V7K B+ @EMI@ PR604 @EMI@ PC603 4.7_1206_5% 680P_0603_50V7K 2SNB_1.0V EMI@ PL601 HCB2012KF-121T50_0805 Pin BYP is for CS Common NB can delete The current limit is set to 8A, 12A or 16A when this pin is pull low, floating or pull high B VFB=0.6V Vout=0.6V* (1+Rup/Rdown) Vout=1.062V +1.0VALWP +3VALW and PC614 B 1 PJ601 2 JUMP_43X118 +3VS PR610 2.55K_0402_1% PU602 SY8003DFC_DFN8_2X2 PL603 1UH_2.8A_30%_4X4X2_F +1.05VSP COMMON PART Rup PR614 15K_0402_1% FB_1.05V @ PJ603 +1.05VSP 2 +1.05VS A Rdown PR615 20K_0402_1% 2 Note:Iload(max)=3A @EMI@ PC620 680P_0402_50V7K FB=0.6V JUMP_43X79 A LX_1.05V NC PC619 22U_0603_6.3V6M PGND PC618 22U_0603_6.3V6M LX 10,29,32,37,39 Note:Iload(max)=2.5A EN IN SUSP# PG PC616 22U_0805_6.3VAM FB PC617 68P_0402_50V8J JUMP_43X79 2 2 @ PJ602 +3VALW PGND SGND @EMI@ PR613 4.7_0603_5% @ PR612 1M_0402_5% 2 @ PR611 100K_0402_5% PC615 0.1U_0402_16V7K 1 +1.05VSP_ON +1.0VALW @ Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2014/03/19 Deciphered Date 2015/03/18 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D C DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: 1.05VS/1.0VALW Document Number A5WAM_Bay Trail M_LA‐B981P Sheet Monday, May 12, 2014 38 of 47 Rev 0.1 2 JUMP_43X79 @ PJ701 1 +3VALW Ultra Low Dropout 0.23V(typical) at 3A Output Current D @ PC702 1U_0402_6.3V6K D Rup +1.5VSP @ PJ702 2 +1.5VS JUMP_43X79 PC704 0.01U_0402_25V7K PC705 22U_0603_6.3V6M 2 @ PR702 100K_0402_5% @ PR704 22K_0402_5% FB 1 EN POK +1.5VSP PR703 20K_0402_1% 2 1 Rdown PR705 22.6K_0402_1% 2 PC701 0.15U_0402_10V6K +3VS GND PR701 51K_0402_1% SUSP# SUSP# 10,29,32,37,38 PU701 APL5930KAI-TRG_SO8 VCNTL VOUT VIN VIN VOUT PC703 4.7U_0805_6.3V6K C C +3VALW Vout=0.8V* (1+Rup/Rdown)=1.507V Ultra Low Dropout 0.23V(typical) at 3A Output Current @ PC706 1U_0402_6.3V6K 2 JUMP_43X79 @ PJ703 PU702 APL5930KAI-TRG_SO8 VCNTL VOUT VIN VIN VOUT Rup PJ704 2 +1.8VALW JUMP_43X79 PC709 0.01U_0402_25V7K @ PC710 22U_0603_6.3V6M FB +1.8VALWP EN POK +1.8VALWP PR708 20K_0402_1% @ PR707 100K_0402_5% B GND Rdown PR710 15.8K_0402_1% +3VS PC708 0.1U_0402_16V7K 2 @ PR709 22K_0402_5% SPOK 29,36,38 PR706 20K_0402_1% 1 PC707 4.7U_0805_6.3V6K B Vout=0.8V* (1+Rup/Rdown)=1.81V A A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2014/03/19 2015/03/18 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: 1.5VSP/1.8VALWP A5WAM_Bay Trail M_LA‐B981P Monday, May 12, 2014 Sheet 39 of 47 Rev 0.1 C D @ PC802 1000P_0402_50V7K +CPU_B+ PQ803 PC804 6800P_0402_25V7K PC807 120P_0402_50V8 PC808 470P_0402_50V7K 2 PR803 499_0402_1% PC809 1000P_0402_25V8J 2 2 1 + VGATE 1.91K_0402_1% 29 PR827 +CPU_B+ PQ801 OCP setting=18A MDV1525URH_PDFN33-8-5 PL803 0.36UH_PDME064T-R36MS_24A_20% 1_0402_5% PR833 Cn = L/((Rntcnet*Rsum)/(Rntcnet+Rsum))*DCR) If Cn is correctly selected, when the load current has a square change, the output voltage also has a square response Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2014/03/19 Deciphered Date 2015/03/18 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: B +SOC_VCC 2 PR832 3.65K_0603_1% PC833 1U_0402_16V7K VSUM+ COMMON PART Rds=13.5mΩ(Typ) 16.5mΩ(Max) @EMI@ PC825 @EMI@ PR831 680P_0402_50V7K 4.7_1206_5% PH804 10K_0402_1%_B25/50 3370K PQ802 AON6554_DFN5X6-8-5 2 1 11K_0402_1% PR840 PC830 0.1U_0402_16V7K PR839 280_0402_1% PC829 0.047U_0402_25V7K 1 Close CPU choke VSUM- @ PC834 330P_0402_50V7K PC835 0.01UF_0402_25V7K PC824 2 PR830 2.2_0603_5% 0.1U_0603_25V7K BOOT_CPU LG1_CPU 1 PR842 137K_0402_1% PC831 1000P_0402_25V8J 2 Layout Note 10 VCORE_VSNS SVID routing Alert# signal must be routed between the Clock and Date lines to reduce the cross talk between them Signal order arrangement: mobile order is Clock-Alert-Date 10 VCORE_GSNS SVID spacing requirement is 18mils(0.475mm) Maximum total microstrip routing length of each SVID signal must not exceed 6000mils(152.4mm) The SVID bus must be ground reference, It cannot be referenced to input (Vbat or 12V) power plans as they can couple noise into the SVID bus as power states change Avoid routing under noisy circuit, e.g switch node , Gate driver, B+, Vin, high speed signal When SVID signal changes Layer, GND return path may be changed also We need add GND via for GND reference A PC832 PR838 6800P_0402_25V7K 2K_0402_1% 2 PC828 120P_0402_50V8 PHASE1_CPU PR836 2.61K_0402_1% VSUM+ PR835 66.5K_0402_1% 0.36uH DCR= 1.4+-5% m ohm, Idc~Isat= 16.8~24A UG1_CPU-1 VSUM- PR828 0_0603_5% Height mm 100u_SF000000I80 Height mm 68u_SF000000W00 +3VALWP UG1_CPU PR841 1.78K_0402_1% @ PC822 68U_25V_M 1 BOOT_CPU EMI@ PC821 2200P_0402_50V7K UG1_CPU 17 PHASE1_CPU 18 PC820 10U_0805_25V6K PC819 10U_0805_25V6K 2 1.91K_0402_1% LG1_CPU VDD source use +5VS and PGOOD source use +3VS Please confirm power on and down sequence, make sure VGATE after CPU_CORE on PC827 470P_0402_50V7K 2 PR837 499_0402_1% VSUMG- 2 VSUMG+ 1 PC816 1U_0603_10V6K @PR822 @ PR822 20 EMI@ PL801 FBMA-L11-322513-151LMA50T_1210 B+ @EMI@ PC823 0.1U_0402_25V6 BOOT1 UGATE1 +CPU_B+ 21 19 16 ISEN2 PGOOD PHASE1 COMP NTC FB LGATE1 @ PR819 @PR819 0_0603_5% 22 PC817 1U_0603_10V6K PWM2 VR_HOT# 23 PR821 1_0603_5% COMMON PART Close CPU L/S MOS PR834 2K_0402_1% 1_0402_5% PR815 3.65K_0603_1% PR814 PR817 and PR826 27.4K ohm for 100 degree 61.9K ohm for 110 degree PC826 680P_0402_50V7K +5VALW 25 UGATEG VDD ISL95833BHRTZ-T_QFN32_4X4 SDA PR826 27.4K_0402_1% PH801 470K_0402_5%_B25/50 4700K @EMI@ PC815 @EMI@ PR813 680P_0402_50V7K 4.7_1206_5% 2 1.91K_0402_1% 26 BOOTG PGOODG 29 27 30 28 COMPG FBG RTNG 32 31 ISUMNG ISUMPG ALERT# 24 @PC801 @ PC801 0.1U_0402_16V7K 2 VCCP 15 +5VALW 1 +1.0VS PR829 3.83K_0402_1% PR825 69.8_0402_1% @ 0_0402_5% 2 @ PC818 47P_0402_50V8J 1 PR801 499_0402_1% For VR_HOT#, already pull high at power side PR824 69.8_0402_1% NTC @ PR823 @PR823 LGATEG SCLK 14 VR_HOT# PAD 33 29 UGA_GFX VR_ON 13 VR_SVID_DATA BOOTA_GFX PHASEG RTN VR_SVID_ALERT# PR843 20_0402_1% SVID_ALERT# PR844 16.9_0402_1% SVID_DATA 0_0402_5% +SOC_VNN PL802 0.36UH_PDME064T-R36MS_24A_20% PQ804 AON6554_DFN5X6-8-5 LGA_GFX Rds=13.5mΩ(Typ) 16.5mΩ(Max) NTCG ISUMN COMMON PART 470K_0402_5%_B25/50 4700K VR_ON VR_SVID_CLK 12 2 11 @PR820 @ PR820 29 PR818 3.83K_0402_1% ISUMP PC813 2 BOOTA_GFX PR812 2.2_0603_5% 0.1U_0603_25V7K PC814 1000P_0402_50V7K LGA_GFX PU801 ISEN1 0.36uH DCR= 1.4+-5% m ohm, Idc~Isat= 16.8~24A MDV1525URH_PDFN33-8-5 PHASEA_GFX 10 PR817 27.4K_0402_1% NTCG_1 PH803 +3VALWP PR807 2.05K_0402_1% PR808 2K_0402_1% PR816 Design Note This circuit is for ULV 1+1 17W CPU: IccMax=33A, TDC=16A(TDP NOM) VSUMG+ Loadline: -2.9 m V/A Output Cap follow Intel PDDG 330uF/9m*3, 22uF_0805*12, 2.2uF_0402*16 GFX(GT2): IccMax=33A, TDC=21.5A Loadline: -3.9 m V/A Output Cap follow Intel PDDG 330uF/9m*2, 22uF_0805*6, 10uF_0603*6 , 1uF_0402*11 Close GFX L/S MOS PR809 21K_0402_1% PC812 0.047U_0402_25V7K PC811 0.1U_0402_16V7K PR811 11K_0402_1% PR810 2.61K_0402_1% 2 1U_0402_16V7K PC810 PH802 10K_0402_1%_B25/50 3370K UGA_GFX-1 PHASEA_GFX 1 PR806 137K_0402_1% PR804 0_0603_5% PR805 324_0402_1% UGA_GFX COMMON PART VSUMG- PR802 2K_0402_1% Close GFX choke OCP setting=21A 1 PC805 10U_0805_25V6K PC803 0.01UF_0402_25V7K VGFX_VSNS 10 E Layout Note Reduce Acoustic Noise The AL bulk capacitor of B+ should be very close to CPU_CORE MOSFET Input ceramic caps must place on symmetry same location on top side and bottom side PC806 10U_0805_25V6K B A C D CPU_CORE/GFX_CORE A5WAM_Bay Trail M_LA‐B981P Sheet Monday, May 12, 2014 E 40 of 47 Rev 0.1 PWR Rule SPEC Modify 8/6 3 X 330u/9m(47W) X 330u/9m(37W) 24 pcs 22uF and reserve pcs 2013/08/16 D D +SOC_VNN =+VGFX_CORE +SOC_VCC =+CPU_CORE +SOC_VNN +SOC_VCC Output Cap (330uF*2+22uF*4) PC903 PC904 PC905 PC906 2 2 PC913 PC914 PC915 PC916 Output Cap (330uF*3+22uF*4) 2 2 PC917 330U_D2_2V_Y 330U_D2_2V_Y PC918 + 330U_D2_2V_Y 330U_D2_2V_Y + PC902 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M + PC901 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M + +SOC_VCC Package Edge Cap (22uF*3) C Back Side Cap (10uF*1+4.7uF*2+2.2uF*2) PC929 22U_0603_6.3V6M PC907 22U_0603_6.3V6M PC930 22U_0603_6.3V6M PC908 22U_0603_6.3V6M PC909 PC910 22U_0603_6.3V6M 22U_0603_6.3V6M PC911 PC912 2.2U_0402_6.3V6M 2.2U_0402_6.3V6M +SOC_VNN Package Edge Cap (22uF*3) Back Side Cap (1uF*3) PC920 PC921 PC922 10U_0603_6.3V6M 10U_0603_6.3V6M 22U_0603_6.3V6M PC923 PC924 PC925 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K @ PC927 @ PC928 C 0.1U_0402_16V7K 0.1U_0402_16V7K B B A A Compal Electronics, Inc Compal Secret Data Security Classification 2014/03/19 Issued Date Deciphered Date 2015/03/18 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: CPU/GFX capacitor A5WAM_Bay Trail M_LA‐B981P Sheet Monday, May 12, 2014 41 of 47 Rev 0.1 Module model information TPS51212_V1.mdd for Single layer TPS51212_V2.mdd for Dual layer D VGA_EMI@ PL1001 HCB2012KF-121T50_0805 DRVL VGA@ PR1006 470K_0402_1% +5VALW LG_+1.5VSDGPUP 11 TPS51212DSCR_SON10_3X3 SW_+1.5VSDGPUP VGA@ PC1007 1U_0603_6.3V6M 2 @ TP PC1005 10U_0805_25V6K VGA@ PC1004 10U_0805_25V6K @EMI@ PR1005 4.7_1206_5% PC1010 @EMI@ 680P_0402_50V7K 1.51V +1.5VSDGPUP PC1009 VGA@ 330U_2.5V_M TST V5IN 0.9% VGA@ PL1002 2.2UH_ETQP3W2R2WFN_8.5A_20% SW VFB UG_+1.5VSDGPUP EN @ 2013/10/28 update PL1002 change Common part 7*7*3 SH00000YV00 C RF_+1.5VSDGPUP DRVH VGA@ PR1001 VGA@ PC1001 2.2_0603_5% 0.1U_0603_25V7K 2 BST_+1.5VSDGPUP D B+ 2013/10/28 update PC509 chang Common part SF000006S00 H4.5 + C ESR=15m ohm H=4.5 SF000002Z00 PC1006 0.1U_0402_16V7K FB_+1.5VSDGPUP TRIP 10 VGA@ PQ1002 AON7506_DFN33-8-5 EN_+1.5VSDGPUP VBST VGA_PWROK PR1004 0_0402_5% PGOOD 15,32,43 VGA@ PU1001 VGA@ PR1003 102K_0402_1% 2TRIP_+1.5VSDGPUP2 VGA@ VGA@ PQ1001 AON7408L_DFN8-5 2013/10/20 update Setting OCP PR1003 >102K VGA_EMI@ PC1003 2200P_0402_50V7K @EMI@ PC1002 0.1U_0402_25V6 +1.5VSDGPUP_B+ PR1007 9.31K_0402_1% 2 VGA@ PR1008 10K_0402_1% @ PJ1001 +1.5VSDGPUP B +1.2V +1.05V Switching Frequency: 290kHz Imax=8A OCP~10.5A OVP: 120%~130% VFB=0.704V, Vout=1.207V Switching Frequency: 290kHz Imax=5.4A Ipeak=6.5A Iocp=7.8A OVP: 120%-130% VFB=0.704V, Vout=1.055V Vout PR1007 PR1008 MOSFET: 3x3 DFN H/S Rds(on): 27mohm(Typ), 34mohm(Max) L/S Rds(on): 22mohm(Typ), 13.5mohm(Max) 11.5k 10k +1.35V 9.31k 10k +1.2V 7.15K 10k 105K +1.05V 4.99k 10k 93.1k 2 +1.5VSDGPU B JUMP_43X118 Choke: 7x7x3 Rdc=15.5mohm +/-15% Switching Frequency: 290kHz Ipeak=10A Delta I =2.16A Iocp=12.14~16.67A OVP: 120%~130% VFB=0.704V, Vout=1.51V PR1003 +1.5V JUMP_43X118 @ PJ1002 2 A A Compal Electronics, Inc Compal Secret Data Security Classification 2014/03/19 Issued Date Deciphered Date 2015/03/18 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: 1.5VSDGPUP A5WAM_Bay Trail M_LA‐B981P Sheet Monday, May 12, 2014 42 of 47 Rev 0.1 A B C Vboot=Vvref*Rref2/(Rref1+Rref2+Rboot) Current Limit threshold setting Rocset= (Ivalley * Rds(on) + 40 mV) / 10uA Rt=Rrefadj // (Rboot+Rref2) Vmin= Vvref*[Rref2/(Rref2+Rboot)]*[Rt/(Rref1+Rt)] Vout=Vmin+N*Vstep OCP=54A/2=27A per phase Ivalley=27A-7.811A/2=23.1A Vstep=(Vmax-Vmin)/Nmax PWM-VID Spec and component Values Config B Config C Config D Vmin 0.6V 0.65V 0.9V Vmax 1.2V 1.15V 1.15V Vboot 0.9V 0.9V 1.028V Voltage step 6.25mV 25mV 12.5mV N of Voltage level 96 20 20 PWM-VID Spec Rrefadj PR1206 20K 39K 27K Rref1 PR1204 20K 30K 7.5K Rboot PR1205 2K 3K Rref2=PR1209 +PR1212 PR1209 18K 24K 6.2K PR1212 3K 1.74K C PC1209 1.8nf N15V-GL C=3*330uF (9mohm)=990uF Vripple=Iripple*ESR(min)=7.811A*3mohm=23.4mV 5.6nf @VGA@ PR1202 1K_0402_5% DGPU_VID N14P-LP Config B Config B Config B Rated TDP Power at Tj=102C 18W 25W 18W 13W 18.9W 25W 25.6W 35.5W 18W 18.16W Boosted GPU Total at Tj=102C 25W 32W 25W 20W 23W N/A 30W 40W 25W 24.72W EDP-Continuous at Tj=102C 24A 32A 26A 22A 25A 27A 38A 45A 31A 29.2A EDP-Peak at Tj=102C 35A 55A 45A 35A 35A 40A 60A 75A 60A 44.3A Istep max (Evaluation) 15A 27A 25A 20A 14A 12A 31.5A 35A OCP Setting Current 42A 66A 54A 42A 42A 48A 72A 90A 72A 54A Rocset 8.96K 12.45K 10.7K 8.96K 8.96K 9.83K 8.3K 9.39K 13K 10.2K N14P-GE Config B Operation phase Number PSI Voltage setting phase with DEM 0V to 0.8V phase with CCM 1.2V to 1.8V Active phase with CCM 2.4V to 5.5V 2phase 1H1L 2phase 1H1L 2phase 1H1L 2phase 1H2L 2phase 1H2L 2phase 1H1L 2phase 1H1L Polymer Cap (330uF) 6mohm * 9mohm * 9mohm * 6mohm * 6mohm * 6mohm * 6mohm * (L=0.22uH) 4.5mohm * (L=0.15uH) Or OSCON (390uF) 10mohm * 10mohm * 10mohm * 10mohm * 10mohm * 10mohm * 32 PC1207 VGA@ 0.22U_0603_25V7K VGA@ PR1223 0_0603_5% U2_UGATE1 Reserve Location VGA@ VGA@ PC1210 0.1U_0402_25V6 U2_BOOT1 U2_UGATE1 GPU_VID GM@ PC1209 5600P_0402_25V7K GPU_EN C DGPU_PWR_EN VGA@ PQ1201 VGA@ PR1233 2.2_0603_5% U2_BOOT1 PL1202 113.4C U2_PHASE2 GL@ PR1217 10.2K_0402_1% @VGA_EMI@ PC1211 680P_0603_50V7K 1 Rocset U2_LGATE2 19 GM@ PR1217 10.2K_0402_1% AON6554_DFN5X6-8-5 BOOT2 UGATE2 18 PGOOD 17 U2_BOOT2 20 GT@ PR1217 13K_0402_1% EN BOOT1 UGATE1 RT8813AGQW_WQFN24_4X4 VGA@ PR1232 0_0603_5% VGA@ VGA@ PQ1204 +5VS VGA_PWROK PL1203 +VGA_CORE 0.22UH 20% FDUE0640J -H 25A U2_PHASE2 15,32,42 U2_LGATE2 VGA@ PR1226 2.2_0603_5% @VGA@ PR1222 10K_0402_1% +3VS VGA@ PC1218 10U_0805_25V6K 2 VGA@ PC1214 0.22U_0603_25V7K AON6552_DFN5X6-8-5 PQ1203 VGA@ PC1222 10U_0805_25V6K VGA@ @VGA_EMI@ PC1215 0.1U_0402_25V6 PR1219 2.2_0603_5% U2_BOOT21 VGA_EMI@ PC1203 2200P_0402_50V7K GPU_B+ VGA@ PSI VID VCC/ISNE1 U2_PWM3 U2_PWM3 110C +VGA_CORE @VGA_EMI@ PR1231 2013/12/13 4.7_1206_5% 106.38C U2_LGATE1 22 21 AON6554_DFN5X6-8-5 PR1221=13K +VGA_CORE EDP-Continuous 31A EDP-Peak 60A OCP 72A update PL1202 PL1203 change to Common part SH000011H00 103.1C 23 @VGA_EMI@ PR1227 4.7_1206_5% @VGA_EMI@ PC1220 680P_0603_50V7K VGA@ PR1225 +3VS 1 T_max 100C U2_LGATE1 100K_0402_1% T_typical 96.73C U2_PHASE1 U2_UGATE2 VGA@ PH1201 470K_0402_5%_TSM0B474J4702RE T_min PR1221=18.7K 2013/10/28 update PH1201 chang Common part SL200002E00 Thermal monitoring: (VGPU_VREF-VTSNS)/PR23=VTSNS/Rth PHASE2 24 GPU_VREF VSNS Soft-Start time (Internal) is 0.7ms (PC1213 un-pop) Tss=(Css*Vrefin)/Iss+2.3ms =0.01U*0.9V/5uA+2.3ms=4.1ms (PC1213 pop) Switching frequency setting: Fsw=(Vin-0.5)/(2*Vin*Rton*3.2p)=304.89Khz U2_UGATE2 GPU_TSNS/ISEN3 PR1228 100_0402_1% LAGTE2 16 @VGA@ PC1213 0.01U_0402_16V7K 13 Css SS 25 VSNS PVCC VGA@ PR1221 18.7K_0402_1% VGA@ RGND GND GPU_FB LGATE1 GND/PWM3 VGA_PWROK 12 REFADJ GPU_COMP PHASE1 TON TALERT/ISEN2 11 @VGA@ PC1212 47P_0402_50V8J VGA@ PQ1202 VREF TSNS/ISEN3 15 10 GPU_DSBL/ISEN1 GPU_TON REFIN 14 GPU_VREF 0_0402_1% +VGA_CORE GPU_REFIN GPU_HOT# VCCSENSE_VGA PR1201 365K_0402_1% VGA@ PC1219 1U_0402_6.3V6K 17 VGA@ PC1221 1U_0402_6.3V6K Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2014/03/19 Deciphered Date 2015/03/18 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B+ U2_PHASE1 GPU_FBRTN @VGA@ PR1235 GM@ 0.22UH 20% FDUE0640J -H 25A GPU_FBRTN @VGA@ PC1201 0.01UF_0402_25V7K VGA@ PR1215 100_0402_1% GT@ NULL VGA_EMI@ PL1201 HCB2012KF-121T50_0805 15 VGA@ PR1238 15K_0402_1% GPU_PSI 2 GT@ PC1209 2700P_0402_50V7K 1 NULL VGA@ PC1206 10U_0805_25V6K PSI GL@ PC1209 1800P_0402_50V7K VSSSENSE_VGA Config C 15 PSI Pull high on HW side PR1207 GPU_REFADJ @VGA@ VGA@ 17 N15V-GM 2phase 1H1L Rton N15S-GT Config B 2phase 1H1L VGA@ PC1205 10U_0805_25V6K Rrefadj GT@ PR1234 20K_0402_1% VGA@ PU1201 GPU_B+ N14P-GT Config B 2phase 1H1L 0_0402_1% @VGA@ PC1208 0.01U_0402_16V7K GT@ PR1209 18K_0402_1% GT@ PR1237 0_0402_5% Rref2 @VGA@ PR1214 0_0402_1% N14P-GS Config B Recommendation VGA_EMI@ PC1204 2200P_0402_50V7K GT@ PR1211 20K_0402_1% GT@PR1208 GT@PR1208 2K_0402_5% GL@ PR1237 3K_0402_1% N14M-LP Config B N14P-GV2 @VGA_EMI@ PC1216 0.1U_0402_25V6 1 Rref1 Rboot GM@ PR1237 1.74K_0402_1% N14M-GS Config B GPU_B+ @VGA@ PR1203 0_0402_1% GM@ PR1208 GL@ PR1208 VGA@ 0_0402_5% 3K_0402_1% PC1202 1U_0402_6.3V6K GL@ PR1209 24K_0402_1% N14P-GV OpenVReg Configurations +3VS GM@ PR1234 27K_0402_1% GL@PR1234 GL@PR1234 39K_0402_1% GM@ PR1209 6.2K_0402_1% L-side MOS:AON6554 Rds(on): 3.2mohm@Vgs=10V 3~3.8mohm@Vgs=4.5V Id :85A@Ta=25 degC Choke: 0.22uH (Size:7*7*4) Rdc=0.97mohm +-5% Heat Rating Current=34A Saturation Current=25A N15V-GM GM@ PR1211 GL@ PR1211 7.5K_0402_1% 30K_0402_1% PWM VID and Output voltage control 1.Boot mode 2.Standby mode (don't support) 3.Normal mode 2.7nf N15S-GT H-side MOS:AON6552 Rds(on): 5.6mohm@Vgs=10V 6.7mohm@Vgs=4.5V Id :20A@Ta=25 degC VGA Chip Different VGA Chip (different EDP-Peak Current) need select different solution I_ripple=(19-0.9)*0.9/ (304.89Khz*0.36u*19)=7.811A Vmax=Vvref*Rref2/[(Rref1//Rrefadj)+Rboot+Rref2] E AON6552_DFN5X6-8-5 Module model information: RT8813A_V1A for IC module RT8813A_V1B for SW module D B C D +VGA_CORE A5WAM_Bay Trail M_LA‐B981P Sheet Monday, May 12, 2014 E 43 of 47 Rev 0.1 +VGA_CORE VGA@ PC1314 4.7U_0603_6.3V6K + + VGA@ PC1346 4.7U_0805_6.3V6K 2 VGA@ PC1338 1U_0402_6.3V6K VGA@ PC1337 1U_0402_6.3V6K VGA@ PC1336 1U_0402_6.3V6K VGA@ PC1335 1U_0402_6.3V6K PC1328 @ 22U_0603_6.3V6M PC1327 VGA@ 22U_0603_6.3V6M PC1326 @ 22U_0603_6.3V6M N15x2013/10/17 Under 4.7uF_0603_15pcs 1uF_0402_8pcs Near 47uF_0805_0pcs 22uF_0603_9pcs(2PCS unpop) 4.7uF_0805_5pcs Near VGA Core C N15x 2013/12/10 Under 4.7uF_0603_10pcs 1uF_0402_4pcs Near 47uF_0805_1pcs 22uF_0603_1pcs(2PCS unpop) 4.7uF_0805_5pcs +VGA_CORE VGA@ PC1304 560U_2.5V_M + VGA@ @ PC1303 330U_D2_2V_Y D PC1302 560U_2.5V_M VGA@ PC1313 4.7U_0603_6.3V6K VGA@ PC1312 4.7U_0603_6.3V6K VGA@ PC1311 4.7U_0603_6.3V6K VGA@ PC1310 4.7U_0603_6.3V6K VGA@ PC1309 4.7U_0603_6.3V6K VGA@ PC1308 4.7U_0603_6.3V6K VGA@ PC1307 4.7U_0603_6.3V6K Under VGA Core VGA@ PC1306 4.7U_0603_6.3V6K 1 D VGA@ PC1305 4.7U_0603_6.3V6K +VGA_CORE C N15x2013/10/07 Under 4.7uF_0603_15pcs 1uF_0402_8pcs Near 47uF_0805_0pcs 22uF_0805_9pcs(2PCS unpop) 4.7uF_0805_5pcs B N14x Under 4.7uF_0603_10pcs 0.1uF_0402_4pcs Near 47uF_0805_1pcs 22uF_0805_1pcs 4.7uF_0805_5pcs VGA@ PC1345 4.7U_0805_6.3V6K VGA@ PC1344 4.7U_0805_6.3V6K VGA@ PC1343 4.7U_0805_6.3V6K VGA@ PC1342 4.7U_0805_6.3V6K 2 B VGA@ PC1341 47U_0805_6.3V6M N15x2013/10/02 Under 4.7uF_0603_15pcs 1uF_0402_8pcs Near 47uF_0805_0pcs 22uF_0805_14pcs 4.7uF_0805_5pcs A A Compal Electronics, Inc Compal Secret Data Security Classification 2014/03/19 Issued Date Deciphered Date 2015/03/18 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: VGA_CORE CAP A5WAM_Bay Trail M_LA‐B981P Sheet Monday, May 12, 2014 44 of 47 Rev 0.1 Version change list (P.I.R List) Item D Fixed Issue Reason for change Rev PG# Page of for PWR Modify List Date Phase D CPU tranistion 40 PR839 change to 280 ohm 4/9 DVT NV power sequence 43 PR1222 VGA@->@VGA@ 4/9 DVT PR1238 0->15K_0402_1% 4/9 DVT PC1210 pop 0.1U(SE00000G880) 4/9 DVT PR1007 change to 9.31K 4/23 PVT PR607 change to R-Short 0402 4/23 PVT PR601 change to R-Short 0603 4/23 PVT For EMI test 42 unused part 38 10 For voltage adjust 36 PR407 change to R-Short 0603 4/23 PVT 38 PR606 change to 15.4K 5/6 PVT 11 C 12 C 13 14 15 16 17 18 B B A A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2014/03/19 2015/03/18 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: PWR_PIR A5WAM_Bay Trail M_LA‐B981P Sheet Monday, May 12, 2014 45 of 47 Rev 0.1 Version Change List ( P I R List ) Item Page# D Function P.6/8/28/32 Date Request Owner Page 1/1 for HW Issue Description Solution Description Fix S3/S5 have pluse at singal Rev U63.5/U58.5/U53.5/U62.5/U64.5 change power source from +1.8VS to +1.8VALW HW 5/8 P.8/15/29 HW 5/8 P.31 HW 5/8 P.29 HW 5/8 Change EC version to latest change EC U28 to SA000075S30(KB9022QD) R506 change from 130K->160K_0402_1%(SD034160380) P.9 HW 5/8 Add for Debug ADD ADD ADD ADD Change R-short for cost down EMI D R236,R237 change to R-Short 0805 R1044 change to R-Short 0402 R1015 change to R-Short 0402 Request from EMI add Bead at speaker C R1094/R1095/R1096/R1097 change from 0ohm to BEAD(SM01000CC00) 0.2 R973 0_0402_5%(@) at USB_HUB reset (connect to SYSON) R1176/R1173 0_0402_5% for DGPU_PWR_EN_SOC1.8V R1175/R1174 0_0402_5% for DGPU_HOLD_RST#_SOC1.8V JP2@ R1081@ R1082@(for debug) P.15 HW 5/8 Add PH resistor P.11 HW 5/8 change cap to improve +1.0VS power rail C1056 C1057 C1059 change footprint from 22U_0805->0603 P.4 HW 5/8 Update DA P/N C R1043 change from 0ohm->10K_0402_5% unpop R2018(DGPU_HOLD_RST#_SOC1.8V) PH resistor DA P/N change to DA60019D000 B B A A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2014/03/19 2015/03/18 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: HW P.I.R (1/3) A5WAM_Bay Trail M_LA‐B981P Sheet Monday, May 12, 2014 46 of 47 Rev 0.1 Z5WE3_DVT Power Sequence AC mode 2013-08-08 BIOS:v0.05 EC:v0.05 G3->S0 S0->S3 S3->S0 S0->S5 ACIN ACIN +3VLP +3VLP EC_ON EC_ON 1.53ms +3VALW 1.58ms D +5VALW +5VALW SPOK SPOK 7.28ms +1.0VALW 8.23ms +1.0VALW +1.8VALW +1.8VALW ON/OFF ON/OFF 95.38ms EC_RSMRST# 101ms EC_RSMRST# PBTN_OUT# 101ms PBTN_OUT# 102ms EC_SLP_S4# EC_SLP_S4# 102ms EC_SLP_S3# EC_SLP_S3# 204ms 222ms SYSON C D +3VALW SYSON 0.6ms +1.35V 3.29ms +1.35V 3.29ms DDR_PWROK C 1.71ms 33.68ms DDR_PWROK 21ms 36.20ms 22.32ms VR_ON VR_ON 2.49ms 2.50ms 8.85ms +SOC_VCC 2.50ms +SOC_VCC 11.5ms +SOC_VNN 2.50ms 10.55ms +SOC_VNN 9.81ms 0.28ms 279us VGATE VGATE 42.56ms 263ms 5.57ms 11.71ms SUSP# 31.28us +1.0VS 2.18ms 1.30ms 1.52ms 1.84ms 2.8ms 2.11ms 2.08ms 16.59ms 3.77ms 4.41ms +3VS 12.83ms 12.77ms +0.675VS 19.60ms 19.61ms 49.83ms 49.87ms KBRST# 148.3ms 144ms KBRST# 110ms 110ms PMC_CORE_PWROK 11.71ms PMC_CORE_PWROK 110ms 110ms DDR_CORE_PWROK 11.71ms DDR_CORE_PWROK 116ms 584ms B +5VS 20.27ms 20.48ms +0.675VS +1.8VS 15.34ms 4.41ms B +5VS 16.63ms 3.77ms 15.31ms +3VS +1.5VS 10.71ms 10.71ms +1.8VS +1.35VS 8.12ms 2.79ms +1.5VS +1.05VS 1.83ms 8ms +1.35VS +1.0VS 1.29ms 1.56ms +1.05VS SUSP# 31.12us 2.56ms 116ms PMC_PLTRST# SUSP# 8.8ms PMC_PLTRST# 2.38ms A A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2014/03/19 Deciphered Date 2015/03/18 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D C DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: Power Sequence Document Number A5WAM_Bay Trail M_LA‐B981P Sheet Monday, May 12, 2014 47 of 47 Rev 0.1 ... A5WAM_Bay Trail M _LA? ? ?B981P Date: Sheet Monday, May 12, 2014 25 of 47 A B C D E LAN Connector JRJ1 T210 25 25 LAN_MIDI2LAN_MIDI2+ LAN_MIDI2LAN_MIDI2+ LAN_MIDI1LAN_MIDI1+ LAN_MIDI1LAN_MIDI1+ LAN_MIDI0LAN_MIDI0+... 26 LAN_MIDI0+ LAN_MIDI0LAN_MIDI1+ LAN_MIDI1LAN_MIDI2+ LAN_MIDI2LAN_MIDI3+ LAN_MIDI3- 23 24 PLT_RST_BUF# LAN_CLKREQ# 30 29 PCIE_PRX_C_DTX_P3 PCIE_PRX_C_DTX_N3 25 26 21 22 LAN_MIDI0+ LAN_MIDI0LAN_MIDI1+... Manahement/Isolation ISOLATEB LAN_PME# RS@ 29 R1124 EC_PME# 0_0402_5% 31 39 ISOLATEBPIN LANWAKEB PCI-Express 8 15,26,29,30,8 C1228,C1230 Place near Pin 25,26 C 7 7 CLK_PCIE_LAN CLK_PCIE_LAN# PLT_RST_BUF# LAN_CLKREQ#