Acer aspire e5 474g compal LA c611p rev 1 0 схема

A B C D E 1 Compal Confidential 2 A4WAS MB Schematic Document LA-C611P 3 Rev: 1.0 2015.07.17 4 DAX Part Number DAZ1DR00100 A4WAS_PCB_REV10 Description Compal Secret Data Security Classification PCB A4W AS LA-C611P LS-C341P 2014/11/10 Issued Date Deciphered Date 2016/11/10 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Cover Sheet Size Document Number Custom B C D Rev 1.0 A4WAS M/B LA-C611P Date: A Compal Electronics, Inc Sheet Friday, July 17, 2015 E of 60 A B VGA C D E eDP HDMI Conn Fan Control page 41 Interleaved Memory page 32 page 29 DP to VGA Realtek RTD2168 eDP Intel Skylake U DDI2 DP x lanes HDMI x lanes DDI WLAN USB port page 35 PCIe 3.0 x4 8GT/s port port 1-4 PCIe 1.0 2.5GT/s port LAN(GbE)/ Card Reader Realtek 8411B Card Reader in (SD) CMOS Camera USB port 1,2 USB/B (port 3) USB port SATA3.0 6.0 Gb/s 6.0 Gb/s port (SATA0) page 37 USBx8 port (SATA1) 15W 1356pin BGA LPC/eSPI BUS page 36 ENE KB9022 page 34 3.3V 24MHz Touch Screen ALC255 SPI SPI ROM x2 CLK=24MHz page 34 page 29 I2C (PORT1) HDA Codec page 06~17 page 36 page 37 48MHz HD Audio SATA CDROM Conn RJ45 conn RTC CKT USB 2.0 conn x1 Dual Core + GT2 SATA3.0 SATA HDD Conn page 19 USB 3.0 conn x2 Flexible IO page 33 204pin DDR3L-SO-DIMM X1 Processor page 20~28 PCIe 1.0 2.5GT/s BANK 4, 5, 6, Skylake U Skylake PCH-LP(MCP) (SKL-U_2+2) Nvidia N16x with DDR3 x4 1.35V DDR3L 1333/1600 page 30 DDI1 page 18 BANK 0, 1, 2, Dual Channel HDMI PS8407A page 31 NGFF 204pin DDR3L-SO-DIMM X1 Memory BUS Int Speaker page USB port page 29 page 40 page 40 UAJ on Sub/B Int MIC page 40 page 37 TPM page 38 page 39 Sub Board page 14 Power On/Off CKT Int.KBD LS-C341 USB+Audio/B Touch Pad PS2 (from EC) / I2C (from SOC) page 37 page 39 page 39 page 39 DC/DC Interface CKT page 42 Compal Electronics, Inc Compal Secret Data Security Classification Power Circuit DC/DC 2014/11/10 Issued Date Deciphered Date 2016/11/10 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC page 43~55 Title Date: A B C D Block Diagrams Size Document Number Custom A4WAS M/B LA-C611P Tuesday, June 16, 2015 Sheet E Rev 1.0 of 60 A B C D Board ID Table for AD channel Vcc Ra Board ID 1 3.3V +/- 5% 100K +/- 5% Rb 12K +/- 1% 15K +/- 1% 20K +/- 1% 27K +/- 1% 33K +/- 1% 43K +/- 1% 56K +/- 1% BOARD ID Table Power State V BID 0.347 0.423 0.541 0.691 0.807 0.978 1.169 V V V V V V V V V BID typ V 0.345 V 0.430 V 0.550 V 0.702 V 0.819 V 0.992 V 1.185 V V BID max 0.300 V 0.360 V 0.438 V 0.559 V 0.713 V 0.831 V 1.006 V 1.200 V EC 0x00 0x0C 0x1D 0x27 0x31 0x3C 0x47 0x55 AD3 - 0x0B - 0x1C - 0x26 - 0x30 - 0x3B - 0x46 - 0x54 - 0x64 SIGNAL STATE E SLP_S3# SLP_S4# SLP_S5# S0 (Full ON) HIGH S3 (Suspend to RAM) S4 (Suspend to Disk) S5 (Soft OFF) +VALW +V +VS Clock HIGH HIGH ON ON ON ON LOW HIGH HIGH ON ON OFF OFF LOW LOW HIGH ON OFF OFF OFF LOW LOW LOW ON OFF OFF OFF Board ID PCB Revision 0.1 0.2 0.3 1.0 BOM Structure Table BOM Option Table BOM Structure Item Unpop @ Connector CONN@ EMC requirement EMC@ EMC requirement depop @EMC@ CODEC(ALC255) 255@ CODEC(ALC283) 283@ SPI ROM 8M*2 8M_DUAL@ 8M_SINGLE@ SPI ROM 8M*1 UMA@ UMA only TPM TPM@ For Intel CMC CMC@ For ES Sampel Only ES@ Keyboard backlight KB@ LPC MODE for EC LPC@ ESPI MODE for EC ESPI@ BA Serial BA@ EA Serial HDD@ Item dGPU N16S-GT N16V-GM SKU GPU CG6 / Non GC6 VRAM BOM Select SR@/DR@ Memory Door/ No Memory Door MDY@/ MDN@ DMIC*1 DMIC*2 For Acer IOAC No Acer IOAC CPU Code Device Reserved (Touch Panel) TM-P2969-001 (TP) SB8787-1200 (TP-ELAN) DIMM1 DIMM2 LIS3DHTR(G-Sensor) N16S-GT (VGA) PCH-LP (SOC) BQ24780 (Charger IC) BATTERY PACK I2C_0 (+3VS) I2C_1 (+3VS) SOC_SMBCLK +3VS SOC_SML1CLK +3VS EC_SMB_CK1 +3VLP BOM Structure VGA@ SGT@ VGM@ NGC6@ / GC6@ X76@/X7601@ ~ X7614@ Single/Dual Rank 1DMIC@ 2DMIC@ IOAC@ NIOAC@ PreES:QH7Y@ ES:QHMF@, QHMG@ QS:QJFC@, QJ8N@, QJ8L@ MP:SR2EU@, SR2EY@, SR2EZ@ I2C Address Table BUS Voltage Rails BOM Option Table Address(7 bit) Address(8bit) Write 0x2C 0x15 0xA0 0xA4 0x30 0x9E 0x90 0x12 0x16 Read Power Plane Description S0 S3 +19V_VIN Adapter power supply N/A N/A S4/S5 N/A +17.4V_BATT Battery power supply N/A N/A N/A +19VB AC or battery power rail for power circuit N/A N/A N/A +VCC_CORE Processor IA Cores Power Rail ON OFF OFF +VCC_GT Processor Graphics Power Rails ON OFF OFF +VCC_SA System Agent power rail ON OFF OFF +0.675VS_VTT DDR +0.675VS power rail for DDR terminator ON OFF OFF +1.0VALW_PRIM +1.0V Always power rail ON ON ON*1 +1.0V_VCCSTU Sustain voltage for processor in Standby modes ON ON OFF +VCCIO CPU IO power rail ON OFF OFF +1.0VS_VCCSTG +1.0VALW_PRIM Gated version of VCCST ON OFF OFF +1.35V_VDDQ DDRIIIL +1.35V Power Rail ON ON OFF +1.8VALW_PRIM +1.8V Always power rail ON ON ON*1 +1.8VS System +1.8V power rail ON OFF OFF +3VLP +19VB to +3VLP power rail for suspend power ON ON ON +3VALW System +3VALW always on power rail ON ON ON*1 +3VS System +3V power rail ON OFF OFF +5VALW +5V Always power rail ON ON ON +5VS System +5V power rail ON OFF OFF +RTCVCC RTC Battery Power ON ON ON +1.05VSDGPU +1.05VS power rail for GPU ON OFF OFF +1.5VSDGPU +1.5VS power rail for GPU ON OFF OFF +3VSDGPU_AON +3VS power rail for GPU(AON rails) ON OFF OFF +3VSDGPU_MAIN +3VS power rail for GPU GC62.0 ON OFF OFF +VGA_CORE Core power for descrete GPU ON OFF OFF Note : ON*1 means power plane is ON only when WOL enable and RTC wake at BIOS setting, otherwise it is OFF 4 Compal Secret Data Security Classification Issued Date 2014/11/10 Deciphered Date 2016/11/10 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Size Document Number Custom B C D Rev 1.0 A4WAS M/B LA-C611P Date: A Compal Electronics, Inc Notes List Thursday, July 16, 2015 Sheet E of 60 D D C C B B A A Compal Secret Data Security Classification 2014/11/10 Issued Date Deciphered Date 2016/11/10 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Power Map Re v 1.0 A4WAS M/B LA-C611P Date: Compal Electronics, Inc Size Document Number Custom Thursday, July 16, 2015 Sheet of 60 A B C D E PWR Sequence_SKL-U2+2_DDR3L_NON CS +RTCVCC tPCH01_Min : ms SOC_RTCRST# +19VB +3VLP 1 EC_ON tPCH04_Min : ms +5VALW/+3VALW(+3VALW_DSW ) SPOK tPCH34_Max : 20 ms tPCH06_Min : 200 us (+3VALW stable (@95% of full value) to +1.0VALW_PRIM starting to ramp) +1.8VALW_PRIM +1.8VALW_PG +VCCPRIM_CORE/+1.0VALW_PRIM tPCH03_Min : 10 ms EC_RSMRST# ON/OFF tPCH43_Min : 95 ms PBTN_OUT# Minimum duration of PWRBTN# assertion = 16mS PWRBTN# can assert before or after RSMRST# PM_SLP_S5# tPCH18_Min : 90 us ESPI_RST# PM_SLP_S4# SYSON +1.0V_VCCSTU +1.35V_VDDQ PM_SLP_S3# SUSP# tCPU04 Min : 100 ns +1.0VS_VCCSTG tCPU10 Min : ms +VCCIO 3 +5VS/+3VS/+1.8VS/+1.5VS tCPU00 Min : ms EC_VCCST_PG VR_ON tCPU19 Max : 100 ns SM_PG_CTRL tCPU18 Max : 35 us +0.675VS_VTT tCPU09 Min : ms +VCC_SA VR_PWRGD tCPU16 Min : ns tPLT05 Min : Platform dependent PCH_PWROK (SYS_PWROK) H_CPUPWRGD PLT_RST# 4 +VCC_CORE / +VCC_GT Compal Secret Data Security Classification 2014/11/10 Issued Date Deciphered Date 2016/11/10 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Power Sequence Size Document Number Custom B C D Rev 1.0 A4WAS M/B LA-C611P Date: A Compal Electronics, Inc Sheet Thursday, July 16, 2015 E of 60 A B C UC1A Functional Strap Definitions DDPB_CTRLDATA/ GPP_E19 (Internal Pull Down): DDPC_CTRLDATA/ GPP_E21 (Internal Pull Down): DDPD_CTRLDATA/ GPP_E23 (Internal Pull Down): (Sampled:Rising edge of PCH_PWROK) Display Port B/C/D Detected =Port is not detected =Port is detected 31 31 31 31 SOC_DP1_N0 SOC_DP1_P0 SOC_DP1_N1 SOC_DP1_P1 30 30 30 30 30 30 30 30 SOC_DP2_N0 SOC_DP2_P0 SOC_DP2_N1 SOC_DP2_P1 SOC_DP2_N2 SOC_DP2_P2 SOC_DP2_N3 SOC_DP2_P3 E55 F55 E58 F58 F53 G53 F56 G56 C50 D50 C52 D52 A50 B50 D51 C51 R4955 EDP_COMP 24.9_0402_1% N7 N8 Reserved CATERR# for sightings issue check 38 @ T166 H_PECI 499_0402_1% RC4 @ T160 @ T161 R615 +3VS 100K_0402_5% SPI touch INT follow CRB CC52 @EMC@ 1U_0402_16V7K H_PECI 38,39 for ESD 29 D22 RB751V-40_SOD323-2 EC_TP_INT# RC137 RC5 RC6 RC7 RC8 PDG0.9 P.771 PROC_POPIRCOMP/PCH_OPIRCOMP PD 50ohm CC53 @EMC@ 1U_0402_16V7K H_PROCHOT#_R Reserved DDI EDP_AUXN EDP_AUXP EDP EDP_DISP_UTIL DDI1_AUXN DDI1_AUXP DDI2_AUXN DDI2_AUXP DDI3_AUXN DDI3_AUXP GPP_E13/DDPB_HPD0 GPP_E14/DDPC_HPD1 GPP_E15/DDPD_HPD2 GPP_E16/DDPE_HPD3 GPP_E17/EDP_HPD GPP_E20/DDPC_CTRLCLK GPP_E21/DDPC_CTRLDATA GPP_E22/DDPD_CTRLCLK GPP_E23/DDPD_CTRLDATA EDP_BKLTEN EDP_BKLTCTL EDP_VDDEN OF 20 EDP_RCOMP EDP_TXN0 EDP_TXP0 EDP_TXN1 EDP_TXP1 EDP_TXN2 EDP_TXP2 EDP_TXN3 EDP_TXP3 E45 F45 EDP_AUXN EDP_AUXP 29 29 29 29 29 29 29 29 29 29 B52 G50 F50 E48 F48 G46 F46 SOC_DP1_AUXN SOC_DP1_AUXP L9 L7 L6 N9 L10 SOC_DP1_HPD SOC_DP2_HPD R12 R11 U13 ENBKL SOC_BKL_PWM SOC_ENVDD SOC_DP1_AUXN SOC_DP1_AUXP 31 31 DP Aux (Port B for VGA) EC_SCI# SOC_DP1_HPD SOC_DP2_HPD EC_SCI# CPU_EDP_HPD EC_SCI# 38 CPU_EDP_HPD 31 30 From VGA Trans From HDMI 29 +3VS RC212 10K_0402_5% @ EC_SCI# SOC internal PU From eDP ENBKL 38 SOC_BKL_PWM 29 29 SOC_ENVDD XDP_BPM#0 XDP_BPM#1 C55 D55 B54 C56 I2C_TS_INT# I2C_TS_INT# I2C_TS_INT# TP_INT# @ 2 2 0_0402_5% 49.9_0402_1% 49.9_0402_1% 49.9_0402_1% 49.9_0402_1% #545659 PCH EDS 0.7 P.108 SCI capability is available on all GPIOs, while NMI and SMI capability is available on selected GPIOs only Below are the PCH GPIOs that can be routed to generate SMI# or NMI: ‧ GPP_B14, GPP_B20, GPP_B23 ‧ GPP_C[23:22] ‧ GPP_D[4:0] ‧ GPP_E[8:0], GPP_E[16:13] SKL-U Rev_0.53 D63 A54 C65 C63 A65 A6 A7 BA5 AY5 CPU_POPIRCOMP AT16 PCH_OPIRCOMP AU16 EDRAM_OPIO_RCOMP H66 EOPIO_RCOMP H65 #544669 CRB RVP7 1.0 EDRAM_OPIO_RCOMP/EOPIO_RCOMP PD50ohm 2014/9/17 GPP_E18/DDPB_CTRLCLK GPP_E19/DDPB_CTRLDATA UC1D H_CATERR# H_PECI H_PROCHOT#_R H_THERMTRIP# TP_INT# 100K_0402_5% DDI2_TXN[0] DDI2_TXP[0] DDI2_TXN[1] DDI2_TXP[1] DDI2_TXN[2] DDI2_TXP[2] DDI2_TXN[3] DDI2_TXP[3] C47 C46 D46 C45 A45 B45 A47 B47 SKL-U_BGA1356 @ H_PROCHOT# 38,45 E52 +1.0VS_VCCSTG +3VS SOC_DP2_CTRL_CLK SOC_DP2_CTRL_DATA N11 N12 RC3 1K_0402_5% RC157 SOC_DP1_CTRL_DATA EDP_COMP H_THERMTRIP# 1K_0402_5% 1 2.2K_0402_5% SOC_DP2_CTRL_CLK SOC_DP2_CTRL_DATA L13 L12 SPI touch RST follow CRB #544669 P.8 #543016 PDG0.9 P.753 PH 1K to VCCST CPU over 130 degree will output low force S0->S5 RC2 30 30 HDMI DDC (Port C) #543016 PDG0.9 P.186 Trace width=20 mils,Spacing=25mil,Max length=100mils +1.0V_VCCST EDP_TXN[0] EDP_TXP[0] EDP_TXN[1] EDP_TXP[1] EDP_TXN[2] EDP_TXP[2] EDP_TXN[3] EDP_TXP[3] DISPLAY SIDEBANDS +VCCIO SKL-U DDI1_TXN[0] DDI1_TXP[0] DDI1_TXN[1] DDI1_TXP[1] DDI1_TXN[2] DDI1_TXP[2] DDI1_TXN[3] DDI1_TXP[3] +3VS COMPENSATION PU FOR eDP RC1 E Rev_0.53 #543016 PDG0.9 P.775 D CATERR# PECI PROCHOT# THERMTRIP# SKTOCC# JTAG PROC_TCK PROC_TDI PROC_TDO PROC_TMS PROC_TRST# CPU MISC BPM#[0] BPM#[1] BPM#[2] BPM#[3] PCH_JTAG_TCK PCH_JTAG_TDI PCH_JTAG_TDO PCH_JTAG_TMS PCH_TRST# JTAGX GPP_E3/CPU_GP0 GPP_E7/CPU_GP1 GPP_B3/CPU_GP2 GPP_B4/CPU_GP3 B61 D60 A61 C60 B59 CPU_XDP_TCK0 SOC_XDP_TDI SOC_XDP_TDO SOC_XDP_TMS SOC_XDP_TRST# B56 D59 A56 C59 C61 A59 PCH_JTAG_TCK1 SOC_XDP_TDI SOC_XDP_TDO SOC_XDP_TMS SOC_XDP_TRST# CPU_XDP_TCK0 PROC_POPIRCOMP PCH_OPIRCOMP OPCE_RCOMP OPC_RCOMP OF 20 SKL-U_BGA1356 @ +1.0VS_VCCSTG Place to CPU side RC11 CMC@ 51_0402_5% SOC_XDP_TMS RC13 CMC@ 51_0402_5% SOC_XDP_TDI RC15 CMC@ 51_0402_5% SOC_XDP_TDO CMC@ 51_0402_5% SOC_XDP_TDO RC17 CMC@ RPC2 SOC_XDP_TMS SOC_XDP_TDI SOC_XDP_TRST# SOC_XDP_TDO XDP CONN XDP_TMS XDP_TDI XDP_TRST# XDP_TDO +1.0VALW_PRIM RC12 0_0804_8P4R_5% APS CONN 17 +1.0V_XDP XDP_ITP_PMODE CFG3 XDP_ITP_PMODE RC55 RC56 CMC@ 0_0402_5% XDP_PRSENT_CPU CMC@ 0_0402_5% XDP_HOOK6 JPCMC1 +3VALW +3VALW_PRIM 10 10,38,42 10 10 10 11 12 13 14 15 16 17 18 19 20 PM_SLP_S3# PM_SLP_S5# PM_SLP_S4# PM_SLP_A# SOC_RTCRST# PBTN_OUT#_R2 10 SYS_RESET# 10,38 PM_SLP_S0# RC31 CMC@ 1K_0402_5% 10 11 12 13 14 15 16 17 18 GND GND RC43 @ 0_0402_5% XDP_PRSENT_CPU RC46 @ 0_0402_5% XDP_PRSENT_PCH XDP_SPI_SI CPU_XDP_TCK0 XDP_SPI_IO2 RC35 CMC@ 51_0402_1% Place to CPU side XDP_ITP_PMODE RC37 RC151 2 @ @ 51_0402_5% 1K_0402_5% XDP_SPI_SI PCH_JTAG_TCK1 CPU_XDP_TCK0 XDP_SPI_IO2 XDP_HOOK3 XDP_TCK1 XDP_TCK0 XDP_PRSENT_PCH 0_0804_8P4R_5% PCH_JTAG_TCK1 CFG0 CMC@ RPC15 10,38 EC_RSMRST# EC_RSMRST# RC23 CMC@ 1K_0402_5% 17 17 XDP_HOOK0 Follow 544924_Skylake_EDS_Vol_1_Rev_0.93 +3VALW_PRIM ACES_50506-01841-P01 CONN@ ACES_50506-01841-P01_18P-NPM RC9 CMC@ 1K_0402_5% 17 17 17 17 17 17 17 17 CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG17 CFG16 17 17 17 17 17 17 17 17 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 17 17 CFG19 CFG18 CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 11 13 15 CFG17 CFG16 17 21 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 10 12 14 16 CFG19 CFG18 18 20 @ 0_0603_5% CMC_DEBUG_36P +1.0V_XDP OBS DATA JAPS1 10,38,42 +1.0V_XDP JTAG/RC/HOOKS DATA_0 DATA_1 DATA_2 DATA_3 DATA_4 DATA_5 DATA_6 DATA_7 VCCOBS_AB XDP_TRST* XDP_TDI XDP_TMS XDP_TCK0 XDP_TCK1 XDP_TDO DATA_CLK_1P DATA_CLK_1N XDP_PREQ* XDP_PRDY* DATA_8 DATA_9 DATA_10 DATA_11 DATA_12 DATA_13 DATA_14 DATA_15 HOOK_0 HOOK_3 HOOK_6 XDP_PRSNT_PCH* XDP_PRSNT_CPU* DATA_CLK_2P DATA_CLK_2N GND GND 22 28 29 30 32 31 35 XDP_TRST# XDP_TDI XDP_TMS XDP_TCK0 XDP_TCK1 XDP_TDO 33 34 XDP_PREQ# XDP_PRDY# 27 25 26 XDP_HOOK0 XDP_HOOK3 XDP_HOOK6 24 23 XDP_PRSENT_PCH XDP_PRSENT_CPU XDP_PREQ# XDP_PRDY# 12 12 19 36 XDP_SPI_SI 4 INTEL_CMC_PRIMARY CONN@ 10,38 PBTN_OUT# 38,39 ON/OFFBTN# RC53 @ 0_0402_5% RC54 @ 0_0402_5% Compal Secret Data Security Classification PBTN_OUT#_R2 Issued Date 2014/11/10 Deciphered Date 2016/11/10 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC SKL-U(1/12)DDI,MSIC,XDP,EDP Document Number Size Custom Date: A B C D Compal Electronics, Inc Title A4WAS M/B LA-C611P Sheet Monday, June 22, 2015 E of Rev 1.0 60 A B C D E Interleaved Memory 1 SKL-U UC1B UC1C SKL-U Rev_0.53 Rev_0.53 18 18 DDR_A_D[0 15] DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63 DDR_A_D[16 31] 18 18 DDR_A_D[32 47] DDR_A_D[48 63] AL71 AL68 AN68 AN69 AL70 AL69 AN70 AN71 AR70 AR68 AU71 AU68 AR71 AR69 AU70 AU69 BB65 AW65 AW63 AY63 BA65 AY65 BA63 BB63 BA61 AW61 BB59 AW59 BB61 AY61 BA59 AY59 AY39 AW39 AY37 AW37 BB39 BA39 BA37 BB37 AY35 AW35 AY33 AW33 BB35 BA35 BA33 BB33 AY31 AW31 AY29 AW29 BB31 BA31 BA29 BB29 AY27 AW27 AY25 AW25 BB27 BA27 BA25 BB25 DDR0_DQ[0] DDR0_DQ[1] DDR0_DQ[2] DDR0_DQ[3] DDR0_DQ[4] DDR0_DQ[5] DDR0_DQ[6] DDR0_DQ[7] DDR0_DQ[8] DDR0_DQ[9] DDR0_DQ[10] DDR0_DQ[11] DDR0_DQ[12] DDR0_DQ[13] DDR0_DQ[14] DDR0_DQ[15] DDR0_DQ[16]/DDR0_DQ[32] DDR0_DQ[17]/DDR0_DQ[33] DDR0_DQ[18]/DDR0_DQ[34] DDR0_DQ[19]/DDR0_DQ[35] DDR0_DQ[20]/DDR0_DQ[36] DDR0_DQ[21]/DDR0_DQ[37] DDR0_DQ[22]/DDR0_DQ[38] DDR0_DQ[23]/DDR0_DQ[39] DDR0_DQ[24]/DDR0_DQ[40] DDR0_DQ[25]/DDR0_DQ[41] DDR0_DQ[26]/DDR0_DQ[42] DDR0_DQ[27]/DDR0_DQ[43] DDR0_DQ[28]/DDR0_DQ[44] DDR0_DQ[29]/DDR0_DQ[45] DDR0_DQ[30]/DDR0_DQ[46] DDR0_DQ[31]/DDR0_DQ[47] DDR0_DQ[32]/DDR1_DQ[0] DDR0_DQ[33]/DDR1_DQ[1] DDR0_DQ[34]/DDR1_DQ[2] DDR0_DQ[35]/DDR1_DQ[3] DDR0_DQ[36]/DDR1_DQ[4] DDR0_DQ[37]/DDR1_DQ[5] DDR0_DQ[38]/DDR1_DQ[6] DDR0_DQ[39]/DDR1_DQ[7] DDR0_DQ[40]/DDR1_DQ[8] DDR0_DQ[41]/DDR1_DQ[9] DDR0_DQ[42]/DDR1_DQ[10] DDR0_DQ[43]/DDR1_DQ[11] DDR0_DQ[44]/DDR1_DQ[12] DDR0_DQ[45]/DDR1_DQ[13] DDR0_DQ[46]/DDR1_DQ[14] DDR0_DQ[47]/DDR1_DQ[15] DDR0_DQ[48]/DDR1_DQ[32] DDR0_DQ[49]/DDR1_DQ[33] DDR0_DQ[50]/DDR1_DQ[34] DDR0_DQ[51]/DDR1_DQ[35] DDR0_DQ[52]/DDR1_DQ[36] DDR0_DQ[53]/DDR1_DQ[37] DDR0_DQ[54]/DDR1_DQ[38] DDR0_DQ[55]/DDR1_DQ[39] DDR0_DQ[56]/DDR1_DQ[40] DDR0_DQ[57]/DDR1_DQ[41] DDR0_DQ[58]/DDR1_DQ[42] DDR0_DQ[59]/DDR1_DQ[43] DDR0_DQ[60]/DDR1_DQ[44] DDR0_DQ[61]/DDR1_DQ[45] DDR0_DQ[62]/DDR1_DQ[46] DDR0_DQ[63]/DDR1_DQ[47] DDR0_CKN[0] DDR0_CKP[0] DDR0_CKN[1] DDR0_CKP[1] DDR0_CKE[0] DDR0_CKE[1] DDR0_CKE[2] DDR0_CKE[3] DDR0_CS#[0] DDR0_CS#[1] DDR0_ODT[0] DDR0_ODT[1] DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7] DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11] DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1] DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13] DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15] DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14] DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16] DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0] DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2] DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1] DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10] DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0] DDR0_MA[3] DDR0_MA[4] DDR0_DQSN[0] DDR0_DQSP[0] DDR0_DQSN[1] DDR0_DQSP[1] DDR0_DQSN[2]/DDR0_DQSN[4] DDR0_DQSP[2]/DDR0_DQSP[4] DDR0_DQSN[3]/DDR0_DQSN[5] DDR0_DQSP[3]/DDR0_DQSP[5] DDR0_DQSN[4]/DDR1_DQSN[0] DDR0_DQSP[4]/DDR1_DQSP[0] DDR0_DQSN[5]/DDR1_DQSN[1] DDR0_DQSP[5]/DDR1_DQSP[1] DDR0_DQSN[6]/DDR1_DQSN[4] DDR0_DQSP[6]/DDR1_DQSP[4] DDR0_DQSN[7]/DDR1_DQSN[5] DDR0_DQSP[7]/DDR1_DQSP[5] DDR0_ALERT# DDR0_PAR DDR CH - A DDR_VREF_CA DDR0_VREF_DQ DDR1_VREF_DQ DDR_VTT_CNTL AU53 AT53 AU55 AT55 DDR_A_CLK#0 DDR_A_CLK0 DDR_A_CLK#1 DDR_A_CLK1 BA56 BB56 AW56 AY56 DDR_A_CKE0 DDR_A_CKE1 AU45 AU43 AT45 AT43 DDR_A_CS#0 DDR_A_CS#1 DDR_A_ODT0 DDR_A_ODT1 BA51 BB54 BA52 AY52 AW52 AY55 AW54 BA54 BA55 AY54 DDR_A_MA5 DDR_A_MA9 DDR_A_MA6 DDR_A_MA8 DDR_A_MA7 DDR_A_BS2 DDR_A_MA12 DDR_A_MA11 DDR_A_MA15 DDR_A_MA14 AU46 AU48 AT46 AU50 AU52 AY51 AT48 AT50 BB50 AY50 BA50 BB52 DDR_A_MA13 DDR_A_CAS# DDR_A_WE# DDR_A_RAS# DDR_A_BS0 DDR_A_MA2 DDR_A_BS1 DDR_A_MA10 DDR_A_MA1 DDR_A_MA0 DDR_A_MA3 DDR_A_MA4 AM70 AM69 AT69 AT70 BA64 AY64 AY60 BA60 BA38 AY38 AY34 BA34 BA30 AY30 AY26 BA26 DDR_A_DQS#0 DDR_A_DQS0 DDR_A_DQS#1 DDR_A_DQS1 DDR_A_DQS#2 DDR_A_DQS2 DDR_A_DQS#3 DDR_A_DQS3 DDR_A_DQS#4 DDR_A_DQS4 DDR_A_DQS#5 DDR_A_DQS5 DDR_A_DQS#6 DDR_A_DQS6 DDR_A_DQS#7 DDR_A_DQS7 AW50 AT52 AY67 AY68 BA67 AW67 @ @ @ DDR_A_CLK#0 DDR_A_CLK0 DDR_A_CLK#1 DDR_A_CLK1 18 18 18 18 DDR_A_CKE0 DDR_A_CKE1 18 18 19 DDR_B_D[0 15] T14 T15 DDR_A_CS#0 DDR_A_CS#1 DDR_A_ODT0 DDR_A_ODT1 18 18 18 18 DDR_A_MA5 DDR_A_MA9 DDR_A_MA6 DDR_A_MA8 DDR_A_MA7 DDR_A_BS2 DDR_A_MA12 DDR_A_MA11 DDR_A_MA15 DDR_A_MA14 18 18 18 18 18 18 18 18 18 18 DDR_A_MA13 DDR_A_CAS# DDR_A_WE# DDR_A_RAS# DDR_A_BS0 DDR_A_MA2 DDR_A_BS1 DDR_A_MA10 DDR_A_MA1 DDR_A_MA0 DDR_A_MA3 DDR_A_MA4 18 18 18 18 18 18 18 18 18 18 18 18 DDR_A_DQS#0 DDR_A_DQS0 DDR_A_DQS#1 DDR_A_DQS1 DDR_A_DQS#2 DDR_A_DQS2 DDR_A_DQS#3 DDR_A_DQS3 DDR_A_DQS#4 DDR_A_DQS4 DDR_A_DQS#5 DDR_A_DQS5 DDR_A_DQS#6 DDR_A_DQS6 DDR_A_DQS#7 DDR_A_DQS7 DDR_B_D[16 31] 19 DDR_B_D[32 47] 19 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 DDR_B_D[48 63] 19 T22 +0.675V_VREFCA +0.675V_A_VREFDQ +0.675V_B_VREFDQ Trace width/Spacing >= 20mils Place componment near SODIMM +0.675V_VREFCA +0.675V_A_VREFDQ +0.675V_B_VREFDQ #543016 PDG0.9 P.163 RC place near SODIMM DDR_PG_CTRL DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63 AF65 AF64 AK65 AK64 AF66 AF67 AK67 AK66 AF70 AF68 AH71 AH68 AF71 AF69 AH70 AH69 AT66 AU66 AP65 AN65 AN66 AP66 AT65 AU65 AT61 AU61 AP60 AN60 AN61 AP61 AT60 AU60 AU40 AT40 AT37 AU37 AR40 AP40 AP37 AR37 AT33 AU33 AU30 AT30 AR33 AP33 AR30 AP30 AU27 AT27 AT25 AU25 AP27 AN27 AN25 AP25 AT22 AU22 AU21 AT21 AN22 AP22 AP21 AN21 OF 20 SKL-U_BGA1356 @ DDR1_DQ[0]/DDR0_DQ[16] DDR1_DQ[1]/DDR0_DQ[17] DDR1_DQ[2]/DDR0_DQ[18] DDR1_DQ[3]/DDR0_DQ[19] DDR1_DQ[4]/DDR0_DQ[20] DDR1_DQ[5]/DDR0_DQ[21] DDR1_DQ[6]/DDR0_DQ[22] DDR1_DQ[7]/DDR0_DQ[23] DDR1_DQ[8]/DDR0_DQ[24] DDR1_DQ[9]/DDR0_DQ[25] DDR1_DQ[10]/DDR0_DQ[26] DDR1_DQ[11]/DDR0_DQ[27] DDR1_DQ[12]/DDR0_DQ[28] DDR1_DQ[13]/DDR0_DQ[29] DDR1_DQ[14]/DDR0_DQ[30] DDR1_DQ[15]/DDR0_DQ[31] DDR1_DQ[16]/DDR0_DQ[48] DDR1_DQ[17]/DDR0_DQ[49] DDR1_DQ[18]/DDR0_DQ[50] DDR1_DQ[19]/DDR0_DQ[51] DDR1_DQ[20]/DDR0_DQ[52] DDR1_DQ[21]/DDR0_DQ[53] DDR1_DQ[22]/DDR0_DQ[54] DDR1_DQ[23]/DDR0_DQ[55] DDR1_DQ[24]/DDR0_DQ[56] DDR1_DQ[25]/DDR0_DQ[57] DDR1_DQ[26]/DDR0_DQ[58] DDR1_DQ[27]/DDR0_DQ[59] DDR1_DQ[28]/DDR0_DQ[60] DDR1_DQ[29]/DDR0_DQ[61] DDR1_DQ[30]/DDR0_DQ[62] DDR1_DQ[31]/DDR0_DQ[63] DDR1_DQ[32]/DDR1_DQ[16] DDR1_DQ[33]/DDR1_DQ[17] DDR1_DQ[34]/DDR1_DQ[18] DDR1_DQ[35]/DDR1_DQ[19] DDR1_DQ[36]/DDR1_DQ[20] DDR1_DQ[37]/DDR1_DQ[21] DDR1_DQ[38]/DDR1_DQ[22] DDR1_DQ[39]/DDR1_DQ[23] DDR1_DQ[40]/DDR1_DQ[24] DDR1_DQ[41]/DDR1_DQ[25] DDR1_DQ[42]/DDR1_DQ[26] DDR1_DQ[43]/DDR1_DQ[27] DDR1_DQ[44]/DDR1_DQ[28] DDR1_DQ[45]/DDR1_DQ[29] DDR1_DQ[46]/DDR1_DQ[30] DDR1_DQ[47]/DDR1_DQ[31] DDR1_DQ[48] DDR1_DQ[49] DDR1_DQ[50] DDR1_DQ[51] DDR1_DQ[52] DDR1_DQ[53] DDR1_DQ[54] DDR1_DQ[55] DDR1_DQ[56] DDR1_DQ[57] DDR1_DQ[58] DDR1_DQ[59] DDR1_DQ[60] DDR1_DQ[61] DDR1_DQ[62] DDR1_DQ[63] DDR1_CKN[0] DDR1_CKN[1] DDR1_CKP[0] DDR1_CKP[1] DDR1_CKE[0] DDR1_CKE[1] DDR1_CKE[2] DDR1_CKE[3] DDR1_CS#[0] DDR1_CS#[1] DDR1_ODT[0] DDR1_ODT[1] DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7] DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11] DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT# DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1] DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13] DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15] DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14] DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16] DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0] DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2] DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10] DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0] DDR1_MA[3] DDR1_MA[4] DDR1_DQSN[0]/DDR0_DQSN[2] DDR1_DQSP[0]/DDR0_DQSP[2] DDR1_DQSN[1]/DDR0_DQSN[3] DDR1_DQSP[1]/DDR0_DQSP[3] DDR1_DQSN[2]/DDR0_DQSN[6] DDR1_DQSP[2]/DDR0_DQSP[6] DDR1_DQSN[3]/DDR0_DQSN[7] DDR1_DQSP[3]/DDR0_DQSP[7] DDR1_DQSN[4]/DDR1_DQSN[2] DDR1_DQSP[4]/DDR1_DQSP[2] DDR1_DQSN[5]/DDR1_DQSN[3] DDR1_DQSP[5]/DDR1_DQSP[3] DDR1_DQSN[6] DDR1_DQSP[6] DDR1_DQSN[7] DDR1_DQSP[7] DDR1_ALERT# DDR1_PAR DRAM_RESET# DDR_RCOMP[0] DDR_RCOMP[1] DDR_RCOMP[2] DDR CH - B AN45 AN46 AP45 AP46 DDR_B_CLK#0 DDR_B_CLK#1 DDR_B_CLK0 DDR_B_CLK1 AN56 AP55 AN55 AP53 DDR_B_CKE0 DDR_B_CKE1 BB42 AY42 BA42 AW42 DDR_B_CS#0 DDR_B_CS#1 DDR_B_ODT0 DDR_B_ODT1 AY48 AP50 BA48 BB48 AP48 AP52 AN50 AN48 AN53 AN52 DDR_B_MA5 DDR_B_MA9 DDR_B_MA6 DDR_B_MA8 DDR_B_MA7 DDR_B_BS2 DDR_B_MA12 DDR_B_MA11 DDR_B_MA15 DDR_B_MA14 BA43 AY43 AY44 AW44 BB44 AY47 BA44 AW46 AY46 BA46 BB46 BA47 DDR_B_MA13 DDR_B_CAS# DDR_B_WE# DDR_B_RAS# DDR_B_BS0 DDR_B_MA2 DDR_B_BS1 DDR_B_MA10 DDR_B_MA1 DDR_B_MA0 DDR_B_MA3 DDR_B_MA4 AH66 AH65 AG69 AG70 AR66 AR65 AR61 AR60 AT38 AR38 AT32 AR32 AR25 AR27 AR22 AR21 DDR_B_DQS#0 DDR_B_DQS0 DDR_B_DQS#1 DDR_B_DQS1 DDR_B_DQS#2 DDR_B_DQS2 DDR_B_DQS#3 DDR_B_DQS3 DDR_B_DQS#4 DDR_B_DQS4 DDR_B_DQS#5 DDR_B_DQS5 DDR_B_DQS#6 DDR_B_DQS6 DDR_B_DQS#7 DDR_B_DQS7 AN43 AP43 AT13 AR18 AT18 AU18 @ @ DDR_B_CLK#0 DDR_B_CLK#1 DDR_B_CLK0 DDR_B_CLK1 19 19 19 19 DDR_B_CKE0 DDR_B_CKE1 19 19 DDR_B_CS#0 DDR_B_CS#1 DDR_B_ODT0 DDR_B_ODT1 19 19 19 19 DDR_B_MA5 DDR_B_MA9 DDR_B_MA6 DDR_B_MA8 DDR_B_MA7 DDR_B_BS2 DDR_B_MA12 DDR_B_MA11 DDR_B_MA15 DDR_B_MA14 19 19 19 19 19 19 19 19 19 19 DDR_B_MA13 DDR_B_CAS# DDR_B_WE# DDR_B_RAS# DDR_B_BS0 DDR_B_MA2 DDR_B_BS1 DDR_B_MA10 DDR_B_MA1 DDR_B_MA0 DDR_B_MA3 DDR_B_MA4 19 19 19 19 19 19 19 19 19 19 19 19 T17 T18 DDR_DRAMRST# DDR_B_DQS#0 DDR_B_DQS0 DDR_B_DQS#1 DDR_B_DQS1 DDR_B_DQS#2 DDR_B_DQS2 DDR_B_DQS#3 DDR_B_DQS3 DDR_B_DQS#4 DDR_B_DQS4 DDR_B_DQS#5 DDR_B_DQS5 DDR_B_DQS#6 DDR_B_DQS6 DDR_B_DQS#7 DDR_B_DQS7 @ SM_RCOMP0 SM_RCOMP1 SM_RCOMP2 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 T23 DDR_DRAMRST# RC38 RC39 RC40 18,19 121_0402_1% 80.6_0402_1% 100_0402_1% OF 20 #543016 PDG0.9 P.117 W=12-15 Space= 20/25 L=500mil SKL-U_BGA1356 @ Pre_ES Sample DDR_VTT_CNTL to DDR VTT supplied ramped AAX05 Use = Enable TOP Swap Mode BA22 AY22 BB22 BA21 AY21 AW22 J5 AY20 AW20 PCH_DMIC_CLK PCH_DMIC_DATA 40 PCH_DMIC_CLK 40 PCH_DMIC_DATA H5 D7 D8 C8 40 SPKR SPKR AW5 HDA_SYNC/I2S0_SFRM HDA_BLK/I2S0_SCLK HDA_SDO/I2S0_TXD HDA_SDI0/I2S0_RXD HDA_SDI1/I2S1_RXD HDA_RST#/I2S1_SCLK GPP_D23/I2S_MCLK I2S1_SFRM I2S1_TXD #543016 PDG0.9 P.321 Terminating Unused SDIO/SDXC Signals SDIO signals are multiplexed with GPIOs and default to GPIO functionality (as input) If SDIO interface is not used, the signals can be used as GPIOs instead If the GPIO functionality is also not used, the signals can be left as no-connect SDIO/SDXC GPP_G0/SD_CMD GPP_G1/SD_DATA0 GPP_G2/SD_DATA1 GPP_G3/SD_DATA2 GPP_G4/SD_DATA3 GPP_G5/SD_CD# GPP_G6/SD_CLK GPP_G7/SD_WP GPP_F1/I2S2_SFRM GPP_F0/I2S2_SCLK GPP_F2/I2S2_TXD GPP_F3/I2S2_RXD GPP_A17/SD_PWR_EN#/ISH_GP7 GPP_A16/SD_1P8_SEL GPP_D19/DMIC_CLK0 GPP_D20/DMIC_DATA0 SD_RCOMP GPP_D17/DMIC_CLK1 GPP_D18/DMIC_DATA1 GPP_F23 AB11 AB13 AB12 W12 W11 W10 W8 W7 BA9 BB9 SD_RCOMP AB7 RC76 200_0402_1% AF13 GPP_B14/SPKR OF 20 SKL-U_BGA1356 @ HDA for AUDIO RPC9 40 40 40 40 HDA_SYNC_R HDA_SDOUT_R HDA_BIT_CLK_R HDA_RST#_R HDA_SYNC HDA_SDOUT HDA_BIT_CLK HDA_RST# 33_0804_8P4R_5% 38 40 ME_EN @ RC77 HDA_SDIN0 HDA_SDOUT 0_0402_5% HDA_SDIN0 SKL_ULT UC1I Rev_0.53 CSI-2 A29 B29 C28 D28 A27 B27 C27 D27 CSI2_COMP GPP_D4/FLASHTRIG CSI2_DN4 CSI2_DP4 CSI2_DN5 CSI2_DP5 CSI2_DN6 CSI2_DP6 CSI2_DN7 CSI2_DP7 +3VALW _1.8VALW _PGPPD C37 D37 C32 D32 C29 D29 B26 A26 E13 CSI2_COMP RC80 DGPU_PRSNT# B7 DGPU_PRSNT# 100_0402_1% EMMC GPP_F13/EMMC_DATA0 GPP_F14/EMMC_DATA1 GPP_F15/EMMC_DATA2 GPP_F16/EMMC_DATA3 GPP_F17/EMMC_DATA4 GPP_F18/EMMC_DATA5 GPP_F19/EMMC_DATA6 GPP_F20/EMMC_DATA7 CSI2_DN8 CSI2_DP8 CSI2_DN9 CSI2_DP9 CSI2_DN10 CSI2_DP10 CSI2_DN11 CSI2_DP11 GPP_F21/EMMC_RCLK GPP_F22/EMMC_CLK GPP_F12/EMMC_CMD OF 20 RC133 10K_0402_5% UMA@ CSI2_CLKN0 CSI2_CLKP0 CSI2_CLKN1 CSI2_CLKP1 CSI2_CLKN2 CSI2_CLKP2 CSI2_CLKN3 CSI2_CLKP3 C31 D31 C33 D33 A31 B31 A33 B33 CSI2_DN0 CSI2_DP0 CSI2_DN1 CSI2_DP1 CSI2_DN2 CSI2_DP2 CSI2_DN3 CSI2_DP3 EMMC_RCOMP AP2 AP1 AP3 AN3 AN1 AN2 AM4 AM1 GPIO67 AM2 AM3 AP4 AT1 RC134 10K_0402_5% VGA@ A36 B36 C38 D38 C36 D36 A38 B38 DGPU_PRSNT# EMMC_RCOMP RC89 DIS,Optimus UMA 200_0402_1% SKL-U_BGA1356 @ 4 Compal Secret Data Security Classification 2014/11/10 Issued Date Deciphered Date 2016/11/10 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title SKL-U(4/12)HDA,EMMC,SDIO,CSI2 Size Document Number Custom B C D Rev 1.0 A4WAS M/B LA-C611P Date: A Compal Electronics, Inc Sheet Tuesday, June 16, 2015 E of 60 A B C D SKL_ULT UC1J +RTCVCC E Rev_0.53 CLOCK SIGNALS 20K_0402_5% SOC_SRTCRST# 20 20 DGPU 1U_0402_6.3V6K CLK_PCIE_N0 D42 CLK_PCIE_P0 C42 CLKREQ_PCIE#0 AR10 CLK_PCIE_N0 CLK_PCIE_P0 PH at DGPU side 33 33 33 GLAN NGFF WL+BT(KEY E) 1U_0402_6.3V6K CLR CMOS 0_0603_5% CLK_PCIE_N2 CLK_PCIE_P2 CLKREQ_PCIE#2 Place at RAM DOOR RC94 D41 C41 AT8 1M_0402_5% CLKREQ_PCIE#4 B40 A40 AU8 CLKREQ_PCIE#5 E40 E38 AU7 SM_INTRUDER# +3VS CLKREQ_PCIE#4 10K_0402_5% CLKREQ_PCIE#5 10K_0402_5% RC124 SOC_XTAL24_IN SOC_XTAL24_OUT E42 XCLK_BIASREF AM18 AM20 SOC_RTCX1 SOC_RTCX2 AN18 AM16 SOC_SRTCRST# SOC_RTCRST# Follow 2014MOW48 Skylake U PU 2.7k ohm to 1V Cannonlake U PD 60.4 ohm T3807@ G RC96 1 RC136 2.7K_0402_1% 60.4_0402_1% @ SOC_RTCRST# 2014MOW48: Skylake U use 24M 50 ohm ESR Cannonlake U use 38.4M 30 ohm ESR SOC_XTAL24_OUT PLT_RST# CLKREQ_PCIE#0 1 PLT_RST_BUF# UC3 MC74VHC1G08DFT2G_SC70-5 2 Y A @ PLT_RST_BUF# 33,35 YC1 24MHZ_12PF_7V24000020 R157 100K_0402_5% 0_0402_5% RC125 10K_0804_8P4R_5% Note for PCH_PWROK PDG1.0 Figure43-4 note20: PCH_PWROK does not glitch when RSMRST# is de-asserted 543016_SKL_U_Y_PDG_0_9 +3VALW _DSW PM_BATLOW # 2 RC104 W AKE# 1K_0402_5% @ AC_PRESENT 10K_0402_5% RC106 #543016 PDG0.9 P.526 PROCPWRGD is used only for power sequence debug and is not required to be connected to anything on the platform +3VALW _PRIM PLT_RST# SYS_RESET# EC_RSMRST# @ H_CPUPW RGD EC_VCCST_PG A68 B65 T89 @ 38,42 SYS_PW ROK 38,42 PCH_PW ROK SYS_PW ROK PCH_PW ROK PCH_DPW ROK B6 BA20 BB20 SUSPW 38 RDNACK WAKE# (DSX wake event) @ T92 10 KΩ pull-up to VccDSW3_3 The pull-up is required even if PCIe* interface is not used on the platform LAN WAKE: LAN Wake Indicator from the GbE PHY 10K_0402_5% SOC_VRALERT# +3VALW _DSW RC111 @ AN10 B5 AY17 @ T95 RC115 @ @ Rev_0.53 SYSTEM POWER MANAGEMENT 20,38,39 PLT_RST# SYS_RESET# 6,38 EC_RSMRST# 10K_0402_5% SKL-U UC1K SUSPW RDNACK AR13 AP11 SUSACK# W AKE# LAN_W AKE# BB15 AM15 AW17 AT15 GPP_B12/SLP_S0# GPD4/SLP_S3# GPD5/SLP_S4# GPD10/SLP_S5# GPP_B13/PLTRST# SYS_RESET# RSMRST# SLP_SUS# SLP_LAN# GPD9/SLP_WLAN# GPD6/SLP_A# PROCPWRGD VCCST_PWRGD SYS_PWROK PCH_PWROK DSW_PWROK GPD3/PWRBTN# GPD1/ACPRESENT GPD0/BATLOW# GPP_A13/SUSWARN#/SUSPWRDNACK GPP_A15/SUSACK# GPP_A11/PME# INTRUDER# WAKE# GPD2/LAN_WAKE# GPD11/LANPHYPC GPD7/RSVD GPP_B11/EXT_PWR_GATE# GPP_B2/VRALERT# 11 OF 20 1M_0402_5% GND GND CC13 15P_0402_50V8J R112 2.2K_0402_5% @ B RC92 CC12 15P_0402_50V8J R107 2.2K_0402_5% @ PCH_PW ROK EC_RSMRST# SYS_RESET# LAN_W AKE# SOC_XTAL24_IN +3VS R115 10K_0402_5% VGA@ Q2 RPC11 RC103 +1.0VALW _CLK5_F24NS CLKOUT_PCIE_N5 CLKOUT_PCIE_P5 GPP_B10/SRCCLKREQ5# D PEG_CLKREQ# S 20 +3VALW _PRIM Follow XCLK_BIASREF T:50ohm S:12/15 L:1000 Via:2 PCH PLTRST Buffer DGPU_PW ROK Pull high @ VGA side SRTCRST# RTCRST# E37 E35 T164 @ T165 @ +3VS 20,42,54,55 CLKOUT_PCIE_N4 CLKOUT_PCIE_P4 GPP_B9/SRCCLKREQ4# SUSCLK 10 OF 20 L2N7002LT1G_SOT23-3 +3VALW _DSW RTCX1 RTCX2 BA17 1 XCLK_BIASREF CLK_CPU_ITP# CLK_CPU_ITP RC123 CLKOUT_PCIE_N3 CLKOUT_PCIE_P3 GPP_B8/SRCCLKREQ3# 1 XTAL24_IN XTAL24_OUT F43 E43 SKL-U_BGA1356 @ CLKREQ_PCIE#1 10K_0402_5% CLKREQ_PCIE#2 10K_0402_5% CLKREQ_PCIE#3 10K_0402_5% RC121 GPD8/SUSCLK RC105 2 RC165 CLKOUT_PCIE_N2 CLKOUT_PCIE_P2 GPP_B7/SRCCLKREQ2# D40 C40 AT10 CLKREQ_PCIE#3 CLKOUT_ITPXDP_N CLKOUT_ITPXDP_P @ 35 35 35 CLK_PCIE_N2 CLK_PCIE_P2 CLKREQ_PCIE#2 CLKOUT_PCIE_N1 CLKOUT_PCIE_P1 GPP_B6/SRCCLKREQ1# CC11 JCMOS1 SOC_RTCRST# B42 A42 AT7 2 20K_0402_5% CLK_PCIE_N1 CLK_PCIE_P1 CLKREQ_PCIE#1 RC93 CLK_PCIE_N1 CLK_PCIE_P1 CLKREQ_PCIE#1 CLKOUT_PCIE_N0 CLKOUT_PCIE_P0 GPP_B5/SRCCLKREQ0# 2 P CC10 G RC91 T84 T85 AT11 AP15 BA16 AY16 PM_SLP_S0# PM_SLP_S3# PM_SLP_S4# PM_SLP_S5# AN15 AW15 BB17 AN16 SLP_SUS# SLP_LAN# SLP_W LAN# PM_SLP_A# BA15 AY15 AU13 PBTN_OUT#_R AC_PRESENT PM_BATLOW # AU11 AP16 SM_INTRUDER# @ T91 AM10 AM11 EXT_PW R_GATE# SOC_VRALERT# @ T93 PM_SLP_S0# PM_SLP_S3# PM_SLP_S4# PM_SLP_S5# @ T86 @ T90 @ T87 @ T88 PM_SLP_A# AC_PRESENT 6,38 6,38,42 6,38,42 38 SOC_RTCX2 SKL-U_BGA1356 @ 100K_0402_5% PBTN_OUT#_R SOC_RTCX1 +1.0V_VCCST 38,42 EC(open-drain) EC_VCCST_PG_R 6,38 PBTN_OUT# RC116 60.4_0402_1% @ PBTN_OUT#_R 0_0402_5% @ PCH_DPW ROK 0_0402_5% RC98 EC_VCCST_PG CC51 @EMC@ 1U_0402_16V7K SYS_RESET# CC50 @EMC@ 1U_0402_16V7K H_CPUPW RGD YC2 Change PN to SJ10000L000 @ PCH_PW ROK 0_0402_5% CC15 8.2P_0402_50V8D 1 CC16 8.2P_0402_50V8D SYS_PW ROK RC110 2014/11/10 Deciphered Date 2016/11/10 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Reserved for ESD 2014/9/17 Title C D Compal Electronics, Inc SKL-U(5/12)CLK,GPIO Size Document Number Custom Rev 1.0 A4WAS M/B LA-C611P Date: B 2 10K_0402_5% Compal Secret Data Security Classification Issued Date A 10M_0402_5% 32.768KHZ_9PF_CM7V-T1A9.0PF20PPM SYS_PW ROK RC122 RC109 EC_RSMRST# RC114 RC113 1K_0402_5% From Note for VCCST_PWRGD 1.0V tolerance PDG1.0 Figure43-4 note17: when failure events, VCCST_PWRGD and PCH_PWROK de-assert at the same time Sheet Tuesday, June 16, 2015 E 10 of 60 B C D Module model information +19VB 3V_EN 2 SH000016800 PC426 5V_SN VL 5V LDO 150mA~300mA @ PC425 22U_0603_6.3V6M @ PC424 22U_0603_6.3V6M PC423 22U_0603_6.3V6M PC422 22U_0603_6.3V6M 21 PC421 22U_0603_6.3V6M 16 PC420 22U_0603_6.3V6M +5VALWP 4.7U_0603_6.3V6M @EMI@ PC427 4.7U_0603_6.3V6M 15 14 13 12 5V_EN ENLDO_3V5V PL404 1.5UH_PCMB053T-1R5MS_6A_20% PC419 GND 18 17 Common part NC 5*5*3 LX_5V PR409 VCC NC 19 4.7_1206_5% PG 20 @EMI@ PC418 BS IN IN IN GND EN2 GND 11 SPOK LX LDO 10 GND OUT LX FF @ PR408 0_0603_5% BST_5V1 0.1U_0603_25V7K LX EN1 LX_5V SPOK_R @EMI@ PC417 0.1U_0402_25V6 @ EMI@ PC416 2200P_0402_50V7K PC415 10U_0805_25V6K PC414 10U_0805_25V6K IN +19VB_5V SY8286CRAC_QFN20_3X3 680P_0603_50V7K PU402 PR413 @ 0_0402_5% Vout is 4.998V~5.202V PC413 PR407 1000P_0402_25V8J 1K_0402_5% 5V_FB 2 38,41,44 MAINPWON PC410 22U_0603_6.3V6M Vout is 3.234V~3.366V Ipeak=4.65A Imax=3.25A TDC=6A Iocp=10A +19VB_5V EMI@ PL403 HCB2012KF-121T50_0805 38 EC_ON PC409 22U_0603_6.3V6M 1 PR405 1 3V_SN 2 @EMI@ 3.3V LDO 150mA~300mA PC402 PR403 1000P_0402_25V8J1K_0402_5% 2 3V_FB 21 PC411 4.7U_0603_6.3V6M +3VALWP 1.5UH_PCMB053T-1R5MS_6A_20% +3VLP 16 SH000016800 680P_0603_50V7K 4.7_1206_5% ENLDO_3V5V PC412 15 14 12 11 GND 18 17 Common part PL402 @EMI@ NC 19 SPOK 38 5*5*3 LX_3V NC NC LDO 38,49 PC401 20 2 GND PG OUT GND PR406 100K_0402_5% @ PR401 0_0603_5% BS IN IN LX EN2 GND FF 10 Check pull up resistor of SPOK at HW side LX 13 IN IN 0.1U_0603_25V7K LX EN1 LX_3V6 +3VALWP BST_3V +19VB_3V PC405 10U_0805_25V6K @EMI@ PC403 0.1U_0402_25V6 EMI@ PC404 2200P_0402_50V7K EMI@ PL401 HCB2012KF-121T50_0805 +19VB PC408 22U_0603_6.3V6M PU401 SY8286BRAC_QFN20_3X3 +19VB E PR404 150K_0402_1% EN1 and EN2 dont't floating PR402 499K_0402_1% ENLDO_3V5V TPS51225C_V1.mdd PC407 22U_0603_6.3V6M A TDC=6A PR410 2.2K_0402_5% PR411 0_0402_5% Ipeak=9A Imax=6.25A Iocp=10A @ @ PJ401 +3VALWP 2 +3VALW JUMP_43X118 PC428 4.7U_0402_6.3V6M PR412 1M_0402_1% 5V_EN @ PJ402 +5VALWP 2 +5VALW JUMP_43X118 4 Compal Secret Data Security Classification 2014/11/10 Issued Date 2016/11/10 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Size Custom Date: A B C D Compal Electronics, Inc PWR-3.3VALWP/5VALWP Document Number R ev 1.0 A4WAS M/B LA-C611P Tuesday, June 16, 2015 Sheet E 46 of 60 A B C D E Module model information RT8207M_V1.mdd RT8207M_V2.mdd For Single layer For Dual layer 1 Pin19 need pull separate from +1.35VP If you have +1.35V and +0.675V sequence question, you can change from +1.35VP to +1.35VS +19VB_1.35VP PR502 2.2_0603_5% BST_1.35VP_R BST_1.35VP SM_PG_CTRL @ PR509 0_0402_5% Mode S5 S3 S0 Level L L H +0.675VSP off off on VTTREF_1.35V off on on Note: S3 - sleep ; S5 - power off 0.1U_0402_10V7K 10mohm(Max) Switching Frequency: 285kHz Ipeak=10A Iocp~13A OVP: 110%~120% VFB=0.75V, Vout=1.3545V MOSFET footprint: SIS412DN @ PJ501 JUMP_43X118 2 +1.35V_VDDQ +0.675VSP @ PJ502 JUMP_43X39 2 +0.675VS_VTT Compal Secret Data Security Classification 2014/11/10 Issued Date Deciphered Date 2016/11/10 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title B C D Compal Electronics, Inc RT8207P Size Document Number Custom Rev 1.0 A4WAS M/B LA-C611P Date: A Vout=0.75V* (1+Rup/Rdown) =0.75*(1+(8.06/10)) =1.354V 0.2% Vout=0.75V* (1+Rup/Rdown) =0.75*(1+(8.2/10)) =1.365V 1.1% @ PR510 0_0402_5% @ PC519 Choke: 7x7x3 Rdc=8.3mohm(Typ), +1.35VP +1.35VP L/S Rds(on): 9.9mohm(Typ), 13mohm(Max) Idsm: 13.5A@Ta=25C, 11A@Ta=70C 2 PR508 10K_0402_1% 13,38,42,45,49 SUSP# PC516 0.033U_0402_16V7K MOSFET: 3x3 DFN H/S Rds(on): 27mohm(Typ), 34mohm(Max) Idsm: 7.5A@Ta=25C, 5.5A@Ta=70C PC508 10U_0603_6.3V6M VLDOIN BOOT VTT FB +1.35VP VTTREF_1.35VP PR506 8.2K_0402_1% @ PR501 0_0402_5% @ PC501 0.1U_0402_10V7K S3 13,38,42 SYSON 1 PR507 887K_0402_1% +19VB_1.35VP PC507 10U_0603_6.3V6M 20 19 453Kohm >455KHz 18 +5VALW VDDQ S5 VDD 21 FB_1.35VP change PQ502 form 7506 to 7716, 20150108 GND VTTREF PR511 2.2_0402_1% UGATE PHASE VDDP 1U_0402_10V6K 11 VTTGND RT8207MZQW _W QFN20_3X3 SI7716ADN-T1-GE3_POW ERPAK8-5 VDD_1.35VP CS PC517 @EMI@ PC518 680P_0402_50V7K +5VALW 1 + PR505 5.1_0603_5% 2 @EMI@ PR504 4.7_1206_5% Update Pc510 change to Common Part SF000006S00 20141227 PC510 330U_2.5V_M PQ502 PAD VTTSNS EN_1.35VP 2LX_1.35VP PGND EN_0.675VSP PR503 13.7K_0402_1% CS_1.35VP 13 PC509 1U_0402_10V6K 12 TON MDV1528URH_PDFN33-8-5 LGATE 14 10 LG_1.35VP 15 PGOOD Choke 1.5uH SH000016700 Common Part 7*7*3 17 PU501 TON_1.35VP PC506 +0.675VSP PQ503 +1.35VP +1.35VP LX_1.35VP 0.1U_0603_25V7K PL502 1.5UH_PCMC063T-1R5MN_9A_20% 0.675Volt +/- 5% TDC 0.7A Peak Current 1A UG_1.35VP PC505 10U_0805_25V6K PC504 10U_0805_25V6K 2 EMI@ PC503 2200P_0402_50V7K change PL501 SM01000C000 to comm part SM01000P200 +19VB_1.35VP @EMI@ PC502 0.1U_0402_25V6 +19VB_CPU 16 EMI@ PL501 HCB2012KF-121T50_0805 Tuesday, June 16, 2015 Sheet E 47 of 60 A B C D E Module model information SYX196D_V3.mdd EN pin don't floating If have pull down resistor at HW side, pls delete PR702 +19VB_1VALW @ PR609 11 ILMT_1VALW 13 0_0402_5% 15 +3VALW NC ILMT NC BYP NC PAD 12 FB = 0.6V PC613 2.2U_0402_6.3V6M 2 2 Rup 1 10 + @ PR610 Rdown 16 21 Pin BYP is for CS Common NB can delete SY8288RAC_QFN20_3X3 PC614 1U_0402_6.3V6K The current limit is set to 6A, 8A or 12A when this pin is pull low, floating or pull high LDO_3V PC612 22U_0603_6.3V6M VCC EN FB_1VALW 17 PC611 22U_0603_6.3V6M GND 20 14 +1.0VALW_PRIM +1.0VALWP 0.1U_0603_25V7K 19 FB +1.0VALWP PL602 1UH_11A_20%_7X7X3_M PC615 220U_B2_4VM_R35M EN_1VALW LX GND LX_1VALW (Common Part) SH00000YE00 PC610 22U_0603_6.3V6M change PL601 SM01000C000 to comm part SM01000P200 GND PC603 BST_1VALW_R1 PC609 22U_0603_6.3V6M 18 LX @ PR606 0_0603_5% PC608 330P_0402_50V7K ILMT_1VALW LX IN BST_1VALW PR608 14K_0402_1% 0_0402_5% IN BS PG IN @ PJ601 JUMP_43X118 2 20K_0402_1% IN @EMI@ PC602 680P_0603_50V7K SNUB_1VALW @ PR607 PC606 10U_0805_25V6K 1 LDO_3V PU601 +19VB_1VALW EMI@ PC604 2200P_0402_50V7K +19VB @EMI@ PR605 4.7_1206_5% EMI@ PL601 HCB2012KF-121T50_0805 @EMI@ PC605 0.1U_0402_25V6 1 +3VALW and PC15 Vout=0.6V* (1+Rup/Rdown) =0.6*(1+(14/20)) Vout=1.02V 2 @ PR602 0_0402_5% +1.8VALW_PG 49 @ PR603 10K_0402_1% 1 EN_1VALW +3VALW @ PC601 PR601 0.22U_0402_10V6K 1M_0402_1% Function Field : VCCEDPIO : IC-35.21 , others - 35.22 VCCEDRAM : IC-35.25 , others - 35.26 3 4 Compal Secret Data Security Classification Issued Date 2014/11/10 Deciphered Date 2016/11/10 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Size C Date: A B C D Compal Electronics, Inc VCCP Document Number Rev 1.0 A4WAS M/B LA-C611P Tuesday, July 14, 2015 Sheet E 48 of 60 A B C D E 1 Module model information SY8032_V2.mdd @ PJ702 JUMP_43X79 2 +1.8VALWP +1.8VALW_PRIM VIN_1.8VALW Imax= 2A, Ipeak= 3A FB=0.6V PC702 22U_0603_6.3V6M PU701 SY8032ABC_SOT23-6 EN +1.8VALWP @EMI@ PR703 PR704 4.7_0603_5% 2 0.1U_0402_16V7K Ipeak=0.27A FB_1.8VALW PR707 2 @ PC701 Rup +1.8VALWP: Imax=0.19A PR701 1M_0402_1% 20K_0402_1% SNUB_1.8VALW @ PR705 0_0402_5% SPOK EN_1.8VALW 38,46 1 FB LX_1.8VALW GND PC705 22U_0603_6.3V6M LX PG +3VALW IN PC704 22U_0603_6.3V6M PR702 100K_0402_1% PC703 68P_0402_50V8J VIN_1.8VALW +1.8VALW_PG PL701 1UH_2.8A_30%_4X4X2_F @ PJ701 JUMP_43X79 2 +3VALW 48 1 Rdown @EMI@ PC706 10K_0402_1% 2 680P_0402_50V7K Note: When design Vin=5V, please stuff snubber to prevent Vin damage Vout=0.6V* Vout=0.6V* (1+Rup/Rdown) (1+(20/10))=1.8V +3VALW +3VALW @ PJ703 3 2 JUMP_43X79 VIN_1.5VS G971ADJF11U_SO8 Rup FB_1.5VS +1.5VSP 2 ADJ 0.4% VO 2 @ PC710 0.1U_0402_16V7K VEN Current limit = 4.7A(min) PC709 0.01U_0402_25V7K PR710 47K_0402_5% EN_1.5VS @ PR708 0_0402_5% 1 GND VO SUSP# VIN TPAD VIN_1.5VS PR709 1K_0402_1% POK 13,38,42,45,47 1U_0402_6.3V6K Ultra Low Dropout 0.23V(typical) at 3A Output Current PU702 VPP 4.7U_0603_6.3V6K PC708 PC707 VIN_1.5VS +1.5VSP: Imax=0.5A @ PJ704 JUMP_43X79 2 +1.5VSP Ipeak=0.75A +1.5VS PC711 22U_0603_6.3V6M PR711 Rdown 1.13K_0402_1% 4 Vout=0.8V* (1+Rup/Rdown) Vout=0.8V* (1+(1/1.13)) = 1.507V Compal Secret Data Security Classification Issued Date 2014/11/10 Deciphered Date 2016/11/10 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Size C Date: A B C D Compal Electronics, Inc SY8032 Document Number Rev 1.0 A4WAS M/B LA-C611P Tuesday, July 14, 2015 Sheet E 49 of 60 C D PC802 0.01U_0402_25V7K 1 2 2 place close to L4 PR816 15K_0402_1% PR818 8.25K_0603_1% SW_1b +3VS 51 PR821 10K_0402_1% VR_PWRGD 38 PR828 110_0402_1% 2.43K_0402_1% 2 2.43K_0402_1% PWM_1a VSSSENSE 15 PR851 100_0402_1% VCCSENSE 15 PC834 2200P_0402_25V7K PC820 0.033U_0402_16V7K 2 PR842 36.5K_0402_1% PC829 15P_0402_50V8J PR840 100_0402_1% 1 71.5K_0402_1% SW_1a 51 15K_0402_1% 2 place close to L1 PH804 100K_0402_1%_NCP15WF104F03RC 51 CSN_1a PC826 1000P_0402_50V7K PR848 2.49K_0402_1% +VCC_CORE 51 @ PR852 0_0402_5% PH805 100K_0402_1%_NCP15WF104F03RC place close to U1 22@ PR859 10K_0402_1% PC832 1000P_0402_50V7K 2 PR867 PC828 1000P_0402_50V7K @ PR847 0_0402_5% 2 @ PR865 0_0402_5% PR835 2 PC815 0.1U_0402_16V7K 100_0402_1% 110_0402_1% 2 VSN_1a PR843 1K_0402_1% PR858 15.4K_0402_1% 15 PC824 2200P_0402_50V8J PC830 1000P_0402_50V7K PR857 88.7K_0402_1% 100_0402_1% PC819 470P_0402_50V7K PR836 VSP_1a PR856 48.7K_0402_1% SOC_SVID_CLK 15 SOC_SVID_ALERT#_R SOC_SVID_DAT 15 PC825 0.015u_0402_25V7K PR824 38 @ PR869 PR846 23E@ PR856 52.3K_0402_1% VR_HOT# PU801 NCP81208 @ PR860 0_0402_5% SCLK PR862 ALERT# 10_0402_1% SDIO 36 35 34 33 32 31 30 29 28 27 26 25 PWM_1b DRVON SCLK ALERT# SDIO VR_HOT# IOUT_1a CSP_1a CSN_1a ILIM_1a COMP_1a VSN_1a PR829 8.25K_0603_1% @ PR866 48 47 46 45 44 43 42 41 40 39 38 37 VSN_2ph VSP_2ph PSYS VSP_1b VSN_1b COMP_1b ILIM_1b CSN_1b CSP_1b IOUT_1b VR_RDY EN PR834 49.9_0402_1% 2 51 45.3_0402_1% 51 DRVON IOUT_2ph DIFFOUT_2ph FB_2ph COMP_2ph ILIM_2ph CSCOMP_2ph CSSUM_2ph CSREF_2ph CSP2_2ph CSP1_2ph TSENSE_2ph VRMP close to the longer distance phase(81208 or 81210) Alert,Data,Clk 38,42 VR_ON PWM_1b PR826 @ PR863 0_0402_5% 1 PR855 61.9K_0402_1% PC831 1U_0603_10V6K 51 220P_0402_50V7K VCC ROSC_COREGT RSOC_SAUS PWM1_2ph PWM2_2ph ICCMAX_2ph ICCMAX_1a ICCMAX_1b ADDR_VBOOT PWM_1a TSENSE_1ph VSP_1a 2 CSN_1b +5VS 24.9k ohm 24.9k ohm 2.43k ohm 2.43k ohm 36.5k ohm 71.5k ohm 10k ohm PH802 100K_0402_1%_NCP15WF104F03RC 113K_0402_1% 13 14 15 16 17 18 19 20 21 22 23 24 PC827 1000P_0402_50V7K PR850 2_0402_1% 1 PR801 1K_0402_1% PC813 470P_0402_50V7K 49 TAB 2 +19VB 1 0 度C place close to U2 @ PR864 0_0402_5% 2 SWN_GT1 PR844 61.9K_0402_1% 51 PR845 2.26K_0402_1% +5VS 2 @ PR868 0_0402_5% PH801 100K_0402_1%_NCP15WF104F03RC PC821 0.01U_0402_50V7K CSN_GT1 0.1U_0402_16V7K PC822 51 PC818 E +1.0V_VCCST PR854 24K_0402_1% 2 PC817 1000P_0402_50V7K 10 11 12 PC801 0.01U_0402_50V7K PR831 75K_0402_1% 22@ PR833 12.4K_0402_1% 220P_0402_50V7K VSN_2ph PC810 1000P_0402_50V7K 2 1 PR830 165K_0402_1% PR825 69.8K_0603_1% 22@ SWN_GT1 2 PR819 PC811 PC814 15P_0402_50V8J 23E@ PR833 15.4K_0402_1% 2 PC804 15P_0402_50V8J 1 PC812 470P_0402_50V7K 1 VSP_2ph 1 place close to L2 PH803 THERM_ 220K 5% 0402 2 PC807 1000P_0402_50V7K PC808 PR814 1000P_0402_50V7K 1K_0402_1% VSNN_2ph PR817 49.9_0402_1% 23E@ PR825 110K_0402_1% @ PR853 33.2K_0402_1% 2 PR815 100_0402_1% PR807 0_0402_5% 2VSN_1b PR811 20K_0402_1% 1 @ @ PR812 0_0402_5% @ PR813 0_0402_5% VSSGT_SENSE VSNN_1b 24.9K_0402_1% 100_0402_1% VCCGT_SENSE @ PR806 0_0402_5% 1 PR810 +VCC_GT 15 100_0402_1% VSP_1b PSYS_MON 1 PR809 15 PR805 2.61K_0402_1% VSPP_1b VSSSA_SENSE @ PR804 0_0402_5% PC805 1000P_0402_50V7K 13 100_0402_1% 2 VCCSA_SENSE 2 PR823 4.75K_0402_1% PR820 1K_0402_1% PC816 1000P_0402_50V7K 13 PR822 PR803 +VCC_SA PR80845 24.9K_0402_1% PC803 1000P_0402_50V7K PR802 1.5K_0402_1% 2 PC806 1000P_0402_50V7K 1 Change PR808 to PR822 to PR846 to PR867 to PR842 to PR836 to PR859 to 20150225 PC833 4700P_0402_25V7K B PC809 0.015u_0402_25V7K A PWM1_2ph 51 4 Compal Secret Data Security Classification Issued Date 2014/11/10 Deciphered Date 2016/11/10 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Size C Date: A B C D Compal Electronics, Inc IMVP8, NCP81206 Document Number Rev 1.0 A4WAS M/B LA-C611P Tuesday, June 16, 2015 Sheet E 50 of 60 A B C D E +19VB EMI@ PL9002 HCB2012KF-121T50_0805 +19VB_CPU LG_VCORE 4 PC9004 68U_25V_M_R0.36 EMI@ PC9003 2200P_0402_50V7K @EMI@ PC9015 0.1U_0402_25V6 PC9002 10U_0805_25V6K 2 2 PC9049 4.7U_0603_6.3V6K LG_VCORE Iocp=34A Ipeak=37A Iocp=44A VCCSA: Imax=4.5A Ipeak=3.15A Height mm 68u_SF000000W00 +VCC_CORE CSN_1a 50 DCR=0.98m ohm +-5% Common part SH000011H00 SW_1a 50 +19VB_CPU PL9005 0.22UH 20% FDUE0640J -H 25A SW1_GT LG1_GT LG1_GT PR9009 +VCC_GT DCR=0.98m ohm +-5% Common part SH000011H00 10_0402_1% CSN_GT1 50 SWN_GT1 50 PC9092 @EMI@ 680P_0603_50V7K @EMI@ PR9010 4.7_1206_5% PQ9007 MDU1511RH_POWERDFN56-8-5 GND PC9090 4.7U_0603_6.3V6K SW EMI@ PC9118 2200P_0402_50V7K @EMI@ PC9117 0.1U_0402_25V6 PR9013 PC9119 2.2_0603_5% 0.22U_0603_16V7K 2 VCC DRVH +19VB_CPU PC9116 10U_0805_25V6K PC9115 10U_0805_25V6K InputCapacitor: 10uF_0805_X5R_25V EN DRVL +5VS PWM InputCapacitor: 10uF_0805_X5R_25V +VCC_GT (Common Part) SH000011H00 7*7*4 3 PQ9009 MDU1511RH_POWERDFN56-8-5 DRVON HG1_GT PWM1_2ph 50 @EMI@ PC9085 0.1U_0402_25V6 PU9003 NCP81151MNTBG_DFN8_2X2 BST FLAG PQ9005 MDU1516URH_POWERDFN56-8-5 EMI@ PC9086 2200P_0402_50V7K PR9005 PC9083 2.2_0603_5% 0.22U_0603_16V7K 2 Iocp=5.4A PC9088 10U_0805_25V6K DRVL Height mm 100u_SF000000I80 Ipeak=28A VCCGT: Imax=25.9A PC9087 10U_0805_25V6K VCC GND + VCC: Imax=19.6A PL9001 0.22UH 20% FDUE0640J -H 25A SW EN (Common Part) SH000011H00 7*7*4 @EMI@ PR9002 4.7_1206_5% PWM SW_VCORE +5VS HG_VCORE 3 PQ9001 MDU1511RH_POWERDFN56-8-5 DRVON DRVH PAD PWM_1a 50 BST 50 1 PU9001 NCP81253MNTBG_DFN8_2X2 change PL9002, PL9003 SM01000C000 to comm part SM01000P200 PL9003 EMI@ HCB2012KF-121T50_0805 @EMI@ PC9073 680P_0603_50V7K PR9001 PC9001 2.2_0603_5% 0.22U_0603_16V7K 2 PQ9003 MDU1511RH_POWERDFN56-8-5 PQ9002 MDU1516URH_POWERDFN56-8-5 PC9014 10U_0805_25V6K InputCapacitor: 10uF_0805_X5R_25V HG_SA D1 G1 D1 D1 D2/S1 G2 S2 2 PC9154 4.7U_0603_6.3V6K SW_SA LG_SA @EMI@ PR9014 4.7_1206_5% DRVL D1 +VCC_SA PL9006 0.47UH 20% MMD-06CZ 17.5A SW_SA ohm DCR=4~4.2m ohm +-5% Common part SH00000ID00 @EMI@ PC9155 680P_0603_50V7K VCC GND SW EN PQ9008 AON7934_DFN3X3A8-10 +5VS PWM 10 S2 S2 DRVON DRVH PWM_1b BST 50 PAD AON7934 Rds(on)=12.4~15.8m PU9004 NCP81253MNTBG_DFN8_2X2 CSN_1b SW_1b 50 50 4 Compal Secret Data Security Classification Issued Date 2014/11/10 Deciphered Date 2016/11/10 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Size C Date: A B C D Compal Electronics, Inc Power Train Document Number Rev 1.0 A4WAS M/B LA-C611P Tuesday, June 16, 2015 Sheet E 51 of 60 PC9078 1U_0201_4V6M PC9077 1U_0201_4V6M PC9076 1U_0201_4V6M PC9075 1U_0201_4V6M PC9074 1U_0201_4V6M PC9172 1U_0201_4V6M PC9173 1U_0201_4V6M PC9174 1U_0201_4V6M 2 1 PC9071 1U_0201_4V6M PC9070 1U_0201_4V6M PC9069 1U_0201_4V6M PC9068 1U_0201_4V6M PC9067 1U_0201_4V6M PC9066 1U_0201_4V6M PC9065 1U_0201_4V6M PC9064 1U_0201_4V6M 2 PC9143 1U_0201_4V6M PC9142 1U_0201_4V6M PC9184 1U_0201_4V6M PC9185 1U_0201_4V6M PC9182 1U_0201_4V6M PC9183 1U_0201_4V6M PC9181 1U_0201_4V6M PC9178 1U_0201_4V6M PC9176 1U_0201_4V6M PC9072 1U_0201_4V6M PC9175 1U_0201_4V6M PC9048 1U_0201_4V6M PC9047 1U_0201_4V6M PC9046 1U_0201_4V6M PC9045 1U_0201_4V6M PC9044 1U_0201_4V6M PC9043 1U_0201_4V6M PC9042 1U_0201_4V6M PC9041 1U_0201_4V6M PC9040 1U_0201_4V6M PC9063 1U_0201_4V6M 2 PC9153 1U_0201_4V6M PC9152 1U_0201_4V6M PC9151 1U_0201_4V6M PC9150 1U_0201_4V6M PC9149 1U_0201_4V6M PC9148 1U_0201_4V6M PC9147 1U_0201_4V6M PC9146 1U_0201_4V6M PC9145 1U_0201_4V6M PC9144 1U_0201_4V6M PC9026 1U_0201_4V6M PC9013 1U_0201_4V6M PC9025 1U_0201_4V6M PC9012 1U_0201_4V6M PC9024 1U_0201_4V6M PC9023 1U_0201_4V6M PC9022 1U_0201_4V6M PC9011 1U_0201_4V6M PC9010 1U_0201_4V6M 2 PC9171 22U_0603_6.3V6M PC9169 22U_0603_6.3V6M PC9164 22U_0603_6.3V6M PC9163 22U_0603_6.3V6M PC9167 22U_0603_6.3V6M PC9165 22U_0603_6.3V6M PC9168 22U_0603_6.3V6M PC9170 22U_0603_6.3V6M 330U_D2_2V_Y 2 2 2 330U_D2_2V_Y PC9039 1U_0201_4V6M 1 1 1 PC9162 1U_0201_4V6M PC9161 1U_0201_4V6M PC9160 1U_0201_4V6M PC9159 1U_0201_4V6M PC9158 1U_0201_4V6M PC9157 1U_0201_4V6M PC9156 1U_0201_4V6M PC9135 22U_0603_6.3V6M PC9134 22U_0603_6.3V6M PC9133 22U_0603_6.3V6M PC9132 22U_0603_6.3V6M PC9131 22U_0603_6.3V6M PC9130 22U_0603_6.3V6M PC9129 22U_0603_6.3V6M PC9128 22U_0603_6.3V6M PC9127 22U_0603_6.3V6M PC9093 PC9052 22U_0603_6.3V6M PC9051 22U_0603_6.3V6M PC9050 22U_0603_6.3V6M PC9180 22U_0603_6.3V6M PC9179 22U_0603_6.3V6M PC9177 22U_0603_6.3V6M PC9028 PC9009 1U_0201_4V6M 2 2 2 2 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 2 PC9141 22U_0603_6.3V6M PC9140 22U_0603_6.3V6M PC9139 22U_0603_6.3V6M PC9138 22U_0603_6.3V6M PC9137 22U_0603_6.3V6M PC9136 22U_0603_6.3V6M PC9114 22U_0603_6.3V6M PC9113 22U_0603_6.3V6M PC9112 22U_0603_6.3V6M PC9111 22U_0603_6.3V6M PC9110 22U_0603_6.3V6M PC9109 22U_0603_6.3V6M PC9108 22U_0603_6.3V6M PC9107 22U_0603_6.3V6M PC9106 22U_0603_6.3V6M PC9126 22U_0603_6.3V6M PC9062 22U_0603_6.3V6M PC9061 22U_0603_6.3V6M PC9060 22U_0603_6.3V6M PC9059 22U_0603_6.3V6M PC9058 22U_0603_6.3V6M PC9057 22U_0603_6.3V6M PC9056 22U_0603_6.3V6M PC9055 22U_0603_6.3V6M PC9054 22U_0603_6.3V6M 330U_D2_2V_Y 2 PC9125 22U_0603_6.3V6M PC9124 22U_0603_6.3V6M PC9123 22U_0603_6.3V6M PC9122 22U_0603_6.3V6M PC9121 22U_0603_6.3V6M PC9120 22U_0603_6.3V6M PC9104 22U_0603_6.3V6M PC9103 22U_0603_6.3V6M PC9102 22U_0603_6.3V6M PC9101 22U_0603_6.3V6M PC9100 22U_0603_6.3V6M PC9099 22U_0603_6.3V6M PC9098 22U_0603_6.3V6M PC9097 22U_0603_6.3V6M PC9105 22U_0603_6.3V6M PC9038 22U_0603_6.3V6M PC9037 22U_0603_6.3V6M PC9036 22U_0603_6.3V6M PC9035 22U_0603_6.3V6M PC9034 22U_0603_6.3V6M PC9033 22U_0603_6.3V6M PC9032 22U_0603_6.3V6M PC9031 22U_0603_6.3V6M PC9030 22U_0603_6.3V6M PC9027 60 of 52 Sheet Tuesday, June 16, 2015 Date: E D Title 2016/11/10 Rev 1.0 Document Number Power Train A4WAS M/B LA-C611P Size C THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Compal Electronics, Inc Compal Secret Data Security Classification Deciphered Date 2014/11/10 Issued Date 2 2 2 2 2 2 1 1 1 1 1 1 +VCC_SA +VCC_GT @ @ PC9053 22U_0603_6.3V6M @ @ @ @ @ @ PC9029 22U_0603_6.3V6M SE00000U200比 比比 , SE00000UC00 1u_0201 故 1u_020 PC9096 22U_0603_6.3V6M PC9095 22U_0603_6.3V6M PC9021 22U_0603_6.3V6M PC9008 22U_0603_6.3V6M PC9007 22U_0603_6.3V6M PC9020 22U_0603_6.3V6M PC9019 22U_0603_6.3V6M PC9018 22U_0603_6.3V6M PC9006 22U_0603_6.3V6M PC9017 22U_0603_6.3V6M PC9005 22U_0603_6.3V6M PC9016 22U_0603_6.3V6M C B A @ @ @ @ @ @ @ + (Common Part) SGA00009S00 @ 3 + + 2@ 1 (Common Part) SGA00009S00 +VCC_SA 543016_543016_SKL_PDG_UY_1_0_pub Total VCORE Output Capacitor: 2014/09/23 22uF_0603_33PCS 1uF_30201_35PCS UNPOP 0603_3PCS 0201_3PCS 330uF_R9_2PCS 1 1uF_0201*7 20140703 22uF_0603*12 +VCC_GT 1uF_0201*14 1uF_0201*6 20150504 D2*1 22uF_0603*32 unpop: 22uF_0603*16 +VCC_CORE 1uF_0201*14 1uF_0201*6 20140923 D2*1 22uF_0603*38 unpop: 22uF_0603*10 1uF_0201*12 1uF_0201*12 22uF_0603*29 22uF_0603*26 20140703 23E: D2*2 22: D2*1 E D C B A +VCC_CORE 4 A B C D E 1 VGA@ ILMT NC BYP NC VGA@ PC1017 1U_0402_6.3V6K PAD 12 Rdown SY8288RAC_QFN20_3X3 1M_0402_1% PR1003 PR1008 0_0402_5% VGA@ PC1002 0.1U_0402_16V7K @ @VGA@ 1 ILMT_1.5VSDGPUP 2 2 1 2 2 +1.5VSDGPUP PJ1002 2 +1.5VSDGPU JUMP_43X118 +3VALW and PC15 VGA Brand Name N16S-GT NV940 VGA@ PR1002 40.2K_0402_1% 1.5VS_DGPU_EN 1 PR1006 20K_0402_1% VRAM Size Voltage @ PR1007 0_0402_5% FB = 0.6V 21 LDO_3V_1.5VSDGPUP Rup VGA@ PC1016 2.2U_0402_6.3V6M 16 Pin BYP is for CS Common NB can delete LDO_3V_1.5VSDGPUP 10 @VGA@ PC1015 22U_0603_6.3V6M NC @VGA@ PC1014 22U_0603_6.3V6M VCC EN 14 17 VGA@ PC1013 22U_0603_6.3V6M GND 20 FB 1.8% +1.5VSDGPUP @ 15 +3VALW LX GND GT@ PR1005 GM2G@ PR1005 30.9K_0402_1% 30.9K_0402_1% VGA@ PC1012 22U_0603_6.3V6M 13 GND 19 VGA@ PC1011 22U_0603_6.3V6M ILMT_1.5VSDGPUP LX VGA@ PC1010 22U_0603_6.3V6M 11 IN 1.527V VGA@ PC1009 22U_0603_6.3V6M 1.5VS_DGPU_EN LX PL1002 VGA@ 1UH_PCMB063T-1R0MS_12A_20% LX_1.5VSDGPUP Ipeak=10A (Common Part) SH00000YE00 PC1001 0.1U_0603_25V7K VGA@ PC1008 330P_0402_50V7K 18 IN VGA@ BST_1.5VSDGPUP 2 BS 1 IN @ PR1001 0_0603_5% PG VGA@ IN 10U_0805_25V6K PC1007 VGA@ @VGA_EMI@ PC1004 0.1U_0402_25V6 change PL1001 SM01000C000 to comm part SM01000P200 GM4G@ PR1005 25.5K_0402_1% PU1001 +19VB_1.5VSDGPUP VGA_EMI@ PC1006 2200P_0402_50V7K +19VB VGA@ PL1001 HCB2012KF-121T50_0805 Imax=7A @VGA_EMI@ @VGA_EMI@ PR1004 PC1003 4.7_1206_5% 680P_0603_50V7K 2SNB_1.5VSDGPUP 1.5VS_DGPU_PW R_EN Change PR1002 from 10K to 40.2K for non GC6 20141219 20,42 N16V-GM 2GB 1.5V(or 1.35V) 4GB 1.5V(or 1.35V) 2GB 1.5V(or 1.35V) VFB=0.6V Vout=0.6V* (1+Rup/Rdown) Vout=1.365V Vout=0.6V* (1+(25.5/20))=1.356 Vout=0.6V* (1+(30.9/20))=1.527 NV920 4GB Only 1.35V The current limit is set to 8A, 12A or 16A when this pin is pull low, floating or pull high Compal Secret Data Security Classification Issued Date 2014/11/10 Deciphered Date 2016/11/10 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Size A3 Date: Compal Electronics, Inc 1.5VSDGPUP Document Number Rev 1.0 A4WAS M/B LA-C611P Tuesday, June 16, 2015 Sheet 53 of 60 A B C D E 1 Module model information SY8032_V2.mdd @ PJ1102 JUMP_43X79 2 +1.05VSDGPUP +1.05VSDGPU VIN_1.05VS VGA@ PC1102 22U_0603_6.3V6M EN LX_1.05VS @ PR1103 0_0402_5% 1SNUB_1.05VS PR1104 10K_0402_1% @ PR1105 1M_0402_1% @ PC1106 0.1U_0402_16V7K Rup FB_1.05VS VGA@ PC1101 @VGA_EMI@ +1.05VSDGPUP Imax= 0.7A, Ipeak= 1.1A PR1106 Rdown 680P_0402_50V7K 10K_0402_1% 2 VGA@ +3VSDGPU_AON DGPU_PWROK 4.7_0603_5% EN_1.05VS 2 10,20,42,55 PR1101 @VGA_EMI@ FB LX GND PG PC1105 VGA@ 22U_0603_6.3V6M IN PC1104 VGA@ 22U_0603_6.3V6M VIN_1.05VS PC1103 VGA@ 68P_0402_50V8J +3VS PL1101 VGA@ 1UH_2.8A_30%_4X4X2_F VGA@ PR1102 7.68K_0402_1% @ PJ1101 JUMP_43X79 2 1 (Common Part) SH00000YG00 4*4*2 VGA@ PU1101 SY8032ABC_SOT23-6 Note: When design Vin=5V, please stuff snubber to prevent Vin damage Vout=0.6V* (1+Rup/Rdown) =>0.6V*(1+(7.68/10)=1.061 =>0.6V*(1+(7.87/10)=1.072 (1.01%) (2.1%) 4 Compal Secret Data Security Classification Issued Date 2014/11/10 Deciphered Date 2016/11/10 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Size C Date: A B C D Compal Electronics, Inc SY8032 Document Number Rev 1.0 A4WAS M/B LA-C611P Tuesday, June 16, 2015 Sheet E 54 of 60 2014/11/10 Issued Date Deciphered Date C PC1211 560U_2.5V_M VGA@ VGA@ Title D Compal Electronics, Inc NVIDIA VGA_CORE Size Document Number Custom Rev 1.0 A4WAS M/B LA-C611P Date: B PC1212 560U_2.5V_M PC1215 PR1212 @VGA_EMI@ @VGA_EMI@ 680P_0402_50V7K 4.7_1206_5% 2016/11/10 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A VGA_EMI@ PC1208 2200P_0402_50V7K @VGA_EMI@ PC1205 0.1U_0402_25V6 VGA@ PC1207 10U_0805_25V6K VGA@ PC1204 10U_0805_25V6K VGA@ PC1203 10U_0805_25V6K VGA@ PC1202 10U_0805_25V6K Compal Secret Data Security Classification N16V-GM VGA@ PC1345 4.7U_0603_6.3V6M 5.6nf VGA@ PC1344 4.7U_0603_6.3V6M 1.8nf 2.7nf N16S-GT VGA@ PC1343 4.7U_0603_6.3V6M PC VGA@ PC1342 4.7U_0603_6.3V6M C VGA@ PC1341 4.7U_0603_6.3V6M 1.74K VGA@ PC1340 4.7U_0603_6.3V6M 3K Near GPU Core VGA@ PC1339 47U_0805_6.3V6M 6.2K PR @RF@_VGA@ PC1333 0.1U_0402_25V6 24K 18K PR Rref2=PR1209 +PR1212 7.5K 3K +VGA_CORE @RF@_VGA@ PC1332 0.1U_0402_25V6 30K 2K @RF@_VGA@ PC1331 0.1U_0402_25V6 20K PR PR Rboot Rref1 20K 27K PR +VGA_CORE @RF@_VGA@ PC1330 0.1U_0402_25V6 39K Rrefadj VGA@ PC1329 4.7U_0603_6.3V6M 20 VGA@ PC1328 4.7U_0603_6.3V6M 20 VGA@ PC1327 4.7U_0603_6.3V6M 96 FSW = 304Khz (R=499K >304Khz) (R=620K >245Khz) Imax=35A Ipeak-51A OCP = 61A OVP=Vout*(145%~155%) Remove GPU OTP circuit for HW request GB2-64 package VGA@ PC1326 4.7U_0603_6.3V6M N of Voltage level VGA@ PC1325 4.7U_0603_6.3V6M 12.5mV VGA@ PC1324 4.7U_0603_6.3V6M 25mV VGA@ PC1323 4.7U_0603_6.3V6M 6.25mV VGA@ PC1337 1U_0402_10V7 1.028V Voltage step VGA@ PC1322 4.7U_0603_6.3V6M 0.9V VGA@ PC1336 1U_0402_10V7 0.9V VGA@ PC1338 4.7U_0603_6.3V6M 1.15V Vboot VGA@ PC1335 1U_0402_10V7 0.9V 1.15V VGA@ PC1320 4.7U_0603_6.3V6M 0.65V 1.2V GPU Core VGA@ PC1334 1U_0402_10V7 0.6V Vmax Vmin +VGA_CORE Under Config D Config C CHOKE:0.36uH, DCR 1.4m ohm, L/2 over 36A PC1321 VGA@ 22U_0603_6.3V6M Config B PWM-VID Spec PQ1201 MDU1516URH_POWERDFN56-8-5 PWM-VID Spec and component Values +VGA_CORE N16S-GT EDP continuous:26A peak: 51A L side Rds(on): 3mohm(Typ), 3.8mohm(Max) Idsm: 11A@Ta=25C, 14A@Ta=70C 1SNUB_VGA2 LG2_VGA +3VS VGA@ PR1223 10K_0402_5% 10,20,42,54 2 PR1221 100_0402_1% 2 PL1203 2 LX2_VGA + VGA@ NVVDD_SENSE_R DGPU_PWROK +VGA_CORE UG2_VGA_R 0.36UH_PDME064T-R36MS1R405_24A_20% PQ1204 MDU1511RH_POWERDFN56-8-5 VCCSENSE_VGA PR1219 0_0603_5% @ UG2_VGA 22 1000P_0402_50V7K + PR1222 @VGA_EMI@ 4.7_1206_5% @VGA@ PC1217 1 @VGA@ PC1218 PC1219 @VGA_EMI@ 680P_0402_50V7K BST2_VGA UG2_VGA_R 0.1U_0603_25V7K NVVDD_GND_SENSE_R VGA@ PC1216 PR1217 0_0603_5% BST2_VGA_R +VGA_CORE +19VB_VGA LX2_VGA @ 1U_0402_16V7K @VGA@ PR1220 0_0402_5% BOOT2 UGATE2 PHASE2 VSSSENSE_VGA 1U_0603_10V6K LG2_VGA +5VS VGA@ PC1214 1SNUB_VGA1 PVCC_VGA 16 22 @VGA@ PR1218 0_0402_5% @VGA@ PR1213 0_0402_5% 2 LG1_VGA VGA@ PL1202 PQ1202 MDU1511RH_POWERDFN56-8-5 19 LX1_VGA 0.1U_0603_25V7K +19VB change PL1201 SM01000C000 to comm part SM01000P200 0.36UH_PDME064T-R36MS1R405_24A_20% LX1_VGA VGA@ PC1201 15 14 13 SS 21 PR1216 100_0402_1% PGOOD RGND VSNS 10 VGA@ PR1214 13K_0402_1% BOOT1 1 EN PSI 20 17 LGATE2 12 PR1215 VGA@ 499K_0402_1% 20,42 BST1_VGA_R 18 PU1201 PVCC VGA@ RT8812AGQW _W QFN20_3X3 TON 3VSDGPU_MAIN_EN @ PR1201 0_0603_5% LGATE1 VREF GND +19VB PL1201 VGA_EMI@ HCB2012KF-121T50_0805 +19VB_VGA GC6@ PR1206 20K_0402_1% VGA@ PR1207 0_0603_5% UG1_VGA UG1_VGA_R PHASE1 REFIN 11 NVVDD_GND_SENSE_R REFADJ UGATE1 REFIN_VGA VGA@ PC1213 1U_0603_25V7K VREF_VGA TON_VGA 2 2 VID VGA@ PC1210 2700P_0402_50V7K @VGA@ PR1224 0_0402_5% +19VB VGA_EN BST1_VGA1 VGA@ PR1210 18K_0402_1% +19VB_VGA NOGC6@ PR1202 20K_0402_1% VGA@ PR1209 20K_0402_1% 1REFADJ VGA@ PR1211 2K_0402_1% E unmount PRV5 for phase select VGA@ PC1209 0.1U_0402_16V7K @ PR1204 0_0402_5% VGA@ PR1208 20K_0402_1% D +3VSDGPU_AON @VGA@ PR1203 10K_0402_5% EN High Threshold = 1.6V VREF_VGA 20 +3VS @ PR1205 10K_0402_5% 0V to 0.8V 1.2V to 1.8V 2.4V to 5.5V PSI 20 DGPU_VID PSI : phase with DEM phase with CCM phase with CCM C B PQ1203 MDU1516URH_POWERDFN56-8-5 A Monday, June 22, 2015 Sheet E 55 of 60 A B C 2.2K Skylake SOC SOC_SMBCLK BG12 SOC_SMBDATA +3VALW_PRIM 2.2K 499 SOC_SML0DATA 499 +3VS SO-DIMM SO-DIMM 2N7002DW SOC_SML0CLK E 2.2K 2.2K BH10 D G-Sensor +3VALW_PRIM 2.2K +3VALW_PRIM 2.2K SOC_SML1CLK SOC_SML1DATA 2 2.2K 2.2K SCL1 SDA1 77 EC_SMB_CK1 78 EC_SMB_DA1 +3VLP_EC 100 ohm 100 ohm ohm ohm KBC SCL2 79 SOC_SML1CLK SDA2 80 SOC_SML1DATA EC_SMB_CK1_CHGR EC_SMB_DA1_CHGR BATTERY CONN 12 11 Charger KB9022 1.8K 1.8K +3VSDGPU_AON I2CS_SCL 2N7002DW I2CS_SDA VGA 4 Compal Secret Data Security Classification 2014/11/10 Issued Date Deciphered Date 2016/11/10 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title SMBUS_Routing_Table Size Document Number Custom B C D Rev 1.0 A4WAS M/B LA-C611P Date: A Compal Electronics, Inc Sheet Tuesday, June 16, 2015 E 56 of 60 Version change list (P.I.R List) Item D Page of for PWR Reason for change Rev PG# Modify List Date Phase 01 Design Change change to the latest 2015 for MOSFET application 01 45 change PQ305 to MDV1528 & PQ306 MDV1527 EVT 02 Design Change change to the latest 2015 for MOSFET application 01 47 change PQ503 to MDV1528 EVT 03 Design Change change to the latest 2015 for MOSFET application 01 51 change PQ9002 & PQ9005 to MDU1516 EVT 04 Design Change change to the latest 2015 for MOSFET application 01 51 change PQ9001, PQ9003, PQ9007 & PQ9009 to MDV1511 EVT 05 Design Change change to the latest 2015 for MOSFET application 01 57 change PQ1201 & PQ1203 to MDU1516 EVT 06 Design Change change to the latest 2015 for MOSFET application 01 57 change PQ1202 & PQ1204 to MDU1511 EVT S5 +0.675VS have a pulse when S0->S5 as attached 01 47 change Pu501 8207P to 8207M EVT S5 8207M output cap is use 330uF poscap 01 47 Delete PC510~PC515 22u*6 EVT S5 8207M output cap is use 330uF poscap 01 47 Add PC510 330u*1 EVT S5 8207M frequency is different with 8207P 02 47 change PR507 to 887k ohm DVT 07 08 09 C Fixed Issue 10 power off pulse issue when S0 -> power off pulse issue when S0 -> power off pulse issue when S0 -> power off pulse issue when S0 -> 11 Design Change Tune +1.5VSDGPUP enable time 02 53 change PR1002 to 40.2k ohm DVT 12 Stop use Anpec LDO Anpec LDO is EOL 02 49 change Pu702 to G971 DVT 13 DFB request pin is too small, avoid open solder 02 44 Change PJP201 SP021210250 (ACES_50458-00801-001_8P-T) to SP020017H00 (CVILU_CI9908M2HR0-NH_8P) DVT Change PR808 to PR822 to PR846 to PR867 to PR842 to PR836 to PR859 to DVT 14 Tune CPU transient Tune CPU transient 02 50 24.9k ohm 24.9k ohm 2.4k ohm 2.4k ohm 36.5k ohm 69.8k ohm 10k ohm D C B B 15 Design Change 02 45 Change PC315 0.1u to 2200p DVT 16 Design Change change 1V output from 1.011V to 1.02V 02 48 Change PR608 13.7k to 14k ohm DVT 17 Tune CPU transient Tune CPU transient 02 50 Change PR846 to 2.43k ohm PR867 to 2.43k ohm PR836 to 71.5k ohm DVT 18 Design Change Change to common part 02 53 Change PL9002, PL9003, PL1001 & PL1201 to common part (HCB2012KF-121T50_0805) 19 thermal request change PH1 from 92degree to 89degree 02 44 Change PR204 from 16.9k ohm to 18.7k ohm DVT A A Compal Secret Data Security Classification Issued Date 2014/11/10 2016/11/10 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Size Custom Date: Compal Electronics, Inc PIR Document Number R ev 1.0 A4WAS M/B LA-C611P Tuesday, June 16, 2015 Sheet 57 of 60 A B C D Version change list (P.I.R List) Page of for HW Item Page 11 CPU 1/9 NA 38 EC 1/9 Reserved protect circuit when adaptor 107% happen, requrie from Acer 10 11 12 13 14 15 38 10 11 11 11 17 18, 19 29, 37 33 35 37, 38 38 38 EC CPU CPU CPU CPU CPU Memory USB LAN WLAN USB EC EC 1/9 1/12 1/12 1/12 1/12 1/12 1/12 1/12 1/12 1/12 1/12 1/12 1/12 Remove unuse part SYS_RESET# Pull-up to ALWAYS power rails Reserved PD for G_INT# NA Separate RPC18 for easy PU Reserved for Cannonlake-U (2014MOW52) Change CIS Symbol and Footprint Change CIS Symbol and Footprint Reserved path for +3V_LAN Disconnect SUSCK to M.2 connector to avoid leakage current Control USB Charger behavior when disabel USB charger funct i on Board ID change to DVT Remove unuse part 16 39 LED 1/12 LED light adjust 17 18 LID PTP 1/12 1/12 Change Hall Sensor IC Add level shift for PTP I2C interface 19 20 21 22 23 24 25 39 39 11 41 42 06 36 39 08 09, 40 Others Sequence Debug HDD Others SPI DMIC 1/12 1/12 1/15 1/15 1/15 1/20 1/20 Follow DFX requriement For power off sequence Reserved for power on select Pin def i nit on modif y Pin def i nit on modif y Remove/Un-Pop unuse part Reserved DMIC path from SOC 26 27 28 29 30 31 32 33 22 30 35 38 39 40 40 41 NV Others WLAN Sequence LED Audio Audio Others 1/20 1/20 1/20 1/20 1/20 1/20 1/20 1/20 Update HYNIX C die straps table Remove unuse part Separate M.2 pin32 and 46 for Intel WLAN 3165 For power down sequence Update CIS Symbol and Footprint Update BOM Structure Adjust MONO_IN input voltage Change reset signal Others 1/20 Change ohm to R-Short Title 34 E Issue Description Date 35 36 37 38 20 30 30 38 NV HDMI HDMI EC 1/28 1/28 1/28 1/28 Remove unuse part Remove unuse part Change U52 main source (HDMI power switch) Un-use part change to @ 40 06 CMC 2/4 Change XDP to CMC 41 08 LPC 2/4 Solution Description Change ohm to R-Short Phase Rev Reserved RC189(0 ohm) for DGPU_AC_DETECT Change net from VCOUT1_PROCHOT# to VCOUT1_PROCHOT Change U4901.117 from SEN_DET# to SW_PROCHOT# Reserved Q2010A/B for SW_PROCHOT# and DGPU_AC_DETECT Add R4960 for SW_PROCHOT# and VCOUT1_PROCHOT Rename R4938.2 to SW_PROCHOT# Delete R4905, R619, R4958 Change RPC11.6 to +3VALW_PRIM Reserved RC117 for G_INT# Move RC212 to Page06 and add note for EC_SCI# Change RPC18 to RC126, RC127 (1K) and RC128, RC129 (2.2K) Connect UC1.U11/U12 to +1.8VALW_PRIM and reserved CC79 for UC1.U11/U12 Change CD16,CD46 PN to SGA00009S00 Change L24,L25,L26,L28,L29,L30, L27 CIS Symbol to SM070003Y00 Reserved R214 0_0850 for +3V_LAN R426 change to 0_0402 @ Change R854.1 from SUSP# to USB_CB and U4901.70 from OPMODE to USB_CB Change R4903 from 0_0402_5% to 12K_0402_5% Delete R4957, R4959 Change R3 to 560 ohm and change R6 to 430 ohm Change R2633.2 to +3VLP DVT 0.2 DVT 0.2 DVT DVT DVT DVT DVT DVT DVT DVT DVT DVT DVT DVT DVT 0.2 0.2 0.2 0.2 0.2 0.2 0.2 0.2 0.2 0.2 0.2 0.2 0.2 DVT 0.2 Change U3 to SA00008K800 (ANPEC) Add Q2012A/B, R2641, R2642, R2639, R2640 Change RC128,RC129 PU to +3VALW_PGPPC Change H17 from 3P2 to 3P3 Add R1000, R1002, Q2013, Q2014, Q2016 for tCPU17, tCPU18, tCPU28, tPLT15 Reserved RC53, RC54 for JAPS1.11 JHDD2.10 connect to GND JLID1.2 change to LID_SW#, JLID1.3 NC Del RC203 and change un-pop RPC6 Reserved R481, R482 for PCH_DMIC_CLK/DATA from UC1.H5/D7 Add R483, R484 0_0402 for Audio DMIC Update HYNIX C die straps table Del R377, R378, R376 JNGFF1.32 change to NC (for Intel 3165) Add D27 for EC_VCCST_PG_R Update LED1, LED2 CIS Symbol Change R2135, R2151 to EMC@ Change R2140 to 27K and R2138 to 27K(@) Mount R2631 and un-mount R2632 0_0603 to R-Short: R2075, R81, RC176, RC209 0_0402 to R-Short: R2131, RC172, R472, R927, R2552, R4953, R4956, RC178, RC197, R427,R428 Del D2002, R2055 DEL ZZZ1 (HDMI ROYALTY) U52 change to SA00004ZA00 R4943 change to @ Change JXDP1 CIS symbol to CMC CIS Symbol(JPCMC1) Del RPC3, RC22, RC25, RC20, RC14, CC120, CC121, RPC4 Rerout i ng RPC2, RPC4, RPC15, RC23, RC151 Add RC17, RC55, RC56 Change RC37 to @ Change XDP@ to CMC@ Change RPC8 to RC144~ RC147 ohm R-short DVT 0.2 DVT 0.2 DVT DVT DVT DVT DVT DVT 0.2 0.2 0.2 0.2 0.2 0.2 DVT 0.2 DVT DVT DVT DVT DVT DVT DVT DVT 0.2 0.2 0.2 0.2 0.2 0.2 0.2 0.2 DVT 0.2 DVT DVT DVT DVT 0.2 0.2 0.2 0.2 DVT 0.2 DVT 0.2 Compal Secret Data Security Classification Issued Date 2014/11/10 2016/11/10 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Size Custom Date: A B C D Compal Electronics, Inc PIR-HW1 Document Number Rev 1.0 A4WAS M/B LA-C611P Tuesday, June 16, 2015 Sheet E 58 of 60 A B C D Version change list (P.I.R List) Item Page Title Page of for HW Issue Description Date Solution Description 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 10 10 10 12 10 13 06 17 19 29,37 10 41 14 40 08 08 18,19 35 39 SOC SOC SOC SOC SOC SOC SOC DIMM USB Chock Crystal D-Cover PCH DMIC SPI Crystal Memory SUSCLK Others 2/4 2/4 2/4 2/4 2/5 2/5 2/9 2/9 2/9 2/9 2/11 2/25 2/26 3/2 3/3 3/3 3/3 3/3 3/3 Remove unuse part Add T164/T165 for CLK_CPU_ITP/CLK_CPU_ITP# Change Material of AND gate Follow PCH EDS1.2 add PD resistor when un-use USB Reserved PD resistor (2014MOW48) Reserved path for VCCIO Reserved path for TP_INT# Reserved power source for U11/U12 Remove un-use part Swap net because update CIS Symbol Update 32.768KHz Crystal to 9pF Reserved SW5 for memory door on D-Cover Reserved for Intel PDG1.2 Table52-9 Follow PDG1.2 Table28-3 2015MOW06 no need PU1K on SPI_IO2/IO3 Modify for 9pF Cyrstal Mount decoupling capacitor Del SUSCLK and reserved TP(Reqruie from Acer) Un-mount un-use part 61 08 SMBUS 3/3 Add level shift for SOC_SMBCLK/SOC_SMBDATA 62 08 Others 4/1 Delete reserved component 63 08 SMBUS 4/1 Add BOM Structure for SPI ROM SMBUS SPI Others Others 4/1 4/1 4/1 4/1 LID Others Others Others 4/1 4/1 4/1 4/8 Delete EC SPI path MOW36 QS sample no need to PD Change ohm to R-Short SMT require delete un-use ohm to avoid USB chock solder issue For 2nd source hall sensor soultion PD for HPD signal Board ID Change for PVT Add discharge circuit for +1.05VSDGPU 64 65 66 67 68 69 70 71 08 08 13,39,41 37 38 30,31 38 42 72 30,37,40 Others 4/14 Change ohm to R-Short 73 37,38 Others 4/16 Change U77 pin4 control by EC GPIO CPU Audio CPU Others GPU CPU 4/17 4/17 4/22 4/22 4/30 4/30 74 75 76 77 78 79 12 40 06 06 22, 25 03, 07 E Follow MOW10, USB2_ID/USB2_VBUSSENSE connect to GND Beep Sound Path from EC Add test point for CATERR# Cancel JAPS1 Mask to avoide soldering issue Add Samsung E-Die VRAM Information Add QS sample CPU for BOM Selection Phase Rev Del RC108 Add T164/T165 for CLK_CPU_ITP/CLK_CPU_ITP# Change UC3 to SA00000OH00 Add RC130, RC131 for USB2_ID and USB2_VBUSSENSE Reserved RC136 for Cannonlake-U Reserved U4902, C977 Reserved RC137 Add RC57 for UC1.U11/U12 Del CD46 SWAP net of L24,L25,L26,L28,L29,L30,L27 Change YC2 PN to SJ10000L000 Reserved SW5(@) Reserved CC123, CC124,CC125 R481,R482 change to 33 ohm Un-Mount RC47 Change CC15,CC16 to 8.2pF Mount and change CD1, CD17, CD28, CD47 to 0.1U_0402 Del R426, C85 and add T3806 Un-mount SW3 change RC202, RC49, RC50, RPC7 PU to +3VALW_PRIM add Q2017, RC220, RC221, RC222, RC223 change net name from SOC_SMBCLK/SOC_SMBDATA to SOC_SMBCLK_1/SOC_SMBDATA_1 change RPC7 PU to 2.2K Del RPC8, RC45, RPC6 Change RPC5 and RC52 to 15 ohm with 8M_SINGLE@ Add RPC5 and RC52 33 ohm with 8M_DUAL@ Add reserved component UC2 with 8M_DUAL@ DVT DVT DVT DVT DVT DVT DVT DVT DVT DVT DVT DVT DVT DVT DVT DVT DVT DVT DVT 0.2 0.2 0.2 0.2 0.2 0.2 0.2 0.2 0.2 0.2 0.2 0.2 0.2 0.2 0.2 0.2 0.2 0.2 0.2 DVT 0.2 PVT 0.3 PVT 0.3 Del RPC6 Change RC51 to ES@ 0_0402 to R-Short: R2631, R2634, RC168, RC186 Del R458, R461, R465, R466 PVT PVT PVT PVT 0.3 0.3 0.3 0.3 Mount R618 Add R380 PD100K, Mount R2530 change R4903 to 15K Mount Q2008, R574, R1001 0_0402 to R-Short: R368,R369, R370, R371, R372,R373, R374, R375 R473, R474, R475, R476, R477, R478, R479, R480 0_0603 to R-Short: R2135, R2151 PVT PVT PVT PVT 0.3 0.3 0.3 0.3 PVT 0.3 link U77.4 to U4901.119 Un-mount R857 Change RC130, RC131 to ohm Change R2138, R2140 to 22K and mount R2138 Add T166 change JAPS1 footprint to ACES_50506-01841-P01_18P-NPM Add X76629BOL13/X76629BOL14 Add UC1 with QJFC@/QJ8N@/QJ8L@ PVT 0.3 PVT PVT PVT PVT PVT PVT 0.3 0.3 0.3 0.3 0.3 0.3 4 Compal Secret Data Security Classification Issued Date 2014/11/10 2016/11/10 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Size Custom Date: A B C D Compal Electronics, Inc PIR-HW2 Document Number Rev 1.0 A4WAS M/B LA-C611P Tuesday, June 16, 2015 Sheet E 59 of 60 A B C D Version change list (P.I.R List) Item Page Title 80 81 82 83 84 85 86 42 38 38 01 39 38 39 Others Others Others Others Others Others Others Page of for HW Issue Description Date 5/14 5/28 5/28 6/17 6/22 7/14 7/14 E Solution Description BOM Error For abnormal shutdown Board ID change to Rev1.0 Update PCB Rev10 PN Cancel the MASK of JLID1 Add C4917 for EC_RST# Add S spec number for i3/i5/i7 CPU Phase Change R574, R1001, Q2008 to VGA@ Mount D26 Change R4903 to 20K_0402_1% Update PCB PN to DAZ1DR00100 Change JLID1 to ACES_50506-01041-P01_10P-NPM Add C4917 add SR2EU@/SR2EY@/SR2EZ@ for UC1 MP number Rev Pre-MP Pre-MP Pre-MP Pre-MP Pre-MP Pre-MP Pre-MP 1.0 1.0 1.0 1.0 1.0 1.0 1.0 2 3 4 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2013/10/30 2014/05/24 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title PIR-HW Size Document Number Custom Date: A B C D Rev 1.0 Z5WAH M/B LA-B161P Friday, July 17, 2015 Sheet E 60 of 60 ... 90 92 94 96 98 10 0 10 2 10 4 10 6 10 8 11 0 11 2 11 4 11 6 11 8 12 0 12 2 12 4 12 6 12 8 13 0 13 2 13 4 13 6 13 8 14 0 14 2 14 4 14 6 14 8 15 0 15 2 15 4 15 6 15 8 16 0 16 2 16 4 16 6 16 8 17 0 17 2 17 4 17 6 17 8 18 0 18 2 18 4 18 6 18 8... PC 815 0. 1U _04 02 _16 V7K 10 0 _04 02 _1% 11 0_ 0 402 _1% 2 VSN_1a PR843 1K _04 02 _1% PR858 15 .4K _04 02 _1% 15 PC824 2 200 P _04 02_50V8J PC8 30 10 00P _04 02_50V7K PR857 88.7K _04 02 _1% 10 0 _04 02 _1% PC 819 470P _04 02_50V7K... 24K _04 02 _1% 2 PC 817 10 00P _04 02_50V7K 10 11 12 PC8 01 0. 01U _04 02_50V7K PR8 31 75K _04 02 _1% 22@ PR833 12 .4K _04 02 _1% 220P _04 02_50V7K VSN_2ph PC 8 10 10 00P _04 02_50V7K 2 1 PR8 30 16 5K _04 02 _1% PR825 69.8K _06 03 _1%