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A B C D E Compal Confidential Model Name : Ezel_CX Board NO: LA-A001P 1 PCB ZZZ DA8000WC200 PCB 0YO LA-A001P REV0 M/B S * DA8000WC210 PCB 0YO LA-A001P REV1 M/B S LA-A001P REV0 M/B S DA8000WC210 updated for new panelization Compal Confidential V5MM1 M/B Schematics Document 2 Intel Chief River (Ivy Bridge 2C BGA+ Pather Point) with On Board DRAM, 1Rx8, pcs Nvidia N14P-GT with GDDR5*8 2012-03-12 REV:1.0 3 Panelization Information Main Board LA-A001P I/O Board LS-A001P Sensor Board LS-A002P Re-driver Board LS-A003P LAN Board LS-A004P LED Board LS-A005P PWR Board LS-A006P E-Compass Board LS-A007P 4 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2011/12/13 Date of EOP Deciphered Date Title Cover Page THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Rev 1.0 Ezel_CX MB_LA-A001P Date: A B C D Wednesday, March 13, 2013 Sheet E of 64 A B C D E eDP eDP Connector 4-Lane Reserved Page 32 DDR3 SO-DIMM x1 If Necessary GDDR5 1.5V GDDR5 1.5V Re-Driver Board GDDR5 1.5V PEG NVIDIA N14P-GT(35W) FCBGA908 GDDR5 1.5V BANK 0, 1, 2, 3, ,5 ,6 ,7 Intel Ivy Bridge ULV Processor 2C BGA1023 1.5V DDRIII 1333 /1600 MHz Page 4~10 PCIe Gen-2, 8-Lane, 5GT/s Page 12 FDI x8 DMI Gen 2x USB Port Page 22~30 USB2.0 USB Charger USB 3.0 Ext Connector (Upper-Left) USB3.0 Port USB Port DPB HDMI Connector USB3.0 Cost Reduced Page 34 DDR3 Memory Down, 1Rx8, pcs with GDDR5, pcs Dongle Port PWR Controlling Page 11 DDR3 SDRAM Memory BUS USB 3.0 Ext Connector (Lower-Left) USB 3.0 Port Page 32 Page 36 DPD mini-DP Connector Dongle Port Controller CMOS Camera Intel Panther Point BGA 989 Balls HM77 USB3.0 Port with TI HD3SS2521 USB2.0 Port USB port 10 USB port 11 USB port 12 Port0 On Sensor Board HDD Connecotr Page 37 Port1 Full Mini-Card mSATA HD Audio I/F Port3 Page 35 Page 13~21 SPI Bus I/O Board Connector Page 37 Page 35 Touch Panel Sensor Hub SATA 3.0 PCIE BUS 1/2 Mini Card WLAN/WiFi Through Function Cable Page 32 Page 33 Port2 Function Cable M/B Side Connector USB port LPC Bus USB port Card Reader RTS5229 SD3.0 HDA Codec ALC3225-CG Combo-Jack Page 40 DMIC Array Page 41 W25Q32BVSSIG(8MB) Amplifier ALC1001-CGT W25Q16CVSSIG(2MB) 3 Placeholder Reserved Only, Page 14 USB 2.0 Only External Connector TPM SLB9655TT1.2 On I/O Board Int SPKR CONN Right Side Int SPKR CONN Left Side Page 43 Page 41 DC/DC Interface PWR D/B Page 39 Page 44 PWM FAN User Interface EC ENE 9012 Page 38 Page 42 Page 39 LED D/B Page 39 Click Pad Connector KB Connector Page 39 4 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2011/06/02 Deciphered Date Date of EOP Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Block Diagrams Rev 1.0 Ezel_CX MB_LA-A001P Date: A B C D Wednesday, March 13, 2013 E Sheet of 64 A B C STATE System Power Rails HIGH HIGH ON ON ON ON HIGH HIGH ON ON ON LOW S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF VIN Adapter power supply (19V) N/A ON ON ON BATT+ Battery power supply (12.6V) N/A N/A N/A N/A B+ AC or battery power rail for power circuit ON ON ON ON +VSB +VSB for power rails to control sequence ON ON ON ON +CPU_CORE Power Supply for CPU Core Power Well ON OFF OFF OFF +VGFX_CORE Power Supply for incorporated GPU ON OFF OFF OFF +5VALW 5V Power Source from 3V/5V IC ON ON ON ON Board ID / SKU ID Table for AD channel +5VALW_PCH 5V Power Supply for PCH VccSus Power Well ON ON ON* ON* +5VS from 5VALW, power supply for 5V device ON OFF OFF OFF +3VALW 3V Power Source from 3V/5V IC ON ON ON ON +3VALW_PCH 3V Power Supply for PCH VccSus Powr Well ON ON ON* ON* +3VS from 3VALW, power supply for 3V device ON OFF OFF OFF +VCCSA power supply for CPU System Agent Voltage ON OFF OFF OFF +1.8VS use 3VALW source, for CPU VDDPLL and PCH LVDS power ON OFF OFF OFF +1.5V use 5VALW source, for DDR3 and for 1.5VS Gate ON ON OFF OFF +1.5VS from 1.5V, power supply for CPU memory controller and PCH ON OFF OFF OFF +1.05VS_VTT source from 5VALW, for CPU VCCIO and PCH Core Power Well ON OFF OFF OFF +0.75VS source from internal LDO of PU501, for DDR3 terminator ON OFF OFF OFF +3V_LAN 3V power supply for RTL8111GS-CG LAN IC(on D/B) ON ON OFF* OFF* +3VS_WLAN 3V power supply for WLAN ON OFF* OFF* OFF* +3VS_DGPU 3V powr source for dGPU ON OFF OFF OFF VGA_CORE Core power for dGPU ON OFF OFF OFF +1.5VSDGPU 1.5V for VRAM and memory controller of dGPU ON* OFF OFF OFF +1.05VSDGPU 1.05V power source for dGPU ON OFF OFF OFF Device Address Smart Battery 0001 011X b Charger IC 0001 0010 b EC SM Bus2 address Device On Board Thermal Senser Vcc Ra/Rc/Re Board ID 3.3V +/- 5% 100K +/- 5% Rb / Rd / Rf 8.2K +/- 5% 18K +/- 5% 33K +/- 5% 56K +/- 5% 100K +/- 5% 200K +/- 5% NC V AD_BID V 0.216 V 0.436 V 0.712 V 1.036 V 1.453 V 1.935 V 2.500 V V AD_BID typ V 0.250 V 0.503 V 0.819 V 1.185 V 1.650 V 2.200 V 3.300 V Board ID ChannelA V AD_BID max V 0.289 V 0.538 V 0.875 V 1.264 V 1.759 V 2.341 V 3.300 V BTO Option Table BOARD ID Table BTO Item BOM with dGPU UMA Only with GC6 w/o GC6 daul-mode suppored EMI solution ESD solution RF solution reserved for EMC PCB Revision 0.1 0.2 0.3 0.4 IOAC supported Structure dGPU@ UMAO@ GC6@ NGC6@ DM@ EMI@ ESD@ RF@ XEMC@ NDM@ IOAC@ no stuff Connector @ CONN@ i3-3227U i5-3337U i7-3537U 3227@ 3337@ 3537@ PCH HM77 HM77@ daul-mode not suppored Address Address DIMM0 A0 1010 000X JDIMM1(SPD) USB Port Table USB 2.0 USB 1.1 Port 10 11 12 13 UHCI0 UHCI1 EHCI1 UHCI2 UHCI3 UHCI4 EHCI2 UHCI5 UHCI6 1001_101xb PCH SM Bus address Device Clock HIGH ON EC SM Bus1 address +VS HIGH S5 ON OFF*: always connected is not supported by default +V LOW S4 ON ON*: 1.5VSDGPU will be switched off by GC6 toggleed +VALW HIGH S3 ON Description E S1(Power On Suspend) S0 RTC power ON*: if no need to disable for Erp Lot Full ON SLP_S1# SLP_S3# SLP_S4# SLP_S5# +RTCVCC Power Plane D SIGNAL USB 3.0 Port XHCI External USB Port USB3.0 port with charging (upper) USB3.0 port (lower) Lightning-Bolt with TI solution ELPIDA DRAM Chip USB external port (upper) USB external port (lower) Lightning-Bolt with TI solution VRAM Hynix-MFR VRAM Hynix-AFR ELPIDA@ HYNMFR@ HYNAFR@ Mini-Card for WiFi External port- USB 2.0 only CMOS Camera Touch Panel Sensor Hub Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2011/12/13 Date of EOP Deciphered Date Title Notes List THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Rev 1.0 Ezel_CX MB_LA-A001P Date: A B C D Wednesday, March 13, 2013 Sheet E of 64 A B C D E PEG_RCOMPO and PEG_ICOMPI should be connected together with 4-mil width first Then be connected to R1 from ball of PEG_ICOMPI PEG_ICOMPO should be connected to R1 with width 12-mil No longer than 500-mil to above two 1 +1.05VS_VTT R1 CPU UCPU1 S IC AV8063801119500 SR0XF L1 1.9G ABO! 3227@ SA00006D990 AV8063801119500 SR0XF L1 1.9G S IC AV8063801129900 SR0XL L1 1.8G ABO! 3337@ SA00006D860 AV8063801129900 SR0XL L1 1.8G UCPU1 S IC AV8063801119700 SR0XG L1 2G ABO! 3537@ SA00006DB90 DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 DMI_CRX_PTX_P3 DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3 DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3 N3 P7 P3 P11 K1 M8 N4 R2 K3 M7 P4 T3 DMI_RX#[0] DMI_RX#[1] DMI_RX#[2] DMI_RX#[3] DMI_RX[0] DMI_RX[1] DMI_RX[2] DMI_RX[3] PEG_RX#[0] PEG_RX#[1] PEG_RX#[2] PEG_RX#[3] PEG_RX#[4] PEG_RX#[5] PEG_RX#[6] PEG_RX#[7] PEG_RX#[8] PEG_RX#[9] PEG_RX#[10] PEG_RX#[11] PEG_RX#[12] PEG_RX#[13] PEG_RX#[14] PEG_RX#[15] DMI UCPU1 DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 DMI_CRX_PTX_N2 DMI_CRX_PTX_N3 M2 P6 P1 P10 DMI_TX#[0] DMI_TX#[1] DMI_TX#[2] DMI_TX#[3] DMI_TX[0] DMI_TX[1] DMI_TX[2] DMI_TX[3] 1 R2 1K_0402_5% FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7 FDI_FSYNC0 FDI_FSYNC1 FDI_INT FDI_LSYNC0 FDI_LSYNC1 U6 W10 W3 AA7 W7 T4 AA3 AC8 AA11 AC12 U11 AA10 AG8 FDI0_TX#[0] FDI0_TX#[1] FDI0_TX#[2] FDI0_TX#[3] FDI1_TX#[0] FDI1_TX#[1] FDI1_TX#[2] FDI1_TX#[3] FDI0_TX[0] FDI0_TX[1] FDI0_TX[2] FDI0_TX[3] FDI1_TX[0] FDI1_TX[1] FDI1_TX[2] FDI1_TX[3] FDI0_FSYNC FDI1_FSYNC FDI_INT FDI0_LSYNC FDI1_LSYNC R3 U7 W11 W1 AA6 W6 V4 Y2 AC9 Intel(R) FDI +1.05VS_VTT +1.05VS_VTT FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7 24.9_0402_1% EDP_COMP CPU_EDP_HPD# CPU_EDP_HPD# EDP_AUXN EDP_AUXP EDP_TXN0 EDP_TXN1 EDP_TXN2 EDP_TXN3 EDP_TXP0 EDP_TXP1 EDP_TXP2 EDP_TXP3 EDP_AUXN EDP_AUXP AG4 AF4 EDP_TXN0 EDP_TXN1 EDP_TXN2 EDP_TXN3 AC3 AC4 AE11 AE7 EDP_TXP0 EDP_TXP1 EDP_TXP2 EDP_TXP3 AC1 AA4 AE10 AE6 eDP_COMPIO eDP_ICOMPO eDP_HPD# eDP_AUX# eDP_AUX eDP_TX#[0] eDP_TX#[1] eDP_TX#[2] eDP_TX#[3] eDP_TX[0] eDP_TX[1] eDP_TX[2] eDP_TX[3] eDP AF3 AD2 AG11 PCI EXPRESS GRAPHICS AV8063801119700 SR0XG L1 2G G3 G1 G4 PEG_ICOMPI PEG_ICOMPO PEG_RCOMPO PEG_RX[0] PEG_RX[1] PEG_RX[2] PEG_RX[3] PEG_RX[4] PEG_RX[5] PEG_RX[6] PEG_RX[7] PEG_RX[8] PEG_RX[9] PEG_RX[10] PEG_RX[11] PEG_RX[12] PEG_RX[13] PEG_RX[14] PEG_RX[15] PEG_TX#[0] PEG_TX#[1] PEG_TX#[2] PEG_TX#[3] PEG_TX#[4] PEG_TX#[5] PEG_TX#[6] PEG_TX#[7] PEG_TX#[8] PEG_TX#[9] PEG_TX#[10] PEG_TX#[11] PEG_TX#[12] PEG_TX#[13] PEG_TX#[14] PEG_TX#[15] PEG_COMP 24.9_0402_1% UCPU1A to improve thermal problem and base upon request from our end-customer, change PEG CFG to 8X on 2013/03/10 H22 J21 B22 D21 A19 D17 B14 D13 A11 B10 G8 A8 B6 H8 E5 K7 PEG_GTX_C_HRX_N15 PEG_GTX_C_HRX_N14 PEG_GTX_C_HRX_N13 PEG_GTX_C_HRX_N12 PEG_GTX_C_HRX_N11 PEG_GTX_C_HRX_N10 PEG_GTX_C_HRX_N9 PEG_GTX_C_HRX_N8 PEG_GTX_C_HRX_N7 PEG_GTX_C_HRX_N6 PEG_GTX_C_HRX_N5 PEG_GTX_C_HRX_N4 PEG_GTX_C_HRX_N3 PEG_GTX_C_HRX_N2 PEG_GTX_C_HRX_N1 PEG_GTX_C_HRX_N0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 @ 0.22U_0402_6.3V6K @ 0.22U_0402_6.3V6K @ 0.22U_0402_6.3V6K @ 0.22U_0402_6.3V6K @ 0.22U_0402_6.3V6K @ 0.22U_0402_6.3V6K @ 0.22U_0402_6.3V6K @ 0.22U_0402_6.3V6K dGPU@0.22U_0402_6.3V6K dGPU@0.22U_0402_6.3V6K dGPU@0.22U_0402_6.3V6K dGPU@0.22U_0402_6.3V6K dGPU@0.22U_0402_6.3V6K dGPU@0.22U_0402_6.3V6K dGPU@0.22U_0402_6.3V6K dGPU@0.22U_0402_6.3V6K PEG_GTX_HRX_N15 PEG_GTX_HRX_N14 PEG_GTX_HRX_N13 PEG_GTX_HRX_N12 PEG_GTX_HRX_N11 PEG_GTX_HRX_N10 PEG_GTX_HRX_N9 PEG_GTX_HRX_N8 PEG_GTX_HRX_N7 PEG_GTX_HRX_N6 PEG_GTX_HRX_N5 PEG_GTX_HRX_N4 PEG_GTX_HRX_N3 PEG_GTX_HRX_N2 PEG_GTX_HRX_N1 PEG_GTX_HRX_N0 K22 K19 C21 D19 C19 D16 C13 D12 C11 C9 F8 C8 C5 H6 F6 K6 PEG_GTX_C_HRX_P15 PEG_GTX_C_HRX_P14 PEG_GTX_C_HRX_P13 PEG_GTX_C_HRX_P12 PEG_GTX_C_HRX_P11 PEG_GTX_C_HRX_P10 PEG_GTX_C_HRX_P9 PEG_GTX_C_HRX_P8 PEG_GTX_C_HRX_P7 PEG_GTX_C_HRX_P6 PEG_GTX_C_HRX_P5 PEG_GTX_C_HRX_P4 PEG_GTX_C_HRX_P3 PEG_GTX_C_HRX_P2 PEG_GTX_C_HRX_P1 PEG_GTX_C_HRX_P0 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 @ 0.22U_0402_6.3V6K @ 0.22U_0402_6.3V6K @ 0.22U_0402_6.3V6K @ 0.22U_0402_6.3V6K @ 0.22U_0402_6.3V6K @ 0.22U_0402_6.3V6K @ 0.22U_0402_6.3V6K @ 0.22U_0402_6.3V6K dGPU@0.22U_0402_6.3V6K dGPU@0.22U_0402_6.3V6K dGPU@0.22U_0402_6.3V6K dGPU@0.22U_0402_6.3V6K dGPU@0.22U_0402_6.3V6K dGPU@0.22U_0402_6.3V6K dGPU@0.22U_0402_6.3V6K dGPU@0.22U_0402_6.3V6K PEG_GTX_HRX_P15 PEG_GTX_HRX_P14 PEG_GTX_HRX_P13 PEG_GTX_HRX_P12 PEG_GTX_HRX_P11 PEG_GTX_HRX_P10 PEG_GTX_HRX_P9 PEG_GTX_HRX_P8 PEG_GTX_HRX_P7 PEG_GTX_HRX_P6 PEG_GTX_HRX_P5 PEG_GTX_HRX_P4 PEG_GTX_HRX_P3 PEG_GTX_HRX_P2 PEG_GTX_HRX_P1 PEG_GTX_HRX_P0 G22 C23 D23 F21 H19 C17 K15 F17 F14 A15 J14 H13 M10 F10 D9 J4 PEG_HTX_GRX_N15 PEG_HTX_GRX_N14 PEG_HTX_GRX_N13 PEG_HTX_GRX_N12 PEG_HTX_GRX_N11 PEG_HTX_GRX_N10 PEG_HTX_GRX_N9 PEG_HTX_GRX_N8 PEG_HTX_GRX_N7 PEG_HTX_GRX_N6 PEG_HTX_GRX_N5 PEG_HTX_GRX_N4 PEG_HTX_GRX_N3 PEG_HTX_GRX_N2 PEG_HTX_GRX_N1 PEG_HTX_GRX_N0 C33 C34 C35 C36 C37 C38 C39 C40 C41 C42 C43 C44 C45 C46 C47 C48 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 @ 0.22U_0402_6.3V6K @ 0.22U_0402_6.3V6K @ 0.22U_0402_6.3V6K @ 0.22U_0402_6.3V6K @ 0.22U_0402_6.3V6K @ 0.22U_0402_6.3V6K @ 0.22U_0402_6.3V6K @ 0.22U_0402_6.3V6K dGPU@0.22U_0402_6.3V6K dGPU@0.22U_0402_6.3V6K dGPU@0.22U_0402_6.3V6K dGPU@0.22U_0402_6.3V6K dGPU@0.22U_0402_6.3V6K dGPU@0.22U_0402_6.3V6K dGPU@0.22U_0402_6.3V6K dGPU@0.22U_0402_6.3V6K PEG_HTX_C_GRX_N15 PEG_HTX_C_GRX_N14 PEG_HTX_C_GRX_N13 PEG_HTX_C_GRX_N12 PEG_HTX_C_GRX_N11 PEG_HTX_C_GRX_N10 PEG_HTX_C_GRX_N9 PEG_HTX_C_GRX_N8 PEG_HTX_C_GRX_N7 PEG_HTX_C_GRX_N6 PEG_HTX_C_GRX_N5 PEG_HTX_C_GRX_N4 PEG_HTX_C_GRX_N3 PEG_HTX_C_GRX_N2 PEG_HTX_C_GRX_N1 PEG_HTX_C_GRX_N0 F22 A23 D24 E21 G19 B18 K17 G17 E14 C15 K13 G13 K10 G10 D8 K4 PEG_HTX_GRX_P15 PEG_HTX_GRX_P14 PEG_HTX_GRX_P13 PEG_HTX_GRX_P12 PEG_HTX_GRX_P11 PEG_HTX_GRX_P10 PEG_HTX_GRX_P9 PEG_HTX_GRX_P8 PEG_HTX_GRX_P7 PEG_HTX_GRX_P6 PEG_HTX_GRX_P5 PEG_HTX_GRX_P4 PEG_HTX_GRX_P3 PEG_HTX_GRX_P2 PEG_HTX_GRX_P1 PEG_HTX_GRX_P0 C49 C50 C51 C52 C53 C54 C55 C56 C57 C58 C59 C60 C61 C62 C63 C64 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 @ 0.22U_0402_6.3V6K @ 0.22U_0402_6.3V6K @ 0.22U_0402_6.3V6K @ 0.22U_0402_6.3V6K @ 0.22U_0402_6.3V6K @ 0.22U_0402_6.3V6K @ 0.22U_0402_6.3V6K @ 0.22U_0402_6.3V6K dGPU@0.22U_0402_6.3V6K dGPU@0.22U_0402_6.3V6K dGPU@0.22U_0402_6.3V6K dGPU@0.22U_0402_6.3V6K dGPU@0.22U_0402_6.3V6K dGPU@0.22U_0402_6.3V6K dGPU@0.22U_0402_6.3V6K dGPU@0.22U_0402_6.3V6K PEG_HTX_C_GRX_P15 PEG_HTX_C_GRX_P14 PEG_HTX_C_GRX_P13 PEG_HTX_C_GRX_P12 PEG_HTX_C_GRX_P11 PEG_HTX_C_GRX_P10 PEG_HTX_C_GRX_P9 PEG_HTX_C_GRX_P8 PEG_HTX_C_GRX_P7 PEG_HTX_C_GRX_P6 PEG_HTX_C_GRX_P5 PEG_HTX_C_GRX_P4 PEG_HTX_C_GRX_P3 PEG_HTX_C_GRX_P2 PEG_HTX_C_GRX_P1 PEG_HTX_C_GRX_P0 PEG_GTX_HRX_N[0 15] PEG_GTX_HRX_P[0 15] PEG_HTX_C_GRX_N[0 15] PEG_HTX_C_GRX_P[0 15] PEG_TX[0] PEG_TX[1] PEG_TX[2] PEG_TX[3] PEG_TX[4] PEG_TX[5] PEG_TX[6] PEG_TX[7] PEG_TX[8] PEG_TX[9] PEG_TX[10] PEG_TX[11] PEG_TX[12] PEG_TX[13] PEG_TX[14] PEG_TX[15] IVY-BRIDGE_BGA1023 @ eDP_COMPIO and eDP_ICOMPO should be connected to R3 respectively eDP_COMPIO Trace Width to R3= 4-mil Trace Spacing to Other Signals= 15-mil Max Routing Length= 500-mil eDP_ICOMPO Trace Width to R3= 12-mil Trace Spacing to Other Signals= 15-mil Routing Length= 500-mil Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2012/07/29 Date of EOP Deciphered Date Title PROCESSOR(1/7) DMI,FDI,PEG THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Rev 1.0 Ezel_CX MB_LA-A001P Date: A B C D Sheet Wednesday, March 13, 2013 E of 64 A B C D E C57 Reserved by ESD PROC_SELECT# PROC_DETECT# H_PECI T1 PAD @ C49 H_PECI A48 H_PECI 62_0402_5% R5 56_0402_5% H_PROCHOT# H_PROCHOT# H_PROCHOT#_R Reserved by ESD XEMC@ C551 0.1U_0402_16V7K H_CPUPWRGD C45 D45 H_THRMTRIP# PECI PROCHOT# R10 C66 should be as close as possible to CPU C48 H_PM_SYNC PM_SYNC 10K_0402_5% H_CPUPWRGD H_CPUPWRGD PM_DRAM_PWRGD_R BUF_CPU_RST# B46 BE45 D44 SM_RCOMP[0] SM_RCOMP[1] SM_RCOMP[2] PRDY# PREQ# PWR MANAGEMENT care should be taken to no stub caused by R10 AG3 DPLL_REF_CLK AG1 DPLL_REF_CLK# DPLL_REF_CLK DPLL_REF_CLK# AT30 SM_DRAMRST# BF44 BE43 BG43 SM_RCOMP0 SM_RCOMP1 SM_RCOMP2 R6 R7 R8 SM_DRAMRST# 2 Width Spacing Length SM_RCOMP0 20-mil 20-mil < 500-mil SM_RCOMP1 20-mil 20-mil < 500-mil SM_RCOMP2 15-mil 20-mil < 500-mil 140_0402_1% 25.5_0402_1% 200_0402_1% UNCOREPWRGOOD SM_DRAMPWROK RESET# TCK TMS TRST# TDI TDO N53 N55 SM_DRAMRST# +3VS L56 L55 J58 XDP_TCK @ @ XDP_TMS XDP_TRST# @ PAD T2 PAD T3 PAD T4 M60 L59 XDP_TDI XDP_TDO @ @ PAD T5 PAD T6 K58 XDP_DBRESET# XEMC@ C573 0.1U_0402_16V7K R9 1K_0402_5% DBR# BPM#[0] BPM#[1] BPM#[2] BPM#[3] BPM#[4] BPM#[5] BPM#[6] BPM#[7] G58 E55 E59 G55 G59 H60 J59 J61 2 Reserved by ESD XDP_DBRESET# C573 should be as close as possible to CPU C65 XEMC@ 0.1U_0402_16V7K Reserved by ESD +3VALW SM_DRAMPWROK THERMTRIP# 2 Reference Clock for eDP Panel SM_DRAMRST# THERMALTRIP# will be asserted when CPU junction temperature exceeds approximately 130 °C Reserved by ESD XEMC@ C66 0.1U_0402_16V7K R4 +1.05VS_VTT CLK_CPU_DMI CLK_CPU_DMI# CATERR# JTAG & BPM XEMC@ C572 0.1U_0402_16V7K THERMAL H_CATERR# DPLL_REF_CLK DPLL_REF_CLK# J3 H2 H_SNB_IVB# BCLK BCLK# DDR3 MISC C572 should be as close as possible to CPU F49 MISC For 2nd Generation IntelR Core processor family mobile, the output will be high For Mobile 3rd Generation IntelR Core processor family, the output will be low CLOCKS UCPU1B +1.5VS 1 SYS_PWROK PM_DRAM_PWRGD A 3 B G VCC IVY-BRIDGE_BGA1023 @ R11 200_0402_5% 2 C67 0.1U_0402_16V7K U15 Y PM_SYS_PWRGD_BUF R13 PM_DRAM_PWRGD_R 130_0402_5% MC74VHC1G09DFT2G_SC70-5 Buffered Reset to CPU +3VS +1.05VS_VTT PLT_RST# 2 U16 NC Y A PLT_RST# R12 75_0402_5% BUFO_CPU_RST# R15 43_0402_1% BUF_CPU_RST# G P C68 0.1U_0402_16V7K 1 SN74LVC1G07DCKR_SC70-5 4 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2012/07/29 Deciphered Date Date of EOP Title PROCESSOR(3/7) DDRIII THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Rev 1.0 Ezel_CX MB_LA-A001P Date: A B C D Wednesday, March 13, 2013 Sheet E of 64 A B C D UCPU1C AG6 AJ6 AP11 AL6 AJ10 AJ8 AL8 AL7 AR11 AP6 AU6 AV9 AR6 AP8 AT13 AU13 BC7 BB7 BA13 BB11 BA7 BA9 BB9 AY13 AV14 AR14 AY17 AR19 BA14 AU14 BB14 BB17 BA45 AR43 AW48 BC48 BC45 AR45 AT48 AY48 BA49 AV49 BB51 AY53 BB49 AU49 BA53 BB55 BA55 AV56 AP50 AP53 AV54 AT54 AP56 AP52 AN57 AN53 AG56 AG53 AN55 AN52 AG55 AK56 BD37 BF36 BA28 DDR_A_BS0 DDR_A_BS1 DDR_A_BS2 DDR_A_CAS# DDR_A_RAS# DDR_A_WE# BE39 BD39 AT41 SA_DQ[0] SA_DQ[1] SA_DQ[2] SA_DQ[3] SA_DQ[4] SA_DQ[5] SA_DQ[6] SA_DQ[7] SA_DQ[8] SA_DQ[9] SA_DQ[10] SA_DQ[11] SA_DQ[12] SA_DQ[13] SA_DQ[14] SA_DQ[15] SA_DQ[16] SA_DQ[17] SA_DQ[18] SA_DQ[19] SA_DQ[20] SA_DQ[21] SA_DQ[22] SA_DQ[23] SA_DQ[24] SA_DQ[25] SA_DQ[26] SA_DQ[27] SA_DQ[28] SA_DQ[29] SA_DQ[30] SA_DQ[31] SA_DQ[32] SA_DQ[33] SA_DQ[34] SA_DQ[35] SA_DQ[36] SA_DQ[37] SA_DQ[38] SA_DQ[39] SA_DQ[40] SA_DQ[41] SA_DQ[42] SA_DQ[43] SA_DQ[44] SA_DQ[45] SA_DQ[46] SA_DQ[47] SA_DQ[48] SA_DQ[49] SA_DQ[50] SA_DQ[51] SA_DQ[52] SA_DQ[53] SA_DQ[54] SA_DQ[55] SA_DQ[56] SA_DQ[57] SA_DQ[58] SA_DQ[59] SA_DQ[60] SA_DQ[61] SA_DQ[62] SA_DQ[63] SA_CK[0] SA_CK#[0] SA_CKE[0] SA_CK[1] SA_CK#[1] SA_CKE[1] SA_CS#[0] SA_CS#[1] SA_ODT[0] SA_ODT[1] SA_DQS#[0] SA_DQS#[1] SA_DQS#[2] SA_DQS#[3] SA_DQS#[4] SA_DQS#[5] SA_DQS#[6] SA_DQS#[7] SA_DQS[0] SA_DQS[1] SA_DQS[2] SA_DQS[3] SA_DQS[4] SA_DQS[5] SA_DQS[6] SA_DQS[7] SA_MA[0] SA_MA[1] SA_MA[2] SA_MA[3] SA_MA[4] SA_MA[5] SA_MA[6] SA_MA[7] SA_MA[8] SA_MA[9] SA_MA[10] SA_MA[11] SA_MA[12] SA_MA[13] SA_MA[14] SA_MA[15] SA_BS[0] SA_BS[1] SA_BS[2] SA_CAS# SA_RAS# SA_WE# AU36 AV36 AY26 DDR_B_D[0 63] DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63 SA_CLK_DDR0 SA_CLK_DDR#0 DDRA_CKE0_DIMMA AT40 AU40 BB26 SA_CLK_DDR1 SA_CLK_DDR#1 DDRA_CKE1_DIMMA BB40 BC41 DDRA_CS0_DIMMA# DDRA_CS1_DIMMA# AY40 BA41 SA_ODT0 SA_ODT1 AL11 AR8 AV11 AT17 AV45 AY51 AT55 AK55 DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7 DDR_A_DQS#[0 7] AJ11 AR10 AY11 AU17 AW45 AV51 AT56 AK54 DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7 DDR_A_DQS[0 7] BG35 BB34 BE35 BD35 AT34 AU34 BB32 AT32 AY32 AV32 BE37 BA30 BC30 AW41 AY28 AU26 DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15 DDR_A_MA[0 15] DDR_B_BS0 DDR_B_BS1 DDR_B_BS2 DDR_B_CAS# DDR_B_RAS# DDR_B_WE# AL4 AL1 AN3 AR4 AK4 AK3 AN4 AR1 AU4 AT2 AV4 BA4 AU3 AR3 AY2 BA3 BE9 BD9 BD13 BF12 BF8 BD10 BD14 BE13 BF16 BE17 BE18 BE21 BE14 BG14 BG18 BF19 BD50 BF48 BD53 BF52 BD49 BE49 BD54 BE53 BF56 BE57 BC59 AY60 BE54 BG54 BA58 AW59 AW58 AU58 AN61 AN59 AU59 AU61 AN58 AR58 AK58 AL58 AG58 AG59 AM60 AL59 AF61 AH60 BG39 BD42 AT22 AV43 BF40 BD45 IVY-BRIDGE_BGA1023 @ SB_DQ[0] SB_DQ[1] SB_DQ[2] SB_DQ[3] SB_DQ[4] SB_DQ[5] SB_DQ[6] SB_DQ[7] SB_DQ[8] SB_DQ[9] SB_DQ[10] SB_DQ[11] SB_DQ[12] SB_DQ[13] SB_DQ[14] SB_DQ[15] SB_DQ[16] SB_DQ[17] SB_DQ[18] SB_DQ[19] SB_DQ[20] SB_DQ[21] SB_DQ[22] SB_DQ[23] SB_DQ[24] SB_DQ[25] SB_DQ[26] SB_DQ[27] SB_DQ[28] SB_DQ[29] SB_DQ[30] SB_DQ[31] SB_DQ[32] SB_DQ[33] SB_DQ[34] SB_DQ[35] SB_DQ[36] SB_DQ[37] SB_DQ[38] SB_DQ[39] SB_DQ[40] SB_DQ[41] SB_DQ[42] SB_DQ[43] SB_DQ[44] SB_DQ[45] SB_DQ[46] SB_DQ[47] SB_DQ[48] SB_DQ[49] SB_DQ[50] SB_DQ[51] SB_DQ[52] SB_DQ[53] SB_DQ[54] SB_DQ[55] SB_DQ[56] SB_DQ[57] SB_DQ[58] SB_DQ[59] SB_DQ[60] SB_DQ[61] SB_DQ[62] SB_DQ[63] SB_CK[0] SB_CK#[0] SB_CKE[0] BA34 AY34 AR22 SB_CLK_DDR0 SB_CLK_DDR#0 DDR_B_CKE0 SB_CK[1] SB_CK#[1] SB_CKE[1] SB_CS#[0] SB_CS#[1] SB_ODT[0] SB_ODT[1] DDR SYSTEM MEMORY B DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63 UCPU1D DDR_A_D[0 63] DDR SYSTEM MEMORY A E SB_DQS#[0] SB_DQS#[1] SB_DQS#[2] SB_DQS#[3] SB_DQS#[4] SB_DQS#[5] SB_DQS#[6] SB_DQS#[7] SB_DQS[0] SB_DQS[1] SB_DQS[2] SB_DQS[3] SB_DQS[4] SB_DQS[5] SB_DQS[6] SB_DQS[7] SB_MA[0] SB_MA[1] SB_MA[2] SB_MA[3] SB_MA[4] SB_MA[5] SB_MA[6] SB_MA[7] SB_MA[8] SB_MA[9] SB_MA[10] SB_MA[11] SB_MA[12] SB_MA[13] SB_MA[14] SB_MA[15] SB_BS[0] SB_BS[1] SB_BS[2] SB_CAS# SB_RAS# SB_WE# BA36 BB36 BF27 BE41 BE47 DDR_B_CS0# AT43 BG47 DDR_B_ODT0 DDR_B_DQS#[0 7] AL3 AV3 BG11 BD17 BG51 BA59 AT60 AK59 DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7 AM2 AV1 BE11 BD18 BE51 BA61 AR59 AK61 DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7 DDR_B_DQS[0 7] BF32 BE33 BD33 AU30 BD30 AV30 BG30 BD29 BE30 BE28 BD43 AT28 AV28 BD46 AT26 AU22 DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15 DDR_B_MA[0 15] IVY-BRIDGE_BGA1023 @ +1.5V R17 1K_0402_5% for S3 Power Reducton SM_DRAMRST# D SM_DRAMRST# S DIMM_DRAMRST#_R Q1 LBSS138LT1G_SOT-23-3 G R19 4.99K_0402_1% RST_GATE#_R RST_GATE# R520 100K_0402_5% C69 0.047U_0402_16V7K R18 1K_0402_5% DIMM_DRAMRST# S0 DRAMRST_CNTRL_PCH hgih ,MOS ON SM_DRAMRST# HIGH,DDR3 DRAMRST# HIGH DRAM not reset S3 DRAMRST_CNTRL_PCH Low ,MOS OFF SM_DRAMRST# Low,DDR3 DRAMRST# HIGH DRAM not reset S4,5 DRAMRST_CNTRL_PCH Low ,MOS OFF SM_DRAMRST# low,DDR3 DRAMRST# low DRAM reset Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2012/07/29 Date of EOP Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC B Rev 1.0 Ezel_CX MB_LA-A001P Date: A PROCESSOR(3/7) DDRIII C D Wednesday, March 13, 2013 Sheet E of 64 A B C D E 1 CFG Straps for Processor UCPU1E PAD @ PAD @ PAD @ T24 T27 PAD @ PAD @ H43 K43 T21 T15 PAD @ PAD @ H45 K45 T8 PAD @ F48 H48 K48 CFG2 RSVD34 RSVD35 RSVD36 RSVD37 RSVD38 RSVD39 RSVD40 VAXG_VAL_SENSE VSSAXG_VAL_SENSE RSVD41 RSVD42 RSVD43 RSVD44 RSVD45 RSVD6 RSVD7 DC_TEST_A4 DC_TEST_C4 DC_TEST_D3 DC_TEST_D1 DC_TEST_A58 DC_TEST_A59 DC_TEST_C59 DC_TEST_A61 DC_TEST_C61 DC_TEST_D61 DC_TEST_BD61 DC_TEST_BE61 DC_TEST_BE59 DC_TEST_BG61 DC_TEST_BG59 DC_TEST_BG58 DC_TEST_BG4 DC_TEST_BG3 DC_TEST_BE3 DC_TEST_BG1 DC_TEST_BE1 DC_TEST_BD1 RSVD8 RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14 RSVD15 RSVD16 RSVD17 RSVD18 RSVD19 RSVD20 RSVD21 RSVD22 RSVD23 RSVD24 RSVD25 RSVD26 RSVD27 N42 L42 L45 L47 dGPU@ R21 1K_0402_1% M13 M14 U14 W14 P13 PCIe Static x16 Lane Numbering Reversal CFG2 AT49 K24 * 1: (Default)Normal Operation Lane # definition matches socket pin map definition 0: Lane Reversed AH2 AG13 AM14 AM15 CFG4 N50 R26 1K_0402_1% These pins are for solder joint reliability and non-critical to function For BGA only A4 C4 D3 D1 A58 A59 C59 A61 C61 D61 BD61 BE61 BE59 BG61 BG59 BG58 BG4 BG3 BE3 BG1 BE1 BD1 DC_TEST_C4_D3 eDP Enable Strap DC_TEST_A59_C59 1: (Default)Disable CFG4 DC_TEST_A61_C61 *0: Enable DC_TEST_BE59_BE61 DC_TEST_BG59_BG61 CFG5 CFG6 DC_TEST_BE3_BG3 DC_TEST_BE1_BG1 @ R27 1K_0402_1% R28 1K_0402_1% BA19 AV19 AT21 BB21 BB19 AY21 BA22 AY22 AU19 AU21 BD21 BD22 BD25 BD26 BG22 BE22 BG26 BE26 BF23 BE24 RSVD30 RSVD31 RSVD32 RSVD33 VCC_VAL_SENSE VSS_VAL_SENSE VCC_DIE_SENSE N59 N58 T38 T44 T45 BCLK_ITP BCLK_ITP# * CFG4 CFG5 CFG6 CFG7 CFG[0] CFG[1] CFG[2] CFG[3] CFG[4] CFG[5] CFG[6] CFG[7] CFG[8] CFG[9] CFG[10] CFG[11] CFG[12] CFG[13] CFG[14] CFG[15] CFG[16] CFG[17] CFG7 1: (Default) PEG Trains immediately and follows xxRESETB de-assertion 0: PEG Wait for BIOS for training B50 C51 B54 D53 A51 C53 C55 H49 A55 H51 K49 K53 F53 G53 L51 F51 D52 L53 CFG2 CFG0 PAD @ RESERVED T7 PEG DEFER TRAINING 3 IVY-BRIDGE_BGA1023 @ PCIE Port Bifurcation Straps CFG[6:5] * 11: 10: 01: 00: (Default) 1x16 PCI Express 2x8 PCI Express Reserved 1x8,2x4 PCI Express 4 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2012/07/29 Date of EOP Deciphered Date Title PROCESSOR(4/7) RSVD,CFG THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Rev 1.0 Ezel_CX MB_LA-A001P Date: A B C D Wednesday, March 13, 2013 Sheet E of 64 A B UCPU1F C D E POWER +1.05VS_VTT VCCIO[1] VCCIO[3] VCCIO[4] VCCIO[5] VCCIO[6] VCCIO[7] VCCIO[8] VCCIO[9] VCCIO[10] VCCIO[11] VCCIO[12] VCCIO[13] VCCIO[14] VCCIO[15] VCCIO[16] VCCIO[17] VCCIO[18] VCCIO[19] VCCIO[20] VCCIO[21] VCCIO[22] VCCIO[23] VCCIO[24] VCCIO[25] VCCIO[26] VCCIO[27] VCCIO[28] VCCIO[29] AA14 AA15 AB17 AB20 AC13 AD16 AD18 AD21 AE14 AE15 AF16 AF18 AF20 AG15 AG16 AG17 AG20 AG21 AJ14 AJ15 +1.05VS_VTT VCCIO50 VCCIO51 VCCIO_SEL W16 W17 BC22 @ PAD VCCIO_SEL T46 +1.05VS_VTT +1.05VS_VTT +1.05VS_VTT C70 1U_0402_6.3V6K R29 130_0402_5% CPU Power Rail Table R30 75_0402_5% AM25 AN22 VCCPQE[1] VCCPQE[2] VCCIO[30] VCCIO[31] VCCIO[32] VCCIO[33] VCCIO[34] VCCIO[35] VCCIO[36] VCCIO[37] VCCIO[38] VCCIO[39] VCCIO[40] VCCIO[41] VCCIO[42] VCCIO[43] VCCIO[44] VCCIO[45] VCCIO[46] VCCIO[47] VCCIO[48] VCCIO[49] AF46 AG48 AG50 AG51 AJ17 AJ21 AJ25 AJ43 AJ47 AK50 AK51 AL14 AL15 AL16 AL20 AL22 AL26 AL45 AL48 AM16 AM17 AM21 AM43 AM47 AN20 AN42 AN45 AN48 PEG IO AND DDR IO VCC[1] VCC[2] VCC[3] VCC[4] VCC[5] VCC[6] VCC[7] VCC[8] VCC[9] VCC[10] VCC[11] VCC[12] VCC[13] VCC[14] VCC[15] VCC[16] VCC[17] VCC[18] VCC[19] VCC[20] VCC[21] VCC[22] VCC[23] VCC[24] VCC[25] VCC[26] VCC[27] VCC[28] VCC[29] VCC[30] VCC[31] VCC[32] VCC[33] VCC[34] VCC[35] VCC[36] VCC[37] VCC[38] VCC[39] VCC[40] VCC[41] VCC[42] VCC[43] VCC[44] VCC[45] VCC[46] VCC[47] VCC[48] VCC[49] VCC[50] VCC[51] VCC[52] VCC[53] VCC[54] VCC[55] VCC[56] VCC[57] VCC[58] VCC[59] VCC[60] VCC[61] VCC[62] VCC[63] VCC[64] VCC[66] VCC[67] VCC[68] VCC[69] VCC[70] VCC[71] VCC[72] VCC[73] VCC[74] VCC[75] VCC[76] QUIET RAILS A26 A29 A31 A34 A35 A38 A39 A42 C26 C27 C32 C34 C37 C39 C42 D27 D32 D34 D37 D39 D42 E26 E28 E32 E34 E37 E38 F25 F26 F28 F32 F34 F37 F38 F42 G42 H25 H26 H28 H29 H32 H34 H35 H37 H38 H40 J25 J26 J28 J29 J32 J34 J35 J37 J38 J40 J42 K26 K27 K29 K32 K34 K35 K37 K39 K42 L25 L28 L33 L36 L40 N26 N30 N34 N38 CORE SUPPLY +CPU_CORE VIDALERT# VIDSCLK VIDSOUT A44 B43 C44 VR_SVID_ALERT# VR_SVID_CLK VR_SVID_DATA R31 43_0402_1% VR_SVID_ALERT# S0 Iccmax Current(A) Voltage Rail Voltage VCC 0.65~1.2 33 Processor Core Voltage 1.05 8.5 Processor Uncore Voltage Memory Controller Voltage VR_SVID_CLK VR_SVID_DATA +CPU_CORE VCCIO VDDQ 1.5 VCCSA 0.675~0.9 System Agent Voltage VCCPLL 1.8 1.2 Processor PLL Voltage 0.65~1.25 29 Processor Graphics Voltage SVID Place the PU resistors close to CPU R32 100_0402_1% VCCSENSE VSSSENSE R33 AN16 AN17 VCCSENSE VSSSENSE 10_0402_5% +1.05VS_VTT VCCIO_SENSE VSSIO_SENSE VCCIO_SENSE VSS_SENSE_VCCIO F43 G43 VAXG VCC_SENSE VSS_SENSE R34 100_0402_1% Refer to Mobile 3rd Generation IntelR Core Processor Family External Design Specification (EDS) Volume of Revision 2.2 SENSE LINES Place the PU resistors close to VR R35 10_0402_5% 4 IVY-BRIDGE_BGA1023 @ Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2012/07/29 Date of EOP Deciphered Date Title PROCESSOR(5/7) PWR,BYPASS THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Rev 1.0 Ezel_CX MB_LA-A001P Date: A B C D Wednesday, March 13, 2013 Sheet E of 64 A B C D E +1.5VS POWER R36 1K_0402_5% BE7 BG7 SA_DIMM_VREFDQ SB_DIMM_VREFDQ VREF @ PAD @ PAD T47 T48 C71 0.1U_0402_16V7K R37 1K_0402_5% 2 SA_DIMM_VREFDQ SB_DIMM_VREFDQ AJ28 AJ33 AJ36 AJ40 AL30 AL34 AL38 AL42 AM33 AM36 AM40 AN30 AN34 AN38 AR26 AR28 AR30 AR32 AR34 AR36 AR40 AV41 AW26 BA40 BB28 BG33 1U_0402_6.3V6K 1U_0402_6.3V6K 2 2 2 2 1U_0402_6.3V6K C81 C80 C79 C78 C77 C76 C75 C74 1U_0402_6.3V6K C73 @ C690 100U_1206_6.3V6M C72 1U_0402_6.3V6K C90 10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M 2 2 2 stuff for first version then check the feasibility to remove them C89 C88 C87 C86 C85 C84 C83 10U_0603_6.3V6M Place BOT OUT BGA - 1.5V RAILS +1.5VS Place TOP IN BGA 1U_0402_6.3V6K DDR3 stuff for first version then check the feasibility to remove them 10U_0603_6.3V6M VDDQ[1] VDDQ[2] VDDQ[3] VDDQ[4] VDDQ[5] VDDQ[6] VDDQ[7] VDDQ[8] VDDQ[9] VDDQ[10] VDDQ[11] VDDQ[12] VDDQ[13] VDDQ[14] VDDQ[15] VDDQ[16] VDDQ[17] VDDQ[18] VDDQ[19] VDDQ[20] VDDQ[21] VDDQ[22] VDDQ[23] VDDQ[24] VDDQ[25] VDDQ[26] 1U_0402_6.3V6K +V_SM_VREF 1U_0402_6.3V6K +VGFX_CORE +V_SM_VREF should be 20-mil trace width and 20-mil spacing AY43 1U_0402_6.3V6K SM_VREF 5A GRAPHICS VAXG[1] VAXG[2] VAXG[3] VAXG[4] VAXG[5] VAXG[6] VAXG[7] VAXG[8] VAXG[9] VAXG[10] VAXG[11] VAXG[12] VAXG[13] VAXG[14] VAXG[15] VAXG[16] VAXG[17] VAXG[18] VAXG[19] VAXG[20] VAXG[21] VAXG[22] VAXG[23] VAXG[24] VAXG[25] VAXG[26] VAXG[27] VAXG[28] VAXG[29] VAXG[30] VAXG[31] VAXG[32] VAXG[33] VAXG[34] VAXG[35] VAXG[36] VAXG[37] VAXG[38] VAXG[39] VAXG[40] VAXG[41] VAXG[42] VAXG[43] VAXG[44] VAXG[45] VAXG[46] VAXG[47] VAXG[48] VAXG[49] VAXG[50] VAXG[51] VAXG[52] VAXG[53] VAXG[54] VAXG[55] VAXG[56] 1U_0402_6.3V6K AA46 AB47 AB50 AB51 AB52 AB53 AB55 AB56 AB58 AB59 AC61 AD47 AD48 AD50 AD51 AD52 AD53 AD55 AD56 AD58 AD59 AE46 N45 P47 P48 P50 P51 P52 P53 P55 P56 P61 T48 T58 T59 T61 U46 V47 V48 V50 V51 V52 V53 V55 V56 V58 V59 W50 W51 W52 W53 W55 W56 W61 Y48 Y61 DC 29A UCPU1G +VGFX_CORE Follow VDDQ 1.5V-Rail Decoupling Recommendation from Intel PDDG Rev 1.0, 1x 330uF 8x 10uF (0603) 10x 1uF (0402) R40 +1.5VS @ +VCCSA 2 C95 1U_0402_6.3V6K Place TOP IN BGA 2 2 C101 C100 1U_0402_6.3V6K C99 1U_0402_6.3V6K C98 1U_0402_6.3V6K C96 C97 1U_0402_6.3V6K 1U_0402_6.3V6K 100U_1206_6.3V6M +VCCSA 10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M 2 2 C106 C105 C104 C103 10U_0603_6.3V6M C102 10U_0603_6.3V6M L17 L21 N16 N20 N22 P17 P20 R16 R18 R21 U15 V16 V17 V18 V21 W20 VCCSA[1] VCCSA[2] VCCSA[3] VCCSA[4] VCCSA[5] VCCSA[6] VCCSA[7] VCCSA[8] VCCSA[9] VCCSA[10] VCCSA[11] VCCSA[12] VCCSA[13] VCCSA[14] VCCSA[15] VCCSA[16] C91 1U_0402_6.3V6K *For ULV Only VID[0] ball D48 BC43 BA43 VDDQ_SENSE VSS_SENSE_VDDQ VID[1] ball D49 VCCSA Output 0 0.9V 0.85V 0.775V 1 0.75V U10 VCCSA_SENSE D48 D49 VCCSA_VID[0] VCCSA_VID[1] H_VCCSA_VID0 H_VCCSA_VID1 H_VCCSA_VID0 H_VCCSA_VID1 IVY-BRIDGE_BGA1023 @ Place BOT OUT BGA 6A VCCPLL[1] VCCPLL[2] VCCPLL[3] SENSE LINES BB3 BC1 BC4 C94 1U_0402_6.3V6K C92 100U_1206_6.3V6M VCCPLL Plane Decoupling Recommendation from Intel PDDG Rev 1.0, 1x 330uF 2x 1uF (0402) VCCSA VID lines +1.8VS SA RAIL 1.2A 100_0402_5% 1.8V RAIL R41 AM28 AN26 VCCDQ[1] VCCDQ[2] VAXG_SENSE VSSAXG_SENSE SENSE LINES F45 G45 VCC_AXG_SENSE VSS_AXG_SENSE QUIET RAILS 100_0402_5% stuff for first version then check the feasibility to remove them Follow VCCSA Plane Decoupling Recommendations from Intel PDDG Rev 1.0, 1x 330uF Security Classification 5x 10uF (0603) Issued Date 5x 1uF (0402) Compal Electronics, Inc Compal Secret Data 2012/07/29 Date of EOP Deciphered Date Title PROCESSOR(6/7) PWR THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Rev 1.0 Ezel_CX MB_LA-A001P Date: A B C D Wednesday, March 13, 2013 Sheet E of 64 A B C D E UCPU1H UCPU1I VSS[1] VSS[2] VSS[3] VSS[4] VSS[5] VSS[6] VSS[7] VSS[8] VSS[9] VSS[10] VSS[11] VSS[12] VSS[13] VSS[14] VSS[15] VSS[16] VSS[17] VSS[18] VSS[19] VSS[20] VSS[21] VSS[22] VSS[23] VSS[24] VSS[25] VSS[26] VSS[27] VSS[28] VSS[29] VSS[30] VSS[31] VSS[32] VSS[33] VSS[34] VSS[35] VSS[36] VSS[37] VSS[38] VSS[39] VSS[40] VSS[41] VSS[42] VSS[43] VSS[44] VSS[45] VSS[46] VSS[47] VSS[48] VSS[49] VSS[50] VSS[51] VSS[52] VSS[53] VSS[54] VSS[55] VSS[56] VSS[57] VSS[58] VSS[59] VSS[60] VSS[61] VSS[62] VSS[63] VSS[64] VSS[65] VSS[66] VSS[67] VSS[68] VSS[69] VSS[70] VSS[71] VSS[72] VSS[73] VSS[74] VSS[75] VSS[76] VSS[77] VSS[78] VSS[79] VSS[80] VSS[81] VSS[82] VSS[83] VSS[84] VSS[85] VSS[86] VSS[87] VSS[88] VSS[89] VSS[90] VSS VSS[91] VSS[92] VSS[93] VSS[94] VSS[95] VSS[96] VSS[97] VSS[98] VSS[99] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] VSS[164] VSS[165] VSS[166] VSS[167] VSS[168] VSS[169] VSS[170] VSS[171] VSS[172] VSS[173] VSS[174] VSS[175] VSS[176] VSS[177] VSS[178] VSS[179] VSS[180] AM38 AM4 AM42 AM45 AM48 AM58 AN1 AN21 AN25 AN28 AN33 AN36 AN40 AN43 AN47 AN50 AN54 AP10 AP51 AP55 AP7 AR13 AR17 AR21 AR41 AR48 AR61 AR7 AT14 AT19 AT36 AT4 AT45 AT52 AT58 AU1 AU11 AU28 AU32 AU51 AU7 AV17 AV21 AV22 AV34 AV40 AV48 AV55 AW13 AW43 AW61 AW7 AY14 AY19 AY30 AY36 AY4 AY41 AY45 AY49 AY55 AY58 AY9 BA1 BA11 BA17 BA21 BA26 BA32 BA48 BA51 BB53 BC13 BC5 BC57 BD12 BD16 BD19 BD23 BD27 BD32 BD36 BD40 BD44 BD48 BD52 BD56 BD8 BE5 BG13 BG17 BG21 BG24 BG28 BG37 BG41 BG45 BG49 BG53 BG9 C29 C35 C40 D10 D14 D18 D22 D26 D29 D35 D4 D40 D43 D46 D50 D54 D58 D6 E25 E29 E3 E35 E40 F13 F15 F19 F29 F35 F40 F55 G51 G6 G61 H10 H14 H17 H21 H4 H53 H58 J1 J49 J55 K11 K21 K51 K8 L16 L20 L22 L26 L30 L34 L38 L43 L48 L61 M11 M15 VSS[181] VSS[182] VSS[183] VSS[184] VSS[185] VSS[186] VSS[187] VSS[188] VSS[189] VSS[190] VSS[191] VSS[192] VSS[193] VSS[194] VSS[195] VSS[196] VSS[197] VSS[198] VSS[199] VSS[200] VSS[201] VSS[202] VSS[203] VSS[204] VSS[205] VSS[206] VSS[207] VSS[208] VSS[209] VSS[210] VSS[211] VSS[212] VSS[213] VSS[214] VSS[215] VSS[216] VSS[217] VSS[218] VSS[219] VSS[220] VSS[221] VSS[222] VSS[223] VSS[224] VSS[225] VSS[226] VSS[227] VSS[228] VSS[229] VSS[230] VSS[231] VSS[232] VSS[233] VSS[234] VSS[235] VSS[236] VSS[237] VSS[238] VSS[239] VSS[240] VSS[241] VSS[242] VSS[243] VSS[244] VSS[245] VSS[246] VSS[247] VSS[248] VSS[249] VSS[250] VSS[251] VSS[252] VSS[253] VSS[254] VSS[255] VSS[256] VSS[257] VSS[258] VSS[259] VSS[260] VSS[261] VSS[262] VSS[263] VSS[264] VSS[265] VSS[266] VSS[267] VSS[268] VSS[269] VSS[270] VSS[271] VSS[272] VSS[273] VSS[274] VSS[275] VSS[276] VSS[277] VSS[278] VSS[279] VSS[280] VSS[281] VSS[282] VSS[283] VSS[284] VSS[285] VSS[286] VSS[287] VSS[288] VSS[289] VSS[290] VSS[291] VSS[292] VSS[293] VSS[294] VSS[295] VSS[296] VSS[297] VSS[298] VSS[299] VSS[300] VSS[301] VSS NCTF A13 A17 A21 A25 A28 A33 A37 A40 A45 A49 A53 A9 AA1 AA13 AA50 AA51 AA52 AA53 AA55 AA56 AA8 AB16 AB18 AB21 AB48 AB61 AC10 AC14 AC46 AC6 AD17 AD20 AD4 AD61 AE13 AE8 AF1 AF17 AF21 AF47 AF48 AF50 AF51 AF52 AF53 AF55 AF56 AF58 AF59 AG10 AG14 AG18 AG47 AG52 AG61 AG7 AH4 AH58 AJ13 AJ16 AJ20 AJ22 AJ26 AJ30 AJ34 AJ38 AJ42 AJ45 AJ48 AJ7 AK1 AK52 AL10 AL13 AL17 AL21 AL25 AL28 AL33 AL36 AL40 AL43 AL47 AL61 AM13 AM20 AM22 AM26 AM30 AM34 VSS_NCTF_1 VSS_NCTF_2 VSS_NCTF_3 VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_8 VSS_NCTF_9 VSS_NCTF_10 VSS_NCTF_11 VSS_NCTF_12 VSS_NCTF_13 VSS_NCTF_14 M4 M58 M6 N1 N17 N21 N25 N28 N33 N36 N40 N43 N47 N48 N51 N52 N56 N61 P14 P16 P18 P21 P58 P59 P9 R17 R20 R4 R46 T1 T47 T50 T51 T52 T53 T55 T56 U13 U8 V20 V61 W13 W15 W18 W21 W46 W8 Y4 Y47 Y58 Y59 G48 A5 A57 BC61 BD3 BD59 BE4 BE58 BG5 BG57 C3 C58 D59 E1 E61 IVY-BRIDGE_BGA1023 @ IVY-BRIDGE_BGA1023 @ 4 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2012/07/29 Deciphered Date Date of EOP Title PROCESSOR(7/7) VSS THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Rev 1.0 Ezel_CX MB_LA-A001P Date: A B C D Wednesday, March 13, 2013 Sheet E 10 of 64 VID [0] 0 1 VID[1] 1 VCCSA Vout 0.9V 0.85V 0.775V 0.75V D D +5VALW SA_PGOOD VCCPPWRGOOD PC701 1U_0402_6.3V6K 0_0402_5% PR701 Rshort@ @ VIN Vo VPP Vo POK D1 VEN/MODE D0 +VCCSAP Rshort@ PR704 0_0402_5% 2 H_VCCSA_VID1 H_VCCSA_VID1 1 H_VCCSA_VID0 H_VCCSA_VID0 0_0402_5% PR703 Rshort@ G978F11U_SO8 PC708 1U_0603_6.3V6M GND 0.9V PC707 22U_0805_6.3V6M JUMP_43X118 PC706 22U_0805_6.3V6M 2 PC705 22U_0805_6.3V6M 1 PU701 PC704 22U_0805_6.3V6M +1.05VS_VTT PJ701 output voltage adjustable network PC703 22U_0805_6.3V6M @ PC702 22U_0805_6.3V6M 1 PR702 100K_0402_5% +3VS +VCCSAP @ +VCCSA PJ702 1 2 JUMP_43X118 Imax= 2A, Ipeak= 3A FB=0.6V C C +3VS B B @ PC714 1U_0402_6.3V6K Note:Iload(max)=3A +1.8VSP_ON PR710 15.8K_0402_1% PJ703 +1.8VSP 1 @ 2 +1.8VS JUMP_43X79 PQ701 2N7002KW_SOT323-3 A D G SUSP Ien=10uA, Vth=0.3V, notice the res and pull high voltage from HW A 2 PC713 0.1U_0402_16V7K @ PR709 22K_0402_5% @ 2 1 SUSP# FB_1.8VSP PR708 200K_0402_1% PC712 22U_0805_6.3VAM PR707 20K_0402_1% FB=0.8V +1.8VSP 2 FB PC711 22U_0805_6.3VAM EN POK VOUT VOUT GND PC715 4.7U_0603_6.3V6K VCNTL VIN VIN PC710 68P_0402_50V8J PU702 APL5930KAI-TRG_SO8 S Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2011/06/24 Date of EOP Deciphered Date Title VCC_SAP/1.8VSP THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Rev 1.0 Ezel M/B Schematics_LAA001P Date: Sheet 50 of 64 VSSSENSE 1 2 VSUMG+ VSUMGPC820 33U_25V_M PC819 33U_25V_M @EMI@ Height mm B +CPU_CORE 1_0402_5% PR836 3.65K_0402_1% PR835 2 3 1 PR834 2.61K_0402_1% MDU1511RH_POWERDFN56-8-5 PQ804 CM@ PQ805 MDU1511RH_POWERDFN56-8-5 0.1U_0603_25V7K PC829 PR831 680P_0402_50V7K 4.7_1206_5% @EMI@ @EMI@ PC827 1 11K_0402_1% PR840 PH804 VSUM+ Close CPU choke 10K_0402_1%_ERTJ0EG103FA 2 PC833 0.1U_0603_25V7K VSUM- PC837 1U_0402_16V7K VSUM- 1 PC832 0.047U_0402_25V7K PR839 422_0402_1% PC835 PR838 6800P_0402_25V7K 649 +-1% 0402 2 1 + PL805 0.22UH_FDUE0640J-H-R22M-P3_25A_20% PQ803 MDV1525URH_PDFN33-8-5 LGATE1 PC838 0.01UF_0402_25V7K + B+ OCP setting=39.9~44.99A PR828 VSUM+ PR842 137K_0402_1% PC824 0.1U_0402_25V6 PC823 10U_0805_25V6K PC822 10U_0805_25V6K 2 UGATE1 0.36uH DCR= 1.4+-5% m ohm, Idc~Isat= 25~34A PR827 0_0603_5% UGATE1-1 +3VS PR833 42.2K_0402_1% PC834 150P_0402_50V8J 2 PC810 10U_0805_25V6K 1 17 PHASE1 2.2_0603_5% PR830 BOOT1 PC831 68P_0402_50V8J PC809 10U_0805_25V6K EMI@ PL801 HCB2012KF-121T50_0805 PHASE1 PC801 1U_0603_10V6K LGATE1 18 1.91K_0402_1% C EMI@ PL802 HCB2012KF-121T50_0805 UGATE1 @ PC836 330P_0402_50V7K VCCSENSE 1 PC818 1U_0603_10V6K UGATEG 25 19 16 BOOT1 1.91K_0402_1% A @EMI@ PC808 2200P_0402_50V7K 1 PR812 27 28 26 BOOTG PGOODG 29 FBG COMPG 31 32 30 RTNG ISUMNG 33 PGOOD PR826 61.9K_0402_1% PH803 470K +-5% ERTJ0EV474J 0402 1 PR825 54.9_0402_1% PR824 130_0402_1% 2 PHASE1 UGATE1 PC817 @EMI@ 680P_0402_50V7K BOOT1 PR841 1.91K_0402_1% NTC ISEN2 @ PR801 20 VGATE Close CPU L/S MOS PC830 470P_0402_50V7K 2 PR837 499_0402_1% PR822 0_0402_5% 1_0402_5% PR816 +CPU_B+ NTC_1 @ PC826 0.1U_0402_16V7K PC828 PR832 470P_0402_50V7K 2K_0402_1% 2 VDD LGATE1 PR829 3.83K_0402_1% B PR18 and PR30 27.4K ohm for 100 degree 61.9K ohm for 110 degree PR823 499_0402_1% +1.05VS_VTT @ +5VS 2 @ PC825 47P_0402_50V8J _HOT#, already igh at power side VR_HOT# 15 NTC PR820 PR819 1_0603_5% 0_0603_5% PL803 3.65K_0402_1% PR815 MDU1511 Vds=30V Rds(on)=2.7~3.3m ohm@Vgs=4.5V 21 PW M2 COMP H_PROCHOT# SDA 14 ALERT# FB 22 VCCP ISL95833HRTZ-T_TQFN32_4X4 RTN VR_SVID_DATA SCLK 13 12 VR_SVID_ALERT# 23 PR814 @EMI@ 4.7_1206_5% PQ802 MDU1511RH_POWERDFN56-8-5 24 +VGFX_CORE 0.36UH_FDUM0640J-H-R3_22A_20% +5VS LGATEG LGATEG ISUMN VR_SVID_DATA VR_SVID_CLK 0.22uH DCR= 0.97+-5% m ohm, Idc~Isat= 25~34A PC816 0.1U_0603_25V7K 2 BOOTG PR813 2.2_0603_5% LGATEG BOOTG PHASEG 11 VR_SVID_ALERT# PQ801 MDV1525URH_PDFN33-8-5 UGATEG1 VR_ON ISUMP 0_0402_5% UGATEG1-1 PHASEG NTCG 10 ISUMPG PAD ISEN1 VR_ON PR809 0_0603_5% UGATEG1 2 1.91K_0402_1% PC815 0.047U_0402_25V7K PC814 0.1U_0603_25V7K PR811 11K_0402_1% PR810 2.61K_0402_1% 2 1U_0402_16V7K PC813 PH802 NTCG_1 NTCG 470K +-5% ERTJ0EV474J 0402 MDV1525 Vds=30V Rds(on)=11.5~14m ohm@Vgs=4.5V PHASEG PU801 +CPU_B+ D PC812 330P_0402_50V7K PR807 604_0402_1% PR817 61.9K_0402_1% VR_SVID_CLK +3VS Close GFX L/S MOS PC805 470P_0402_50V7K 2 PR802 PC807 499_0402_1% 150P_0402_50V8J 2 PR804 PR805 137K_0402_1% 2.55K_0402_1% PR806 2K_0402_1% PR808 33.2K_0402_1% 1 OCP setting=39.9~44.99A VDD source use +5VS and PGOOD source use +3VS Please confirm power on and down sequence, make sure VGATE after CPU_CORE on PC804 68P_0402_50V8J PC806 6800P_0402_25V7K VSUMG+ PC803 0.01UF_0402_25V7K VSS_AXG_SENSE PH801 10K_0402_1%_ERTJ0EG103FA VSUMG- PR818 3.83K_0402_1% Rshort@ PR821 VCC_AXG_SENSE Close GFX choke C Layout Note Reduce Acoustic Noise The AL bulk capacitor of B+ should be very close to CPU_CORE MOSFET Input ceramic caps must place on symmetry same location on top side and bottom side @ PC802 1000P_0402_50V7K PR803 649 +-1% 0402 D Layout Note SVID routing Alert# signal must be routed between the Clock and Date lines to reduce the cross talk between them Signal order arrangement: mobile order is Clock-Alert-Date SVID spacing requirement is 18mils(0.475mm) Maximum total microstrip routing length of each SVID signal must not exceed 6000mils(152.4mm) The SVID bus must be ground reference, It cannot be referenced to input (Vbat or 12V) power plans as they can couple noise into the SVID bus as power states change Avoid routing under noisy circuit, e.g switch node , Gate driver, B+, Vin, high speed signal When SVID signal changes Layer, GND return path may be changed also We need add GND via for GND reference A PL701 Issued Date 用SH00000HQ00代代,因因SH00000NM00_R22因2PIN PL702 Footprint 2011/06/24 2012/07/05 Compal Electronics, Inc Compal Secret Data Security Classification Date of EOP Deciphered Date Title CPU_CORE/VGFX_CORE THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Rev 1.0 Ezel M/B Schematics_LAA001P Date: Sheet 51 of 64 2 PC990 22U_0805_6.3V6M @ PC938 22U_0805_6.3V6M PC937 22U_0805_6.3V6M PC936 22U_0805_6.3V6M PC935 22U_0805_6.3V6M 1 2 2 2 1 2 2 2 2 PC922 10U_0603_6.3V6M PC921 10U_0603_6.3V6M PC920 10U_0603_6.3V6M PC919 10U_0603_6.3V6M PC918 10U_0603_6.3V6M 1 PC995 1U_0402_6.3V6K PC994 1U_0402_6.3V6K 2 PC993 1U_0402_6.3V6K 2 PC992 1U_0402_6.3V6K PC991 1U_0402_6.3V6K PC911 1U_0402_6.3V6K PC910 1U_0402_6.3V6K PC909 1U_0402_6.3V6K PC908 1U_0402_6.3V6K PC906 1U_0402_6.3V6K 2 PC923 10U_0603_6.3V6M PC917 22U_0805_6.3V6M 2 2 @ 2 @ @ PC934 22U_0805_6.3V6M 1 PC930 22U_0805_6.3V6M PC932 330U_D2_2V_Y D PC969 2.2U_0402_6.3V6M PC967 2.2U_0402_6.3V6M PC965 2.2U_0402_6.3V6M PC931 330U_D2_2V_Y PC968 2.2U_0402_6.3V6M PC966 2.2U_0402_6.3V6M PC950 2.2U_0402_6.3V6M @ PC929 22U_0805_6.3V6M PC916 2.2U_0402_6.3V6M 1 PC928 22U_0805_6.3V6M PC915 2.2U_0402_6.3V6M 1 PC927 22U_0805_6.3V6M + PC926 22U_0805_6.3V6M ESR=9m ohm @ @ 2 C PC940 22U_0805_6.3V6M PC946 22U_0805_6.3V6M @ PC945 22U_0805_6.3V6M PC944 22U_0805_6.3V6M ‧ Can connect to GND if motherboard only PC943 22U_0805_6.3V6M Vaxg PC942 22U_0805_6.3V6M PC941 22U_0805_6.3V6M C PC925 22U_0805_6.3V6M + @ @ +CPU_CORE 1 @ PC914 2.2U_0402_6.3V6M @ @ PC913 2.2U_0402_6.3V6M PC912 2.2U_0402_6.3V6M @ @ PC905 2.2U_0402_6.3V6M @ PC904 2.2U_0402_6.3V6M @ PC903 2.2U_0402_6.3V6M @ PC902 2.2U_0402_6.3V6M D @ +CPU_CORE PC901 2.2U_0402_6.3V6M @ +VGFX_CORE PC907 1U_0402_6.3V6K PWR Rule 17W@ULV(CR BGA1023_GT2) CPU2.9m GFx3.9m CPU 330uF/9m *3, 22uF(0805) *12, 2.2uF(0402)*16 GFX 330uF/9m*2, 22uF(0805)*6, 10uF(0603)*6, 1uF(0402)*11 1.05V 330uF*2,10uF(0603)*10,1uF(0402)*26 @ supports external graphics and if GFX VR is not stuffed in a common motherboard design, ‧ VAXG can be left floating in a common motherboard design (Gfx VR keeps VAXG from floating) if the VR is stuffed +CPU_CORE +1.05VS_VTT PC979 1U_0402_6.3V6K PC978 1U_0402_6.3V6K PC977 1U_0402_6.3V6K PC976 1U_0402_6.3V6K PC975 1U_0402_6.3V6K PC986 1U_0402_6.3V6K PC988 1U_0402_6.3V6K PC963 1U_0402_6.3V6K PC962 1U_0402_6.3V6K PC961 1U_0402_6.3V6K PC960 1U_0402_6.3V6K PC959 1U_0402_6.3V6K PC987 1U_0402_6.3V6K PC989 1U_0402_6.3V6K + PC933 330U_D2_2V_Y PC953 10U_0603_6.3V6M 2 PC952 10U_0603_6.3V6M 2 PC951 10U_0603_6.3V6M 2 PC939 10U_0603_6.3V6M PC924 10U_0603_6.3V6M 1 1 PC980 1U_0402_6.3V6K PC964 1U_0402_6.3V6K @ + ESR=9m ohm PC947 330U_D2_2V_Y + ESR=9m ohm PC948 330U_D2_2V_Y + PC949 330U_D2_2V_Y B PC955 10U_0603_6.3V6M PC981 1U_0402_6.3V6K PC970 1U_0402_6.3V6K @ PC956 10U_0603_6.3V6M PC982 1U_0402_6.3V6K PC971 1U_0402_6.3V6K @ @ PC957 10U_0603_6.3V6M PC983 1U_0402_6.3V6K PC972 1U_0402_6.3V6K @ PC958 10U_0603_6.3V6M PC984 1U_0402_6.3V6K PC973 1U_0402_6.3V6K PC954 10U_0603_6.3V6M PC985 1U_0402_6.3V6K PC974 1U_0402_6.3V6K 2 B +-20% SGA00006100 ESR=9m ohm A A Compal Electronics, Inc Compal Secret Data Security Classification 2011/06/24 Issued Date Deciphered Date Date of EOP Title CPU_CORE_CAP THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Rev 1.0 Ezel M/B Schematics_LAA001P Date: Sheet 52 of 64 +1.5VSDGPU Ipeak=12.5A ;1.2Ipeak=15A ;Imax=8.75A 1/2Delta I=1.08A (F=290K Hz) PR1004=63.4Kohm Rds(on)=5m ohm(max) ; Rds(on)=4.2m ohm(typical) Iocp=Ilimit+1/2Delta I=15.16~21.5A Iocp(min)>1.2Ipeak 2013/03/13 D 1.5VS_DGPU_PWR_EN D OVP 120 125 130% UG_+1.5VSG SW _+1.5VSG DRVL TP LG_+1.5VSG 11 TPS51212DSCR_SON10_3X3 PC1006 VGA@ 1U_0603_6.3V6M 2 PR1007 470K_0402_1% VGA@ +5VALW @VGA_EMI@ PC1003 2200P_0402_50V7K +1.5VSDGPUP TST C Vout= 1.36V (0.7%) @VGA_EMI@ PR1006 4.7_1206_5% V5IN SW VFB 7*7*4 VGA@ PL1002 1.5UH_TMPB0604M-1R5MN-Z01_11A_20% @VGA_EMI@ PC1009 680P_0402_50V7K + ESR=17m ohm 2 EN B+ PC1008 VGA@ 330U_2.5V_M 10 VGA@ RF_+1.5VSG DRVH TRIP VBST PQ1002 FB_+1.5VSG PGOOD 2 MDU1512RH_POWERDFN56-8-5 EN_+1.5VSG VGA@ PQ1001 MDV1525URH_PDFN33-8-5 VGA@ PC1005 0.1U_0402_16V7K 1 PR1004 63.4K_0402_1% TRIP_+1.5VSG VGA@ PC1001 0.1U_0603_25V7K VGA_PW ROK VGA@ PU1001 VGA@ PR1005 0_0402_5% VGA@ PR1001 2.2_0603_5% BST_+1.5VSG VGA@ PC1004 10U_0805_25V6K @VGA_EMI@ PC1002 0.1U_0402_25V6 C PR1003 30K_0402_1% VGA@ @ VGA_EMI@ PL1001 HCB2012KF-121T50_0805 +1.5VSG_B+ PR1009 9.31K_0402_1% 2 B The RC value (PC10 and PR7) need fine-tune if need B PR1011 10K_0402_1% VGA@ +1.5VSDGPUP @ 1 PJ1001 2 +1.5VSDGPU JUMP_43X118 @ PJ1002 2 JUMP_43X118 A A Compal Electronics, Inc Compal Secret Data Security Classification 2012/04/22 Issued Date Deciphered Date Date of EOP THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title +1.5VSDGPUP Size Document Number Custom Date: W ednesday, March 13, 2013 Rev 1.0 Sheet 53 of 64 A B C D VGA@ PL1202 HCB2012KF-121T50_0805 +VGA_B+ VGA@ PL1201 HCB2012KF-121T50_0805 1 @ 2 @VGA_EMI@ PC1207 680P_0402_50V7K VGA_ON# @ PQ1207 2N7002KW_SOT323-3 G S +5VS VGA@ PQ1204 LGATE2_VGA VGA@ PQ1205 Thermistor near MOSFET trigger point 110 degree C VGA@ PQ1206 +VGA_CORE SH00000NM00 @VGA_EMI@ PR1225 4.7_1206_5% VGA@ PR1226 10K_0402_5% +3VS LGATE2_VGA 10x10x4 1SNUB2_VGA VGA@ VGA@ PL1204 0.22UH_PCMB104T-R22MS_35A_20% PHASE2_VGA PR1224 2.2_0402_5% +5VS UGATE2_2_VGA VGA@ PC1218 0.22U_0603_10V7K BOOT2_2_VGA VGA@ PR1223 10K_0402_5% +3VS VGA@ PR1222 0_0603_5% VGA_PWROK UGATE2_VGA VGA@ PC1216 10U_0805_25V6K VGA@ PR1220 0_0603_5% 1 NCP81172MNTXG_QFN24_4X4 19 +VGA_B+ PR1215 0_0402_5% MDU1516URH_POWERDFN56-8-5 PVCC_VGA 20 MDU1511RH_POWERDFN56-8-5 21 22 VGA@ PC1215 10U_0805_25V6K PC1210 4.7U_0603_10V6K VGA@ MDU1511RH_POWERDFN56-8-5 HG2 23 BOOT2_VGA VGA@PC1219 1U_0402_10V6K D BST2 18 17 16 PH2 PR1228 22_1206_5% 1SNUB1_VGA SH00000NM00 @VGA_EMI@ PC1220 680P_0402_50V7K N14P-GT 35W Ipeak=45A Imax=31.5A Iocp=80A Fsw=450KHz bulk cap 330uF 9m *5 MDU1511, Rdson(typ)=2.7mohm ,Rdson(max)=3.3mohm Compal Secret Data Security Classification Issued Date 2011/12/05 Deciphered Date Date of EOP Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A @VGA_EMI@ PC1203 2200P_0402_50V7K @VGA_EMI@ PC1202 0.1U_0402_25V6 VGA@ PC1205 10U_0805_25V6K VGA@ PC1204 10U_0805_25V6K MDU1516URH_POWERDFN56-8-5 MDU1511RH_POWERDFN56-8-5 3 10x10x4 +VGA_CORE 24 Rshort@ LG2 PGOOD FB VCC VGA@ PQ1203 VGA@ PL1203 0.22UH_PCMB104T-R22MS_35A_20% @VGA_EMI@ PR1207 4.7_1206_5% B+ for EMI PHASE1_VGA BST1 EN HG1 PVCC COMP VGA@ PQ1202 PR1227 @ 100K_0402_1% LGATE1_VGA BOOT1_VGA EN_VGA PSI VIDBUF PGND FBRTN 25 2 PR1209=20K PR1208=20K PR1210=2K PR1212=18K PR1211=0K PC1208=2.7nF VGA@ PC1217 1U_0402_16V7K FS TALERT# VGA@ PR1217 10_0402_1% N14P-GT Vmin=0.6V Vmax=1.2V Vboot=0.9V +VGA_CORE Vstep=6.25mV N=96 FPWM=1.125MHz TDmin=9.26ns 12 LG1 15 2FB2_VGA1 11 PH1 VREF 14 VGA@ PC1214 VGA@ PR1219 100P_0402_50V8J 82K_0402_1% FB_VGA VGA@ PC1213 10P_0402_50V8J COMP_VGA REFIN GND VGA@ PC1212 VGA@ PR1216 47P_0402_50V8J 51_0402_1% 2FB1_VGA1 VGA@ PR1218 10K_0402_1% VID UGATE1_VGA VCC_VGA FS VGA@ PH1201 100K_0402_1%_NCP15WF104F03RC VGA@ PR1221 3.92K_0402_1% VREF VCCSENSE_VGA VGA@ PR1213 33.2K_0402_1% 10 VGA@ PC1211 1000P_0402_50V7K VSSSENSE_VGA PC1208 VGA@ REFIN 2700P_0402_50V7K VREF VGA@ PC1209 0.01U_0402_50V7K 2 PU1201 VGA@ 1 VGA@ TSNS 0_0402_5% VGA@ PR1212 18K_0402_1% 13 Rshort@ PR1211 GPU_VID PR1210 2K_0402_1% VGA@ PR1214 10_0402_1% 1 VGA@ PR1209 20K_0402_1% 1VIDBUF LGATE1_VGA MDU1511RH_POWERDFN56-8-5 VGA@ PR1202 VGA@ PC1206 0_0603_5% 0.22U_0603_10V7K 1BOOT1_2_VGA 2 VGA@ PR1208 20K_0402_1% VREF VGA@ PQ1201 1U_0402_16V7K PSI PR1203 VGA@ 0_0603_5% UGATE1_2_VGA VGA@ PC1201 2 39K_0402_1% Rshort@ PR1206 0_0402_5% VGA@ PR1201 DGPU_VID +3VS VGA@ PR1205 10K_0402_5% Rshort@ PR1204 0_0402_5% 2 @ PC1221 2700P_0402_50V7K VGA_ON B C Compal Electronics, Inc VGA_COREP Document Number Rev 1.0 Wednesday, March 13, 2013 D Sheet 54 of 64 VGA@ PC1317 4.7U_0603_6.3V6K VGA@ PC1316 4.7U_0603_6.3V6K VGA@ PC1315 4.7U_0603_6.3V6K VGA@ PC1314 4.7U_0603_6.3V6K VGA@ PC1311 4.7U_0603_6.3V6K VGA@ PC1321 0.1U_0402_10V7K VGA@ PC1313 4.7U_0603_6.3V6K VGA@ PC1310 4.7U_0603_6.3V6K VGA@ PC1320 0.1U_0402_10V7K VGA@ PC1312 4.7U_0603_6.3V6K VGA@ PC1309 4.7U_0603_6.3V6K VGA@ PC1319 0.1U_0402_10V7K 1 2 VGA@ PC1308 4.7U_0603_6.3V6K D Under VGA Core VGA@ PC1318 0.1U_0402_10V7K +VGA_CORE GB4-128 Under 4.7uF_0603_10pcs 0.1uF_0402_4pcs Near 47uF_0805_1pcs 22uF_0805_1pcs 4.7uF_0805_5pcs D C C +VGA_CORE + + + + B VGA@ PC1328 4.7U_0805_6.3V6K VGA@ PC1327 4.7U_0805_6.3V6K @ VGA@ PC1301 560U_2.5V_M VGA@ PC1304 560U_2.5V_M VGA@ PC1323 22U_0805_6.3V6M VGA@ PC1326 4.7U_0805_6.3V6K 1 VGA@ PC1325 4.7U_0805_6.3V6K 1 2 VGA@ PC1324 4.7U_0805_6.3V6K B VGA@ PC1322 47U_0805_6.3V6M + VGA@ PC1303 560U_2.5V_M @ PC1302 330U_2.5V_M Near VGA Core PC1305 330U_D2_2V_Y +VGA_CORE A A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2011/06/24 Deciphered Date Date of EOP Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC VGA_CORE CAP Size Document Number Custom Date: Wednesday, March 13, 2013 Rev 1.0 Sheet 55 of 64 Version change list (P.I.R List) Item D Fixed Issue Acoustic noise Silergy update revision C B Reason for change Rev PG# Modify List Date 1.Add 2pcs 1K_0402_5% (PR412 PR413) 1pcs 4700P_0402_25V7K (PC425) 1pcs 0.047U_0402_25V7K (PC426) 2.Add 4.7u_0402_6.3V6M (PC401) 3V 5V light load efficiency improvement 3V/5V 3V 5V enable control for Rev0.7 But un-pop 3V/5V Add un-pop 2pcs 0402 resistors(PR415 UMA SKU VGA_CORE IC un-pop VGA PU1201 VGA Change to R-short (PR1211 PR1204 PR414) change to VGA@ Phase 01/03 EVT D 01/03 EVT 01/03 EVT Reduce part count DFB: PC1305 PC1304 PC1303 PC1301 too close VGA 330U_2.5V_M_SF000002Z00 change to 330U_D2_2V_Y_SGA20331E10 (PC1305) 01/03 EVT EMI risk fot CPU/GFX H-Side CPU Change 01/03 EVT The modify values for CPU transition test CPU 0.22uH_SH00000O200 change to modify charger current to meet battery charge time AC Mode no rest function 10 VRAM efficiency improvement 13 Charger (PR809 01/03 EVT ) PR827) 0.02_1206_1%_SD00000S110 charger to 0.01_1206_1%_SD00000K820 01/10 EVT Del PQ401 2N7002KW_SOT323-3 02/18 DVT 1.PQ1002 AON7702A_SB00000T600 change to MDU1512RH_POWERDFN56-8-5_SB00000SY00 2.PQ1001 AON7408L 1N DFN_SB00000H800 change to MDV1525URH 1N PDFN33-8_SB00000S600 3V/5V VGA The 5VALW will fast than 3VALW and the rising time will under 2mS 3V/5V PR416 add 100K_0402_5%_SD028100380 2011/06/24 02/18 DVT 02/18 02/18 DVT PC426 4700P_0402_25V7K_SE075472K80 change to 0.01U_0402_25V7K_SE075103K80 PC425 0.047U_0402_25V7K_SE00000MJ00 change to 6800P_0402_25V7K_SE075682K80 02/18 DVT Deciphered Date A Compal Electronics, Inc Date of EOP Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC PIR (PWR) Rev 1.0 Ezel M/B Schematics_LAA001P Date: B DVT PR1228 add un-pop 22_1206_5%_SD001220A80 PQ1207 add un-pop 2N7002KW_SOT323-3_SB000009Q80 Compal Secret Data Security Classification C 01/03 EVT (PL803) 1.5VDGPU The discharge time may cause GC6 entry/exit quickly fail, worry about the off time too long problem cause the GC6 fail Issued Date 2pcs 0_0603_5% PR1215 0.36uH_SH00000OJ00 When pwm IC shutdown on S0, EC could detect SLP_S5#, but cannot detect PCH was no power 12 PR1206 422_0402_1% change to 604_0402_1% (PR807) 3V/5V 11 A Page 1of for PWR Sheet 56 of 64 Version change list (P.I.R List) Item D Fixed Issue Page 2of for PWR Reason for change 14 VCIN1_function 15 VGA enable sequence for NV suggest VRAM voltage change to 1.35V 16 Rev PG# OTP VGA 1.5VDGPU Modify List Date 1.90W@ PR225 3.3K_0402_1%_SD00000GW80 change to 6.19K_0402_1%_SD034619180 2.65W@ PR225 1.02K_0402_1%_SD034102180 change to 1.91K_0402_1%_SD000009O80 3.PR207 10K_0402_1%_SD034100280 change to 60.4K_0402_1%_SD034604280 PR1003 22K_0402_1%_SD034220280 change to 30K_0402_1%_SD034300280 PR1201 22K_0402_1%_SD034220280 change to 39K_0402_1%_SD034390280 PR100911.5K_0402_1%_SD034115280 change to 9.31K_0402_1%_SD034931180 PR1004 137K_0402_1%_SD034137380 change to 63.4K_0402_1%_SD03463K280 PR318 499K_0402_0.1%_SD00000U380 change to 499K_0402_1%_SD034499380 Phase 02/18 DVT 02/18 DVT 03/13 D PVT C C B B A A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2011/06/24 Date of EOP Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC PIR (PWR) Rev 1.0 Ezel M/B Schematics_LAA001P Date: Sheet 57 of 64 A B Item Page# Function Date Request Owner C D Issue Description E Solution Description Rev 33 HW 12/27/2012 Customer To reserve DP++ circuitry to support dual-mode reserve placeholder of Q46, Q48, Q49, R499, R501 Rev02 33 HW 12/27/2012 Compal output from mDP connector cannot be normally transition change R389 from 100k to 10k Rev02 33 HW 12/27/2012 Compal for safety concern a change U29 from AP2330W-7 to RB491D-YS b also reserve one jump, J11, then track DVT result Rev02 39 HW 12/27/2012 Compal change PU domain for LID_SW# change PU domain of R361 from +3VALW to +3VALW_EC Rev02 39 HW 12/27/2012 Customer remove LAN board remove JLAN1, add JPWR1(A020419-SAHR22, the same as JBL1) Rev02 39 HW 12/27/2012 Compal add NPI test on/off button on M/B add SW6 Rev02 39 HW 12/27/2012 Compal update driving circuit for buzzer add R519 and Q6 Rev02 2 33 HW 12/28/2012 Compal 34 HW 12/28/2012 Compal recommandation from vendor 10 HW 12/28/2012 Compal ME height limit, caused by click-pad structure 11 38 HW 12/28/2012 Compal follow AE's comment, put the back drive current protection FET, Q16, between IC and connector recommandation from vendor Rev02 follow AE's comment, change R338 from 100k to 0ohm, and base on DVT's test result to see if okay to remove it or not Rev02 remove C82, then reserve placeholder for C689 and C690 Rev02 to prevent back drive from WLAN module, change the PU power domain from 3VALW to 3V_WLAN connect 3V_WLAN to R379 then move this component to the page related WLAN Rev02 12 38 HW 12/28/2012 Compal to avoid 0.02V leakage voltage on 3VS change the connection direction of Q24A Rev02 13 38 HW 12/28/2012 Compal update board ID for DVT build stuff R384(100k) and change R388 to 8.2k Rev02 14 14,38 HW 12/28/2012 Customer LAN/B request had been cancelled by customer 15 38 HW 12/28/2012 Compal no PU for Home-Key related signals add RP45 for I2C and INT# signals to PU to 3VALW_EC Rev02 16 38 HW 12/28/2012 Compal wrong control signal for buzzer swap pin connection for BT_ON# and BUZZ# Rev02 2011/06/24 Rev02 Compal Electronics, Inc Compal Secret Data Security Classification Issued Date delete the connection of LAN_PWR_EN and EC_PME# remove C628, C530, C682, C629 and JLAN1 remove C173 and C174 Date of EOP Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC PIR-HW Rev 1.0 Ezel M/B Schematics_LAA001P Date: A B C D Sheet E 58 of 64 A B Item Page# Function 17 38 HW Date 12/28/2012 C Request Owner Issue Description Compal no PU for volume tuning button D E Solution Description Rev PU VOL_UP# and VOL_DOWN# to 3VS by RP45 and RP44 respectively Rev02 1 18 32 HW 12/28/2012 Compal abnormal display via redriver board to solve the probelm without any gauge increased 19 38 HW 12/28/2012 Compal for keyboard back light auto-negotiation swap the pin connected for EC_SPOK and KB_BKL Rev02 20 17 HW 12/28/2012 Compal to reduce 0-ohm usage remove R488 and R485 becuase GC6 is ready remove R489 and R490 because GC6 is ready Rev02 21 13 HW 12/30/2012 Compal for long-term solution, use 64Mb to replace 32Mb+16Mb change U18 as 8MB ROM part, and only reserve placeholder for U19 Rev02 22 14 HW 12/30/2012 Compal to pervent potential back drive from PCH correct PU domain for OC6# from 3VS to 3VALW_PCH Rev02 23 20 HW 12/30/2012 Compal to reduce 0-ohm usage change R480 to J16 and change R78 to J17 Rev02 24 39 HW 12/30/2012 Compal to reserve power source from 3VLP for LID add R522 and R523 Rev02 25 39 HW 12/30/2012 Compal short-term solution for battery no output with PMOS add R376 and R299 Rev02 26 13 HW 01/03/2013 Compal to trial-run single 8MB SPI ROM add R300, R301, R302 and R303 and only stuff R302 and R303 Rev02 27 35 HW 01/03/2013 Compal add PU resistor for A4 EC's GPIO5B's pin type Add R393 as PU resistor, PU to 3VS_WLAN Rev02 28 42 HW 01/03/2013 Compal hole with diameter 6mm not need screw hole footprint remove H5 Rev02 29 33 HW 01/07/2013 Compal change the CFG pin of Lightning-Bolt from PMOS to in NMOS and one single channel NMOS delete Q17 and Q18, then add Q50 and Q47 Rev02 Rev02 2011/06/24 Compal Electronics, Inc Compal Secret Data Security Classification Issued Date add R521 and C129, then connects PIN27 fo JEDP1 to 3VS, this solution is only for cable which need to pass via re-drvier board Date of EOP Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC PIR-HW Rev 1.0 Ezel M/B Schematics_LAA001P Date: A B C D Sheet E 59 of 64 A B Item Page# Function 30 33 HW Date 01/07/2013 Request Owner Compal C D E Issue Description Solution Description to reduce the usage of 0-ohm Rev replace R309 and R310 by jumps (J11 and J12) Rev02 1 connects EC power from +3VALW to +3VLP, stuff R513 and also change the power domain of lid switch as EC > stuff R522 31 38 HW 01/07/2013 Compal change the power domain of EC 32 HW 01/07/2013 Compal for known issue from DM meeting about RST_GATE# 33 32 HW 01/07/2013 Compal to reduce EDP cable's gauge 34 20 HW 01/07/2013 Compal default as no Erp Lot concern for PCH power remove R479 Rev02 change R520 from 0-ohm to 100k Rev02 add R521 and C129 to replace HPD signal by +LCDVDD, but still reserve R298 and R391 as back-up Rev02 Rev02 35 13 HW 01/07/2013 Compal SPI uses single device topology remove R67 and RP12 36 39 HW 01/07/2013 Compal no need to PU twice for LID_SW# remove R400 37 33 HW 01/07/2013 Compal PU LB_RST when not in debug mode add R324 with 47k 38 18 HW 01/15/2013 Compal to identify SKUs have TPM solution or not after aligning with SW team, add R116 and R118 for DVT 39 39 HW 01/15/2013 Compal let lid swich has the same power domain as EC stuff R522, and de-pop R523 40 33 HW 01/17/2013 Compal update the config1 and config2 control circuit remove Q50, Q47 and R390 and replaced by Q36 and Q38 Rev03 41 33 HW 01/29/2013 Compal to reduce 0-ohm usage remove R316 and R317 Rev03 42 33 HW 01/29/2013 Compal to remove placeholder for depop components remove SW1 Rev03 42 33 HW 01/29/2013 Compal to remove placeholder for depop components remove LED3 and R318 Rev03 Rev02 Rev02 Rev02 Rev02 3 Rev02 4 2011/06/24 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification Date of EOP Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC PIR-HW Rev 1.0 Ezel M/B Schematics_LAA001P Date: A B C D Sheet E 60 of 64 A B Item Page# Function 43 33 HW Date 01/29/2013 C Request Owner Compal D Issue Description E Solution Description to remove placeholder for depop components Rev remove R375 > back-dirve just depends on the configuration of external device for this unexpected situation, we need to keep protect FET present Rev03 1 44 33 HW 01/29/2013 Compal to reduce components which might interfered by RF frame 45 32 HW 01/30/2013 Compal 46 13 HW 01/30/2013 47 38 HW 48 40 49 remove R400, R517 and change R522 and R523 to 0402 size Rev03 ESD test fail add C446 (22p capacitor) close to sensor connector for ESD Rev03 Compal 8MB SPI ROM ready change BOM structure of R75 and R76 to "@" Rev03 01/30/2013 Compal normally update board ID for PVT PCB change R338 from 8.2k to 18k Rev03 HW 01/31/2013 Compal no need to connect BEEP# from EC depop R422 first then track PVT result Rev03 41 HW 02/01/2013 Compal no too many problems from EC, change EC power domain to +3VLP change R513 to short pad Rev03 50 44 HW 02/03/2013 Compal for VGA sequence R469 change from 47k to 270k Rev03 51 18 HW 02/03/2013 Compal ESD test fail add C472, 0.1uF, on mSATA_DET# and close to PCH Rev03 52 33.34 HW 02/05/2013 Compal for cost saving and USB safety concern add U38 (USB power switch) and C526 change R338 from 0-ohm to 100-ohm for discharge circuit replace C457 by C691 and C692 then stuff one of them remove Q19,Q20,R333,R447,Q45,U31,R337,R334,R476 change connection of LB_CHARGE_OFF to test point only Rev03 53 42 HW 02/05/2013 Compal request from ME change H18 from 3P0 to 4P5 Rev03 54 32,38 HW 02/05/2013 Compal no need to support wake-up function by home-key change power to home key from +3VALW to +3VS, change PU domain for home key related signals to +3VS Rev03 55 39 HW 02/05/2013 Compal to prevent worse contact for safety screw hole change H9 footprint to CLIP_SHAPE8P5X7P0-S Rev03 2011/06/24 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification Date of EOP Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC PIR-HW Rev 1.0 Ezel M/B Schematics_LAA001P Date: A B C D Sheet E 61 of 64 A B Item Page# Function 56 HW Date 02/05/2013 Request Owner Compal C D E Issue Description Solution Description Rev remove C93, C689, C128, C109, C110, C123, C125, C407 , C467, C470, C471, R92, C502, C500, R365, C524, C536 ,C592, C542, C560, C658, C659, C660, C661, C664, R70, R71, R111, R117 to reduce depop components Rev03 change to stuff C111, C112, C126 57 34 HW 02/05/2013 Compal for part count reduction, idea from EC depop R393, R344 and Q23 first then track PVT result Rev03 58 36 HW 02/06/2013 Compal to avoid assembly interfere remove C504 Rev03 59 36 HW 02/06/2013 Compal to reduce 0-ohm usage change R407, R408 and R409 from 0-ohm to R-Shotr Rev03 60 35 HW 02/06/2013 Compal add Frame for RF, for USB 3.0 signal noise add CLIP1 Rev03 61 20 HW 02/18/2013 Compal to reduce system power under S4/S5 stuff Q39 and U28 for 3V/5V PCH power Rev03 62 38 HW 02/18/2013 Compal reset battery is defined and toggled only by battery only & and change the design circuit to prevent battery no output caused by PMOS del Q28, R403 and D29 add R390, 100k and PU to +RTCVCC remove C533 Rev03 3 63 43 HW 02/18/2013 Compal after checking VGA sequence, discharge circuit is not needed for 3VSDGPU 64 14 HW 02/18/2013 Compal for part count reduction remove R515 and let SMB_ALERT# connect to RP16 Rev03 65 36 HW 02/18/2013 Compal to avoid components' interfere no stuff C593, C581, C575, C578, C579, C580 Rev03 66 38 HW 02/18/2013 Compal to correct switch button type remove SW6 Rev03 67 40 HW 02/18/2013 Compal to solve the not balance volume output from R/L speaker change R434 from 1k to 1.2k Rev03 no stuff R461 and Q34 Rev03 4 2011/06/24 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification Date of EOP Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC PIR-HW Rev 1.0 Ezel M/B Schematics_LAA001P Date: A B C D Sheet E 62 of 64 A B Item Page# Function Date Request Owner D E Issue Description Solution Description Rev 68 38 HW 02/18/2013 Compal not request from EMC and no reason to keep no stuff C531 Rev03 69 32 HW 02/18/2013 Compal to avoid unstable configuration for HPD cause anything wrong stuff R298 and R391, then depop R521 and C129 Rev03 70 40 HW 02/23/2013 Customer to avoid too large deviation cause problems for speaker volume keep resistance of R434,R437,R426,R429 as before but change the tolerance from 5% to 1% Rev03 Customer to improve thermal problem and base upon request from our end-customer, change PEG CFG to 8X 71 C 4,6 HW 03/10/2013 depop C1,C2,C3,C4,C5,C6,C7,C8,C17,C18,C19,C20, C21,C22,C23,C24,C33,C34,C35,C36,C37,C38,C39,C40, C49,C50,C51,C52,C53,C54,C55,C56 Rev10 add R27 and R28 for PEG CFG to strap to 8-Lane 72 34 HW 03/10/2013 Customer cancel the request to for IOAC supported add J18 then depop C468 and U33 Rev10 73 33 HW 03/10/2013 Comapl to prevent HD3SS2521 only works on DP mode after system cold-boot swap pin-3 and pin-4 of Q48A Rev10 74 39 HW 03/11/2013 Comapl to prevent pop noise add U25, R294 and R87 Rev10 75 33 HW 03/12/2013 Comapl follow TI AE's recommendation chagne R320 to 100k and remove R319 then connected the signal directly Rev10 03/12/2013 Comapl to fix EMI solution and remove unnecessary items del del del del del EMI R293, R304, R410, R430, R440, R297 and L13 then pass the signal directly R305 and L14 then pass the signal directly R412, R413, R414 then pass the signals directly R431, R435, R436 then pass the signals directly R445, R447 then pass the signals directly Rev10 75 32 76 32 ESD 03/12/2013 Comapl request from ESD change R446 from 22p to 100p Rev10 77 32 ESD 03/12/2013 Comapl to fix ESD solution and remove unnecessary items remove D30, D31, D32, D33 Rev10 4 2011/06/24 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification Date of EOP Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC PIR-HW Rev 1.0 Ezel M/B Schematics_LAA001P Date: A B C D Sheet E 63 of 64 A B Item Page# Function 22,44 HW Date 01/23/2013 Request Owner Compal C D E Issue Description Solution Description to meet VGA sequence Rev 1.change R154 to 10k 2.change R469 to 270k Rev02 2 27~30 HW 01/23/2013 Compal to reduce 0.1uF usage for VRAM de-pop C303,C306,C331,C334,C357,C370,C394,C395 Rev02 22,23 HW 01/23/2013 Compal to reduce ohm usage change R153,R177,R178 to R-short Rev03 22,24 HW 01/23/2013 Compal to reduce part count 1.change R137,R139,R140,R141 to RP46 2.change R142,R180,R181,R269 to RP47 3.remove R149 Rev03 22 HW 01/23/2013 Compal simplefy GC6 function circuit 1.change to Diode for GC6_CLAMP_MON remove R509,R268,Q43,Q44B add D7, R360 2.change Q44A to Q45(single MOS) Rev03 27~30 HW 02/02/2013 Compal to reduce de-pop part count HW 02/23/2013 Compal for thermal issue 24 1.De-pop C296,C361,C386 and pop C311,C362,C376 for 10uF 2.remove C296,C297,C303,C306,C312,C326,C331,C334,C336,C337, C348,C357,C361,C363,C370,C386,C387,C388,C394,C395 downgrade the frequeceny by change R174 from 24.9k to 34.8k Rev03 Rev03 3 4 2011/06/24 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification Date of EOP Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC PIR-HW Rev 1.0 Ezel M/B Schematics_LAA001P Date: A B C D Sheet E 64 of 64 ... 10 00 000 0 10 K 10 01 00 01 15K 10 10 0 01 0 20K 10 11 0 011 24.9K 11 00 01 0 0 30. 1K 11 01 01 0 1 34.8K 11 10 01 1 0 45.3K 11 11 01 1 1 STRAP0 USER[3 :0] STRAP1 3GIO_PADCFG_LUT_ADR[3 :0] STRAP2 PCI_DEVID[3 :0] STRAP3... 10 6 10 8 11 0 11 2 11 4 11 6 11 8 12 0 12 2 12 4 12 6 12 8 13 0 13 2 13 4 13 6 13 8 14 0 14 2 14 4 14 6 14 8 15 0 15 2 15 4 15 6 15 8 16 0 16 2 16 4 16 6 16 8 17 0 17 2 17 4 17 6 17 8 18 0 18 2 18 4 18 6 18 8 19 0 19 2 19 4 19 6 19 8 200 ... C5 81 0. 1U _04 02 _16 V4Z C593 10 U _06 03_6.3V6M C525 0. 1U _04 02 _16 V4Z @ +5VS +3VS JHDD1 CONN@ 10 11 12 13 14 15 16 17 18 19 20 G1 G2 G3 G4 C498 0. 1U _04 02 _16 V4Z 10 11 12 13 14 15 16 17 18 19 20 21 22
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