Acer aspire r7 572 r7 572g compal LA a021p rev 1 0 схема

A B C D E Compal Confidential Model Name : V5MM2_Ezel_HW File Name : LA-A021P 1 Compal Confidential 2 M/B Schematics Document Intel Shark Bay ULT (Hasswell + Lynx Point-LP) nVidia N14P-GT 2013-08-XX 3 REV:1.0 4 ZZZ1 Part Number DAZ0YY00100 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification Description PCB V5MM2 LA-A021P LS-A001P/A002P/A003P/A005P/A006P/A007P 2012/11/XX EOP Deciphered Date Title Cover Page THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC V5MM2 M/B LA-A021P Schematic Date: A B C D Tuesday, August 27, 2013 Sheet E of 57 Rev 1.0 A B C D E Fan Control page 37 Lighting Bolt HDMI Conn eDP Conn page 27 page 26 page 28,29 Intel Haswell ULT eDP x lanes DP x lanes HDMI x lanes 2.7GT/s 2.97GT/s 204pin DDR3L-SO-DIMM X1 DDI page 15 BANK 0, 1, 2, Memory BUS Dual Channel Haswell ULT 204pin DDR3L-SO-DIMM X1 1.35V DDR3L 1333/1600 Processor page 16 BANK 4, 5, 6, MINI Card nVidia N14P-GT GDDR5*8 WLAN USB port page 30 OPI page 17~25 PCIe 2.0 5GT/s PCIe 2.0 x4 5GT/s port port USB/B USB2.0 conn x1 USB3.0 conn x2 Flexible IO USB3.0 port 1,2 USB2.0 port 0,1 Lynx Point - LP PCIe 2.0 5GT/s PCIe 2.0 5GT/s port port PCH SATA3.0 SATA3.0 6.0 Gb/s 6.0 Gb/s port Card Reader in (SD/MMC) mSATA HDD Conn Lightning Bolt x1 Touch Panel USB3.0 port USB2.0 port SATA HDD Conn Sensor Hub STM32F USB port page 28 page 31 USB port page 26 page 30 48MHz port page 30 page 31 USBx8 USB port USB port page 31 page 32 CMOS Camera Bluetooth USB port page 26 page 26 1168pin BGA page 04~14 HD Audio 3.3V 24MHz Sub Board LPC BUS RTC CKT page LS-A001P IO/B (USB*1+Cardpage Reader) 31 LS-A002P Sensor/B DC/DC Interface CKT page 39 Power Circuit DC/DC page 39~51 TPM page 38 ACCEL with E-COMPASS LSM303D page page 26 Amplifier page 36 page 26 page 26 Touch Pad page 34 LS-A005P LED/B GYRO L3GD20TR page 26 SPI ROM x2 LS-A003P Redriver/B ALS CM3218 page 26 ALC3225 page 35 ENE KB9012 page 33 Power On/Off CKT page 34 HDA Codec SPI LPC CLK=24MHz Int.KBD page 34 Int Speaker page 34 Int MIC page 36 Combo Jack (HP/MIC) page 36 page 36 4 LS-A006P Power/B page 34 2012/11/XX Issued Date Deciphered Date EOP THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC E-Compass/B page 26 A Compal Electronics, Inc Compal Secret Data Security Classification LS-A007P B C D Title Block Diagrams Size Document Number Custom V5MM2 M/B LA-A021P Schematic Date: Sheet Tuesday, August 27, 2013 E of 57 Rev 1.0 A B C D SIGNAL STATE Voltage Rails Description S1 S3 S5 VIN Adapter power supply (19V) N/A N/A N/A BATT+ Battery power supply (12.6V) N/A N/A N/A B+ AC or battery power rail for power circuit N/A N/A N/A +CPU_CORE Core voltage for CPU ON OFF OFF +VGA_CORE Core voltage for GPU ON OFF OFF HIGH HIGH ON ON ON ON HIGH HIGH ON ON ON LOW S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF Board ID / SKU ID Table for AD channel OFF OFF ON OFF OFF +1.05VS_VTT +1.05VSP to +1.05VS_VTT switched power rail for CPU ON OFF OFF Vcc Ra/Rc/Re +1.35V +1.35VP to +1.35V power rail for DDRIIIL ON ON OFF Board ID +1.5VS +1.5V to +1.5VS switched power rail ON OFF OFF +1.5VSDGPU +1.5VSDGPUP to +1.5VSDGPU switched power rail for GPU ON OFF OFF ON ON ON* ON ON ON +3VS +3VALW to +3VS power rail ON OFF OFF +3VSDGPU +3VS to +3VSDGPU switched power rail for GPU ON OFF OFF +5VALW +5VALWP to +5VALW power rail ON ON ON* +5VS +5VALW to +5VS switched power rail ON OFF OFF ON RTC power ON Device Address Smart Battery 0001 011X EC SM Bus2 address Device On Board Thermal Senser Address 0100 110x VGA Internal Thermal Senser 0100 000x G Senser USB 2.0 DIMM0 1001 000x JDIMM1 ChannelB DIMM1 1001 010x JDIMM2 EHCI1 USB 3.0 XHCI V AD_BID max V 0.289 V 0.538 V 0.875 V 1.264 V 1.759 V 2.341 V 3.300 V Item Unpop Connector UMA only nVidia N14P-GT VRAM Selection With GC6 Without GC6 USB Charger TPM Module without TPM Buzzer EMI,ESD parts PCB Revision 0.1 0.2 0.3 0.4 1.0 Port Address ChannelA V AD_BID typ V 0.250 V 0.503 V 0.819 V 1.185 V 1.650 V 2.200 V 3.300 V USB Port Table 0011 000x PCH SM Bus address Device V AD_BID V 0.216 V 0.436 V 0.712 V 1.036 V 1.453 V 1.935 V 2.500 V B0M Option Table Board ID ON Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF EC SM Bus1 address 3.3V +/- 5% 100K +/- 5% Rb / Rd / Rf 8.2K +/- 5% 18K +/- 5% 33K +/- 5% 56K +/- 5% 100K +/- 5% 200K +/- 5% NC BOARD ID Table HIGH ON +3VALW always on power rail Clock HIGH +0.675VSP to +0.675VS switched power rail for DDR terminator B+ to +3VLP power rail for suspend power +VS LOW +1.05VSDGPU switched power rail for GPU +3VALW +V HIGH +0.675VS +3VLP +VALW S1(Power On Suspend) +1.05VSDGPU +RTCVCC SLP_S1# SLP_S3# SLP_S4# SLP_S5# Full ON Power Plane E Port USB3.0 Connector (Left) USB3.0 Connector (Left) Lightning Bolt mDP Conn USB2.0 (USB/B) Mini Card (WLAN+BT) Touch Panel Sensor Hub Camera BOM Structure @ CONN@ UMA@ DIS@ X76@ GC6@ NGC6@ CHR@ TPM@ NTPM@ BUZZ@ EMC@ XEMC@ RF@ XRF@ DM@ NDM@ RF parts Support DP++ no support DP++ USB Port(Left 3.0) USB Port(Left 3.0) Lightning Bolt USB3.0 4 2012/11/XX Issued Date Compal Electronics, Inc Compal Secret Data Security Classification EOP Deciphered Date Title Notes List THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC V5MM2 M/B LA-A021P Schematic Date: A B C D Tuesday, August 27, 2013 Sheet E of 57 Rev 1.0 1, Directly to mDP connector DP for Lightning-Bolt 3, connected to TI-HD3SS2521 D CPU_DP1_N0 CPU_DP1_P0 CPU_DP1_N1 CPU_DP1_P1 CPU_DP1_N2_C CPU_DP1_P2_C CPU_DP1_N3_C CPU_DP1_P3_C CPU_DP1_N2_C CPU_DP1_P2_C CPU_DP1_N3_C CPU_DP1_P3_C HDMI 1 1 C904 C905 C907 C906 2 2 1U_0402_16V7K 1U_0402_16V7K 1U_0402_16V7K 1U_0402_16V7K CPU_DP1_N2 CPU_DP1_P2 CPU_DP1_N3 CPU_DP1_P3 C54 C55 B58 C58 B55 A55 A57 B57 C51 C50 C53 B54 C49 B50 A53 B53 CPU_DP2_N0 CPU_DP2_P0 CPU_DP2_N1 CPU_DP2_P1 CPU_DP2_N2 CPU_DP2_P2 CPU_DP2_N3 CPU_DP2_P3 DDI1_TXN0 DDI1_TXP0 DDI1_TXN1 DDI1_TXP1 DDI1_TXN2 DDI1_TXP2 DDI1_TXN3 DDI1_TXP3 HASWELL_MCP_E U1A @ EDP_TXN0 EDP_TXP0 EDP_TXN1 EDP_TXP1 DDI EDP DDI2_TXN0 DDI2_TXP0 DDI2_TXN1 DDI2_TXP1 DDI2_TXN2 DDI2_TXP2 DDI2_TXN3 DDI2_TXP3 EDP_TXN2 EDP_TXP2 EDP_TXN3 EDP_TXP3 EDP_AUXN EDP_AUXP EDP_RCOMP EDP_DISP_UTIL Reserved for ESD T20 T2 R68 62_0402_5% H_PROCHOT# C Reserved for ESD R184 470_0603_5% C95 R6 C60 Reserved for ESD placed near to the CPU DIMM_DRAMRST# R11 R13 R41 XEMC@ C1450 100P_0402_50V8J D EDP_AUXN EDP_AUXP EDP_COMP R1 24.9_0402_1% +VCCIOA_OUT Trace width=20 mils,Spacing=25mil,Max length=100mils Rev1p2 D61 K61 N62 @ @ R8 56_0402_5% H_PROCHOT#_R K63 6.8P_0402_50V8C XEMC@ 10K_0402_5% H_CPUPW RGD C61 PROC_DETECT CATERR PECI MISC PRDY PREQ PROC_TCK PROC_TMS PROC_TRST PROC_TDI PROC_TDO JTAG PROCHOT PROCPWRGD THERMAL 1 200_0402_1% SM_RCOMP0 AU60 120_0402_1% SM_RCOMP1 AV60 100_0402_1% SM_RCOMP2 AU61 DIMM_DRAMRST# AV15 AV61 DDR_PG_CTRL DDR_PG_CTRL SM_RCOMP0 SM_RCOMP1 SM_RCOMP2 SM_DRAMRST SM_PG_CNTL1 DDR3 Compensation Signals J62 K62 E60 E61 E59 F63 F62 @ @ @ @ @ @ @ T107 T108 T109 T110 T111 T112 T113 C PWR 6.8P_0402_50V8C XEMC@ BPM#0 BPM#1 BPM#2 BPM#3 BPM#4 BPM#5 BPM#6 BPM#7 Reserved for ESD DIMM_DRAMRST# D20 A43 EDP_TXN2 EDP_TXP2 EDP_TXN3 EDP_TXP3 XEMC@ 6.8P_0402_50V8C H_PECI +1.05VS_VTT A45 B45 HASWELL_MCP_E U1B @ +1.35V C47 C46 A49 B49 EDP_TXN0 EDP_TXP0 EDP_TXN1 EDP_TXP1 EDP_DISP_UTIL OF 19 C94 C45 B46 A47 B47 DDR3 J60 H60 H61 H62 K59 H63 K60 J61 Rev1p2 OF 19 B B U1 U1 U1 U1 CPU_QDJB_B1 QDJB@ CPU_QDJ7_B1 QDJ7@ CPU_QDJ8_B1 QDJ8@ CPU_QEA4_C0 QEA4@ SA000067060 SA000067H50 SA00006G710 SA00006NM00 ES: SA000067060 - QDJB B1 0.8G SA000067H50 - QDJ7 B1 0.8G SA00006G710 - QDJ8 B1 0.8G Pre-QS: SA00006NM00 - QEA4 C0 1.3G 43L: 4319NZBOL05 4319NZBOL06 4319NZBOL07 4319NZBOL08 4319NZBOL09 A A 43L: 4319NZBOL01 4319NZBOL02 4319NZBOL03 4319NZBOL04 U1 U1 U1 U1 U1 CPU_QDJB_B1 QDJBe@ CPU_QDJ7_B1 QDJ7e@ CPU_QDJ6_B1 QDJ6@ CPU_QDJ9_B1 QDJ9@ CPU_QDJC_B1 QDJC@ SA000067060 SA000067H50 SA00006FY20 SA00006G120 SA00006EY30 Compal Electronics, Inc Compal Secret Data Security Classification 2012/11/XX Issued Date Deciphered Date EOP THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title HSW MCP(1/11) DDI,MSIC,XDP Size Document Number Custom V5MM2 M/B LA-A021P Schematic Date: Sheet Tuesday, August 27, 2013 of 57 Rev 1.0 U1C @ HASWELL_MCP_E U1D @ D C DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63 AH63 AH62 AK63 AK62 AH61 AH60 AK61 AK60 AM63 AM62 AP63 AP62 AM61 AM60 AP61 AP60 AP58 AR58 AM57 AK57 AL58 AK58 AR57 AN57 AP55 AR55 AM54 AK54 AL55 AK55 AR54 AN54 AY58 AW58 AY56 AW56 AV58 AU58 AV56 AU56 AY54 AW54 AY52 AW52 AV54 AU54 AV52 AU52 AK40 AK42 AM43 AM45 AK45 AK43 AM40 AM42 AM46 AK46 AM49 AK49 AM48 AK48 AM51 AK51 SA_DQ0 SA_DQ1 SA_DQ2 SA_DQ3 SA_DQ4 SA_DQ5 SA_DQ6 SA_DQ7 SA_DQ8 SA_DQ9 SA_DQ10 SA_DQ11 SA_DQ12 SA_DQ13 SA_DQ14 SA_DQ15 SA_DQ16 SA_DQ17 SA_DQ18 SA_DQ19 SA_DQ20 SA_DQ21 SA_DQ22 SA_DQ23 SA_DQ24 SA_DQ25 SA_DQ26 SA_DQ27 SA_DQ28 SA_DQ29 SA_DQ30 SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37 SA_DQ38 SA_DQ39 SA_DQ40 SA_DQ41 SA_DQ42 SA_DQ43 SA_DQ44 SA_DQ45 SA_DQ46 SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55 SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63 SA_CLK#0 SA_CLK0 SA_CLK#1 SA_CLK1 SA_CKE0 SA_CKE1 SA_CKE2 SA_CKE3 SA_CS#0 SA_CS#1 SA_ODT0 SA_RAS SA_WE SA_CAS SA_BA0 SA_BA1 SA_BA2 DDR CHANNEL A SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7 SA_MA8 SA_MA9 SA_MA10 SA_MA11 SA_MA12 SA_MA13 SA_MA14 SA_MA15 SA_DQSN0 SA_DQSN1 SA_DQSN2 SA_DQSN3 SA_DQSN4 SA_DQSN5 SA_DQSN6 SA_DQSN7 SA_DQSP0 SA_DQSP1 SA_DQSP2 SA_DQSP3 SA_DQSP4 SA_DQSP5 SA_DQSP6 SA_DQSP7 SM_VREF_CA SM_VREF_DQ0 SM_VREF_DQ1 B AU37 AV37 AW36 AY36 SA_CLK_DDR#0 SA_CLK_DDR0 SA_CLK_DDR#1 SA_CLK_DDR1 AU43 AW43 AY42 AY43 DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63 DDRA_CKE0_DIMMA DDRA_CKE1_DIMMA AP33 AR32 DDRA_CS0_DIMMA# DDRA_CS1_DIMMA# AP32 DDRA_ODT0 @ AY34 AW34 AU34 T4 DDR_A_RAS# DDR_A_W E# DDR_A_CAS# AU35 AV35 AY41 DDR_A_BS0 DDR_A_BS1 DDR_A_BS2 AU36 DDR_A_MA0 AY37 DDR_A_MA1 AR38 DDR_A_MA2 AP36 DDR_A_MA3 AU39 DDR_A_MA4 AR36 DDR_A_MA5 AV40 DDR_A_MA6 AW39DDR_A_MA7 AY39 DDR_A_MA8 AU40 DDR_A_MA9 AP35 DDR_A_MA10 AW41DDR_A_MA11 AU41 DDR_A_MA12 AR35 DDR_A_MA13 AV42 DDR_A_MA14 AU42 DDR_A_MA15 AJ61 DDR_A_DQS#0 AN62 DDR_A_DQS#1 AM58 DDR_A_DQS#2 AM55 DDR_A_DQS#3 AV57 DDR_A_DQS#4 AV53 DDR_A_DQS#5 AL43 DDR_A_DQS#6 AL48 DDR_A_DQS#7 AJ62 DDR_A_DQS0 AN61 DDR_A_DQS1 AN58 DDR_A_DQS2 AN55 DDR_A_DQS3 AW57DDR_A_DQS4 AW53DDR_A_DQS5 AL42 DDR_A_DQS6 AL49 DDR_A_DQS7 AP49 AR51 AP51 SM_DIMM_VREFCA SA_DIMM_VREFDQ SB_DIMM_VREFDQ AY31 AW31 AY29 AW29 AV31 AU31 AV29 AU29 AY27 AW27 AY25 AW25 AV27 AU27 AV25 AU25 AM29 AK29 AL28 AK28 AR29 AN29 AR28 AP28 AN26 AR26 AR25 AP25 AK26 AM26 AK25 AL25 AY23 AW23 AY21 AW21 AV23 AU23 AV21 AU21 AY19 AW19 AY17 AW17 AV19 AU19 AV17 AU17 AR21 AR22 AL21 AM22 AN22 AP21 AK21 AK22 AN20 AR20 AK18 AL18 AK20 AM20 AR18 AP18 HASWELL_MCP_E SB_DQ0 SB_DQ1 SB_DQ2 SB_DQ3 SB_DQ4 SB_DQ5 SB_DQ6 SB_DQ7 SB_DQ8 SB_DQ9 SB_DQ10 SB_DQ11 SB_DQ12 SB_DQ13 SB_DQ14 SB_DQ15 SB_DQ16 SB_DQ17 SB_DQ18 SB_DQ19 SB_DQ20 SB_DQ21 SB_DQ22 SB_DQ23 SB_DQ24 SB_DQ25 SB_DQ26 SB_DQ27 SB_DQ28 SB_DQ29 SB_DQ30 SB_DQ31 SB_DQ32 SB_DQ33 SB_DQ34 SB_DQ35 SB_DQ36 SB_DQ37 SB_DQ38 SB_DQ39 SB_DQ40 SB_DQ41 SB_DQ42 SB_DQ43 SB_DQ44 SB_DQ45 SB_DQ46 SB_DQ47 SB_DQ48 SB_DQ49 SB_DQ50 SB_DQ51 SB_DQ52 SB_DQ53 SB_DQ54 SB_DQ55 SB_DQ56 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63 SB_CK#0 SB_CK0 SB_CK#1 SB_CK1 SB_CKE0 SB_CKE1 SB_CKE2 SB_CKE3 SB_CS#0 SB_CS#1 SB_ODT0 SB_RAS SB_WE SB_CAS SB_BA0 SB_BA1 SB_BA2 SB_MA0 SB_MA1 SB_MA2 SB_MA3 SB_MA4 SB_MA5 SB_MA6 SB_MA7 SB_MA8 SB_MA9 SB_MA10 SB_MA11 SB_MA12 SB_MA13 SB_MA14 SB_MA15 DDR CHANNEL B SB_DQSN0 SB_DQSN1 SB_DQSN2 SB_DQSN3 SB_DQSN4 SB_DQSN5 SB_DQSN6 SB_DQSN7 SB_DQSP0 SB_DQSP1 SB_DQSP2 SB_DQSP3 SB_DQSP4 SB_DQSP5 SB_DQSP6 SB_DQSP7 AM38 AN38 AK38 AL38 SB_CLK_DDR#0 SB_CLK_DDR0 SB_CLK_DDR#1 SB_CLK_DDR1 AY49 AU50 AW49 AV50 DDRB_CKE0_DIMMB DDRB_CKE1_DIMMB AM32 AK32 D DDRB_CS0_DIMMB# DDRB_CS1_DIMMB# AL32 DDRB_ODT0 @ T5 AM35 AK35 AM33 DDR_B_RAS# DDR_B_W E# DDR_B_CAS# AL35 AM36 AU49 DDR_B_BS0 DDR_B_BS1 DDR_B_BS2 AP40 DDR_B_MA0 AR40 DDR_B_MA1 AP42 DDR_B_MA2 AR42 DDR_B_MA3 AR45 DDR_B_MA4 AP45 DDR_B_MA5 AW46DDR_B_MA6 AY46 DDR_B_MA7 AY47 DDR_B_MA8 AU46 DDR_B_MA9 AK36 DDR_B_MA10 AV47 DDR_B_MA11 AU47 DDR_B_MA12 AK33 DDR_B_MA13 AR46 DDR_B_MA14 AP46 DDR_B_MA15 C AW30DDR_B_DQS#0 AV26 DDR_B_DQS#1 AN28 DDR_B_DQS#2 AN25 DDR_B_DQS#3 AW22DDR_B_DQS#4 AV18 DDR_B_DQS#5 AN21 DDR_B_DQS#6 AN18 DDR_B_DQS#7 AV30 DDR_B_DQS0 AW26DDR_B_DQS1 AM28 DDR_B_DQS2 AM25 DDR_B_DQS3 AV22 DDR_B_DQS4 AW18DDR_B_DQS5 AM21 DDR_B_DQS6 AM18 DDR_B_DQS7 B DDR_A_D[0 63] DDR_B_D[0 63] DDR_A_MA[0 15] DDR_B_MA[0 15] DDR_A_DQS#[0 7] DDR_B_DQS#[0 7] Rev1p2 OF 19 DDR_A_DQS[0 7] DDR_B_DQS[0 7] Rev1p2 OF 19 A A Compal Electronics, Inc Compal Secret Data Security Classification 2012/11/XX Issued Date Deciphered Date EOP THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title HSW MCP(2/11) DDRIII Size Document Number Custom V5MM2 M/B LA-A021P Schematic Date: Sheet Tuesday, August 27, 2013 of 57 Rev 1.0 PCH_RTCX1 10M_0402_5% PCH_RTCX2 D C153 18P_0402_50V8J R69 20K_0402_1% 2 R70 20K_0402_1% C150 1U_0402_6.3V6K C154 18P_0402_50V8J ME CMOS R72 @ PCH_RTCX1 PCH_RTCX2 1M_0402_5% SM_INTRUDER# PCH_INTVRMEN PCH_SRTCRST# PCH_RTCRST# R71 0_0603_5% HDA_SDIN0 RTCX1 RTCX2 INTRUDER INTVRMEN SRTCRST RTCRST SATA_RN0/PERN6_L3 SATA_RP0/PERP6_L3 SATA_TN0/PETN6_L3 SATA_TP0/PETP6_L3 RTC SATA_RN1/PERN6_L2 SATA_RP1/PERP6_L2 SATA_TN1/PETN6_L2 SATA_TP1/PETP6_L2 CMOS +RTCVCC R73 AW5 AY5 AU6 AV7 AV6 AU7 RTCRST close RAM door Y1 change to SJ100004Z00 on DVT only PCH_INTVRMEN HASWELL_MCP_E U1E @ +RTCVCC 1 +RTCVCC Y1 32.768KHZ_12.5PF_FC-135 C149 1U_0402_6.3V6K R101 T6 T7 T8 T9 HDA_BIT_CLK HDA_SYNC HDA_RST# HDA_SDIN0 @ HDA_SDOUT @ @ @ AW8 AV11 AU8 AY10 AU12 AU11 AW10 AV10 AY8 330K_0402_5% ： ： HDA_BCLK/I2S0_SCLK HDA_SYNC/I2S0_SFRM HDA_RST/I2S_MCLK HDA_SDI0/I2S0_RXD HDA_SDI1/I2S1_RXD HDA_SDO/I2S0_TXD HDA_DOCK_EN/I2S1_TXD HDA_DOCK_RST/I2S1_SFRM I2S1_SCLK AUDIO SATA SATA_RN3/PERN6_L0 SATA_RP3/PERP6_L0 SATA_TN3/PETN6_L0 SATA_TP3/PETP6_L0 SATA0GP/GPIO34 SATA1GP/GPIO35 SATA2GP/GPIO36 SATA3GP/GPIO37 INTVRMEN H Integrated VRM enable L Integrated VRM disable * T95 51_0402_5% HDA for AUDIO C HDA_BITCLK_AUDIO HDA_SYNC_AUDIO HDA_RST_AUDIO# HDA_SDOUT_AUDIO RP14 EMC@ @ T21 T19 T15 @ PCH_JTAG_RST# PCH_JTAG_TCK @ PCH_JTAG_TDI @ PCH_JTAG_TDO @ PCH_JTAG_TMS T11 T22 T12 @ @ PCH_TCK_JTAGX @ R97 AU62 AE62 AD61 AE61 AD62 AL11 AC4 AE63 AV2 SATA_RN2/PERN6_L1 SATA_RP2/PERP6_L1 SATA_TN2/PETN6_L1 SATA_TP2/PETP6_L1 PCH_TRST PCH_TCK PCH_TDI PCH_TDO PCH_TMS RSVD RSVD JTAGX RSVD SATA_IREF RSVD RSVD SATA_RCOMP SATALED JTAG J5 H5 B15 A15 J8 H8 A17 B17 SATA_PRX_DTX_N0 SATA_PRX_DTX_P0 SATA_PTX_DRX_N0 SATA_PTX_DRX_P0 HDD SATA_PRX_DTX_N1 SATA_PRX_DTX_P1 SATA_PTX_DRX_N1 SATA_PTX_DRX_P1 mSATA D J6 H6 B14 C15 PVT PIR-99 F5 E5 C17 D17 V1 U1 V6 AC1 R76 0_0402_5% @ PCH_GPIO34 MSATA_DET# PCH_GPIO36 PCH_GPIO37 A12 L11 @ K10 @ C12 U3 EC_SCI# PCH_GPIO34 MSATA_DET# PCH_GPIO36 PCH_GPIO37 SATA_IREF T13 T14 SATA_RCOMP PCH_SATALED# R75 @ +1.05VS_ASATA3PLL 0_0603_5% within 500 mils R2 R10 1 3.01K_0402_1% 10K_0402_5% +3VS C HDA_BIT_CLK HDA_SYNC HDA_RST# HDA_SDOUT Rev1p2 OF 19 33_0804_8P4R_5% R163 HDA_SDO @ 0_0402_5% B B W=20mils trace width 10mil +RTCBATT +CHGRTC W=20mils +RTCVCC D22 A A BAS40-04_SOT23-3 C151 0.1U_0402_16V4Z Compal Electronics, Inc Compal Secret Data Security Classification 2012/11/XX Issued Date Deciphered Date EOP THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title HSW MCP(3/11) RTC,SATA,XDP Size Document Number Custom V5MM2 M/B LA-A021P Schematic Date: Sheet Tuesday, August 27, 2013 of 57 Rev 1.0 HASWELL_MCP_E U1F @ PCH_GPIO18 C43 C42 U2 CARD_CLKREQ# B41 A41 Y5 XTAL24_IN R48 D 1M_0402_5% XTAL24_OUT PCH_GPIO18 C2 12P_0402_50V8J CLK_PCIE_CARD# CLK_PCIE_CARD CLK_PCIE_CARD# CLK_PCIE_CARD Card Reader Y2 24MHZ_12PF_X3G024000DC1H 1 CARD_CLKREQ# PVT PIR-97 PCIE LAN +3VS C3 12P_0402_50V8J R52 TESTLOW_C35 TESTLOW_C34 TESTLOW_AK8 TESTLOW_AL8 CLOCK SIGNALS CLKOUT_PCIE_N3 CLKOUT_PCIE_P3 PCIECLKRQ3/GPIO21 CLKOUT_LPC_0 CLKOUT_LPC_1 CLKOUT_ITPXDP_N CLKOUT_ITPXDP_P CLKOUT_PCIE_N4 CLKOUT_PCIE_P4 PCIECLKRQ4/GPIO22 B37 A37 T2 PCH_GPIO23 RSVD RSVD DIFFCLK_BIASREF CLKOUT_PCIE_N2 CLKOUT_PCIE_P2 PCIECLKRQ2/GPIO20 A39 B39 U5 PCH_GPIO23 XTAL24_IN XTAL24_OUT CLKOUT_PCIE_N1 CLKOUT_PCIE_P1 PCIECLKRQ1/GPIO19 B38 C37 N1 CLK_PEG_VGA# CLK_PEG_VGA VGA_CLKREQ# CLK_PEG_VGA# CLK_PEG_VGA VGA LAN_CLKREQ# CLK_PCIE_MINI1# CLK_PCIE_MINI1 MINI1_CLKREQ# CLK_PCIE_MINI1# CLK_PCIE_MINI1 MINI1_CLKREQ# WLAN 10K_0402_5% CLKOUT_PCIE_N0 CLKOUT_PCIE_P0 PCIECLKRQ0/GPIO18 C41 B42 AD1 A25 B25 XTAL24_IN XTAL24_OUT K21 @ M21 @ C26 C35 C34 AK8 AL8 AN15 AP15 T16 T17 XCLK_BIASREF R140 R141 R142 R148 1 1 2 2 R78 3.01K_0402_1% +1.05VS_AXCK_LCPLL D 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% CLKOUT_LPC0 CLKOUT_LPC1 EMC@ 22_0402_5% TPM@ 22_0402_5% R390 R395 CLK_PCI_LPC CLK_PCI_TPM B35 A35 CLKOUT_PCIE_N5 CLKOUT_PCIE_P5 PCIECLKRQ5/GPIO23 Rev1p2 OF 19 +3VS VGA_CLKREQ# SMBALERT/GPIO11 SMBCLK SMBDATA SML0ALERT/GPIO60 SMBUS SML0CLK SML0DATA SML1ALERT/PCHHOT/GPIO73 SML1CLK/GPIO75 SML1DATA/GPIO74 LPC LAD0 LAD1 LAD2 LAD3 LFRAME R107 2.2K_0402_5% @ 2 R106 2.2K_0402_5% @ PCH_SPI_CLK PCH_SPI_CS0# for safe PCH_SPI_MOSI PCH_SPI_MISO PCH_SPI_W P1# PCH_SPI_HOLD1# AA3 Y7 Y4 AC2 AA2 AA4 Y6 AF1 SPI_CLK SPI_CS0 SPI_CS1 SPI_CS2 SPI_MOSI SPI_MISO SPI_IO2 SPI_IO3 SPI C-LINK CL_CLK CL_DATA CL_RST SMB_ALERT# PCH_SMBCLK PCH_SMBDATA PCH_GPIO60 SML0CLK SML0DATA PCH_GPIO73 SML1CLK SML1DATA AF2 AD2 AF4 @ @ @ SMB_ALERT# PCH_GPIO73 +3VALW _PCH T23 T24 T25 SML0CLK RP8 SML0DATA PCH_SMBDATA PCH_SMBCLK 0.1U_0402_16V7K RP19 PCH_SPI_IO3_1 PCH_SPI_CLK_1 PCH_SPI_MOSI_1 PCH_SPI_MOSI_1 PCH_SPI_CLK_1 PCH_SPI_IO3_1 PCH_SPI_MISO_1 W 25Q64FVSSIQ_SO8 SA000039A30 PCH_SPI_MOSI PCH_SPI_CLK PCH_SPI_HOLD1# PCH_SPI_MISO EMC@ 15_0804_8P4R_5% 2 D_CK_SDATA Q7A DMN66D0LDW -7_SOT363-6 PCH_SMBCLK D_CK_SCLK S VCC /HOLD(IO3) CLK DI(IO0) D /CS DO(IO1) /WP(IO2) GND R119 4.7K_0402_5% B D_CK_SDATA G PCH_SPI_CS0# PCH_SPI_MISO_1 PCH_SPI_IO2_1 R116 4.7K_0402_5% S Q7B DMN66D0LDW -7_SOT363-6 PCH_SMBDATA D R108 15_0402_5% 2 2.2K_0402_5% 2.2K_0402_5% +3VS U13 PCH_SPI_W P1# R114 R113 C66 2.2K_0804_8P4R_5% G SPI ROM ( 8MByte ) Rev1p2 D29 design for Debug board flash SPI ROM (can be short after MP) +3VS B C PCH_GPIO60 SML1CLK SML1DATA OF 19 +3VS AN2 AP2 AH1 AL2 AN1 AK1 AU4 AU3 AH3 LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 LPC_FRAME# D AU14 LPC_AD0 AW12 LPC_AD1 AY12 LPC_AD2 AW11 LPC_AD3 LPC_FRAME# AV12 1 DIS@ Q2 2N7002K_SOT23-3 2 R111 0_0402_5% @ S PEG_CLKREQ# G C Pull high @ VGA side HASWELL_MCP_E U1G @ R105 10K_0402_5% VGA_ON D_CK_SCLK Reserve for EMI(Near SPI ROM) 1K_0402_5% 1K_0402_5% C152 10P_0402_50V8J 2 PCH_SPI_CLK_1 XEMC@ R104 XEMC@ 33_0402_5% PCH_SPI_HOLD1# PCH_SPI_W P1# +3VS PU 2.2K at EC side (+3VS) G EC_SMB_CK2 S D Q8B DMN66D0LDW -7_SOT363-6 SML1CLK G EC_SMB_DA2 S D Q8A DMN66D0LDW -7_SOT363-6 SML1DATA R103 R102 +3VS A A Compal Electronics, Inc Compal Secret Data Security Classification 2012/11/XX Issued Date Deciphered Date EOP THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title HSW MCP(4/11) CLK,SPI,SMBUS Size Document Number Custom V5MM2 M/B LA-A021P Schematic Date: Sheet Tuesday, August 27, 2013 of 57 Rev 1.0 1 +3VS R227 10K_0402_5% PM_APW ROK R64 0_0402_5% 1 R110 0_0402_5% * LH： ：Enable(DEFAULT) Disable DSWODVREN - On Die DSW VR Enable SYS_RESET# PCH_PW ROK_R R124 R125 D PBTN_OUT# ESD request close U1 XEMC@ C937 22P_0402_50V8J @ PBTN_OUT#_R SUSW ARN# SYS_PW ROK PCH_PW ROK VCCST_PG_EC R117 PCH_RSMRST# PCH_RSMRST# 10K_0402_5% 1 Note: EC is +3VL change to @ +3VALW _PCH R156 0_0402_5% PCH_RSMRST#_R SUSW ARN# SUSW ARN# PBTN_OUT#_R PCH_ACIN 8.2K_0402_5% PCH_BATLOW # T31 @ @ AK2 AC3 AG2 AY7 AB5 AG7 SUSACK SYS_RESET SYS_PWROK PCH_PWROK APWROK PLTRST AW6 AV4 AL7 AJ8 AN4 AF3 AM5 AW7 AV5 AJ5 DSWVRMEN DPWROK WAKE V5 AG4 AE6 AP5 CLKRUN/GPIO32 SUS_STAT/GPIO61 SUSCLK/GPIO62 SLP_S5/GPIO63 RSMRST SUSWARN/SUSPWRDNACK/GPIO30 PWRBTN ACPRESENT/GPIO31 BATLOW/GPIO72 SLP_S0 SLP_WLAN/GPIO29 DSW ODVREN PCH_RSMRST#_R PCH_PCIE_W AKE# 1K_0402_5% 8.2K_0402_5% PCH_GPIO32 @ @ AJ6 AT4 AL5 AP4 AJ7 SLP_S4 SLP_S3 SLP_A SLP_SUS SLP_LAN PM_SLP_S4# PM_SLP_S3# @ @ PM_SLP_LAN# +3VALW _PCH +3VS SUSCLK PM_SLP_S5# T27 T28 @ T29 PM_SLP_S4# PM_SLP_S3# T30 T96 R118 @ 10K_0402_5% +3VALW _PCH not support Deep S4,S5 can NC C 2 D Rev1p2 OF 19 Note: Deep Sx need use EC GPIO for ACPRESENT function @ R245 100K_0402_5% @ D21 R120 R157 SUSCLK PM_SLP_S5# +3VALW_PCH ACIN 330K_0402_5% 330K_0402_5% @ SYSTEM POWER MANAGEMENT R206 0_0402_5% SUSACK# SYS_RESET# 0_0402_5% SYS_PW ROK_R R61 @ 0_0402_5% R62 PCH_PW ROK_R 0_0402_5% R63 @ PM_APW ROK PLT_RST# PLT_RST# R79 @ +RTCVCC HASWELL_MCP_E U1H @ DDPB_CTRLDATA: Port B Detected DDPC_CTRLDATA: Port C Detected PCH_ACIN C RB751V40_SC76-2 * R65 1: Port B or C is detected 0: Port B or C is not detected (Have internal PD) 0_0402_5% HASWELL_MCP_E U1I @ Y A R207 10K_0402_5% @ EC_SMI# VGA_ON_PCH DGPU_HOLD_RST#_PCH U17 @ NC VGATE VCC A Y @ R310 10K_0402_5% VGATE_3V PCH_GPIO55 PCH_GPIO51 EDP_BKLCTL EDP_BKLEN EDP_VDDEN U6 EC_SMI# P4 VGA_ON_PCH DGPU_HOLD_RST#_PCH N4 N2 PCH_GPIO80 AD4 T26 @ PCH_GPIO55 PCH_GPIO52 Project_ID1 PCH_GPIO51 Project_ID0 PIRQA/GPIO77 PIRQB/GPIO78 PIRQC/GPIO79 PIRQD/GPIO80 PME U7 L1 L3 R5 L4 DDPB_CTRLCLK DDPB_CTRLDATA DDPC_CTRLCLK DDPC_CTRLDATA eDP SIDEBAND DISPLAY GPIO DDPB_AUXN DDPC_AUXN DDPB_AUXP DDPC_AUXP GPIO55 GPIO52 GPIO54 GPIO51 GPIO53 DDPB_HPD DDPC_HPD EDP_HPD B +3VS +1.05VS_VTT B8 A9 C6 PCH_INV_PW M ENBKL PCH_ENVDD SYS_PW ROK U43 @ MC74VHC1G08DFT2G_SC70-5 R208 10K_0402_5% ESD request close U1 B 1 G VGATE_3V XEMC@ C936 22P_0402_50V8J PCH_PW ROK 1 P +3VS C5 B6 B5 A6 CPU_DP1_AUXN DDPB_CTRLCLK DDPB_CTRLDATA DDI2_CTRL_CK DDI2_CTRL_DATA CPU_DP1_AUXN CPU_DP1_AUXP CPU_DP1_AUXP C8 A8 D6 CPU_LB_HPD CPU_HDMI_HPD CPU_EDP_HPD B Rev1p2 OF 19 VGATE_3V B9 C9 D9 DDI2_CTRL_CK D11 DDI2_CTRL_DATA GND VGA_ON_PCH R407 74AUP1G07GW _TSSOP5 R81 0_0402_5% @ +3VS VGA_ON_EC VGA_ON_EC @ R405 DIS@ 0_0402_5% VGA_ON VGA_ON 0_0402_5% R403 2_0402_1% +3VS R214 10K_0402_5% @ R215 10K_0402_5% Project_ID0 Project_ID1 Project_ID0 GPIO54 GPIO53 V5WE2/T2 UMA 0 *V5WE2/T2 DIS V5MM2 x 1 @ 0_0402_5% R391 100K_0402_5% DIS@ 2 C932 22P_0402_50V8J XEMC@ IN1 IN2 OUT PLT_RST_BUF# R67 IRST_RST# R416 100K_0402_5% U30 MC74VHC1G08DFT2G_SC70-5 IRST_RST# PLT_RST# VCC DGPU_HOLD_RST# @ IN2 0_0402_5% R404 DIS@ 0_0402_5% U37 MC74VHC1G08DFT2G_SC70-5 DIS@ PLTRST_VGA# GND A ESD request close U30 Project ID Project_ID1 R204 10K_0402_5% @ R205 10K_0402_5% A +3VS +3VS R406 @ OUT DGPU_HOLD_RST#_EC DGPU_HOLD_RST#_EC IN1 DGPU_HOLD_RST#_PCH 1 PLT_RST# VCC MINI1_CLKREQ# PCH_GPIO33 GND PCH_GPIO52 PCH_GPIO80 MINI1_CLKREQ# PCH_GPIO33 10K_0804_8P4R_5% +3VS RP27 Compal Electronics, Inc Compal Secret Data Security Classification 2012/11/XX Issued Date Deciphered Date EOP THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title HSW MCP(5/11) PM,GPIO,DDI Size Document Number Custom V5MM2 M/B LA-A021P Schematic Date: Sheet Tuesday, August 27, 2013 of 57 Rev 1.0 +3VS +3VS PCH_GPIO55 SERIRQ PCH_GPIO51 PCH_GPIO83 10K_0804_8P4R_5% PCH_GPIO68 PCH_GPIO4 10K_0804_8P4R_5% PCH_GPIO5 PCH_GPIO1 PCH_GPIO94 PCH_GPIO93 10K_0804_8P4R_5% PCH_GPIO2 PCH_GPIO91 PCH_GPIO90 DEVSLP1 10K_0804_8P4R_5% CARD_CLKREQ# PCH_GPIO36 VGA_ON_PCH EC_KBRST# 10K_0804_8P4R_5% PCH_GPIO18 MSATA_DET# PCH_GPIO48 PCH_GPIO34 10K_0804_8P4R_5% PCH_GPIO71 PCH_GPIO49 PCH_GPIO16 PCH_GPIO37 10K_0804_8P4R_5% RP16 RP28 RP29 RP30 C RP31 RP32 R311 10K_0402_5% PCH_GPIO88 PCH_GPIO92 PCH_GPIO85 PCH_GPIO39 10K_0804_8P4R_5% +1.05VS_VTT HASWELL_MCP_E U1J @ R144 1K_0402_5% D P1 PCH_GPIO76 AU2 EC_LID_OUT#_TAB AM7 AD6 EC_LID_OUT# Y1 PCH_GPIO16 T3 PCH_GPIO17 PCH_GPIO24 AD5 PCH_GPIO27 AN5 PCH_GPIO28 AD7 PCH_GPIO26 AN3 EC_LID_OUT#_TAB EC_LID_OUT# CARD_CLKREQ# PCH_GPIO36 VGA_ON_PCH PCH_GPIO18 MSATA_DET# PCH_GPIO56 PCH_GPIO57 PCH_GPIO58 PCH_GPIO59 SNSR_HUB_DFU_EN# PCH_GPIO47 PCH_GPIO48 PCH_GPIO49 PCH_GPIO50 PCH_GPIO71 PCH_GPIO13 PCH_GPIO14 PCH_GPIO25 PCH_GPIO45 SNSR_HUB_PW R_GATE TOUCH_PANEL_INT# SNSR_HUB_DFU_EN# PCH_GPIO34 PCH_GPIO37 PCH_GPIO67 PCH_GPIO65 PCH_GPIO64 10K_0804_8P4R_5% PCH_GPIO84 PCH_GPIO0 PCH_GPIO3 PCH_GPIO89 10K_0804_8P4R_5% PCH_GPIO17 PCH_GPIO23 PCH_GPIO76 PCH_GPIO50 10K_0804_8P4R_5% PCH_GPIO70 SNSR_HUB_PW R_GATE TOUCH_PANEL_INT# EC_SCI# EC_SCI# R77 AG6 AP1 AL4 AT5 AK4 AB6 U4 Y3 P3 Y2 AT3 AH4 AM4 AG5 AG3 AM3 0_0402_5% PCH_GPIO10 AM2 P2 PCH_GPIO33 C4 PCH_GPIO70 L2 DEVSLP1 DEVSLP1 N5 PCH_GPIO39 V2 PCH_SPKR PCH_SPKR @ PCH_GPIO33 BMBUSY/GPIO76 GPIO8 LAN_PHY_PWR_CTRL/GPIO12 GPIO15 GPIO16 GPIO17 GPIO24 GPIO27 GPIO28 GPIO26 GPIO56 GPIO57 GPIO58 GPIO59 GPIO44 GPIO47 GPIO48 GPIO49 GPIO50 HSIOPC/GPIO71 GPIO13 GPIO14 GPIO25 GPIO45 GPIO46 THERMTRIP RCIN/GPIO82 SERIRQ PCH_OPI_RCOMP RSVD RSVD CPU/ MISC GSPI0_CS/GPIO83 GSPI0_CLK/GPIO84 GSPI0_MISO/GPIO85 GSPI0_MOSI/GPIO86 GSPI1_CS/GPIO87 GSPI1_CLK/GPIO88 GSPI1_MISO/GPIO89 GSPI_MOSI/GPIO90 UART0_RXD/GPIO91 UART0_TXD/GPIO92 UART0_RTS/GPIO93 UART0_CTS/GPIO94 UART1_RXD/GPIO0 UART1_TXD/GPIO1 UART1_RST/GPIO2 UART1_CTS/GPIO3 I2C0_SDA/GPIO4 I2C0_SCL/GPIO5 I2C1_SDA/GPIO6 I2C1_SCL/GPIO7 SDIO_CLK/GPIO64 SDIO_CMD/GPIO65 SDIO_D0/GPIO66 SDIO_D1/GPIO67 SDIO_D2/GPIO68 SDIO_D3/GPIO69 GPIO LPIO GPIO9 GPIO10 DEVSLP0/GPIO33 SDIO_POWER_EN/GPIO70 DEVSLP1/GPIO38 DEVSLP2/GPIO39 SPKR/GPIO81 PCH_GPIO23 D60 H_THERMTRIP# V4 T4 SERIRQ AW15 PCH_OPIRCOMP AF20 @ T106 AB21 @ T32 R6 L6 N6 L8 R7 L5 N7 K2 J1 K3 J2 G1 K4 G2 J3 J4 F2 F3 G4 F1 E3 F4 D3 E4 C3 E2 PCH_GPIO83 PCH_GPIO84 PCH_GPIO85 PCH_GPIO86 DGPU_PRSNT# PCH_GPIO88 PCH_GPIO89 PCH_GPIO90 PCH_GPIO91 PCH_GPIO92 PCH_GPIO93 PCH_GPIO94 PCH_GPIO0 PCH_GPIO1 PCH_GPIO2 PCH_GPIO3 PCH_GPIO4 PCH_GPIO5 EC_KBRST# SERIRQ R145 49.9_0402_1% +3VS RP26 R1337 1K_0402_5% R1338 1K_0402_5% RP25 4 RP36 D PCH_GPIO51 RP24 PCH_GPIO55 RP23 C PCH_I2C1_SDA PCH_I2C1_SCL PCH_GPIO64 PCH_GPIO65 PCH_GPIO66 PCH_GPIO67 PCH_GPIO68 PCH_GPIO69 PVT PIR-89 Rev1p2 10 OF 19 PVT PIR-65 +3VALW _PCH +3VS +3VS RP37 RP38 RP39 RP40 R248 10K_0402_5% 10K_0804_8P4R_5% PCH_GPIO73 +3VALW _PCH +3VALW _PCH 1 USB_OC1# USB_OC1# PCH_GPIO13 PCH_GPIO26 10K_0804_8P4R_5% PCH_GPIO45 PCH_GPIO14 SNSR_HUB_DFU_EN# SNSR_HUB_PW R_GATE 10K_0804_8P4R_5% DGPU_HOLD_RST#_PCH DGPU_HOLD_RST#_PCH PCH_GPIO47 PCH_GPIO24 PCH_GPIO28 10K_0804_8P4R_5% PCH_GPIO58 PCH_GPIO59 PCH_GPIO27 PCH_GPIO25 10K_0804_8P4R_5% USB_OC2# USB_OC2# PCH_GPIO60 PCH_GPIO60 USB_OC0# USB_OC0# TOUCH_PANEL_INT# TPM@ R313 10K_0402_5% R301 10K_0402_5% R303 10K_0402_5% PCH_GPIO69 B PCH_GPIO56 NTPM@ R312 10K_0402_5% B SMB_ALERT# SUSW ARN# PCH_GPIO43 RP35 PCH_GPIO10 SMB_ALERT# SUSW ARN# PCH_GPIO43 10K_0804_8P4R_5% 1 PCH_GPIO57 +3VS R269 With TPM Without TPM RP34 GPIO69 1K_0402_1% @ SPKR / GPIO81 : NO REBOOT 1: ENABLED * +3VALW _PCH 0: DISABLED (Have internal PD) +3VS PCH_GPIO66 R247 R249 PCH_GPIO73 PCH_SPKR @ @ 10K_0402_5% 10K_0402_5% EC_LID_OUT# EC_LID_OUT#_TAB GPIO15 : TLS Confidentiality PCH_GPIO86 R272 R273 R270 @ 1K_0402_1% 1K_0402_1% 1K_0402_5% @ GSPI0_MOSI / GPIO86 : Boot BIOS Strap SDIO_D0 / GPIO66 : Top-Block Swap Override +3VS R306 10K_0402_5% UMA@ 1: Intel ME TLS with confidentiality 1: ENABLED 0: Intel ME TLS with no confidentiality 0: SPI ROM (Have internal PD) (Have internal PD) * * 1: ENABLED (Have internal PU) 0: DISABLED A * GPIO87 DGPU_PRSNT# DGPU_PRSNT# R219 10K_0402_5% DIS@ DIS,Optimus UMA Compal Electronics, Inc Compal Secret Data Security Classification 2012/11/XX Issued Date Deciphered Date EOP THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A Title HSW MCP(6/11) GPIO,LPIO Size Document Number Custom V5MM2 M/B LA-A021P Schematic Date: Sheet Tuesday, August 27, 2013 of 57 Rev 1.0 HASWELL_MCP_E U1K @ C76 C77 1 DIS@ 0.22U_0402_10V6K DIS@ 0.22U_0402_10V6K PEG_GTX_C_HRX_N0 F10 PEG_GTX_C_HRX_P0 E10 PEG_HTX_C_GRX_N0 C78 PEG_HTX_C_GRX_P0 C79 1 DIS@ 0.22U_0402_10V6K DIS@ 0.22U_0402_10V6K PEG_HTX_GRX_N0 PEG_HTX_GRX_P0 PEG_GTX_HRX_N1 PEG_GTX_HRX_P1 PEG_GTX_HRX_N0 PEG_GTX_HRX_P0 PEG_GTX_HRX_N[0 3] PEG_GTX_HRX_P[0 3] D PEG_HTX_C_GRX_N[0 3] PEG_HTX_C_GRX_P[0 3] PCIE LAN WLAN C80 C81 1 DIS@ 0.22U_0402_10V6K DIS@ 0.22U_0402_10V6K PEG_GTX_C_HRX_N1 F8 PEG_GTX_C_HRX_P1 E8 PEG_HTX_C_GRX_N1 C82 PEG_HTX_C_GRX_P1 C83 1 DIS@ 0.22U_0402_10V6K DIS@ 0.22U_0402_10V6K PEG_HTX_GRX_N1 PEG_HTX_GRX_P1 PEG_GTX_HRX_N2 PEG_GTX_HRX_P2 C84 C85 1 DIS@ 0.22U_0402_10V6K DIS@ 0.22U_0402_10V6K PEG_GTX_C_HRX_N2 H10 PEG_GTX_C_HRX_P2 G10 PEG_HTX_C_GRX_N2 C86 PEG_HTX_C_GRX_P2 C87 1 DIS@ 0.22U_0402_10V6K DIS@ 0.22U_0402_10V6K PEG_HTX_GRX_N2 PEG_HTX_GRX_P2 PEG_GTX_HRX_N3 PEG_GTX_HRX_P3 C88 C89 1 DIS@ 0.22U_0402_10V6K DIS@ 0.22U_0402_10V6K PEG_GTX_C_HRX_N3 E6 PEG_GTX_C_HRX_P3 F6 PEG_HTX_C_GRX_N3 C90 PEG_HTX_C_GRX_P3 C91 1 DIS@ 0.22U_0402_10V6K DIS@ 0.22U_0402_10V6K PEG_HTX_GRX_N3 PEG_HTX_GRX_P3 PVT PIR-97 Card Reader B21 C21 B22 A21 C29 B30 PCIE_PRX_DTX_N4 PCIE_PRX_DTX_P4 C156 C157 1 0.1U_0402_16V7K 0.1U_0402_16V7K PCIE_PRX_DTX_N4 PCIE_PRX_DTX_P4 F13 G13 PCIE_PTX_DRX_N4 PCIE_PTX_DRX_P4 B29 A29 G17 F17 PCH_USB3_RX3_N PCH_USB3_RX3_P USB3 for Lightning Bolt B23 A23 G11 F11 PCIE_PTX_C_DRX_N4 PCIE_PTX_C_DRX_P4 C C23 C22 C165 C160 PCH_USB3_TX3_N_C PCH_USB3_TX3_P_C 1 0.1U_0402_16V7K 0.1U_0402_16V7K PCIE_PRX_DTX_N2 PCIE_PRX_DTX_P2 C166 C164 PCIE_PTX_C_DRX_N2 PCIE_PTX_C_DRX_P2 1 0.1U_0402_16V7K 0.1U_0402_16V7K PCH_USB3_TX3_N PCH_USB3_TX3_P C30 C31 PCIE_PRX_DTX_N2 PCIE_PRX_DTX_P2 F15 G15 PCIE_PTX_DRX_N2 PCIE_PTX_DRX_P2 B31 A31 PERN5_L0 PERP5_L0 USB2N0 USB2P0 PETN5_L0 PETP5_L0 USB2N1 USB2P1 PERN5_L1 PERP5_L1 USB2N2 USB2P2 PETN5_L1 PETP5_L1 USB2N3 USB2P3 PERN5_L2 PERP5_L2 USB2N4 USB2P4 PETN5_L2 PETP5_L2 USB2N5 USB2P5 PERN5_L3 PERP5_L3 USB2N6 USB2P6 PETN5_L3 PETP5_L3 USB2N7 USB2P7 PERN3 PERP3 USB3RN1 USB3RP1 PETN3 PETP3 USB PCIe PERN4 PERP4 R232 R155 1 @ 3.01K_0402_1% 0_0603_5% @ E15 @ E13 A27 B27 USB3TN1 USB3TP1 USB3RN2 USB3RP2 PETN4 PETP4 USB3TN2 USB3TP2 AN8 AM8 USB20_N0 USB20_P0 AR7 AT7 USB20_N1 USB20_P1 AR8 AP8 USB20_N2 USB20_P2 AR10 AT10 USB20_N3 USB20_P3 AM15 AL15 USB20_N4 USB20_P4 AM13 AN13 USB20_N5 USB20_P5 AP11 AN11 USB20_N6 USB20_P6 AR13 AP13 USB20_N7 USB20_P7 G20 H20 USB20_N0 USB20_P0 USB2 Port (USB3.0 P1) USB20_N1 USB20_P1 USB2 Port (USB3.0 P2) USB20_N2 USB20_P2 USB2 Port (USB3.0 P3) For Lightning Bolt USB20_N3 USB20_P3 USB2.0 D/B USB20_N4 USB20_P4 Mini Card (WLAN+BT) USB20_N5 USB20_P5 Panel Touch IC USB20_N6 USB20_P6 Sensor Hub USB20_N7 USB20_P7 Camera D PCH_USB3_RX1_N PCH_USB3_RX1_P C33 B34 USB3 Port PCH_USB3_TX1_N PCH_USB3_TX1_P E18 F18 PCH_USB3_RX2_N PCH_USB3_RX2_P B33 A33 USB3 Port PCH_USB3_TX2_N PCH_USB3_TX2_P PERN1/USB3RN3 PERP1/USB3RP3 C USB3.0 P3 / PCIE P1 PETN1/USB3TN3 PETP1/USB3TP3 PERN2/USB3RN4 PERP2/USB3RP4 USB3.0 P4 / PCIE P2 USBRBIAS USBRBIAS RSVD RSVD PETN2/USB3TN4 PETP2/USB3TP4 OC0/GPIO40 OC1/GPIO41 OC2/GPIO42 OC3/GPIO43 +1.05VS_AUSB3PLL T33 T34 PCIE_RCOMP PCIE_IREF RSVD RSVD PCIE_RCOMP PCIE_IREF AJ10 AJ11 AN10 AM10 AL3 AT1 AH2 AV3 USBRBIAS R154 22.6_0402_1% USB_OC0# USB_OC1# USB_OC2# PCH_GPIO43 USB_OC0# USB_OC1# USB_OC2# PCH_GPIO43 11 OF 19 CAD note: Route single-end 50-ohms and max 450-mils length Avoid routing next to clock pins or under stitching capacitors Recommended minimum spacing to other signal traces is 15 mils C612 0.1U_0402_16V4Z @ Rev1p2 B B A A Compal Electronics, Inc Compal Secret Data Security Classification 2012/11/XX Issued Date Deciphered Date EOP THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title HSW MCP(7/11) PCIE,USB Size Document Number Custom V5MM2 M/B LA-A021P Schematic Date: Sheet Tuesday, August 27, 2013 10 of 57 Rev 1.0 A B C D EN1 and EN2 dont't floating E PR404 499K_0402_1% ENLDO_3V5V 3V5V_EN +3VLP PR416 100K_0402_5% PC411 4.7U_0603_6.3V6K X76_2@ PU401 SY8206BQNC QFN 10P PWM 3.3V LDO 1500mA~300mA SPOK @ B+ Rshort@ MAINPWON ENLDO_3V5V PC401 4.7U_0402_6.3V6M PR403 160K_0402_1% Rshort@ 2 VCC OUT PG LDO 0_0603_5% 10 VL SY8208CQNC_QFN10_3X3 X76_2@ PU402 SY8206CQNC QFN 10P PWM PC424 4.7U_0603_6.3V6K 2012/12/14 Vout is 4.998V~5.202V SH00000O400 X76_1@ PL404 LX_5V SPOK PC418 4.7U_0603_6.3V6K LX 7*7*3 VCC_3.3V GND 2 +5VALWP 1UH_FDSD0630-H-1R0M-P3_11A_20% X76_2@ PL404 1UH +-20% PCMC063T-1R0MN 11A PC422 22U_0805_6.3V6M BST_5V PC416 0.1U_0603_25V7K PC421 22U_0805_6.3V6M PR408 PC420 22U_0805_6.3V6M BS PC425 PR412 6800P_0402_25V7K 1K_0402_5% FB 3V5V_EN PC419 22U_0805_6.3V6M EN 680P_0603_50V7K 4.7_1206_5% IN Ipeak=5.6A ; Imax=3.92A ;Iocp=8A PR414 @ 0_0402_5% X76_1@ @EMI@ @EMI@ PC423 PR409 5V_SN PU402 @EMI@ PC417 0.1U_0402_25V6 @EMI@ PC415 2200P_0402_50V7K PC414 10U_0805_25V6K @ 2012/12/14 Vout is 3.234V~3.366V 5V_VIN PC413 10U_0805_25V6K +3VALW Ipeak=5.6A ; Imax=3.92A ;Iocp=8A EMI@ PL403 HCB2012KF-121T50_0805 3V5V_EN EN1 and EN2 dont't floating B+ PR402 PR410 1M_0402_1% PR411 953K_0402_1% VS PJ401 JUMP_43X118 0_0402_5% VIN PD401 LL4148_LL34-2 @ +3VALWP @ PR401 2.2K_0402_5% EC_ON PR415 499K_0402_1% X76_2@ PL402 1UH +-20% PCMC063T-1R0MN 11A PC410 22U_0805_6.3V6M SY8208BQNC_QFN10_3X3 Check pull up resistor of SPOK at HW side +3VALWP LDO 1UH_FDSD0630-H-1R0M-P3_11A_20% PG LX_3V SH00000O400 X76_1@ PL402 1 3V_SN OUT +3VALW GND 7*7*3 0.1U_0603_25V7K 10 LX 0_0603_5% Rshort@ PC409 22U_0805_6.3V6M PR405 PC408 22U_0805_6.3V6M BST_3V PC404 2 BS @ PC426 PR413 0.022U_0402_16V7K 1K_0402_5% 2 FB PC407 22U_0805_6.3V6M 1 EN1 IN B+ EN2 680P_0603_50V7K @EMI@ PC412 PC406 10U_0805_25V6K PC405 10U_0805_25V6K @EMI@ PC403 2200P_0402_50V7K @EMI@ PC402 0.1U_0402_25V6 1 3V_VIN 4.7_1206_5% EMI@ PL401 HCB2012KF-121T50_0805 X76_1@ PR407 @EMI@ PU401 PR406 150K_0402_1% B+ +5VALWP @ PJ402 2 +5VALW JUMP_43X118 5V LDO 1500mA~300mA 4 Compal Secret Data Security Classification 2011/06/15 Issued Date 2012/07/11 Deciphered Date Title Compal Electronics, Inc +3VALW/+5VALW THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C D Rev 1.0 Tuesday, August 27, 2013 Sheet E 43 of 57 A +1.35V_B+ VDDP VTTREF VDDQ PC506 10U_0805_6.3V6M VTTREF_1.35V +1.35VP X76_2@ PU501 G5616ARZ1U TQFN 20P PWM FB 2 PC510 0.033U_0402_16V7K S3 S5 EN_1.35V 10 +5VALW EN_0.675VSP VDD 20 19 VLDOIN 18 BOOT VTT GND RT8207MZQW_WQFN20_3X3 CS 21 PR501 887K_0402_1% +1.35V_B+ 20130627 PR506 8.2K_0402_1% +1.35VP 1 AON7702A SB00000T600_EOL charger to AON7506 SB000010A00 FB_1.35V PC511 1U_0603_10V6K 17 PHASE VTTSNS TON 11 VDD_1.35V UGATE 16 PAD VTTGND PGND PGOOD +5VALW PQ502 AON7506 12 PU501 PC505 10U_0805_6.3V6M 2 PR505 5.1_0603_5% 13 LGATE @EMI@ PC512 680P_0402_50V7K PR503 9.31K_0402_1% CS_1.35V PC507 1U_0603_10V6K X76_1@ 15 X76_2@ PQ502 SI7716ADN-T1-GE3 1N POWERPAK1212-8 @EMI@ PR504 4.7_1206_5% + LG_1.35V 14 PC508 330U_2.5V_M ESR=15m ohm 7*7*4 X76_1@ PL502 1.5UH_TMPB0604M-1R5MN-Z01_11A_20% +1.35VP X76_1@ (1.1%) +0.675VSP LX_1.35V PC504 0.1U_0603_25V7K X76_1@ SH00000PM00 +1.35VP UG_1.35V PQ501 AON7408L Vout=1.364V BOOT_1.35V X76_2@ PL502 1.5uH PCME064T-1R5MS PR502 2.2_0603_5% 0.75Volt +/- 5% TDC 0.7A Peak Current 1A X76_2@ PQ501 SIS412DN-T1-GE3 1N POWERPAK1212-8 PC503 10U_0805_25V6K @EMI@ PC502 2200P_0402_50V7K @EMI@ PC501 0.1U_0402_25V6 BST_1.35V TON_1.35V B+ Pin19 need pull separate from +1.5VP If you have +1.5V and +0.75V sequence question, you can change from +1.5VP to +1.5VS EMI@ PL501 HCB2012KF-121T50_0805 Level L L H +0.675VSP off off on VTTREF_13.5V off on on DDR_VTT_PG_CTRL Note: S3 - sleep ; S5 - power off @ PC514 0.1U_0402_10V7K @ PR509 680K_0402_1% SUSP# Rshort@ PR510 0_0402_5% 1 Mode S5 S3 S0 PC513 1U_0402_16V7K SYSON PR507 10K_0402_1% Rshort@ PR508 0_0402_5% Ipeak=6A ; Imax=4.2A ;Iocp=7.2A Delta I=2.93=>1/2Delta I=1.47A (F=285K Hz) Rds(on)=13m ohm(max) ; Rds(on)=9.9m ohm(typical) Ilimit_min=5.75A Ilimit_max=8.86A Iocp=Ilimit+1/2Delta I =7.22~10.33A PC515 0.1U_0402_10V7K PJ501 @ +1.35VP @ SUSP @ Issued Date JUMP_43X118 +0.675VSP S 2N7002KW_SOT323-3 @ Deciphered Date +0.675VS JUMP_43X39 H=4.5 Compal Electronics, Inc Compal Secret Data 2011/06/24 +1.35V PJ503 G SF000002Z00 Security Classification D 2012/12/14 SUSP @ PQ503 JUMP_43X118 PJ502 2 Date of EOP Title 1.35VP/0.675VSP THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Rev 1.0 V5MM2_SB Date: A Sheet 44 of 57 D D C C +1.05VSP Ipeak=8A ; Imax=5.6A ; OCP=12A ,F= 750K Hz(typ) (ILMT_1.05V floating) @ +1.05VSP 2012/12/14 PJ601 2 +1.05VS_VTT JUMP_43X118 @ PJ602 2 JUMP_43X118 SY8208DQNC_QFN10_3X3 FB = 0.6V B PC615 22U_0805_6.3VAM 2 PR609 Rdown 20K_0402_1% 2 +3VALW PC612 22U_0805_6.3VAM LDO_3V PC611 22U_0805_6.3VAM LDO PR608 @ 0_0402_5% PG Rup (1.1%) +1.05VSP PC610 22U_0805_6.3VAM PR607 10K_0402_5% +1.05V_PGOOD 2 BYP PC614 4.7U_0603_6.3V6K FB ILMT SH00000O400 7*7*3 LX_1.05V Vout=1.062V X76_1@ PL602 1UH_FDSD0630-H-1R0M-P3_11A_20% PC609 22U_0805_6.3VAM PC604 0.1U_0603_25V7K @ ILMT_1.05V3 10 LX PR604 BST_1.05V GND PC608 330P_0402_50V7K 1 BS EN PR606 15.4K_0402_1% IN X76_2@ PL602 1UH +-20% PCMC063T-1R0MN 11A 0_0603_5% 10U_0805_25V6K PC607 Rshort@ +3VS 10U_0805_25V6K PC606 B+_1.05V X76_1@ PC613 4.7U_0603_6.3V6K ILMT_1.05V @ PR605 0_0402_5% PU601 @EMI@ PC605 0.1U_0402_25V6 1 LDO_3V PC601 1U_0402_16V7K @EMI@ PR603 @EMI@ PC602 4.7_1206_5% 680P_0603_50V7K 2SNB_1.05V1 EMI@ PL601 HCB2012KF-121T50_0805 @EMI@ PC603 2200P_0402_50V7K B+ B 1M_0402_1% PR602 @ X76_2@ PU601 SY8206DQNC QFN 10P PWM SUSP# 1 PR601 1K_0402_5% VCCST_PWRGD The current limit is set to 8A, 12A or 16A when this pin is pull low, floating or pull high Pin BYP is for CS Common NB can delete +3VALW and PC15 VFB=0.6V Vout=0.6V* (1+Rup/Rdown) A A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2012/07/10 2013/07/10 Deciphered Date Title +1.05VSP THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Rev 1.0 V5MM2_SB Date: Tuesday, August 27, 2013 Sheet 45 of 57 D D C C +3VS Ipeak=0.5A ; Imax=0.35A ; @ PC707 1U_0402_6.3V6K X76_2@ PU702 G971ADJF11U SO 8P 2012/12/14 Note:Iload(max)=3A PU702 X76_1@ APL5930KAI-TRG_SO8 PR707 22.6K_0402_1% @ PR708 22K_0402_5% @ PC712 0.1U_0402_16V7K @ PC711 22U_0805_6.3V6M +1.5VSP_ON B 2 FB_1.5VSP FB=0.8V PC710 22U_0805_6.3V6M PR705 20K_0402_1% (0.5%) +1.5VSP 0_0402_5% 2 SUSP# Rshort@ PR706 FB Vout=1.508V PC709 0.022U_0402_16V7K EN POK VOUT VOUT VCNTL VIN VIN PC708 4.7U_0603_6.3V6K B GND +1.5VSP @ PJ701 2 Ien=10uA, Vth=0.3V, notice the res and pull high voltage from HW +1.5VS JUMP_43X39 A A Compal Electronics, Inc Compal Secret Data Security Classification 2012/07/10 Issued Date Deciphered Date 2013/07/10 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title +1.5VSP Size Document Number Custom Date: Tuesday, August 27, 2013 Rev 1.0 Sheet 46 of 57 + X76_2@ PL803 0.22UH +-20% MMD-10DZ-R22MEX2L 35A 10*10*4 CPU_PHASE1 VDIO 0_0402_5% VDD PR822 PR817 24.9K_0402_1% PH802 PR818 10K_0402_1%_TSM0A103F34D1RZ 3.01K_0402_1% 2 PC813 0.082U_0402_16V7K Close choke B value:3435K C CSN1 VGATE Rshort@ +3VS Use X7R is better or far away inductor 2 Maximum current: 32A @ PR824 2K_0402_1% PC815 1U_0402_6.3V6K PC816 0.1U_0402_16V7K PR826 75_0402_1% PR827 130_0402_1% @ PR825 54.9_0402_1% +1.05VS_VTT 51622_VREF COMP Close to PWR IC VR_SVID_DATA VR_ALERT# VR_SVID_CLK PR829 3.48K_0402_1% DCR:0.82mΩ±5% PC814 0.082U_0402_16V7K 33 32 31 30 29 28 27 26 25 PR828 10K_0402_1% CSP1-1 CSP1 DROOP @ PC817 100P_0402_50V8J 1 PR801 10K_0402_1% VFB VDD PWM1 +CPU_CORE PGOOD GFB N/C SKIP# 10 11 12 13 O-USR F-IMAX B-RAMP OCP-I 14 THERM IMON 15 16 PC811 1U_0603_10V6K VR_ON 24 N/C PAD VFB TPS51622RSM_QFN32_4X4 PU3 ALERT# 23 PWM2 VCLK GFB PWM1 CSP2 VR_HOT# 0_0402_5% 0_0402_5% CSN2 GND VCC_SENSE Rshort@ PR821 Rshort@ PR823 SKIP# V5A 22 VSS_SENSE VR_ON CSN1 VREF 21 +3VS SLEWA VBAT Rshort@ C CSP1 COMP 17 DROOP CSP1 18 CSN1 PR819 0_0402_5% 19 PR820 0_0402_5% 20 NM00 X76_1@ PL803 0.22UH_PCMB104T-R22MS_35A_20% +5VS PR816 2.21K_0402_1% PU802 CSD97374CQ4M_SON8_3P5X4P5 SKIP# SKIP# VIN BOOT_R VDD PGND1 BOOT VSW PWM PGND2 PC812 PR815 680P_0402_50V7K 4.7_1206_5% @EMI@ @EMI@ 2.2_0603_5% 1CPU_BOOT1 0.1U_0603_25V7K 2CPU_BOOT1-1 PWM1 PR814 PC810 1 F-IMAX O-USR Rshort@ D @ PC809 1000P_0402_50V7K PR813 10K_0402_1% VBAT PU801 2 B-RAMP B+ PC822 33U_25V_M + PC821 33U_25V_M @EMI@ PC808 0.1U_0402_25V6 @EMI@ PC807 2200P_0402_50V7K 2 PC806 10U_0805_25V6K @ OCP-I PR812 39K_0402_1% CPU_B+ PC805 10U_0805_25V6K @ PR811 10K_0402_1% SLEWA EMI@ PL802 HCB2012KF-121T50_0805 2 PR809 PR810 383K_0402_1% 56K_0402_1% 2 EMI@ PL801 HCB2012KF-121T50_0805 CPU_B+ PC804 10U_0805_25V6K THERM PC803 0.1U_0402_25V6 D @ PR808 PR804 150K_0402_1% 8.87K_0402_1% 2 PC802 4700P_0402_25V7K PR803 PR807 39K_0402_1% 255K_0402_1% 2 1 Close MOS B value:4250K PR805 10K_0402_1% PR806 PR802 150K_0402_1% 100K_0402_1% 2 51622_VREF PH801 100K_0402_1%_NCP15WF104F03RC PC818 PR830 PC819 1500P_0402_50V7K 3.83K_0402_1% 0.33U_0402_10V6K 1 2 VR_HOT# V5A B +5VS PR831 22_0603_5% PC820 2.2U_0402_6.3V6M B Consider use 0603 for inrush power VIN 12V-20V MAX current 32A Thermal current 10A Dynamic current 27A Over current level 45A Switching frequency 600KHz Boot voltage 1.7V DC Load- line 2m Ohm A A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2012/07/10 2013/07/10 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC +CPU_CORE Rev 1.0 V5MM2_SB Date: Tuesday, August 27, 2013 Sheet 47 of 57 PWR Rule CPU DCLL=1.5m ohm dedign 330uF/9m *0, 22uF *30 1 2 2 2 2 2 2 1 2 D For BOT side PC916 22U_0805_6.3V6M PC915 22U_0805_6.3V6M PC914 22U_0805_6.3V6M PC913 22U_0805_6.3V6M PC912 22U_0805_6.3V6M PC911 22U_0805_6.3V6M PC910 22U_0805_6.3V6M PC909 22U_0805_6.3V6M PC908 22U_0805_6.3V6M PC907 22U_0805_6.3V6M PC906 22U_0805_6.3V6M PC905 22U_0805_6.3V6M PC904 22U_0805_6.3V6M PC903 22U_0805_6.3V6M D PC902 22U_0805_6.3V6M PC901 22U_0805_6.3V6M +CPU_CORE +CPU_CORE 2 ESD@ PC924 22U_0805_6.3V6M PC923 22U_0805_6.3V6M PC922 22U_0805_6.3V6M PC921 22U_0805_6.3V6M PC920 22U_0805_6.3V6M PC919 22U_0805_6.3V6M 22u *28, @*4 C PC918 22U_0805_6.3V6M PC917 22U_0805_6.3V6M For TOP side C @ PC932 22U_0805_6.3V6M @ PC931 22U_0805_6.3V6M PC930 22U_0805_6.3V6M PC929 22U_0805_6.3V6M PC928 22U_0805_6.3V6M PC927 22U_0805_6.3V6M PC926 22U_0805_6.3V6M PC925 22U_0805_6.3V6M @ B B A A Compal Electronics, Inc Compal Secret Data Security Classification 2012/07/10 Issued Date Deciphered Date 2013/07/10 Title CPU_CORE_CAP THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Rev 1.0 V5MM2_SB Date: Tuesday, August 27, 2013 Sheet 48 of 57 OVP 120 125 130% VGA_EMI@ PL1001 HCB2012KF-121T50_0805 VGA@ PC1004 10U_0805_25V6K 2013/03/11 @VGA_EMI@ PC1003 2200P_0402_50V7K +1.5VSG_B+ @VGA_EMI@ PC1002 0.1U_0402_25V6 +1.5VSDGPU Ipeak=12.5A ;1.2Ipeak=15A ;Imax=8.75A 1/2Delta I=1.08A (F=290K Hz) PR1004=63.4Kohm Rds(on)=5m ohm(max) ; Rds(on)=4.2m ohm(typical) Iocp=Ilimit+1/2Delta I=15.16~21.5A Iocp(min)>1.2Ipeak D D B+ for EMI X76_VGA_2@ PQ1001 AON7518 1N DFN UG_+1.5VSG SW _+1.5VSG TP LG_+1.5VSG 11 TPS51212DSCR_SON10_3X3 PC1006 VGA@ 1U_0603_6.3V6M 2 PR1007 470K_0402_1% VGA@ X76_VGA_2@ PQ1002 AON6508 1N DFN @VGA_EMI@ PR1006 4.7_1206_5% @VGA_EMI@ PC1009 680P_0402_50V7K + ESR=17m ohm for EMI PR1009 VGA@ 9.31K_0402_1% B (0.7%) +1.5VSDGPUP PC1008 VGA@ 330U_2.5V_M DRVL +5VALW TST V5IN SW VFB C Vout=1.36V EN 7*7*4 X76_VGA_1@ PL1002 1.5UH_TMPB0604M-1R5MN-Z01_11A_20% X76_VGA_1@ RF_+1.5VSG DRVH TRIP VBST PQ1002 FB_+1.5VSG PGOOD MDU1512RH_POWERDFN56-8-5 EN_+1.5VSG @VGA@ PC1005 0.1U_0402_16V7K 1.5VS_DGPU_PW R_EN Rshort@ PR1003 0_0402_5% 2 C PR1004 63.4K_0402_1% TRIP_+1.5VSG X76_VGA_2@ PL1002 1.5uH PCME064T-1R5MS VGA@ PU1001 VGA@ X76_VGA_1@ PQ1001 MDV1525URH_PDFN33-8-5 VGA@ PC1001 0.1U_0603_25V7K 10 VGA@ PR1001 2.2_0603_5% BST_+1.5VSG The RC value (PC10 and PR7) need fine-tune if need B PR1011 10K_0402_1% VGA@ +1.5VSDGPUP @ 1 PJ1001 2 +1.5VSDGPU JUMP_43X118 @ PJ1002 2 JUMP_43X118 A A Compal Electronics, Inc Compal Secret Data Security Classification 2012/04/22 Issued Date Deciphered Date Date of EOP THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title +1.5VSDGPUP Size Document Number Custom Date: Tuesday, August 27, 2013 Rev 1.0 Sheet 49 of 57 A B C D VGA_EMI@ PL1202 HCB2012KF-121T50_0805 1 1SNUB1_VGA X76_VGA_2@ PQ1205 AON6554 1N DFN5X6-8 X76_VGA_1@ PQ1205 X76_VGA_1@ PQ1206 X76_VGA_2@ PQ1206 AON6554 1N DFN5X6-8 X76_VGA_1@ PQ1207 2N7002KW_SOT323-3 D VGA_ON# G S X76_VGA_2@ PQ1207 L2N7002WT1G 1N SC-70-3 Compal Secret Data Security Classification 560uF*1 Issued Date 2011/12/05 Deciphered Date Date of EOP Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC B @VGA_EMI@ 22_0805_5% Date: A 2200P_0402_50V7K 2 MDU1511, Rdson(typ)=2.7mohm ,Rdson(max)=3.3mohm VGA@ PR1229 @VGA_EMI@ PR1225 4.7_1206_5% PC1220 680P_0402_50V7K PR1226 10K_0402_5% +3VS N14P-GT 35W Ipeak=45A Imax=31.5A Iocp=80A Fsw=450KHz bulk cap 330uF 9m *3 LGATE2_VGA LGATE2_VGA +VGA_CORE PHASE2_VGA VGA@ PC1205 10U_0805_25V6K 0_0603_5% X76_VGA_1@ PL1204 0.22UH_PCME064T-R22MS0R985_28A_20% 1 UGATE2_2_VGA VGA@ PC1218 0.22U_0603_10V7K BOOT2_2_VGA 1SNUB2_VGA PR1222 VGA_PWROK VCC_VGA UGATE2_VGA B+ X76_VGA_2@ PL1204 22UH 20% PCME064T-R22MS0R985 28A PR1209=20K PR1208=20K PR1210=2K PR1212=18K PR1211=0K PC1208=2.7nF VGA@ PR1220 0_0603_5% 39 30 24 1.8 BOOT2_VGA @VGA_EMI@ PC1203 0.1U_0402_25V6 PQ1204 X76_VGA_1@ MDU1516URH_POWERDFN56-8-5 19 NCP81172MNTXG_QFN24_4X4 VGA_EMI@ PL1201 HCB2012KF-121T50_0805 +VGA_B+_2 20 MDU1511RH_POWERDFN56-8-5 20 20 18 2.7 @VGA_EMI@ PC1202 PQ1203 X76_VGA_2@ PQ1204 AON6552 1N DFN5X6 MDU1511RH_POWERDFN56-8-5 Rshort@ PR1215 0_0402_5% +5VS VGA@ PC1216 10U_0805_25V6K PVCC_VGA 21 R1 R2 R3 R4 R5 C VGA@ 680P_0402_50V7K PC1210 4.7U_0603_10V6K VGA@ Rshort@ Thermistor near MOSFET trigger point 110 degree C PC1207 22 VGA@ PC1219 1U_0402_10V6K C 0.65 1.15 0.9 25 20 0.676 2 X76_VGA_2@ PQ1203 AON6554 1N DFN5X6-8 @VGA_EMI@ PHASE1_VGA BST1 PH2 23 VGA@ PR1224 2.2_0402_5% +5VS 2 B 0.6 1.2 0.9 6.25 96 1.125 SH00000OY00乾乾symblo, 實7x7x4 實實實SH00000O200 DCR=0.97m ohm 24 VGA@ PR1223 10K_0402_5% +3VS 1 Config A Vmin 0.6 Vmax 1.2 Vboot 0.875 Vstep 6.25 Level 96 PWM 1.125 N14P-GT Vmin=0.6V Vmax=1.2V Vboot=0.9V Vstep=6.25mV N=96 FPWM=1.125MHz TDmin=9.26ns +VGA_CORE VGA@ PH1201 100K_0402_1%_NCP15WF104F03RC VGA@ PR1221 3.92K_0402_1% VREF VGA@ PC1217 1U_0402_16V7K X76_VGA_2@ PL1203 22UH 20% PCME064T-R22MS0R985 28A @VGA_EMI@ PR1207 4.7_1206_5% VGA@ PR1217 10_0402_1% VGA@ PC1204 10U_0805_25V6K X76_VGA_2@ PQ1202 AON6554 1N DFN5X6-8 X76_VGA_1@ PQ1202 BST2 COMP LGATE1_VGA B+ X76_VGA_1@ PL1203 0.22UH_PCME064T-R22MS0R985_28A_20%+VGA_CORE 1 EN_VGA EN HG1 LG2 25 VGA@ PC1214 VGA@ PR1219 100P_0402_50V8J 82K_0402_1% PSI FB 18 VID PVCC HG2 12 PGND FBRTN PGOOD 2FB2_VGA1 FS 17 11 LG1 16 FB_VGA VGA@ PC1213 10P_0402_50V8J COMP_VGA VGA@ PC1212 VGA@ PR1216 47P_0402_50V8J 51_0402_1% 2FB1_VGA1 VGA@ PR1218 10K_0402_1% PH1 VREF VCC REFIN TALERT# GND VGA@ PC1211 1000P_0402_50V7K VCCSENSE_VGA 39 39 1.5 30 1.5 1.5 10 VSSSENSE_VGA VIDBUF REFIN PC1208 2700P_0402_50V7K VREF VGA@ PC1209 0.01U_0402_50V7K FS PR1213 33.2K_0402_1% 15 VGA@ PU1201 14 VGA@ TSNS VGA@ VGA@ PR1212 18K_0402_1% PR1211 0_0402_5% PR1227 @VGA@ 100K_0402_1% UGATE1_VGA VGA@ 13 Rshort@ PR1210 2K_0402_1% VGA@ PR1214 10_0402_1% 1 VGA@ PR1209 GPU_VID 20K_0402_1% 1VIDBUF X76_VGA_1@ LGATE1_VGA MDU1511RH_POWERDFN56-8-5 0_0603_5% VGA@ PR1208 20K_0402_1% VREF UGATE1_2_VGA VGA@ PC1206 0.22U_0603_10V7K 1BOOT1_2_VGA 1U_0402_16V7K Rshort@ BOOT1_VGA 1 VGA@ PR1201 VGA@ PC1201 24.9K_0402_1% 0_0402_5% PR1206 Rshort@ PR1202 @VGA@ PC1221 2700P_0402_50V7K 2 Rshort@ PR1204 0_0402_5% VGA@ PR1205 10K_0402_5% +3VS X76_VGA_1@ PQ1201 MDU1511RH_POWERDFN56-8-5 VGA_ON PSI DGPU_VID PR1203 VGA@ 0_0603_5% VGA@ PC1215 10U_0805_25V6K +VGA_B+_1 MDU1516URH_POWERDFN56-8-5 X76_VGA_2@ PQ1201 AON6552 1N DFN5X6 C Compal Electronics, Inc VGA_COREP Document Number Rev 1.0 Tuesday, August 27, 2013 D Sheet 50 of 57 VGA@ PC1317 4.7U_0603_6.3V6K VGA@ PC1316 4.7U_0603_6.3V6K VGA@ PC1315 4.7U_0603_6.3V6K VGA@ PC1314 4.7U_0603_6.3V6K VGA@ PC1311 4.7U_0603_6.3V6K VGA@ PC1321 0.1U_0402_10V7K VGA@ PC1313 4.7U_0603_6.3V6K VGA@ PC1310 4.7U_0603_6.3V6K VGA@ PC1320 0.1U_0402_10V7K VGA@ PC1312 4.7U_0603_6.3V6K VGA@ PC1309 4.7U_0603_6.3V6K VGA@ PC1319 0.1U_0402_10V7K 1 2 VGA@ PC1308 4.7U_0603_6.3V6K D Under VGA Core VGA@ PC1318 0.1U_0402_10V7K +VGA_CORE GB4-128 Under 4.7uF_0603_10pcs 0.1uF_0402_4pcs Near 47uF_0805_1pcs 22uF_0805_1pcs 4.7uF_0805_5pcs D C C +VGA_CORE + + + B VGA@ PC1328 4.7U_0805_6.3V6K VGA@ PC1327 4.7U_0805_6.3V6K 1 VGA@ PC1305 330U_2.5V_M VGA@ PC1323 22U_0805_6.3V6M VGA@ PC1326 4.7U_0805_6.3V6K 1 VGA@ PC1325 4.7U_0805_6.3V6K 1 2 VGA@ PC1324 4.7U_0805_6.3V6K B VGA@ PC1322 47U_0805_6.3V6M + VGA@ PC1304 330U_2.5V_M VGA@ PC1301 330U_2.5V_M Near VGA Core VGA@ PC1307 560U_D2_2VM_R4.5M +VGA_CORE A A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2011/06/24 Deciphered Date Date of EOP Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC VGA_CORE CAP Size Document Number Custom Date: Tuesday, August 27, 2013 Rev 1.0 Sheet 51 of 57 Version change list (P.I.R List) Item D Fixed Issue Page of for PWR Reason for change Acoustic noise Silergy update revision Rev PG# Modify List 3V 5V light load efficiency improvement 3V/5V 3V 5V enable control for Rev0.3 But un-pop 3V/5V 2.remove (PR207) Change to R-short PR1204 VGA/CPU (PR1211 modify charger current to meet battery charge time Charger 0.02_1206_1%_SD00000S110 charger to BI_GATE remove HW VGA_sequence test When pwm IC shutdown on S0, EC could detect SLP_S5#, but cannot detect PCH was no power The 5VALW will fast than 3VALW and the rising time will under 2mS 10 VRAM efficiency improvement The discharge time may cause GC6 entry/exit quickly fail, worry about the off time too long problem cause the GC6 fail 11 A D PR1206 PR1215 0.01_1206_1%_SD00000K820 PR822 ) 01/15 EVT (PR310) 1.PR803 270K_0402_1%_SD00000G280 change to255K_0402_1%_SD034255380 2.PR809 392K_0402_1%_SD034392380 change to383K_0402_1%_SD034383380 3.PR831 10_0603_5%_SD013100A80 change to22_0603_5%_SD000001R80 4.PC820 1U_0603_10V6K_SE080105K80 change to2.2U_0402_6.3V6M_SE000008880 CPU PQ401 2N7002KW_SOT323-3_SB000009Q80 remove 3V/5V 1.PC1201un-pop charger to 0.1U_0402_16V7K_SE076104K80 2.PR1201un-pop charger to 24.9K_0402_1%_SD034249280 3.PR12280_0402_5% charger to un-pop VGA add 3V/5V PR416 3V/5V PC426 4700P_0402_25V7K_SE075472K80 change to 0.01U_0402_25V7K_SE075103K80 PC425 0.047U_0402_25V7K_SE00000MJ00 change to 6800P_0402_25V7K_SE075682K80 01/15 EVT C 01/16 EVT 01/21 EVT 100K_0402_5%_SD028100380 3/11 3/11 1.PQ1002 AON7702A_SB00000T600 change to MDU1512RH_POWERDFN56-8-5_SB00000SY00 2.PQ1001 AON7408L 1N DFN_SB00000H800 change to MDV1525URH 1N PDFN33-8_SB00000S600 PL1002 2.2uH_7*7*3_SH00000MR00 charger to 1.5uH_7*7*4_SH00000PM00 1.5VDGPU PR1229 add un-pop 22_0805_5%_SD002220A80 PQ1207 add un-pop 2N7002KW_SOT323-3_SB000009Q80 VGA 01/15 EVT 01/15 EVT Reduce part count The modify values for CPU transition test Phase 01/15 EVT 1.Add un-pop 2pcs 0402 resistors(PR415 PR414) C B Date 1.Add 2pcs 1K_0402_5% (PR412 PR413) 1pcs 4700P_0402_25V7K (PC425) 1pcs 0.047U_0402_25V7K (PC426) 2.Add 4.7u_0402_6.3V6M (PC401) DVT DVT 3/11 DVT 3/11 DVT B A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2011/06/24 2012/07/12 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: PIR (PWR) Rev 1.0 Tuesday, August 27, 2013 Sheet 52 of 57 Version change list (P.I.R List) Item D Fixed Issue Page of for PWR Reason for change Rev remove VGA enable for +3VSDGPU VRAM voltage change to 1.35V ESD request VCIN1 function Material change Modify List VGA_COREP The discharge time may cause GC6 entry/exit quickly fail, worry about the off time too long problem cause the GC6 fail Reduce part count Reduce part count follow ON solution for VGA 10 PR1228_0_0402_5% 3/11 +1.5VSDGPUP PR1009 11.5K_0402_1%_SD034115280 PR1004 137K_0402_1%_SD034137380 Add PC924 22U_0805_6.3V6M_SE000000I10 3/11 CPU_CORE PH801 SL200000U00 change to SL200000V00 PL602 SH00000PJ00 change to SH00000O400 Add PR1229 Add PQ1207 VGA 22_0805_5%_SD002220A80 2N7002KW_SOT323-3_SB000009Q80 C 4/16 PVT-1 5/14 PVT-1 1.35V/1.5VSP /1.5VSDGPU SD028000080 Change to 0402_R-short (PR510 PR706 PR1003) 5/14 PVT-1 3V/5V/ 1.05V/VGA SD013000080 Change to 0603 R-short (PR405 PR408 PR604 PR1202 PR1222) 5/14 PVT-1 VGA PC1221_SE074272K00_2700P charger to un-pop PC1208_SE071101J80_100P charger to SE074272K00_2700P PVT-1 PVT-1 B 1.35V PR506_8.2K_0402_1%_SD000004100 12 Material EOL 1.35V PQ502 AON7702A SB00000T600 change to AON7506 SB000010A00 14 16 PVT-2 PR411 316K_0402_1%_SD034316380 change to 953K_0402_1%_SD00000X100 PR403 402K_0402_1%_SD034402380 change to 160K_0402_1%_SD034160380 PR225 9.76K_0402_1%_SD034976180 change to 10K_0402_1%_SD034100280(65W@) change to 10.5K_0402_1%_SD034105280 (90W@) PR207 71.5K_0402_1%_SD034715280 change to 127K_0402_1%_SD034127380(65W@) change to 91K_0402_1%_SD034910280 (90W@) PVT-2 PVT-2 Fixed system can't power on (HW suggest delay the 3V power on sequency.) 3V/5V PC426 0.01U_25V_K_X7R_0402_SE075103K80 change to 0.022U_16V_K_X7R_0402_SE076223K80 PVT-3 ACER must not GC6 function VGA 1.PR1229 2.PQ1207 1.PR1229 2.PQ1207 VGA 22_0805_5%_SD002220A80 =>un-pop 2N7002KW_SOT323-3_SB000009Q80 =>un-pop un-pop =>22_0805_5%_SD002220A80 un-pop =>2N7002KW_SOT323-3_SB000009Q80 Issued Date 8/7 8/7 2012/07/10 PVT-3 Compal Electronics, Inc 2013/07/10 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A PVT-3 8/12 Compal Secret Data Security Classification PVT-2 PR506_8.06K_SD034806180 charger to 8.2K_0402_1%_SD000004100 Cancel ->ACER must not GC6 function 17 BATTERY CONN /OTP charger to 8.06K_SD034806180 1.35V Adjust the FB voltage for 1.35V 15 DVT PR225 5.1K_0402_1%_SD034510180 change to 9.76K_0402_1%_SD034976180_90W@ 1.02K_0402_1%_SD034102180 change to 9.76K_0402_1%_SD034976180_65W@ BATTERY CONN/OTP PR207 UN-pop-0K_0402_1%_SD034100280 change to 47.5K_0402_1%_SD034475280_90W@ UN-pop-0K_0402_1%_SD034100280 change to 71.5K_0402_1%_SD034715280_65W@ PR318 499K_0402_0.1%_SD00000U380 DVT CHARGER 3/11 change to 499K_0402_1%_SD034499380 Adjust the FB voltage for 1.35V 13 DVT change to 9.31K_0402_1%_SD034931180 DVT change to 63.4K_0402_1%_SD03463K280 11 VCIN1 Recovery 85% chang to 100% Phase D 3V/5V A Date remove 1.05V B PG# CPU capacitor C PIR (PWR) Rev 1.0 Tuesday, August 27, 2013 Sheet 53 of 57 A Item Page# B Date 28 28 28 2013/1/8 2013/1/8 2013/1/8 28 28 28 28 31,34 31,33 2013/1/8 2013/1/8 2013/1/8 2013/1/8 2013/1/8 2013/1/8 10 31 2013/1/8 EC Board ID for Rev0.2 11 2013/1/8 Change SPI ROM from 4M+2M to 8M 12 26 2013/1/8 1.abnormal display via re-driver board to solve the problem without any gauge increased 13 14 15 16 28 38 26,32 D Issue Description Add DP++ Schematic Add DP++ config Change mDP HPD Schematic from Before-IC to After-IC for LB_RST no use LB HPD issue for not support LB wake function for not support LB wake function Remove LAN/B from Acer request Remove LAN/B from Acer request C Solution Description Add Q101,Q102,Q46,R336 Add DM@ , NDM@ 2013/1/9 2013/1/9 2013/1/9 2013/1/9 2013/1/9 2013/1/9 2013/1/9 2013/1/9 2013/1/14 some risk for OPs on factory side Pull-high 10K to +3VS for SMB_ALERT#_R Update KB backlight schematic Battery can`t detect issue (BI_GATE) GC6 schematic update Change SPI serial resistor value For BI signal screw hole Change SPI ROM from dual to single LAN_CLKREQ# already pull-up on CPU side 26 2013/1/15 For Cost/Part count 27 28 2013/1/15 For Cost/Part count 28 29 33 34 2013/1/15 2013/1/15 For Cost/Part count For Cost/Part count 30 34 2013/1/15 Update BI_GATE schematic 31 32 33 34 35 39 27 30 31 2013/1/15 2013/1/15 2013/1/15 2013/1/15 2013/1/15 For For For For For Cost/Part Cost/Part Cost/Part Cost/Part Cost/Part count count count count count , reserve R499,R502 DVT DVT DVT pop R1327 for LB_RST no use Change R1344 from 100K to 10K Add R503 and unpop it Add J24 Remove JLAN1 , Add JPWR1 (same as JBL1) LAN_CLKREQ# pull-high to +3VS (R131, remove) Remove C530,R312,R1170 reserve R234,R236,R237 for differential pair route space DVT DVT DVT DVT DVT Change R1191 to 8.2K pop R1190,R1191 DVT 後後 DVT Remove U14,RP20,R109,R402,C67,C453 Connect JEDP1_pin27 to +3VS, this solution is only for cable which need to pass via re-driver board Add R522,C140 , unpop R421,R424 Change Q43 to 2N7002K incorrect gpio define For LightningBolt debug , will unpop in PVT Change TPM IC P/N For EMI request , change EMI part P/N 30 34 34 34 33 37 7 Stage 2013/1/8 2013/1/8 2013/1/8 2013/1/8 17 18 19 20 21 22 23 24 25 E DVT DVT 後後 unpop R214 ,pop R205 pop SW7( remove) Change U89 from SA00005XH00 to SA00005XH40 Change L26 to SM01000EJ00 Change L17,L18,L20,L21,L22 to SM070001R00 Change JMINI1 and JMINI2 to JWLAN1 and JMSATA1 Add R452 Remove Q56,R928 Add R530 , unpop Q30 connect VGA_PWROK to EC_pin120 Change RP19,R108 from 22ohm to 15ohm Add H19 Remove U14,RP20,R109,R402,C67,C453 ( ) Remove R313( R52 pull-up) Remove R66 unpop R67,U30 Change R403 from 0ohm to 2ohm DVT DVT DVT DVT DVT DVT DVT DVT DVT DVT DVT DVT DVT 多多 已已 DVT Remove SW7,C1443 unpop D64,D65,D66 DVT Remove R1160 Remove R930,SW1 Remove D43,Q34,R489,R530,C888,C890 Q30 change from P-MOS to N-MOS R486,R487 change to 100K ohm DVT DVT Change Change Change Change Change DVT DVT DVT DVT Date of EOP Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC PIR-HW V5MM2 M/B LA-A021P Schematic Date: A B C Compal Electronics, Inc Compal Secret Data 2011/06/24 Issued Date DVT R987 to 2ohm R111 to R-short 0402 R368,R369,R409,R410,R417,R418,R415,R419 to R-short 0402 R876,R877 to R-short 0402 R49 to R-short 0805 Security Classification D Sheet E 54 of 57 Rev 1.0 A Item Page# B Date 33 34 35 37 39 26 34 11 39 32 29 2013/1/15 2013/1/15 2013/1/15 2013/1/15 2013/1/15 2013/1/16 2013/1/16 2013/1/17 2013/1/17 2013/1/17 2013/1/21 2013/1/21 2013/1/21 For Cost/Part count For Cost/Part count For Cost/Part count For Cost/Part count For Cost/Part count For ESD request Update BI_GATE schematic For ESD request For ESD request For ESD request Change main source on DVT only Change main source on DVT only Change main source for AP-code 47 8,39 2013/1/21 Update GC6 schematic 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 29 34 40-53 34 26 26 26 20 39 33 36 34 32 26 33 2013/1/21 2013/1/21 2013/1/22 2013/1/22 2013/1/22 2013/1/23 2013/2/7 2013/2/7 2013/2/19 2013/2/19 2013/2/19 2013/2/19 2013/2/19 2013/2/19 2013/2/19 Update LB schematic unpop debug switch update Power schematic 0121A For X1 code For SMT eDP HPD issue eDP HPD issue VGA schematic mistake Change EN pin for +1.5VSDGPU off-current Add SPOK to turn on/off +3,5VALW Audio SPK sound not balance issue BI_GATE issue Add RF frame ESD issue Board ID for Rev 0.3 PCB 63 29 2013/2/19 Change LBT 5V switch schematic 統統統 26,33 D Issue Description 36 37 38 39 40 41 42 43 44 43 44 45 46 64 C 2013/2/19 No need support wake by Home-Key 65 2013/2/19 Add GPIO pin for TPM/no-TPM sku 66 30 2013/2/27 AOAC on/AOAC off co-lay 67 20 2013/2/27 VGA part count and unpop reduce 68 22 2013/2/27 VGA part count and unpop reduce 69 23 2013/2/27 VGA part count and unpop reduce 70 24 2013/2/27 VGA part count and unpop reduce 71 25 2013/2/27 VGA part count and unpop reduce 72 26 2013/2/27 For Cost/Part count E Solution Description Stage DVT DVT DVT DVT DVT DVT DVT DVT DVT DVT DVT DVT DVT Change R1162 to R-short 0805 Change R929 to R-short 0402 Change R495,R496,R497 to R-short 0603 Change R508,R510 to R-short 0603 Change R988 to R-short 0402 Add C803 Change R486 to 510K , BI_GATE power change to +RTCVCC Add C932,C936,C937 Add C920,C925 Add C940 Y1 change to SJ100004Z00 U76,U78 change to SA00003TV00 Q95,Q96 change to SB966750010 Pop R404,R405 unpop R406,R407 R469 change from 330k to 47k R1347 change from 100k to 100 ohm unpop SW4 DVT DVT DVT DVT DVT DVT DVT PVT PVT PVT PVT PVT PVT PVT PVT PVT Change U82 from SA00001TC00 to SA000057Z00 Change L26 back to SM010014520 Pop R421,R424 ; unpop R522 , C140 Remove Q43 Change R1245 from 42.2ohm to 40.2ohm Q64 change to Dual-N and gate pin change to 1.5VS_DGPU_PWR_EN , add R984,R998 Add EC pin_16 named SPOK Change R575 from 1k ohm to 1.2k ohm Change H9 symbol Add CLIP1 C803 change from 0.1u to 22p R1191 change from 8.2k to 18k Add U38(USB power switch),C526 Remove Q95,Q96,Q97,U156,R1337,R1338,R1343,R1339.R1340 Change R1347 from 100_0402 to 470_0603 for discharge Change R1341 from 100k to 10k (follow CR) Change power to home key from +3VALW to +3VS (JSNSR1.pin12) Change Pull-up domain from +3VALW to +3VS (R1181,R1182,R1183) Add R312,R313 and unpop R312 Add J21 from +3VS unpop U79,C941 Remove C1316,C1317 Remove C1341,C1342,C1327 unpop C1345,C1346,C1348,C1350,C1329,C1331,C1334,C1336 Remove C1366,C1367,C1355 unpop C1369,C1371,C1372,C1374,C1357,C1358,C1362,C1363 Remove C1392,C1393,C1378 unpop C1394,C1397,C1399,C1401,C1380,C1382,C1385,C1387 Remove C1417,C1418,C1404 unpop C1421,C1422,C1423,C1426,C1405,C1407,C1413,C1415 R424 change to R-short 0402 Remove R522,C140 2011/06/24 Issued Date Date of EOP Deciphered Date PVT PVT PVT Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC PIR-HW V5MM2 M/B LA-A021P Schematic Date: A B C Compal Electronics, Inc Compal Secret Data Security Classification D Sheet E 55 of 57 Rev 1.0 A Item Page# B Date C Issue Description 73 74 75 76 77 78 79 80 81 82 83 84 85 86 37 32 31 11,15,33 30 29 11 26 32 33 38 20 35 36 2013/3/4 2013/3/5 2013/3/5 2013/3/5 2013/3/5 2013/3/5 2013/3/6 2013/3/6 2013/3/6 2013/3/6 2013/3/6 2013/3/6 2013/3/6 2013/3/6 ME screw change USB charger schematic update Remove JHDD2 For ESD request For ESD request For ESD request For Cost/Part count For Cost/Part count For Cost/Part count For Cost/Part count For Cost/Part count For Cost/Part count For Cost/Part count For Cost/Part count 87 17 2013/3/6 Update GC6 schematic 88 35,36 2013/3/6 Audio PoPo issue 89 9,34 2013/3/6 Add I2C for touchpad 28 19 ALL 38 28 34 ALL 7,10,31 34 6,11 35,36 6,10 28 2013/3/8 2013/3/8 2013/3/11 2013/3/13 2013/4/1 2013/4/1 2013/4/1 2013/5/9 2013/5/9 2013/5/9 2013/5/9 2013/5/9 2013/5/9 2013/5/10 Update LBT schematic (TI request) Change VRAM power from 1.5V to 1.35V Combine power schematic 0311A Change TPM power from +3VALW to +3VS Add F1 for LBT fuse Update H9 symbol Update All RC*NEW footprint Remove LAN Reserve one/two Lid-switch funtion For Cost/Part count For Cost/Part count For Cost/Part count For Cost/Part count Add net for 2nd hall sensor Lid-out 104 7,9 2013/5/10 Change Card-Reader CLK from Port5 to Port1 105 106 107 108 109 110 33 16 15,16 22,23 24,25 2013/5/16 2013/5/16 2013/5/22 2013/5/22 2013/5/22 2013/5/22 Add Pull-up for LID_SW#_TAB reserve Pull-up for EC_LID_OUT#_TAB pop C141 Change 1uF to 2.2uF Change 1uF to 2.2uF Change 1uF to 2.2uF 2013/5/22 Co-lay LBT schematic 2013/5/22 2013/5/22 For Cost/Part count For Cost/Part count 112 113 28 12,15 15,16 Stage H4 change from 3P0 to 4P5 , H3 from 2P5 to 3P0 R853 pull-up power rail change from +3VALW to +3VALW_EC Remove JHDD2 pop C6,C117,C1255 (Page11,Page15,Page33) Add C62,C63,C64 Add C65 Change R167,R168 to R-short 0402 Change R355,R359,R366,R367,R413,R414,R335 to R-short 0402 Change R852,R855,R865,R866 to R-short 0402 Change R80 to R-short 0402 Change R978,R980 to R-short 0402 Change R1241 to R-short 0603 Change R518,R520,R527,R529 to R-short 0603 Change R519,R521,R524,R525,R556,R566,R567 to R-short 0603 Add D3,Q95 Remove Q84,,Q90,R1204 Change R1201 from 10k to 1k Reserve R1205 Add U31,R1313 and un-pop Add R408 Amp PD pin change from EC_MUSE# to AMP_MUTE# Add R84,R85 and unpop Add R82,R83,R1337,R1338 Swap Q101A pin3 and pin4 Change R1229 from 24.9k to 34.8k Combine power schematic 0311A pop J17 , unpop J16 Add F1 Update H9 footprint 90 91 92 93 94 95 96 97 98 99 100 101 102 103 111 E Solution Description D PVT PVT2 Remove C168,C169,R234,R,236,R237 Add U83,U84,R930.R931,C989,C990,C991,C992 Change R76,R180 to R-short 0402 Change R408,R512,R513 to R-short 0402 Change R75,R155 to R-short 0603 Change R373,R381 to R-short 0402 Change PCH_GPIO14 for EC LID_OUT_TAB (LID_OUT need place between GPIO1 to GPIO15) modify net name : GPIO19 -> CARD_CLKREQ# CARD_CLKREQ# -> GPIO23 Add R1163 Add R249 and reserve it Pop C141 Change C108,C123,C130,C143 to 2.2uF Change C1328,C1343,C1356,C1368 to 2.2uF Change C1379,C1395,C1409,C1419 to 2.2uF Remove D1 Add U66 and co-lay with F1 Remove R210,C50,C34,C126 Remove C107,C109,C121,C122,C129,C131,C144,C146 2011/06/24 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification Date of EOP Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC PIR-HW V5MM2 M/B LA-A021P Schematic Date: A B C D Sheet E 56 of 57 Rev 1.0 A Item Page# 114 115 116 117 118 119 22 23 24 25 30,31 33 B Date 2013/5/22 2013/5/22 2013/5/22 2013/5/22 2013/5/22 2013/5/22 C D Issue Description For For For For For For Cost/Part Cost/Part Cost/Part Cost/Part Cost/Part Cost/Part E Solution Description count count count count count count 120 28,29 2013/5/23 Change LBT power rail to +3VS/+5VS 121 122 123 124 125 126 127 128 129 130 131 22 23 24 25 33 28 24 34 ALL 17 2013/5/24 2013/5/24 2013/5/24 2013/5/24 2013/5/28 2013/5/29 2013/5/30 2013/5/30 2013/5/31 2013/6/4 2013/6/4 Pop VGA cap Pop VGA cap Pop VGA cap Pop VGA cap Change Board ID Add cap for Lightning Bolt 3V power Add cap for VGA_1.5V (debug) Change LID_OUT GPIO from GPIO14 to GPIO8 Update Part Number for PVT-2 SMT Combine Power schematic 0603 Update Part Number for PVT-2 SMT 132 30 2013/7/2 Update WLAN schmatic 133 134 135 136 137 138 139 140 141 ALL ALL 34 34 30 33 ALL ALL 2013/7/3 2013/7/5 2013/7/29 2013/7/31 2013/7/31 2013/8/1 2013/8/4 2013/8/14 2013/8/27 For layout spacing Combine Power schematic 0627 Combine Power schematic 0729 Remove Buzzer schematic Update BI GATE schematic (2nd BI_GATE) Update mSATA schematic for DEVSLP function Change Board ID Combine Power schematic 0812A Combine Power schematic 0814 Stage Remove C1346,C1350,C1331,C1336 Remove C1371,C1374,C1358,C1363 Remove C1397,C1401,C1382,C1387 Remove C1422,C1426,C1407,C1415 Remove C946,C961,R869,R870,C870,C872 Remove C1269,C1257 U38 change from +5VALW to +5VS Remove J23 (+3VALW JUMP) Pop C1345,C1348,C1329,C1334 Pop C1369,C1372,C1357,C1362 Pop C1394,C1399,C1380,C1385 Pop C1421,C1423,C1405,C1413 Change R1191 from 18K to 33K Add C262 (47uF) Add C1401 (0.1uF) Change GPIO8,GPIO14 net name Change U82,U83,U84 to SA00003GI00 Combine Power schematic 0603 Change D62 to SCS00000Z00 Change C958 from 4.7uF to 10uF Add C961 Remove R74 Combine Power schematic 0627 Combine Power schematic 0729 Remove BUR1,Q53,R492,R493 Add R86 and unpop it Change R877 from R-short to unpop Change R1191 from 33K to 56K Combine Power schematic 0812A Combine Power schematic 0814 PVT2 PVT3 Pre-MP 3 4 2011/06/24 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification Date of EOP Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC PIR-HW V5MM2 M/B LA-A021P Schematic Date: A B C D Sheet E 57 of 57 Rev 1.0 ... 10 1 10 3 10 5 10 7 10 9 11 1 11 3 11 5 11 7 11 9 12 1 12 3 12 5 12 7 12 9 13 1 13 3 13 5 13 7 13 9 14 1 14 3 14 5 14 7 14 9 15 1 15 3 15 5 15 7 15 9 16 1 16 3 16 5 16 7 16 9 17 1 17 3 17 5 17 7 17 9 18 1 18 3 18 5 18 7 18 9 19 1 19 3 19 5 19 7... 00 01 15K 10 10 0 01 0 20K 10 11 0 011 24.9K 11 00 01 0 0 30. 1K 11 01 01 0 1 34.8K 11 10 01 1 0 45.3K 11 11 01 1 1 STRAP0 USER[3 :0] STRAP1 3GIO_PADCFG_LUT_ADR[3 :0] STRAP2 PCI_DEVID[3 :0] STRAP3 SOR[3 :0] STRAP4... H_PROCHOT# @PC 104 @ PC 104 10 00P _06 03_50V7K EMI@ PC 103 10 0P _06 03_50V8 1 EMI@ PC 102 10 0P _06 03_50V8 2 @PC1 01 @ PC1 01 100 0P _06 03_50V7K +3VALW 1 DC_IN_S1 2 GND GND D VIN @ PJP1 01 ACES_ 503 05 -00 4 41- 0 01_ 4P C