Acer aspire 4741z 4741ZG 5741 5741g 5741z 5741ZG COMPAL LA 5891p REV 1 0

A B C D E 1 Compal Confidential 2 NEW50/70/80/90 M/B Schematics Document Intel Arrandale Processor with DDRIII + Ibex Peak-M ATI Madision/Park 2010-01-07 3 REV:1.0 4 2009/08/01 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2010/08/01 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Cover Page NEW70 M/B LA-5891P Schematic Date: A B C D Friday, January 08, 2010 Sheet E of 59 Rev 1.0 A B C D E Clock Generator Compal Confidential IDT: 9LVS3199AKLFT Realtek: RTM890N-631-VB-GRT Model Name : NEW50/70/80/90 File Name : LA5891P 133/120/100/96/14.318MHZ to PCH Fan Control page 38 page 12 1 PEG(DIS) 100MHz PCI-E 2.0x16 5GT/s PER LANE Memory BUS(DDRIII) 204pin DDRIII-SO-DIMM X2 Dual Channel Intel 133MHz Madision/Park page 10,11 1.5V DDRIII 800/1066 Processor rPGA988A LVDS(DIS) page 4,5,6,7,8,9 HDMI(DIS) CRT(DIS) FDI x8 (UMA) HDMI Conn CRT Conn page 31 BANK 0, 1, 2, Arrandale (UMA/DIS) page 22,23,24,25,26,27,28 LVDS Conn page 30 page 29 HDMI(UMA) USB conn x3 USB port 100MHz 100MHz 2.7GT/s 1GB/s x4 LVDS(UMA) CRT(UMA) TMDS(UMA) HDMI Level Shift DMI x4 Intel Ibex Peak-M USB port 0, on USB/B page 36 Bluetooth Conn CMOS Camera Card Reader RTS5160 USB port 11 USB port USB port page 36 USBx14 3.3V 48MHz HD Audio 3.3V 24MHz page 29 page 36 page 31 port MINI Card x2 WLAN, WWAN USB port 12,13 page 35 port SATA x (GEN1 1.5GT/S ,GEN2 3GT/S) SATA HDD Conn page 32 TI TPS6017 page 41 page 13 SATA CDROM Conn page 32 LPC BUS 33MHz Int Speaker ENE KB926 Phone Jack x page 41 page 41 page 37 USB/B 2Port USB Port0,2 page 36 Touch Pad Int.KBD page 38 LS-5892P page 34 Audio AMP port Sub-board LS-5891P Power On/Off CKT page 40 SPI ROM x1 page 33 page 34 page 15 ALC272X SPI BCM57780 RJ45 RTC CKT HDA Codec page 13,14,15,16 17,18,19,20,21 100MHz LAN(GbE) port PCH 100MHz PCI-Express x (ARD PCIE2.0 2.5GT/s) page 38 CPU XDP Card Reader USB Port9 page 36 page BIOS ROM DC/DC Interface CKT page 38 Power Circuit DC/DC page 40~48 LS-5893P page 38 LS-5894P Power/B PCH XDP LID_SW/B page 38 page 21 LS-5895P 3G USB Port10,13page 35 2009/08/01 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2010/08/01 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C D Block Diagrams Document Number NEW70 M/B LA-5891P Schematic Tuesday, December 29, 2009 Sheet E of 59 Rev 1.0 A B C D SIGNAL STATE Full ON Power Plane S1 S3 S5 Adapter power supply (19V) Description N/A N/A N/A BATT+ Battery power supply (12.6V) N/A N/A N/A B+ AC or battery power rail for power circuit N/A N/A N/A +CPU_CORE Core voltage for CPU ON OFF OFF HIGH HIGH ON ON ON ON HIGH HIGH ON ON ON LOW S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF ON OFF OFF ON OFF OFF +0.75VS +0.75VP to +0.75VS switched power rail for DDR terminator ON OFF OFF +1.0VSDGPU +1.0VSPDGPU to +1.0VSDGPU switched power rail for GPU ON OFF OFF +1.05VS_VTT +1.05VS_VTTP to +1.05VS_VTT switched power rail for ARD CPU ON OFF OFF Vcc Ra/Rc/Re +1.05VS_PCH +1.05VS_VTT to +1.05VS_PCH power for PCH ON OFF OFF Board ID +1.5V +1.5VP to +1.5V power rail for DDRIII ON ON OFF ON OFF OFF ON OFF OFF +1.8VS (+5VALW or +3VALW) to 1.8V switched power rail to PCH & GPU ON OFF OFF +3VALW +3VALW always on power rail ON ON ON* +3VALW_EC +3VALW always to KBC ON ON ON* +3V_LAN +3VALW to +3V_LAN power rail for LAN ON ON ON* +3V +3VALW to +3V power rail for PCH (Short Jumper) ON ON ON* +3VS +3VALW to +3VS power rail ON OFF OFF +5VALW +5VALWP to +5VALW power rail ON ON ON* +5V +5VALW to +5V switched power rail for PCH (Short resister) ON ON ON* +5VS +5VALW to +5VS switched power rail ON OFF OFF +VSB +VSBP to +VSB always on power rail for sequence control ON ON ON* +RTCVCC RTC power ON ON ON Device Address Smart Battery 0001 011X b 3.3V +/- 5% 100K +/- 5% Rb / Rd / Rf 8.2K +/- 5% 18K +/- 5% 33K +/- 5% 56K +/- 5% 100K +/- 5% 200K +/- 5% NC V AD_BID V 0.216 V 0.436 V 0.712 V 1.036 V 1.453 V 1.935 V 2.500 V V AD_BID typ V 0.250 V 0.503 V 0.819 V 1.185 V 1.650 V 2.200 V 3.300 V BOARD ID Table Board ID Address BTO Option Table BTO Item UMA UMA Only Discrete Discrete Only GPU ALL Components VRAM Switchable Connector 3G Blue Tooth Unpop UMA HDMI Discrete HDMI UMA & DIS POP HDMI GPU Madision GPU Park NEW70,80 LED NEW50,90 LED PCB Revision 0.1 0.2 0.3 1.0 USB Port Table PCH SM Bus address USB 2.0 USB 1.1 Port Device Address Clock Generator (9LVS3199AKLFT, RTM890N-631-VB-GRT) 1101 0010b DDR DIMM0 1001 000Xb DDR DIMM2 1001 010Xb Option UMAHD@ VGAHD@ UMA V X VGA X SG NO HDMI HDMI@ 3G & BT Config 3G SKU: 3G@ BT SKU: BT@ @ SG@ V X X V V X X X V V X V X X X X X LED BOM config NEW70,80 SKU: 7080@ NEW50,90 SKU: 5090@ UHCI0 UHCI1 EHCI1 GPU BOM Config Madision SKU: MADI@ Park SKU: PARK@ VRAM BOM Config X761@: X76198BOL01 Park Samsung 512MB X762@: X76198BOL02 Park Hynix 512MB X763@: X76198BOL03 Madision Samsung 1024MB X764@: X76198BOL04 Madision Hynix 1024MB X765@: X76198BOL05 Park AMD 512MB X766@: X76198BOL06 Madision AMD 1024MB UHCI2 UHCI3 UHCI4 EHCI2 UHCI5 UHCI6 10 11 12 13 External USB Port USB/B (Right Side) USB Port (Left Side) USB/B (Right Side) A BOM Structure UMA@ UMAO@ DIS@ DISO@ VGA@ X76@ SG@ CONN@ 3G@ BT@ @ UMAHD@ VGAHD@ HDMI@ MADI@ PARK@ 7080@ 5090@ X76@ ID3 , ID1 : VRAM Vender Location ID2: VRAM Size Location VRAM_ID3 VRAM_ID1 Samsung R492 R474 HYNIX R491 R474 AMD R491 R473 VRAM Camera Card Reader SIM Card Blue Tooth Mini Card(WLAN) Mini Card(GPS) VRAM VRAM_ID2 8PCS 64Mx16 4PCS 64Mx16 R482 R483 VRAM P/N : Samsung : SA000035700 (S IC D3 64MX16 K4W1G1646E-HC12 FBGA 96P) Hynix : SA000032400 (S IC D3 64MX16 H5TQ1G63BFR-12C FBGA 1.5V ) AMD: SA00003PF20 (S IC D3 23EY2387MB-12) BOM Config UMA W/O HDMI SKU: UMA W/ HDMI SKU: Discrete W/O HDMI SKU: Discrete W/ HDMI SKU: Switchable W/O HDMI SKU: Switchable W HDMI SKU: V AD_BID max V 0.289 V 0.538 V 0.875 V 1.264 V 1.759 V 2.341 V 3.300 V EC SM Bus2 address Device Board ID / SKU ID Table for AD channel Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF EC SM Bus1 address Clock HIGH Core voltage for Arrandale GPU (only for arrandaleCPU) +1.5V to +1.5VS switched power rail +VS HIGH Core voltage for GPU +1.5VS to +1.5VSDGPU switched power rail for GPU +V LOW +VGA_CORE +1.5VSDGPU +VALW HIGH +VGFX_CORE +1.5VS SLP_S1# SLP_S3# SLP_S4# SLP_S5# S1(Power On Suspend) Voltage Rails VIN E BT@/3G@/UMA@/UMAO@ BT@/3G@/UMA@/UMAO@/HDMI@/UMAHD@ BT@/3G@/DIS@/DISO@/VGA@/HDMI@/VGAHD@ BT@/3G@/DIS@/UMA@/VGA@/SG@ BT@/3G@/DIS@/UMA@/VGA@/SG@/HDMI@/VGAHD@ B 2009/08/01 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification BT@/3G@/DIS@/DISO@/VGA@ Deciphered Date 2010/08/01 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: C D Notes List Document Number NEW70 M/B LA-5891P Schematic Tuesday, December 29, 2009 Sheet E of 59 Rev 1.0 JCPU1E DMI_RX#[0] DMI_RX#[1] DMI_RX#[2] DMI_RX#[3] DMI_PTX_HRX_P0 DMI_PTX_HRX_P1 DMI_PTX_HRX_P2 DMI_PTX_HRX_P3 B24 D23 B23 A22 DMI_RX[0] DMI_RX[1] DMI_RX[2] DMI_RX[3] DMI_HTX_PRX_N0 DMI_HTX_PRX_N1 DMI_HTX_PRX_N2 DMI_HTX_PRX_N3 D24 G24 F23 H23 DMI_TX#[0] DMI_TX#[1] DMI_TX#[2] DMI_TX#[3] DMI_HTX_PRX_P0 DMI_HTX_PRX_P1 DMI_HTX_PRX_P2 DMI_HTX_PRX_P3 D25 F24 E23 G23 DMI_TX[0] DMI_TX[1] DMI_TX[2] DMI_TX[3] E22 D21 D19 D18 G21 E19 F21 G18 FDI_TX#[0] FDI_TX#[1] FDI_TX#[2] FDI_TX#[3] FDI_TX#[4] FDI_TX#[5] FDI_TX#[6] FDI_TX#[7] H_FDI_TXP0 H_FDI_TXP1 H_FDI_TXP2 H_FDI_TXP3 H_FDI_TXP4 H_FDI_TXP5 H_FDI_TXP6 H_FDI_TXP7 D22 C21 D20 C18 G22 E20 F20 G19 FDI_TX[0] FDI_TX[1] FDI_TX[2] FDI_TX[3] FDI_TX[4] FDI_TX[5] FDI_TX[6] FDI_TX[7] F17 E17 FDI_FSYNC[0] FDI_FSYNC[1] H_FDI_INT C17 FDI_INT 15 H_FDI_LSYNC0 15 H_FDI_LSYNC1 F18 D17 FDI_LSYNC[0] FDI_LSYNC[1] C 15 H_FDI_FSYNC0 15 H_FDI_FSYNC1 15 Intel(R) FDI H_FDI_TXN0 H_FDI_TXN1 H_FDI_TXN2 H_FDI_TXN3 H_FDI_TXN4 H_FDI_TXN5 H_FDI_TXN6 H_FDI_TXN7 15mil B PCI EXPRESS GRAPHICS A24 C23 B22 A21 DMI D 10mil PEG_IRCOMP R485 49.9_0402_1% EXP_RBIAS R493 750_0402_1% PEG_ICOMPI PEG_ICOMPO PEG_RCOMPO PEG_RBIAS B26 A26 B27 A25 PEG_RX#[0] PEG_RX#[1] PEG_RX#[2] PEG_RX#[3] PEG_RX#[4] PEG_RX#[5] PEG_RX#[6] PEG_RX#[7] PEG_RX#[8] PEG_RX#[9] PEG_RX#[10] PEG_RX#[11] PEG_RX#[12] PEG_RX#[13] PEG_RX#[14] PEG_RX#[15] K35 J34 J33 G35 G32 F34 F31 D35 E33 C33 D32 B32 C31 B28 B30 A31 PEG_GTX_C_HRX_N15 PEG_GTX_C_HRX_N14 PEG_GTX_C_HRX_N13 PEG_GTX_C_HRX_N12 PEG_GTX_C_HRX_N11 PEG_GTX_C_HRX_N10 PEG_GTX_C_HRX_N9 PEG_GTX_C_HRX_N8 PEG_GTX_C_HRX_N7 PEG_GTX_C_HRX_N6 PEG_GTX_C_HRX_N5 PEG_GTX_C_HRX_N4 PEG_GTX_C_HRX_N3 PEG_GTX_C_HRX_N2 PEG_GTX_C_HRX_N1 PEG_GTX_C_HRX_N0 C69 C72 C76 C84 C87 C96 C105 C106 C121 C123 C129 C141 C149 C160 C161 C167 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K PEG_GTX_HRX_N15 PEG_GTX_HRX_N14 PEG_GTX_HRX_N13 PEG_GTX_HRX_N12 PEG_GTX_HRX_N11 PEG_GTX_HRX_N10 PEG_GTX_HRX_N9 PEG_GTX_HRX_N8 PEG_GTX_HRX_N7 PEG_GTX_HRX_N6 PEG_GTX_HRX_N5 PEG_GTX_HRX_N4 PEG_GTX_HRX_N3 PEG_GTX_HRX_N2 PEG_GTX_HRX_N1 PEG_GTX_HRX_N0 PEG_RX[0] PEG_RX[1] PEG_RX[2] PEG_RX[3] PEG_RX[4] PEG_RX[5] PEG_RX[6] PEG_RX[7] PEG_RX[8] PEG_RX[9] PEG_RX[10] PEG_RX[11] PEG_RX[12] PEG_RX[13] PEG_RX[14] PEG_RX[15] J35 H34 H33 F35 G33 E34 F32 D34 F33 B33 D31 A32 C30 A28 B29 A30 PEG_GTX_C_HRX_P15 PEG_GTX_C_HRX_P14 PEG_GTX_C_HRX_P13 PEG_GTX_C_HRX_P12 PEG_GTX_C_HRX_P11 PEG_GTX_C_HRX_P10 PEG_GTX_C_HRX_P9 PEG_GTX_C_HRX_P8 PEG_GTX_C_HRX_P7 PEG_GTX_C_HRX_P6 PEG_GTX_C_HRX_P5 PEG_GTX_C_HRX_P4 PEG_GTX_C_HRX_P3 PEG_GTX_C_HRX_P2 PEG_GTX_C_HRX_P1 PEG_GTX_C_HRX_P0 C71 C75 C81 C86 C95 C98 C99 C113 C115 C128 C140 C142 C151 C153 C165 C174 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K PEG_GTX_HRX_P15 PEG_GTX_HRX_P14 PEG_GTX_HRX_P13 PEG_GTX_HRX_P12 PEG_GTX_HRX_P11 PEG_GTX_HRX_P10 PEG_GTX_HRX_P9 PEG_GTX_HRX_P8 PEG_GTX_HRX_P7 PEG_GTX_HRX_P6 PEG_GTX_HRX_P5 PEG_GTX_HRX_P4 PEG_GTX_HRX_P3 PEG_GTX_HRX_P2 PEG_GTX_HRX_P1 PEG_GTX_HRX_P0 PEG_TX#[0] PEG_TX#[1] PEG_TX#[2] PEG_TX#[3] PEG_TX#[4] PEG_TX#[5] PEG_TX#[6] PEG_TX#[7] PEG_TX#[8] PEG_TX#[9] PEG_TX#[10] PEG_TX#[11] PEG_TX#[12] PEG_TX#[13] PEG_TX#[14] PEG_TX#[15] L33 M35 M33 M30 L31 K32 M29 J31 K29 H30 H29 F29 E28 D29 D27 C26 PEG_HTX_GRX_N15 PEG_HTX_GRX_N14 PEG_HTX_GRX_N13 PEG_HTX_GRX_N12 PEG_HTX_GRX_N11 PEG_HTX_GRX_N10 PEG_HTX_GRX_N9 PEG_HTX_GRX_N8 PEG_HTX_GRX_N7 PEG_HTX_GRX_N6 PEG_HTX_GRX_N5 PEG_HTX_GRX_N4 PEG_HTX_GRX_N3 PEG_HTX_GRX_N2 PEG_HTX_GRX_N1 PEG_HTX_GRX_N0 C586 C561 C584 C559 C582 C557 C580 C555 C578 C553 C576 C551 C574 C549 C572 C547 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K PEG_HTX_C_GRX_N15 PEG_HTX_C_GRX_N14 PEG_HTX_C_GRX_N13 PEG_HTX_C_GRX_N12 PEG_HTX_C_GRX_N11 PEG_HTX_C_GRX_N10 PEG_HTX_C_GRX_N9 PEG_HTX_C_GRX_N8 PEG_HTX_C_GRX_N7 PEG_HTX_C_GRX_N6 PEG_HTX_C_GRX_N5 PEG_HTX_C_GRX_N4 PEG_HTX_C_GRX_N3 PEG_HTX_C_GRX_N2 PEG_HTX_C_GRX_N1 PEG_HTX_C_GRX_N0 PEG_TX[0] PEG_TX[1] PEG_TX[2] PEG_TX[3] PEG_TX[4] PEG_TX[5] PEG_TX[6] PEG_TX[7] PEG_TX[8] PEG_TX[9] PEG_TX[10] PEG_TX[11] PEG_TX[12] PEG_TX[13] PEG_TX[14] PEG_TX[15] L34 M34 M32 L30 M31 K31 M28 H31 K28 G30 G29 F28 E27 D28 C27 C25 PEG_HTX_GRX_P15 PEG_HTX_GRX_P14 PEG_HTX_GRX_P13 PEG_HTX_GRX_P12 PEG_HTX_GRX_P11 PEG_HTX_GRX_P10 PEG_HTX_GRX_P9 PEG_HTX_GRX_P8 PEG_HTX_GRX_P7 PEG_HTX_GRX_P6 PEG_HTX_GRX_P5 PEG_HTX_GRX_P4 PEG_HTX_GRX_P3 PEG_HTX_GRX_P2 PEG_HTX_GRX_P1 PEG_HTX_GRX_P0 C585 C560 C583 C558 C581 C556 C579 C554 C577 C552 C575 C550 C573 C548 C571 C546 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K PEG_HTX_C_GRX_P15 PEG_HTX_C_GRX_P14 PEG_HTX_C_GRX_P13 PEG_HTX_C_GRX_P12 PEG_HTX_C_GRX_P11 PEG_HTX_C_GRX_P10 PEG_HTX_C_GRX_P9 PEG_HTX_C_GRX_P8 PEG_HTX_C_GRX_P7 PEG_HTX_C_GRX_P6 PEG_HTX_C_GRX_P5 PEG_HTX_C_GRX_P4 PEG_HTX_C_GRX_P3 PEG_HTX_C_GRX_P2 PEG_HTX_C_GRX_P1 PEG_HTX_C_GRX_P0 AP25 AL25 AL24 AL22 AJ33 AG9 M27 L28 J17 H17 G25 G17 E31 E30 R58 3.01K_0402_1% @ R61 3.01K_0402_1% R60 3.01K_0402_1% DIS@ @ R59 3.01K_0402_1% @ CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17 CFG18 2 2 WW41 Recommend not pull down PCIE2.0 Jitter is over on ES1 R497 0_0402_5% @ @ H_RSVD17_R H_RSVD18_R R501 0_0402_5% DMI_PTX_HRX_N[0 3] 15 DMI_PTX_HRX_P[0 3] 15 15 15 PEG_GTX_HRX_N[0 15] 22 PEG_GTX_HRX_P[0 15] 22 PEG_HTX_C_GRX_N[0 15] 22 PEG_HTX_C_GRX_P[0 15] 22 CFG[0] CFG[1] CFG[2] CFG[3] CFG[4] CFG[5] CFG[6] CFG[7] CFG[8] CFG[9] CFG[10] CFG[11] CFG[12] CFG[13] CFG[14] CFG[15] CFG[16] CFG[17] RSVD_TP_86 B19 A19 RSVD15 RSVD16 A20 B20 RSVD17 RSVD18 U9 T9 RSVD19 RSVD20 AC9 AB9 RSVD21 RSVD22 C1 A3 DMI_HTX_PRX_N[0 3] 15 DMI_HTX_PRX_P[0 3] 15 H_FDI_TXN[0 7] H_FDI_TXP[0 7] AM30 AM28 AP31 AL32 AL30 AM31 AN29 AM32 AK32 AK31 AK28 AJ28 AN30 AN32 AJ32 AJ29 AJ30 AK30 H16 RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 RSVD6 RSVD7 RSVD8 SA_DIMM_VREF SB_DIMM_VREF RSVD11 RSVD12 RSVD13 RSVD14 RSVD32 RSVD33 AJ13 AJ12 RSVD34 RSVD35 AH25 AK26 RSVD36 RSVD_NCTF_37 AL26 AR2 RSVD38 RSVD39 AJ26 AJ27 (CFD Only) (CFD Only) RESERVED JCPU1A DMI_PTX_HRX_N0 DMI_PTX_HRX_N1 DMI_PTX_HRX_N2 DMI_PTX_HRX_N3 RSVD_NCTF_40 RSVD_NCTF_41 AP1 AT2 RSVD_NCTF_42 RSVD_NCTF_43 AT3 AR1 RSVD45 RSVD46 RSVD47 RSVD48 RSVD49 RSVD50 RSVD51 RSVD52 RSVD53 RSVD_NCTF_54 RSVD_NCTF_55 RSVD_NCTF_56 RSVD_NCTF_57 RSVD58 AL28 AL29 AP30 AP32 AL27 AT31 AT32 AP33 AR33 AT33 AT34 AP35 AR35 AR32 RSVD_TP_59 RSVD_TP_60 KEY RSVD62 RSVD63 RSVD64 RSVD65 E15 F15 A2 D15 C15 AJ15 AH15 RSVD_TP_66 RSVD_TP_67 RSVD_TP_68 RSVD_TP_69 RSVD_TP_70 RSVD_TP_71 RSVD_TP_72 RSVD_TP_73 RSVD_TP_74 RSVD_TP_75 AA5 AA4 R8 AD3 AD2 AA2 AA1 R9 AG7 AE3 RSVD_TP_76 RSVD_TP_77 RSVD_TP_78 RSVD_TP_79 RSVD_TP_80 RSVD_TP_81 RSVD_TP_82 RSVD_TP_83 RSVD_TP_84 RSVD_TP_85 V4 V5 N2 AD5 AD7 W3 W2 N3 AE5 AD9 RSVD_NCTF_23 RSVD_NCTF_24 J29 J28 RSVD26 RSVD27 A34 A33 RSVD_NCTF_28 RSVD_NCTF_29 C35 B35 RSVD_NCTF_30 RSVD_NCTF_31 IC,AUB_CFD_rPGA,R1P0 CONN@ VSS D C R146 0_0402_5% RSVD64_R @ RSVD65_R @ R147 0_0402_5% 1 B AP34 IC,AUB_CFD_rPGA,R1P0 CONN@ A eDP Signals Mapping eDP Singal PEG Singals eDP_TX0 PEG_HTX_C_GRX_P15 eDP_TX#0 PEG_HTX_C_GRX_N15 eDP_TX1 PEG_HTX_C_GRX_P14 eDP_TX#1 PEG_HTX_C_GRX_N14 eDP_TX2 PEG_HTX_C_GRX_P13 eDP_TX#2 PEG_HTX_C_GRX_N13 eDP_TX3 PEG_HTX_C_GRX_P12 eDP_TX#3 PEG_HTX_C_GRX_N12 eDP_AUX PEG_GTX_C_HRX_P13 eDP_AUX# PEG_GTX_C_HRX_N13 eDP_HPD# PEG_GTX_C_HRX_P12 Lane Reversal PEG_HTX_C_GRX_P0 PEG_HTX_C_GRX_N0 PEG_HTX_C_GRX_P1 PEG_HTX_C_GRX_N1 PEG_HTX_C_GRX_P2 PEG_HTX_C_GRX_N2 PEG_HTX_C_GRX_P3 PEG_HTX_C_GRX_N3 PEG_GTX_C_HRX_P2 PEG_GTX_C_HRX_N2 PEG_GTX_C_HRX_P3 H_FDI_FSYNC0 H_FDI_FSYNC1 R519 DISO@ 1K_0402_5% R517 DISO@ 1K_0402_5% H_FDI_INT R513 DISO@ 1K_0402_5% H_FDI_LSYNC0 H_FDI_LSYNC1 R520 DISO@ 1K_0402_5% R515 DISO@ 1K_0402_5% CheckList0.8 1.22 Auburndale Graphics Disable CFG0 - PCI-Express Configuration Select CFG4 - Display Port Presence *1:Single PEG 0:Bifurcation enabled *1:Disabled; No Physical Display Port attached to Embedded Display Port 0:Enabled; An external Display Port device is connected to the Embedded Display Port CFG3 - PCI-Express Static Lane Reversal *:Default *1 :Normal Operation :Lane Numbers Reversed 15 -> 0, 14 -> 1, Compal Electronics, Inc Compal Secret Data Security Classification 2009/08/01 Issued Date Deciphered Date 2010/08/01 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A Title PROCESSOR (1/6) DMI,FDI,PEG Size B Date: Document Number NEW70 M/B LA-5891P Schematic Tuesday, December 29, 2009 Sheet of 59 Rev 1.0 JCPU1B H_COMP2 AT24 COMP2 R521 49.9_0402_1% H_COMP1 G16 COMP1 R503 49.9_0402_1% H_COMP0 AT26 COMP0 SKTOCC#_R AH24 SKTOCC# T7 PAD @ D 18 R547 0_0402_5% H_PECI H_PECI_R AT15 H_PROCHOT# 54 H_PROCHOT# R124 0_0402_5% 18 H_THERMTRIP# PROCHOT# THERMTRIP# H_CPURST# AP26 RESET_OBS# H_PM_SYNC_R AL15 PM_SYNC R122 0_0402_5% H_CPUPW RGD_1 AN14 VCCPWRGOOD_1 H_VTTPW RGD @ R540 R126 1.5K_0402_1% H_CPUPW RGD_0 H_PW RGD_XDP R489 0_0402_5% AN27 PM_DRAM_PW RGD_R H_VTTPW RGD_R 0_0402_5% 2 VCCPWRGOOD_0 AK13 SM_DRAMPWROK AM15 VTTPWRGOOD H_PW RGD_XDP_R AM26 TAPPWRGOOD PLT_RST#_R AL14 RSTIN# A16 B16 BCLK_ITP BCLK_ITP# AR30 AT30 PEG_CLK PEG_CLK# E16 D16 DPLL_REF_SSCLK DPLL_REF_SSCLK# A18 A17 SM_DRAMRST# 2009/2/4 #414044 DG Update Rev1.11 CLK_CPU_XDP CLK_CPU_XDP# 2009/08/14 remove DP REF SSCLK CLK_CPU_DMI 14 CLK_CPU_DMI# 14 CLK_CPU_DP_R CLK_CPU_DP#_R CLK_CPU_DP_R CLK_CPU_DP#_R PM_EXT_TS#[0] PM_EXT_TS#[1] AN15 AP15 PM_EXTTS#0 PM_EXTTS#1_R PRDY# PREQ# AT28 AP27 XDP_PRDY# XDP_PREQ# TCK TMS TRST# AN28 AP28 AT27 XDP_TCLK XDP_TMS XDP_TRST# TDI TDO TDI_M TDO_M AT29 AR27 AR29 AP29 XDP_TDI_R XDP_TDO_R XDP_TDI_M XDP_TDO_M DBR# AN25 XDP_DBR#_R BPM#[0] BPM#[1] BPM#[2] BPM#[3] BPM#[4] BPM#[5] BPM#[6] BPM#[7] AJ22 AK22 AK24 AJ24 AJ25 AH22 AK23 AH23 0_0402_5% 0_0402_5% R567 100K_0402_5% R539 R538 R548 +1.05VS_VTT 2009/08/14 #425302 CP_S3PowerReduction WhitePaper_Rev1.0 SM_DRAMRST# 10 SM_RCOMP_0 SM_RCOMP_1 SM_RCOMP_2 R504 R510 D F6 +1.05VS_VTT 10K_0402_5% 10K_0402_5% 0_0402_5% SM_RCOMP_0 R578 SM_RCOMP_1 R576 SM_RCOMP_2 R573 XDP_PRDY# XDP_TMS XDP_TDI_R XDP_PREQ# XDP_TCLK R89 R496 R495 R90 R62 XDP_TRST# R499 XDP_TDI_R XDP_TDO_M R488 R475 @ @ @ @ @ 1 1 51_0402_5% 51_0402_5% 51_0402_5% 51_0402_5% 51_0402_5% 2 2 PM_EXTTS#0_1 10,11 51_0402_5% 100_0402_1% 24.9_0402_1% 130_0402_1% R87 0_0402_5% 0_0402_5% @ XDP_TDI XDP_TDO R480 0_0402_5% 0_0402_5% XDP_DBRESET# XDP_DBRESET# 15,21 XDP_TDI_M XDP_TDO_R XDP_OBS0 XDP_OBS1 XDP_OBS2 XDP_OBS3 XDP_OBS4 XDP_OBS5 XDP_OBS6 XDP_OBS7 C @ R481 R476 2 0_0402_5% 0_0402_5% JTAG MAPPING 2009/09/16 update 2009/2/4 Delete dampling resistor for power noise and Layout space issue IC,AUB_CFD_rPGA,R1P0 CONN@ Scan Chain (Default) STUFF -> R488 , R480 , R476 NO STUFF -> R475 , R481 CPU Only STUFF -> R488 ,R475 NO STUFF -> R480 , R481 , R476 GMCH Only STUFF -> R481,R476 NO STUFF -> R488, R475 , R480 R125 750_0402_1% CLK_CPU_BCLK 18 CLK_CPU_BCLK# 18 AL1 AM1 AN1 SM_RCOMP[0] SM_RCOMP[1] SM_RCOMP[2] 17,21,33,37 PLT_RST# AK15 PECI R123 0_0402_5% R150 0_0402_5% 15 PM_DRAM_PW RGD H_THERMTRIP#_R R121 0_0402_5% 18 H_CPUPW RGD AN26 CATERR# PWR MANAGEMENT 15 H_PM_SYNC C AK14 THERMAL H_CATERR# BCLK BCLK# 1 20_0402_1% COMP3 R507 CLOCKS AT23 DDR3 MISC H_COMP3 JTAG & BPM 20_0402_1% MISC R512 +1.05VS_VTT R127 R88 R91 2 @ 49.9_0402_1% 68_0402_5% 68_0402_5% H_CATERR# H_PROCHOT# H_CPURST# JP2 B 2009/8/14 change back to 2K B A P U38 H_VTTPW RGD +3VALW MC74VHC1G08DFT2G_SC70-5 H_VTTPW RGD_R XDP_OBS2 XDP_OBS3 G Y XDP_OBS0 XDP_OBS1 R550 2K_0402_1% R542 52 H_VTTPW RGD XDP_PREQ# XDP_PRDY# 1K_0402_1% XDP_OBS4 XDP_OBS5 #425302 CP_S3PowerReduction WhitePaper_Rev0.7 P A Y R152 @ 1.1K_0402_1% 1 U11 B G Need to check Voltage Level +1.5V_1 R151 H_VTTPW RGD MC74VHC1G08DFT2G_SC70-5 R197 1K_0402_5% H_CPUPW RGD H_PW RGOOD_R R84 PBTN_OUT#_XDP 15,21,37 PBTN_OUT# 0_0402_5% +1.05VS_VTT H_PW RGD_XDP C211 @ 21 SMB_DATA_S3 0.1U_0402_16V4Z 21 SMB_CLK_S3 XDP_TCLK 1.5K_0402_1% A XDP_OBS6 XDP_OBS7 +3VALW XDP Connector GND0 OBSFN_A0 OBSFN_A1 GND2 OBSDATA_A0 OBSDATA_A1 GND4 OBSDATA_A2 OBSDATA_A3 GND6 OBSFN_B0 OBSFN_B1 GND8 OBSDATA_B0 OBSDATA_B1 GND10 OBSDATA_B2 OBSDATA_B3 GND12 PWRGOOD/HOOK0 HOOK1 VCC_OBS_AB HOOK2 HOOK3 GND14 SDA SCL TCK1 TCK0 GND16 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 GND1 OBSFN_C0 OBSFN_C1 GND3 OBSDATA_C0 OBSDATA_C1 GND5 OBSDATA_C2 OBSDATA_C3 GND7 OBSFN_D0 OBSFN_D1 GND9 OBSDATA_D0 OBSDATA_D1 GND11 OBSDATA_D2 OBSDATA_D3 GND13 ITPCLK/HOOK4 ITPCLK#/HOOK5 VCC_OBS_CD RESET#/HOOK6 DBR#/HOOK7 GND15 TD0 TRST# TDI TMS GND17 B H_RESET#_R R83 1K_0402_5% @ H_CPURST# PLT_RST# R85 0_0402_5% CLK_CPU_XDP CLK_CPU_XDP# H_RESET#_R XDP_DBRESET# XDP_TDO XDP_TRST# XDP_TDI XDP_TMS +1.05VS_VTT R81 1K_0402_5% R79 51_0402_5% 1 +3VS +1.05VS_VTT A SAMTE_BSH-030-01-L-D-A CONN@ 1 PM_DRAM_PW RGD_R 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 R149 2009/04/23 Intel CRB 1.55 Update Change R68 to 1.1K_1%, R71 to 3.01K_1% Compal Electronics, Inc Compal Secret Data Security Classification 750_0402_1% R148 @ 3.01K_0402_1% 2009/08/01 Issued Date Deciphered Date 2010/08/01 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title PROCESSOR (2/6) CLK,JTAG Size B Date: Document Number NEW70 M/B LA-5891P Schematic Tuesday, December 29, 2009 Sheet of 59 Rev 1.0 B 10 10 10 DDR_A_BS0 DDR_A_BS1 DDR_A_BS2 10 DDR_A_CAS# 10 DDR_A_RAS# 10 DDR_A_W E# A10 C10 C7 A7 B10 D10 E10 A8 D8 F10 E6 F7 E9 B7 E7 C6 H10 G8 K7 J8 G7 G10 J7 J10 L7 M6 M8 L9 L6 K8 N8 P9 AH5 AF5 AK6 AK7 AF6 AG5 AJ7 AJ6 AJ10 AJ9 AL10 AK12 AK8 AL7 AK11 AL8 AN8 AM10 AR11 AL11 AM9 AN9 AT11 AP12 AM12 AN12 AM13 AT14 AT12 AL13 AR14 AP14 DDR_A_BS0 DDR_A_BS1 DDR_A_BS2 AC3 AB2 U7 DDR_A_CAS# DDR_A_RAS# DDR_A_W E# AE1 AB3 AE9 SA_CK[0] SA_CK#[0] SA_CKE[0] SA_DQ[0] SA_DQ[1] SA_DQ[2] SA_DQ[3] SA_DQ[4] SA_DQ[5] SA_DQ[6] SA_DQ[7] SA_DQ[8] SA_DQ[9] SA_DQ[10] SA_DQ[11] SA_DQ[12] SA_DQ[13] SA_DQ[14] SA_DQ[15] SA_DQ[16] SA_DQ[17] SA_DQ[18] SA_DQ[19] SA_DQ[20] SA_DQ[21] SA_DQ[22] SA_DQ[23] SA_DQ[24] SA_DQ[25] SA_DQ[26] SA_DQ[27] SA_DQ[28] SA_DQ[29] SA_DQ[30] SA_DQ[31] SA_DQ[32] SA_DQ[33] SA_DQ[34] SA_DQ[35] SA_DQ[36] SA_DQ[37] SA_DQ[38] SA_DQ[39] SA_DQ[40] SA_DQ[41] SA_DQ[42] SA_DQ[43] SA_DQ[44] SA_DQ[45] SA_DQ[46] SA_DQ[47] SA_DQ[48] SA_DQ[49] SA_DQ[50] SA_DQ[51] SA_DQ[52] SA_DQ[53] SA_DQ[54] SA_DQ[55] SA_DQ[56] SA_DQ[57] SA_DQ[58] SA_DQ[59] SA_DQ[60] SA_DQ[61] SA_DQ[62] SA_DQ[63] SA_BS[0] SA_BS[1] SA_BS[2] SA_CAS# SA_RAS# SA_WE# AA6 AA7 P7 Y6 Y5 P6 DDR_A_CLK1 10 DDR_A_CLK1# 10 DDR_A_CKE1 10 SA_CS#[0] SA_CS#[1] AE2 AE8 DDR_A_CS0# 10 DDR_A_CS1# 10 SA_ODT[0] SA_ODT[1] AD8 AF9 DDR_A_ODT0 10 DDR_A_ODT1 10 B9 D7 H7 M7 AG6 AM7 AN10 AN13 DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63 DDR_A_CLK0 10 DDR_A_CLK0# 10 DDR_A_CKE0 10 SA_CK[1] SA_CK#[1] SA_CKE[1] SA_DM[0] SA_DM[1] SA_DM[2] SA_DM[3] SA_DM[4] SA_DM[5] SA_DM[6] SA_DM[7] DDR SYSTEM MEMORY A C DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63 DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7 SA_DQS#[0] SA_DQS#[1] SA_DQS#[2] SA_DQS#[3] SA_DQS#[4] SA_DQS#[5] SA_DQS#[6] SA_DQS#[7] C9 F8 J9 N9 AH7 AK9 AP11 AT13 DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7 SA_DQS[0] SA_DQS[1] SA_DQS[2] SA_DQS[3] SA_DQS[4] SA_DQS[5] SA_DQS[6] SA_DQS[7] C8 F9 H9 M9 AH8 AK10 AN11 AR13 DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7 SA_MA[0] SA_MA[1] SA_MA[2] SA_MA[3] SA_MA[4] SA_MA[5] SA_MA[6] SA_MA[7] SA_MA[8] SA_MA[9] SA_MA[10] SA_MA[11] SA_MA[12] SA_MA[13] SA_MA[14] SA_MA[15] Y3 W1 AA8 AA3 V1 AA9 V8 T1 Y9 U6 AD4 T2 U3 AG8 T3 V9 DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15 11 11 11 DDR_B_BS0 DDR_B_BS1 DDR_B_BS2 11 DDR_B_CAS# 11 DDR_B_RAS# 11 DDR_B_W E# JCPU1D 11 DDR_B_D[0 63] 11 DDR_B_DM[0 7] 11 DDR_B_DQS#[0 7] 11 DDR_B_DQS[0 7] 11 DDR_B_MA[0 15] JCPU1C 10 DDR_A_D[0 63] 10 DDR_A_DM[0 7] 10 DDR_A_DQS#[0 7] 10 DDR_A_DQS[0 7] 10 DDR_A_MA[0 15] D B5 A5 C3 B3 E4 A6 A4 C4 D1 D2 F2 F1 C2 F5 F3 G4 H6 G2 J6 J3 G1 G5 J2 J1 J5 K2 L3 M1 K5 K4 M4 N5 AF3 AG1 AJ3 AK1 AG4 AG3 AJ4 AH4 AK3 AK4 AM6 AN2 AK5 AK2 AM4 AM3 AP3 AN5 AT4 AN6 AN4 AN3 AT5 AT6 AN7 AP6 AP8 AT9 AT7 AP9 AR10 AT10 SB_DQ[0] SB_DQ[1] SB_DQ[2] SB_DQ[3] SB_DQ[4] SB_DQ[5] SB_DQ[6] SB_DQ[7] SB_DQ[8] SB_DQ[9] SB_DQ[10] SB_DQ[11] SB_DQ[12] SB_DQ[13] SB_DQ[14] SB_DQ[15] SB_DQ[16] SB_DQ[17] SB_DQ[18] SB_DQ[19] SB_DQ[20] SB_DQ[21] SB_DQ[22] SB_DQ[23] SB_DQ[24] SB_DQ[25] SB_DQ[26] SB_DQ[27] SB_DQ[28] SB_DQ[29] SB_DQ[30] SB_DQ[31] SB_DQ[32] SB_DQ[33] SB_DQ[34] SB_DQ[35] SB_DQ[36] SB_DQ[37] SB_DQ[38] SB_DQ[39] SB_DQ[40] SB_DQ[41] SB_DQ[42] SB_DQ[43] SB_DQ[44] SB_DQ[45] SB_DQ[46] SB_DQ[47] SB_DQ[48] SB_DQ[49] SB_DQ[50] SB_DQ[51] SB_DQ[52] SB_DQ[53] SB_DQ[54] SB_DQ[55] SB_DQ[56] SB_DQ[57] SB_DQ[58] SB_DQ[59] SB_DQ[60] SB_DQ[61] SB_DQ[62] SB_DQ[63] DDR_B_BS0 DDR_B_BS1 DDR_B_BS2 AB1 W5 R7 SB_BS[0] SB_BS[1] SB_BS[2] DDR_B_CAS# DDR_B_RAS# DDR_B_W E# AC5 Y7 AC6 SB_CAS# SB_RAS# SB_WE# DDR SYSTEM MEMORY - B SB_CK[0] SB_CK#[0] SB_CKE[0] W8 W9 M3 DDR_B_CLK0 11 DDR_B_CLK0# 11 DDR_B_CKE0 11 SB_CK[1] SB_CK#[1] SB_CKE[1] V7 V6 M2 DDR_B_CLK1 11 DDR_B_CLK1# 11 DDR_B_CKE1 11 SB_CS#[0] SB_CS#[1] AB8 AD6 DDR_B_CS0# 11 DDR_B_CS1# 11 SB_ODT[0] SB_ODT[1] AC7 AD1 DDR_B_ODT0 11 DDR_B_ODT1 11 SB_DM[0] SB_DM[1] SB_DM[2] SB_DM[3] SB_DM[4] SB_DM[5] SB_DM[6] SB_DM[7] D4 E1 H3 K1 AH1 AL2 AR4 AT8 DDR_B_DM0 DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7 SB_DQS#[0] SB_DQS#[1] SB_DQS#[2] SB_DQS#[3] SB_DQS#[4] SB_DQS#[5] SB_DQS#[6] SB_DQS#[7] D5 F4 J4 L4 AH2 AL4 AR5 AR8 DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7 SB_DQS[0] SB_DQS[1] SB_DQS[2] SB_DQS[3] SB_DQS[4] SB_DQS[5] SB_DQS[6] SB_DQS[7] C5 E3 H4 M5 AG2 AL5 AP5 AR7 DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7 SB_MA[0] SB_MA[1] SB_MA[2] SB_MA[3] SB_MA[4] SB_MA[5] SB_MA[6] SB_MA[7] SB_MA[8] SB_MA[9] SB_MA[10] SB_MA[11] SB_MA[12] SB_MA[13] SB_MA[14] SB_MA[15] U5 V2 T5 V3 R1 T8 R2 R6 R4 R5 AB5 P3 R3 AF7 P5 N1 DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15 D C B IC,AUB_CFD_rPGA,R1P0 CONN@ IC,AUB_CFD_rPGA,R1P0 CONN@ A Compal Electronics, Inc Compal Secret Data Security Classification 2009/08/01 Issued Date Deciphered Date 2010/08/01 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A Title PROCESSOR (3/6) DDRIII Size B Date: Document Number NEW70 M/B LA-5891P Schematic Tuesday, December 29, 2009 Sheet of 59 Rev 1.0 JCPU1F WW15 MOW +CPU_CORE Peak 21A A VTT0_1 VTT0_2 VTT0_3 VTT0_4 VTT0_5 VTT0_6 VTT0_7 VTT0_8 VTT0_9 VTT0_10 VTT0_11 VTT0_12 VTT0_13 VTT0_14 VTT0_15 VTT0_16 VTT0_17 VTT0_18 VTT0_19 VTT0_20 VTT0_21 VTT0_22 VTT0_23 VTT0_24 VTT0_25 VTT0_26 VTT0_27 VTT0_28 VTT0_29 VTT0_30 VTT0_31 VTT0_32 VTT0_33 VTT0_34 VTT0_35 VTT0_36 VTT0_37 VTT0_38 VTT0_39 VTT0_40 VTT0_41 VTT0_42 VTT0_43 VTT0_44 10U_0805_6.3V6M +CPU_CORE C258 1 C274 C286 C282 10U_0805_6.3V6M C288 C284 10U_0805_6.3V6M 10U_0805_6.3V6M C281 10U_0805_6.3V6M 10U_0805_6.3V6M C676 10U_0805_6.3V6M C677 10U_0805_6.3V6M C669 C674 10U_0805_6.3V6M 10U_0805_6.3V6M C657 C652 10U_0805_6.3V6M 10U_0805_6.3V6M C679 C262 10U_0805_6.3V6M C232 10U_0805_6.3V6M (Place these capacitors between inductor and socket on Bottom) +CPU_CORE + 10U_0805_6.3V6M C268 + C667 1 C242 10U_0805_6.3V6M C223 C257 10U_0805_6.3V6M C261 C269 C275 C155 2 330U_X_2VM_R6M 2 2 2 330U_X_2VM_R6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M (Place these capacitors under CPU socket, top layer) CSC (Current Sense Configuration) 8/25 +1.05VS_VTT CPU_VID0 R436 R451 @ 1K_0402_1% 1K_0402_1% CPU_VID1 R437 R452 @ 1K_0402_1% 1K_0402_1% 22U_0805_6.3V6M AF10 AE10 AC10 AB10 Y10 W10 U10 T10 J12 J11 J16 J15 C278 C277 22U_0805_6.3V6M 2 22U_0805_6.3V6M CPU_VID2 R438 R453 CPU_VID3 R439 R454 @ 1K_0402_1% 1K_0402_1% CPU_VID4 R440 R455 @ 1K_0402_1% 1K_0402_1% PSI# AN33 H_PSI# AK35 AK33 AK34 AL35 AL33 AM33 AM35 AM34 CPU_VID0 54 CPU_VID1 54 CPU_VID2 54 CPU_VID3 54 CPU_VID4 54 CPU_VID5 54 CPU_VID6 54 H_DPRSLPVR 54 @ VTT_SELECT G15 H_VTTVID1 @ 1K_0402_1% 1K_0402_1% C157 CPU_VID6 VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6] PROC_DPRSLPVR C +CPU_CORE R441 R456 R442 R457 @ @ H_DPRSLPVR R443 R458 @ H_PSI# @ R444 R459 1 C276 22U_0805_6.3V6M C270 C256 22U_0805_6.3V6M 22U_0805_6.3V6M C241 22U_0805_6.3V6M C231 2 22U_0805_6.3V6M (Place these capacitors on CPU cavity, Bottom Layer) 1K_0402_1% 1K_0402_1% 1K_0402_1% 1K_0402_1% +CPU_CORE 22U_0805_6.3V6M 1K_0402_1% 1K_0402_1% 1K_0402_1% 1K_0402_1% C222 54 C651 22U_0805_6.3V6M C658 C666 22U_0805_6.3V6M 22U_0805_6.3V6M C665 22U_0805_6.3V6M C668 2 22U_0805_6.3V6M (Place these capacitors on CPU cavity, Bottom Layer) B T8 PAD VTT Rail H_VTTVID1 = low, 1.1V H_VTTVID1 = high, 1.05V Auburndale +1.1VS_VTT=1.05V Clarksfield +1.1VS_VTT=1.1V +CPU_CORE ISENSE VCC_SENSE VSS_SENSE VTT_SENSE VSS_SENSE_VTT AN35 AJ34 AJ35 B15 A15 x 470uF(4.5mohm@100kHz; 4.0mohm@SRF) IMVP_IMON 54 VCCSENSE_R R450 VSSSENSE_R R449 0_0402_5% 0_0402_5% VTT_SENSE 52 VSS_SENSE_VTT R523 1 R435 VCCSENSE VSSSENSE 100_0402_1% R448 100_0402_1% +CPU_CORE VCCSENSE 54 VSSSENSE 54 + + C541 2 330U_X_2VM_R6M 0_0402_5% @ 330U_X_2VM_R6M + C136 + C251 330U_X_2VM_R6M 330U_X_2VM_R6M C134 330U_X_2VM_R6M TOP side (under inductor) +CPU-CORE Decoupling SPCAP,Polymer 2009/08/01 Issued Date C,uF ESR, mohm 4X470uF 4m ohm/4 16X22uF 3m ohm/12 16X10uF 3m ohm/16 Stuffing Option 2X470uF A Compal Electronics, Inc Compal Secret Data Security Classification IC,AUB_CFD_rPGA,R1P0 CONN@ + C97 MLCC 0805 X5R 2010/08/01 Deciphered Date Title PROCESSOR (4/6) PWR,Bypass THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC NEW70 M/B LA-5891P Schematic Date: D +1.05VS_VTT CPU_VID5 POWER B +1.05VS_VTT 10U_0805_6.3V6M 10U_0805_6.3V6M AH14 AH12 AH11 AH10 J14 J13 H14 H12 G14 G13 G12 G11 F14 F13 F12 F11 E14 E12 D14 D13 D12 D11 C14 C13 C12 C11 B14 B12 A14 A13 A12 A11 +1.05VS_VTT CPU VIDS C VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCC18 VCC19 VCC20 VCC21 VCC22 VCC23 VCC24 VCC25 VCC26 VCC27 VCC28 VCC29 VCC30 VCC31 VCC32 VCC33 VCC34 VCC35 VCC36 VCC37 VCC38 VCC39 VCC40 VCC41 VCC42 VCC43 VCC44 VCC45 VCC46 VCC47 VCC48 VCC49 VCC50 VCC51 VCC52 VCC53 VCC54 VCC55 VCC56 VCC57 VCC58 VCC59 VCC60 VCC61 VCC62 VCC63 VCC64 VCC65 VCC66 VCC67 VCC68 VCC69 VCC70 VCC71 VCC72 VCC73 VCC74 VCC75 VCC76 VCC77 VCC78 VCC79 VCC80 VCC81 VCC82 VCC83 VCC84 VCC85 VCC86 VCC87 VCC88 VCC89 VCC90 VCC91 VCC92 VCC93 VCC94 VCC95 VCC96 VCC97 VCC98 VCC99 VCC100 SENSE LINES D CPU CORE SUPPLY AG35 AG34 AG33 AG32 AG31 AG30 AG29 AG28 AG27 AG26 AF35 AF34 AF33 AF32 AF31 AF30 AF29 AF28 AF27 AF26 AD35 AD34 AD33 AD32 AD31 AD30 AD29 AD28 AD27 AD26 AC35 AC34 AC33 AC32 AC31 AC30 AC29 AC28 AC27 AC26 AA35 AA34 AA33 AA32 AA31 AA30 AA29 AA28 AA27 AA26 Y35 Y34 Y33 Y32 Y31 Y30 Y29 Y28 Y27 Y26 V35 V34 V33 V32 V31 V30 V29 V28 V27 V26 U35 U34 U33 U32 U31 U30 U29 U28 U27 U26 R35 R34 R33 R32 R31 R30 R29 R28 R27 R26 P35 P34 P33 P32 P31 P30 P29 P28 P27 P26 Continuous 18A 1.1V RAIL POWER 48A Tuesday, December 29, 2009 Sheet of 59 Rev 1.0 +VGFX_CORE JCPU1G C272 C673 C672 + UMA@ UMA@ UMA@ UMA@ 2 330U_X_2VM_R6M 22U_0805_6.3V6M 10U_0805_6.3V6M C J24 J23 H25 VTT1_45 VTT1_46 VTT1_47 15A GRAPHICS 091211 EMI ADD 0.1U VAXG1 VAXG2 VAXG3 VAXG4 VAXG5 VAXG6 VAXG7 VAXG8 VAXG9 VAXG10 VAXG11 VAXG12 VAXG13 VAXG14 VAXG15 VAXG16 VAXG17 VAXG18 VAXG19 VAXG20 VAXG21 VAXG22 VAXG23 VAXG24 VAXG25 VAXG26 VAXG27 VAXG28 VAXG29 VAXG30 VAXG31 VAXG32 VAXG33 VAXG34 VAXG35 VAXG36 3A 2 C260 FDI 22U_0805_6.3V6M AR22 AT22 GFX_VID[0] GFX_VID[1] GFX_VID[2] GFX_VID[3] GFX_VID[4] GFX_VID[5] GFX_VID[6] AM22 AP22 AN22 AP23 AM23 AP24 AN24 GFX_VR_EN GFX_DPRSLPVR GFX_IMON AR25 AT25 AM24 VCC_AXG_SENSE 53 VSS_AXG_SENSE 53 D GFXVR_VID_0 GFXVR_VID_1 GFXVR_VID_2 GFXVR_VID_3 GFXVR_VID_4 GFXVR_VID_5 GFXVR_VID_6 GFXVR_EN GFXVR_DPRSLPVR_R R92 R99 GFXVR_EN 53 53 53 53 53 53 53 R98 Reserved for +1.5V to +1.5V_1 GFXVR_EN 53 GFXVR_DPRSLPVR 53 GFXVR_IMON 53 0_0402_5% +1.5V_1 22U_0805_6.3V6M VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15 VDDQ16 VDDQ17 VDDQ18 AJ1 AF1 AE7 AE4 AC1 AB7 AB4 Y1 W7 W4 U1 T7 T4 P1 N7 N4 L1 H1 1U_0402_6.3V4Z 1U_0402_6.3V4Z 22U_0805_6.3V6M C307 1 C308 C309 C306 22U_0805_6.3V6M 1.1V VTT1_48 VTT1_49 VTT1_50 VTT1_51 VTT1_52 VTT1_53 VTT1_54 VTT1_55 VTT1_56 VTT1_57 VTT1_58 C310 C303 C315 2 1 @ JUMP_43X118 + C326 330U_D2_2V_Y J2 2 1 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 22U_0805_6.3V6M +1.5VS C Short for +1.5VS to +1.5V_1 11/03 add four 0.1u 0402 Intel suggest for S3 reduse +1.5V_1 +1.5V P10 N10 L10 K10 C267 VTT1_63 VTT1_64 VTT1_65 VTT1_66 VTT1_67 VTT1_68 J22 J20 J18 H21 H20 H19 VCCPLL1 VCCPLL2 VCCPLL3 L26 L27 M26 C797 0.1U_0402_16V4Z C798 0.1U_0402_16V4Z C799 0.1U_0402_16V4Z C800 0.1U_0402_16V4Z 10U_0805_6.3V6M C283 22U_0805_6.3V6M B +1.8VS 0.6A 1.8V K26 J27 J26 J25 H27 G28 G27 G26 F26 E26 E25 +1.05VS_VTT VTT0_59 VTT0_60 VTT0_61 VTT0_62 PEG & DMI 22U_0805_6.3V6M B C285 @ JUMP_43X118 2 @ JUMP_43X118 +1.05VS_VTT +1.5V J4 DISO@ 1K_0402_5% +1.05VS_VTT C287 470_0402_5% J3 +1.05VS_VTT C253 VAXG_SENSE VSSAXG_SENSE - 1.5V RAILS DDR3 C675 UMA@ C250 GRAPHICS VIDs 2 D POWER R514 0_0402_5% DISO@ C610 0.1U_0402_16V4Z AT21 AT19 AT18 AT16 AR21 AR19 AR18 AR16 AP21 AP19 AP18 AP16 AN21 AN19 AN18 AN16 AM21 AM19 AM18 AM16 AL21 AL19 AL18 AL16 AK21 AK19 AK18 AK16 AJ21 AJ19 AJ18 AJ16 AH21 AH19 AH18 AH16 SENSE LINES 10U_0805_6.3V6M 22U_0805_6.3V6M 2.2U_0603_6.3V4Z +1.8VS_VCCSFR C230 1U_0402_6.3V4Z IC,AUB_CFD_rPGA,R1P0 CONN@ C224 1 2 1U_0402_6.3V4Z C235 R97 0_0805_5% 40mil C234 C233 22U_0805_6.3V6M 4.7U_0805_10V4Z A A Compal Electronics, Inc Compal Secret Data Security Classification 2009/08/01 Issued Date Deciphered Date 2010/08/01 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title PROCESSOR (5/6) PWR Size Document Number Custom NEW70 M/B LA-5891P Schematic Date: Tuesday, December 29, 2009 Sheet of 59 Rev 1.0 D C B VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 JCPU1I VSS VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98 VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160 AE34 AE33 AE32 AE31 AE30 AE29 AE28 AE27 AE26 AE6 AD10 AC8 AC4 AC2 AB35 AB34 AB33 AB32 AB31 AB30 AB29 AB28 AB27 AB26 AB6 AA10 Y8 Y4 Y2 W35 W34 W33 W32 W31 W30 W29 W28 W27 W26 W6 V10 U8 U4 U2 T35 T34 T33 T32 T31 T30 T29 T28 T27 T26 T6 R10 P8 P4 P2 N35 N34 N33 N32 N31 N30 N29 N28 N27 N26 N6 M10 L35 L32 L29 L8 L5 L2 K34 K33 K30 K27 K9 K6 K3 J32 J30 J21 J19 H35 H32 H28 H26 H24 H22 H18 H15 H13 H11 H8 H5 H2 G34 G31 G20 G9 G6 G3 F30 F27 F25 F22 F19 F16 E35 E32 E29 E24 E21 E18 E13 E11 E8 E5 E2 D33 D30 D26 D9 D6 D3 C34 C32 C29 C28 C24 C22 C20 C19 C16 B31 B25 B21 B18 B17 B13 B11 B8 B6 B4 A29 A27 A23 A9 IC,AUB_CFD_rPGA,R1P0 CONN@ VSS161 VSS162 VSS163 VSS164 VSS165 VSS166 VSS167 VSS168 VSS169 VSS170 VSS171 VSS172 VSS173 VSS174 VSS175 VSS176 VSS177 VSS178 VSS179 VSS180 VSS181 VSS182 VSS183 VSS184 VSS185 VSS186 VSS187 VSS188 VSS189 VSS190 VSS191 VSS192 VSS193 VSS194 VSS195 VSS196 VSS197 VSS198 VSS199 VSS200 VSS201 VSS202 VSS203 VSS204 VSS205 VSS206 VSS207 VSS208 VSS209 VSS210 VSS211 VSS212 VSS213 VSS214 VSS215 VSS216 VSS217 VSS218 VSS219 VSS220 VSS221 VSS222 VSS223 VSS224 VSS225 VSS226 VSS227 VSS228 VSS229 VSS230 VSS231 VSS232 VSS233 D C VSS NCTF JCPU1H AT20 AT17 AR31 AR28 AR26 AR24 AR23 AR20 AR17 AR15 AR12 AR9 AR6 AR3 AP20 AP17 AP13 AP10 AP7 AP4 AP2 AN34 AN31 AN23 AN20 AN17 AM29 AM27 AM25 AM20 AM17 AM14 AM11 AM8 AM5 AM2 AL34 AL31 AL23 AL20 AL17 AL12 AL9 AL6 AL3 AK29 AK27 AK25 AK20 AK17 AJ31 AJ23 AJ20 AJ17 AJ14 AJ11 AJ8 AJ5 AJ2 AH35 AH34 AH33 AH32 AH31 AH30 AH29 AH28 AH27 AH26 AH20 AH17 AH13 AH9 AH6 AH3 AG10 AF8 AF4 AF2 AE35 VSS_NCTF1 VSS_NCTF2 VSS_NCTF3 VSS_NCTF4 VSS_NCTF5 VSS_NCTF6 VSS_NCTF7 AT35 AT1 AR34 B34 B2 B1 A35 H_NCTF1 H_NCTF2 @ @ PAD T14 PAD T19 H_NCTF6 H_NCTF7 @ @ PAD T18 PAD T15 B IC,AUB_CFD_rPGA,R1P0 CONN@ A A Compal Electronics, Inc Compal Secret Data Security Classification 2009/08/01 Issued Date Deciphered Date 2010/08/01 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title PROCESSOR (6/6) VSS Size Document Number Custom NEW70 M/B LA-5891P Schematic Date: Tuesday, December 29, 2009 Sheet of 59 Rev 1.0 +1.5V DIMMA VREFDQ M1 Circuit JDIMM1 DDR_A_DQS#[0 7] +DIMM_VREFDQA +1.5V DDR_A_D[0 63] DDR_A_DM[0 7] +DIMM_VREFDQA R222 1 DDR_A_D0 DDR_A_D1 C402 DDR_A_DM0 0.1U_0402_16V4Z DDR_A_MA[0 15] 20mil C401 DDR_A_DQS[0 7] 1K_0402_1% 2 2.2U_0603_6.3V4Z DDR_A_D2 DDR_A_D3 DDR_A_D8 DDR_A_D9 R227 D DDR_A_DQS#1 DDR_A_DQS1 1K_0402_1% DDR_A_D10 DDR_A_D11 DDR_A_D16 DDR_A_D17 DDR_A_DQS#2 DDR_A_DQS2 DIMMA & DIMMB VREFCA circuit +1.5V DDR_A_D18 DDR_A_D19 DDR_A_D24 DDR_A_D25 +DIMM_VREFCA R203 DDR_A_DM3 1K_0402_1% +1.5V R201 R254 0_0402_5% @ 1K_0402_1% DDR_A_D26 DDR_A_D27 #425302 CP_S3PowerReduction WhitePaper_Rev1.0 20mil DDR_A_CKE0 DDR_A_BS2 DDR_A_CKE0 2 D S DIMM_DRAMRST# Q17 BSS138LT1G_SOT23-3 SM_DRAMRST# G C RST_GATE DIMM_DRAMRST# 11 DDR_A_BS2 DDR_A_MA12 DDR_A_MA9 C422 RST_GATE DDR_A_MA8 DDR_A_MA5 DDR_A_MA3 DDR_A_MA1 0.047U_0402_16V7K 6 6 6 DDR_A_CLK0 DDR_A_CLK0# DDR_A_CLK0 DDR_A_CLK0# DDR_A_MA10 DDR_A_BS0 DDR_A_BS0 DDR_A_WE# DDR_A_CAS# DDR_A_WE# DDR_A_CAS# DDR_A_MA13 DDR_A_CS1# DDR_A_CS1# DDR_A_D32 DDR_A_D33 Layout Note: Place near JDIMM1 DDR_A_DQS#4 DDR_A_DQS4 DDR_A_D34 DDR_A_D35 Layout Note: Place these Caps near Command and Control signals of DIMMA DDR_A_D40 DDR_A_D41 B +1.5V DDR_A_DM5 10U_0805_6.3V6M 10U_0805_6.3V6M 0.1U_0402_16V4Z 0.1U_0402_16V4Z DDR_A_D42 DDR_A_D43 10U_0805_6.3V6M C355 C356 10U_0805_6.3V6M C405 C404 10U_0805_6.3V6M C406 10U_0805_6.3V6M 1 2 C362 0.1U_0402_16V4Z C363 C399 C400 C354 + C425 330U_2.5V_M_R15 @ DDR_A_D48 DDR_A_D49 DDR_A_DQS#6 DDR_A_DQS6 DDR_A_D50 DDR_A_D51 0.1U_0402_16V4Z DDR_A_D56 DDR_A_D57 DDR_A_DM7 DDR_A_D58 DDR_A_D59 Layout Note: Place near JDIMM1.203 & JDIMM1.204 R218 10K_0402_5% C403 2.2U_0603_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1 2 C398 +3VS +0.75VS 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 VREF_DQ VSS2 DQ0 DQ1 VSS4 DM0 VSS5 DQ2 DQ3 VSS7 DQ8 DQ9 VSS9 DQS#1 DQS1 VSS11 DQ10 DQ11 VSS13 DQ16 DQ17 VSS15 DQS#2 DQS2 VSS18 DQ18 DQ19 VSS20 DQ24 DQ25 VSS22 DM3 VSS23 DQ26 DQ27 VSS25 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203 CKE0 VDD1 NC1 BA2 VDD3 A12/BC# A9 VDD5 A8 A5 VDD7 A3 A1 VDD9 CK0 CK0# VDD11 A10/AP BA0 VDD13 WE# CAS# VDD15 A13 S1# VDD17 NCTEST VSS27 DQ32 DQ33 VSS29 DQS#4 DQS4 VSS32 DQ34 DQ35 VSS34 DQ40 DQ41 VSS36 DM5 VSS37 DQ42 DQ43 VSS39 DQ48 DQ49 VSS41 DQS#6 DQS6 VSS44 DQ50 DQ51 VSS46 DQ56 DQ57 VSS48 DM7 VSS49 DQ58 DQ59 VSS51 SA0 VDDSPD SA1 VTT1 VSS1 DQ4 DQ5 VSS3 DQS#0 DQS0 VSS6 DQ6 DQ7 VSS8 DQ12 DQ13 VSS10 DM1 RESET# VSS12 DQ14 DQ15 VSS14 DQ20 DQ21 VSS16 DM2 VSS17 DQ22 DQ23 VSS19 DQ28 DQ29 VSS21 DQS#3 DQS3 VSS24 DQ30 DQ31 VSS26 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 DDR_A_D4 DDR_A_D5 DDR_A_DQS#0 DDR_A_DQS0 DDR_A_D6 DDR_A_D7 DDR_A_D12 DDR_A_D13 D DDR_A_DM1 DIMM_DRAMRST# DDR_A_D14 DDR_A_D15 DDR_A_D20 DDR_A_D21 DDR_A_DM2 DDR_A_D22 DDR_A_D23 DDR_A_D28 DDR_A_D29 DDR_A_DQS#3 DDR_A_DQS3 DDR_A_D30 DDR_A_D31 R274 1K_0402_1% 18 +1.5V R217 205 0.1U_0402_16V4Z 10K_0402_5% G1 G2 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 DDR_A_CKE1 DDR_A_CKE1 DDR_A_MA15 DDR_A_MA14 DDR_A_MA11 DDR_A_MA7 C DDR_A_MA6 DDR_A_MA4 DDR_A_MA2 DDR_A_MA0 DDR_A_CLK1 DDR_A_CLK1# DDR_A_CLK1 DDR_A_CLK1# DDR_A_BS1 DDR_A_RAS# DDR_A_BS1 DDR_A_RAS# DDR_A_CS0# DDR_A_ODT0 DDR_A_CS0# DDR_A_ODT0 DDR_A_ODT1 +DIMM_VREFCA DDR_A_ODT1 20mil DDR_VREF_CA_DIMMA R202 0_0402_5% DDR_A_D36 DDR_A_D37 DDR_A_DM4 DDR_A_D38 DDR_A_D39 C358 2.2U_0603_6.3V4Z DDR_A_D44 DDR_A_D45 1 2 C361 0.1U_0402_16V4Z B DDR_A_DQS#5 DDR_A_DQS5 DDR_A_D46 DDR_A_D47 DDR_A_D52 DDR_A_D53 DDR_A_DM6 DDR_A_D54 DDR_A_D55 DDR_A_D60 DDR_A_D61 DDR_A_DQS#7 DDR_A_DQS7 DDR_A_D62 DDR_A_D63 PM_EXTTS#0_1 D_CK_SDATA D_CK_SCLK PM_EXTTS#0_1 5,11 D_CK_SDATA 11,12 D_CK_SCLK 11,12 +0.75VS 206 FOX_AS0A626-U8RN-7F A A CKE1 VDD2 A15 A14 VDD4 A11 A7 VDD6 A6 A4 VDD8 A2 A0 VDD10 CK1 CK1# VDD12 BA1 RAS# VDD14 S0# ODT0 VDD16 ODT1 NC2 VDD18 VREF_CA VSS28 DQ36 DQ37 VSS30 DM4 VSS31 DQ38 DQ39 VSS33 DQ44 DQ45 VSS35 DQS#5 DQS5 VSS38 DQ46 DQ47 VSS40 DQ52 DQ53 VSS42 DM6 VSS43 DQ54 DQ55 VSS45 DQ60 DQ61 VSS47 DQS#7 DQS7 VSS50 DQ62 DQ63 VSS52 EVENT# SDA SCL VTT2 C391 C388 C397 C396 1 2 DDR3 SO-DIMM A H=8mm C394 10U_0805_6.3V6M 2009/08/01 Issued Date 1U_0402_6.3V4Z Compal Electronics, Inc Compal Secret Data Security Classification 1U_0402_6.3V4Z 2010/08/01 Deciphered Date Title DDRIII-SODIMM SLOT1 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC NEW70 M/B LA-5891P Schematic Date: Sheet Tuesday, December 29, 2009 10 of 59 Rev 1.0 A 10 EC_SMCA TH PI D PH1 under CPU botten side : CPU thermal protection at 92 degree C Recovery at 56 degree C EC_SMDA C PR542 100_0402_1% GND GND B PJP2 SUYIN_200275GR008G13GZR PR543 100_0402_1% VL EC_SMB_DA1 37 VMB VL GND RHYST1 OT1 TMSNS2 OT2 RHYST2 PR549 9.53K_0402_1% G718TM1U_SOT23-8 @ PR551 47K_0402_1% 1 VCC TMSNS1 2 PR550 1K_0402_1% @ PR547 100K_0402_1% PU30 +3VALW P PR546 21K_0402_1% PH1 100K_0402_1%_NCP15W F104F03RC PC380 0.01U_0402_25V7K PC379 1000P_0402_50V7K PR545 10K_0402_1% PC381 0.1U_0603_25V7K PR548 6.49K_0402_1% 1 PR544 1K_0402_5% EC_SMB_CK1 37 BATT_S1 BATT+ PL44 SMB3025500YA_2P 2 CONN@ BATT_TEMP 37 MAINPW ON 18,46,48 2 @ PH2 100K_0402_1%_NCP15W F104F03RC PQ44 TP0610K-T1-E3_SOT23-3 PC222 0.1U_0603_25V7K 2 PR327 22K_0402_1% VL +VSBP 1 PR325 100K_0402_1% PC221 0.22U_0603_25V7K B+ PQ45 G D S 2N7002W -T/R7_SOT323-3 PC224 1U_0402_6.3V6K SPOK PR330 1K_0402_5% 46 PR329 100K_0402_1% 4 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2007/09/20 Deciphered Date 2010/08/01 Title BATTERY CONN / OTP THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Rev 1.0 NEW70 M/B LA-5891P Schematic Date: A B C Tuesday, December 29, 2009 D Sheet 45 of 59 ISL6237_B+ ISL6237_B+ B+ VBST1 17 DRVL2 30 VOUT2 FB3 32 VL LL1 16 DRVL1 18 LG5 PGND 22 VOUT1 10 FB1 11 VSW VREF2 LDOREFIN 28 EN_LDO PGOOD1 13 TRIP1 12 ILM1 TRIP2 31 ILIM2 14 EN1 27 EN2 PR340 @ 0_0402_5% PR341 0_0402_5% + PC237 220U_6.3VM_R15 SPOK RT8206BGQW QFN 32P 45 For +5VALWP Power Budget=8.8A, Ipeak=7A, I max=4.9A Fsw=300KHz by RT8206 setting ∆I=2.61A, 1/2∆I=1.306A 5uA*PR344=10*Iocpmin*18mΩ*1.3 =>PR344=397KΩ~402KΩ PR344 402K_0402_1% 2 C VL PR345 267K_0402_1% B 5uA*402K=10*ILIMTmin*18mΩ*1.3 ILIMTmin=8.589A 5uA*402K=10*ILIMTmax*15mΩ*1.1 ILMIT=12.181A Iocp=9.89A~13.48A 13/5V_TON PR347 0_0402_5% 21 PC241 1U_0603_10V6K 13/5V_NC For +3VALWP Power Budget=4.72A, Ipeak=4.72A, Imax=4A Iocpmin=4.72*1.2=5.664~5.7A Fsw=375KHz, ∆I=1.547A, 1/2∆I=0.773A 5uA*PR345=10*Iocpmin*Rdsonmax*1.3 5uA*PR345=10*5.7A*18mΩ*1.3 PR345=266.76K~267K PR350 0_0402_5% 2VREF_ISL6237 PC243 @ 0.047U_0402_16V7K GND PGOOD2 TONSE NC TP0610K-T1-E3_SOT23-3 @ PQ50 080414:PQ23 ,Del @ 5V_SKIP 29 2 2 PR349 47K_0402_5% 1 18,45,48 MAINPWON PR348 0_0402_5% @ PR346 0_0402_5% PD8 1SS355_SOD323-2 PR561 806K_0603_1% PC242 0.047U_0402_16V7K B 1 VS 3/5V_EN1 PC240 0.22U_0603_25V7K 2VREF_ISL6237 VL EN_LDO PC238 680P_0603_50V7K FB5 SKIPSEL VREF3 20 PR342 100K_0402_1% PC236 0.1U_0603_25V7K REFIN2 1 PR343 200K_0402_5% EN_LDO-1 1 LL2 23 25 LG3 SW 1 SW PC239 0.22U_0603_25V7K PD7 RLZ5.1B_LL34 PR336 4.7_1206_5% 2BST5A-1 PR334 PC234 0.1U_0603_25V7K PC235 680P_0603_50V7K BST5A1 2.2_0603_5% VBST2 PQ49 AO4712_SO8 HG5 15 PL27 4.7UH_SIL104R-4R7PF_5.7A_30% DRVH1 PC232 1U_0603_10V6K +5VALWP PQ47 AO4466_SO8 DRVH2 2VREF_ISL6237 VS PC231 4.7U_0603_6.3V6K PC230 1U_0603_10V6K 3/5V_VCC 19 V5DRV D PR339 0_0402_5% 2 LDO 24 V5FILT BST3A-1 PQ48 BST3A 2.2_0603_5% PR333 AO4712_SO8 PR338 @ 10K_0402_1% C 3/5V_VIN 26 VIN UG3 TP 2 33 1 + 13V_SNB 2 PU16 PR332 4.7_1206_5% PR335 0_0402_5% 2 PL28 4.7UH_SIL104R-4R7PF_5.7A_30% +3VALWP PC229 0.1U_0603_25V7K PQ46 AO4466_SO8 VL @ PR337 61.9K_0402_1% 5 PC226 2200P_0402_50V7K PC225 10U_1206_25V6M HCB4532KF-800T90_1812 D PC228 2200P_0402_50V7K 2 PC227 10U_1206_25V6M PR331 0_0805_5% PL26 PC233 220U_6.3VM_R15 5uA*267KΩ=10*ILIMTmin*18mΩ*1.3 ILIMTmin=5.705A 5uA*267KΩ=10*ILIMTmax*15mΩ*1.1 ILIMTmax=8.09A Iocp=6.47A~8.86A A A Compal Secret Data Security Classification 2009/02/04 Issued Date 2010/08/01 Deciphered Date Title Compal Electronics, Inc 3VALW/5VALW THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Tuesday, December 29, 2009 Date: Rev 1.0 NEW70 M/B LA-5891P Schematic Sheet 46 of 59 A B Iada=0~4.74A(90W/19V=4.736A) Iada=0~3.42A(90W/19V=3.421A) P2 B+ P3 PQ52 AO4407A_SO8 CHG_B+ B+ PR351 0.02_2512_1% PQ53 AO4407A_SO8 PJ18 EN CSON 22 CELLS CSOP 21 ICOMP CSIN 20 VCOMP CSIP 19 ICM PHASE 18 10K_0402_1% VREF UGATE 17 DH_CHG CHLIM BOOT 16 ACLIM VDDP 15 LGATE 12 GND PGND 13 D 0.02_1206_1% PR376 4.7_0603_5% PC265 4.7U_0603_6.3V6K ISL6251AHAZ-T_QSOP24 S VMB PR379 15.4K_0402_1% PR380 340K_0402_1% PR383 10K_0402_1% 2 PU13B LM358DT_SO8 + - PC267 0.01U_0402_25V7K PR384 105K_0402_1% CV mode 1 37 BATT_OVP PR382 499K_0402_1% 2 Per cell=4.5V BATT-OVP=0.1112*VMB Kv Rinternal ic=514K Rec=3K R1=PR379=15.4K R2=PR381=31.6K R=514K//31.6K//(15.4K+3k)=11.372K r=514K//514K//31.6K=28.14K Vcell=0.175*Vadj+3.99v 4.2V=0.175*Vadj+3.99V =>Vadj=1.2V Vadj=Vref*(R/(R+514K))+CALIBRATE*(r/(r=514K)) 1.1483=CALIBRATE*0.6046 =>CALIBRATE=1.899 1.899=(4.2-(Vcell+A*0.175))*Kv=(4.2-(4.2+A*0.175))*Kv A=Vref*(R/(R+514K))=0.052 Kv=9.451 VS LI-3S :13.5V BATT-OVP=1.5012V PC266 0.01U_0402_25V7K PR381 31.6K_0402_1% Ki Vchlim=Iref*(PR374/(PR372+PR374)) =Iref*(100K/(80.6K+100K)) =Iref*0.5537 Ichanrge=(165mV/PR369)*(Vchlim/3.3V) =(165m/20m)*(1/3.3V)*Iref*0.5537 =1.3842*Iref Iref=0.7224*Ichanrge =>Ki=0.7224 12600mV RB751V-40_SOD323-2 26251VDD Normal 3S LI-ON Cells 2N7002W -T/R7_SOT323-3 PQ66 G 6251VDDP DL_CHG CHG PQ64 AO4466_SO8 BATT+ PR369 PC260 0.1U_0603_25V7K BST_CHGA PD13 VADJ 14 TCR=50ppm / C PL29 10UH_PCMB104T-100MS_6A_20% 2 11 PACIN 2N7002W -T/R7_SOT323-3 G S 10 PQ61D 6251ACLIM 20K_0402_1% PR378 12.1K_0402_1% 6251VREF 37 CALIBRATE# Charging Voltage (0x15) PR373 0_0603_5% BST_CHG PQ62 AO4466_SO8 PR375 CP mode Iinput=(1/0.02)(0.05*Vaclm/2.39+0.05) where Vaclm=1.502V, Iinput=4.07A BATT Type CSOP 0.1U_0402_16V7K 37 65W/90W# CC=0.6~4.48A Iref=0.7224*Ichanrge kI=0.7224 IREF=0.43V~3.24V CSON PR374 100K_0402_1% 6251VREF PC259 IREF ADP_I PR368 100_0402_1% 2 PC258 @ 100P_0402_50V8J PR372 80.6K_0402_1% PR363 20_0402_5% PC254 0.047U_0402_16V7K PR364 20_0402_5% PR365 PC257 20_0402_5% 0.1U_0603_25V7K PR367 2_0402_5% LX_CHG PC264 10U_1206_25V6M PC263 10U_1206_25V6M 23 ACSET ACPRN VIN PD12 PR370 4.7_1206_5% DCIN ACOFF 1SS355_SOD323-2 PR357 200K_0402_1% 1SS355_SOD323-2 24 PD9 DCIN VIN PC262 680P_0402_50V7K VDD wrong Value PC252 0.1U_0603_25V7K 1 PR366 6800P_0402_25V7K PR377 2.55K_0402_1% ACOFF 37 ACOFF 37 PR371 22K_0402_5% PQ65 PDTC115EU_SOT323 PC256 0.01U_0402_25V7K ACON PACIN PQ57 PDTC115EU_SOT323 PR352 47K_0402_1% 1 PC250 2.2U_0603_6.3V6K 6251_EN 1 PC255 S PC261 0.01U_0402_25V7K PACIN D 2N7002W -T/R7_SOT323-3 ACON 37,48 PU17 S SUSP# 37,39,43,49 BAS40CW _SOT323-3 3S/4S# SUSP# 100K_0402_1% 37 PQ63 G 44,48 PR356 10K_0402_1% FSTCHG 1 PQ60 PDTC115EU_SOT323 48 PR358 D 2N7002W -T/R7_SOT323-3 PQ59 G PR361 150K_0402_1% 2 PC251 0.1U_0402_16V7K PR360 47K_0402_5% 100K_0402_1% 1 FSTCHG 6251VDD PR362 37 PQ55 PDTC115EU_SOT323 PD10 PR359 10K_0402_5% FSTCHG DCIN PD11 1SS355_SOD323-2 6251VDD 47K PQ58 PDTC115EU_SOT323 P3 PR355 100K_0402_1% 1 PC249 0.1U_0603_25V7K 2 PR354 200K_0402_1% PQ54 TP0610K-T1-E3_SOT23-3 PQ56 PDTA144EU_SOT323-3 47K CSIP PC248 5600P_0402_25V7K 4 PR353 47K_0402_1% CSIN JUMP_43X118 1 3 PC253 0.1U_0603_25V7K 2 PC247 2200P_0402_25V7K 1 PC246 0.1U_0603_25V7K PC245 10U_1206_25V6M 1 P G PC244 10U_1206_25V6M VIN D CP = 85%*Iada ; CP = 4.07A CP = 85%*Iada ; CP = 2.91A ADP_I = 19.9*Iadapter*Rsense PQ51 AO4407A_SO8 C 12.60V Issued Date Compal Electronics, Inc Compal Secret Data Security Classification - 2007/09/20 Deciphered Date 2010/08/01 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC CHARGER Rev 1.0 NEW70 M/B LA-5891P Schematic Date: A B C Tuesday, December 29, 2009 D Sheet 47 of 59 D D B+ PR385 2.2M_0402_5% PR386 1K_1206_5% 2 1 PR393 PR396 100K_0402_5% 1 C PQ68 PDTC115EU_SOT323 PR398 47K_0402_5% 2 2N7002W -T/R7_SOT323-3 G 37,47 ACOFF PQ70 PDTC115EU_SOT323 PACIN 44,47 PQ69D B+ 1 PR397 34K_0402_1% 2 PRG++ PR395 499K_0402_1% PC270 0.01U_0402_25V7K PR394 191K_0402_1% 2 32.4 PC268 0.1U_0603_25V7K RTCVREF PR391 1K_1206_5% 2 BAS40CW _SOT323-3 - O 3 PR390 1K_1206_5% PU18B LM393DG_SO8 ACON + PC269 1000P_0402_50V7K 47 P G PD15 LL4148_LL34-2 18,45,46 MAINPWON TP0610K-T1-E3_SOT23-3 PQ67 PR388 1K_1206_5% PD14 100K_0402_5% VS PR389 100K_0402_1% C VIN PR387 499K_0402_1% 100K_0402_5% PR392 VL S PQ71 PDTC115EU_SOT323 @ PR399 66.5K_0402_1% +5VALW 3 ACIN B Precharge detector Min typ Max H >L 14.589V 14.84V 15.243V L >H 15.562V 15.97V 16.388V B BATT ONLY Precharge detector Min typ Max H >L 6.138V 6.214V 6.359V L >H 7.196V 7.349V 7.505V A A 2007/09/20 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification Deciphered Date 2010/08/01 Title PRECHARGE THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Rev 1.0 NEW70 M/B LA-5891P Schematic Date: Tuesday, December 29, 2009 Sheet 48 of 59 D D C C PL30 2.2UH_MSCDRI-74A-2R2M-E_6.5A_20% +1.8VSP LX_1.8V FB GND SW IN BS EN/SYNC 10 PC279 22U_0805_6.3V6M 2 PC278 22U_0805_6.3V6M 1.8V_EN PC281 0.01U_0402_16V7K SW IN POK PC382 680P_0402_50V7K +5VALW GND 1 PR563 4.7_1206_5% PU20 MP2121DQ-LF-Z_QFN10_3X3 PR407 402K_0402_1% 2 PR405 309K_0402_1% VFB=0.8V PC283 10U_0805_10V4Z PR566 0_0402_5% B @ PD16 11 +1.5VS B340A_SMA2 +1.5V TP 1 PJ20 JUMP_43X39 PU21 NC REFEN NC VOUT NC GND +3VALW PC285 1U_0402_6.3V6K S 2007/09/20 Deciphered Date PC288 10U_0805_6.3V6M A Compal Electronics, Inc Compal Secret Data Security Classification Issued Date +0.75VSP PR410 1K_0402_1% PC286 0.1U_0402_16V7K 1 D S PQ72 2N7002W -T/R7_SOT323-3 OP1@ PQ102 2N7002W -T/R7_SOT323-3 SUSP G D G OP1@ PC287 1U_0402_6.3V6K A 1 OP1@ PR409 24.9K_0402_1% 2 1 39,43 SUSP PC274 0.47U_0603_16V7K VCNTL GND APL5336KAI-TRL SO8 1.8V_EN VIN 2 OP2@ PR409 0_0402_5% 37,39,43,47 SUSP# PR408 1K_0402_1% PC284 4.7U_0603_6.3V6K PR401 22K_0402_5% 1 2 PJ24 JUMP_43X39 1 OP1 Short OP2 Short 1 PC282 10U_0805_10V4Z B 2010/08/01 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC +1.8VSP/+0.75VSP Rev 1.0 NEW70 M/B LA-5891P Schematic Date: Tuesday, December 29, 2009 Sheet 49 of 59 A B C D PL31 FBMA-L18-453215-900LMA90T_1812 RT8209BGQW _W QFN14_3P5X3P5 2 1 + PC295 4.7U_0805_10V6K PC293 330U_6.3V_M PC294 680P_0603_50V7K Rds=4.5mΩ(Typ) 5.6mΩ(Max) VFB=0.75V VFB=0.75V Vo=VFB*(1+PR418/PR419)=1.52V Freq=282KHz(min) , 300KHz(typ) PR418 5.9K_0402_1% PR415 4.7_1206_5% LG_1.5V LGATE PQ74 AO4456_SO8 VDDP 10 +5VALW +1.5VP LX_1.5V 11 12 CS 14 NC PGND PHASE PL32 1UH_FDUE1040D-1R0M-P3_21.3A_20% PC292 0.1U_0603_25V7K @ PC297 47P_0402_50V8J PC296 4.7U_0603_6.3V6K 15 open-drain PGOOD GND FB UG_1.5V VDD UGATE 13 PR417 11K_0402_1% PR414 0_0603_5% 2BST_1.5V-1 BOOT VOUT EN/DEM TON PR416 100_0603_1% +5VALW BST_1.5V PU22 1.5V_EN @ PC291 0.1U_0402_16V7K @ PR413 47K_0402_5% PR412 0_0402_5% 37,43 SYSON PR411 280K_0402_1% B+ PC290 4.7U_0805_25V6-K PQ73 AO4466_SO8 Because +1.5VSP has 17.74A power budget, it includes DDR3, VGA chip, VRAM, so must use molding choke EN_PSV GND=>Disable SMPS FLOAT=>PWM_only mode HIGH=>Auto_skip mode PC289 4.7U_0805_25V6-K 51117_1.5V_B+ PR419 5.76K_0402_1% Cesr=15m ohm Ipeak=15.82A Iocpmin=18.98A ∆I=((19-1.5)*(1.5/19))/(L*Freq)=4.899A 1/2∆I=2.449A Iocp=18.09A~29.13A 3 4 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2008/08/10 Deciphered Date 2010/08/01 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC 1.5VP Rev 1.0 NEW70 M/B LA-5891P Schematic Date: A B C Tuesday, December 29, 2009 D Sheet 50 of 59 VGA_CORE F=1/(75*e-12*44.2)=300K Ipeak=33A Imax=23.1A Iocp=39.6A Iocpmin=(5.11K*26uA)/((5.6mohm/2)*1.2)=39.54A Iocpmin=39.54A B+_CORE 7138_VCORE LX_VCORE 1 VGA@ PC165 10U_1206_25V6M DH_VCORE VGA@ PR184 0_0603_5% BST_VCORE @ PR182 10K_0402_1% 2 D D 18 VGA_PWROK VGA@ PC166 0.1U_0603_25V7K +5VS VGA@ PQ38 SI7686DP-T1-E3_SO8 VGA@ PR186 4.7_0603_5% 7138_VCORE VGA@ PC167 2.2U_0603_6.3V6K VIN VCC BOOT UG PHASE PVCC 14 LG 13 PGND 12 ISEN 11 4 VGA@ PR552 0_0402_5% + VGA@ PC169 390U_2.5V_M ESR=10mohm VGA@ PC171 680P_0603_50V7K VGA@ PR553 10_0402_5% GCORE_SEN C GCORE_SEN 24 MAD@ PR197 68.1K_0402_1% Rds=4.5m/5.6mOHM +3VS S 1 G VGA@ PC175 4700P_0402_25V7K @ PR200 10K_0402_5% 2 MAD@ PR198 9.53K_0402_1% VGA@ PR199 10K_0402_5% D PAK@ PR198 8.87K_0402_1% PR195/PC172/PC174 must pop and modify in PVT VGA@ PR211 10K_0402_5% VGA@ PQ76 2N7002W-T/R7_SOT323-3 VGA@ PC174 6800P_0402_25V7K PAK@ PR197 43.2K_0402_1% @ PC998 0.01U_0402_25V7K PR196 36.5K_0402_1% VGA@ PR193 4.99K_0402_1% VGA@ PR195 49.9K_0402_1% S VGA@ PC172 22P_0402_50V8J 2 G 23,43,52 VGA_ON# VGA@ PQ98 2N7002W-T/R7_SOT323-3 D VGA@ 10 VGA@ PQ78 AO4456_SO8 +VGA_COREP VGA@ PQ75 AO4456_SO8 VGA@ PR190 5.11K_0402_1% VGA@ PR191 4.7_1206_5% VO NC VGA@ PC170 0.1U_0402_16V7K FSET EN FB C VGA@ PL14 0.36UH_PCMC104T-R36MN1R17_30A_20% 1 VGA@ PR189 10K_0402_1% VFB=0.6V VGA_ON DL_VCORE VGA@ PU998 APW7138NITRL_SSOP16 9,43,52 VGA_ON VGA@ PC168 2.2U_0603_6.3V6K 2 7138_VCORE @ PR187 10K_0402_5% @ PQ79 SI7686DP-T1-E3_SO8 +3VS PGOOD GND 15 16 VGA@ PR185 0_0603_5% 2 VGA@ PC164 10U_1206_25V6M VGA@ PL13 FBMA-L11-322513-201LMA40T_1210 B+ 5 B B MAD@ PR201 31.6K_0402_1% +3VS PAK@ PR201 25.5K_0402_1% +3VS @ PR555 10K_0402_5% 0.95 V 1.00 V 1.00 V 1.05 V X @ PR204 10K_0402_5% @ PR558 10K_0402_5% 1.12 V D VGA@ PQ100 2N7002W-T/R7_SOT323-3 A VGA@ PR559 10K_0402_5% 2 G 1.05 V 1 X VGA@ PR557 10K_0402_5% +3VS VGA@ PC177 4700P_0402_25V7K GPU_VID1 23 S 2 G S 0.93 V VGA@ PR556 10K_0402_5% 2 G 0.90 V 1 VGA@ PQ99 D 2N7002W-T/R7_SOT323-3 VGA@ PR202 10K_0402_5% 1 VGA@ PQ77 D 2N7002W-T/R7_SOT323-3 VGA@ PR210 10K_0402_5% 2 Core Voltage Level PARK XT GPU_VID1 GPU_VID0 Core Voltage Level MADISON PRO GPU_VID0 23 A VGA@ PR560 10K_0402_5% S Compal Secret Data Security Classification Issued Date 2007/12/18 2010/08/01 Deciphered Date Title Compal Electronics, Inc VGA_COREP/+1.1VSDGPU THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Rev 1.0 NEW70 M/B LA-5891P Schematic Date: Tuesday, December 29, 2009 Sheet 51 of 59 PL37 FBMA-L18-453215-900LMA90T_1812 DH_1.05VS_VTT PR461 BST_1.05VS_VTT 0_0603_5% 4 VO PR467 4.99K_0402_1% 2 PR470 57.6K_0402_1% PR469 90.9K_0402_1% @ PC999 0.01U_0402_25V7K PR472 5.11K_0402_1% 1 + PC332 680P_0603_50V7K PC333 390U_2.5V_M C Material Note: 330uF/9 mΩ, number are 3, Power 1, HW 單單單單單單Pin15 +1.05VS_VTTP @ PR473 10_0402_5% VTT_SENSE VFB=0.6V PR564 0_0402_5% +5VS +1.05VS_VTT B B PR465 4.7_1206_5% Rdson=2.3mΩ/3.2mΩ Layout Note: Close IC @ PR471 0_0402_5% 2 PC336 6800P_0402_25V7K PC334 22P_0402_50V8J Fsw=1/(PR470*K)=231KHz, K=75*10^-12 +1.05VSP_VTT Ipeak=25A Imax=17.5A Rsen(PR467)=2.2K Iocp=31.19A~56.41A Vref=(Rb/(Rtop+Rbot))*Vo =>0.6=(6.65/(5.11+6.65))*Vo Vo=1.061V +1.05VS_VTTP @ ISEN 11 10 FB NC PC331 0.1U_0402_16V7K FSET EN 12 C PGND 1 PC330 2.2U_0603_6.3V6K DCR=2.7mΩ(Typ) 3.0mΩ(Max) PL38 1UH_FDUE1040D-1R0M-P3_21.3A_20% PU999 APW7138NITRL_SSOP16 @ PR468 10K_0402_5% 13 PC329 2.2U_0603_6.3V6K DL_1.05VS_VTT PQ95 TPCA8028-H_SOP-ADVANCE8-5 VS_ON LG Layout Note: Close IC PQ83 TPCA8028-H_SOP-ADVANCE8-5 39 14 PQ82 SI7686DP-T1-E3_SO8 6268_VCORE_1.05VS_VTT VCC PR464 4.7_0603_5% 6268_VCORE_1.05VS_VTT BOOT PVCC D PR463 0_0603_5% 15 16 UG PHASE PGOOD VIN 1 GND PR466 57.6K_0402_1% PC328 0.1U_0603_25V7K +5VS 2 @ PR462 1K_0402_1% LX_1.05VS_VTT @ H_VTTPWRGD PGOOD=1V +3VS PR459 2K_0402_1% +5VS PR458 0_0402_5% PR460 2K_0402_1% 2 D PC327 10U_1206_25V6M 6268_B+ PC326 10U_1206_25V6M B+ +1.5V 1 @ PJ22 JUMP_43X118 VGA@ PR528 1.54K_0402_1% +1.0VSPDGPU VGA@ PC366 22U_0805_6.3V6M VGA@ PC365 0.022U_0402_25V7K 1 VGA@ PU28 APL5913-KAC-TRL_SO8 @ PR562 22K_0402_5% A S D FB=0.8V VGA@ PR529 6.04K_0402_1% Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2009/4/15 2010/08/01 Deciphered Date Title VGA@ PQ101 2N7002W-T/R7_SOT323-3 23,43,51 VGA_ON# G 2 VGA@ PC369 1U_0402_6.3V6K A FB VGA@ PC367 4.7U_0603_6.3V6K EN POK VOUT VOUT VCNTL VIN VIN GND 23,39,43,51 VGA_ON VGA@ PR530 27K_0402_1% 2 2 PR476 6.65K_0402_1% VGA@ PC320 1U_0402_6.3V6K THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC +1.05VS_VTTP Rev 1.0 NEW70 M/B LA-5891P Schematic Date: Sheet Tuesday, December 29, 2009 52 of 59 Intel Auburndale CPU(Integrate Graphics) Ipeak=22A Imax=15A OCP calculation : Assume DCR=1.1m ohm G1=Rn/(Rn+Rsum)=0.617 where Rn=PR277 // (PR274+PH3)=5.875k ohm Rsum=PR269=3.65k ohm LL=2*Rdroop*G1*DCR/Ri= 6.96m V/A where Rdroop=PR271=8.66k ohm, Ri=PR283=1.69k ohm Iocp=OCP Threshold*Rdroop/LL=24.89A D D UMA@ PL23 FBMA-L18-453215-900LMA90T_1812 GFX_B+ 1 2 UMA@ PC191 0.22U_0402_6.3V6K GFXVR_IMON ISUMBST_GFX 1 C 14 15 DH_GFX UMA@ PC199 680P_0603_50V7K 22 UMA@ PC198 2.2U_0603_6.3V6K Rds=4.5mOHM(typ) Rds=5.6mOHM(max) UMA@ PR270 0_0402_5% + UMA@ PC130 330U_X_2VM_R6M 10K +-5% TSM0A103J4302RE 0402 UMA@ PR277 11K_0402_1% Layout Note: Place near Choke Material Note: 330uF/6 mΩ, number are 3, PW 1, HW 1, of HW is backup UMA@ PC202 0.1U_0402_16V7K B UMA@ PC204 0.01U_0402_16V7K ISUM+ +1.05VS_VTT 2 @ PR284 100_0402_1% UMA@ PC203 0.1U_0402_16V7K UMA@ PR283 1.69K_0402_1% UMA@ PR288 82.5_0402_1% 2 GFXVR_VID_0 GFXVR_VID_1 GFXVR_VID_2 GFXVR_VID_3 GFXVR_VID_4 GFXVR_VID_5 GFXVR_VID_6 GFXVR_EN GFXVR_DPRSLPVR UMA@ PR280 UMA@ PR281 UMA@ PR282 UMA@ PR285 UMA@ PR286 UMA@ PR287 UMA@ PR289 UMA@ PR290 @ PR291 UMA@ PR567 0_0402_5% 2 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 37 GFX_CORE_PWRGD B UMA@ PR274 2.61K_0402_1% UMA@ PH3 2 +5VALW @ PR279 10K_0402_1% UMA@ PR269 3.65K_0805_1% UMA@ PR273 0_0603_5% UMA@ PR268 4.7_1206_5% UMA@ PQ41 AO4456_SO8 21 UMA@ PQ40 AO4456_SO8 19 VID2 8 18 DL_GFX VID1 17 20 +VGFX_COREP UMA@ PL10 0.45UH_PCMB104T-R45MN_25A_20% 16 LX_GFX 13 12 11 10 UMA@ PQ39 SI7686DP-T1-E3_SO8 BOOT IMON VIN VDD RTN CLK_EN# UMA@ PC200 150P_0402_50V8J ISUM VID0 VID3 UMA@ PR276 8.06K_0402_1% PGOOD VID4 UMA@ PC201 22P_0402_50V8J VCCP 23 UMA@ PR275 17.8K_0402_1% 1 +VGFX_COREP RBIAS 24 147K for CPU 47K for GPU UMA@ PC196 100P_0402_50V8J LGATE VID5 UMA@ PC197 1000P_0402_50V7K VSSP VW 25 UMA@ PR272 825K_0402_1% PHASE COMP 28 UMA@ PR271 8.66K_0402_1% VID6 UMA@ PC193 0.22U_0603_25V7K DCR=1.1 mOHM UGATE UMA@ PU12 ISL62881HRZ-T_QFN28_4X4 FB VR_ON UMA@ PR294 47K_0402_1% VSEN DPRSLPVR 26 27 UMA@ PR293 10_0402_1% ISUM+ AGND UMA@ PC195 330P_0402_50V7K 29 2 +VGFX_COREP UMA@ PR266 0_0603_5% UMA@ PC194 330P_0402_50V7K VSS_AXG_SENSE VCC_AXG_SENSE ISUM+ UMA@ PC192 1000P_0402_50V7K C UMA@ PR265 22.6K_0402_1% UMA@ PR292 10_0402_1% VSS_AXG_SENSE UMA@ PC189 1U_0402_6.3V6K 1 UMA@ PR263 0_0603_5% UMA@ PR264 1_0603_5% 2 +5VALW @ PC188 0.1U_0402_25V6 UMA@ PC190 0.22U_0603_25V7K UMA@ PC126 10U_1206_25V6M UMA@ PC125 10U_1206_25V6M 2 UMA@ PC187 2200P_0402_50V7K B+ @ PC205 180P 50V J NPO 0402 ISUM- 2009-1214 common circiut modify A A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2009/4/15 Deciphered Date 2010/08/01 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title GFX_COREP Size C Date: Document Number Rev 1.0 NEW70 M/B LA-5891P Schematic Tuesday, December 29, 2009 Sheet 53 of 59 +5VS HFM_VID PH0 H H_DPRSLPVR PR565 0_0805_5% H_PSI# CPU_VID6 CPU_VID5 CPU_VID4 CPU_VID3 CPU_VID2 CPU_VID1 CPU_VID0 HFM_Icc LL Icc_Dyn Icc_TDC # of PH Auburndale 45W 1.075 50 1.9m 37 35 29 27 Auburndale 35W 0.975 38 1.9m 1 Clarksfield SV 0.95 51 1.9m 38 39 Clarksfield XE 0.95 65 TBD 48 TBD +5VS_3212 H +5VS_3212 7 7 7 PH1 +CPU_B+ PL39 FBMA-L18-453215-900LMA90T_1812 PR481 10_0603_5% VR_ON B+ 3212_VRTT 10 TTSENSE 11 VARFR SWFB2 VRTT SW2 28 3212_DRVH2 3212_DRVH2 PR515 69.8K_0402_1% 3212_SW2 3 1 PC343 220U_25V_M PC341 10U_1206_25V6M 2 CSREF 3212_CS_PH1 PC359 680P_0603_50V7K @ PQ92 TPCA8028-H_SOP-ADVANCE8-5 C PR522 73.2K_0402_1% PR523 165K_0402_1% PH6 100K_0402_1%_NCP15WF104F03RC 2 CSREF PC363 1200P_0402_50V7K PC361 1000P_0402_50V7K PC362 680P_0402_50V7K 2 D PR513 10_0402_5% 1 PR520 1K_0402_1% 2 1 +CPU_B+ Place PH1 close to PHASE inductor on the same layer TTSense PC360 0.01U_0402_50V7K 3212_DRVL2 VGA@ PQ93 TPCA8028-H_SOP-ADVANCE8-5 PR519 2.05K_0402_1% Connect to input caps PWM3 SWFB3 3212_DRVL2 2.05K PR517 649K_0402_1% PL41 0.36UH +-20% ETQP4LR36WFC 24A PR512 4.7_1206_5% @ 24 OD3 23 22 ILIM 21 3212_CSCOMP 3212_CSCOMP PR514 80.6K_0402_1% C PR521 0_0402_5% @ PQ91 TPCA8030-H_SOP-ADV8-5 PC358 0.1U_0603_25V7K CSCOMP 20 CSSUM 19 CSREF 18 17 LLINE RAMP 15 PR516 162K_0402_1% 16 14 RT RPM IREF 3212_VRTT G S PC339 10U_1206_25V6M 13 25 PR518 7.32K_0402_1% BST2 +5VS_3212 D PQ94 2N7002W-T/R7_SOT323-3 H_PROCHOT# AGND 49 GND PR511 0_0402_5% D PR510 @ 499_0402_1% 3212_DRVH2 PR509 0_0603_5% @ PC356 0.1U_0603_25V7K 26 PC355 10U_1206_25V6M DRVH2 1 2 3212_SW2 27 PQ90 TPCA8030-H_SOP-ADV8-5 3212_CS_PH2 TTSNS PC342 2200P_0402_50V7K E 3212_DRVL2 PR506 100_0402_1% 29 12 Avoid high dV/dt +CPU_B+ 30 DRVL2 +3VS PR508 0_0402_5% VGA@ PQ89 TPCA8028-H_SOP-ADVANCE8-5 PC350 4.7U_0603_6.3V6K 2 PGND 5.11K_0402_1% TRDET +5VS_3212 PR507 0_0402_5% COMP 3212_DRVL1 PR503 1.65K_0402_1% E 31 PQ88 TPCA8028-H_SOP-ADVANCE8-5 ADP3212MNR2G_QFN48_7X7 DRVL1 +5VS FB 32 PC347 680P_0603_50V7K @ CSREF PC353 150P_0402_50V8J PR504 39.2K_0402_1% 2 PR505 3212_CS_PH1 PVCC FBRTN 33 3212_DRVL1 +CPU_CORE F 3212_CS_PH2 12P_0402_50V8J 3212_FB PC352 PC351 150P_0402_50V8J SWFB1 PR502 100_0402_1% 3212_FBRTN CLKEN PR500 10_0402_5% PL40 0.36UH +-20% ETQP4LR36WFC 24A DCR=1.1m OHM PC354 10U_1206_25V6M 1 PC349 1000P_0402_50V7K CLK_EN# 3212_DRVL1 3212_SW1 34 PR499 4.7_1206_5% @ 3212_DRVH1 PC348 0.068U_0402_16V7K PR501 5.49K_0402_1% VCC SW1 35 37 38 PH1 39 PH0 40 IMON 36 PC346 0.1U_0603_25V7K 499_0402_1% 0_0402_5% PSI 41 PR490 0_0402_5% VID6 42 PR489 0_0402_5% VID5 43 PR488 0_0402_5% VID4 44 PR487 0_0402_5% VID3 45 PR486 0_0402_5% VID2 46 PR485 0_0402_5% VID1 47 PR483 48 DRVH1 PR498 0_0603_5% + @ PQ86 TPCA8030-H_SOP-ADV8-5 3212_SW1 AGND BST1 PWRGD 3212_DRVH1 PGND IMVP_IMON EN @ G 1 IMVP_IMON PQ87 TPCA8030-H_SOP-ADV8-5 2 PR496 0_0402_5% @ PR491 0_0603_5% 1 F VGATE PC344 1U_0603_16V6K 3212_DRVH1 DPRSLP 12,15 VID0 +1.05VS_VTT CLK_EN# PR497 0_0402_5% PU27 PR494 12 CLK_ENABLE# 0_0402_5% 1 PR493 3K_0402_5% PR495 0_0402_5% PR482 2 +3VS PR492 3K_0402_5% +3VS PR484 0_0402_5% G PC345 0.1U_0603_25V7K 2 37,39 PC364 1U_0603_16V6K PH7 100K_0402_1%_NCP15WF104F03RC PR524 2 B PR525 @ PR526 100_0402_1% VCCSENSE VSSSENSE 130K_0603_1% 3212_CS_PH1 3212_CS_PH2 B 130K_0603_1% +CPU_CORE VCCSENSE VSSSENSE PR527 100_0402_1% @ A A Compal Secret Data Security Classification 2009/02/04 Issued Date Deciphered Date 2010/08/01 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC CPU_CORE Size C Date: Compal Electronics, Inc Document Number Rev 1.0 NEW70 M/B LA-5891P Schematic Tuesday, December 29, 2009 Sheet 54 of 59 Version change list (P.I.R List) Item Page of for PWR Fixed Issue For BOM unique D Reason for change Rev For BOM unique 0.1 For BOM unique For UMA Arrandale CPU commond design PG# 46 54 0.1 52 0.1 54 Change PR500 from SD028100A00(S RES 1/16W 10 +-5% 0402) 2009-1021 to DVT to SD028100A80(S RES 1/16W 10 +-5% 0402) 0.1 47 Chnage PC265 from SE107475M80(S CER CAP 4.7U 6.3V M X5R 0603 to SE107475K80(S CER CAP 4.7U 6.3V K X5R 0603) 2009-1021 to DVT 0.1 49 Chnage PC284 from SE107475M80(S CER CAP 4.7U 6.3V M X5R 0603 to SE107475K80(S CER CAP 4.7U 6.3V K X5R 0603) 2009-1021 to DVT CIS link error 2009-1021 to DVT BOM unique 0.1 54 Chnage PC350 from SE107475M80(S CER CAP 4.7U 6.3V M X5R 0603 to SE107475K80(S CER CAP 4.7U 6.3V K X5R 0603) 2009-1021 to DVT BOM unique.(For Madison/Park SKU) 0.1 52 Chnage PC367 from SE107475M80(S CER CAP 4.7U 6.3V M X5R 0603 to SE107475K80(S CER CAP 4.7U 6.3V K X5R 0603) 2009-1021 to DVT BOM unique BOM unique 0.1 46 BOM unique BOM unique 0.1 54 +1.05VS_VTTP Cost down LS MOS Because +1.05VS_VTT has voltage drop issue, HW request, remote sense to close to PCH 0.2 52 Because we remove a LS MOS, so OCP must adjust 0.2 52 Change PR467 from SD000004O80(S RES 1/16W 2.2K +-1% 0402) to SD034499180(S RES 1/16W 4.99K 0402 1%) 2009-1029 to DVT 0.2 49 Delete PU19 SA00001NC00 (S IC APL5913-KAC-TRL SO 8P) 2009-1029 to DVT C +1.05VS_VTTP Cost down LS MOS HW request Adjust +1.05VS_VTTP OCP +1.8VSP2, Using MP2121 for 1.8V only +1.8VSP2, Using MP2121 for 1.8V only No need to Delete all No need to Delete all +1.8VSP2, Using MP2121 for 1.8V only No need to use LDO for +1.8V Delete all PU19 circiut +VGA_COREP, efficiency issue +VGA_COREP, OVP issue 19 Change PC225/PC227 from SE153106K80(S CER CAP 10U 25V K X6S 1206) to SE142106M80 (S CER CAP 10U 25V M X5R 1206) Change PC339/PC341 from SE153106K80(S CER CAP 10U X6S 1206) to SE142106M80 (S CER CAP 10U 25V M X5R Change PC354/PC355 from SE153106K80(S CER CAP 10U X6S 1206) to SE142106M80 (S CER CAP 10U 25V M X5R Delete PQ95 SB00000GL00(S TR TPCA8028-H 1N SOP ) Delete PR471 SD028000080(S RES 0402 5%) Delete PR473 from SD034100A80(S RES 10 0402 5%) 25V K 1206) 25V K 1206) 2009-1021 to DVT 2009-1021 to DVT 2009-1029 to DVT Add PR564 SD028000080(S RES 1/16W 0402 5%) use LDO for +1.8V PU19 circiut use LDO for +1.8V PU19 circiut 0.2 0.2 49 49 Increase Freq, decrease choke, to improve efficiency 0.2 51 Becasue if PR199/PR202 pop 0ohm, it will cause OVP when VID change from 00 to 11) 0.2 51 Delete PR402 SD034150280, PR404 SD034120280 Delete PC273 SE075103K80 B PC275 SE000000I10 2009-1029 to DVT Delete PC272 SE107475K80, PC271 SE107105M80 Delete PR401 and PR403 SD028220280, PC274 SE026474K80 Change PR196 from SD034442280 to SD034365280 2009-1029 to DVT 2009-1029 to DVT Change PL14 from SL200000V00 to SH000005680 Change PR199/PR202 from SD028000080 to SD028100280 (S RES 1/16W 10K 0402 5%) 2009-1029 to DVT +VGA_COREP, cost issue Cost down 0.2 51 Change PQ75/PQ78 from SB00000GL00(S TR TPCA8028-H 1N SOP) 2009-1029 to DVT to SB000009F80(S TR AO4456 1N SO8) +VGA_COREP, satndard design +VGA_COREP, satndard design, pop 1HS MOS and 2LS MOS, so remove one HS MOS PQ79 0.2 51 Delete PQ79 SB000008L80 (S TR SI7686DP-T1-E3 1N POWERPAK SO8 ) +GFX_COREP, spike issue Because +GFX_COREP has spike voltage issue, add schottky diode across GFXVR_EN and VS_ON to solve it 0.2 51 0.2 51 20 21 22 23 Delete PQ95 SB00000GL00(S TR TPCA8028-H 1N SOP) BOM unique 18 A 2009-1021 to DVT BOM unique 13 17 Delete PQ89/PQ93 SB00000GL00(S TR TPCA8028-H 1N SOP) BOM unique 10 16 D 2009-1021 to DVT BOM unique 15 Add PQ87/PQ90 SB00000HL00(S TR TPCA8030-H 1N SOP) BOM unique BOM unique.(For Madison/Park SKU) B Delete PQ86/PQ91 SB00000HL00(S TR TPCA8030-H 1N SOP) 0.1 14 2009-1021 to DVT For UMA Arrandale CPU, we just only pop HS MOS and LS MOS 12 Phase 54 11 Date 0.1 C Modify List Change PD8 from SC1SS355003(S DIO 1SS355) to SC100001K00( DIO 1SS355 SOD323 T/R-5K) For BOM unique For VTT Power rail commond design, we pop HS MOS For VTT Power rail commond design and 1LS MOS CIS link error +VGA_COREP, OCP caaculation erroe issue Because VGA_CORE has LS MOS, APW7138 detect LS Rdson, so when caculate OCP, Rdson must reduce 1/2 Issued Date Add PD17 SCS00000Z00 (S SCH DIO RB751V-40 SOD-323 ) Change PR190 from SD034649180 to SD034511180 (S RES 1/16W 5.11K 0402 1%) 2007/09/20 Deciphered Date 2009-1029 to DVT 2009-1029 to DVT A Compal Electronics, Inc Compal Secret Data Security Classification 2009-1029 to DVT 2010/08/01 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC PIR (PWR) NEW70 M/B LA-5891P Schematic Date: Tuesday, December 29, 2009 Sheet 55 of 59 Rev 1.0 Version change list (P.I.R List) Item D Page of for PWR Fixed Issue Reason for change Rev PG# Modify List Date Phase CPU choke TOHO quality issue Because TOHO has quality issue before, change to Panasonic choke 0.2 54 Change PL40/PL41 from SHSH00000F000 S COIL 0.36UH +-20% to DVT SF-I104-R36 23A to SH000005680 S COIL 0.36UH +-20% 2009-1029 PCMC104T-R36MN1R17 +VGA_COREP, voltage change ATI updated Park output voltage 0.2 51 Change PR197 from SD034649280 to SD034432280 2009-1029 +VGA_COREP, voltage change ATI updated Park output voltage 0.2 51 Chnage PR198 from SD034953180 to SD034887180 2009-1029 to DVT +VGA_COREP, voltage change ATI updated Park output voltage 0.2 51 CHange PR201 from SD034316280 to SD034255280 2009-1029 to DVT 0.2 51 Add PR557/PR560 SD028100280( S RES 1/16W 10K 0402 5%) Because HW request that adjust power sequence, +1.0VSPDGPU,adjust power sequence we will follow the value which given by HW 0.2 52 Change PC369 from SE076104K80 to SE000000K80 (S CER CAP 1U 0402 X7R) Because HW request that adjust power sequence, +1.0VSPDGPU,adjust power sequence we will follow the value which given by HW 0.2 52 Change PR530 from SD028150380 to SD034270280 (S RES 1/16W 27K 0402 1%) 2009-1029 to DVT Because HW request that adjust power sequence, +1.0VSPDGPU,adjust power sequence we will follow the value which given by HW 0.2 52 Delete PR562 SD028220280 (S RES 1/16W 22K +-5% 0402) 2009-1029 to DVT +0.75VSP,adjust power sequence Because HW request that adjust power sequence, we will follow the value which given by HW 0.2 49 =1.8VSP, voltage too small Because +1.8VSP drop in HW side, increase +1.8VSP 0.2 49 Because GFX_COREP has spike voltage issue, originally we add a schottcky diode to solve it, but Intel's 0.3 command is that not add it, because of overdriving, so delete it now 53 EMI request to add snubber 53 D to DVT C When VGA_CORE start up, but VBIOS doesn't ready, +VGA_COREP, initial state unknow the VID is unknow, add pull down R 10 +GFX_COREP, spike voltage issue 11 12 +GFX_COREP, EMI request 0.3 2009-1029 B +1.05VS_VTTP, EMI request EMI request to add snubber 14 +VGA_COREP, EMI request EMI request to add snubber 0.3 52 0.3 51 0.3 50 0.3 47 15 Change PC287 from SE076104K80 to SE000000K80 EMI request to add snubber Charger, EMI request EMI request to add snubber CPU_COREP, transient, load line modify CPU_COREP, transient, load line modify 16 17 18 0.3 54 to DVT 2009-1029 to DVT Change PR405 from SD034316380(S RES 1/16W 316K +-1% 0402) to DVT 2009-1029 to SD034309380(S RES 1/16W 309K 0402 1%) Delete PD17 SCS00000Z00( S SCH DIO RB751V-40 SOD-323) Add PR268 SD001470B80(S RES 1/4W 4.7 +-5% 1206) Add PR465 SD001470B80(S RES 1/4W 4.7 +-5% 1206) Add PC332 SE025681K80(S CER CAP 680P 50V K X7R 0603) Add PR191 SD001470B80(S RES 1/4W 4.7 +-5% 1206) Add PC171 SE025681K80(S CER CAP 680P 50V K X7R 0603) Add PR415 SD001470B80(S RES 1/4W 4.7 +-5% 1206) +1.5VP, EMI request to DVT C Change PR409 SD028000080 to SD034249280( 24.9K 0402 1%) Add PC199 SE025681K80(S CER CAP 680P 50V K X7R 0603) 13 2009-1029 2009-1104 to DVT 2009-1104 to DVT 2009-1104 to DVT 2009-1104 to DVT B Add PC294 SE025681K80(S CER CAP 680P 50V K X7R 0603) Add PR370 SD001470B80(S RES 1/4W 4.7 +-5% 1206) Add PC262 SE074681K80 (S CER CAP 680P 50V K X7R 0402) 2009-1104 to DVT 2009-1104 to DVT Change PR524/PR525 from SD014120380 to SD014130380 Change PR501 from SD034536180 to SD034549180 2009-1104 to DVT Change PC362 from SE074391K80 to SE074681K80 Change PL40/PL41 from SH000005680 to SH12036BM00 +VSBP, EMI request EMI request to add cap to reduce EMI noise on B+ 0.3 45 +1.8VSP BOM error Loss +1.8VSP enable circiut 0.3 49 19 20 21 Because ATI change Park output voltage, we saperate +VGA_COREP, output voltage change Park and Madison by PAK@ and MAD@ And Change Madison X63 BOM 22 +CPU_COREP, power measure 0.4 51 Add PC221 SE000005Z80 S CER CAP 22U 25V K X7R 0603 Add PC222 SE042104K80 S CER CAP 1U 25V K X7R 0603 Add PR401 SD014220280 S RES 1/16W 22K 0402 5% Add PC274 SE026474K80 S CER CAP 0.47U 16V K X7R 0603 2009-1104 to DVT 2009-1104 to DVT Change PR197 from SD034432280 to SD034681280 Chnage PR198 from SD034887180 to SD034953180 2009-1113 to DVT Change PR201 SD034255280 to SD034316280 A A Because HW want to measure CPU_CORE IC power loss, Add 0805 R to saperate +5VS 0.4 Add PR565 SD002000080 S RES 1/8W +-5% 0805 2007/09/20 Deciphered Date 2009-1113 to DVT Compal Electronics, Inc Compal Secret Data Security Classification Issued Date 54 2010/08/01 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC PIR (PWR) NEW70 M/B LA-5891P Schematic Date: Tuesday, December 29, 2009 Sheet 56 of 59 Rev 1.0 Version change list (P.I.R List) Item Page of for PWR Fixed Issue Reason for change Rev PG# Modify List Date Phase +CPU_COREP, IMON design change Intel release IMON RC time constant new request, change PC348 to 0.068u to meet spec 0.4 54 +CPU_COREP, cost issue SF000000G80 will cost up, change to SF22004M210 0.4 54 +3V/+5V cost issue Because Nippon cost up thier OS-CON cap, so we change Nippon cap to Sanyo cap by sourcer request 0.5 46 +1.05VS_VTTP issue +1.05VS_VTTP choke unique to +1.5VP 0.5 52 0.6 51 0.6 51 Change location PU23 to PU998 2009-1208 to PVT 0.6 52 Change PU26 from SA00001HT80 S IC ISL6268CAZ-T SSOP 16P to PU999 SA00002O600 S IC APW7138NITRL SSOP 16P 2009-1208 to PVT 0.6 52 Delete PC335 SE075103K80 S CER CAP 01U 25V K X7R 0402 and change location to PC999 2009-1208 to PVT 0.6 45 Add PC224 SE000000K80 S CER CAP 1U 6.3V K X5R 0402 2009-1208 to PVT If add PC224, must change PR330 from to 1K to avoid SPOK pin fail that is add a current limit R on SPOK pin 0.6 45 Chnage PR330 from SD028000080 to SD028100180 2009-1208 to PVT 49 Change PL30 from SH000006I80 S COIL 2.2UH +-20% PCMC063T 2009-1208 to PVT -2R2MN 8A to SH000009Q00 S COIL 2.2UH 20% MSCDRI-74A2R2M-E 6.5A D +VGA_COREP 2nd source issue C +VGA_COREP 2nd source issue +1.05VS_VTTP 2nd source issue +1.05VS_VTTP 2nd source issue HDD LED flash issue 10 HDD LED flash issue 11 BOM error In order to phase in 2nd source of APW7138, must add Pin6 components to meet ISL6268 reqirement In order to phase in 2nd source of APW7138, must add Pin6 components to meet ISL6268 reqirement In order to phase in 2nd source, change ISL6268 to APW7138 APW7138 needn't pop PC335 Change PC348 from SE076103K80 S CER CAP 01U 16V K X7R 0402 2009-1113 to DVT to SE000003J80 S CER CAP 0.068U 16V K X7R 0402 Change PC343 from SF000000G80 to SF22004M210 D 2009-1113 to DVT Change PC233/PC237 from SF22001M300 S ELE CAP 220U 6.3V M F60(6.3X5.7) PXC to SF22001M200 S ELE CAP 220U 6.3V M B 2009-1118 to DVT C6 SVPC ESR15 Change PL38 from SH000008V80 S COIL 1UH +-20% PCMB103E-1R0MS2009-1118 to DVT 20A to SH000009U00 S COIL 1UH +-20% FDUE1040D-1R0M=P3 21.3A Add PC172 SE071220J80 S CER CAP 22P 50V J NPO 0402 2009-1208 to PVT Add PC174 SE075682K80 S CER CAP 6800P 25V K X7R 0402 Add PR195 SD034909280 S RES 1/16W 90.9K 0402 1% C HDD LED will flash when plug in adapter, because +3VS rise a little HW request add PC224 to solve it +1.8VSP choke use wrong material 0.6 12 13 14 B B 15 16 17 18 19 20 A A 21 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2007/09/20 Deciphered Date 2010/08/01 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC PIR (PWR) NEW70 M/B LA-5891P Schematic Date: Tuesday, December 29, 2009 Sheet 57 of 59 Rev 1.0 A > B Change List D C B 1012: Page 29,30 Update F1,F2 symbol to SP04301P120(F_SMD1812P110TF) Page 36,38 C789,C788,C684 symbol update (have pin define) Page 31, U3 P/N change from SA00001RM00 to SA00003O900 1102: Page 7,8 C97,C675,C134,C136,C251,C268,C541,C667 symbol update from SGA00002380 to SGA00002U00 Page 23 Add C609 0.1u_0402(SE076104K80) R739 24K_0402(SD034240280) fix +3VSDGPU Ramp up issue Page 17,35 Add more USB trace to 3G/B connector from PCH USB20_P10 & USB20_N10 1103: Page 43 R200 change symbol from 22_0402_5% to 22_0603_5% Page 39 SW1,SW4 BOM structure change to @ Page 36 C789.2 power source +3VS change to +3VALW 1104: Page 8, Add C797,C798,C799,C800 0.1u_0402 at between +1.5V&+1.5V_1(Intel suggest) Page 15,37 U41.F3 modify net from GPIO62 to susclk Page 37 Add R740(@) close U32.123 1105: Page R98 change from 4.7K_0402_5% to 330ohm_0402_5% (Intel feekback VGFX_CORE issue solution) 1109: Page 23 Change R717,R718,R720,R509 BOM structure from VGA@ to @ (Madison&Park prodution remove JTAG option2) Page 24 Change R64 BOM structure from @ to VGA@ (Madison&Park prodution remove JTAG option2) Page 23 Remove and short R729 (A2VDD) Page 23 Change C600,C172,C599 BOM structure from VGA@ to @ (+A2VDD) Page 23 Remove and short L6 (+A2VDDQ) Page 26 Remove and short R730,R731,R732,R733,R734,R735,R736,R737,R738, (DPB,DPC,DPD power source) Page 37 Add R508 100K_0402 Pull down to GND(EC E51TXD_P80DATA)(fix Intel WLAN Card reset issue) RF request: Page 35 Add C801 (SE071470J80 47P_0402) and C173(SE000005T80 10U_0603)(+3VS_WWAN) Page 23 Remove R508 (100_0402) change to C802(@) (12P_0402_50V8J)(SE071120J80) (VGA_CLK_27M) Page 29 Add two shunt C804,C803 12P_0402_50V8J(SE071120J80)(P31.DDC to HDMI conn) Page 29 Add two shunt C805,C806 22P_0402_50V8J(SE071220J80)(P29.LCD Conn) pop R403(47_0402) and C516 (22P_0402)(CLK_PCI_LPC) pop R163 (10_0402)and C319 (10P_0402) (CLK_BUF_ICH_14M) EMI request: Page 36 POP D26, CM1293-04SO(SC300000O00) Page 38,40,41 POP D18,D19,D10,D9,D11,D28,D30 PJDLC05C(SCA00001100) 1110: Page 38 Add Q53(ACIN_LED#) 1111: Page 40 C775,C776,C777,C778 change Symbol from SE093475K80(4.7U_0805) to SE107475M80(4.7U_0603) Page 38 R341,R343 100_0402_5% change to 680_0402_5%(BLUE LED Bright) Page 38 R342,R344 300_0402_5% change to 3.9K_0402_5%(Orange LED Bright) 1113: Page R98 change from 330_0402_5% to 470_0402_5%(SD028470080) Page 23 Change back R717,R718,R720,R509 BOM structure from @ to VGA@ (Madison&Park prodution remove JTAG option2) Page 24 Change back R64 BOM structure from VGA@ to @ (Madison&Park prodution remove JTAG option2) 1116: Page 13 U41 change P/N from SA00003N700 to SA00003N7B0 Page 34 T16 change P/N from SP050006C00 to SP050006B00 1117: Page 58 Add HW PIR 1211: ADD C807,C808 1000P_0402(SE074102K80) LAN EMI ADD C610 0.1U_0402 Y5V(SE070104Z80) VGFX_CORE EMI ADD C809 C810 0.1U_0402 Y5V(SE070104Z80) +1.5V EMI 1211B: Add U32.36 WLAN_LED# (output) Add U32.91 3G_LED# (output) Add U32.85 WWAN_LED# (input) 1214: ADD R735 For U24 power source +3VS (POP) ADD R736 For U24 power source +5VS (@) 1215: ADD R737 asmedia CLKADD R738 asmedia CLK+ U24 PN change to SA00000U500 (74AHC1G125GW_SOT353-5) 1216: C465 change BOM structure to @(3G 150U) R41 change BOM structure to @(CRT DET) Q20 change BOM structure to @(CRT DET) R343,R341 change to 2.2K_0402_5%(SD028220180) (LED) R334 change to 249K_0402_1%(SD034249380) 1217: R253 2.2K_0402_5% change to @ R252 2.2K_0402_5% change to UMAHD@ R343 change to 2.2K_0402_5%(7080@) 680_0402_5%(90@) R344 change to 3.9K_0402_5%(7080@) 680_0402_5%(90@) R341 change to 2.2K_0402_5%(7080@) 680_0402_5%(90@) R342 change to 3.9K_0402_5%(7080@) 680_0402_5%(90@) 1219: R382 change to 18K_0402(SD028180280)(Board ID) R389 ADD 100K_0402_5%(SD028100380) PH +3VALW(Board ID) 1223: R157 change to R167 10K_0402_5% (GPIO66: L:6L H:8L) GPIO21 define to Project ID (L:NEW50/70/80/90 H:NEW71/91) 1228: MB PCB P/N (DA80000H700)change to (DAZ0C900100) Q5,Q9,Q16,Q19,Q21,Q22,Q26,Q27,Q35,Q40,Q47,Q54 change SB00000AR10 to SB00000D900 DEL D10 (Int MIC ESD Diode PASS Can remove) R382 change to 18K_0402_5%(SD028180280 Board ID rev0.3) DEL R667,R668(SD028000080) USb common mode choke DEL R167,(SD028100280)(GPIO66 PH 8L,PD 6L) 10K_0402_5% ADD R157 (SD028100280)(GPIO66 PH 8L,PD 6L) 10K_0402_5% ADD R389 (SD028100380)(Board ID)100K_0402_5% ADD L68(SM070001600 12ohm bead) USB common mode choke Modify U24 Symbol MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC B 0104: ADD R350 100K_0402_5%(SD028100380)(3G PH +3VS_WWAN) 0107: Q5,Q9,Q16,Q19,Q21,Q22,Q26,Q27,Q35,Q40,Q47,Q54 change SB00000D900 to SB00000DH00 1209: R679 change BOM structure to @ D13,D15 change BOM structure to @ Change R717,R718,R720,R509 BOM structure from VGA@ to @ (Madison&Park prodution remove JTAG option2) Change R64 BOM structure from @ to VGA@ (Madison&Park prodution remove JTAG option2) Add R729 0_0402(SD028000080,@) Add R730 0_0402(SD028000080,@) LOCAL_DIM for Panel new feature Add R731 0_0402(SD028000080,@) COLOR_ENG_EN for Panel new feature Add R732 100K_0402(SD028100380)LOCAL_DIM PD to GND Add R733 100K_0402(SD028100380)COLOR_ENG_EN PD to GND Q53 change BOM structure to @ ADD Q54 2N7002DWH_SOT363-6(SB00000AR10) for AC PLUG HDD LED flash issue DEL U16 for AC PLUG HDD LED flash issue C97,C134,C136,C251,C541,C268,C675,C667 symbol update from SGA00002U00 to SGA00001Q80 C775,C776,C777,C778 change P/N SE107475M80 to SE107475K80(4.7U_0603_6.3V6K) Security Classification Compal Secret Data R272(100K PU +3VS) change BOM structure to @ 2007/09/20 2010/08/01 Issued Date Deciphered Date Add U32.85 WWAN_LED# (input) THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Add U32.17 MINI1_LED# (input) AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D ADD R734 PD to GND (fix CPT Panel Flash issue) DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C C > MP Change List B > C Change List A D A Compal Electronics, Inc Title PIR (HW) Size Document Number Custom Rev 1.0 NEW70 M/B LA-5891P Schematic Date: Friday, January 08, 2010 Sheet 58 of 59 A B C CRT Option Components D E NEW90 LED Option 5090@1 R343 680_0402_5% C607 C592 1 C567 1 5090@1 R344 680_0402_5% DIS@2 DIS@2 15P_0402_50V8J 15P_0402_50V8J 15P_0402_50V8J 5090@1 R341 680_0402_5% C603 5090@1 R342 680_0402_5% DIS@2 C593 C569 1 DIS@2 DIS@2 DIS@2 12P_0402_50V8J 12P_0402_50V8J 12P_0402_50V8J 15P_0402_50V8J: SE071150J80 12P_0402_50V8J: SE071120J80 VGA U34 L47 DIS@ 0_0805_5% L40 DIS@ 0_0805_5% L38 DIS@ 0_0805_5% PARK XT M2 A11: SA00003MC10 PARK@ 216-0774007 A11 PARK XT M2 PCH SKU Option 2 0_0805_5%: SD002000080 R259 10K_0402_5% UMAO@ GPIO19 PCB ZZZ LA-5891P MB Rev0: DA80000H700 LA-5891P MB Rev1: DA80000H710 LA-5891P MB with Small Board Rev1: DAZ0C900100 LA-5891P REV1 M/B X76 ZZZ X761@ X76198BOL01 VRAM 512M SAM NEW70 Samsung : SA000035700 (S IC D3 64MX16 K4W1G1646E-HC12 FBGA 96P) X76198BOL01 3 ZZZ X762@ X76198BOL02 VRAM 512M HYN NEW70 Hynix : SA000032400 (S IC D3 64MX16 H5TQ1G63BFR-12C FBGA 1.5V ) X76198BOL02 ZZZ X763@ X76198BOL03 VRAM 1G SAM NEW70 Samsung : SA000035700 (S IC D3 64MX16 K4W1G1646E-HC12 FBGA 96P) X76198BOL03 ZZZ X764@ X76198BOL04 VRAM 1G HYN NEW70 Hynix : SA000032400 (S IC D3 64MX16 H5TQ1G63BFR-12C FBGA 1.5V ) X76198BOL04 ZZZ X765@ X76198BOL05 X76198BOL05 VRAM 512M AMD NEW70 AMD :SA00003PF10 (S IC D3 64M16/800 23EY2387MB-12 PG-TFBGA 96P 1.5V) ZZZ X766@ X76198BOL06 A AMD :SA00003PF10 (S IC D3 64M16/800 23EY2387MB-12 PG-TFBGA 96P 1.5V) B Compal Electronics, Inc Compal Secret Data Security Classification X76198BOL06 VRAM 1G AMD NEW70 2008/08/10 Issued Date Deciphered Date 2010/08/01 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC C D Title Option Component Size Document Number Custom NEW70 M/B LA-5891P Schematic Date: Tuesday, December 29, 2009 Sheet E 59 of 59 Rev 1.0 ... 90 92 94 96 98 10 0 10 2 10 4 10 6 10 8 11 0 11 2 11 4 11 6 11 8 12 0 12 2 12 4 12 6 12 8 13 0 13 2 13 4 13 6 13 8 14 0 14 2 14 4 14 6 14 8 15 0 15 2 15 4 15 6 15 8 16 0 16 2 16 4 16 6 16 8 17 0 17 2 17 4 17 6 17 8 18 0 18 2 18 4 18 6 18 8... 81 83 85 87 89 91 93 95 97 99 10 1 10 3 10 5 10 7 10 9 11 1 11 3 11 5 11 7 11 9 12 1 12 3 12 5 12 7 12 9 13 1 13 3 13 5 13 7 13 9 14 1 14 3 14 5 14 7 14 9 15 1 15 3 15 5 15 7 15 9 16 1 16 3 16 5 16 7 16 9 17 1 17 3 17 5 17 7 17 9 18 1... DIS@ 0. 1U _04 02 _16 V7K 0. 1U _04 02 _16 V7K 0. 1U _04 02 _16 V7K 0. 1U _04 02 _16 V7K 0. 1U _04 02 _16 V7K 0. 1U _04 02 _16 V7K 0. 1U _04 02 _16 V7K 0. 1U _04 02 _16 V7K 0. 1U _04 02 _16 V7K 0. 1U _04 02 _16 V7K 0. 1U _04 02 _16 V7K 0. 1U _04 02 _16 V7K