Acer aspire 3 a315 56 compal FH5LI LA j801p rev 1 0 схема

A B C D E Compal Confidential FH5LI MB Schematic Document 2 LA-J801P 3 Rev:1.0 2019.10.30 4 Compal Secret Data Security Classification 2017/11/23 Issued Date Deciphered Date 2018/09/01 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Cover Sheet Size Document Number Custom FH5LI M/B Date: A B C D Compal Electronics, Inc Rev 1.0 LA-H801P W ednesday, October 30, 2019 Sheet E of 102 A B C D E eDP HDMI Conn Interleaved Memory DDR4-ON BOARD 4G 8Gbx16 page 40 page 24 Memory BUS page 38 Dual Channel DDI2 HDMI x lanes eDP 260pin DDR4-SO-DIMM X1 1.2V DDR4 2666/3200 page 23 DDI USB 3.0 USB 2.0 CMOS x2 conn x1 conn USB2 port3 (MB) Camera USB3 port Intel Ice Lake U USB2 port USB2 port4(SUB) USB2 port Processor Card Reader RTS5140 Reserved page 68 SATA Gen 6.0 Gb/s (SATA2) NGFF WLAN PCIe 1.0 2.5GT/s support CNVi port 10 USB2 port 10 page 52 PCIe 1.0 2.5GT/s port PCIE 3.0 x4 8GT/s Port 13-16 Flexible IO page 72 SATA Gen SATA Gen 6.0 Gb/s 1.5 Gb/s Ice Lake PCH-LP port (SATA1A) port (SATA0) LAN(GbE) SATA HDD Realtek 8111H Conn SATA ODD Conn page 51 RJ45 conn 15W 1526pin BGA ICL-U 4+2 page 06~19 eSPI BUS ENE KB9052 3.3V 24MHz HDA Codec ALC255page 56 page 11 Fan Control page page 63 DC/DC Interface CKT page 38 Int DMIC on Camera page 38 UAJ page 56 Touch Pad PS2 (from EC) / I2C (from SOC) 77 Int.KBD Power On/Off CKT USB2 port page 56 RTC CKT USB2 port Touch Screen Int Speaker page 58 USB2 port 8(SUB) Finger Printer SPI SPI ROM 128Mb page CLK=24MHz page 38 48MHz HD Audio 50x25 mm page 67 USBx8 page 71 USB2 port (FP) Sub Board LS-H781P IO/B page 63 page 63 page 73 page 78 Power Circuit DC/DC page 81~100 LS-H783P LID/B 2018/12/27 Issued Date page 63 Compal Electronics, Inc Compal Secret Data Security Classification Deciphered Date 2019/12/27 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title B C D Rev 1.0 FH5LI M/B LA-H801P Date: A Block Diagrams Size Document Number Custom Sheet Tuesday, October 15, 2019 E of 102 A B C D E Board ID Table for AD channel Vcc Ra 3.3V +/- 5% 100K +/- 1% Rb 12K +/- 1% 15K +/- 1% 20K +/- 1% 27K +/- 1% 33K +/- 1% 43K +/- 1% 56K +/- 1% Board ID 1 Power State V BID 0.347 0.423 0.541 0.691 0.807 0.978 1.169 V V V V V V V V V BID typ V 0.345 V 0.430 V 0.550 V 0.702 V 0.819 V 0.992 V 1.185 V V BID max 0.300 V 0.360 V 0.438 V 0.559 V 0.713 V 0.831 V 1.006 V 1.200 V EC 0x00 0x14 0x1F 0x26 0x31 0x3B 0x46 0x55 AD3 - 0x13 - 0x1E - 0x25 - 0x30 - 0x3A - 0x45 - 0x54 - 0x64 PCB Revision SIGNAL STATE 0.1(EVT) 1.0(PVT) 1.0(MP) SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS HIGH HIGH ON ON ON ON LOW HIGH HIGH ON ON OFF OFF LOW LOW HIGH ON OFF OFF OFF LOW LOW LOW ON OFF OFF OFF S0 (Full ON) HIGH S3 (Suspend to RAM) S4 (Suspend to Disk) S5 (Soft OFF) Clock Voltage Rails BOM Structure Table BOM Option Table Item Unpop Connector G Sensor CODEC For over cell battery For Intel CMC CNVi EMI/ESD requirement BOM select RF requirement TPM Finger Print Finger print power SATA/ODD select BOM Structure @ CONN@ GSEN@ 255@/256@ 3S@ CMC@ CNVI@ EMC@ / XEMC@ 15@ @RF@ TPM@ FP@/FPEMC@ FP3V@/FP5V@ RD@/NRD@/ODD@ MD BOM Select NOX76@/X76DSAM@/ X76DMIC@/X76DHYN@/ Memory related SPD@/DDP@/MEM@ MB Stage EVT@/DVT@/PVT@/MP@ Premium/Volume CPU PREM@/VOL@ i3@/i5@ DAZ PCB@ Power Plane Description +19V_VIN Adapter power supply S0 N/A S3 N/A S4/S5 N/A +12.6V_BATT Battery power supply N/A N/A N/A +19VB AC or battery power rail for power circuit N/A N/A N/A +VCCIN Core voltage for CPU ON OFF OFF +VCCIN_AUX CPU and PCH merged auxiliary power rail ON OFF OFF +0.6VS_VTT DDR +0.6VS power rail for DDR terminator ON OFF OFF +1.05VO_OUT_FET FIVR output of PCH to platform 1.05V Power Gates ON ON OFF +1.05V_VCCST Sustain voltage for CPU standby modes ON ON OFF +1.05VS_VCCSTG Gated sustain voltage for CPU standby modes ON OFF/ON OFF +1.2V_VDDQ DDR4 +1.2V Power Rail ON ON OFF +1.2V_VCCPLL_OC 1.2V power rail for CPU digital PLL ON ON OFF +1.8VALW_PRIM +1.8V Always power rail ON ON ON*1 +1.8VS System +1.8V power rail ON OFF OFF +3VLP +19VB to +3VLP power rail for suspend power ON ON ON +3VALW System +3VALW always on power rail ON ON ON*1 +3VALW_PRIM +3VALW power for PCH suspend rails ON ON ON*1 +3VS System +3V power rail ON OFF OFF +5VALW +5V Always power rail ON ON ON +5VS System +5V power rail ON OFF OFF +RTCVCC RTC Battery Power ON ON ON Note : ON*1 means power plane is ON only when WOL enable and RTC wake at BIOS setting, otherwise it is OFF ON*2 power plane is ON when DGPU turn on 43 level BOM table 43 Level Description 431ALBBOL01 SMT MB AJ801 FH5LI I31005D1 HDMI 431ALBBOL02 SMT MB AJ801 FH5LI I51035D1 HDMI BOM Structure 255@/3S@/MEM@/15@/VOL@/CNVI@/CMC@/SDP@/MP@/FP@/FP3V@/i3@/NRD@/PCB@ 255@/3S@/MEM@/15@/VOL@/CNVI@/CMC@/SDP@/MP@/FP@/FP3V@/i5@/NRD@/PCB@ 4 Compal Secret Data Security Classification Issued Date 2018/12/27 Deciphered Date 2019/12/27 Title Compal Electronics, Inc Notes List THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Rev 1.0 FH5LI M/B LA-H801P Date: A B C D Tuesday, October 15, 2019 Sheet E of 102 A B C JUMP (PJZ1) VR_ON RT3612EBGQW (PUZ1) +VCCIN JUMP (PJG1) 1.8VALW_PG RT6543AGQW (PUG1) +VCCIN_AUX D E VOL@ R-Short (RC3970) PREM@ ADAPTER SYSON JUMP (PJM3) +1.2VP SM_PG_CTRL RT8207PGQW (PUM1) JUMP (PJM4) +0.6VSP +19VB BATTERY SY8288CRAC (PU501) EC_ON +5VALWP JUMP (PJ501) +5VALW EM5201V (UC11) +1.2V_VDDQ +1.2V_VCCPLL_OC_P JUMP (JPC6) +1.2V_VCCPLL_OC +0.6VS_VTT SUSP# AOZ1331DI (UQ1) USB_EN +5VS_OUT SY6288C20AAC (US21) CHARGER (PU301) JUMP (JPQ2) +5VS JUMP (JPC10) +USB3_VCCB +TS_PWR AP2330W (UY1) +HDMI_5V_OUT ohm (RO3) +5VS_HDD ohm (RO26) +5VS_ODD JUMP (JPA1) +VDDA R-Short (RF1) +USB3_VCCA KBL_EN JLID1 (LID/B) LDO R-Short (RX8) +VCC_FAN1 SY6288C20AAC (U1) +5VS_BL JIO1 (IO/B) +3VLP SY8286BRAC (PU301) 3V_EN +3VALWP JUMP (PJ301) R-Short (RC173) +3VALW JUMP (JPC7) SYSON SOC_ENVDD +3VALW_DSW +3VALW_PRIM R-Short (LC2) R-Short (RC154) SY6288C20AAC (UX1) +3VALW_HDA +3V_PTP +3VALW_SPI ohm (RM9) +3VS_SSD_NGFF G9661MF11U (PUM2) +2.5VP LAN_PWR_EN SY6288C20AAC (UL1) +3V_LAN TP_PWR_EN SY6288C20AAC (UK1) +3V_PTP R-Short (RW2)@ +3VS_TPM WLAN_ON SY6288C20AAC (UM1) +3VS_WLAN R-Short (RA2) +3VS_DVDDIO R-Short (RA5) +3VS_DVDD FP_PWR_EN SUSP# SY6288C20AAC (UK6)FP@ +FP_VCC JEDP1 (CAMERA) R-Short (RW1) +3VALW_TPM JMIC1 (4DMIC) AOZ1331DI (UQ2) +3VS_OUT JUMP (JPQ1) +LCDVDD ohm (RK3)@ VOL@ +3VS R-Short (RC407) PREM@ EN_1.8VALW SY8032ABC (PU1801) +1.8VALWP JUMP (PJ1802) +1.8VALW_PRIM SUSP# EM5201V (UC12) G2898KD1U (UC14) +1.8V_PRIM_SOC_P +1.8VS R-Short (RA6) JUMP (JPC5) +1.8V_PRIM_SOC +1.8VS_VDDA PREM@ ICL-U FIVR (UC1) +1.05VO_OUT_FET (BY2,CB2,CC1) VCCST_EN_LS EM5201V (UC9) +1.05V_VCCST_SINGLE 0Ohm (RC3989) +1.05V_VCCST 0Ohm (RC414) VOL@ JUMP (JPC16) +1.05V_VCCST_P 0Ohm (RC413) PREM@ VCCSTG_EN_LS G2898KD1U (UC14) +1.05V_VCCST_DUAL 0Ohm (RC3981) +1.05VS_VCCSTG 4 HCB2012KF (LX1) 3S@ +INVPWR_B+ Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2018/12/27 Deciphered Date 2019/12/27 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title B C D Rev 1.0 FH5LI M/B LA-H801P Date: A Power Rail Size Document Number Custom Tuesday, October 15, 2019 E Sheet of 102 D D FH5LI_EVT Power Sequence AC mode BIOS ver: V0.01T015 EC: ver: V0.01T08B Plug in Power On Power Off S3 Resume S3 +19VB +19VB +3VLP +3VLP EC_ON +5VALW → EC_ON 209.9us +5VALW → 2.144ms ON/OFFBTN# ★ ON/OFFBTN# 3V_EN +3VALW SPOK_3V +1.8VALW_PRIM 1.8VALW_PG +VCCIN_AUX C VCC_AUX_PWRGD VCCIN_AUX_CORE_VID → → 98.52ms →567.3us → 702.5us → 644.6us → 279.6us → 779.9us → 314.7us → 2.383ms → ★ SLP_S4# 31.4ms → → → 11.52ms → 121.1ms → ←→ → 20ms → → PCH_PWROK EC_VCCST_EN +1.05V_VCCST EC_RSMRST# (DSW_PWROK) AC_PRESENT 9.59s 10.99us 9.301us PBTN_OUT# → → 28.04ms → SLP_S3# → → 1.25ms → C VCCST_OVERRIDE_LS 4.906ms 4.223ms 3.463us → 515.9us → → 20.26ms 20.28ms → → 122ms → → 20.16ms 20.18ms → 1.966ms → 319.3us 124.7ms +0.6VS_VTT EC_VCCST_PG_R VR_ON 105.7us +VCCIN 147.6us → → B SM_PG_CTRL 2.198us 120.9ms → +3VS +1.8VS 6.098us → 9.940ms +5VS 923us 392.9us → → 182.2us SUSP# 2.163ms 4.841us → 5.291us → 174.3us → +2.5V_VPP 402.6us → → → → 922.5us → → 20.19ms +1.2V_VDDQ 9.894us 763.3us → SYSON 1.006ms 1.563ms 693.9us 32.3us → 120.5ms → 1.170ms → 1.742us → → → → 4.772us → 9.98ms PLT_RST# 600.9us → → 1.964ms SYSPWROK → 8.698ms 4.599us 4.897us → 25.83ms 2.588ms → → → → 7.833us → 20.21ms → +0.6VS_VTT +VCCIN +VCCIN_AUX 13.7ms 811us 121.1us → 6.44ms +3VS VR_ON 1.8VALW_PG SLP_S4# → → 1.18ms → 741us EC_VCCST_PG_R → +1.8VALW_PRIM 23.76ms → 1.56ms +1.8VS 43.89us 3.976us → → 10.09ms +5VS SM_PG_CTRL → 1.118ms → → +2.5V_VPP B 43.75us → +1.2V_VDDQ SUSP# → 814.3us SLP_S3# SYSON SPOK_3V 38.59us → → +1.05V_VCCST +3VALW 683us → 4.565ms → 4.261ms EC_VCCST_EN PBTN_OUT# 3V_EN → VCCST_OVERRIDE_LS EC_RSMRST# (DSW_PWROK) AC_PRESENT 19.97us PCH_PWROK 155.5us SYSPWROK 348.8us PLT_RST# A A Compal Electronics, Inc Compal Secret Data Security Classification 2019/07/12 Issued Date Deciphered Date 2019/12/31 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: Power Sequence Document Number Rev 1.0 FH5LI M/B LA-H801P Tuesday, October 15, 2019 Sheet of 100 A B C D E 1 UC1A Y5 Y3 Y1 Y2 V2 V1 V3 V5 EDP_TXN0 EDP_TXP0 EDP_TXN1 EDP_TXP1 EDP_TXN2 EDP_TXP2 EDP_TXN3 EDP_TXP3 W4 W3 EDP_AUXN EDP_AUXP AE3 AE5 AE2 AE1 AC5 AC3 AC1 AC2 SOC_DP2_N0 SOC_DP2_P0 SOC_DP2_N1 SOC_DP2_P1 SOC_DP2_N2 SOC_DP2_P2 SOC_DP2_N3 SOC_DP2_P3 AD3 AD4 DP15 DJ17 HDMI DDC (Port 2) DL40 DP42 SOC_DP2_CTRL_CLK SOC_DP2_CTRL_DATA T302 TP@ T509 TP@ T510 TP@ T511 TP@ 1SOC_GPP_E19 DL17 DK17 1SOC_GPP_E21 DN17 DP17 1SOC_GPP_D10 DK34 DL34 CPU_EDP_HPD SOC_DP2_HPD 1SOC_GPP_A19 1SOC_GPP_A20 USB_OC1# USB_OC2# 1SOC_GPP_E17 T512 TP@ T303 TP@ T306 TP@ EDP_VDDEN: 100K PD on load swith side DN33 DL33 1SOC_GPP_D12 SOC_ENVDD ENBKL SOC_BKL_PW M DN21 DL19 DU19 J3 ENBKL RSVD_1 +3VALW _PRIM 10K_0402_5% 10K_0402_5% USB_OC1# USB_OC2# DDIA_AUX_N DDIA_AUX_P TCP0_AUX_N TCP0_AUX_P BB5 BB6 AV6 AV5 BH2 BH1 BF1 BF2 PCB DAZ ZZZ AY5 AY6 DDI DDIB_TXN_0 DDIB_TXP_0 DDIB_TXN_1 DDIB_TXP_1 DDIB_TXN_2 DDIB_TXP_2 DDIB_TXN_3 DDIB_TXP_3 TCP1_TX_N0 TCP1_TX_P0 TCP1_TX_N1 TCP1_TX_P1 TCP1_TXRX_N0 TCP1_TXRX_P0 TCP1_TXRX_N1 TCP1_TXRX_P1 DDIB_AUX_N DDIB_AUX_P TCP1_AUX_N TCP1_AUX_P GPP_E22/DDPA_CTRLCLK/PCIE_LNK_DOWN GPP_E23/DDPA_CTRLDATA/BK4/SBK4 AR5 AR6 AL5 AL3 BD2 BD1 BB1 BB2 PCB@ TCP2_TX_N0 TCP2_TX_P0 TCP2_TX_N1 TCP2_TX_P1 TCP2_TXRX_N0 TCP2_TXRX_P0 TCP2_TXRX_N1 TCP2_TXRX_P1 GPP_E18/DDP1_CTRLCLK/TBT_LSX0_TXD GPP_E19/DDP1_CTRLDATA/TBT_LSX0_RXD GPP_E20/DDP2_CTRLCLK/TBT_LSX1_TXD GPP_E21/DDP2_CTRLDATA/TBT_LSX1_RXD GPP_D9/ISH_SPI_CS_N/DDP3_CTRLCLK/GSPI2_CS0_N/TBT_LSX2_TXD GPP_D10/ISH_SPI_CLK/DDP3_CTRLDATA/GSPI2_CLK/TBT_LSX2_RXD GPP_D11/ISH_SPI_MISO/DDP4_CTRLCLK/GSPI2_MISO/TBT_LSX3_TXD GPP_D12/ISH_SPI_MOSI/DDP4_CTRLDATA/GSPI2_MOSI/TBT_LSX3_RXD GPP_E14/DPPE_HPDA/DISP_MISCA GPP_A18/DDSP_HPDB/DISP_MISCB GPP_A19/DDSP_HPD1/DISP_MISC1 GPP_A20/DDSP_HPD2/DISP_MISC2 GPP_A14/USB_OC1_N/DDSP_HPD3/DISP_MISC3 GPP_A15/USB_OC2_N/DDSP_HPD4/DISP_MISC4 GPP_E17 TCP2_AUX_N TCP2_AUX_P TCP3_TX_N0 TCP3_TX_P0 TCP3_TX_N1 TCP3_TX_P1 TCP3_TXRX_N0 TCP3_TXRX_P0 TCP3_TXRX_N1 TCP3_TXRX_P1 TCP3_AUX_N TCP3_AUX_P EDP_VDDEN EDP_BKLTEN EDP_BKLTCTL RSVD_1 TC_RCOMP_N TC_RCOMP_P GPP_A17/DISP_MISCC GPP_A21 GPP_A22 DISP_UTILS DISP_RCOMP DAZ2W V00100 PCB FH5LI LA-J801P LS-H781P/H783P AN3 AN5 Ice Lake-U CPU SKU i3-1005G1 i5-1035G1 TBT / USB / DP GPP_H16/DDPB_CTRLCLK GPP_H17/DDPB_CTRLDATA 1 D2 R2 TCP0_TX_N0 TCP0_TX_P0 TCP0_TX_N1 TCP0_TX_P1 TCP0_TXRX_N0 TCP0_TXRX_P0 TCP0_TXRX_N1 TCP0_TXRX_P1 BF6 BF5 BJ5 BJ6 BL1 BL2 BM2 BM1 UC1 UC1 ICL-U_BGA1526 S IC FJ8068904310007 SRGKF D1 1.2G FCBGA SA0000CVQ30 i3@ BG6 BG5 ICL-U_BGA1526 S IC FJ8068904368700 SRGKG D1 1G FCBGA SA0000CUQ20 i5@ BP6 BP5 BV5 BV6 BR1 BR2 BT2 BT1 BT6 BT5 AY1 AY2 TC_RCOMP_N TC_RCOMP_P CT38 CV43 CV41 TPM_PIRQ# TS_EN RC351 150_0402_1% TPM_PIRQ# TS_EN 0f 19 RC350 150_0402_1% ICL-U_BGA1526 @ RC164 RC165 1DISP_UTILS DISP_RCOMP T301 TP@ DW11 CV42 CV39 CY43 CR41 CT41 DV14 DDIA_TXN_0 DDIA_TXP_0 DDIA_TXN_1 DDIA_TXP_1 DDIA_TXN_2 DDIA_TXP_2 DDIA_TXN_3 DDIA_TXP_3 Reserve Test Point GPP_E19 TBT LSX #0 PINS VCCIO CONFIGURATION NO INTERNAL PU/PD RSVD_1: Follow 573129_ICL_U_DDR4_SODIMM_HW_SCH_RN HIGH: 3.3V LOW: 1.8V RC348 100K_0402_5% RSVD_1 RC422 100K_0402_5% ENBKL GPP_E21 TBT LSX #1 PINS VCCIO CONFIGURATION INTERNAL PD 20K HIGH: 3.3V LOW: 1.8V GPP_D10 TBT LSX #2 PINS VCCIO CONFIGURATION NO INTERNAL PU/PD HIGH: 3.3V LOW: 1.8V 2019/04/12 Issued Date HIGH: 3.3V LOW: 1.8V Compal Electronics, Inc Compal Secret Data Security Classification GPP_D12 TBT LSX #3 PINS VCCIO CONFIGURATION NO INTERNAL PU/PD Deciphered Date 2020/04/12 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Size B C D Rev 1.0 FH5LI M/B LA-H801P Date: A ICL-U(1/14)DDI,EDP Document Number Tuesday, October 15, 2019 Sheet E of 102 A B C D E +3VS EC_SCI#_R @ RC3984 10K_0402_5% +1.05VS_VCCSTG_OUT_LGC check XDP /DCI Reserve < PU/PD for CMC Debug > RC6 1K_0402_5% +3VALW _PRIM RC371 100K_0402_5% DC10 EC_SLP_S0IX# EC_SCI# EC_TP_INT# VCCIN_AUX_CORE_ALERT#_R J4 CD5 C3 E3 CATERR# H_PECI H_PROCHOT#_R H_THERMTRIP# H_PECI RC7 499_0402_1% CC1 EMC@ 100P_0201_50V8J H_PROCHOT# H_PROCHOT# EC_SLP_S0IX# 0_0402_5% 0_0402_5% @ PROC_POPIRCOMP PCH_OPIRCOMP CJ41 DU3 A14 B14 XDP_ITP_PMODE DL15 DV11 RC3991 EC_SCI#_R DT11 RC3963 TP_INT# CR38 CR39 H_PROCHOT# SOC_GPP_E6 SOC_GPP_H2 RB751V-40_SOD323-2 SCS00000Z00 DT12 DJ38 DL38 +3VALW _PRIM +1.05V_VCCST CATERR# PECI PROCHOT# THRMTRIP# PROC_TCK PROC_TDI PROC_TDO PROC_TMS PROC_TRST# PROC_POPIRCOMP PCH_OPIRCOMP JTAG RSVD_25 RSVD_26 DBG_PMODE GPP_E3/CPU_GP0 GPP_E7/CPU_GP1 GPP_B3/CPU_GP2 GPP_B4/CPU_GP3 PCH_TRST# PCH_TCK PCH_TDI PCH_TDO PCH_TMS PCH_JTAGX PROC_PRDY# PROC_PREQ# P3 K5 K3 P4 N1 SOC_XDP_TCK0 SOC_XDP_TDI SOC_XDP_TDO SOC_XDP_TMS SOC_XDP_TRST# SOC_XDP_TMS RC13 CMC@ 51_0402_5% SOC_XDP_TDI RC14 CMC@ 51_0402_5% SOC_XDP_TDO RC15 CMC@ 51_0402_5% N5 R5 K1 K2 N3 N2 SOC_XDP_TRST# PCH_JTAG_TCK1 SOC_XDP_TDI SOC_XDP_TDO SOC_XDP_TMS SOC_XDP_TCK0 XDP_PREQ# RC17 51_0402_5% SOC_XDP_TCK0 RC20 2 51_0402_5% P6 M6 XDP_PRDY# XDP_PREQ# PCH_JTAG_TCK1 RC22 @ 51_0402_5% SOC_XDP_TRST# RC21 @ 51_0402_5% @ CMC@ TP@ T497 TP@ T2 GPP_E6 GPP_H2/CNV_BT_I2S_SDO GPP_H19/TIME_SYNC0 of 19 ICL-U_BGA1526 @ RC3990 +1.05VS_VCCSTG_OUT_LGC UC1D EC_SLP_S0IX# 100K_0402_5% RC11 49.9_0402_1% CATERR# RC12 1K_0402_5% H_THERMTRIP# CC4 CC130 EMC@ 0.1U_0201_10V6K 0.1U_0201_10V6K H_PECI XEMC@ RC366 RC365 PROC_POPIRCOMP PCH_OPIRCOMP 49.9_0402_1% 49.9_0402_1% XDP_ITP_PMODE DFX TEST MODE INTERNAL PD 20K HIGH: DFX TEST MODE DISABLED(DEFAULT) LOW: DFX TES TMODE ENABLED SOC_GPP_E6 JTAG ODT DISABLE NO INTERNAL PU/PD HIGH: JTAG ODT ENABLED LOW: JTAG ODT DISABLED +3VALW _PRIM +3VALW _PRIM GPP_H2 MAF/SAF STRAP INTERNAL PD 20K HIGH: Slave Attached Flash Sharing (SAFS) is enabled LOW: Master Attached Flash Sharing (MAFS) is enabled (Default) +1.05VO_OUT_FET RC370 RC18 CMC@ 1K_0402_5% RC19 @ XDP_ITP_PMODE RC3965 @ 100K_0402_5% SOC_GPP_E6 RC389 @ 2.2K_0402_5% 100K_0402_5% RC3966 @ 2.2K_0402_5% SOC_GPP_H2 1K_0402_5% 4 Compal Electronics, Inc Compal Secret Data Security Classification 2019/04/12 Issued Date Deciphered Date 2020/04/12 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Size B C D Rev 1.0 FH5LI M/B LA-H801P Date: A ICL-U(1/14)DDI,MSIC,XDP Document Number Tuesday, October 15, 2019 Sheet E of 102 Follow Intel DDR4 NIL DDR4: Refer to 575034_ICL_U42_DDR4_T3_6L_Core_Schematics_Rev0p7 D D UC1B DDR_A_D[0 15] DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63 DDR_A_D[16 31] DDR_A_D[32 47] C DDR_A_D[48 63] 100_0402_1% 100_0402_1% 100_0402_1% 2 RC25 RC26 RC27 SM_RCOMP0 SM_RCOMP1 SM_RCOMP2 CA48 CA47 CA49 BV49 CA45 BV47 BV45 BV48 CC42 CC39 CC43 CE38 CC38 CE39 CE42 CE43 BT48 BT47 BT49 BN49 BT45 BN47 BN45 BN48 BV42 BV39 BV43 BW38 BV38 BW39 BW42 BW43 AY48 AY47 AY49 AU45 AY45 AU47 AU48 AU49 AY42 AY38 AY43 BB39 AY39 BB38 BB42 BB43 AR48 AR47 AR49 AM45 AR45 AM47 AM48 AM49 AT42 AT39 AR43 AT38 AR38 AR39 AR42 AT43 D47 E46 C47 LP4(NIL) / DDR4(NIL) LP4(NIL) / DDR4(NIL) DDRA_DQ0_0/DDR0_DQ0_0 DDRA_DQ0_1/DDR0_DQ0_1 DDRA_DQ0_2/DDR0_DQ0_2 DDRA_DQ0_3/DDR0_DQ0_3 DDRA_DQ0_4/DDR0_DQ0_4 DDRA_DQ0_5/DDR0_DQ0_5 DDRA_DQ0_6/DDR0_DQ0_6 DDRA_DQ0_7/DDR0_DQ0_7 DDRA_DQ1_0/DDR0_DQ1_0 DDRA_DQ1_1/DDR0_DQ1_1 DDRA_DQ1_2/DDR0_DQ1_2 DDRA_DQ1_3/DDR0_DQ1_3 DDRA_DQ1_4/DDR0_DQ1_4 DDRA_DQ1_5/DDR0_DQ1_5 DDRA_DQ1_6/DDR0_DQ1_6 DDRA_DQ1_7/DDR0_DQ1_7 DDRA_DQ2_0/DDR0_DQ2_0 DDRA_DQ2_1/DDR0_DQ2_1 DDRA_DQ2_2/DDR0_DQ2_2 DDRA_DQ2_3/DDR0_DQ2_3 DDRA_DQ2_4/DDR0_DQ2_4 DDRA_DQ2_5/DDR0_DQ2_5 DDRA_DQ2_6/DDR0_DQ2_6 DDRA_DQ2_7/DDR0_DQ2_7 DDRA_DQ3_0/DDR0_DQ3_0 DDRA_DQ3_1/DDR0_DQ3_1 DDRA_DQ3_2/DDR0_DQ3_2 DDRA_DQ3_3/DDR0_DQ3_3 DDRA_DQ3_4/DDR0_DQ3_4 DDRA_DQ3_5/DDR0_DQ3_5 DDRA_DQ3_6/DDR0_DQ3_6 DDRA_DQ3_7/DDR0_DQ3_7 DDRB_DQ0_0/DDR0_DQ4_0 DDRB_DQ0_1/DDR0_DQ4_1 DDRB_DQ0_2/DDR0_DQ4_2 DDRB_DQ0_3/DDR0_DQ4_3 DDRB_DQ0_4/DDR0_DQ4_4 DDRB_DQ0_5/DDR0_DQ4_5 DDRB_DQ0_6/DDR0_DQ4_6 DDRB_DQ0_7/DDR0_DQ4_7 DDRB_DQ1_0/DDR0_DQ5_0 DDRB_DQ1_1/DDR0_DQ5_1 DDRB_DQ1_2/DDR0_DQ5_2 DDRB_DQ1_3/DDR0_DQ5_3 DDRB_DQ1_4/DDR0_DQ5_4 DDRB_DQ1_5/DDR0_DQ5_5 DDRB_DQ1_6/DDR0_DQ5_6 DDRB_DQ1_7/DDR0_DQ5_7 DDRB_DQ2_0/DDR0_DQ6_0 DDRB_DQ2_1/DDR0_DQ6_1 DDRB_DQ2_2/DDR0_DQ6_2 DDRB_DQ2_3/DDR0_DQ6_3 DDRB_DQ2_4/DDR0_DQ6_4 DDRB_DQ2_5/DDR0_DQ6_5 DDRB_DQ2_6/DDR0_DQ6_6 DDRB_DQ2_7/DDR0_DQ6_7 DDRB_DQ3_0/DDR0_DQ7_0 DDRB_DQ3_1/DDR0_DQ7_1 DDRB_DQ3_2/DDR0_DQ7_2 DDRB_DQ3_3/DDR0_DQ7_3 DDRB_DQ3_4/DDR0_DQ7_4 DDRB_DQ3_5/DDR0_DQ7_5 DDRB_DQ3_6/DDR0_DQ7_6 DDRB_DQ3_7/DDR0_DQ7_7 DDR_RCOMP_0 DDR_RCOMP_1 DDR_RCOMP_2 DDRA_CLK_N/DDR0_CLK_N_0 DDRA_CLK_P/DDR0_CLK_P_0 DDRB_CLK_N/DDR0_CLK_N_1 DDRB_CLK_P/DDR0_CLK_P_1 DDRA_CKE0/DDR0_CKE0 DDRA_CKE1/NC DDRB_CKE0/NC DDRB_CKE1/DDR0_CKE1 DDRA_CS_0/DDR0_CS#0 DDRA_CS_1/NC DDRB_CS_0/NC DDRB_CS_1/DDR0_CS#1 DDRB_CA4/DDR0_BA0 NC/DDR0_BA1 DDRA_CA5/DDR0_BG0 NC/DDR0_BG1 NC/DDR0_MA0 NC/DDR0_MA1 DDRB_CA5/DDR0_MA2 NC/DDR0_MA3 NC/DDR0_MA4 DDRA_CA0/DDR0_MA5 DDRA_CA2/DDR0_MA6 DDRA_CA4/DDR0_MA7 DDRA_CA3/DDR0_MA8 DDRA_CA1/DDR0_MA9 NC/DDR0_MA10 NC/DDR0_MA11 NC/DDR0_MA12 DDRB_CA0/DDR0_MA13 DDRB_CA2/DDR0_MA14WE# DDRB_CA1/DDR0_MA15CAS# DDRB_CA3/DDR0_MA16RAS# NC/DDR0_ODT_0 NC/DDR0_ODT_1 DDRA_DQSN_0/DDR0_DQSN_0 DDRA_DQSP_0/DDR0_DQSP_0 DDRA_DQSN_1/DDR0_DQSN_1 DDRA_DQSP_1/DDR0_DQSP_1 DDRA_DQSN_2/DDR0_DQSN_2 DDRA_DQSP_2/DDR0_DQSP_2 DDRA_DQSN_3/DDR0_DQSN_3 DDRA_DQSP_3/DDR0_DQSP_3 DDRB_DQSN_0/DDR0_DQSN_4 DDRB_DQSP_0/DDR0_DQSP_4 DDRB_DQSN_1/DDR0_DQSN_5 DDRB_DQSP_1/DDR0_DQSP_5 DDRB_DQSN_2/DDR0_DQSN_6 DDRB_DQSP_2/DDR0_DQSP_6 DDRB_DQSN_3/DDR0_DQSN_7 DDRB_DQSP_3/DDR0_DQSP_7 NC/DDR0_PAR NC/DDR0_ACT# NC/DDR0_ALERT# RSVD_73 DDR0_VREF_CA DDR1_VREF_CA DDR_VTT_CTL DRAM_RESET# of 19 UC1C BL48 BL47 BF42 BF43 BG49 BJ47 BF38 BF41 BM38 BM42 BP42 BG42 BM43 BG39 BB49 BD47 BB48 BL49 BG38 BL45 BJ46 BG48 BE45 BG45 BG47 BE47 BJ38 BB47 BE48 BM39 BG43 BJ42 BM41 BJ39 BB45 BY47 BY46 CC41 CE41 BR47 BR46 BV41 BW41 AV46 AV47 AY41 BB41 AN46 AN47 AR41 AT41 DDR_A_CKE0 DDR_A_CKE1 DDR_A_CS#0 DDR_A_CS#1 DDR_A_BA0 DDR_A_BA1 DDR_A_BG0 DDR_A_BG1 DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15 DDR_A_MA16 DDR_A_ODT0 DDR_A_ODT1 DDR_A_DQS#0 DDR_A_DQS0 DDR_A_DQS#1 DDR_A_DQS1 DDR_A_DQS#2 DDR_A_DQS2 DDR_A_DQS#3 DDR_A_DQS3 DDR_A_DQS#4 DDR_A_DQS4 DDR_A_DQS#5 DDR_A_DQS5 DDR_A_DQS#6 DDR_A_DQS6 DDR_A_DQS#7 DDR_A_DQS7 BF39 BE49 BD46 M38 C44 B45 M39 DK47 DDR_A_CLK#0 DDR_A_CLK0 DDR_A_CLK#1 DDR_A_CLK1 DDR_B_D[0 15] DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63 DDR_B_D[16 31] DDR_B_D[32 47] DDR_B_D[48 63] DDR_A_PAR DDR_A_ACT# DDR_A_ALERT# DDR_PG_CTRL DDR_DRAMRST# TP@ T244 +0.6V_A_VREFCA +0.6V_B_VREFCA Trace width/Spacing >= 20mils DDR_DRAMRST# AK48 AK45 AK49 AG47 AK47 AG45 AG48 AG49 AJ38 AL39 AJ39 AL43 AL38 AJ42 AL42 AJ43 AB49 AB48 AE49 AE47 AE48 AB47 AB45 AE45 AD38 AD39 AE39 AE43 AE38 AD43 AD42 AE42 J48 J45 J49 G47 J47 G45 G48 E48 J38 G39 G38 G42 J39 J42 G43 J43 B43 D43 A43 C40 C43 D40 B40 A40 B35 D35 A35 D38 C35 C38 B38 A38 LP4(NIL) / DDR4(NIL) LP4(NIL) / DDR4(NIL) DDRC_DQ0_0/DDR1_DQ0_0 DDRC_DQ0_1/DDR1_DQ0_1 DDRC_DQ0_2/DDR1_DQ0_2 DDRC_DQ0_3/DDR1_DQ0_3 DDRC_DQ0_4/DDR1_DQ0_4 DDRC_DQ0_5/DDR1_DQ0_5 DDRC_DQ0_6/DDR1_DQ0_6 DDRC_DQ0_7/DDR1_DQ0_7 DDRC_DQ1_0/DDR1_DQ1_0 DDRC_DQ1_1/DDR1_DQ1_1 DDRC_DQ1_2/DDR1_DQ1_2 DDRC_DQ1_3/DDR1_DQ1_3 DDRC_DQ1_4/DDR1_DQ1_4 DDRC_DQ1_5/DDR1_DQ1_5 DDRC_DQ1_6/DDR1_DQ1_6 DDRC_DQ1_7/DDR1_DQ1_7 DDRC_DQ2_0/DDR1_DQ2_0 DDRC_DQ2_1/DDR1_DQ2_1 DDRC_DQ2_2/DDR1_DQ2_2 DDRC_DQ2_3/DDR1_DQ2_3 DDRC_DQ2_4/DDR1_DQ2_4 DDRC_DQ2_5/DDR1_DQ2_5 DDRC_DQ2_6/DDR1_DQ2_6 DDRC_DQ2_7/DDR1_DQ2_7 DDRC_DQ3_0/DDR1_DQ3_0 DDRC_DQ3_1/DDR1_DQ3_1 DDRC_DQ3_2/DDR1_DQ3_2 DDRC_DQ3_3/DDR1_DQ3_3 DDRC_DQ3_4/DDR1_DQ3_4 DDRC_DQ3_5/DDR1_DQ3_5 DDRC_DQ3_6/DDR1_DQ3_6 DDRC_DQ3_7/DDR1_DQ3_7 DDRD_DQ0_0/DDR1_DQ4_0 DDRD_DQ0_1/DDR1_DQ4_1 DDRD_DQ0_2/DDR1_DQ4_2 DDRD_DQ0_3/DDR1_DQ4_3 DDRD_DQ0_4/DDR1_DQ4_4 DDRD_DQ0_5/DDR1_DQ4_5 DDRD_DQ0_6/DDR1_DQ4_6 DDRD_DQ0_7/DDR1_DQ4_7 DDRD_DQ1_0/DDR1_DQ5_0 DDRD_DQ1_1/DDR1_DQ5_1 DDRD_DQ1_2/DDR1_DQ5_2 DDRD_DQ1_3/DDR1_DQ5_3 DDRD_DQ1_4/DDR1_DQ5_4 DDRD_DQ1_5/DDR1_DQ5_5 DDRD_DQ1_6/DDR1_DQ5_6 DDRD_DQ1_7/DDR1_DQ5_7 DDRD_DQ2_0/DDR1_DQ6_0 DDRD_DQ2_1/DDR1_DQ6_1 DDRD_DQ2_2/DDR1_DQ6_2 DDRD_DQ2_3/DDR1_DQ6_3 DDRD_DQ2_4/DDR1_DQ6_4 DDRD_DQ2_5/DDR1_DQ6_5 DDRD_DQ2_6/DDR1_DQ6_6 DDRD_DQ2_7/DDR1_DQ6_7 DDRD_DQ3_0/DDR1_DQ7_0 DDRD_DQ3_1/DDR1_DQ7_1 DDRD_DQ3_2/DDR1_DQ7_2 DDRD_DQ3_3/DDR1_DQ7_3 DDRD_DQ3_4/DDR1_DQ7_4 DDRD_DQ3_5/DDR1_DQ7_5 DDRD_DQ3_6/DDR1_DQ7_6 DDRD_DQ3_7/DDR1_DQ7_7 ICL-U_BGA1526 @ DDRC_CLK_N/DDR1_CLK_N_0 DDRC_CLK_P/DDR1_CLK_P_0 DDRD_CLK_N/DDR1_CLK_N_1 DDRD_CLK_P/DDR1_CLK_P_1 DDRC_CKE0/DDR1_CKE0 DDRC_CKE1/NC DDRD_CKE0/NC DDRD_CKE1/DDR1_CKE1 DDRC_CS_0/DDR1_CS#0 DDRC_CS_1/NC DDRD_CS_0/NC DDRD_CS_1/DDR1_CS#1 DDRD_CA4/DDR1_BA0 NC/DDR1_BA1 DDRC_CA5/DDR1_BG0 NC/DDR1_BG1 NC/DDR1_MA0 NC/DDR1_MA1 DDRD_CA5/DDR1_MA2 NC/DDR1_MA3 NC/DDR1_MA4 DDRC_CA0/DDR1_MA5 DDRC_CA2/DDR1_MA6 DDRC_CA4/DDR1_MA7 DDRC_CA3/DDR1_MA8 DDRC_CA1/DDR1_MA9 NC/DDR1_MA10 NC/DDR1_MA11 NC/DDR1_MA12 DDRD_CA0/DDR1_MA13 DDRD_CA2/DDR1_MA14WE# DDRD_CA1/DDR1_MA15CAS# DDRD_CA3/DDR1_MA16RAS# NC/DDR1_ODT_0 NC/DDR1_ODT_1 DDRC_DQSN_0/DDR1_DQSN_0 DDRC_DQSP_0/DDR1_DQSP_0 DDRC_DQSN_1/DDR1_DQSN_1 DDRC_DQSP_1/DDR1_DQSP_1 DDRC_DQSN_2/DDR1_DQSN_2 DDRC_DQSP_2/DDR1_DQSP_2 DDRC_DQSN_3/DDR1_DQSN_3 DDRC_DQSP_3/DDR1_DQSP_3 DDRD_DQSN_0/DDR1_DQSN_4 DDRD_DQSP_0/DDR1_DQSP_4 DDRD_DQSN_1/DDR1_DQSN_5 DDRD_DQSP_1/DDR1_DQSP_5 DDRD_DQSN_2/DDR1_DQSN_6 DDRD_DQSP_2/DDR1_DQSP_6 DDRD_DQSN_3/DDR1_DQSN_7 DDRD_DQSP_3/DDR1_DQSP_7 NC/DDR1_PAR NC/DDR1_ACT# NC/DDR1_ALERT# Y48 Y47 M43 M42 DDR_B_CLK#1 DDR_B_CLK1 U45 V46 M41 P43 DDR_B_CKE1 V42 V39 Y39 T39 DDR_B_CS#1 DDR_B_CLK#0 DDR_B_CLK0 TP@ T3 TP@ T4 DDR_B_CKE0 TP@ T504 DDR_B_CS#0 TP@ T498 T38 T42 DDR_B_BA0 DDR_B_BA1 R45 N47 DDR_B_ODT1 DDR_B_BG0 DDR_B_BG1 DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15 DDR_B_MA16 DDR_B_ODT0 TP@ T500 P42 Y49 U48 Y45 U47 R49 U49 M47 M45 R47 P39 N46 R48 Y41 V41 Y42 V47 V43 V38 AH46 AH47 AJ41 AL41 AC47 AC46 AE41 AD41 H47 H46 G41 J41 C42 D42 D36 C36 DDR_B_DQS#0 DDR_B_DQS0 DDR_B_DQS#1 DDR_B_DQS1 DDR_B_DQS#2 DDR_B_DQS2 DDR_B_DQS#3 DDR_B_DQS3 DDR_B_DQS#4 DDR_B_DQS4 DDR_B_DQS#5 DDR_B_DQS5 DDR_B_DQS#6 DDR_B_DQS6 DDR_B_DQS#7 DDR_B_DQS7 P38 M48 M49 C DDR_B_PAR DDR_B_ACT# DDR_B_ALERT# of 19 ICL-U_BGA1526 @ +1.2V_VDDQ B B RC30 470_0402_5% Buffer with Open Drain Output DDR_DRAMRST# For VTT power control +1.2V_VDDQ +3VS 0.1U_0201_10V6K UC3 VCC A Y RC28 100K_0402_5% CC9 100P_0402_50V8J EMC@ DDR_PG_CTRL NC SM_PG_CTRL ESD GND @ 74AUP1G07GW_TSSOP5 SA00005U600 1 CC6 RC16 1M_0402_5% SM_PG_CTRL to DDR VTT supplied ramped HDA_RST#_R RC3947 HDA_BIT_CLK_R RC46 EMC@ 33_0402_5% HDA_BIT_CLK HDA_SYNC_R RC48 33_0402_5% HDA_SYNC HDA_SDOUT_R RC47 33_0402_5% HDA_SDOUT RC3946 @ 33K_0402_5% HDA_SDIN1 Follow 572907_ICL_UY_PDG for Glitch 33_0402_5% HDA_RST# 100K_0402_5% HDA_BIT_CLK 33K_0402_5% HDA_RST# 1 RC49 499_0402_1% @ < To Enable ME Override > B B ME_EN RC51 0_0402_5% HDA_SDOUT A A Compal Electronics, Inc Compal Secret Data Security Classification 2019/04/12 Issued Date Deciphered Date 2020/04/12 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Size Rev 1.0 FH5LI M/B LA-H801P Date: ICL-U(4/12)HDA,SD Document Number Tuesday, October 15, 2019 Sheet 10 of 102 Module model information RT3612EB_2Phase_V1A.mdd for IC portion RT3612EB_2Phase_V1B.mdd for SW portion A A RT3612EBGQW-02 is not MP part +5VALW PUZ1 PRZ2 6.8_0603_1% 10 +19VB_VCCIN VCC VIN 22 VCC_RT3612 PCZ1 4.7U_0402_6.3V6M PRZ1 2.2_0603_1% PRZ3 VIN_RT3612 PCZ2 0.47U_0402_25V6K VRON 29 23 VRON_RT3612 PVCC PVCC_RT3612 PRZ5 75_0402_5% 0.6V VRHOT_RT3612 27 28 LX1_VCCIN LG1_VCCIN B UGATE2 21 PHASE2 SET2_RT3612 SET3_RT3612 32 UG2_VCCIN 31 LX2_VCCIN LG2_VCCIN TSEN LGATE2 220K_0402_5%_B25/50 4700K SET1_RT3612 BST2_VCCIN SET1 ISEN1P 30 20 PRZ16 2.61K_0603_1% PRZ17 ISENSE1P_VCCIN_R ISENSE1P_VCCIN_RR SET3 PRZ19 4.53K_0402_1% 19 ISENSE1N_VCCIN_R1 2 ISEN1N PCZ7 0.1U_0402_25V6 PRZ23 681_0402_1% ISEN2P PRZ27 ISENSE2P_VCCIN_RR 17 PRZ33 4.53K_0402_1% ISEN2N 18 ISENSE2N_VCCIN_R1 ISENSE1P_VCCIN ISENSE1N_VCCIN PRZ34 681_0402_1% 2.61K_0603_1% PRZ29 ISENSE2P_VCCIN_R 2.1K_0603_1% ISENSE2P_VCCIN ISENSE2N_VCCIN PCZ9 0.1U_0402_25V6 PCZ10 0.1U_0402_25V6 +VCCIN VCLK SVID_CLK_PWR_VCCIN 2.1K_0603_1% PCZ6 0.1U_0402_25V6 SET2 TSEN_RT3612 1 BOOT2 PRZ15 41.2K_0402_1% Close to Phase1 MOS PHZ1 TSEN_RT3612_R PRZ35 0_0402_5% CPU_SVID_CLK_R UG1_VCCIN PRZ10 8.2K_0402_1% LGATE1 VR_HOT# 110 degreeC ALERT# 107 degreeC PRZ22 24K_0402_1% PRZ14 1.74K_0402_1% VREF06 PRZ28 15K_0402_1% PRZ26 PRZ21 680_0402_1% 510_0402_1% 2 PRZ13 560_0402_1% PRZ8 16.9K_0402_1% PRZ9 750_0402_1% PRZ12 3.4K_0402_1% PRZ25 PRZ20 1.5K_0402_1% 15.8K_0402_1% 2 1 PRZ7 68.1K_0402_1% 1 PRZ11 62K_0402_1% 2 PRZ18 7.68K_0402_1% 2 PRZ32 45.3_0402_1% BST1_VCCIN 26 PCZ5 0.47U_0402_6.3V6K @ PRZ31 100_0402_1% 2 PRZ30 0_0402_5% 1 PCZ8 0.1U_0402_25V6 PRZ24 15K_0402_1% +1.05V_VCCST PHASE1 12 25 VR_HOT VREF06_RT3612 PRZ6 3.9_0402_1% B BOOT1 UGATE1 High: > 0.7V Low: < 0.3V VREF06_RT3612 PCZ4 4.7U_0402_6.3V6M VR_ON VR_HOT# PRZ4 0_0402_5% @ PCZ3 0.1U_0402_25V6 2 Pull High in HW site 2.2_0805_5% C CPU_SVID_ALERT#_R PRZ38 0_0402_5% SVID_ALERT#_PWR_VCCIN ALERT VSEN +3VS COMP PRZ40 10K_0402_1% 24 PRZ43 16.2K_0402_1% Close to Phase1 Inductor FB I_SYS LL/IMON Compesation PHZ2 PRZ46 100K_0402_1%_B25/50 4250K 22.6K_0402_1% VCCIN_NTC1P VCCIN_NTC1N 82P_0402_50V8J 16 FB_VCCIN 23.7K_0402_1% PRZ42 8.45K_0402_1% LL=2m PRZ44 PSYS 13 PCZ12 330P_0402_50V7K RGND_VCCIN 0_0402_5% VCC_SENSE_VCCIN @ PCZ13 330P_0402_50V7K @PCZ16 0.01UF_0402_25V7K VSS_SENSE_VCCIN IMON_VCCIN 11 IMON GND PRZ47 100_0402_1% 33 PRZ45 3.4K_0402_1% COMP_VCCIN PCZ11 PRZ41 RGND VREF06_RT3612 15 0_0402_5% PRZ39 VSEN_VCCIN VR_READY @ PCZ15 0.47U_0402_6.3V6K VR_PWRGD 14 C PRZ36 100_0402_1% VDIO @ PCZ14 0.082U_0402_16V7K CPU_SVID_DAT_R SVID_DAT_PWR_VCCIN PRZ37 0_0402_5% RT3612EBGQW-02_WQFN32_4X4 PRZ48 17.4K_0402_1% D D Compal Secret Data Security Classification Issued Date 2019/05/15 Deciphered Date 2020/05/15 Title Compal Electronics, Inc +VCORE(RT3612EB) THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: Tuesday, October 15, 2019 Sheet Rev 0.1 88 of 102 ICCMAX=54A TDC=25A OCP=160% of Iccmax=86.4A OVP=VID+0.35V=2.24V Frequency 600KHz @ D +19VB_VCCIN @ UG1_VCCIN LX1_VCCIN LX1_VCCIN D2/S1 @EMI@ PCZ47 @EMI@ PRZ50 680P_0402_50V7K 4.7_1206_5% SNUB1_VCCIN G2 S2 S2 S2 PCZ34 10U_0603_25V6M LG1_VCCIN C + D 2 PCZ21 + 33U_25V_NC_6.3X4.5 PCZ22 PLZ3 1 Rdc=0.98 mohm LX1_VCCIN +VCCIN AONY36352 2N DFN5X6D + 33U_25V_NC_6.3X4.5 PQZ1 G1 PCZ36 0.1U_0402_25V6 + +19VB PJZ1 1 JUMP_43X118 1 BST1_VCCIN_R D1 BST1_VCCIN PCZ20 10U_0603_25V6M PRZ49 2.2_0603_5% EMI@ PCZ33 2200P_0402_50V7K @EMI@ PCZ19 0.1U_0402_25V6 1 +VCCIN PCZ18 330U_D2_2.5VY_R9M PCZ17 330U_D2_2.5VY_R9M 0.22UH_24A_20%_ 7X7X4_M ISENSE1N_VCCIN ISENSE1P_VCCIN C +19VB_VCCIN LG2_VCCIN S2 G2 S2 AONY36352 2N DFN5X6D S2 D2/S1 PLZ4 @EMI@ PCZ59 @EMI@ PRZ52 680P_0402_50V7K 4.7_1206_5% 1SNUB2_VCCIN D1 LX2_VCCIN Rdc=0.98 mohm G1 PQZ2 B PCZ58 0.1U_0402_25V6 LX2_VCCIN PCZ57 10U_0603_25V6M BST2_VCCIN_R PCZ56 10U_0603_25V6M PRZ51 2.2_0603_5% BST2_VCCIN B EMI@ PCZ55 2200P_0402_50V7K @EMI@ PCZ54 0.1U_0402_25V6 UG2_VCCIN LX2_VCCIN +VCCIN 0.22UH_24A_20%_ 7X7X4_M ISENSE2N_VCCIN ISENSE2P_VCCIN A A Compal Secret Data Security Classification Issued Date 2019/05/15 Deciphered Date 2020/05/15 Title Compal Electronics, Inc Power stage-VCCIN THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: Rev 0.1 Tuesday, October 15, 2019 Sheet 89 of 102 Size A Date: Tuesday, October 15, 2019 Sheet 90 of PCZ65 12P_0402_50V8J PCZ35 22U_0603_6.3V6M PCZ32 22U_0603_6.3V6M PCZ31 22U_0603_6.3V6M PCZ30 22U_0603_6.3V6M PCZ29 22U_0603_6.3V6M PCZ28 22U_0603_6.3V6M PCZ27 22U_0603_6.3V6M PCZ26 22U_0603_6.3V6M PCZ25 22U_0603_6.3V6M 2 @RF@ PCZ64 12P_0402_50V8J @RF@ PCZ63 12P_0402_50V8J @RF@ PCZ62 12P_0402_50V8J C @RF@ PCZ61 12P_0402_50V8J PCZ46 22U_0603_6.3V6M PCZ45 22U_0603_6.3V6M PCZ44 22U_0603_6.3V6M PCZ43 22U_0603_6.3V6M PCZ42 22U_0603_6.3V6M 1 PCZ24 22U_0603_6.3V6M 2 @RF@ PCZ60 12P_0402_50V8J +VCCIN @RF@ PCZ53 1U_0201_6.3V6M PCZ41 22U_0603_6.3V6M PCZ40 22U_0603_6.3V6M PCZ39 22U_0603_6.3V6M PCZ38 22U_0603_6.3V6M @ PCZ52 1U_0201_6.3V6M 1 PCZ51 1U_0201_6.3V6M PCZ50 1U_0201_6.3V6M PCZ49 1U_0201_6.3V6M B PCZ48 1U_0201_6.3V6M 2 @ PCZ37 22U_0603_6.3V6M 2 +VCCIN D D 330U_R9 *1 22U_0603 *18 1U_0201 *6 C +VCCIN B A Title A Document Number Rev 102 A B C D E Module model information RT6543A_V1A.mdd for IC portion RT6543A_V1B.mdd for SW portion 1 +19VB AUX input cap need place 5pcs PRG2 0_0805_5% +19VB_AUX PCG1 0.1U_0402_25V6 PRG1 2.2_0603_5% 1 BST_AUX_R UG_AUX D1 VCC PH 12 14 LG_AUX VID1 ISENSEP ISENSEP_RT6543 PRG12 ISENSEP_RT6543_R VID0 ISENSEN ISENSEN_RT6543 ISENSEN_RT6543_R +VCCIN_AUX PCG11 @ PRG14 100K_0402_1% FSW SEL_RT6543 FSWSEL VOUT 10K_0402_1% PCG12 820P_0402_25V7 COMP_RT6543 PCG13 390P_0402_50V7K FB_RT6543 1 PRG24 PHG1 PRG25 0_0402_5% VCC_SENSE_VCCIN_AUX @ PCG18 1 +VCCIN_AUX *1 *13 + @ @RF@ PCG37 12P_0402_50V8J @RF@ PCG38 12P_0402_50V8J 1 PCG40 12P_0402_50V8J @RF@ @RF@ PCG39 12P_0402_50V8J @RF@ PCG41 12P_0402_50V8J 1 @RF@ PCG42 12P_0402_50V8J 2 +VCCIN_AUX PCG22 22U_0603_6.3V6M + PCG34 22U_0603_6.3V6M PCG21 22U_0603_6.3V6M +VCCIN_AUX PCG20 22U_0603_6.3V6M 1.8 0.01UF_0402_25V7K 330U_R9 22U_0603 PCG33 22U_0603_6.3V6M 1 PCG32 22U_0603_6.3V6M 1 1 1.65 @PCG19 1.1 330P_0402_50V7K 1 PCG31 330U 2.5V Y D2 LESR9M PCG15 0.1U_0402_25V6 PCG16 0.1U_0402_25V6 PCG30 330U 2.5V Y D2 LESR9M 0.082U_0402_16V7K @ PCG17 +VCCIN_AUX Voltage VID0 B=3435(B25/85) PRG29 100_0402_1% VCCIN_AUX VID Follow Intel PDG Rev0.71 10K_0402_1%_B25/50 3370K VSS_SENSE_VCCIN_AUX VID1 2 RGND 20K_0402_1% 1.5K_0402_1% ISENSEN_AUX_NTC 1.6K_0402_1% 2 21 @ PRG27 10K_0402_1% 100_0402_1% PRG22 FB PRG18 ISENSEP_RT6543_R PCG14 15P_0402_50V8J 5V: 800KHz Float: 600KHz GND: 400KHz PRG15 1 1.24K_0402_1% PRG21 AGND 1 PRG17 0_0402_5% 2 VCCIN_AUX_CORE_VID0_R VCCIN_AUX_CORE_VID1_R 1 2 PRG23 10K_0402_1% @ PRG26 10K_0402_1% PRG16 0.1U_0402_25V6 VOUT_RT6543 @ PRG19 100K_0402_1% COMP PRG20 10K_0402_1% 1 ISENSEN_RT6543_R +5VALW PCG29 22U_0603_6.3V6M VCCIN_AUX_CORE_VID0_R 18 VCCIN_AUX_CORE_VID0_R PCG28 22U_0603_6.3V6M PCG27 22U_0603_6.3V6M +3VALW 0_0402_5% PCG26 22U_0603_6.3V6M 17 PCG25 22U_0603_6.3V6M VCCIN_AUX_CORE_VID1_R VCCIN_AUX_CORE_VID1_R 0_0402_5% @ PRG10 PGND PRG11 EN PCG9 0.1U_0402_25V6 ISENSEN_AUX 0.22UH_24A_20%_ 7X7X4_M PCG24 22U_0603_6.3V6M 19 0_0402_5% AUX_SNUB EN_RT6543 2 VCC_AUX_PWRGD PRG9 PRG13 PRG8 8.87K_0603_1% 8.87K_0603_1% 1ISENSEP_AUX_R 1 G2 S2 13 @EMI@ PRG7 4.7_1206_5% LGATE AONY36352 2N DFN5X6D @EMI@ PCG10 680P_0402_50V7K PGOOD LG_AUX S2 VCC_AUX_PW RGD LX_AUX ISENSEP_AUX S2 PLG1 LX_AUX D2/S1 1U_0402_6.3V6K PRG6 100K_0402_1% +3VALW 16 PCG8 PCG23 22U_0603_6.3V6M VCC_RT6543 2 Rdc=0.98 mohm 0_0402_5% PQG3 UGATE 1 ICCMAX=31A TDC=14A DC LL=TBD AC LL=4.5 JUMP_43X118 G1 PVCC 15 PCG7 1U_0402_6.3V6K 5.1_0603_5% PRG4 1.8VALW_PG +VCCIN_AUX PVCC_RT6543 2 2 EMI@ PCG6 2200P_0402_50V7K 11 UG_AUX @EMI@ PCG5 0.1U_0402_25V6 VSYS_RT6543 PCG4 10U_0603_25V6M 20 +19VB PJG1 0_0603_5% High > 1V Low