Acer nitro AN517 52 compal FH51M LA j871p rev 1 0 схема

A B C D E 1 Compal Confidential 2 MB Schematic Document FH51M LA-J871P 3 Rev:1.0 2020.02.11 4 Compal Secret Data Security Classification 2019/09/20 Issued Date Deciphered Date 2020/09/20 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Cover Sheet Size Document Number Custom FH51M M/B Date: A B C D Compal Electronics, Inc Rev 1.0 LA-J871P Tuesday, February 11, 2020 Sheet E of 112 A B mDP - JDP1 C HDMI - JHDMI1 D eDP - JEDP1 DDI - VGA Port E - CPU eDP - VGA Port C N18P-G61/G62 P.39 P.40 E Interleaved (DDR4 2400/2666) Cof f eeLake H Pr ocess or BGA1440 (42X28) (CFL-H & CML-H _ 8+2) Memory BUS - DDR4 So-DIMM 260 pin - Channel A - BANK 0,1,2,3 - Address : 0XA0/1 P.23 P.38 - MAX-Q - GDDR6 4G PEG x16 8GT/s VBIOS ROM P.27-37 - SOP8 - Size : 1M P.29 LAN(GbE) JRJ45 USB3.1 - JUSB - PCIE 2.0 5GT/s - Port 14 - E2600 P.6-13 X4 DMI USB3.1 - JUSB USB3.1 - JUSB Type C - JTYPEC1 - GEN2 - On M/B - Port - W/USB Charger (SLGC55544) - GEN2 - USB3.1 Port - USB2.0 Port - GEN2 - USB3.1 Port - USB2.0 Port - DDR4 So-DIMM 260 pin - Channel B - BANK 4,5,6,7 - Address : 0XA3/4 P.24 - USB3.1 GEN2 - USB3.1 Port3&4 - RTS5441E P.71 USB3 Re-driver USB3 Re-driver - PS8713 - PS8713 P.42-43 SPI ROM 16M Cannonlake PCH - H FCBGA874 (25X24) SPI - SOP8 - Size : 16M P.16 CFL-H : HM370 CML-H : HM470 IO_B P.73 LPC/eSPI BUS P.14-21 HDD - JHDD1 SSD - JSSD3 (PCIE/SATA) SSD - JSSD2 (PCIE/SATA) SSD - JSSD1 (PCIE) TPM HD Audio - NPCT750 I2C P.66 - SATA 3.0 - Port 13 (SATA 0B) P.67 - PCIE 2.0 5GT/s - PCIE Port 17-20 - SATA @ Port 17 P.69 - PCIE 2.0 5GT/s - PCIE Port 9-12 - SATA @ Port 12 - PCIE 2.0 5GT/s - PCIE Port 21-24 EMR - JEMR1 P.68 P.68 Touch Pad EC KB9022 - PCH I2C0 P.64 - EC PS2 - PCH I2C1 P.58 P.63 I2C/PS2 WIFI - JNGFF1 DDC Camera Finger print Tuch Screen - USB2 Port - USB2 Port - PCH I2C2 Fan Control*2 page 77 - Port P.38 P.66 P.38 - PCIE1.0 2.5GT/s - USB2 Port P.52 - PCIE Port 15 RTC CKT (JRTC1) Int.KBD P.59 P.56 P.73 HS/B (JHS1) TURBO/B (JTURBO1) - I2C - KC3810 - ALC295 Sub Board IO/B (JIO1/JIO2) Extend IC HDA Codec - KSI/KSO - W/BL or Zone RGB P.66 P.63 Int Speaker P.77 Int DMIC Audio Jack P.20 Power On/Of f CKT HW Circuit DC/DC - ON IO/B > L - ON M/B > R P.63 - On IO/B - On CCD Module Issued Date Power Circuit DC/DC Compal Electronics, Inc Compal Secret Data Security Classification P.78 2019/09/20 Deciphered Date 2020/09/20 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC P.82-111 Title B C D R ev 1.0 FH51M M/B LA-J871P Date: A Block Diagrams Size Document Number Custom Tuesday, February 11, 2020 Sheet E of 112 A Vcc Ra Board ID 1 10 11 12 13 14 15 16 17 18 19 3.3V +/- 5% 100K +/- 1% Rb 12K +/- 1% 15K +/- 1% 20K +/- 1% 27K +/- 1% 33K +/- 1% 43K +/- 1% 56K +/- 1% 75K +/- 1% 100K +/- 1% 130K +/- 1% 160K +/- 1% 200K +/- 1% 240K +/- 1% 270K +/- 1% 330K +/- 1% 430K +/- 1% 560K +/- 1% 750K +/- 1% NC B EC Board ID Table for AD channel Vmin 0.347 0.423 0.541 0.691 0.807 0.978 1.169 1.398 1.634 1.849 2.015 2.185 2.316 2.395 2.521 2.667 2.791 2.905 3.000 I2C_0 (+3VS) I2C_1 (+3VS) PCH_SMBCLK (+3VS) PCH_SML1CLK (+3VALW) EC_SMB_CK2 (+3VS) EC_SMB_CK1 (+3VLP) EC_SMB_CK3 (+3VALW) V V V V V V V V V V V V V V V V V V V Vtyp 0.000 0.345 0.430 0.550 0.702 0.819 0.992 1.185 1.414 1.650 1.865 2.031 2.200 2.329 2.408 2.533 2.677 2.800 2.912 3.000 V V V V V V V V V V V V V V V V V V V V Vmax 0.300 V 0.360 V 0.438 V 0.559 V 0.713 V 0.831 V 1.006 V 1.200 V 1.430 V 1.667 V 1.881 V 2.046 V 2.215 V 2.343 V 2.421 V 2.544 V 2.687 V 2.808 V 2.919 V EC AD 0x00 - 0x13 0x14 - 0x1E 0x1F - 0x25 0x26 - 0x30 0x31 - 0x3A 0x3B - 0x45 0x46 - 0x54 0x55 - 0x64 0x65 - 0x76 0x77 - 0x87 0x88 - 0x96 0x97 - 0xA4 0xA5 - 0xAF 0xB0 - 0xB7 0xB8 - 0xBF 0xC0 - 0xC9 0xCA - 0xD4 0xD5 - 0xDD 0xDE - 0xF0 0xF1 - 0xFF Device BUS C D *PCB Version *Key board type Board ID 10 11 12 13 14 15 16 17 18 19 SD034120280 SD034150280 SD034200280 SD034270280 SD034330280 SD034430280 SD034560280 SD034750280 SD034100380 SD034130380 SD034160380 SD034200380 SD000001B80 SD00000G280 SD034330380 SD00000WM80 SD034560380 SD00000AL80 STATE PCB Revision 50 Rev0.1 50 Rev0.2 50 Rev0.3 50 Rev1.0 50 Rev0.2+RGB 50 Rev0.3+RGB 50 Rev1.0+RGB 60 Rev0.1 60 Rev0.2 60 Rev0.3 60 Rev1.0 60 Rev0.2+RGB 60 Rev0.3+RGB 60 Rev1.0+RGB Address(8bit) Address(7 bit) Write Read XXXXXX (EMR) TM-P3393-003 (Touch Pad) DIMM1 DIMM2 N18P-G0/N17P-G0-K1 (VGA) Thermal Sensor (NCT7718W) Thermal Sensor (G781) PCH BQ24780 (Charger IC) BATTERY PACK 0x9E 1001_100xb 1001_101xb 0x90 0x12 0x16 LED driver 0xC0 KC3810 0xC0 Item (X43 / X76) Unpop Connector PCB UMA Only(Reserved) H62 CPU(Reserved) H82 CPU(POP) CFL i5QS CPU CFL i5 CPU CFL QS PCH BOM Structure @ CONN@ PCB@ V UMA@ H62@ H82@ V CFLi5QS@ CFLi5@ CFLPCHQS@ CML i5QS CPU CML i7QS CPU CML i9QS CPU CML QS PCH CML i5 CPU CML i7 CPU CML i9 CPU CML PCH CMLi5QS@ CMLi7QS@ CMLi9QS@ dGPU circuit N17P GPU N18P GPU N18P-G61 N18P-G62 MP2 VGA@ N17P@ N18P@ VGAG61@ VGAG62@ CMLi5@ CMLi7@ CMLPCH@ V Item (X43 / X76) eDP-TS USB eDP-TS USB eDP-TS I2C mDP For Acer IOAC No Acer IOAC Intel CNVi FOR UART BT module FOR UART debug Extend GPIO BOM Structure TS_USB@ NONTS_I2C@ V TS_I2C@ DP@ V IOAC@ V NIOAC@ CNVI@ V UART_BT@ UART@ KC3810@ Finger Print FinerPrint(with PBA) FP@ V PBA@ V Remove KBLED@ LED14P@ WC18V@ WC33V@ TMS@ V TPM@ NTPM@ V SSD3@ KB LED driver EMR 1.8V EMR 3.3V Thermal sensor TPM pop TPM non-pop SSD3 pop 1001_1001b 1001_1011b 1001_1000b 1001_1010b Descript i on 43 Level +VALW +V +VS HIGH HIGH ON ON ON LOW HIGH HIGH ON ON OFF LOW LOW HIGH ON OFF OFF LOW LOW LOW ON OFF OFF HIGH S3 (Suspend to RAM) S4 (Suspend to Disk) S5 (Soft OFF) Power Plane Description S0 S3 S4 S5 +RTCVCC RTC Battery Power ON ON ON ON +19V_VIN Adapter power supply N/A N/A N/A N/A +12.6V_BATT Battery power supply N/A N/A N/A N/A +19VB AC or battery power rail for power circuit N/A N/A N/A N/A +3VLP +19VB to +3VLP power rail for suspend power ON ON ON ON +5VALW +5V Always power rail ON ON ON ON +3VALW System +3VALW always on power rail ON ON ON ON* +3VALW_DSW +3VALW power for PCH DSW rails ON ON ON ON +1.05VALW +1.05V Always power rail ON ON ON ON +1.2V_VDDQ DDR4 +1.2V power rail ON ON OFF OFF OFF +1.05V_VCCST Sustain voltage for processor in Standby modes ON ON OFF +5VS System +5V power rail ON OFF OFF OFF +3VS System +3V power rail ON OFF OFF OFF +1.05VS_VCCSTG +1.05VALW_PRIM Gated version of VCCST ON OFF OFF OFF +0.6VS_VTT DDR +0.6VS power rail for DDR terminator ON OFF OFF OFF +VCC_CORE Core voltage for CPU ON OFF OFF OFF +VCC_GT Sliced graphics power rail ON OFF OFF OFF +VCCIO CPU IO +0.95VS power rail ON OFF OFF OFF +VCC_SA System Agent power rail ON OFF OFF OFF +1.8VSDGPU_AON +1.8VS power rail for GPU(AON rails) ON OFF OFF OFF +1.8VSDGPU_MAIN +1.8VS power rail for GPU GC6 ON OFF OFF OFF +NVVDD1 Core voltage for VGA (merge core & core_s) ON OFF OFF OFF +1.35VSDGPU +1.35VS power rail for GPU ON OFF OFF OFF +1.0VSDGPU +1.0VS power rail for GPU ON OFF OFF OFF +1.8VALW System +1.8VALW always on power rail ON ON ON ON* 431AMBBOL02 Item (X4E) EMI requirement EMI require reserve ESD requirement ESD require reserve FP ESD requirement BOM Structure EMI@ V XEMI@ ESD@ V XESD@ FPESD@ V Item (X76) OVRM-uPI OVRM-ON VRAM-SAMSUNG VRAM-MICRON Issued Date B PCB@/H82@/SATANRD@/CMLi5@/CMLPCH@/VGA@/N18P@/VGAG61@/TS_USB@/NONTS_I2C@/DP@/IOAC@/CNVI@/FP@/PBA@/KBLED@/LED14P@/WC18V@/TMS/@TPM@ FH51M PG61QS 4G BOM Structure uPI_X76@ ON_X76@ X76SAM@ X76MIC@ X4EAMBBOL01 X4EP4MBOL01 PG6162 FOR EE PG6162 IO FOR EE X76869BOL01 X76869BOL02 X76869BOL03 X76869BOL04 - MICRON SAMSUNG ON OVRM UPI OVRM Compal Secret Data 2019/09/20 Deciphered Date 2020/09/20 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title C D Compal Electronics, Inc Notes List Size Document Number Custom R ev 1.0 FH51M M/B LA-J871P Date: A BOM Structure Security Classification PVT@ PVTRGB@ SLP_S3# SLP_S4# SLP_S5# S0 (Full ON) Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF V PVT PVT W/RGB E SIGNAL Tuesday, February 11, 2020 Sheet E of 112 DC_IN PL101,2,3 PJP101 +19V_VIN AC CONN +2.5VP +12.6V_BATT+ +12.6V_BATT PU2501 BATTERY PL201,2 PU1002 DDR4 Conn JDIMM2 +1.0VSDGPUP PJP201 JDIMM1 +2.5V PJ2502 +1.0VSDGPU GPU PJ1003 IMVP8 D PUZ2,3,4,5 D +19VB_CPU PLZ1,2,3,4 +19VB PUB1 +VCC_CORE CPU UQ1 +3VS JPQ1 EN:DRVON +3VALW_TPM R19 +19VB_CPU CHARGER +19VB PRG5 +VCC_GT PLG1 CPU UM1 +3VS_WLAN UL1 +3V_LAN U5 JNGFF1 UL2 +19VB_CPU +3V_PTP UM2 RM54 +3VS_SSD1 +3VSDGPU RM11 +3VS_WLAN JNGFF1 WLAN CARD Conn R20 +3VS_TPM U5 TPM UX1 +LCDVDD LAN JTP1 TP Conn JSSD1 SSD Conn SATA Re-driver GPU JEDP1 +3VS_DVDDIO PRA3 +VCC_SA PLA1 CPU UM2 RM55 +3VS_SSD2 JSSD2 SSD Conn +3VS_DVDD EN:DRVON RA4 RH101 +3VALW_HDA PCH RH99 +3VALW_DSW PCH UK2 +FP_VCC +3VALWP EN:3V_EN +3VALW PJ302 PU301 EC,LID C +3VLP +1.2VP PJM2 JFP1 +1.2V_VDDQ +1.2V_VCCPLL_OC RC24 CODEC FP Conn JPH1 +1.05VALW_PRIM PCH RH94 +1.05VALW_PCH PCH CPU +19VB EN:SM_PG_CTRL RH102 +0.6VSP RH103 PJM3 PANEL CODEC C CPU,Memory EN:SYSON PUM1 UV45 RA2 +19VB +19VB +3VS WLAN CARD Conn EN:DRVON UK1 UO1 TPM +0.6VS_VTT RH105 +1.05VALW_VCCAZPLL +1.05VALW_VCCAMPHYPLL +1.05VALW_XTAL PCH +1.05VALWP PU1101 PJ1101 +19VB UQ2 +1.05VALW RQ5 EN:+1.8_PG +1.05V_VCCST CPU +1.05VS_VCCSTG UC4 EN:DGPU_PWR_EN +1.0VS_VCCIOP +19VB PUH1 PJH1 +1.8VSDGPU_AON CPU +VCCIO EN:SUSP# B GPU UG27 UQ2 +1.8VALWP +19VB +FP_FUSE_GPU UV48 GPU +1.8VSDGPU_MAIN PU1801 PJ1801 +1.8VALW RH100 RQ9 +1.8VS +1.8VALW _PRIM +1.8VS_VDDA RA3 CODEC B PCH EN:SPOK_3V PU501 +5VALWP PJ502 +19VB PUV1 CC logic/U3 MUX JIO1 JIO1 IO/B Conn US11 +USB3_VCCC JTYPEC1 Type-C Conn US12 +USB_VCCA JUSB1 USB3.0 Conn US13 +USB_VCCB JUSB2 USB3.0 Conn PLV2,3 +NVVDD1 UE5 +5V_LEDPWR JBL2 KB BackLight Conn JPA1 UK2 +FP_VCC JFP1 FP Conn U4 +5VS_BL RO4 +5VS_HDD JHDD1 HDD Conn JHDMI1 HDMI Conn UQ1 JPQ2 RF4 +VCC_FAN1 JFAN1 FAN1 Conn RF7 +VCC_FAN2 JFAN1 FAN2 Conn UA1 CODEC JBL1 KB BackLight Conn +VDDA +5VS GPU GPU_B+ PUW1 US3 +5VALW GPU PUV2,3 EN:1.35VSDGPU_EN +19VB A +5VALW_MUX +5VALW NVVDD_B+ +19VB RS127 UY2 +1.35VSDGPU +HDMI_5V_OUT +TS_PWR RX7 +19VB → +19VB_CPU A PLW1 LX1 +INVPWR_B+ JEDP1 Touch Screen PANEL Compal Secret Data Security Classification Issued Date 2019/09/20 Deciphered Date 2020/09/20 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Power Map Number Re v 1.0 FH51M M/B LA-J871P Date: Compal Electronics, Inc Size Document Custom Tuesday, February 11, 2020 Sheet of 112 A B DH5VF_EVT Power Sequence C D E AC mode BIOS ver: V0.02W1 EC: ver: V002AT04 1 Plug in Power On S3 S3 Resume Power Off +3VLP +3VLP EC_ON +5VALW EC_ON → 330.8ms → 333.3ms +5VALW ON/OFFBTN# ON/OFFBTN# → 92.03ms → 94.88ms +3VALW +3VALW → 293.7us +1.05VALW EC_RSMRST# PBTN_OUT# → 29.19ms 2.439ms → 174.6ms PM_SLP_S4# PM_SLP_S3# SYSON +1.05V_VCCST +1.2V_VDDQ +2.5VS SUSP# +1.05VS_VCCSTG +5VS +3VS +1.8VS EC_VCCST_PG SM_PG_CTRL +0.6VS_VTT VR_ON +VCC_SA +VCC_CORE +VCC_GT PCH_PWROK SYS_PWROK PLT_RST# +1.05VALW EC_RSMRST# 20.1ms ← → PBTN_OUT# → 19.18ms → 19.22ms → 72.1us → 275.9us → 692.9us → 910.1us → 12.7ms PM_SLP_S4# 100.5us PM_SLP_S3# 152.8us → SYSON → → → 13.01us → → 8.378us → 877.7us → 630.4us → 412us → 25.34ms 25.35ms → 25.36ms → 25.19ms → → → → → → → → → 55.47us → 618.5us → 8.679ms → 347.6us → 0us → 0us → 3.819ms → 1.759ms 173.0ms NA 12.42ms 150.3ms 152.3ms → → → → → → → → → 26.91us → → → → → 67.04ms 51.25us 656.1us NA 47.39us 61.95us 318.7us +1.2V_VDDQ 2.266ms +2.5VS SUSP# 424.9us +1.05VS_VCCSTG +5VS +3VS 446.2us 25.25ms +1.8VS 0us 25.25ms → → 25.26ms 25.59ms → → → → → → 87.75us 367.6us → 68.53us → 686.0us 11.65ms → 906.0us EC_VCCST_PG 13.97ms SM_PG_CTRL 2.034ms +0.6VS_VTT → 27.06us → 48.00us → 112.0us 1.757ms 167.1ms VR_ON +VCC_SA +VCC_CORE NA NA 12.18ms → → 150.6ms +1.05V_VCCST 13us → 8.502us 88.37us +VCC_GT 47.83us PCH_PWROK 62.37us SYS_PWROK 151.8ms PLT_RST# 4 Compal Secret Data Security Classification Issued Date 2019/09/20 Deciphered Date 2020/09/20 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Power Sequence B C D Rev 1.0 FH51M M/B LA-J871P Date: A Compal Electronics, Inc Size Document Number Custom Tuesday, February 11, 2020 E Sheet of 112 A B Coffee Lake-H - Re-fresh R0 stepping UC1 UC1 SA0000COG00 CMLi5QS@ S IC CL8068404121905 SRF6X U0 2.4G CMLi5@ S IC CL8070104398806 QTJ1 R0 2.1G 1440 S S IC CL8070104399510 SRH84 R1 2.5G SA0000COG40 UH1 E UC6 CFLi5@ S IC CL8068404121905 QRR5 U0 2.4G FCBGA D Comet Lake-H UC5 CFLi5QS@ C SA0000D3I10 SA0000DCP40 UC1 UC8 CFLPCHQS@ CMLi7QS@ S IC FHHM370 QNYF B0 BGA 874P PCH- CMLi7@ S IC CL8070104398908 QTJ2 R0 2.4G 1440 S S IC CL8070104399510 SRH84 R1 2.5G SA0000BPF10 SA0000D3N10 SA0000DCP40 UC1 CMLi9QS@ S IC CL8070104399007 QTJ0 R0 2.8G S SA0000D3G10 UH1 CMLPCH@ S IC FH82HM470 SRJAU A0 FCBGA PCH-H SA0000DDP80 CFL-H @ UC1D K36 K37 J35 J34 H37 H36 J37 J38 D27 E27 H34 H33 F37 G38 F34 F35 E37 E36 F26 E26 C34 D34 B36 B34 F33 E33 C33 B33 A27 B27 DDI1_TXP_0 DDI1_TXN_0 DDI1_TXP_1 DDI1_TXN_1 DDI1_TXP_2 DDI1_TXN_2 DDI1_TXP_3 DDI1_TXN_3 EDP_TXP_0 EDP_TXN_0 EDP_TXP_1 EDP_TXN_1 EDP_TXP_2 EDP_TXN_2 EDP_TXP_3 EDP_TXN_3 DDI1_AUXP DDI1_AUXN EDP_AUXP EDP_AUXN DDI2_TXP_0 DDI2_TXN_0 DDI2_TXP_1 DDI2_TXN_1 DDI2_TXP_2 DDI2_TXN_2 DDI2_TXP_3 DDI2_TXN_3 EDP_DISP_UTIL DISP_RCOMP D29 E29 F28 E28 A29 B29 C28 B28 EDP_TXP0 EDP_TXN0 EDP_TXP1 EDP_TXN1 EDP_TXP2 EDP_TXN2 EDP_TXP3 EDP_TXN3 C26 B26 EDP_AUXP EDP_AUXN EDP_TXP0 EDP_TXN0 EDP_TXP1 EDP_TXN1 EDP_TXP2 EDP_TXN2 EDP_TXP3 EDP_TXN3 eDP EDP_AUXP EDP_AUXN +VCCIO A33 D37 DP_RCOMP RC1 24.9_0402_1% Trace Width/Space: 15 mil/ 20 mil Max Trace Length: 600 mil DDI2_AUXP DDI2_AUXN DDI3_TXP_0 DDI3_TXN_0 DDI3_TXP_1 DDI3_TXN_1 DDI3_TXP_2 DDI3_TXN_2 DDI3_TXP_3 DDI3_TXN_3 DDI3_AUXP DDI3_AUXN PROC_AUDIO_CLK PROC_AUDIO_SDI ofPROC_AUDIO_SDO 13 G27 G25 G29 CPU_DISPA_SDI RC2 20_0402_5% CPU_DISPA_BCLK_R CPU_DISPA_SDO_R CPU_DISPA_SDI_R CPU_DISPA_BCLK_R CPU_DISPA_SDO_R CPU_DISPA_SDI_R 20191024 - SDI 20 ohm close to CPU - BCLK/SDO 30 ohm close to PCH CFL-H_BGA1440 4 Compal Secret Data Security Classification 2019/09/20 Issued Date Deciphered Date 2020/09/20 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title CFL-H(1/8)DDI/eDP Size Document Number Custom B C D Rev 1.0 FH51M M/B LA-J871P Date: A Compal Electronics, Inc Tuesday, February 11, 2020 Sheet E of 112 A B C D E CHANNEL-A Interleaved Memory CFL-H @UC1A DDR CHANNEL A DDR_A_D[0 63] DDR4(IL)/LP3-DDR4(NIL) DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63 BR6 BT6 BP3 BR3 BN5 BP6 BP2 BN3 BL4 BL5 BL2 BM1 BK4 BK5 BK1 BK2 BG4 BG5 BF4 BF5 BG2 BG1 BF1 BF2 BD2 BD1 BC4 BC5 BD5 BD4 BC1 BC2 AB1 AB2 AA4 AA5 AB5 AB4 AA2 AA1 V5 V2 U1 U2 V1 V4 U5 U4 R2 P5 R4 P4 R5 P2 R1 P1 M4 M1 L4 L2 M5 M2 L5 L1 BA2 BA1 AY4 AY5 BA5 BA4 AY1 AY2 For ECC DIMM LP3/DDR4 DDR0_DQ_0/DDR0_DQ_0 DDR0_CKP_0/DDR0_CKP_0 DDR0_DQ_1/DDR0_DQ_1 DDR0_CKN_0/DDR0_CKN_0 DDR0_DQ_2/DDR0_DQ_2 DDR0_CKP_1/DDR0_CKP_1 DDR0_DQ_3/DDR0_DQ_3 DDR0_CKN_1/DDR0_CKN_1 DDR0_DQ_4/DDR0_DQ_4 NC/DDR0_CKP_2 DDR0_DQ_5/DDR0_DQ_5 NC/DDR0_CKN_2 DDR0_DQ_6/DDR0_DQ_6 NC/DDR0_CKP_3 DDR0_DQ_7/DDR0_DQ_7 NC/DDR0_CKN_3 DDR0_DQ_8/DDR0_DQ_8 DDR0_DQ_9/DDR0_DQ_9 DDR0_CKE_0/DDR0_CKE_0 DDR0_DQ_10/DDR0_DQ_10 DDR0_CKE_1/DDR0_CKE_1 DDR0_DQ_11/DDR0_DQ_11 DDR0_CKE_2/DDR0_CKE_2 DDR0_DQ_12/DDR0_DQ_12 DDR0_CKE_3/DDR0_CKE_3 DDR0_DQ_13/DDR0_DQ_13 DDR0_DQ_14/DDR0_DQ_14 DDR0_CS#_0/DDR0_CS#_0 DDR0_DQ_15/DDR0_DQ_15 DDR0_CS#_1/DDR0_CS#_1 DDR0_DQ_16/DDR0_DQ_32 NC/DDR0_CS#_2 DDR0_DQ_17/DDR0_DQ_33 NC/DDR0_CS#_3 DDR0_DQ_18/DDR0_DQ_34 DDR0_DQ_19/DDR0_DQ_35 DDR0_ODT_0/DDR0_ODT_0 DDR0_DQ_20/DDR0_DQ_36 NC/DDR0_ODT_1 DDR0_DQ_21/DDR0_DQ_37 NC/DDR0_ODT_2 DDR0_DQ_22/DDR0_DQ_38 NC/DDR0_ODT_3 DDR0_DQ_23/DDR0_DQ_39 DDR0_DQ_24/DDR0_DQ_40 DDR0_CAB_4/DDR0_BA_0 DDR0_DQ_25/DDR0_DQ_41 DDR0_CAB_6/DDR0_BA_1 DDR0_DQ_26/DDR0_DQ_42 DDR0_CAA_5/DDR0_BG_0 DDR0_DQ_27/DDR0_DQ_43 DDR0_DQ_28/DDR0_DQ_44 DDR0_CAB_3/DDR0_MA_16 DDR0_DQ_29/DDR0_DQ_45 DDR0_CAB_2/DDR0_MA_14 DDR0_DQ_30/DDR0_DQ_46 DDR0_CAB_1/DDR0_MA_15 DDR0_DQ_31/DDR0_DQ_47 DDR0_DQ_32/DDR1_DQ_0 DDR0_CAB_9/DDR0_MA_0 DDR0_DQ_33/DDR1_DQ_1 DDR0_CAB_8/DDR0_MA_1 DDR0_DQ_34/DDR1_DQ_2 DDR0_CAB_5/DDR0_MA_2 DDR0_DQ_35/DDR1_DQ_3 NC/DDR0_MA_3 DDR0_DQ_36/DDR1_DQ_4 NC/DDR0_MA_4 DDR0_DQ_37/DDR1_DQ_5 DDR0_CAA_0/DDR0_MA_5 DDR0_DQ_38/DDR1_DQ_6 DDR0_CAA_2/DDR0_MA_6 DDR0_DQ_39/DDR1_DQ_7 DDR0_CAA_4/DDR0_MA_7 DDR0_DQ_40/DDR1_DQ_8 DDR0_CAA_3/DDR0_MA_8 DDR0_DQ_41/DDR1_DQ_9 DDR0_CAA_1/DDR0_MA_9 DDR0_DQ_42/DDR1_DQ_10 DDR0_CAB_7/DDR0_MA_10 DDR0_DQ_43/DDR1_DQ_11 DDR0_CAA_7/DDR0_MA_11 DDR0_DQ_44/DDR1_DQ_12 DDR0_CAA_6/DDR0_MA_12 DDR0_DQ_45/DDR1_DQ_13 DDR0_CAB_0/DDR0_MA_13 DDR0_DQ_46/DDR1_DQ_14 DDR0_CAA_9/DDR0_BG_1 DDR0_DQ_47/DDR1_DQ_15 DDR0_CAA_8/DDR0_ACT# DDR0_DQ_48/DDR1_DQ_32 DDR0_DQ_49/DDR1_DQ_33 NC/DDR0_PAR DDR0_DQ_50/DDR1_DQ_34 NC/DDR0_ALERT# DDR0_DQ_51/DDR1_DQ_35 DDR4(IL)/LP3-DDR4(NIL) DDR0_DQ_52/DDR1_DQ_36 DDR0_DQ_53/DDR1_DQ_37DDR0_DQSN_0/DDR0_DQSN_0 DDR0_DQ_54/DDR1_DQ_38DDR0_DQSN_1/DDR0_DQSN_1 DDR0_DQ_55/DDR1_DQ_39DDR0_DQSN_2/DDR0_DQSN_4 DDR0_DQ_56/DDR1_DQ_40DDR0_DQSN_3/DDR0_DQSN_5 DDR0_DQ_57/DDR1_DQ_41DDR0_DQSN_4/DDR1_DQSN_0 DDR0_DQ_58/DDR1_DQ_42DDR0_DQSN_5/DDR1_DQSN_1 DDR0_DQ_59/DDR1_DQ_43DDR0_DQSN_6/DDR1_DQSN_4 DDR0_DQ_60/DDR1_DQ_44DDR0_DQSN_7/DDR1_DQSN_5 DDR0_DQ_61/DDR1_DQ_45 DDR0_DQ_62/DDR1_DQ_46DDR0_DQSP_0/DDR0_DQSP_0 DDR0_DQ_63/DDR1_DQ_47DDR0_DQSP_1/DDR0_DQSP_1 DDR0_DQSP_2/DDR0_DQSP_4 LP3/DDR4 DDR0_DQSP_3/DDR0_DQSP_5 NC/DDR0_ECC_0 DDR0_DQSP_4/DDR1_DQSP_0 NC/DDR0_ECC_1 DDR0_DQSP_5/DDR1_DQSP_1 NC/DDR0_ECC_2 DDR0_DQSP_6/DDR1_DQSP_4 NC/DDR0_ECC_3 DDR0_DQSP_7/DDR1_DQSP_5 NC/DDR0_ECC_4 NC/DDR0_ECC_5 DDR0_DQSP_8/DDR0_DQSP_8 NC/DDR0_ECC_6 DDR0_DQSN_8/DDR0_DQSN_8 OF 13 NC/DDR0_ECC_7 AG1 AG2 AK2 AK1 AL3 AK3 AL2 AL1 DDR_A_CLK0 DDR_A_CLK#0 DDR_A_CLK1 DDR_A_CLK#1 AT1 AT2 AT3 AT5 DDR_A_CKE0 DDR_A_CKE1 AD5 AE2 AD2 AE5 DDR_A_CS#0 DDR_A_CS#1 AD3 AE4 AE1 AD4 DDR_A_ODT0 DDR_A_ODT1 AH5 AH1 AU1 DDR_A_BA0 DDR_A_BA1 DDR_A_BG0 AH4 AG4 AD1 DDR_A_MA16_RAS# DDR_A_MA14_W E# DDR_A_MA15_CAS# AH3 AP4 AN4 AP5 AP2 AP1 AP3 AN1 AN3 AT4 AH2 AN2 AU4 AE3 AU2 AU3 DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_BG1 DDR_A_ACT# AG3 AU5 DDR_A_PAR DDR_A_ALERT# BR5 BL3 BG3 BD3 AA3 U3 P3 L3 DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7 BP5 BK3 BF3 BC3 AB3 V3 R3 M3 DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7 DDR_A_CLK0 DDR_A_CLK#0 DDR_A_CLK1 DDR_A_CLK#1 DDR_A_CKE0 DDR_A_CKE1 DDR_A_CS#0 DDR_A_CS#1 DDR_A_ODT0 DDR_A_ODT1 DDR_A_BA0 DDR_A_BA1 DDR_A_BG0 DDR_A_MA16_RAS# DDR_A_MA14_W E# DDR_A_MA15_CAS# DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_BG1 DDR_A_ACT# DDR_A_PAR DDR_A_ALERT# DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7 DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7 AY3 BA3 For ECC DIMM CFL-H_BGA1440 4 Compal Secret Data Security Classification 2019/09/20 Issued Date Deciphered Date 2020/09/20 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title CFL-H(2/8)DIMMA Size Document Number Custom B C D Rev 1.0 FH51M M/B LA-J871P Date: A Compal Electronics, Inc Tuesday, February 11, 2020 Sheet E of 112 A B C D E CHANNEL-B Interleaved Memory CFL-H @ UC1B DDR_B_D[0 63] DDR CHANNEL B DDR4(IL)/LP3-DDR4(NIL) DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 BT11 BR11 BT9 BR8 BP11 BN11 BP8 BN8 BL12 BL11 BL8 BJ8 BJ11 BJ10 BL7 BJ7 BG11 BG10 BG8 BF8 BF11 BF10 BG7 BF7 BB11 BC11 BB8 BC8 BC10 BB10 BC7 BB7 AA11 AA10 AC11 AC10 AA7 AA8 AC8 AC7 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63 W8 W7 V10 V11 W11 W10 V7 V8 R11 P11 P7 R8 R10 P10 R7 P8 L11 M11 L7 M8 L10 M10 M7 L8 For ECC DIMM RC3 RC4 RC5 121_0402_1% SM_RCOMP0 75_0402_1% SM_RCOMP1 100_0402_1% SM_RCOMP2 1 AW11 AY11 AY8 AW8 AY10 AW10 AY7 AW7 G1 H1 J2 LP3/DDR4 DDR1_DQ_0/DDR0_DQ_16 DDR1_DQ_1/DDR0_DQ_17 DDR1_DQ_2/DDR0_DQ_18 DDR1_DQ_3/DDR0_DQ_19 DDR1_DQ_4/DDR0_DQ_20 DDR1_DQ_5/DDR0_DQ_21 DDR1_DQ_6/DDR0_DQ_22 DDR1_DQ_7/DDR0_DQ_23 DDR1_DQ_8/DDR0_DQ_24 DDR1_DQ_9/DDR0_DQ_25 DDR1_DQ_10/DDR0_DQ_26 DDR1_DQ_11/DDR0_DQ_27 DDR1_DQ_12/DDR0_DQ_28 DDR1_DQ_13/DDR0_DQ_29 DDR1_DQ_14/DDR0_DQ_30 DDR1_DQ_15/DDR0_DQ_31 DDR1_DQ_16/DDR0_DQ_48 DDR1_DQ_17/DDR0_DQ_49 DDR1_DQ_18/DDR0_DQ_50 DDR1_DQ_19/DDR0_DQ_51 DDR1_DQ_20/DDR0_DQ_52 DDR1_DQ_21/DDR0_DQ_53 DDR1_DQ_22/DDR0_DQ_54 DDR1_DQ_23/DDR0_DQ_55 DDR1_DQ_24/DDR0_DQ_56 DDR1_DQ_25/DDR0_DQ_57 DDR1_DQ_26/DDR0_DQ_58 DDR1_DQ_27/DDR0_DQ_59 DDR1_DQ_28/DDR0_DQ_60 DDR1_DQ_29/DDR0_DQ_61 DDR1_DQ_30/DDR0_DQ_62 DDR1_DQ_31/DDR0_DQ_63 DDR1_DQ_32/DDR1_DQ_16 DDR1_DQ_33/DDR1_DQ_17 DDR1_DQ_34/DDR1_DQ_18 DDR1_DQ_35/DDR1_DQ_19 DDR1_DQ_36/DDR1_DQ_20 DDR1_DQ_37/DDR1_DQ_21 DDR1_DQ_38/DDR1_DQ_22 DDR1_DQ_39/DDR1_DQ_23 DDR1_CKP_0/DDR1_CKP_0 DDR1_CKN_0/DDR1_CKN_0 DDR1_CKP_1/DDR1_CKP_1 DDR1_CKN_1/DDR1_CKN_1 NC/DDR1_CKP_2 NC/DDR1_CKN_2 NC/DDR1_CKP_3 NC/DDR1_CKN_3 DDR1_CKE_0/DDR1_CKE_0 DDR1_CKE_1/DDR1_CKE_1 DDR1_CKE_2/DDR1_CKE_2 DDR1_CKE_3/DDR1_CKE_3 DDR1_CS#_0/DDR1_CS#_0 DDR1_CS#_1/DDR1_CS#_1 NC/DDR1_CS#_2 NC/DDR1_CS#_3 DDR1_ODT_0/DDR1_ODT_0 NC/DDR1_ODT_1 NC/DDR1_ODT_2 NC/DDR1_ODT_3 DDR1_CAB_3/DDR1_MA_16 DDR1_CAB_2/DDR1_MA_14 DDR1_CAB_1/DDR1_MA_15 DDR1_CAB_4/DDR1_BA_0 DDR1_CAB_6/DDR1_BA_1 DDR1_CAA_5/DDR1_BG_0 DDR1_CAB_9/DDR1_MA_0 DDR1_CAB_8/DDR1_MA_1 DDR1_CAB_5/DDR1_MA_2 NC/DDR1_MA_3 NC/DDR1_MA_4 DDR1_CAA_0/DDR1_MA_5 DDR1_CAA_2/DDR1_MA_6 DDR1_CAA_4/DDR1_MA_7 DDR4(IL)/LP3-DDR4(NIL) DDR1_DQ_40/DDR1_DQ_24 DDR1_CAA_3/DDR1_MA_8 DDR1_DQ_41/DDR1_DQ_25 DDR1_CAA_1/DDR1_MA_9 DDR1_DQ_42/DDR1_DQ_26 DDR1_CAB_7/DDR1_MA_10 DDR1_DQ_43/DDR1_DQ_27 DDR1_CAA_7/DDR1_MA_11 DDR1_DQ_44/DDR1_DQ_28 DDR1_CAA_6/DDR1_MA_12 DDR1_DQ_45/DDR1_DQ_29 DDR1_CAB_0/DDR1_MA_13 DDR1_DQ_46/DDR1_DQ_30 DDR1_CAA_9/DDR1_BG_1 DDR1_DQ_47/DDR1_DQ_31 DDR1_CAA_8/DDR1_ACT# DDR1_DQ_48/DDR1_DQ_48 DDR1_DQ_49/DDR1_DQ_49 NC/DDR1_PAR DDR1_DQ_50/DDR1_DQ_50 NC/DDR1_ALERT# DDR1_DQ_51/DDR1_DQ_51 DDR4(IL)/LP3-DDR4(NIL) DDR1_DQ_52/DDR1_DQ_52 DDR1_DQ_53/DDR1_DQ_53DDR1_DQSN_0/DDR0_DQSN_2 DDR1_DQ_54/DDR1_DQ_54DDR1_DQSN_1/DDR0_DQSN_3 DDR1_DQ_55/DDR1_DQ_55DDR1_DQSN_2/DDR0_DQSN_6 DDR1_DQ_56/DDR1_DQ_56DDR1_DQSN_3/DDR0_DQSN_7 DDR1_DQ_57/DDR1_DQ_57DDR1_DQSN_4/DDR1_DQSN_2 DDR1_DQ_58/DDR1_DQ_58DDR1_DQSN_5/DDR1_DQSN_3 DDR1_DQ_59/DDR1_DQ_59DDR1_DQSN_6/DDR1_DQSN_6 DDR1_DQ_60/DDR1_DQ_60DDR1_DQSN_7/DDR1_DQSN_7 DDR1_DQ_61/DDR1_DQ_61 DDR1_DQ_62/DDR1_DQ_62DDR1_DQSP_0/DDR0_DQSP_2 DDR1_DQ_63/DDR1_DQ_63DDR1_DQSP_1/DDR0_DQSP_3 DDR1_DQSP_2/DDR0_DQSP_6 LP3/DDR4 NC/DDR1_ECC_0 DDR1_DQSP_3/DDR0_DQSP_7 NC/DDR1_ECC_1 DDR1_DQSP_4/DDR1_DQSP_2 NC/DDR1_ECC_2 DDR1_DQSP_5/DDR1_DQSP_3 NC/DDR1_ECC_3 DDR1_DQSP_6/DDR1_DQSP_6 NC/DDR1_ECC_4 DDR1_DQSP_7/DDR1_DQSP_7 NC/DDR1_ECC_5 NC/DDR1_ECC_6 DDR1_DQSP_8/DDR1_DQSP_8 NC/DDR1_ECC_7 DDR1_DQSN_8/DDR1_DQSN_8 DDR_RCOMP_0 DDR_RCOMP_1 DDR_RCOMP_2 DDR_VREF_CA DDR0_VREF_DQ DDR1_VREF_DQ OF 13 AM9 AN9 AM7 AM8 AM11 AM10 AJ10 AJ11 DDR_B_CLK0 DDR_B_CLK#0 DDR_B_CLK1 DDR_B_CLK#1 AT8 AT10 AT7 AT11 DDR_B_CKE0 DDR_B_CKE1 AF11 AE7 AF10 AE10 DDR_B_CS#0 DDR_B_CS#1 AF7 AE8 AE9 AE11 DDR_B_ODT0 DDR_B_ODT1 AH10 AH11 AF8 DDR_B_MA16_RAS# DDR_B_MA14_W E# DDR_B_MA15_CAS# AH8 AH9 AR9 DDR_B_BA0 DDR_B_BA1 DDR_B_BG0 AJ9 AK6 AK5 AL5 AL6 AM6 AN7 AN10 DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 AN8 AR11 AH7 AN11 AR10 AF9 AR7 AT9 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_BG1 DDR_B_ACT# AJ7 AR8 DDR_B_PAR DDR_B_ALERT# BN9 BL9 BG9 BC9 AC9 W9 R9 M9 DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7 BP9 BJ9 BF9 BB9 AA9 V9 P9 L9 DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7 AW9 AY9 BN13 BP13 BR13 DDR_B_CLK0 DDR_B_CLK#0 DDR_B_CLK1 DDR_B_CLK#1 DDR_B_CKE0 DDR_B_CKE1 DDR_B_CS#0 DDR_B_CS#1 DDR_B_ODT0 DDR_B_ODT1 DDR_B_MA16_RAS# DDR_B_MA14_W E# DDR_B_MA15_CAS# DDR_B_BA0 DDR_B_BA1 DDR_B_BG0 DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_BG1 DDR_B_ACT# DDR_B_PAR DDR_B_ALERT# DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7 DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7 For ECC DIMM +0.6V_VREFCA +0.6V_B_VREFDQ +0.6V_VREFCA +0.6V_B_VREFDQ CFL-H_BGA1440 Trace Width/Space: 15 mil/ 25 mil Max Trace Length: 500 mil 4 Compal Secret Data Security Classification 2019/09/20 Issued Date Deciphered Date 2020/09/20 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title B C D CFL-H(3/8)DIMMB Size Document Number Custom Rev 1.0 FH51M M/B LA-J871P Date: A Compal Electronics, Inc Tuesday, February 11, 2020 Sheet E of 112 A B C D E PEG&DMI To DGPU PEG Lane Reversed To DGPU PEG Lane Reversed CFL-H UC1C PEG_CRX_C_GTX_P15 PEG_CRX_C_GTX_N15 CC1 CC3 VGA@ VGA@ 0.22U_0201_6.3V6K 0.22U_0201_6.3V6K PEG_CRX_GTX_P15 PEG_CRX_GTX_N15 E25 D25 PEG_CRX_C_GTX_P14 PEG_CRX_C_GTX_N14 CC5 CC6 VGA@ VGA@ 0.22U_0201_6.3V6K 0.22U_0201_6.3V6K PEG_CRX_GTX_P14 PEG_CRX_GTX_N14 E24 F24 PEG_CRX_C_GTX_P13 PEG_CRX_C_GTX_N13 CC7 VGA@ CC14 VGA@ 0.22U_0201_6.3V6K 0.22U_0201_6.3V6K PEG_CRX_GTX_P13 PEG_CRX_GTX_N13 E23 D23 PEG_CRX_C_GTX_P12 PEG_CRX_C_GTX_N12 CC16 VGA@ CC17 VGA@ 0.22U_0201_6.3V6K 0.22U_0201_6.3V6K PEG_CRX_GTX_P12 PEG_CRX_GTX_N12 E22 F22 E21 D21 PEG_CRX_C_GTX_P11 PEG_CRX_C_GTX_N11 CC19 VGA@ CC20 VGA@ 0.22U_0201_6.3V6K 0.22U_0201_6.3V6K PEG_CRX_GTX_P11 PEG_CRX_GTX_N11 PEG_CRX_C_GTX_P10 PEG_CRX_C_GTX_N10 CC10 VGA@ CC23 VGA@ 0.22U_0201_6.3V6K 0.22U_0201_6.3V6K PEG_CRX_GTX_P10 PEG_CRX_GTX_N10 E20 F20 PEG_CRX_C_GTX_P9 PEG_CRX_C_GTX_N9 CC25 VGA@ CC27 VGA@ 0.22U_0201_6.3V6K 0.22U_0201_6.3V6K PEG_CRX_GTX_P9 PEG_CRX_GTX_N9 E19 D19 PEG_CRX_C_GTX_P8 PEG_CRX_C_GTX_N8 CC29 VGA@ CC31 VGA@ 0.22U_0201_6.3V6K 0.22U_0201_6.3V6K PEG_CRX_GTX_P8 PEG_CRX_GTX_N8 E18 F18 PEG_CRX_C_GTX_P7 PEG_CRX_C_GTX_N7 CC33 VGA@ CC35 VGA@ 0.22U_0201_6.3V6K 0.22U_0201_6.3V6K PEG_CRX_GTX_P7 PEG_CRX_GTX_N7 D17 E17 PEG_CRX_C_GTX_P6 PEG_CRX_C_GTX_N6 CC37 VGA@ CC39 VGA@ 0.22U_0201_6.3V6K 0.22U_0201_6.3V6K PEG_CRX_GTX_P6 PEG_CRX_GTX_N6 F16 E16 PEG_CRX_C_GTX_P5 PEG_CRX_C_GTX_N5 CC41 VGA@ CC43 VGA@ 0.22U_0201_6.3V6K 0.22U_0201_6.3V6K PEG_CRX_GTX_P5 PEG_CRX_GTX_N5 D15 E15 PEG_CRX_C_GTX_P4 PEG_CRX_C_GTX_N4 CC45 VGA@ CC47 VGA@ 0.22U_0201_6.3V6K 0.22U_0201_6.3V6K PEG_CRX_GTX_P4 PEG_CRX_GTX_N4 F14 E14 PEG_CRX_C_GTX_P3 PEG_CRX_C_GTX_N3 CC49 VGA@ CC51 VGA@ 0.22U_0201_6.3V6K 0.22U_0201_6.3V6K PEG_CRX_GTX_P3 PEG_CRX_GTX_N3 D13 E13 F12 E12 PEG_CRX_C_GTX_P2 PEG_CRX_C_GTX_N2 CC53 VGA@ CC55 VGA@ 0.22U_0201_6.3V6K 0.22U_0201_6.3V6K PEG_CRX_GTX_P2 PEG_CRX_GTX_N2 PEG_CRX_C_GTX_P1 PEG_CRX_C_GTX_N1 CC57 VGA@ CC59 VGA@ 0.22U_0201_6.3V6K 0.22U_0201_6.3V6K PEG_CRX_GTX_P1 PEG_CRX_GTX_N1 D11 E11 PEG_CRX_C_GTX_P0 PEG_CRX_C_GTX_N0 CC61 VGA@ CC63 VGA@ 0.22U_0201_6.3V6K 0.22U_0201_6.3V6K PEG_CRX_GTX_P0 PEG_CRX_GTX_N0 F10 E10 PEG_RXP_0 PEG_RXN_0 PEG_TXP_0 PEG_TXN_0 PEG_RXP_1 PEG_RXN_1 PEG_TXP_1 PEG_TXN_1 PEG_RXP_2 PEG_RXN_2 PEG_TXP_2 PEG_TXN_2 PEG_RXP_3 PEG_RXN_3 PEG_TXP_3 PEG_TXN_3 PEG_RXP_4 PEG_RXN_4 PEG_TXP_4 PEG_TXN_4 PEG_RXP_5 PEG_RXN_5 PEG_TXP_5 PEG_TXN_5 PEG_RXP_6 PEG_RXN_6 PEG_TXP_6 PEG_TXN_6 PEG_RXP_7 PEG_RXN_7 PEG_TXP_7 PEG_TXN_7 PEG_RXP_8 PEG_RXN_8 PEG_TXP_8 PEG_TXN_8 PEG_RXP_9 PEG_RXN_9 PEG_TXP_9 PEG_TXN_9 PEG_RXP_10 PEG_RXN_10 PEG_TXP_10 PEG_TXN_10 PEG_RXP_11 PEG_RXN_11 PEG_RXP_12 PEG_RXN_12 PEG_RXP_13 PEG_RXN_13 PEG_RXP_14 PEG_RXN_14 PEG_RXP_15 PEG_RXN_15 PEG_TXP_11 PEG_TXN_11 PEG_TXP_12 PEG_TXN_12 PEG_TXP_13 PEG_TXN_13 PEG_TXP_14 PEG_TXN_14 PEG_TXP_15 PEG_TXN_15 B25 A25 PEG_CTX_GRX_P15 0.22U_0201_6.3V6K PEG_CTX_GRX_N15 0.22U_0201_6.3V6K 2 1VGA@ CC2 1VGA@ CC4 B24 C24 PEG_CTX_GRX_P14 0.22U_0201_6.3V6K PEG_CTX_GRX_N14 0.22U_0201_6.3V6K 2 1VGA@ CC11 1VGA@ CC12 B23 A23 PEG_CTX_GRX_P13 0.22U_0201_6.3V6K PEG_CTX_GRX_N13 0.22U_0201_6.3V6K 2 1VGA@ CC13 1VGA@ CC15 B22 C22 PEG_CTX_GRX_P12 0.22U_0201_6.3V6K PEG_CTX_GRX_N12 0.22U_0201_6.3V6K 2 1VGA@ CC8 1VGA@ CC18 B21 A21 PEG_CTX_GRX_P11 0.22U_0201_6.3V6K PEG_CTX_GRX_N11 0.22U_0201_6.3V6K 2 1VGA@ CC9 1VGA@ CC21 B20 C20 PEG_CTX_GRX_P10 0.22U_0201_6.3V6K PEG_CTX_GRX_N10 0.22U_0201_6.3V6K 2 1VGA@ CC22 1VGA@ CC24 B19 A19 PEG_CTX_GRX_P9 PEG_CTX_GRX_N9 0.22U_0201_6.3V6K 0.22U_0201_6.3V6K 2 1VGA@ CC26 1VGA@ CC28 B18 C18 PEG_CTX_GRX_P8 PEG_CTX_GRX_N8 0.22U_0201_6.3V6K 0.22U_0201_6.3V6K 2 1VGA@ CC30 1VGA@ CC32 A17 B17 PEG_CTX_GRX_P7 PEG_CTX_GRX_N7 0.22U_0201_6.3V6K 0.22U_0201_6.3V6K 2 1VGA@ CC34 1VGA@ CC36 C16 B16 PEG_CTX_GRX_P6 PEG_CTX_GRX_N6 0.22U_0201_6.3V6K 0.22U_0201_6.3V6K 2 1VGA@ CC38 1VGA@ CC40 A15 B15 PEG_CTX_GRX_P5 PEG_CTX_GRX_N5 0.22U_0201_6.3V6K 0.22U_0201_6.3V6K 2 1VGA@ CC42 1VGA@ CC44 C14 B14 PEG_CTX_GRX_P4 PEG_CTX_GRX_N4 0.22U_0201_6.3V6K 0.22U_0201_6.3V6K 2 1VGA@ CC46 1VGA@ CC48 A13 B13 PEG_CTX_GRX_P3 PEG_CTX_GRX_N3 0.22U_0201_6.3V6K 0.22U_0201_6.3V6K 2 1VGA@ CC50 1VGA@ CC52 C12 B12 PEG_CTX_GRX_P2 PEG_CTX_GRX_N2 0.22U_0201_6.3V6K 0.22U_0201_6.3V6K 2 1VGA@ CC54 1VGA@ CC56 A11 B11 PEG_CTX_GRX_P1 PEG_CTX_GRX_N1 0.22U_0201_6.3V6K 0.22U_0201_6.3V6K 2 1VGA@ CC58 1VGA@ CC60 C10 B10 PEG_CTX_GRX_P0 PEG_CTX_GRX_N0 0.22U_0201_6.3V6K 0.22U_0201_6.3V6K 2 1VGA@ CC62 1VGA@ CC64 B8 A8 DMI_CTX_PRX_P0 DMI_CTX_PRX_N0 C6 B6 DMI_CTX_PRX_P1 DMI_CTX_PRX_N1 B5 A5 DMI_CTX_PRX_P2 DMI_CTX_PRX_N2 D4 B4 DMI_CTX_PRX_P3 DMI_CTX_PRX_N3 PEG_CTX_C_GRX_P15 PEG_CTX_C_GRX_N15 PEG_CTX_C_GRX_P14 PEG_CTX_C_GRX_N14 PEG_CTX_C_GRX_P13 PEG_CTX_C_GRX_N13 PEG_CTX_C_GRX_P12 PEG_CTX_C_GRX_N12 PEG_CTX_C_GRX_P11 PEG_CTX_C_GRX_N11 PEG_CTX_C_GRX_P10 PEG_CTX_C_GRX_N10 PEG_CTX_C_GRX_P9 PEG_CTX_C_GRX_N9 PEG_CTX_C_GRX_P8 PEG_CTX_C_GRX_N8 PEG_CTX_C_GRX_P7 PEG_CTX_C_GRX_N7 PEG_CTX_C_GRX_P6 PEG_CTX_C_GRX_N6 PEG_CTX_C_GRX_P5 PEG_CTX_C_GRX_N5 PEG_CTX_C_GRX_P4 PEG_CTX_C_GRX_N4 PEG_CTX_C_GRX_P3 PEG_CTX_C_GRX_N3 PEG_CTX_C_GRX_P2 PEG_CTX_C_GRX_N2 PEG_CTX_C_GRX_P1 PEG_CTX_C_GRX_N1 PEG_CTX_C_GRX_P0 PEG_CTX_C_GRX_N0 +VCCIO RC6 24.9_0402_1% PEG_RCOMP G2 DMI_CRX_PTX_P0 DMI_CRX_PTX_N0 D8 E8 DMI_CRX_PTX_P1 DMI_CRX_PTX_N1 E6 F6 DMI_CRX_PTX_P2 DMI_CRX_PTX_N2 D5 E5 DMI_CRX_PTX_P3 DMI_CRX_PTX_N3 J8 J9 PEG_RCOMP Trace Width/Space: 15 mil/ 15 mil Max Trace Length: 600 mil DMI_CRX_PTX_P0 DMI_CRX_PTX_N0 DMI_CRX_PTX_P1 DMI_CRX_PTX_N1 To PCH DMI_CRX_PTX_P2 DMI_CRX_PTX_N2 DMI_CRX_PTX_P3 DMI_CRX_PTX_N3 DMI_RXP_0 DMI_RXN_0 DMI_TXP_0 DMI_TXN_0 DMI_RXP_1 DMI_RXN_1 DMI_TXP_1 DMI_TXN_1 DMI_RXP_2 DMI_RXN_2 DMI_TXP_2 DMI_TXN_2 DMI_RXP_3 DMI_RXN_3 OF 13 DMI_TXP_3 DMI_TXN_3 DMI_CTX_PRX_P0 DMI_CTX_PRX_N0 DMI_CTX_PRX_P1 DMI_CTX_PRX_N1 To PCH DMI_CTX_PRX_P2 DMI_CTX_PRX_N2 DMI_CTX_PRX_P3 DMI_CTX_PRX_N3 CFL-H_BGA1440 @ 4 Compal Secret Data Security Classification 2019/09/20 Issued Date Deciphered Date 2020/09/20 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title B C D PEG/DMI Size Document Number Custom Rev 1.0 FH51M M/B LA-J871P Date: A Compal Electronics, Inc Tuesday, February 11, 2020 Sheet E of 112 A B C D UC1E PCH_CPU_BCLK_P PCH_CPU_BCLK_N PCH_CPU_BCLK_P PCH_CPU_BCLK_N PCH_CPU_PCIBCLK_P PCH_CPU_PCIBCLK_N PCH_CPU_24M_CLK_P PCH_CPU_24M_CLK_N B31 A32 PCH_CPU_PCIBCLK_P PCH_CPU_PCIBCLK_N D35 C36 PCH_CPU_24M_CLK_P PCH_CPU_24M_CLK_N E31 D31 BCLKP BCLKN CFG_0 CFG_1 CFG_2 CFG_3 CFG_4 CFG_5 CFG_6 CFG_7 CFG_8 CFG_9 CFG_10 CFG_11 CFG_12 CFG_13 CFG_14 CFG_15 PCI_BCLKP PCI_BCLKN CLK24P CLK24N Sensitive CPU_SVID_CLK_R CPU_SVID_ALERT# CPU_SVID_CLK_R CPU_SVID_DAT_R H_PROCHOT#_R BH31 BH32 BH29 BR30 DDR_PG_CTRL BT13 VIDALERT# VIDSCK VIDSOUT PROCHOT# DDR_VTT_CNTL CFG_17 CFG_16 CFG_19 CFG_18 VCCST_PWRGD BPM#_0 BPM#_1 BPM#_2 BPM#_3 Sensitive EC_VCCST_PG H_CPUPW RGD H_PLTRST_CPU# H_PM_SYNC_R H_PECI PCH_THERMTRIP#_R RC17 @ 20191024 PROC_SELECT# > should be unconnected on CFL/CML processor XESD@ CC65 0.1U_0201_10V6K 0_0402_5% H13 H_CPUPW RGD H_PLTRST_CPU# H_PM_SYNC_R H_PM_DOW N H_PECI H_THERMTRIP# BT31 BP35 BM34 BP31 BT34 J31 @ TC5 SKTOCC# BR33 BN1 @ TC6 CATERR# BM30 PROCPWRGD RESET# PM_SYNC PM_DOWN PECI THERMTRIP# PROC_TRST# PROC_PREQ# PROC_PRDY# CATERR# CFG_RCOMP BN25 BN27 BN26 BN28 BR20 BM20 BT20 BP20 BR23 BR22 BT23 BT22 BM19 BR19 BP19 BT19 CFG0 CFG0 CFG2 CFG4 CFG5 CFG6 CFG7 CFG2 CFG4 CFG5 CFG6 CFG7 XDP_BPM#0 XDP_BPM#1 XDP_BPM#2 XDP_BPM#3 BR27 BT27 BM31 BT30 BT28 BL32 BP28 BR28 CPU_XDP_TDO CPU_XDP_TDI CPU_XDP_TMS CPU_XDP_TCK0 BP30 BL30 BP27 CPU_XDP_TRST# XDP_PREQ# XDP_PRDY# CFG_RCOMP RC18 BT25 TC1 TC2 TC3 TC4 @ @ @ @ CPU_XDP_TDO CPU_XDP_TDI CPU_XDP_TMS CPU_XDP_TCK0 EC_VCCST_PG Near CPU XDP_PREQ# XDP_PRDY# 8/21 follow 1050 RC76 +1.2V_VDDQ Request +3VS +1.05V_VCCST A UC3 Y *20191024 - CML RCP/PDG/Check list , PROC_TDO PU 100 ohm to VCCXT *20191104 - CMC@ change to always pop (RC76/77/78/79) 51_0402_5% CPU_XDP_TMS RC77 51_0402_5% CPU_XDP_TDI RC78 51_0402_5% CPU_XDP_TDO RC79 51_0402_5% CPU_XDP_TCK0 RC80 @ 51_0402_5% PCH_JTAG_TCK1 RC81 @ 51_0402_5% CPU_XDP_TRST# Place to CPU side Place to CPU side PCH_JTAG_TCK1 8/21 PU 330K follow CRB +1.05VS_VCCSTG 74AUP1G07SE-7_SOT353-5 SM_PG_CTRL G DDR_PG_CTRL 1K_0402_5% Vcc NC RH1 RC23 330K_0402_5% H_THERMTRIP# XDP_PREQ# XDP_PRDY# Trace Width/Space: mil/ 12 mil Max Trace Length: 600 mil RSVD1 RSVD2 CC69 0.1U_0201_10V6K 1K_0402_5% 1K_0402_5% 1K_0402_5% 1K_0402_5% 1K_0402_5% 1K_0402_5% CFL-H_BGA1440 @ side @ @ @ 2 2 2 To be confirm 49.9_0402_1% H_THERMTRIP# @ CPU_XDP_TRST# TC19 @ TC20 @ +1.05VS_VCCSTG ESD@ CC68 1000P_0402_50V7K 1 1 1 *CFG Pin Use CMC debug on DDX03 R02 Schematic OF 13 XESD@ CC67 0.1U_0201_10V6K RC7 RC8 RC9 RC10 RC11 RC12 The CFG signals have a default value of '1' if not terminated on the board CFG[0]: Stall reset sequence after PCU PLL lock until de-asserted * = (Default) Normal Operation; = Stall CFG[2]: PCI Express* Static x16 Lane Numbering Reversal = Normal operation * = Lane numbers reversed CFG[4]: eDP enable: = Disabled * = Enabled CFG[6:5]: PCI Express* Bifurcation: 00 = x8, x4 PCI Express* 01 = reserved 10 = x8 PCI Express* 11 = x16 PCI Express* * CFG[7]: PEG Training: * = (default) PEG Train immediately following RESET# de assertion = PEG Wait for BIOS for training BN23 BP23 BP22 BN22 ZVM# MSM# AU13 AY13 H_PROCHOT#_R PROC_TDO PROC_TDI PROC_TMS PROC_TCK SKTOCC# PROC_SELECT# AT13 AW13 H_CPUPW RGD ESD@ CC66 1000P_0402_50V7K E CFL-H 571391_CFL_H_PDG_Rev0p5 The total Length of Data and Clock (from CPU to each VR) must be equal (± 0.1 inch) Route the Alert signal between the Clock and the Data signals Place those resistors close CPU side RC21 1K_0402_5% RC14 H_PROCHOT# 499_0402_1% H_PROCHOT#_R SVID +1.05V_VCCST RC22 1K_0402_5% EC_VCCST_PG_R RC16 H_PM_DOW N_R 20_0402_5% H_PM_DOW N EC_VCCST_PG CPU_SVID_ALERT#_R RC20 100_0402_1% RC13 1 60.4_0402_1% RC19 56_0402_1% RC15 1 1 +1.05V_VCCST @ CPU_SVID_ALERT# CPU_SVID_DAT_R CPU_SVID_DAT_R RH2 13_0402_5% 220_0402_5% Compal Secret Data Security Classification 2019/09/20 Issued Date Deciphered Date 2020/09/20 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title B C D CFL-H(5/8)CFG,SVID Size Document Number Custom Rev 1.0 FH51M M/B LA-J871P Date: A Compal Electronics, Inc Tuesday, February 11, 2020 Sheet E 10 of 112 PCV276 10U_0402_6.3V6M PCV237 10U_0402_6.3V6M PCV280 10U_0402_6.3V6M PCV283 10U_0402_6.3V6M 2 PCV279 10U_0402_6.3V6M PCV282 10U_0402_6.3V6M PCV287 10U_0402_6.3V6M PCV250 10U_0402_6.3V6M PCV275 10U_0402_6.3V6M PCV281 10U_0402_6.3V6M PCV284 10U_0402_6.3V6M PCV277 10U_0402_6.3V6M PCV227 10U_0402_6.3V6M PCV229 10U_0402_6.3V6M PCV228 10U_0402_6.3V6M PCV230 10U_0402_6.3V6M PCV231 10U_0402_6.3V6M PCV232 10U_0402_6.3V6M PCV233 10U_0402_6.3V6M PCV234 10U_0402_6.3V6M Security Classification Issued Date 2019/09/20 Deciphered Date PCV256 22U_0603_6.3V6M PCV257 22U_0603_6.3V6M 1 2020/09/20 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Compal Secret Data Date: Size PCV361 22U_0603_6.3V6M PCV360 22U_0603_6.3V6M PCV359 22U_0603_6.3V6M PCV358 22U_0603_6.3V6M PCV248 22U_0603_6.3V6M PCV247 22U_0603_6.3V6M PCV246 22U_0603_6.3V6M PCV245 22U_0603_6.3V6M PCV244 22U_0603_6.3V6M PCV243 22U_0603_6.3V6M 2 PCV224 10U_0402_6.3V6M PCV223 10U_0402_6.3V6M PCV222 10U_0402_6.3V6M PCV221 10U_0402_6.3V6M PCV220 10U_0402_6.3V6M PCV219 10U_0402_6.3V6M PCV218 10U_0402_6.3V6M PCV217 10U_0402_6.3V6M PCV216 10U_0402_6.3V6M PCV252 22U_0603_6.3V6M PCV253 22U_0603_6.3V6M PCV254 22U_0603_6.3V6M 1 +NVVDD1 PCV236 10U_0402_6.3V6M PCV226 10U_0402_6.3V6M 2 PCV215 10U_0402_6.3V6M PCV235 10U_0402_6.3V6M PCV225 10U_0402_6.3V6M 1 PCV148 1U_0201_6.3VAM PCV154 1U_0201_6.3VAM + PCV147 1U_0201_6.3VAM PCV153 1U_0201_6.3VAM 2 PCV272 560U_D2_2VM_R4.5M 1 PCV146 1U_0201_6.3VAM PCV152 1U_0201_6.3VAM 2 PCV139 560U_D2_2VM_R4.5M + PCV145 1U_0201_6.3VAM PCV151 1U_0201_6.3VAM 2 PCV165 1U_0201_6.3VAM PCV144 1U_0201_6.3VAM PCV150 1U_0201_6.3VAM + PCV138 560U_D2_2VM_R4.5M PCV164 1U_0201_6.3VAM PCV143 1U_0201_6.3VAM PCV149 1U_0201_6.3VAM 2 PCV137 330U_D1_2VY_R9M + PCV163 1U_0201_6.3VAM PCV142 1U_0201_6.3VAM PCV258 1U_0201_6.3VAM PCV136 330U_D1_2VY_R9M PCV162 1U_0201_6.3VAM PCV141 1U_0201_6.3VAM PCV161 1U_0201_6.3VAM @ PCV135 560U_D2_2VM_R4.5M + PCV158 1U_0201_6.3VAM PCV140 1U_0201_6.3VAM 1 PCV160 1U_0201_6.3VAM 2 PCV157 1U_0201_6.3VAM PCV156 1U_0201_6.3VAM 1 PCV251 1U_0201_6.3VAM 2 + PCV159 1U_0201_6.3VAM 1 PCV155 1U_0201_6.3VAM N18P-G62 +NVVDD 560uF X 22uF_0603 X 15 10uF_0402X 34 1uF_0201 X 28 D D +NVVDD1 +NVVDD1 C C B B A A Title PWR_VGA DECOUPLING Compal Electronics, Inc Document Number FXXXX M/B LA-J871P Tuesday, February 11, 2020 Sheet 98 of 112 R ev 1.0 D D C C Reserve Page B B A A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2019/09/20 2020/09/20 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Reserve Size R ev 1.0 FXXXX M/B LA-J871P Date: Document Number Tuesday, February 11, 2020 Sheet 99 of 112 co-lay 0603 low noise MLCC EMI@ PLW11 FBMA-L11-201209-800LMA50T LG1_+1.35VS_VGAP 18 PVCC_+1.35VS_VGAP 17 16 PCW26 10U_0603-H1_2_25V6M PCW5 10U_0805_25VAK 1 @ PCW13 22U_0603_6.3V6M + PCW12 22U_0603_6.3V6M @ + PCW29 330U_D1_2VY_R9M + PCW28 330U_D1_2VY_R9M + PCW10 330U_D1_2VY_R9M PCW9 330U_D1_2VY_R9M @ + C EMI@ PCW16 680P_0402_50V7K PRW11 2.2_0603_5% SW1_+1.35VS_VGAP 19 PCW14 0.22U_0603_25V7K PCW23 330U_D1_2VY_R9M LG1_+1.35VS_VGAP PHASE2 20 +1.35VSDGPU D1_2 D1_1 D2/S1_1 G2 D2/S1_2 G1 D2/S1_3 S1/D2 EMI@ PRW8 4.7_1206_5% +5VALW PCW17 2.2U_0402_6.3V6M BOOT2 UGATE2 10 15 14 S2 EN_+1.35VS_VGAP UG1_+1.35VS_VGAP BOOT1_+1.35VS_VGAP BOOT1 UGATE1 PSI_+1.35VS_VGAP PGOOD 13 D1_3 1.35VSDGPU_PG VSNS GND @ @ PRW17 36.5K_0402_1% RGND PRW19 100_0402_1% PRW20 0_0402_5% LGATE2 Rocset for 75.6A 10 EN PVCC TON PCW27 0.1U_0402_25V6 FB_VDDQ_SENSE B +1.35VSDGPU PSI VID 0.1U_0402_25V6 PHASE1 VREF OCSET/SS RGND PUW1 RT8816BGQW_WQFN20_3X3 LGATE1 11 PCW18 1TON_+1.35VS_VGAP_R TON_+1.35VS_VGAP 21 PRW13 453K_0402_1% REFIN B+_+1.35VS_VGAP PRW12 2.2_0402_1% REFADJ 1OCset_+1.35VS_VGAP 12 REFIN_+1.35VS_VGAP 0_0402_5% @ PRW14 PCW22 2200P_0402_50V7K VID_+1.35VS_VGAP 2 REFADJ_+1.35VS_VGAP VREF_+1.35VS_VGAP PRW24 14K_0402_1% @ PCW15 0.1U_0402_16V7K PRW25 120K_0402_1% REFADJ_+1.35VS_VGAP Vsense_+1.35VS_VGAP PRW28 10K_0402_1% PCW21 2200P_0402_50V7K REFADJ 2 PCW20 0.1U_0402_25V6 PRW22 4.99K_0402_1% 2 PRW23 3.3K_0402_1% @0@ PRW9 0_0402_5% VRAM_VDD_CTL PRW4 2.2_0603_5% PLW1 PQW1 0.47UH_MHT-MHDZIR47MEM1-RT_30A_20% AOE6930_DFN5X6E8-10 SW1_+1.35VS_VGAP-1 PCW11 22U_0603_6.3V6M 1 PRW6 10K_0402_1% REFIN_+1.35VS_VGAP REF2 +1.35VSDGPU N18P-G62 TDC 17.2A Peak Current 18.4A OCP current 30A fsw=400kHz 13X8X4 Isat:55A DCR:1.3mΩ (+/-5%) SNB1_+1.35VS_VGAP RBOOT D @ BOOT1_+1.35VS_VGAP_R REFADJ_+1.35VS_VGAP_R @ SW1_+1.35VS_VGAP @ PRW3 0_0402_5% VREF_+1.35VS_VGAP C GPU_B+ UG1_+1.35VS_VGAP PRW10 31.6K_0402_1% FBVDDQ_PSI REF1 @ PCW25 10U_0603-H1_2_25V6M +3VALW PCW24 10U_0603-H1_2_25V6M Samesung & Micron VRAM When,VRAM_VDD_CTL=High Vboot=1.25V When,VRAM_VDD_CTL=Low Vboot=1.2V MOSFET: DFN 5X6E H/S Rds(on): 5.2mohm(Typ), 7mohm(Max) L/S Rds(on): 0.8mohm(Typ), 1.05mohm(Max) PCW4 10U_0805_25VAK PCW6 0.1U_0402_25V6 PCW3 10U_0805_25VAK 1.35VSDGPU_EN D EMI@ PCW1 2200P_0402_50V7K PRW1 1K_0402_1% EMI@ PCW2 0.1U_0402_25V6 B+_+1.35VS_VGAP B PRW18 10K_0402_1% +3VS 1.35VSDGPU_PG A A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2019/09/20 Deciphered Date 2020/09/20 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title PWR_+1.5VRAM Size Date: Document Number Rev 1.0 Tuesday, February 11, 2020 Sheet SKL_H 42 100 of 112 D D C C Reserve Page B B A A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2019/09/20 2020/09/20 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Reserve Size R ev 1.0 FXXXX M/B LA-J871P Date: Document Number Tuesday, February 11, 2020 Sheet 101 of 112 A B C D E 1 @0@ PR1010 0_0402_5% Current limit = 4.7A(min) +3VALW PU1002 Rdown PR1012 20K_0402_1% VFB=0.6V Vout=0.6V* (1+Rup/Rdown) =0.6V* (1+13.7/20) Vout=1.011V EMI@ PC1008 680P_0402_50V7K FB=0.6V Note:Iload(max)=3A 2 PR1011 13.7K_0402_1% FB_1.0VSDGPUP +1.0VSDGPUP Choke 1uH SH00000YG00 (Common Part) (Size:3.8 x 3.8 x 1.9 mm) Isat:3.42A (DCR:20m~25m) Choke: SH00000YG00 Size:4x4x2 (Common Part) Rdc=27± 20% Taiyo Rdc=20mohm(Typ), 25mohm(Max) Cyntec Rdc=27± 20% 3L Rdc=30± 20% Tai-Tech Rdc=32± 20% Chilisin Rdc=36mohm(Typ), Xmohm(Max) Maglayers @ PC1011 22U_0603_6.3V6M Rup 2 SY8003ADFC_DFN8_2X2 22U_0603_6.3V6M EMI@ PR1007 4.7_0603_5% Ipeak=2.23A, Iocp:2.68A NC Imax=1.6A, PL1002 1UH_2.8A_30%_4X4X2_F LX_1.0VSDGPUP PC1010 22U_0603_6.3V6M PGND LX EN IN PC1013 PG PC1009 22U_0603_6.3V6M PGND SGND PC1012 68P_0402_50V8J VIN_1.0VSDGPUP FB @ PJ1001 JUMP_43X79 2 1 PG_1VSDGPU +3VALW @ PC1014 0.1U_0402_16V7K 1M_0402_5% PR1008 PR1009 10K_0402_5% 1VSDGPU_EN 1 EN_1VSDGPU +1.0VSDGPUP @ PJ1003 JUMP_43X79 2 +1.0VSDGPU 3 4 Compal Secret Data Security Classification Issued Date 2019/09/20 Deciphered Date 2020/09/20 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Size C Date: A B C D Compal Electronics, Inc 1.05VSDGPU Document Number Rev 1.0 FXXXX M/B LA-J871P Tuesday, February 11, 2020 Sheet E 102 of 112 D D C C Reserve Page B B A A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2019/09/20 2020/09/20 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Reserve Size R ev 1.0 FXXXX M/B LA-J871P Date: Document Number Tuesday, February 11, 2020 Sheet 103 of 112 D D C C Reserve Page B B A A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2019/09/20 2020/09/20 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Reserve Size R ev 1.0 FXXXX M/B LA-J871P Date: Document Number Tuesday, February 11, 2020 Sheet 104 of 112 D D C C Reserve Page B B A A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2019/09/20 2020/09/20 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Reserve Size R ev 1.0 FXXXX M/B LA-J871P Date: Document Number Tuesday, February 11, 2020 Sheet 105 of 112 D D C C Reserve Page B B A A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2019/09/20 2020/09/20 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Reserve Size R ev 1.0 FXXXX M/B LA-J871P Date: Document Number Tuesday, February 11, 2020 Sheet 106 of 112 D D C C Reserve Page B B A A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2019/09/20 2020/09/20 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Reserve Size R ev 1.0 FXXXX M/B LA-J871P Date: Document Number Tuesday, February 11, 2020 Sheet 107 of 112 D D C C Reserve Page B B A A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2019/09/20 2020/09/20 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Reserve Size R ev 1.0 FXXXX M/B LA-J871P Date: Document Number Tuesday, February 11, 2020 Sheet 108 of 112 D D C C Reserve Page B B A A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2019/09/20 2020/09/20 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Reserve Size R ev 1.0 FXXXX M/B LA-J871P Date: Document Number Tuesday, February 11, 2020 Sheet 109 of 112 Version change list (P.I.R List) Item 01 Fixed Issue Reason for change NA Page of for PWR PG# for cost down D 02 avoid incomplete replacement sourcer request NA 03 NA 04 NA NA P85 Date Phase PUZ1 change from ncp81215m_SA0000AQE00 to ncp81215p_SA0000CTW00 PCZ24, PCZ27 change from 82P_0402_SE000014700 to 82p_0402_SE071820J80 PCB17 change from 2.2u_0603_25V_SE00000WP00 to 2.2u_0603_16V_SE000006S80 PCB20 & PCB21 change from 100p_0603_SE024101J80 to 100p_0402_SE071101J80 PCM6 change from 10u_0603_SE000005T80 to 22u_0603_SE00000M000 PCM7 10u_0603_SE000005T80 change to unpop PRB12 change form 10_1206_SD011100A80 to 10_0805_SD002100A80 Modify List 1202 DVT PQB1 & PQB11 change from 2n7002_SB000009Q80 to 2n7002_SB00001GE00 1202 D DVT P84 PQ201 change from BSS139_SB00001GD00 to BSS138_SB00000PF00 1202 DVT P85 Add PRB37 & PRB38 & PRB39 0_0402_SD028000080 avoid chager B2B damage 1209 DVT 05 NA for acoustic noise P97 Co-lay PCV362~PCV369 10u_0603_SE00000X210 for acoustic noise 1209 DVT 06 NA for acoustic noise P100 Co-lay PCW24~PCW26 10u_0603_SE00000X210 for acoustic noise 1209 DVT 07 NA CPU transient P91 PRZ49 change from 274k_0402_SD034274380 to 165k_0402_SD034165380 PRZ14 change from 28k_0402_SD034280280 to 29.4k_0402_SD034294280 1212 DVT 08 NA CPU transient P95 1212 DVT 09 NA for efficiency P100 PCZ101 330u_D2_SGA00009S00 change to unpop for CFL PCZ102 & PCZ103 330u_D2_SGA00009S00 change to SMT for CFL PCZ108, PCZ109, PCZ110, PCZ112, PCZ119, PCZ125, PCZ133, PCZ137 change to SMT for CFL PCZ163, PCZ164, PCZ165, PCZ166, PCZ167, PCZ168 1u_0201_SE00000UC00 change to SMT for CFL PCZ107, PCZ113, PCZ114, PCZ115, PCZ116, PCZ121, PCZ123, PCZ127, PCZ128, PCZ130, PCZ131, PCZ132, PCZ172, PCZ173, PCZ174 change to unpop for CFL PCZ104, PCZ105, PCZ107, PCZ111, PCZ113, PCZ114, PCZ115, PCZ116, PCZ118, PCZ120, PCZ121, PCZ123, PCZ124, PCZ126, PCZ127, PCZ128, PCZ130, PCZ131, PCZ132, PCZ134, PCZ135, PCZ136, PCZ138, PCZ172, PCZ173, PCZ174 22u_0603_SE00000M000 change to unpop for CML PRW13 change from 383k_SD034383380 to 453k_SD034453380 1212 DVT 10 NA for DFB issue P85 PRB3 footprint change from R_1206_4P to R_1206_4P-D 0114 PVT C C 11 NA NA P100 reserve PCW28 & PCW29 330_D1_SGA00009S00 0114 PVT 12 NA NA P84 PH204 SL200002H00 change to SMT PH203 SL200002H00 change to unpop 0114 PVT 13 NA PR217,PRB22,PRB25,PRV50,PRV51,PRW9 change from 0_0402 to R-short 0114 PVT 14 NA P85 PRB19 footprint change from R_1206_4P to R_1206_4P-D 0116 PVT NA for DFB issue B B A A Compal Secret Data Security Classification Issued Date 2019/09/20 Deciphered Date 2020/09/20 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title PIR Size Document Number Custom R ev 1.0 FXXXX M/B LA-J871P Date: Compal Electronics, Inc Tuesday, February 11, 2020 Sheet 110 of 112 Version change list (P.I.R List) Item Fixed Issue Reason for change Page of for PWR PG# D 01 C Design Update For EA Turning and HW sequence 93, 94 95, 97 89, 92 Modify List Date change PR1009 from 100K_0402_5% (SD028100380) to 10K_0402_5% (SD028100280) change PG pull high from +3VS to +3VALW change PRW1 from 20K_0402_1% (SD034200280) to 1K_0402_1% (SD034100180) Change the PCW27 from pop to un-pop, and PCW27.2 net name change from +1.35VSDGPU to Vsense_+1.35VS_VGAP unpop PCV135 Change the PUV8, PCV9 from pop to un-pop Add location PRV51 0_0402_5% (SD028000080), and pop Change the PCW21, PCW22 From 4700P_0402_50V (SE074472K80) to 2200P_0402_50V(SE074222K80) Delete PL1111 (HCB2012KF-121T50_0805) Phase D 11/14 A 02 Design Update solution change 83, 85 90, 91 Change the PQB2,PQM2 from AON7506 (SB000010A00) to EMB12N03V (SB00001HV00) update location PRG5 PRA3 to PUG1 PUA1 PLZ1,PLG1,PLZ2,PLZ3,PLZ4 change to common part P/N (SH00001EE00) pop PQZ2, PQZ4 unpop PQZ1, PQZ3 11/16 A 03 Design Update ohm to R-short 83, 85 90, 91 Change PRM10, PRM8, PRV82, PRV85, PRV92, PRV95, PRV79, PRV81, PRV84, PRV89, PRV91, PRV94, PRV54, PRV56, PRV70, PRV145, PRV146, PRZ72, PRZ73, PRZ25, PRZ30, PRZ32, PRZ18, PRZ9, PRZ11, PRZ24, PRZ27,PRV20, PRV34 11/16 A 89, 92 change PRZ12 from 1.78K_0402_1%(SD00000WY80) to 1.62K_0402_1%(SD000003380) change PRZ14 from 31.6K_0402_1%(SD034316280) to 28K_0402_1%(SD034280280) change PCZ24 from 470P_0402_50V8J(SE071471J80) to 220P_0402_50V8J(SE082221J80) change PRZ51 from 84.5K_0603_1%(SD014845280) to 100K_0603_1%(SD014100380) PRZ61=110k ohm @H82, PRZ61=102k ohm @H62 PRZ35=25.5k ohm @H82, PRZ35=28k ohm @H62 unpop PCZ101, PCZ103, PCG102 pop PCZ176 un pop PCZ120, PCZ104, PCZ105, PCZ118, PCZ111, PCZ108, PCZ126, PCZ124 for H82 un pop PCZ120, PCZ104, CZ105, PCZ118, PCZ111, PCZ108, PCZ126, PCZ124, PCZ123, PCZ127, PCZ107, PCZ113, PCZ116, PCZ114 for H62 11/19 A C 04 Design Update For CPU transient 05 Design Update solution change 84 Change the PL501 1.5uH to common part Change the PCZ47, PCZ48, PCZ65, PCV36, PCV249 from 33U_25V_NC_6.3X4.5 (SF000007200) to 33U_25V_M (SF000007700) Chnage the PRZ43 from 12.1K_0402_1% (SD034121280) to 12K_0402_1% (SD034120280) 12/3 A 06 Design Update solution change 87 unpop PC1811 0.47U_0402_6.3V6K (SE124474K80) 12/12 B 07 Design Update solution change 83, 97 pop PCV149~PCV158, PCV162~PCV165, PCV258 (1U_0201_6.3V6M) reserve PDB2 for dead battery 12/18 B 08 Design Update solution change 87, 93, 94 Change PR1010, PRW9, PR1801, PR2501 from 0ohm to r-short 12/18 B 09 Design Update For ESD request 82 Pop PC205 0.1U_0603_25V7K coupling到 到 小到 到 fail 1/15 B 10 Design Update For EMI request 93, 96 Pop PCW1, PCV48 2200P_0402_50V7K (SE074222K80) for EMI request Pop PCW2, PCV47 0.1U_0402_25V6 (SE00000G880) for EMI request 1/15 B 11 Design Update Design change 90, 87 delete boost circuit and PCZ47 5/7 FH58F EVT 12 Design Update Design change 90, 87 delete PC1112 5/7 FH58F EVT 13 Design Update Design change 88, 93 change PCB15 from S CER CAP 1U 6.3V K X5R 0402(SE000000K80) to 1U 16V K X5R 0402(SE00000OU00) change PCB16 from S CER CAP 1U 6.3V K X5R 0402(SE000000K80) to S CER CAP 2.2U 16V K X5R 0402(SE000013780) Add PLV2, PLV3 second source S COIL 22UH TMPC1004H-R22MG-R5505-D 50A(SH00001XH00) 6/25 INV2 14 Design Update change CH_OC to 75A 6/25 FH58F PVT B B 95 (SE042104K80) HS 附 附 附 附 附 附 ,E SD 能能能能 HS小小小 HS cable change PRV71 from S RES 1/16W 133K +-1% 0402(SD034133380) to S RES 1/16W 113K +-1% 0402(SD034113380) A A Compal Secret Data Security Classification Issued Date 2019/09/20 Deciphered Date 2020/09/20 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title PIR Size Document Number Custom R ev 1.0 FXXXX M/B LA-J871P Date: Compal Electronics, Inc Tuesday, February 11, 2020 Sheet 111 of 112 A B C D Version change list (P.I.R List) Item Page 52 Page of for HW Title Date Issue Description Solution Description CNVi 1205B CNVi-Intel review (FH5VF) UART_BT review Add RM67 / RM68 0-ohm Add PU RM70 / PD RM69 (Reserve) RM66 Change to @ for Vender review 52 UART_BT 1205B 81-111 PWR SCH 1206A POWER update Combined Power SCH (1204) 40 HDMI 1206B HDMI EMI solution Remove RY52/RY53/CY27 , LS15 change to pop (EMI@) 17/69 JSSD3 1206B JSSD3 SATA/PCIE detect SATAGP change to GP4 & RH303 PU 64 EMR 1206B EMR Power source RH285/RH286/RH292 power source change to +3VALW 63 Touch Pad 1206B ESD Add CK203(100p) for ESD 27 VGA 1206C CLKREQ RV83 change to pop(VGA@) / CV226 change to unpop (@) 19 PROJECT ID 1206C PROJECT ID defined as Project - 50 ( ID1:H / ID0:L ) 10 38 11 16/58 12 13 73 Panel OD 1206C Panel OD function RX11 change to unpop & BIOS needs to detect panel to select H or L BT_ON 1206C BT_ON change to PCH RH304 pop (PCH) & RB85 unpop (EC) IO_B conn 15/68/69 M.2 SSD 1209A IO_B conn IO_B change pin define 1209B Fixed naming > SSD1 - GPP_B9/CLKREQ4# (PCIE only) (2018 @SSD2) > SSD2 - GPP_B8/CLKREQ3# (PCIE/SATA) (2018 @SSD1) > SSD3 - GPP_B10/CLKREQ5# (PCIE/SATA) (2019 NEW) 14 52 CNVi 1209B CNVi-Intel review (FH5VF) RM70 change power source to +3VS_WLAN 15 81-111 PWR SCH 1209C POWER update Combined Power SCH (1209) 16 81-111 PWR SCH 1210A POWER update Combined Power SCH (1209B) 17 77 H6 1210B For Layout H6 change to GNDA for Layout 18 69 SSD3 1210B BOM Config ADD "SSD3@" for BOM 19 58 Board ID 1210B Board ID config ADD DVT@ & DVTRGB@ for DVT BOM 20 52 CNVi 1210C CNVi-Intel review (FH51M) > > > > 21 63 ESD 1211B 22 63 SW 0114A BTN SW1 set EVT@ 23 58 0114A Action plan CB6/CB9 100P 0402 Change to SE00000SE00 (0201) 24 15 E Phase Rev RM69 change to 71.5k & CNVI@ RM70 set CNVI@ RH22 change to 20K RM36/RM37/RM67/RM68 change to 22 ohm > Pop CK203 680p & ESD@ > CB12/CB13 change to 33p for ESD & ESD@ PVT Rev 1.0 0114A Action plan CH7/CH8 10P 0402 Change to SE173100J80 (0201) 25 0114A Action plan RO25 Change to 0201 R-short 26 0114A Action plan RH100 Change to 0603 R-short 27 0114A Action plan RS112/RS137/RA9/RB87/RX8/RX9 Change to 0402 R-short 0114A CNVi-Intel review (FH5VF) Add CM51/CM52 10U Add CM53/CM54 0.01U Combined Power SCH (0114B) 28 52 29 81-111 30 63 31 81-111 CNVi PWR SCH 0114B POWER update 0115B Action plan POWER update R41 Change to 0603 R-short R18 Change to 0201 R-short *remove KBLED@ Combined Power SCH (0116) PWR SCH 0116A 32 CPU/PCH 0211A Update CPU/PCH PN & config 33 62 LED 0211A RG4/RG11 change to 1k 34 58 Board ID 0211A Board ID config ADD PVT@ & PVTRGB@ for PVT BOM 4 Compal Secret Data Security Classification Issued Date 2019/09/20 Deciphered Date 2020/09/20 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title PIR-HW1 Size Document Number Custom B C D R ev 1.0 FH51M M/B LA-J871P Date: A Compal Electronics, Inc Tuesday, February 11, 2020 Sheet E 112 of 112 ... SD03 415 02 80 SD034 200 2 80 SD0342 702 80 SD0343 302 80 SD0344 302 80 SD0345 602 80 SD0347 502 80 SD03 4 10 03 80 SD03 413 03 80 SD03 416 03 80 SD034 200 3 80 SD 000 001 B 80 SD 000 00G2 80 SD0343 303 80 SD 000 00WM 80 SD0345 603 80 SD 000 00AL 80. .. SD 000 00AL 80 STATE PCB Revision 50 Rev0 .1 50 Rev0 .2 50 Rev0 .3 50 Rev1 .0 50 Rev0 .2+RGB 50 Rev0 .3+RGB 50 Rev1 .0+ RGB 60 Rev0 .1 60 Rev0 .2 60 Rev0 .3 60 Rev1 .0 60 Rev0 .2+RGB 60 Rev0 .3+RGB 60 Rev1 .0+ RGB... GND 14 1 14 2 14 7 14 8 15 3 15 4 15 9 16 0 16 3 +1. 2V_VDDQ 258 +0. 6VS_VTT 257 259 +2.5V 99 10 2 10 3 10 6 10 7 16 7 16 8 17 1 17 2 17 5 17 6 18 0 18 1 18 4 18 5 18 8 18 9 19 2 19 3 19 6 19 7 2 01 202 205 206 209 2 10 213 214