A I I B I C I D E Compal Confidential V15 /DH5VF V17 /DH7VF Vxl 5/DH53F Vxl 7/DH73F * MB Schematic Document Intel CoffeeLake H Nvidia N17P-G0/G1 LA-F 951P 3 Rev: lA 2018.02.22 4 Compal Secret Data Security Classification 2017/12 /18 Issued Date Deciphered Date 2018/09 / 01 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R8D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITFER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C D Title Size Sustorr Date : Cnmpnl Electronics, Inc Cover Sheet Document Number - DH5 VF M/ B LA F591PR01 Thursday, February 22, 2018 Rev 1.0 ISheet E of 67 BOM Structure Table BOM Option Table BOM Structure VX15@ SATA HDD W REDRIVER SATA HDD WO REDRIVER NV N17P-G0(1050) NV N17P-G1(1050TI) i5 CPU i7 CPU I5QP89 PG1 4G 32HDMI I78750 PG1 4G 32HDMI X76730BOL51 X76730BOL52 X76730BOL53 X76730BOL54 X76730BOL55 SAMSUNG1280 HYNLX1280 SAMSUNG2560 HYNIX2560 MICRON2560 SATARD@ SATANRD@ G0@ G1@ i5@ i7@ +VCCIO +VCC_SA +1.8VSDGPU_AON +1.8VSDGPU_MAIN +1.8VGA_CORE +1.35VSDGPU UQ2 RH92 RH94 +1.8VS +1.05VALW_PRIM PCH +1.05VALW_PCH PCH RH102 RH103 RH105 +19VB -> +19V_CPU LX1 PCH A B DH5VF_EVT Power Sequence C D E AC mode BIOS ver: V0.02W1 EC: ver: V002AT04 1 Plug in Power On S3 S3 Resume Power Off +3VLP +3VLP EC_ON +5VALW EC_ON → 330.8ms → 333.3ms +5VALW ON/OFFBTN# ON/OFFBTN# → 92.03ms → 94.88ms +3VALW +1.05VALW EC_RSMRST# PBTN_OUT# PM_SLP_S4# PM_SLP_S3# SYSON +1.05V_VCCST +1.2V_VDDQ +2.5VS SUSP# +1.05VS_VCCSTG +5VS +3VS +1.8VS EC_VCCST_PG SM_PG_CTRL +0.6VS_VTT VR_ON +VCC_SA +VCC_CORE +VCC_GT PCH_PWROK SYS_PWROK PLT_RST# → +3VALW → 293.7us +1.05VALW 29.19ms 2.439ms → 174.6ms EC_RSMRST# 20.1ms ← → PBTN_OUT# → 19.18ms → 19.22ms → 72.1us → 275.9us → 692.9us → 910.1us → 12.7ms PM_SLP_S4# 100.5us → → → → → → 8.378us → 877.7us → 630.4us → 412us → 25.34ms 25.35ms → 25.36ms → 25.19ms → → → → → → → → 13.01us → 55.47us → 618.5us → 8.679ms → 347.6us → 0us → 0us → 3.819ms → → → → → → 1.759ms 173.0ms NA 12.42ms 150.3ms 152.3ms → → → → → → → → → 26.91us → 67.04ms 87.75us NA 47.39us 61.95us 318.7us SYSON 88.37us 906.0us 656.1us 367.6us +1.2V_VDDQ 2.266ms +2.5VS 13us 424.9us SUSP# +1.05VS_VCCSTG +5VS +3VS 446.2us 25.25ms +1.8VS 0us → → 25.25ms 25.26ms EC_VCCST_PG 13.97ms SM_PG_CTRL 2.034ms +0.6VS_VTT → 27.06us → 48.00us → 112.0us 25.59ms 1.757ms 167.1ms NA VR_ON +VCC_SA +VCC_CORE NA → → 12.18ms 150.6ms +1.05V_VCCST → 68.53us → 686.0us 11.65ms → 8.502us → → → → → → 51.25us PM_SLP_S3# 152.8us +VCC_GT 47.83us PCH_PWROK 62.37us SYS_PWROK 151.8ms PLT_RST# 4 Compal Secret Data Security Classification Issued Date 2017/12/18 Deciphered Date 2018/09/01 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title B C D Rev 1.0 DH5VF M/B LA-F591PR01 Date: A Compal Electronics, Inc Power Sequence Size Document Number Custom Thursday, February 22, 2018 E Sheet of 67 2.2K 2.2K +3VALW_PCH_PRIM +3VS PCH_SMBCLK (QH7) 2N7002DW PCH_SML0CLK 499 PCH_SML0DATA 499 2.2K Skylake-H PCH 2.2K D_CK_SDATA +3VS SO-DIMM A & B G-Sensor +3VALW_PCH_PRIM 1.8K +3VALW_PCH_PRIM I2CB_SCL VGA_I2CS_SCL EC_SMB_CK2 (RH189/RH190) R-short PCH_SML1DATA (QV2) PJT138KA EC_SMB_DA2 I2CB_SDA VGA_I2CS_SDA 2K N17P-G0 N17P-G1 2.2K 2.2K +3VLP_EC EC_SMB_CK1 100 ohm EC_SMB_CK1-1 EC_SMB_DA1 100 ohm EC_SMB_DA1-1 ohm ohm EC_SMB_CK1_CHGR EC_SMB_DA1_CHGR BATTERY (co-lay) CONN 2N7002 R-Short +1.8VSDGPU_AON 2K +1.8VSDGPU_MAIN PCH_SML1CLK D 2K +1.8VSDGPU_AON 1.8K 2.2K KB9022 D_CK_SCLK PCH_SMBDATA D 2.2K I2CC_SDA 179F_SMB_CK2 179F_SMB_DA2 +1.8VSDGPU_AON 2K I2CC_SCL USB CC EJ179F 2.2K Charger +3VS 2.2K +3VS EC_SMB_CK2 (QF1) 2N7002DW EC_SMB_DA2 C TMS_SMB_CLK TMS_SMB_DATA THERMAL SENSOR C B B A A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2017/12/18 Deciphered Date 2018/09/01 THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC Title N17E-GDDR5_D Size Document Number Rev 1.0 DH5VF M/B LA-F591PR01 Date: Thursday, February 22, 2018 Sheet of 67 A B C D E CO-LAY FOR VGA OUTPUT RG183 RG184 RG185 RG186 RG187 RG188 RG189 RG190 GPU_EDP_TXP0 GPU_EDP_TXN0 GPU_EDP_TXP1 GPU_EDP_TXN1 GPU_EDP_TXP2 GPU_EDP_TXN2 GPU_EDP_TXP3 GPU_EDP_TXN3 1 1 1 1 2 2 2 2 @ @ @ @ @ @ @ @ 1 RG191 RG192 GPU_EDP_AUXP GPU_EDP_AUXN 0_0201_5% 0_0201_5% 0_0201_5% 0_0201_5% 0_0201_5% 0_0201_5% 0_0201_5% 0_0201_5% @ @ 0_0201_5% 0_0201_5% EDP_AUXP EDP_AUXN CFL-H UC1D K36 K37 J35 J34 H37 H36 J37 J38 D27 E27 H34 H33 F37 G38 F34 F35 E37 E36 F26 E26 C34 D34 B36 B34 F33 E33 C33 B33 Coffee Lake-H CPU SKU UC1 UC1 A27 B27 I7@ I5@ CFL-H 2.3G BGA CFL-H 2.2G BGA SA0000BPJ40 SA0000BPZ40 DDI1_TXP_0 DDI1_TXN_0 DDI1_TXP_1 DDI1_TXN_1 DDI1_TXP_2 DDI1_TXN_2 DDI1_TXP_3 DDI1_TXN_3 EDP_TXP_0 EDP_TXN_0 EDP_TXP_1 EDP_TXN_1 EDP_TXP_2 EDP_TXN_2 EDP_TXP_3 EDP_TXN_3 DDI1_AUXP DDI1_AUXN EDP_AUXP EDP_AUXN DDI2_TXP_0 DDI2_TXN_0 DDI2_TXP_1 DDI2_TXN_1 DDI2_TXP_2 DDI2_TXN_2 DDI2_TXP_3 DDI2_TXN_3 EDP_DISP_UTIL DISP_RCOMP D29 E29 F28 E28 A29 B29 C28 B28 EDP_TXP0 EDP_TXN0 EDP_TXP1 EDP_TXN1 EDP_TXP2 EDP_TXN2 EDP_TXP3 EDP_TXN3 C26 B26 EDP_AUXP EDP_AUXN EDP_TXP0 EDP_TXN0 EDP_TXP1 EDP_TXN1 EDP_TXP2 EDP_TXN2 EDP_TXP3 EDP_TXN3 EDP_AUXP EDP_AUXN eDP +VCCIO A33 D37 DP_RCOMP RC1 24.9_0402_1% Trace Width/Space: 15 mil/ 20 mil Max Trace Length: 600 mil DDI2_AUXP DDI2_AUXN DDI3_TXP_0 DDI3_TXN_0 DDI3_TXP_1 DDI3_TXN_1 DDI3_TXP_2 DDI3_TXN_2 DDI3_TXP_3 DDI3_TXN_3 DDI3_AUXP DDI3_AUXN PROC_AUDIO_CLK PROC_AUDIO_SDI ofPROC_AUDIO_SDO 13 G27 G25 G29 CPU_DISPA_SDI RC2 20_0402_5% CPU_DISPA_BCLK_R CPU_DISPA_SDO_R CPU_DISPA_SDI_R CPU_DISPA_BCLK_R CPU_DISPA_SDO_R CPU_DISPA_SDI_R follow CRB CFL-H_BGA1440 Cannon Lake PCH SKU UH1 QNDQ@ CNP-H_BGA874 SA0000BVP10 NV N17P SKU UV1 UV1 4 G0@ N17P-G0-A1 SA0000A0540 G1@ N17P-G1-A1 SA0000A0660 Compal Secret Data Security Classification 2017/12/18 Issued Date Deciphered Date 2018/09/01 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Size Document Number Custom B C D Rev 1.0 DH5VF M/B LA-F591PR01 Date: A Compal Electronics, Inc CFL-H(1/8)DDI/eDP Thursday, February 22, 2018 Sheet E of 67 A B C D E CHANNEL-A Interleaved Memory CFL-H UC1A DDR CHANNEL A DDR_A_D[0 63] DDR4(IL)/LP3-DDR4(NIL) DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63 BR6 BT6 BP3 BR3 BN5 BP6 BP2 BN3 BL4 BL5 BL2 BM1 BK4 BK5 BK1 BK2 BG4 BG5 BF4 BF5 BG2 BG1 BF1 BF2 BD2 BD1 BC4 BC5 BD5 BD4 BC1 BC2 AB1 AB2 AA4 AA5 AB5 AB4 AA2 AA1 V5 V2 U1 U2 V1 V4 U5 U4 R2 P5 R4 P4 R5 P2 R1 P1 M4 M1 L4 L2 M5 M2 L5 L1 BA2 BA1 AY4 AY5 BA5 BA4 AY1 AY2 For ECC DIMM LP3/DDR4 DDR0_DQ_0/DDR0_DQ_0 DDR0_CKP_0/DDR0_CKP_0 DDR0_DQ_1/DDR0_DQ_1 DDR0_CKN_0/DDR0_CKN_0 DDR0_DQ_2/DDR0_DQ_2 DDR0_CKP_1/DDR0_CKP_1 DDR0_DQ_3/DDR0_DQ_3 DDR0_CKN_1/DDR0_CKN_1 DDR0_DQ_4/DDR0_DQ_4 NC/DDR0_CKP_2 DDR0_DQ_5/DDR0_DQ_5 NC/DDR0_CKN_2 DDR0_DQ_6/DDR0_DQ_6 NC/DDR0_CKP_3 DDR0_DQ_7/DDR0_DQ_7 NC/DDR0_CKN_3 DDR0_DQ_8/DDR0_DQ_8 DDR0_DQ_9/DDR0_DQ_9 DDR0_CKE_0/DDR0_CKE_0 DDR0_DQ_10/DDR0_DQ_10 DDR0_CKE_1/DDR0_CKE_1 DDR0_DQ_11/DDR0_DQ_11 DDR0_CKE_2/DDR0_CKE_2 DDR0_DQ_12/DDR0_DQ_12 DDR0_CKE_3/DDR0_CKE_3 DDR0_DQ_13/DDR0_DQ_13 DDR0_DQ_14/DDR0_DQ_14 DDR0_CS#_0/DDR0_CS#_0 DDR0_DQ_15/DDR0_DQ_15 DDR0_CS#_1/DDR0_CS#_1 DDR0_DQ_16/DDR0_DQ_32 NC/DDR0_CS#_2 DDR0_DQ_17/DDR0_DQ_33 NC/DDR0_CS#_3 DDR0_DQ_18/DDR0_DQ_34 DDR0_DQ_19/DDR0_DQ_35 DDR0_ODT_0/DDR0_ODT_0 DDR0_DQ_20/DDR0_DQ_36 NC/DDR0_ODT_1 DDR0_DQ_21/DDR0_DQ_37 NC/DDR0_ODT_2 DDR0_DQ_22/DDR0_DQ_38 NC/DDR0_ODT_3 DDR0_DQ_23/DDR0_DQ_39 DDR0_DQ_24/DDR0_DQ_40 DDR0_CAB_4/DDR0_BA_0 DDR0_DQ_25/DDR0_DQ_41 DDR0_CAB_6/DDR0_BA_1 DDR0_DQ_26/DDR0_DQ_42 DDR0_CAA_5/DDR0_BG_0 DDR0_DQ_27/DDR0_DQ_43 DDR0_DQ_28/DDR0_DQ_44 DDR0_CAB_3/DDR0_MA_16 DDR0_DQ_29/DDR0_DQ_45 DDR0_CAB_2/DDR0_MA_14 DDR0_DQ_30/DDR0_DQ_46 DDR0_CAB_1/DDR0_MA_15 DDR0_DQ_31/DDR0_DQ_47 DDR0_DQ_32/DDR1_DQ_0 DDR0_CAB_9/DDR0_MA_0 DDR0_CAB_8/DDR0_MA_1 DDR0_DQ_33/DDR1_DQ_1 DDR0_CAB_5/DDR0_MA_2 DDR0_DQ_34/DDR1_DQ_2 DDR0_DQ_35/DDR1_DQ_3 NC/DDR0_MA_3 DDR0_DQ_36/DDR1_DQ_4 NC/DDR0_MA_4 DDR0_DQ_37/DDR1_DQ_5 DDR0_CAA_0/DDR0_MA_5 DDR0_CAA_2/DDR0_MA_6 DDR0_DQ_38/DDR1_DQ_6 DDR0_DQ_39/DDR1_DQ_7 DDR0_CAA_4/DDR0_MA_7 DDR0_DQ_40/DDR1_DQ_8 DDR0_CAA_3/DDR0_MA_8 DDR0_DQ_41/DDR1_DQ_9 DDR0_CAA_1/DDR0_MA_9 DDR0_DQ_42/DDR1_DQ_10 DDR0_CAB_7/DDR0_MA_10 DDR0_DQ_43/DDR1_DQ_11 DDR0_CAA_7/DDR0_MA_11 DDR0_DQ_44/DDR1_DQ_12 DDR0_CAA_6/DDR0_MA_12 DDR0_DQ_45/DDR1_DQ_13 DDR0_CAB_0/DDR0_MA_13 DDR0_DQ_46/DDR1_DQ_14 DDR0_CAA_9/DDR0_BG_1 DDR0_DQ_47/DDR1_DQ_15 DDR0_CAA_8/DDR0_ACT# DDR0_DQ_48/DDR1_DQ_32 DDR0_DQ_49/DDR1_DQ_33 NC/DDR0_PAR DDR0_DQ_50/DDR1_DQ_34 NC/DDR0_ALERT# DDR0_DQ_51/DDR1_DQ_35 DDR4(IL)/LP3-DDR4(NIL) DDR0_DQ_52/DDR1_DQ_36 DDR0_DQ_53/DDR1_DQ_37DDR0_DQSN_0/DDR0_DQSN_0 DDR0_DQ_54/DDR1_DQ_38DDR0_DQSN_1/DDR0_DQSN_1 DDR0_DQ_55/DDR1_DQ_39DDR0_DQSN_2/DDR0_DQSN_4 DDR0_DQ_56/DDR1_DQ_40DDR0_DQSN_3/DDR0_DQSN_5 DDR0_DQ_57/DDR1_DQ_41DDR0_DQSN_4/DDR1_DQSN_0 DDR0_DQ_58/DDR1_DQ_42DDR0_DQSN_5/DDR1_DQSN_1 DDR0_DQ_59/DDR1_DQ_43DDR0_DQSN_6/DDR1_DQSN_4 DDR0_DQ_60/DDR1_DQ_44DDR0_DQSN_7/DDR1_DQSN_5 DDR0_DQ_61/DDR1_DQ_45 DDR0_DQ_62/DDR1_DQ_46DDR0_DQSP_0/DDR0_DQSP_0 DDR0_DQ_63/DDR1_DQ_47DDR0_DQSP_1/DDR0_DQSP_1 DDR0_DQSP_2/DDR0_DQSP_4 LP3/DDR4 DDR0_DQSP_3/DDR0_DQSP_5 NC/DDR0_ECC_0 DDR0_DQSP_4/DDR1_DQSP_0 NC/DDR0_ECC_1 DDR0_DQSP_5/DDR1_DQSP_1 DDR0_DQSP_6/DDR1_DQSP_4 NC/DDR0_ECC_2 NC/DDR0_ECC_3 DDR0_DQSP_7/DDR1_DQSP_5 NC/DDR0_ECC_4 NC/DDR0_ECC_5 DDR0_DQSP_8/DDR0_DQSP_8 NC/DDR0_ECC_6 OFDDR0_DQSN_8/DDR0_DQSN_8 13 NC/DDR0_ECC_7 AG1 AG2 AK2 AK1 AL3 AK3 AL2 AL1 DDR_A_CLK0 DDR_A_CLK#0 DDR_A_CLK1 DDR_A_CLK#1 AT1 AT2 AT3 AT5 DDR_A_CKE0 DDR_A_CKE1 AD5 AE2 AD2 AE5 DDR_A_CS#0 DDR_A_CS#1 AD3 AE4 AE1 AD4 DDR_A_ODT0 DDR_A_ODT1 AH5 AH1 AU1 DDR_A_BA0 DDR_A_BA1 DDR_A_BG0 AH4 AG4 AD1 DDR_A_MA16_RAS# DDR_A_MA14_W E# DDR_A_MA15_CAS# AH3 AP4 AN4 AP5 AP2 AP1 AP3 AN1 AN3 AT4 AH2 AN2 AU4 AE3 AU2 AU3 DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_BG1 DDR_A_ACT# AG3 AU5 DDR_A_PAR DDR_A_ALERT# BR5 BL3 BG3 BD3 AA3 U3 P3 L3 DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7 BP5 BK3 BF3 BC3 AB3 V3 R3 M3 DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7 AY3 BA3 DDR_A_CLK0 DDR_A_CLK#0 DDR_A_CLK1 DDR_A_CLK#1 DDR_A_CKE0 DDR_A_CKE1 DDR_A_CS#0 DDR_A_CS#1 DDR_A_ODT0 DDR_A_ODT1 DDR_A_BA0 DDR_A_BA1 DDR_A_BG0 DDR_A_MA16_RAS# DDR_A_MA14_W E# DDR_A_MA15_CAS# DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_BG1 DDR_A_ACT# DDR_A_PAR DDR_A_ALERT# DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7 DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7 For ECC DIMM CFL-H_BGA1440 4 Compal Secret Data Security Classification 2017/12/18 Issued Date Deciphered Date 2018/09/01 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title B C D CFL-H(2/8)DIMMA Size Document Number Custom Rev 1.0 DH5VF M/B LA-F591PR01 Date: A Compal Electronics, Inc Thursday, February 22, 2018 Sheet E of 67 A B C D E CHANNEL-B Interleaved Memory CFL-H UC1B DDR_B_D[0 63] DDR CHANNEL B DDR4(IL)/LP3-DDR4(NIL) DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 BT11 BR11 BT9 BR8 BP11 BN11 BP8 BN8 BL12 BL11 BL8 BJ8 BJ11 BJ10 BL7 BJ7 BG11 BG10 BG8 BF8 BF11 BF10 BG7 BF7 BB11 BC11 BB8 BC8 BC10 BB10 BC7 BB7 AA11 AA10 AC11 AC10 AA7 AA8 AC8 AC7 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63 W8 W7 V10 V11 W11 W10 V7 V8 R11 P11 P7 R8 R10 P10 R7 P8 L11 M11 L7 M8 L10 M10 M7 L8 AW11 AY11 AY8 AW8 AY10 AW10 AY7 AW7 For ECC DIMM RC3 RC4 RC5 121_0402_1% SM_RCOMP0 75_0402_1% SM_RCOMP1 100_0402_1% SM_RCOMP2 1 Trace Width/Space: 15 mil/ 25 mil Max Trace Length: 500 mil G1 H1 J2 LP3/DDR4 DDR1_DQ_0/DDR0_DQ_16 DDR1_DQ_1/DDR0_DQ_17 DDR1_DQ_2/DDR0_DQ_18 DDR1_DQ_3/DDR0_DQ_19 DDR1_DQ_4/DDR0_DQ_20 DDR1_DQ_5/DDR0_DQ_21 DDR1_DQ_6/DDR0_DQ_22 DDR1_DQ_7/DDR0_DQ_23 DDR1_DQ_8/DDR0_DQ_24 DDR1_DQ_9/DDR0_DQ_25 DDR1_DQ_10/DDR0_DQ_26 DDR1_DQ_11/DDR0_DQ_27 DDR1_DQ_12/DDR0_DQ_28 DDR1_DQ_13/DDR0_DQ_29 DDR1_DQ_14/DDR0_DQ_30 DDR1_DQ_15/DDR0_DQ_31 DDR1_DQ_16/DDR0_DQ_48 DDR1_DQ_17/DDR0_DQ_49 DDR1_DQ_18/DDR0_DQ_50 DDR1_DQ_19/DDR0_DQ_51 DDR1_DQ_20/DDR0_DQ_52 DDR1_DQ_21/DDR0_DQ_53 DDR1_DQ_22/DDR0_DQ_54 DDR1_DQ_23/DDR0_DQ_55 DDR1_DQ_24/DDR0_DQ_56 DDR1_DQ_25/DDR0_DQ_57 DDR1_DQ_26/DDR0_DQ_58 DDR1_DQ_27/DDR0_DQ_59 DDR1_DQ_28/DDR0_DQ_60 DDR1_DQ_29/DDR0_DQ_61 DDR1_DQ_30/DDR0_DQ_62 DDR1_DQ_31/DDR0_DQ_63 DDR1_DQ_32/DDR1_DQ_16 DDR1_DQ_33/DDR1_DQ_17 DDR1_DQ_34/DDR1_DQ_18 DDR1_DQ_35/DDR1_DQ_19 DDR1_DQ_36/DDR1_DQ_20 DDR1_DQ_37/DDR1_DQ_21 DDR1_DQ_38/DDR1_DQ_22 DDR1_DQ_39/DDR1_DQ_23 DDR1_CKP_0/DDR1_CKP_0 DDR1_CKN_0/DDR1_CKN_0 DDR1_CKP_1/DDR1_CKP_1 DDR1_CKN_1/DDR1_CKN_1 NC/DDR1_CKP_2 NC/DDR1_CKN_2 NC/DDR1_CKP_3 NC/DDR1_CKN_3 DDR1_CKE_0/DDR1_CKE_0 DDR1_CKE_1/DDR1_CKE_1 DDR1_CKE_2/DDR1_CKE_2 DDR1_CKE_3/DDR1_CKE_3 DDR1_CS#_0/DDR1_CS#_0 DDR1_CS#_1/DDR1_CS#_1 NC/DDR1_CS#_2 NC/DDR1_CS#_3 DDR1_ODT_0/DDR1_ODT_0 NC/DDR1_ODT_1 NC/DDR1_ODT_2 NC/DDR1_ODT_3 DDR1_CAB_3/DDR1_MA_16 DDR1_CAB_2/DDR1_MA_14 DDR1_CAB_1/DDR1_MA_15 DDR1_CAB_4/DDR1_BA_0 DDR1_CAB_6/DDR1_BA_1 DDR1_CAA_5/DDR1_BG_0 DDR1_CAB_9/DDR1_MA_0 DDR1_CAB_8/DDR1_MA_1 DDR1_CAB_5/DDR1_MA_2 NC/DDR1_MA_3 NC/DDR1_MA_4 DDR1_CAA_0/DDR1_MA_5 DDR1_CAA_2/DDR1_MA_6 DDR1_CAA_4/DDR1_MA_7 DDR4(IL)/LP3-DDR4(NIL) DDR1_DQ_40/DDR1_DQ_24 DDR1_CAA_3/DDR1_MA_8 DDR1_CAA_1/DDR1_MA_9 DDR1_DQ_41/DDR1_DQ_25 DDR1_DQ_42/DDR1_DQ_26 DDR1_CAB_7/DDR1_MA_10 DDR1_DQ_43/DDR1_DQ_27 DDR1_CAA_7/DDR1_MA_11 DDR1_DQ_44/DDR1_DQ_28 DDR1_CAA_6/DDR1_MA_12 DDR1_DQ_45/DDR1_DQ_29 DDR1_CAB_0/DDR1_MA_13 DDR1_DQ_46/DDR1_DQ_30 DDR1_CAA_9/DDR1_BG_1 DDR1_CAA_8/DDR1_ACT# DDR1_DQ_47/DDR1_DQ_31 DDR1_DQ_48/DDR1_DQ_48 DDR1_DQ_49/DDR1_DQ_49 NC/DDR1_PAR DDR1_DQ_50/DDR1_DQ_50 NC/DDR1_ALERT# DDR1_DQ_51/DDR1_DQ_51 DDR4(IL)/LP3-DDR4(NIL) DDR1_DQ_52/DDR1_DQ_52 DDR1_DQ_53/DDR1_DQ_53DDR1_DQSN_0/DDR0_DQSN_2 DDR1_DQ_54/DDR1_DQ_54DDR1_DQSN_1/DDR0_DQSN_3 DDR1_DQ_55/DDR1_DQ_55DDR1_DQSN_2/DDR0_DQSN_6 DDR1_DQ_56/DDR1_DQ_56DDR1_DQSN_3/DDR0_DQSN_7 DDR1_DQ_57/DDR1_DQ_57DDR1_DQSN_4/DDR1_DQSN_2 DDR1_DQ_58/DDR1_DQ_58DDR1_DQSN_5/DDR1_DQSN_3 DDR1_DQ_59/DDR1_DQ_59DDR1_DQSN_6/DDR1_DQSN_6 DDR1_DQ_60/DDR1_DQ_60DDR1_DQSN_7/DDR1_DQSN_7 DDR1_DQ_61/DDR1_DQ_61 DDR1_DQ_62/DDR1_DQ_62DDR1_DQSP_0/DDR0_DQSP_2 DDR1_DQ_63/DDR1_DQ_63DDR1_DQSP_1/DDR0_DQSP_3 DDR1_DQSP_2/DDR0_DQSP_6 LP3/DDR4 NC/DDR1_ECC_0 DDR1_DQSP_3/DDR0_DQSP_7 DDR1_DQSP_4/DDR1_DQSP_2 NC/DDR1_ECC_1 NC/DDR1_ECC_2 DDR1_DQSP_5/DDR1_DQSP_3 NC/DDR1_ECC_3 DDR1_DQSP_6/DDR1_DQSP_6 NC/DDR1_ECC_4 DDR1_DQSP_7/DDR1_DQSP_7 NC/DDR1_ECC_5 DDR1_DQSP_8/DDR1_DQSP_8 NC/DDR1_ECC_6 NC/DDR1_ECC_7 DDR1_DQSN_8/DDR1_DQSN_8 DDR_RCOMP_0 DDR_RCOMP_1 DDR_RCOMP_2 DDR_VREF_CA DDR0_VREF_DQ DDR1_VREF_DQ OF 13 AM9 AN9 AM7 AM8 AM11 AM10 AJ10 AJ11 DDR_B_CLK0 DDR_B_CLK#0 DDR_B_CLK1 DDR_B_CLK#1 AT8 AT10 AT7 AT11 DDR_B_CKE0 DDR_B_CKE1 AF11 AE7 AF10 AE10 DDR_B_CS#0 DDR_B_CS#1 AF7 AE8 AE9 AE11 DDR_B_ODT0 DDR_B_ODT1 AH10 AH11 AF8 DDR_B_MA16_RAS# DDR_B_MA14_W E# DDR_B_MA15_CAS# AH8 AH9 AR9 DDR_B_BA0 DDR_B_BA1 DDR_B_BG0 AJ9 AK6 AK5 AL5 AL6 AM6 AN7 AN10 DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 AN8 AR11 AH7 AN11 AR10 AF9 AR7 AT9 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_BG1 DDR_B_ACT# AJ7 AR8 DDR_B_PAR DDR_B_ALERT# BN9 BL9 BG9 BC9 AC9 W9 R9 M9 DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7 BP9 BJ9 BF9 BB9 AA9 V9 P9 L9 DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7 AW9 AY9 BN13 BP13 BR13 DDR_B_CLK0 DDR_B_CLK#0 DDR_B_CLK1 DDR_B_CLK#1 DDR_B_CKE0 DDR_B_CKE1 DDR_B_CS#0 DDR_B_CS#1 DDR_B_ODT0 DDR_B_ODT1 DDR_B_MA16_RAS# DDR_B_MA14_W E# DDR_B_MA15_CAS# DDR_B_BA0 DDR_B_BA1 DDR_B_BG0 DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_BG1 DDR_B_ACT# DDR_B_PAR DDR_B_ALERT# DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7 DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7 For ECC DIMM +0.6V_VREFCA +0.6V_B_VREFDQ +0.6V_VREFCA +0.6V_B_VREFDQ CFL-H_BGA1440 4 Compal Secret Data Security Classification 2017/12/18 Issued Date Deciphered Date 2018/09/01 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title B C D CFL-H(3/8)DIMMB Size Document Number Custom Rev 1.0 DH5VF M/B LA-F591PR01 Date: A Compal Electronics, Inc Thursday, February 22, 2018 Sheet E of 67 A B C D E PEG&DMI To DGPU PEG Lane Reversed CC1 CC3 VGA@ VGA@ 0.22U_0201_6.3V6K 0.22U_0201_6.3V6K PEG_CRX_GTX_P15 PEG_CRX_GTX_N15 E25 D25 PEG_CRX_C_GTX_P14 PEG_CRX_C_GTX_N14 CC5 CC6 VGA@ VGA@ 0.22U_0201_6.3V6K 0.22U_0201_6.3V6K PEG_CRX_GTX_P14 PEG_CRX_GTX_N14 E24 F24 PEG_CRX_C_GTX_P13 PEG_CRX_C_GTX_N13 CC7 VGA@ CC14 VGA@ 0.22U_0201_6.3V6K 0.22U_0201_6.3V6K PEG_CRX_GTX_P13 PEG_CRX_GTX_N13 E23 D23 PEG_CRX_C_GTX_P12 PEG_CRX_C_GTX_N12 CC16 VGA@ CC17 VGA@ 0.22U_0201_6.3V6K 0.22U_0201_6.3V6K PEG_CRX_GTX_P12 PEG_CRX_GTX_N12 E22 F22 E21 D21 PEG_CRX_C_GTX_P11 PEG_CRX_C_GTX_N11 CC19 VGA@ CC20 VGA@ 0.22U_0201_6.3V6K 0.22U_0201_6.3V6K PEG_CRX_GTX_P11 PEG_CRX_GTX_N11 PEG_CRX_C_GTX_P10 PEG_CRX_C_GTX_N10 CC10 VGA@ CC23 VGA@ 0.22U_0201_6.3V6K 0.22U_0201_6.3V6K PEG_CRX_GTX_P10 PEG_CRX_GTX_N10 E20 F20 PEG_CRX_C_GTX_P9 PEG_CRX_C_GTX_N9 CC25 VGA@ CC27 VGA@ 0.22U_0201_6.3V6K 0.22U_0201_6.3V6K PEG_CRX_GTX_P9 PEG_CRX_GTX_N9 E19 D19 PEG_CRX_C_GTX_P8 PEG_CRX_C_GTX_N8 CC29 VGA@ CC31 VGA@ 0.22U_0201_6.3V6K 0.22U_0201_6.3V6K PEG_CRX_GTX_P8 PEG_CRX_GTX_N8 E18 F18 PEG_CRX_C_GTX_P7 PEG_CRX_C_GTX_N7 CC33 VGA@ CC35 VGA@ 0.22U_0201_6.3V6K 0.22U_0201_6.3V6K PEG_CRX_GTX_P7 PEG_CRX_GTX_N7 D17 E17 PEG_CRX_C_GTX_P6 PEG_CRX_C_GTX_N6 CC37 VGA@ CC39 VGA@ 0.22U_0201_6.3V6K 0.22U_0201_6.3V6K PEG_CRX_GTX_P6 PEG_CRX_GTX_N6 F16 E16 PEG_CRX_C_GTX_P5 PEG_CRX_C_GTX_N5 CC41 VGA@ CC43 VGA@ 0.22U_0201_6.3V6K 0.22U_0201_6.3V6K PEG_CRX_GTX_P5 PEG_CRX_GTX_N5 D15 E15 PEG_CRX_C_GTX_P4 PEG_CRX_C_GTX_N4 CC45 VGA@ CC47 VGA@ 0.22U_0201_6.3V6K 0.22U_0201_6.3V6K PEG_CRX_GTX_P4 PEG_CRX_GTX_N4 F14 E14 PEG_CRX_C_GTX_P3 PEG_CRX_C_GTX_N3 CC49 VGA@ CC51 VGA@ 0.22U_0201_6.3V6K 0.22U_0201_6.3V6K PEG_CRX_GTX_P3 PEG_CRX_GTX_N3 D13 E13 PEG_CRX_C_GTX_P2 PEG_CRX_C_GTX_N2 CC53 VGA@ CC55 VGA@ 0.22U_0201_6.3V6K 0.22U_0201_6.3V6K PEG_CRX_GTX_P2 PEG_CRX_GTX_N2 F12 E12 PEG_CRX_C_GTX_P1 PEG_CRX_C_GTX_N1 CC57 VGA@ CC59 VGA@ 0.22U_0201_6.3V6K 0.22U_0201_6.3V6K PEG_CRX_GTX_P1 PEG_CRX_GTX_N1 D11 E11 PEG_CRX_C_GTX_P0 PEG_CRX_C_GTX_N0 CC61 VGA@ CC63 VGA@ 0.22U_0201_6.3V6K 0.22U_0201_6.3V6K PEG_CRX_GTX_P0 PEG_CRX_GTX_N0 F10 E10 UC1C PEG_CRX_C_GTX_P15 PEG_CRX_C_GTX_N15 To DGPU PEG Lane Reversed CFL-H PEG_RXP_0 PEG_RXN_0 PEG_TXP_0 PEG_TXN_0 PEG_TXP_1 PEG_TXN_1 PEG_RXP_1 PEG_RXN_1 PEG_TXP_2 PEG_TXN_2 PEG_RXP_2 PEG_RXN_2 PEG_TXP_3 PEG_TXN_3 PEG_RXP_3 PEG_RXN_3 PEG_TXP_4 PEG_TXN_4 PEG_RXP_4 PEG_RXN_4 PEG_TXP_5 PEG_TXN_5 PEG_RXP_5 PEG_RXN_5 PEG_TXP_6 PEG_TXN_6 PEG_RXP_6 PEG_RXN_6 PEG_RXP_7 PEG_RXN_7 PEG_TXP_7 PEG_TXN_7 PEG_RXP_8 PEG_RXN_8 PEG_TXP_8 PEG_TXN_8 PEG_RXP_9 PEG_RXN_9 PEG_TXP_9 PEG_TXN_9 PEG_RXP_10 PEG_RXN_10 PEG_TXP_10 PEG_TXN_10 PEG_RXP_11 PEG_RXN_11 PEG_TXP_11 PEG_TXN_11 PEG_RXP_12 PEG_RXN_12 PEG_TXP_12 PEG_TXN_12 PEG_RXP_13 PEG_RXN_13 PEG_TXP_13 PEG_TXN_13 PEG_RXP_14 PEG_RXN_14 PEG_RXP_15 PEG_RXN_15 PEG_TXP_14 PEG_TXN_14 PEG_TXP_15 PEG_TXN_15 B25 A25 PEG_CTX_GRX_P15 0.22U_0201_6.3V6K PEG_CTX_GRX_N15 0.22U_0201_6.3V6K 2 1VGA@ CC2 1VGA@ CC4 B24 C24 PEG_CTX_GRX_P14 0.22U_0201_6.3V6K PEG_CTX_GRX_N14 0.22U_0201_6.3V6K 2 1VGA@ CC11 1VGA@ CC12 B23 A23 PEG_CTX_GRX_P13 0.22U_0201_6.3V6K PEG_CTX_GRX_N13 0.22U_0201_6.3V6K 2 1VGA@ CC13 1VGA@ CC15 B22 C22 PEG_CTX_GRX_P12 0.22U_0201_6.3V6K PEG_CTX_GRX_N12 0.22U_0201_6.3V6K 2 1VGA@ CC8 1VGA@ CC18 B21 A21 PEG_CTX_GRX_P11 0.22U_0201_6.3V6K PEG_CTX_GRX_N11 0.22U_0201_6.3V6K 2 1VGA@ CC9 1VGA@ CC21 B20 C20 PEG_CTX_GRX_P10 0.22U_0201_6.3V6K PEG_CTX_GRX_N10 0.22U_0201_6.3V6K 2 1VGA@ CC22 1VGA@ CC24 B19 A19 PEG_CTX_GRX_P9 PEG_CTX_GRX_N9 0.22U_0201_6.3V6K 0.22U_0201_6.3V6K 2 1VGA@ CC26 1VGA@ CC28 B18 C18 PEG_CTX_GRX_P8 PEG_CTX_GRX_N8 0.22U_0201_6.3V6K 0.22U_0201_6.3V6K 2 1VGA@ CC30 1VGA@ CC32 A17 B17 PEG_CTX_GRX_P7 PEG_CTX_GRX_N7 0.22U_0201_6.3V6K 0.22U_0201_6.3V6K 2 1VGA@ CC34 1VGA@ CC36 C16 B16 PEG_CTX_GRX_P6 PEG_CTX_GRX_N6 0.22U_0201_6.3V6K 0.22U_0201_6.3V6K 2 1VGA@ CC38 1VGA@ CC40 A15 B15 PEG_CTX_GRX_P5 PEG_CTX_GRX_N5 0.22U_0201_6.3V6K 0.22U_0201_6.3V6K 2 1VGA@ CC42 1VGA@ CC44 C14 B14 PEG_CTX_GRX_P4 PEG_CTX_GRX_N4 0.22U_0201_6.3V6K 0.22U_0201_6.3V6K 2 1VGA@ CC46 1VGA@ CC48 A13 B13 PEG_CTX_GRX_P3 PEG_CTX_GRX_N3 0.22U_0201_6.3V6K 0.22U_0201_6.3V6K 2 1VGA@ CC50 1VGA@ CC52 C12 B12 PEG_CTX_GRX_P2 PEG_CTX_GRX_N2 0.22U_0201_6.3V6K 0.22U_0201_6.3V6K 2 1VGA@ CC54 1VGA@ CC56 A11 B11 PEG_CTX_GRX_P1 PEG_CTX_GRX_N1 0.22U_0201_6.3V6K 0.22U_0201_6.3V6K 2 1VGA@ CC58 1VGA@ CC60 C10 B10 PEG_CTX_GRX_P0 PEG_CTX_GRX_N0 0.22U_0201_6.3V6K 0.22U_0201_6.3V6K 2 1VGA@ CC62 1VGA@ CC64 B8 A8 DMI_CTX_PRX_P0 DMI_CTX_PRX_N0 C6 B6 DMI_CTX_PRX_P1 DMI_CTX_PRX_N1 B5 A5 DMI_CTX_PRX_P2 DMI_CTX_PRX_N2 D4 B4 DMI_CTX_PRX_P3 DMI_CTX_PRX_N3 PEG_CTX_C_GRX_P15 PEG_CTX_C_GRX_N15 PEG_CTX_C_GRX_P14 PEG_CTX_C_GRX_N14 PEG_CTX_C_GRX_P13 PEG_CTX_C_GRX_N13 PEG_CTX_C_GRX_P12 PEG_CTX_C_GRX_N12 PEG_CTX_C_GRX_P11 PEG_CTX_C_GRX_N11 PEG_CTX_C_GRX_P10 PEG_CTX_C_GRX_N10 PEG_CTX_C_GRX_P9 PEG_CTX_C_GRX_N9 PEG_CTX_C_GRX_P8 PEG_CTX_C_GRX_N8 PEG_CTX_C_GRX_P7 PEG_CTX_C_GRX_N7 PEG_CTX_C_GRX_P6 PEG_CTX_C_GRX_N6 PEG_CTX_C_GRX_P5 PEG_CTX_C_GRX_N5 PEG_CTX_C_GRX_P4 PEG_CTX_C_GRX_N4 PEG_CTX_C_GRX_P3 PEG_CTX_C_GRX_N3 PEG_CTX_C_GRX_P2 PEG_CTX_C_GRX_N2 PEG_CTX_C_GRX_P1 PEG_CTX_C_GRX_N1 PEG_CTX_C_GRX_P0 PEG_CTX_C_GRX_N0 +VCCIO RC6 24.9_0402_1% PEG_RCOMP G2 PEG_RCOMP Trace Width/Space: 15 mil/ 15 mil Max Trace Length: 600 mil To PCH DMI_CRX_PTX_P0 DMI_CRX_PTX_N0 DMI_CRX_PTX_P1 DMI_CRX_PTX_N1 DMI_CRX_PTX_P2 DMI_CRX_PTX_N2 DMI_CRX_PTX_P3 DMI_CRX_PTX_N3 DMI_CRX_PTX_P0 DMI_CRX_PTX_N0 D8 E8 DMI_CRX_PTX_P1 DMI_CRX_PTX_N1 E6 F6 DMI_CRX_PTX_P2 DMI_CRX_PTX_N2 D5 E5 DMI_CRX_PTX_P3 DMI_CRX_PTX_N3 J8 J9 DMI_RXP_0 DMI_RXN_0 DMI_TXP_0 DMI_TXN_0 DMI_RXP_1 DMI_RXN_1 DMI_TXP_1 DMI_TXN_1 DMI_RXP_2 DMI_RXN_2 DMI_TXP_2 DMI_TXN_2 DMI_RXP_3 DMI_RXN_3 OF 13 DMI_TXP_3 DMI_TXN_3 DMI_CTX_PRX_P0 DMI_CTX_PRX_N0 DMI_CTX_PRX_P1 DMI_CTX_PRX_N1 DMI_CTX_PRX_P2 DMI_CTX_PRX_N2 DMI_CTX_PRX_P3 DMI_CTX_PRX_N3 To PCH CFL-H_BGA1440 4 Compal Secret Data Security Classification 2017/12/18 Issued Date Deciphered Date 2018/09/01 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title B C D PEG/DMI Size Document Number Custom Rev 1.0 DH5VF M/B LA-F591PR01 Date: A Compal Electronics, Inc Thursday, February 22, 2018 Sheet E 10 of 67 A B 11 ILMT_1VALW 13 15 +3VALW EN NC ILMT NC BYP NC PAD 10 12 FB = 0.6V PC613 2.2U_0402_6.3V6M 1 1 + +1.05VALW +1.05VALWP PR610 16 Rdown 21 Pin BYP is for CS Common NB can delete PC614 1U_0402_6.3V6K Rup PC612 22U_0603_6.3V6M LDO_3V FB_1VALW 17 PC611 22U_0603_6.3V6M 14 SY8288RAC_QFN20_3X3 Choke 1uH SH00000YE00 (Common Part) (Size:6.86 x 6.47 x mm) (DCR:6.2m~7.2m Ohm) 20 VCC PL602 1UH_11A_20%_7X7X3_M PC610 22U_0603_6.3V6M GND +1.05VALWP PC603 0.1U_0603_25V7K 2 LX FB LX_1VALW 19 BST_1VALW_R PC609 22U_0603_6.3V6M GND GND @ PR606 0_0603_5% LX BST_1VALW @ PJ601 JUMP_43X118 2 @ PC615 220U_B2_4VM_R35M EN_1VALW LX IN IN PC608 330P_0402_50V7K BS PG IN IN PR608 15.4K_0402_1% The current limit is set to 6A, 8A or 12A when this pin is pull low, floating or pull high @EMI@ PC602 680P_0402_50V7K @ PR609 0_0402_5% 18 change PL601 SM01000C000 to comm part SM01000P200 SNUB_1VALW 20K_0402_1% ILMT_1VALW @EMI@ PR605 4.7_1206_5% @ PR607 0_0402_5% E PU601 +19VB_1VALW PC606 10U_0805_25V6K 2 @EMI@ PC605 0.1U_0402_25V6 LDO_3V @ PJ602 JUMP_43X39 EN pin don't floating If have pull down resistor at HW side, pls delete PR702 EMI@ PC604 2200P_0402_50V7K EMI@ PC607 0.1U_0402_25V6 +19VB D +19VB_1VALW @EMI@ PL601 FBMA-L11-201209-800LMA50T C +3VALW and PC15 Vout=0.6V* (1+Rup/Rdown) =0.6*(1+(15.4/20)) Vout=1.062V 2 PR611 0_0402_5% +1.8_PG @ PR603 10K_0402_1% 1 EN_1VALW +3VALW @ PC601 PR601 0.22U_0402_10V6K 1M_0402_1% 3 4 Compal Secret Data Security Classification Issued Date 2016/07/18 Deciphered Date 2017/06/14 THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Size C Date: A B C D Compal Electronics, Inc 1V Document Number Rev 0.1 C5MMH M/B LAE911P Thursday, February 22, 2018 Sheet E 53 of 67 A B C D @ PR7123 0_0402_5% SPOK_3V 1 EN_1.8V E PR7124 1M_0402_1% @ PC7118 0.1U_0402_16V7K PR7126 100K_0402_5% PU7105 Rup FB_1.8V FB=0.6V Note:Iload(max)=3A @ PC7126 22U_0603_6.3V6M SY8003ADFC_DFN8_2X2 +1.8VALWP NC PL7103 1UH_2.8A_30%_4X4X2_F PGND LX_1.8V PC7125 22U_0603_6.3V6M LX PC7127 22U_0603_6.3V6M EN IN JUMP_43X79 PG 2 PC7119 22U_0603_6.3V6M PR7122 20.5K_0402_1% PC7123 68P_0402_50V8J @ PJ7108 Choke 1uH SH00000YG00 (Common Part) (Size:3.8 x 3.8 x 1.9 mm) (DCR:20m~25m) PGND SGND FB +3VALW 2 VIN_1.8V 1 @EMI@ PR7125 4.7_0603_5% +1.8_PG @EMI@ PC7124 680P_0402_50V7K PR7121 10K_0402_1% Rdown +3VALW Vout=0.6V* (1+Rup/Rdown) Vout=0.6V*(1+20.5/10) =1.83V (x1.017) 2 @ PJ7107 JUMP_43X79 2 +1.8VALWP +1.8VALW +3VALW +5VALW 1U_0402_6.3V6K Note:Iload(max)=3A PC7111 22U_0603_6.3V6M FB_2.5V @ PC7110 22U_0603_6.3V6M 1M_0402_5% Rup 21.5K_0402_1% PR7113 PR7115 PC7109 0.01U_0402_25V7K +2.5VP NC VO ADJ GND @ VPP VIN VEN POK GND EN_2.5V SYSON 0.1U_0402_16V7K PC7107 2 FB=0.8V PU7102 G9661MF11U_SO8 VIN_2.5V @ PR7110 0_0402_5% +2.5V PC7210 VIN_2.5V PC7108 4.7U_0402_6.3V6M @ PJ7103 JUMP_43X79 2 PJ7105 JUMP_43X79 @ 1 2 +2.5VP PR7116 Rdown 10K_0402_1% Vout=0.8V* (1+Rup/Rdown) Vout=0.8V* (1+(21.5/10)) = 2.52V (x1.008) 4 Compal Secret Data Security Classification Issued Date 2016/07/18 Deciphered Date 2017/06/14 THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Size C Date: A B C D Compal Electronics, Inc 1.5VS/2.5V Document Number Rev 0.1 C5MMH M/B LAE911P Thursday, February 22, 2018 Sheet E 54 of 67 EMI@ PR7203 4.7_1206_5% @ PJ7201 EMI@ PC7203 680P_0402_50V7K SNB_+VCCIOP +VCCIOP 1 2 +VCCIO JUMP_43X118 +VCCIOP_EN 11 +VCCIOP_ILMT 13 15 PC7209 1U_0402_6.3V6K +3VALW NC ILMT NC BYP NC PAD 10 12 PC7218 2.2U_0402_6.3V6M @ FB = 0.6V @ Rup 21 Pin BYP is for CS Common NB can delete +3VALW and PC15 VCCIO_SENSE_R VR_ON @ PR7207 0_0402_5% SUSP# PR7208 1K_0402_5% @ PR7209 0_0402_5% VCCIO_SENSE @ PR7210 0_0402_5% VSSIO_SENSE VCCIO_SENSE VSSIO_SENSE C VR_ON SUSP# +VCCIOP_EN 2 check delay time with HW PC7201 0.1U_0402_25V6 PR7201 1M_0402_5% 1 +VCCIOP_ILMT @ PR7217 0_0402_5% Vout=0.6V* (1+Rup/Rdown) =0.6*(1+(12k/20.5k)) =0.951V - (x1.001) PR7218 12K_0402_1% +VCCIOP_LDO_3V @ PR7213 0_0402_5% Note:Iload(max)=5.5A IOCP=7A~8A(typ) 16 SY8288RAC_QFN20_3X3 C PC7214 22U_0603_6.3V6M +VCCIOP_LDO_3V PC7212 22U_0603_6.3V6M +VCCIOP_FB 17 PC7211 22U_0603_6.3V6M VCC EN 14 PC7206 22U_0603_6.3V6M GND +VCCIOP @ PC7205 22U_0603_6.3V6M FB 19 20 LX GND Real Voltage=0.95V PL7202 0.68UH_7.9A_20%_5X5X3_M PC7204 22U_0603_6.3V6M GND PC7202 0.1U_0603_25V7K LX +VCCIOP_LX IN PR7202 0_0603_5% +VCCIOP_BST 2+VCCIOP_BST_R LX PR7212 10_0402_1% 18 IN BS PG IN IN PR7214 1K_0402_1% Rdown D Choke 0.68uH SH00000Z300 (Common Part) (Size:4.85 x 4.7 x 2.8 mm) (DCR:11m~12m) PR7215 20.5K_0402_1% 2 1 JUMP_43X39 @EMI@ PC7217 0.1U_0402_25V6 1 PC7207 EMI@ 2200P_0402_50V7K +19VB PU7201 +VCCIOP_B+ @ PJ7202 PC7208 10U_0805_25V6K D PC7219 330P_0402_50V7K EMI@ PL7201 FBMA-L11-201209-800LMA50T B B A A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2016/07/18 Deciphered Date 2017/06/14 THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC Title C5MMH M/B LAE911P Size C Date: Document Number Rev 0.1 1.0VS_VCCIO Thursday, February 22, 2018 Sheet 55 of 67 +19VB_CPU for ICCMAX=2.2V 76A for 2 G1 D1 1 PC8161 RT9610CGQW _W DFN8_2X2 1U_0201_6.3V6K PR8123 200_0402_1% 2 1 PR8160 200_0402_1% PR8182 200_0402_1% B AVcore3 Ta=70=>Id=17.5A Rdson=8.2~10.5 mohm VCC_PHASE4 D1 G1 VCC_UG4 PL8106 0.15UH_MMD06CZER15MG_37A_20% VCC_PHASE4 D2/S1 VCC_LG4 S2 AON6962_DFN5X6D-8-7 LGATE GND RT9610CGQW _W DFN8_2X2 PC8157 1U_0201_6.3V6K @EMI@ PR8194 4.7_1206_5% PR8195 200_0402_1% VCC PGND PHASE EN UGATE PWM S2 BOOT +5VALW G2 max:3.5mOhm EN4 S2 PR8193 5.1_0402_1% @ PR8198 0_0402_5% RTCPU_PS4 EN4 PC8159 PR8197 200_0402_1% 0.47U_0402_6.3V6K 1 @EMI@ PC8160 @ PR8199 680P_0402_50V7K 0_0402_5% Ta=70=>Id=30A Rdson=2.8~3.5 mohm S2 AON6962_DFN5X6D-8-7 AISP3 PC8148 PC8149 EMI@ EMI@ VCCGT_PHASE1 D2/S1 A S2 S2 G2 S2 S2 PR8192 PC8150 2.2_0603_1% 0.1U_0603_25V7K 2BOOST_VCC4_R 1 2 @ PC8147 D1 G1 AISP4 AVcore4 @EMI@ PR8201 4.7_1206_5% PR8202 182_0402_1% 2 Ta=70=>Id=30A Rdson=2.8~3.5 mohm PL8107 0.15UH_MMD06CZER15MG_37A_20% VCCGT_LG1 S2 PR8183 PC8140 200_0402_1% 0.47U_0402_6.3V6K 2 @EMI@ PC8141 @ PR8185 680P_0402_50V7K 0_0402_5% SNUB_VCC4 LGATE GND VCCGT_PHASE1 @EMI@ PR8181 4.7_1206_5% PQ8104 +VCC_GT VCC PGND S2 BOOST_VCC4 PHASE EN S2 UGATE PWM G2 BOOT RT9610CGQW _W DFN8_2X2 PC8139 1U_0201_6.3V6K Ta=70=>Id=17.5A Rdson=8.2~10.5 mohm +5VALW EN5 S2 AON6962_DFN5X6D-8-7 EN3 1 2 1 2 1 0.1U_0402_25V6 L/S AON6314 Rds(on) :typ:2.8mOhm, Idsm(TA=25)=37A, Idsm(TA=70)=30A VCCGT_UG1 PL8305 0.15UH_MMD06CZER15MG_37A_20% VCC_PHASE3 D2/S1 2 +3VALW 2200P_0402_50V7K PR8200 D1 G1 VCC_LG3 SNUB_VCC3 @ PR8184 0_0402_5% RTCPU_PS4 PQ8105 AVcore2 LGATE GND VCC_PHASE3 VCC PGND EN VCC_UG3 G2 PHASE S2 UGATE BOOT PWM S2 +5VALW PC8155 PC8156 EMI@ EMI@ PU8106 AISP2 Ta=70=>Id=17.5A Rdson=8.2~10.5 mohm VCCCORE_VR_PWRGD EN3 PR8179 5.1_0402_1% PC8154 10U_0805_25V6K 10U_0805_25V6K 10U_0805_25V6K 10U_0805_25V6K PC8153 C @ PR8164 0_0402_5% PQ8103 PC8158 PR8196 2.2_0603_1% 0.1U_0603_25V7K BOOST_VCCGT1 2BOOST_VCCGT1_R 5.1_0402_1% D1 G1 1 PR8174 PC8135 2.2_0603_1% 0.1U_0603_25V7K 2BOOST_VCC3_R PU8104 H/S AON6380 Rds(on) :typ:8.2mOhm, max:10.5mOhm Idsm(TA=25)=22A, Idsm(TA=70)=17.5A RTCPU_PW MA1 S2 BOOST_VCC3 2.2U_0402_6.3V6M +19VB_CPU PC8152 PC8124 0.47U_0402_6.3V6K PC8132 PC8133 EMI@ EMI@ PU8105 4 1 AVGT1 PC8136 PC8131 PC8130 AISPGT1 PR8171 680_0402_1% Ta=70=>Id=30A Rdson=2.8~3.5 mohm PC8151 PR8161 200_0402_1% @EMI@ PC8125 680P_0402_50V7K +19VB_CPU CPU_SVID_DAT @EMI@ PR8158 4.7_1206_5% Ta=70=>Id=30A Rdson=2.8~3.5 mohm 48 PWMA3 CPU_SVID_ALERT#_R 10_0402_1% RTCPU_PW MA1 PR8173 10_0603_1% 2 EN2 0_0402_5% AON6962_DFN5X6D-8-7 +19VB_CPU CPU_SVID_CLK VCC_LG2 PR8191 D2/S1 SNUB_VCC2 @ PR8163 0_0402_5% RTCPU_PS4 AVcore4 @ PR8190 PC8146 49.9_0402_1% PL8306 0.15UH_MMD06CZER15MG_37A_20% VCC_PHASE2 2200P_0402_50V7K SDIO_CPU VCC_PHASE2 0.1U_0402_25V6 ALERT_CPU VCC_UG2 RT9610CGQW _W DFN8_2X2 PC8123 1U_0201_6.3V6K 1 LGATE GND AVcore3 0.1U_0402_25V6 VCC PGND 10U_0805_25V6K 45.3_0402_1% 100_0402_1% PHASE EN PR8162 680_0402_1% UGATE PWM G2 BOOT PR8159 680_0402_1% PC8143 PR8188 AVcore1 46 PWMA2 ISENA1P ISENA2P ISENA1N AISP4 RTCPU_ISEN4N AISP1 38 37 RTCPU_ISENA1N 39 ISENA2N ISENA3P 41 40 36 ISENA3N VCC AISP3 RTCPU_ISEN3N +5VALW AVcore2 EN2 10U_0805_25V6K PR8189 ENABLE Upper Threshold > 0.8V Lower Threshold < 0.3V 100_0402_1% 1 PR8186 @ PR8187 47 1 PR8152 680_0402_1% PR8151 5.1_0402_1% AISP2 RTCPU_ISEN2N PR8125 PC8113 200_0402_1% 0.47U_0402_6.3V6K 2 @EMI@ PC8114 @ PR8131 680P_0402_50V7K 0_0402_5% Ta=70=>Id=17.5A Rdson=8.2~10.5 mohm 2 32 13 27 EN RGNDA 24 25 VCLK VDIO ALERT AVcore1 PR96and PR98 pull high resistor are pop at the end of VR SVID Other VR is unpop B 2 PR8150 680_0402_1% 2 @RF@ PC8142 2.2P_0402_50V8C 1 2 0_0402_5% PR8128 26 23 16 NC VR_HOT RGND AISP1 RTCPU_ISEN1N +5VALW confirm with power sequence, it need behind +5VS D @EMI@ PR8121 4.7_1206_5% PQ8102 PU8103 PR8180 100K_0402_1% +1.05V_VCCST PR8114 5.76K_0402_1% VCCCORE_VR_PWRGD RTCPU_VCC 54 29 FBA PGOOD COMPA NC DVD 2 PC8122 PR8144 0.1U_0603_25V7K 2.2_0603_1% 2BOOST_VCC2_R 0.1U_0402_25V6 PR8169 510K_0402_1% BOOST_VCC2 RTCPU_VCC RTCPU_VCC Reserved for RF Team Request AON6962_DFN5X6D-8-7 Ta=70=>Id=30A Rdson=2.8~3.5 mohm PC8121 PC8117 EMI@ EMI@ 2200P_0402_50V7K PR8172 100K_0402_1% PC8115 1U_0201_6.3V6K +VCC_GT SCLK_CPU PC8120 PC8119 10U_0805_25V6K PR8176 16.9K_0402_1% PC8138 68P_0402_50V8J ISEN4P COMP PC8134 0.1U_0402_50V7K PR8177 10K_0402_1% RTCPU_PW M4 PWMA1 @ PR8170 0_0402_5% PC8137 270P_0402_50V7K RTCPU_PW M3 ISEN4N RTCPU_DVD PR8178 100_0402_1% RTCPU_PW M2 53 ISEN3N VSEN +19VB_CPU @ PR8175 0_0402_5% 51 50 ISEN2P RT3607CE FB VCC_LG1 SETA2 11 Choke 0.15uH SH00000X700 (Size:6.59 x 6.6 x 3.0 mm) (DCR:0.9m +-7%) +VCC_CORE D2/S1 EN1 ISEN2N 10 2 10U_0805_25V6K VCCGT_SENSE IBIAS GND SETA1 RTCPU_FB PC8127 82P_0402_50V8J RTCPU_PW M1 ISEN1N 35 PR8167 23.2K_0402_1% PC8126 330P_0402_50V8J 1 PL8101 0.15UH_MMD06CZER15MG_37A_20% VCC_PHASE1 +19VB_CPU VR_ON SET3 45 PR8166 10K_0402_1% PR8130 0_0402_5% 52 ISEN1P SET2 12 +19VB @ 30 NC SET1 RTCPU_VSENA PR8105 4.02K_0402_1% 2 PR8124 100K_0402_1% RTCPU_IBIAS PS4 28 RTCPU_VSEN PR8168 100_0402_1% +VCC_CORE 22 PWM4 RTCPU_FBA RTCPU_COMP @ PR8165 0_0402_5% VCCSENSE IMONA VREF 21 20 42 IMON GND PWM2 PWM3 VSENA PGND LGATE GND + RT9610CGQW _W DFN8_2X2 PC8112 1U_0201_6.3V6K PU8101 RT3607CEGQW _W QFN56_6X6 TONSETA RTCPU_COMPA 34 RTCPU_VSEN @ PR8129 0_0402_5% RTCPU_PS4 RTCPU_EN VSSGT_SENSE_R VSSSENSE_R @ ISEN3P RTCPU_VSEN VSSSENSE SCLK_CPU SDIO_CPU ALERT_CPU TONSET RTCPU_VSENA 33 RTCPU_VSENA VCC SNUB_VCC1 VR_HOT# NC C PR8126 100_0402_1% PWM1 RTCPU_SETA2 19 EN VCC_PHASE1 2 @ 1K_0402_1% NC RTCPU_SETA1 18 PHASE 15 17 PWM VCC_UG1 14 RTCPU_SET2 RTCPU_SET3 RTCPU_SET1 57 49 1 PR8113 1.8K_0402_1% PR8119 57.6K_0402_1% RTCPU_PS4 TSEN PR8135 10K_0402_1% PR8140 2K_0402_1% PR8148 402_0402_1% PR8149 PR8157 300_0402_1% 3.16K_0402_1% 2 PR8156 412_0402_1% 43 TSENA PR8134 13.3K_0402_1% PR8141 PR8136 8.2K_0402_1% 5.1K_0402_1% 2 PR8133 13.3K_0402_1% PR8138 26.7K_0402_1% PR8147 768_0402_1% PR8155 0_0402_5% PR8132 3.01K_0402_1% PR8137 24.9_0402_1% PR8145 1.02K_0402_1% PR8146 3.4K_0402_1% PR8154 0_0402_5% PR8153 0_0402_5% 55 RTCPU_TONSETA +5VALW @ PR8120 0_0402_5% EN1 UGATE 0.1U_0402_25V6 RTCPU_TONSET +1.05V_VCCST PR8112 5.1_0402_1% BOOT + 2200P_0402_50V7K @ @ RTCPU_SET1 RTCPU_SET2 RTCPU_SET3 RTCPU_SETA1 RTCPU_SETA2 0_0402_5% 56 0_0402_5% 44 PR8115 100_0402_1% @ PR8122 +VREF @ PR8139 @ PR8142 10U_0805_25V6K @ 10U_0805_25V6K @ PR8143 0_0402_5% +VREF PR8104 7.5K_0402_1% RTCPU_TONSET 31 RTCPU_TONSETA PU8102 VSSGT_SENSE Ta=70=>Id=17.5A Rdson=8.2~10.5 mohm PQ8101 @ PR8111 0_0402_5% PC8111 0.47U_0402_16V4Z Core offset function disable, GT offset function disable, PSYS disable NTCGT1N PR8127 1_0402_1% 2 SETA2 Ramp=133%, DVIDW=9us, QRT=25mV, QRW=44% PR8117 442K_0402_1% PR8101 PC8101 2.2_0603_1% 0.1U_0603_25V7K 2BOOST_VCC1_R 10K_0402_1%_B25/50 3370K 100K_0402_1%_B25/50 4250K PR8110 PH8104 8.66K_0402_1% 220K_0402_5%_B25/50 4700K RTCPU_TSENA 1 RTCPU_TSENA_R PR8118 57.6K_0402_1% 1 SETA1 ICCMAX=32A, OCP=120%, DVIDT=60mV PH8103 PR8109 220K_0402_5%_B25/50 4700K 8.66K_0402_1% RTCPU_TSEN RTCPU_TSEN_R 1 PR8108 2.2_0402_1% PC8110 0.22U_0402_25V6K 1 PR8107 2.2_0402_1% 1 PR8116 402K_0402_1% BOOST_VCC1 + PC8116 33U_D1_25VM_R6M SET3 Zero LL disable, VR address Core=0, GT=1 PH8101 1 EMI@ PL8102 FBMA-L11-201209-800LMA50T PC8118 33U_D1_25VM_R6M SET2 Ramp=133%, DVIDW=9us, QRT=25mV, QRW=44% PR8106 100_0402_1% 0.1U_0402_25V6 SET1 ICCMAX=128A, OCP=120%, DVIDT=35.7mV NTCGT1P PC8106 PC8107 EMI@ EMI@ 2200P_0402_50V7K Fs=400k, LL=2.1m for GT D PH8102 NTC1N 10U_0805_25V6K 0.22U_0402_25V6K Fs=400k, LL=1.8m for Core 8.45K_0402_1% NTC1P 10U_0805_25V6K PC8109 +19VB_CPU PR8103 30.1_0402_1% PC8108 100U_25V_NC_6.3X6 PC8105 PC8104 confirm with power sequence, it need behind +5VS PR8102 +19VB_CPU EMI@ PL8103 FBMA-L11-201209-800LMA50T +19VB_CPU ICCMAX=2.2V +VREF +VREF 90A A SNUB_VCCGT1 EN5 @ PR8204 0_0402_5% RTCPU_PS4 PR8203 182_0402_1% @EMI@ PC8162 680P_0402_50V7K PC8163 0.47U_0402_6.3V6K @ PR8205 0_0402_5% AISPGT1 AVGT1 Compal Secret Data Security Classification Issued Date 2016/07/18 Deciphered Date 2017/06/14 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title RT3607CE Size Document Number Custom Date: Thursday, February 22, 2018 Rev 0.1 Sheet 56 of 67 PR902 and PR904 pull high resistor are pop at the end of VR SVID Other VR is unpop +1.05V_VCCST SVID_ALERT# pull high resistor is at HW side Confirm HW side Don't double pull high +1.05V_VCCST @ PR8302 D confirm with power sequence, it need behind +5VS D UGATE 23 FB_VCCSA 24 RGND_VCCSA 22 UG_VCCSA BOOST_VCCSA EMI@ PC8308 2200P_0402_50V7K @EMI@ PC8307 0.1U_0402_25V6 10U_0805_25V6K PC8305 1.1K PR832 10K PR833 40.2K 37.4K PR828 604 665 PR830 243 549 PR831 10K 1K LX_VCCSA 10 LG_VCCSA FB 29 +VCC_SA S2 S2 G2 AISP1_R PQ8301 AONH36334_DFN3X3A8-10 C 10K(3370K) 1K(3650K) PL8301 0.24UH_22A_20%_ 7X7X3_M D1 D1 G1 D1 D1 PR8331 576_0603_1% LX_VCCSA D2/S1 10 LG_VCCSA 73.2K PH802 COMP PC8310 0.47U_0402_6.3V6K PR8336 PR8337 255_0402_1% 10K_0402_1% 2AVcore1_NTC @ PR8340 0_0201_5% 2AVcore1_NTC_R PH8301 10K_0402_1%_B25/50 3370K For NTC trace routing only ISEN1N ISEN1P 20 B +5VALW AISP1_VCCSA AVcore1_VCCSA PC8319 0.1U_0402_25V6 PC8317 1U_0201_6.3V6K PC8318 2.2U_0603_10V6K 21 15 PVCC 12 2 1 Local sense, for debug only PR8349 22_0402_1% PR8348 VCC +VCC_VCCSA1 VCCSA_VR_PW RGD 100K_0402_5% Confirm HW side Don't double pull high DRVEN RGND 11 68.1K PR841 AVcore1_VCCSA VSEN BOOT COMP_VCCSA 14 PR813 UG_VCCSA S2 PWM SET3 PHASE 25 SET2 @ PC8315 0.1U_0402_25V6 @ PC8316 0.1U_0402_25V6 LX_VCCSA SET1 2 PR8347 100_0402_1% VSSSA_SENSE @ PR8346 0_0402_5% 2 PSYS LGATE VSEN_VCCSA ISEN 26 COMP PU8301 VR_READY B VR_ON 27 PC8314 100P_0402_50V8J high > 0.7V, Low < 0.3V PR8301 2.2_0603_5% BOOST_VCCSA 2BOOST_VCCSA_R GND @ PC8313 0.1U_0402_25V6 PR8321 EN: 0_0402_5% RT3601EAGQW _W QFN28_4X4 28 10U_0805_25V6K PC8304 2 0.1U_0402_25V6 EN SDIO_VCCSA ALERT#_VCCSA VDIO VCLK ALERT# VCLK_VCCSA VREF_VCCSA 17 VREF 18 IMON VIN @ PC8306 VCCSA_VR_EN PC8301 0.22U_0402_16V7K 19 Choke 7x7x4 7x7x3 Size and DCR 0.67m +-5%0.9m +-5% IMON VRHOT# 13 CPU_SVID_DAT +19VB_CPU PR8316 2.4K_0402_1% IMON_VCCSA TSEN_VCCSA 16 PR8322 2.2_0805_1% TSEN PR8318 2K_0402_1% +19VB_CPU PR8311 10_0402_1% PR8310 59K_0402_1% PR8315 7.32K_0402_1% PR8312 10K_0402_1% PR8320 22.6K_0402_1% PR8326 0_0402_5% 2 PR8324 120_0402_1% Vboot=0V CPU_SVID_ALERT#_R SET1_VCCSA SET2_VCCSA SET3_VCCSA @ PR8342 PR8343 PR8344 PR8345 0_0402_5% 10K_0402_1% 300_0402_1% 47.5K_0402_1% 2 2 PC8312 330P_0402_50V8J CPU_SVID_CLK @ PR8308 0_0402_5% 1_0402_1% PR8313 PR8314 48.7K_0402_1% 200_0402_1% TSEN_VCCSA_R 2 PSYS_VCCSA @ PR8339 0_0402_5% @ PR8341 0_0402_5% PR8306 49.9_0402_1% PR8307 PH8302 100K_0402_1%_B25/50 4250K AISP1_VCCSA VCCSA_SENSE @ PR8303 45.3_0402_1% @EMI@ PC8311 @EMI@ PR8330 680P_0402_50V7K 4.7_1206_5% SNUB_VCCSA 2 PR8335 100_0402_1% VR_HOT# 90 degreeC ALERT# 87.3 degreeC PC8309 0.22U_0402_25V6K PR8334 PR8329 7.68K_0402_1% 2.2K_0402_1% 2 +VCC_SA PR8325 300_0402_1% PR8317 3.6K_0402_1% Local sense, for debug only Trace is form output cap that is near choke PR8328 PR8333 300_0402_1% 20K_0402_1% 2 PR8332 PR8327 100_0402_1% 1.78K_0402_1% 2 C PR8319 22K_0402_1% VREF_VCCSA SET1 connect to 5V is into test mode The output is 1.05V PR8309 PR8305 14K_0402_1% 30.9K_0402_1% 1 VREF_VCCSA PR8304 100_0402_1% VR2_HOT# PC8302 0.47U_0402_6.3V6K PC8303 0.1U_0402_25V6 2 1K_0402_5% +3VALW +5VALW VCCSENSE and VSSSENSE need have a 100ohm at HW Side A A Compal Secret Data Security Classification Issued Date 2016/07/18 Deciphered Date 2017/06/14 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title RT3601EA VCC_SA Size Document Number Custom Date: Rev 0.1 Thursday, February 22, 2018 Sheet 57 of 67 1 1 1 @ PC9148 1U_0201_6.3V6M 1 1 1 Issued Date Security Classification 2016/07/18 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Deciphered Date 2017/06/14 Compal Secret Data Date: 2 @ PC9138 1U_0201_6.3V6M 2 1 1 PC9113 22U_0603_6.3V6M PC9112 22U_0603_6.3V6M PC9111 22U_0603_6.3V6M PC9110 22U_0603_6.3V6M PC9109 22U_0603_6.3V6M @ @ PC9137 1U_0201_6.3V6M @ PC9108 22U_0603_6.3V6M 1 1 1 1 1 1 1 1 PC9092 22U_0603_6.3V6M PC9091 22U_0603_6.3V6M PC9090 22U_0603_6.3V6M PC9089 22U_0603_6.3V6M PC9088 22U_0603_6.3V6M PC9087 22U_0603_6.3V6M @ PC9107 1U_0201_6.3V6M @ PC9106 1U_0201_6.3V6M @ PC9105 1U_0201_6.3V6M @ PC9104 1U_0201_6.3V6M @ PC9103 1U_0201_6.3V6M @ PC9102 1U_0201_6.3V6M @ PC9101 1U_0201_6.3V6M @ PC9100 1U_0201_6.3V6M PC9099 1U_0201_6.3V6M PC9098 1U_0201_6.3V6M 1 1 1 1 1 1 1 PC9086 1U_0201_6.3V6M PC9085 1U_0201_6.3V6M PC9084 1U_0201_6.3V6M PC9083 1U_0201_6.3V6M PC9082 1U_0201_6.3V6M PC9081 1U_0201_6.3V6M PC9080 1U_0201_6.3V6M PC9079 1U_0201_6.3V6M PC9078 1U_0201_6.3V6M PC9077 1U_0201_6.3V6M PC9076 22U_0603_6.3V6M PC9075 22U_0603_6.3V6M PC9074 22U_0603_6.3V6M PC9073 22U_0603_6.3V6M PC9072 22U_0603_6.3V6M 1 1 1 1 1 1 1 1 PC9058 22U_0603_6.3V6M PC9057 22U_0603_6.3V6M PC9056 22U_0603_6.3V6M PC9055 22U_0603_6.3V6M PC9054 22U_0603_6.3V6M PC9053 22U_0603_6.3V6M PC9052 22U_0603_6.3V6M PC9051 22U_0603_6.3V6M PC9050 22U_0603_6.3V6M PC9049 22U_0603_6.3V6M PC9048 22U_0603_6.3V6M PC9047 22U_0603_6.3V6M PC9046 22U_0603_6.3V6M PC9045 22U_0603_6.3V6M PC9044 22U_0603_6.3V6M PC9043 22U_0603_6.3V6M 1 1 1 1 1 1 1 1 PC9028 22U_0603_6.3V6M PC9027 22U_0603_6.3V6M PC9026 22U_0603_6.3V6M PC9025 22U_0603_6.3V6M PC9024 22U_0603_6.3V6M PC9023 22U_0603_6.3V6M PC9022 22U_0603_6.3V6M PC9021 22U_0603_6.3V6M PC9020 22U_0603_6.3V6M PC9019 22U_0603_6.3V6M PC9018 22U_0603_6.3V6M PC9017 22U_0603_6.3V6M PC9016 22U_0603_6.3V6M PC9015 22U_0603_6.3V6M PC9014 22U_0603_6.3V6M PC9013 22U_0603_6.3V6M PC9012 22U_0603_6.3V6M 1 1 1 PC9151 22U_0603_6.3V6M PC9152 22U_0603_6.3V6M PC9153 22U_0603_6.3V6M PC9155 22U_0603_6.3V6M PC9156 22U_0603_6.3V6M PC9150 22U_0603_6.3V6M PC9154 22U_0603_6.3V6M PC9004 220U_D2_2V_Y 1 1 1 1 1 PC9166 22U_0603_6.3V6M PC9165 22U_0603_6.3V6M PC9164 22U_0603_6.3V6M PC9161 22U_0603_6.3V6M PC9159 22U_0603_6.3V6M PC9163 22U_0603_6.3V6M PC9160 22U_0603_6.3V6M PC9157 22U_0603_6.3V6M PC9158 22U_0603_6.3V6M PC9162 22U_0603_6.3V6M PC9007 220U_D2_2V_Y @ PC9123 1U_0201_6.3V6M 2 PC9071 22U_0603_6.3V6M PC9042 22U_0603_6.3V6M PC9011 22U_0603_6.3V6M PC9003 220U_D2_2V_Y @ @ PC9136 1U_0201_6.3V6M PC9122 1U_0201_6.3V6M 1 +VCC_GT 1 PC9121 1U_0201_6.3V6M 2 @ PC9097 22U_0603_6.3V6M PC9070 22U_0603_6.3V6M PC9041 22U_0603_6.3V6M PC9002 220U_D2_2V_Y + PC9120 1U_0201_6.3V6M 1 PC9010 22U_0603_6.3V6M 2 @ PC9135 1U_0201_6.3V6M PC9119 1U_0201_6.3V6M 2 @ PC9096 22U_0603_6.3V6M PC9069 22U_0603_6.3V6M 1 1 PC9118 1U_0201_6.3V6M 1 PC9040 22U_0603_6.3V6M 2 PC9009 22U_0603_6.3V6M PC9134 1U_0201_6.3V6M PC9117 1U_0201_6.3V6M 2 PC9095 22U_0603_6.3V6M PC9133 1U_0201_6.3V6M PC9132 1U_0201_6.3V6M PC9131 1U_0201_6.3V6M PC9130 1U_0201_6.3V6M PC9129 1U_0201_6.3V6M PC9128 1U_0201_6.3V6M 1 PC9068 22U_0603_6.3V6M 2 PC9039 22U_0603_6.3V6M @ PC9147 1U_0201_6.3V6M @ PC9146 1U_0201_6.3V6M @ PC9145 1U_0201_6.3V6M @ PC9144 1U_0201_6.3V6M @ PC9143 1U_0201_6.3V6M PC9127 1U_0201_6.3V6M 2 PC9116 1U_0201_6.3V6M +VCC_CORE PC9142 1U_0201_6.3V6M 1 PC9094 22U_0603_6.3V6M 2 PC9067 22U_0603_6.3V6M + 2 PC9126 1U_0201_6.3V6M PC9115 1U_0201_6.3V6M 2 PC9093 22U_0603_6.3V6M PC9141 1U_0201_6.3V6M 1 + PC9125 1U_0201_6.3V6M 2 PC9114 1U_0201_6.3V6M PC9140 1U_0201_6.3V6M 1 2 B + PC9124 1U_0201_6.3V6M PC9139 1U_0201_6.3V6M +VCC_CORE +VCC_GT D D C +VCC_SA C B A A Title C5MMH M/B LAE911P Compal Electronics, Inc Size Document Number Custom Thursday, February 22, 2018 Sheet 58 of 67 R ev 0.1 A B C D E +19VB VGA_EMI@ PL1301 FBMA-L11-201209-800LMA50T TYP MAX H/S_AON6428 Rds(on) = 11.3m Ohm , 14.5m Ohm L/S_AON6794 Rds(on) = 2.8m Ohm , 3.5m Ohm +19VB_1.35VSDGPUP VGA@ PR1312 10K_0402_5% PU1301 VGA@ RT8237EZQW (2)_W DFN10_3X3 LGATE_1.35VSDGPUP VGA@ PR1306 200K_0402_1% VGA@ PC1307 1U_0402_6.3V6K VGA@ PQ1303 AON6314 1N DFN5X6-8 VGA@ PR1315 49.9_0402_1% 2 VGA@ PC1313 680P_0402_50V7K ->290KHz ->340KHz ->380KHz 1.35VS_DGPU_FB S G PR1309 0_0402_5% @VGA@ VGA@ PQ1302 L2N7002W T1G_SC70-3 Change the output voltage from 1.35V to 1.5V VGA@ + VGA@ PR1314 100_0402_1% PR1307 1 + 2 @VGA@ VFB=0.704V Vout=0.704V* PC1308 680P_0402_50V7K VGA_EMI@ 18.7K_0402_1% VGA@ PR1308 20K_0402_1% D 2 VGA@ PR1311 10K_0402_1% @VGA@ PC1309 0.1U_0402_16V7K VRAM_VDD_CTL PR1310 VGA@ 90.9K_0402_1% +1.35VSDGPUP PR1305 4.7_1206_5% VGA_EMI@ 11 SNB_1.35VSDGPUP Rrf=470K Rrf=200K Rrf=100K +5VALW PC1311 VGA@ 220U_D2 SX_2VY_R9M LGATE VGA@ PL1302 0.82UH PCMC063T-R82MN 13A_20% PC1301 VGA@ 220U_D2 SX_2VY_R9M RF LX_1.35VSDGPUP Choke 0.82uH SH00000FH00/SH00000YJ00 (Size:6.95 x 6.6 x 2.8 mm) (DCR:6.7m~8m Ohm) VCC HGATE_1.35VSDGPUP PHASE TP Frequency EN FB UGATE CS VGA@ PC1305 0.1U_0603_25V7K 2 2 1M_0402_1% PR1304 BOOT VGA@ PR1302 0_0603_5% BST_1.35VSDGPUP 1 @VGA@ VGA@ PC1306 0.1U_0402_16V7K 1.35VSDGPU_PW R_EN 1.35VS_DGPU_EN PGOOD 10 PR1303 VGA@ 1K_0402_1% VGA@ PR1301 69.8K_0402_1% 2ILMT_1.35VSDGPUP IOCP +3VS @ PJ1301 JUMP_43X79 VGA_EMI@ PC1312 0.1U_0402_25V6 AON6380 1N DFN5X6-8 10U_0805_25V6K VGA@ PC1310 PQ1301 10U_0805_25V6K VGA@ PC1304 VGA@ @VGA_EMI@ PC1303 0.1U_0402_25V6 VGA_EMI@ PC1302 2200P_0402_50V7K 1.35VS_DGPU_PG FB_VDDQ_SENSE PR1313 0_0402_5% (1+Rup/Rdown) Vout=0.704V* (1+(18.7/20))=1.36 0.97% Vout=0.704V* (1+(18.7/(20//93.1)))=1.5 Vout=0.704V* (1+(18.7/(20//90.9)))=1.524 Vout=0.704V* (1+(18.7/(20//88.7)))=1.548 0.03% 1.62% 3.23% @ +1.35VSDGPUP PJ1302 2 +1.35VSDGPU JUMP_43X118 Rds on 2.8 / 3.5mohm Rlimt=69.8K @ PJ1303 2 JUMP_43X118 4 Compal Secret Data Security Classification Issued Date 2016/07/18 Deciphered Date 2017/06/14 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Size A3 Date: Compal Electronics, Inc VRAM Document Number Rev 0.1 C5MMH M/B LAE911P Thursday, February 22, 2018 Sheet 59 of 67 A B C D @ PJ1401 JUMP_43X79 2 +1.0VSDGPUP VGA@ PC1402 22U_0603_6.3V6M VGA@ PC1404 0.1U_0402_16V7K 2 VGA@ PR1404 1M_0402_1% Rdown VGA_EMI@ PC1405 680P_0402_50V7K 2 VGA@ PC1407 22U_0603_6.3V6M FB_1.0VSDGPUP VGA@ PR1403 13.7K_0402_1% EN_1.0VSDGPUP VGA@ PC1403 22U_0603_6.3V6M 4.7K_0402_5% +1.0VSDGPUP Rup VGA_EMI@ PR1402 4.7_0603_5% @VGA@ PC1406 22U_0603_6.3V6M EN VGA@ PL1401 1UH_2.8A_30%_4X4X2_F LX_1.0VSDGPUP VGA@ PC1401 68P_0402_50V8J FB GND VFB=0.6V Vout=0.6V* (1+Rup/Rdown) =0.6V* (1+13.7/20) Vout=1.011V PG LX VGA@ PR1406 0_0402_5% VGA@ PR1401 IN 1.0VSDGPU_EN 1VS_DGPU_PG +3VS VIN_1.0VSDGPUP Choke 1uH SH00000YG00 (Common Part) (Size:3.8 x 3.8 x 1.9 mm) (DCR:20m~25m) VGA@ PU1401 SY8032ABC_SOT23-6 SNUB_1.0VSDGPUP @ PJ1402 JUMP_43X79 2 +1.0VSDGPU VGA@ PR1405 20K_0402_1% +3VALW 1 E Note: When design Vin=5V, please stuff snubber to prevent Vin damage 2 3 4 Compal Secret Data Security Classification Issued Date 2016/07/18 Deciphered Date 2017/06/14 THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Size C Date: A B C D Compal Electronics, Inc 1.05VSDGPU Document Number Rev 0.1 C5MMH M/B LAE911P Thursday, February 22, 2018 Sheet E 60 of 67 +19VB_NVVDD NVVDD_ISUMN1 NVVDD_ISUMN2 D For N17P-G1, TDP 50W 0.1U_0402_25V6 PR1203 20K_0402_1% NVVDD1 TDC = 45+13=58A Peak Current = 106+18=124A OCP = 148A GPU_PH2 C 5VCC 11 5VCC 10 PR1231 5VCC 請 教 A U TO PHASE的 設定 PR1239 PR1248 10K_0402_5% PR1244 51K_0402_5% PR1257 0_0402_5% 0_0402_5% @ @ 1 GPU_LPC GPU_PROG2 GPU_PROG3 2 GPU_PROG1 @ 0_0402_5% PR1255 GPU_PWM2 1 PR1246 36K_0402_5% PR1252 8.2K_0402_5% GPU_PWM1 +5VS PR1242 43K_0402_5% PR1251 8.2K_0402_5% PROG1 PROG2 PWM1 2.2_0603_1% +5VS 1 REFIN 1 2 CSNSUM CSPSUM GPU_PROG2 12 GPU_PH1 0_0402_5% PR1256 R5 R2 PR1258 Close to PL1301 PC1209 0.1U_0402_10V6K PR1225 2.2K_0402_1% PR1226 2.2K_0402_1% PR1264 100K_0402_5% PWM2 PWM3 ISEN2 ISEN1 13 PWM2 R4 4.32K_0402_1% PH1201 470K_0402_5%_B25/50 4700K 17 18 19 IMON PWM4 14 PR1234 33K_0402_5% 0_0402_5% @ 0.1U_0402_10V6K PR1219 1K_0402_1% PR1245 R3 B NTC_Lb NTC_La 15 的compon en t layout 上 : 請 將 RSE N1 ~ 放 靠 近 C o n t r o l l e r Fsw=300kHz PR1241 B 20.5K_0402_1% C PC1216 PC1215 4700P_0402_50V7K 1 1_0402_1% 1_0402_1% FBRTN Cold Boot = 4-phase Warm Boot = 4-phase 0.01U_0402_16V DGPU_VID PR1210 PR1211 309_0402_1% 16.5K_0402_1% @ 0_0402_5% 16 PWMVID 的 RC BOM 請 根 據GPU 's conf ig 設 定 PR1240 VGA_CORE_PG PC1202 GPU_PROG1 VINMON GPU_PROG3 SS 22 20 PROG3 R1 PR1249 PR1238 100K_0402_5% 作 5VCC PWM1 FSW GND LOW動 PGOOD 6.19K_0402_1% 0_0402_5% SS PIN 30 PSI +3VS VINMON ISEN4 0_0402_5% 1 EN @ PR1237 EAP ISEN3 0_0402_5% @ PR1235 ISEN2 LPC GPU_VID 24.9K_0402_1% PQ1201B DMN53D0LDW-7 2N SOT363-6 PR1230 1 33 PU1201 UP9511QQKI_WQFN32_4X4 TP2 31 32 ISEN1 PR1236 DGPU_PSI PR1233 30 GPU_PSI CSNSUM FBRTN +1.8VS PR1232 0_0402_5% PQ1201A DMN53D0LDW-7 2N SOT363-6 @ 0_0402_5% PC1214 1U_0402_6.3V6K VGA_CORE_EN +3VS 29 NVVDD1_ENP PR1263 10K_0402_5% @ 28 GPU_LPC PC1207 TP1 GPU_FSW 100K_0402_5% 26 27 GPU_TP2 layout 上 : 請 將 Tota l DC R sensin g 放 靠 近Control le r @ PC1205 0.1U_0402_25V6 CSPSUM VREF GPU_TP1 REFIN 1 FB PR1247 2 C 24 FBRTN +5VS FBRTN 25 100K_0402_5% PR1243 PR1228 100_0402_5% +3VALW @ PC1212 0.1U_0402_25V6 PR1223 1K_0402_1% PR1224 0_0402_5% VSSSENSE_VGA 23 PR1262 @ 0_0402_5% 0_0402_5% @ PR1212 @ PC1204 0.1U_0402_25V6 EAP PR1222 100_0402_5% COMP @ COMP @ PC1208 0.1U_0402_25V6 NVVDD_ISUMP2 NTC_La NTC_Lb @ PR1208 @ PR1209 2 PR1217 0_0402_5% VID 2 0_0402_5% +VGA_CORE @ NVVDD_ISUMP1 PR1215 0_0402_5% REFADJ PR1220 VCCSENSE_VGA 0_0402_5% 0_0402_5% PR1221 0_0402_5% PR1214 2 PC1206 PR1216 PR1218 0.015U_0402_16V7K 2.4K_0402_1% 2 21 2 Close to PU1201 PR1205 0_0402_5% PC1217 @ 0.1U_0402_25V6 REFADJ PC1203 0.01U_0402_16V7K 10K_0402_5% @ PR1207 10.7K_0402_1% 2 D PR1206 91K_0402_1% PR1201 PR1207 for OCP setting PC1201 0.1U_0402_25V6 PR1202 20K_0402_1% A A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2016/07/18 Deciphered Date 2017/06/14 THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC Title PWR_VGA_UP9511P Size Document Number Rev 1.0 C5MMH M/B LAE911P Date: Sheet Thursday, February 22, 2018 61 of 67 +19VB EMI@ PL1502 FBMA-L11-201209-800LMA50T +19VB_NVVDD EMI@ PL1503 FBMA-L11-201209-800LMA50T A VGA_CORE Vboot=0.8V TDC=58A Peak Current=124A OCP=148A FSW=300kHz Dr.MOS SIC632 TYP MAX H/S Rds(on) = 4.8mohm ,5.76mohm L/S Rds(on) = 1.3mohm ,1.56mohm +5VS 0.1U_0402_50V7K 28 27 26 25 24 23 22 21 20 19 18 17 16 15 PR1506 2.2_0603_1% Choke 0.22uH SH00000QZ00 GPU_PH1 PL1501 0.22UH_MMD-10DZ-R22MES1L 35A_20% GPU_PH1 +VGA_CORE SIC632CDT1GE3_POWERPAK31_5X5 B EMI@ PR1507 4.7_1206_5% NVVDD_ISUMP1 NVVDD_ISUMN1 GPU_SNB1 @ PC1511 10U_0603_25V6M PC1510 10U_0603_25V6M PC1509 10U_0603_25V6M @ CGND GL DSBL# THW n VDRV PGND GL SW SW SW SW SW SW SW PC1501 0_0402_5% PC1507 10U_0603_25V6M PC1506 10U_0603_25V6M 0_0402_5% EMI@ PC1505 2200P_0402_50V7K @EMI@ PC1504 0.1U_0402_25V6 B PW M ZCD_EN# VCIN CGND BOOT NC PHASE VIN VIN PGND SW SW SW SW PC1503 1U_0603_16V7 +19VB_NVVDD PR1501 PC1502 1U_0402_6.3V6K @ PR1505 +5VS 10 11 12 13 14 GPU_PWM1 A PR1503 10K_0402_1% PU1501 PR1504 1K_0402_1% PC1508 10U_0603_25V6M 0_0402_5% @ PR1502 +5VS EMI@ PC1512 680P_0402_50V7K 0_0402_5% +5VS PC1514 0_0402_5% 0.1U_0402_50V7K CGND GL DSBL# THW n VDRV PGND GL SW SW SW SW SW SW SW 28 27 26 25 24 23 22 21 20 19 18 17 16 15 PR1509 C 10K_0402_1% PR1512 2.2_0603_1% GPU_PH2 PL1504 0.22UH_MMD-10DZ-R22MES1L 35A_20% GPU_PH2 SIC632CDT1GE3_POWERPAK31_5X5 +VGA_CORE EMI@ PR1514 4.7_1206_5% PC1521 10U_0603_25V6M NVVDD_ISUMP2 GPU_SNB2 PC1520 10U_0805_25VAK PC1519 10U_0603_25V6M PC1518 10U_0805_25VAK EMI@ PC1517 2200P_0402_50V7K @EMI@ PC1516 0.1U_0402_25V6 1 +19VB_NVVDD 1 PW M ZCD_EN# VCIN CGND BOOT NC PHASE VIN VIN PGND SW SW SW SW PC1515 1U_0603_16V7 PR1513 PC1513 1U_0402_6.3V6K 0_0402_5% +5VS 10 11 12 13 14 GPU_PWM2 @ PR1511 PU1502 PR1510 1K_0402_1% C @ PR1508 +5VS EMI@ PC1522 680P_0402_50V7K NVVDD_ISUMN2 D D Compal Electronics, Inc Compal Secret Data Security Classification 2016/07/18 Issued Date Deciphered Date 2017/06/14 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title PWR_+NVVDD1 Size Rev 1.0 C5MMH M/B LAE911P Date: Document Number Thursday, February 22, 2018 Sheet 62 of 67 VGA@ VGA@ PC1789 22U_0603_6.3V6M VGA@ PC1790 22U_0603_6.3V6M VGA@ PC1791 22U_0603_6.3V6M @VGA@ PC1792 22U_0603_6.3V6M @VGA@ PC1793 22U_0603_6.3V6M VGA@ PC1794 22U_0603_6.3V6M VGA@ PC1795 22U_0603_6.3V6M VGA@ PC1796 22U_0603_6.3V6M PC1780 10U_0603_6.3V6M VGA@ PC1788 22U_0603_6.3V6M VGA@ PC1774 560U_2.5V_M VGA@ PC1777 220U_D2 SX_2VY_R9M @VGA@ PC1776 220U_D2 SX_2VY_R9M VGA@ PC1772 560U_2.5V_M VGA@ PC1773 220U_D2 SX_2VY_R9M VGA@ PC1771 220U_D2 SX_2VY_R9M VGA@ PC1798 22U_0603_6.3V6M VGA@ PC1797 22U_0603_6.3V6M VGA@ PC1786 22U_0603_6.3V6M VGA@ PC1785 22U_0603_6.3V6M VGA@ PC1784 22U_0603_6.3V6M VGA@ PC1783 22U_0603_6.3V6M VGA@ PC1782 22U_0603_6.3V6M 2 VGA@ VGA@ PC17992 10U_0603_6.3V6M 2 2 1 1 VGA@ VGA@ VGA@ VGA@ VGA@ @VGA@ @VGA@ @VGA@ VGA@ VGA@ @VGA@ VGA@ VGA@ VGA@ 2 2 2 2 2 1 1 1 1 1 VGA@ VGA@ VGA@ 2 1 1 VGA@ VGA@ VGA@ VGA@ PC1756 1U_0402_6.3V6K PC17991 10U_0603_6.3V6M PC1755 1U_0402_6.3V6K PC1799 10U_0603_6.3V6M PC1754 1U_0402_6.3V6K PC1728 10U_0603_6.3V6M PC1753 1U_0402_6.3V6K PC1727 10U_0603_6.3V6M PC1779 10U_0603_6.3V6M PC1778 10U_0603_6.3V6M PC1765 22U_0603_6.3V6M PC1764 22U_0603_6.3V6M PC1763 22U_0603_6.3V6M PC1762 22U_0805_6.3V6M PC1761 22U_0603_6.3V6M PC1760 22U_0805_6.3V6M PC1759 22U_0603_6.3V6M PC1758 22U_0603_6.3V6M PC1757 22U_0805_6.3V6M VGA@ PC1781 22U_0603_6.3V6M PC1752 1U_0402_6.3V6K PC1751 4.7U_0402_6.3V6M VGA@ PC1750 4.7U_0402_6.3V6M @VGA@ PC1749 22U_0603_6.3V6M VGA@ PC1748 22U_0603_6.3V6M VGA@ PC1747 22U_0603_6.3V6M VGA@ PC1775 10U_0603_6.3V6M VGA@ PC1770 10U_0603_6.3V6M VGA@ PC1769 10U_0603_6.3V6M VGA@ PC1746 10U_0603_6.3V6M VGA@ PC1745 10U_0603_6.3V6M PC1744 10U_0603_6.3V6M @VGA@ VGA@ PC1743 4.7U_0402_6.3V6M VGA@ PC1742 4.7U_0402_6.3V6M @VGA@ PC1741 4.7U_0402_6.3V6M VGA@ PC1740 4.7U_0402_6.3V6M @VGA@ @VGA@ PC1739 4.7U_0402_6.3V6M PC1738 4.7U_0402_6.3V6M VGA@ PC1737 4.7U_0402_6.3V6M VGA@ PC1736 4.7U_0402_6.3V6M VGA@ PC1735 4.7U_0402_6.3V6M VGA@ PC1734 4.7U_0402_6.3V6M VGA@ PC1733 4.7U_0402_6.3V6M VGA@ PC1732 4.7U_0402_6.3V6M VGA@ PC1731 4.7U_0402_6.3V6M VGA@ PC1730 4.7U_0402_6.3V6M PC1729 4.7U_0402_6.3V6M 2 @VGA@ @VGA@ PC1768 22U_0603_6.3V6M VGA@ PC1767 22U_0603_6.3V6M VGA@ PC1766 22U_0603_6.3V6M VGA@ PC1726 10U_0603_6.3V6M @VGA@ @VGA@ PC1725 10U_0603_6.3V6M PC1724 4.7U_0402_6.3V6M VGA@ PC1723 4.7U_0402_6.3V6M VGA@ PC1722 4.7U_0402_6.3V6M VGA@ PC1721 4.7U_0402_6.3V6M VGA@ PC1720 4.7U_0402_6.3V6M VGA@ PC1719 4.7U_0402_6.3V6M VGA@ PC1718 4.7U_0402_6.3V6M VGA@ PC1717 4.7U_0402_6.3V6M @VGA@ PC1716 4.7U_0402_6.3V6M PC1715 4.7U_0402_6.3V6M VGA@ PC1787 22U_0603_6.3V6M 2 VGA@ VGA@ PC1714 22U_0603_6.3V6M @VGA@ PC1713 22U_0603_6.3V6M VGA@ PC1712 22U_0603_6.3V6M @VGA@ PC1711 22U_0603_6.3V6M VGA@ VGA@ PC1710 22U_0603_6.3V6M PC1709 1U_0402_6.3V6K VGA@ PC1708 1U_0402_6.3V6K VGA@ PC1707 1U_0402_6.3V6K VGA@ PC1706 1U_0402_6.3V6K VGA@ PC1705 1U_0402_6.3V6K VGA@ PC1704 1U_0402_6.3V6K VGA@ PC1703 1U_0402_6.3V6K VGA@ PC1702 1U_0402_6.3V6K PC1701 1U_0402_6.3V6K 2 67 of 63 Sheet Thursday, February 22, 2018 Date: Rev 0.1 Document Number Size VGA DECOUPLING C5MMH M/B LAE911P THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title 2017/06/14 Deciphered Date 2016/07/18 Issued Date + + + 2 Compal Electronics, Inc Compal Secret Data Security Classification 1 + + + A A 1 B B D D C C +VGA_CORE +VGA_CORE 560uF_OS X 220uF_D2 X 3(+1@) 22uF_0805 X 0(+3@) 22uF_0603 X 27(+8@) 10uF_0603X 16 4.7uF_0402 X 20(+7@) 1uF_0402 X 14 +VGA_CORE 5 Version change list (P.I.R List) Item Fixed Issue Reason for change Rev 01 Design Update Solution Change 0.2 50 02 Design Update Solution Change 0.2 53 03 Design Update Solution Change 0.2 54 04 Design Update Solution Change 0.2 63 05 Design Update Down size for SNB MLCC 0.2 06 Design Update Solution Change 0.2 07 Design Update Down size for MLCC 0.2 A 59 Design Update Down size for EMI MLCC 0.2 48 09 Design Update Down size for MLCC 0.2 63 10 Design Update Solution Change 0.2 56 11 雷雷雷 Down size for Jump 0.2 53 12 Design Update Solution Change 0.2 、5 13 Design Update Solution Change 0.2 58 14 Design Update CPU transient test result 0.2 15 Design Update Power sequence 0.2 16 Design Update Solution Change 0.2 17 Design Update Solution Change 0.2 18 Design Update Solution Change 0.2 Page of for PWR Change the PQ310 from AON6366E (SB00001D800) to EMB04N03H (SB00001C500) Change the PQ311、P Q31 fro m AON6366E ( SB00001 D800) to AON7380 ( SB00001 G M00) Change the PC302、PC303 、 PC310、 PC3 1 、PC 312 f rom 0U_0603_ 25V ( SE00 000X2 00) t o 0U_0805_ 25V ( SE00 000Q K00) Delete the PC323 10U_0603_25V (SE00000X200) Change the PR603 (10K_0402_1%, SD034100280) from pop to un-pop Change the PR7126 (100K_0402_5%, SD028100380) from un-pop to pop Change the PR7126.2 net from +3VS to +3VALW Change the PC1748、PC1 761、 PC1710、PC1 2、PC1767、 PC 1768 ( 22U_0603_6 3V, SE0 0000M000) from po p to un-pop Change the PC1307 from 1U_6.3V_M_X5R_0603 (SE107105M80) to 1U_6.3V_K_X5R_0402 (SE000000K80) Phase 10/13 A2 10/13 A2 10/13 A2 10/13 A2 10/13 A2 10/13 A2 10/13 A2 Change the PC102 from 100P_50V_J_NPO_0603 (SE024101J80) to 100P_50V_J_NPO_0402 (SE071101J80) 10/13 Change the PC104 from 1000P_50V_K_X7R_0603 (SE025102K80) to 1000P_50V_K_X7R_0402 (SE074102K80) Change the PC1747、P C1 759 、 PC1 74 9、 P C1 58、 P C1764、 P C 766、 P C 17 10/13 from 22U_6.3V_M_X5R_0805(SE000000I10) to 22U_6.3V_M_X5R_0603 (SE00000M000) Change the PH8103、P H81 04 fro m 50K_5 %_0402_B25/50_4500K ( SL200002K00) to 220K_5 %_0402_B25/50_4700K ( SL200002I00) Change the PR8109、P R811 fro m 87K_0402_1 %( SD0348871 80) to 66K_0402_1 %( SD0348661 80) 10/23 Change the PR8118、P R811 fro m 93 K_0402_1 %( SD034931 280) to 57 6K_0402_1 %( SD034576280) A2 A2 A2 Change the PJ602 from 43X79 to 43X39 10/23 A2 Change the PC8113、PC81 24 、 PC81 0、 PC8159、PC8 from 0.47U_16V_Z_Y5V_0402 (SE000002F80) to 0.47U_6.3V_K_X5R_0402 (SE124474K80) Change the PC8310 from 0.47U_25V_K_X5R_0402 (SE00000WA00) to 0.47U_6.3V_K_X5R_0402 (SE124474K80) 10/25 A2 Add the location PC9164、PC91 65 、 PC91 66 and pop, 2U_6 3V _M_X5R_0603 ( SE0000 0M000) 10/26 A2 10/27 A2 Change 、5 7、 58 Change Change Change Change Change Change Change Change Change Change Change Change Change Change Change Change Change Change Change Change Change Change Change Change the PR8114 from 6.81K_0402_1% (SD034681180) to 5.76K_0402_1% (SD034576180) the PR8113 from 2.49K_0402_1% (SD034249180) to 1.8K_0402_1% (SD00000R580) the PR8117 from 560K_0402_1% (SD034560380) to 442K_0402_1% (SD034442300) the PR8116 from 510K_0402_1% (SD00000RK80) to 402K_0402_1% (SD034402380) the PR8141 from 100_0402_1% (SD034100080) to 8.2K_0402_1% (SD000004100) the PR8149 from 1.05K_0402_1% (SD00000J480) to 3.16K_0402_1% (SD000006580) the PR8176 from 20K_0402_1% (SD034200280) to 16.9K_0402_1% (SD034169280) the PR8310 from 63.4K_0402_1% (SD03463K280) to 59K_0402_1% (SD034590280) the PR8319 from 24.9K_0402_1% (SD034249280) to 22K_0402_1% (SD034220280) the PR8325 from 0_0402_5% (SD028000080) to 300_0402_1% (SD034300080) the PR8328 from 22K_0402_1% (SD034220280) to 20K_0402_1% (SD034200280) the PR8333 from 680_0402_1% (SD034680080) to 300_0402_1% (SD034300080) the PC8312 from 270P_0402_50V7K (SE074271K80) to 330P_0402_50V8J (SE000006I80) the PR8331 from 470_0603_1% (SD014470080) to 576_0603_1% (SD014576080) the PR8336 from 42.2_0402_1% (SD00000ZN00) to 255_0402_1% (SD034255080) the PR8134 from 121K_0402_1% (SD034121380) to 13.3K_0402_1% (SD034133280) the PR8138 from 49.9K_0402_1% (SD034499280) to 26.7K_0402_1% (SD034267280) the PR8147 from 3.32K_0402_1% (SD034332180) to 768_0402_1% (SD00000TT80) the PC9110、PC91 08 fro m 22 U_0603_6 3V6 M ( SE00000 M000) to un- pop the PC9112、PC911 fro m un- pop to 22 U_0603_6 3V6 M ( SE00000 M000) the PC8126 from 330P_0402_25V8J (SE00000FD80) to 330P_0402_50V8J (SE000006I80) the PR8173 from 0_0603_5% (SD013000080) to 10_0603_1% (SD014100A80) the PC8137 from 330P_0402_25V8J (SE00000FD80) to 270P_0402_50V7K (SE074271K80) the PC9159、PC91 60 fro m 22 U_0603_6 3V6 M( SE00000 M000) to un- pop the PC9057、PC9058 fro m un- pop to 22 U_0603_6 3V6 M( SE00000 M000) C B Change the PR1303 from 10K_0402_1% (SD034100280) to 1K_0402_1% (SD034100180) 11/02 A2 Change the PR1401 from 10K_0402_5% (SD028100280) to 4.7K_0402_5% (SD028470180) Change the PU1201 from UP9511P (SA00009SW00) to UP9511Q (SA0000BK300) 61 11/08 A2 Change the PR1243、P R1 247 fro m 0K_0402_5 % ( SD0281 00280) to 00K_0402_5 % ( SD0281 00380) 、5 6、 57 Change the PC8317、PC509 、 PC517 fr om U_0402_1 0V6K( SE0000 0QL10) to U_0201 _6 3V6K ( SE00000YB00) 11/08 A2 Change the PC8112、PC811 、 PC81 3、 PC8139、PC8 57、PC8161 fr o m U_0402_25V6K ( SE000010V00) t o U_0201 _6 3V6K ( SE00000YB00) 、5 Change the PR340、P Q31 、 PQ31 A、 PQ313B、 PR 32 7、 P Q3 07、 PQ30 fro m p op to un -po p A2 11/14 Change the PR326 from un-pop to 0_0603_5% (SD013000080) Change the PR310 from 51.1K_0402_1% (SD034511280) to 52.3K_0402_1% (SD034523280) Security Classification Compal Secret Data Change the PC8147 from Compal Electronics, Inc Title 2016/01/29 2017/06/14 Issued Date Deciphered Date 10U_0805_25V_X5R PIR (SE00000QK00) to un-pop THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS DH53F M/B LA-E951P MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC 、6 Date: Date D Change the PC315、PC1 308 、 PC1512、PC1 5 、5 9、 62 from 680P_50V_K_X7R_0603 (SE025681K80) to 680P_50V_K_X7R_0402 (SE074681K80) 59 Change the PQ1302 from 2N7002KW (SB000009Q80) to L2N7002WT1G (SB00000ST00) 08 B Modify List PG# D C Thursday, February 22, 2018 Sheet 64 of A R ev 0.1 67 D Version change list (P.I.R List) Item Fixed Issue 19 Design Update Reason for change Rev Solution Change 1.0 Page of for PWR Modify List Date Phase Change the PC313、PC31 fro m U_1 6V_X5R_0402( SE00000 OU00) to U_6 3V_X5R_0201 ( SE00000YB00) 12/15 C Change the PR304、P R31 、 PR316、 PR3 22、 PR 334、PR 81 1、 P R81 20、PR8128、P R81 39 、 PR81 2、 PR8143、PR8 53、 PR 4、 PR8155、P R81 65 、 P R81 0、 PR8175、 P R8 90、 P R 81 29、 PR81 63、PR8184、P R81 98 、 P R820 4、 P R83 08、 P R8 26 、 P R 83 39 、 PR8341、P R8342 、 PR834 6、 PR3 7、 PR 333 f r o m 0_040 2_5 %( SD0280000 80) to R-shor t 12/15 C PG# 50 20 Design Update Solution Change 1.0 、5 5 、5 21 Design Update Solution Change 1.0 50 Change the PC305、PC324 fro m U_0402_25V7K( SE00000 W21 0) to U_0402_25V6 ( SE00000G880) 12/18 C 22 Design Update Solution Change 1.0 56 12/18 C 23 Design Update SW2 un-pop 1.0 49 Change the PC8101、PC81 22 、 PC81 5、 PC8150、PC8158 f r om U_0603_50V7K( SE0251 04K80) to 0.1U 25V K X7R 0603 (SE042104K80) Change the PR217 from un-pop to 0_0402_5%(SD028000080) 12/18 C 24 Design Update Solution Change 1.0 50 Change the PR326、P R7202 fro m 0_0603_5 %( SD01 3000080) to R-short 12/18 C 25 Design Update Solution Change 1.0 56 Add PC8116、PC811 8, 33 U_D1 _25V M_R6 M( SGA0000 A400), and un- pop 12/19 C 12/20 C 4S_BATT 1.0 50 Design Update Solution Change 1.0 50 Design Update ACIN_CHG 1.0 50 Design Update Power sequence 1.0 60 26 Design Update 27 28 29 C 30 Design Update 3valw interfere 1.0 5 、5 31 Design Update Solution Change 1.A 55 Delete location PR326、P R327 、 P Q30 7、 P Q3 Add location PR338->2M_0402_1% (SD034200480)、P R339->1 00K_0402_1 %( SD0341 00380) Add location PQ315->LTC015EUBFS8TL(SB000011K00)、P Q31 6-> N7002K W1 N S OT323- ( SB00000ST00) Change the PC309 from 0.22U_0603_25V(SE000005Z80) to 0.47U_0402_16V(SE000002F80) Change the PR306 from 392K_0402_1%(SD034392380) to 499K_0402_1%(SD034499380) Change the PR310 from 52.3K_0402_1%(SD034523280) to 66.5K_0402_1%(SD034665280) Change the PR1406 from 10K_0402_1%(SD034100280) to 0_0402_5%(SD028000080) 12/21 C 12/25 C 12/27 C Change the Jump PJ7202、P J1 301 fro m short to open Change the bead PL7201、PL1 301 fro m un- pop to pop 0805_5 A ( S M01 000 U600) Change the PR7203 from un-pop to pop 4.7_1206_5% (SD001470B80) Change the PC7203 from un-pop to pop 680pF_0402_50V (SE074681K80) 01/10 C Change the PR7202 from R-short to 0_0603_5%(SD013000080) 01/12 C D C B B A A Compal Secret Data Security Classification Issued Date 2016/01/29 2017/06/14 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Size Document Number Custom R ev 0.1 C5MMH M/B LA-E911P Date: Compal Electronics, Inc PIR Thursday, February 22, 2018 Sheet 65 of 67 A B C D Version change list (P.I.R List) Item Page Title Page of for HW Issue Description Date Solution Description Rev 29 Design Update 9/27 power source optimization DGPU1.8V power source change to 1.8VALW A2 0.2 39 Design Update 9/27 version upgrade Change board ID to DVT (V15_ID1/VX15_ID11) A2 0.2 37 Design Update 10/17 CNVI power request A2 0.2 A2 0.2 41,42 44 Design Update 10/19 Design Update 10/19 Design Update 10/24 Design Update 10/25 Add RM44 for +3VALW to +3VS_WLAN ohm part count reduce RH186/RH47/RH103/RH105/RH97/RH98/RH99/RH100/ RD3/RD6/RD2/RD15/RD13/RD17/RM22/RM23/RM24/ RM25/RM26/RM27/RM28/RM29/RM30/RM31/RM32/ RM33/RM34/RM35/RM38/RM39/RM40/RS1/RS8/RS16/ R19/R20/RQ5/RQ9/RQ6 USB common voltage footprint update LS1/LS10 change footprint to "MURAT_DLM0NSN900HY2D_4P" A2 0.2 for cost, change 10uF_0402 to 0603 CV75, Cv83, CV86, Cc88, CV87, Cv83, Cv73, Cv82,Cv108, Cv119, Cv118, Cv110, Cv120, Cv121, Cv114, Cv115 , CC75, Cc73, Cc80, CC74,CC76, CC78, CC79, CX1 CX3, CA6, CA8, CA9, CA16, CA17, CC71, CC72, CC81, CC89, CC90, A2 0.2 USB CMC move to M/B add L11/ L12 for USB2.0 CMC A2 0.2 CNVI device detact issue add PU 100K RB78 for CNVI card detect reserved RB79 PD 0ohm for CNVI card detect EC add PIN89 GPIO50 as CNVI_DET# add PIN 19 CNVI_DET# A2 0.2 Phase E 39 Design Update 10/26 38 Design Update 10/26 for reserve dmic Change JDMIC1 to 4pin : SP02000TI00 A2 0.2 10 43 Design Update 11/02 SATA HDD redriver EQ tuning UNPOP RO17 for redriver EQ A2 0.2 11 25 Design Update 11/02 NV vga sequence tuning change RV105 to 8.2K (vga_core_en) RV12 change to 100k_1% (1.35VSDGPU_PWR_EN) RV113 change to 4.7k_5% PR1303 change to 1k PR1401 change to 4.7k A2 0.2 12 43 Design Update 11/06 co-lay no HDD re-driver circuit add CO14/CO16~18/RO21~24 for no re-driver A2 0.2 13 45 Design Update 11/13 for factory request, don't include SW1 in bom unpop SW1 and control by SMT memo A2 0.2 14 40 Design Update 11/13 replace level shift by ohm on Type-C circuit unpop QS1/RS107/RS108 POP RS114/RS115 A2 0.2 15 Design Update 11/13 fine tune crystal frequency 24Mhz Keep 33 18 /1M 25Mhz Keep 10 18 /330 27Mhz CV1 change to 15PF (15 12 /0) 32.768Khz change CH7/CH8 to 10PF (10 10 /10M) A2 0.2 16 Design Update 12/14 OHM change to R-short change RC17/RH5/RH6/RH94/RH96/RV125/RM2/RB19/RB76/RO4 /RS114/RS115 to R-short PVT 1.0 peci issue, can't get system temperature UNPOP RH41 PVT 1.0 17 18 Design Update 12/14 18 46 Design Update 12/14 unpop SW2(BI SW) PVT 1.0 19 39 Design Update 12/16 channge board ID to ver1.0 (V series 15k/ vx series 200k) PVT 1.0 20 40 Design Update 12/18 add RS116 on VBUS_EN_179 change US2 to SA00006Y700, add RS156/RS155/CS101/CS124 PVT 1.0 change typeC VCONN sol to G527 Compal Secret Data Security Classification Issued Date 2017/12/18 2018/09/01 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title B C D Compal Electronics, Inc PIR-HW1 Size Document Number Custom Rev 1.0 DH5VF M/B LA-F591PR01 Date: A Thursday, February 22, 2018 Sheet E 66 of 67 A B C D Version change list (P.I.R List) Item Page Title E Page of for HW Issue Description Date Solution Description Phase Rev 21 37 Design Update 12/18 BT lost issue reserve RM45 for pull up BT_ON to +3VS_WLAN PVT 1.0 22 25 Design Update 12/20 vga sequence tuning change RV105 to 6.2k / RV103 to 24.9k PVT 1.0 23 21 Design Update 12/20 intel sensitive net pop CH29 & CH34 PVT 1.0 24 45 Design Update 12/21 Change RS64,RS65,RS74,RS76,RS82~RS85 to 0201 size Add CS102~CS105,RS119~RS122 PVT 1.0 25 37 21 Design Update 12/22 CNVI lost issue reserve CM18 on CNV_RF_RESET# add CH52 0.1U on +1.8VALW_PRIM PVT 1.0 26 37 21 Design Update 12/26 CNVI lost issue reserve CM19 4.7uF on +3VS_WLAN reserve CH53_10uF on +1.8VALW_PRIM change RH100 R-short to 0_0603 PVT 1.0 27 38 Design Update 12/26 charmeleon down z-high on wi-fi card area change CA6/CA17 to 0402 package PVT 1.0 28 32 Design Update 12/26 improve HDMI layout PVT 1.0 29 18, 35 Design Update 01/11 improve optone layout for HM370 remove GPAK circuit for improve HDMI layout del U18/CV225/RV126/RV125/CG341/CG342 change PCIE port from 17-20 to 12-9 change from SSD_DEVSLP4 to SSD_DEVSLP1 change from SATA_GP4 to SATA_GP1 PVT 1A 30 18 Design Update 01/11 HDD port change to SATA0B PVT 1A 31 32 Design Update 01/11 PVT 1A 32 Design Update 02/22 change PN for MP chip UC1/UH1/UV1/ change to MP part number 33 19 Design Update 02/22 PVT memo improve POP RH183 Remove CQ7/CQ8 intel ECN_Update JTYPEC1.A2/A3/B2/B3 change to NET NAME PVT 1A PVT 1A 3 4 Compal Secret Data Security Classification Issued Date 2017/12/18 2018/09/01 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title B C D PIR-HW1 Size Document Number Custom Rev 1.0 DH5VF M/B LA-F591PR01 Date: A Compal Electronics, Inc Thursday, February 22, 2018 Sheet E 67 of 67 ... +LAN_VDD RL14 330_0402_5% XTLO_R +3V_LAN Transceiver Interface LAN_MIDI0+ LAN_MIDI0LAN_MIDI1+ LAN_MIDI1LAN_MIDI2+ LAN_MIDI2LAN_MIDI3+ LAN_MIDI3- RL18 15K_0402_5% @ PVT modify 01/06 R2534, R2537,... PCIE_PRX_DTX_P15 PCIE_PRX_DTX_N15 CLK_PCIE_W LAN CLK_PCIE_W LAN# W LAN_CLKREQ# W LAN_PME# CLK_PCIE_W LAN CLK_PCIE_W LAN# W LAN_CLKREQ# W LAN_PME# RM28 RM29 0_0201_5% CNV_PTX_R_DRX_N1... VCCPGPPHK1 VCCPGPPHK2 VCCPGPPEF1 VCCPGPPEF2 VCCPRIM_1P 0523 VCCPRIM_1P 0524 VCCPRIM_1P 0525 VCCPRIM_1P 0526 VCCPRIM_1P 0527 VCCPRIM_1P 0528 VCCPRIM_1P 0529 VCCPGPPD VCCPGPPBC1 VCCPGPPBC2 VCCPRIM_1P0514 VCCPGPPA