Acer aspire 5220 COMPAL LA 3581p REV 1 0

A B C D E 1 Compal Confidential 2 ICW50 Schematics Document AMD Turion/Sempron + Nvidia MCP67-MV 2007 / 04 / 20 Rev:1.0 FOR Pre-MP 3 4 Compal Electronics, Inc Compal Secret Data Security Classification 2006/08/18 Issued Date Deciphered Date 2007/8/18 Cover Sheet THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C Title D Size Document Number Custom ICW50 / ICY70 Date: Rev 1.0 LA-3581P Friday, April 20, 2007 Sheet E of 42 Compal confidential Project Code: ICW50 File Name : LA-3581P Thermal Sensor ADM1032ARM DDRII AMD Turion/Sempron CPU Socket S1 638P DDRII-SO-DIMM X2 page 08,09 page 4,5,6,7 page 533/667/800 Dual Channel HT LINK D D 200-800MHz DVI-D Conn LCD Conn page 20 CRT & TV-out page 20 page 19 LVDS DVI USB conn x4 Nvidia MCP67-MV page 25,26 836 BGA LVDS MXM II VGA/B HD Audio 3.3V 24.576MHz/48Mhz IDE BUS 3.3V ATA-100 PCI-Express CDROM Conn page 21 port PCI BUS MINI Card x2 PHY(GbE) WLAN, TV-Tuner RTL8211B IDSEL:AD20 (PIRQE#, GNT#0, REQ#0) page 22 29 20 SATA BUS page 18 New Card Socket CMOS Camera page USB 2.0 BUS PCI-Express C Bluetooth Conn page S-ATA HDD Conn page 21 3.3V 33 MHz HDA Codec ALC268 page 31 C Audio AMP page 10,11,12,13,14,15,16,17 page 32 Card Reader RICOH R5C833 Phone Jack x3 LPC BUS page 23 RJ45 MDC 1.5 Conn page 29 page 32 page 22 1394 Conn B page 23 in socket B ENE KB926 page 24 page 27,28 Power On/Off CKT / LID switch / Power OK CKT page 30 Int.KBD Touch Pad page 29 DC/DC Interface CKT page 33 CIR/LED page 29 page 29 RTC CKT page 16 EC I/O Buffer BIOS page 29 Power Circuit DC/DC page 29 page 35~41 CIR page 30 A A Compal Secret Data Security Classification 2006/08/18 Issued Date 2007/8/18 Deciphered Date Title BLOCK DIAGRAM THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Size Document Number Custom ICW50 / ICY70 Date: Rev 1.0 LA-3581P Sheet Friday, April 20, 2007 of 42 SIGNAL STATE Voltage Rails D C +VALW +V +VS Clock HIGH HIGH ON ON ON ON S1(Power On Suspend) LOW HIGH HIGH ON ON ON LOW S3 (Suspend to RAM) LOW LOW HIGH ON ON OFF OFF S4 (Suspend to Disk) LOW LOW HIGH ON OFF OFF OFF S5 (Soft OFF) LOW LOW LOW ON OFF OFF OFF Power Plane Description S1 S3 S5 Adapter power supply (19V) N/A N/A N/A B+ AC or battery power rail for power circuit N/A N/A N/A +CPU_CORE Core voltage for CPU ON OFF OFF +0.9V 0.9V switched power rail for DDR terminator ON ON OFF +1.5VS 1.5V switched power rail ON OFF OFF +1.2VALW 1.2V always on power rail ON ON ON* +1.2VS 1.2V switched power rail ON OFF OFF +1.2V_HT 1.2V switched power rail ON OFF OFF +1.8V 1.8V power rail for DDR ON ON OFF Vcc Ra/Rc/Re +1.8VS 1.8V switched power rail ON OFF OFF Board ID +2.5VS 2.5V switched power rail ON OFF OFF 3.3V always on power rail ON ON ON* +3VS 3.3V switched power rail ON OFF OFF +5VALW 5V always on power rail ON ON ON* +5VS 5V switched power rail ON OFF OFF +VSB VSB always on power rail ON ON ON* +RTCVCC RTC power ON ON ON D Board ID / SKU ID Table for AD channel Board ID External PCI Devices IDSEL# 1394 AD20 REQ#/GNT# 3.3V +/- 5% 100K +/- 5% Rb / Rd / Rf 8.2K +/- 5% 18K +/- 5% 33K +/- 5% 56K +/- 5% 100K +/- 5% 200K +/- 5% NC V AD_BID V 0.216 V 0.436 V 0.712 V 1.036 V 1.453 V 1.935 V 2.500 V V AD_BID typ V 0.250 V 0.503 V 0.819 V 1.185 V 1.650 V 2.200 V 3.300 V Interrupts PIRQE Device Address Smart Battery 0001 011X b EC SM Bus2 address Device ADM1032 PCB Revision UMA (0V) DISCRETE (3.3V) SKU ID Table SKU ID Address 1001 100X b MCP67 SM Bus address Device Address DDR DIMM0 1001 000Xb DDR DIMM2 1001 001Xb C BTO Option Table B EC SM Bus1 address V AD_BID max V 0.289 V 0.538 V 0.875 V 1.264 V 1.759 V 2.341 V 3.300 V BOARD ID Table Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF Device SLP_S1# SLP_S3# SLP_S5# HIGH Full ON VIN +3VALW/+3V/+3VAUX SKU B - PHASE C - PHASE BTO Item BOM Structure DIP CAP & RTC 45@ UMA UMA@ VGA VGA@ UMA & TV-OUT UMA&TV@ SATA HDD SATA2@ CAMERA CMOS@ BLUETOOTH BT@ MINI CARD 1(TV) MINI1@ MINI CARD 2(WLAN) MINI2@ NEW CARD EXPRESS@ TV-OUT TV@ DVI DVI@ 1394 1394@ CARD READER 5IN1@ HT Debug Port HT@ B A A Compal Secret Data Security Classification 2006/08/18 Issued Date 2007/8/18 Deciphered Date Title TABLE OF CONTENTS THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Size Document Number Custom ICW50 / ICY70 Date: Rev 1.0 LA-3581P Sheet Friday, April 20, 2007 of 42 PROCESSOR HYPERTRANSPORT INTERFACE VLDT_Ax AND VLDT_Bx ARE CONNECTED TO THE LDT_RUN POWER SUPPLY THROUGH THE PACKAGE OR ON THE DIE IT IS ONLY CONNECTED ON THE BOARD TO DECOUPLING NEAR THE CPU PACKAGE D D FAN Conn +1.2V_HT JP22A C +1.2V_HT (10) (10) (10) (10) H_CLKIP1 H_CLKIN1 H_CLKIP0 H_CLKIN0 H_CLKIP1 H_CLKIN1 H_CLKIP0 H_CLKIN0 J5 K5 J3 J2 L0_CLKIN_H1 L0_CLKIN_L1 L0_CLKIN_H0 L0_CLKIN_L0 L0_CADOUT_H15 L0_CADOUT_L15 L0_CADOUT_H14 L0_CADOUT_L14 L0_CADOUT_H13 L0_CADOUT_L13 L0_CADOUT_H12 L0_CADOUT_L12 L0_CADOUT_H11 L0_CADOUT_L11 L0_CADOUT_H10 L0_CADOUT_L10 L0_CADOUT_H9 L0_CADOUT_L9 L0_CADOUT_H8 L0_CADOUT_L8 L0_CADOUT_H7 L0_CADOUT_L7 L0_CADOUT_H6 L0_CADOUT_L6 L0_CADOUT_H5 L0_CADOUT_L5 L0_CADOUT_H4 L0_CADOUT_L4 L0_CADOUT_H3 L0_CADOUT_L3 L0_CADOUT_H2 L0_CADOUT_L2 L0_CADOUT_H1 L0_CADOUT_L1 L0_CADOUT_H0 L0_CADOUT_L0 T4 T3 V5 U5 V4 V3 Y5 W5 AB5 AA5 AB4 AB3 AD5 AC5 AD4 AD3 T1 R1 U2 U3 V1 U1 W2 W3 AA2 AA3 AB1 AA1 AC2 AC3 AD1 AC1 H_CADOP15 H_CADON15 H_CADOP14 H_CADON14 H_CADOP13 H_CADON13 H_CADOP12 H_CADON12 H_CADOP11 H_CADON11 H_CADOP10 H_CADON10 H_CADOP9 H_CADON9 H_CADOP8 H_CADON8 H_CADOP7 H_CADON7 H_CADOP6 H_CADON6 H_CADOP5 H_CADON5 H_CADOP4 H_CADON4 H_CADOP3 H_CADON3 H_CADOP2 H_CADON2 H_CADOP1 H_CADON1 H_CADOP0 H_CADON0 Y4 Y3 Y1 W1 H_CLKOP1 H_CLKON1 H_CLKOP0 H_CLKON0 L0_CLKOUT_H1 L0_CLKOUT_L1 L0_CLKOUT_H0 L0_CLKOUT_L0 H_CLKOP1 H_CLKON1 H_CLKOP0 H_CLKON0 (10) (10) (10) (10) (10) (10) (10) (10) (10) (10) (10) (10) (10) (10) (10) (10) (10) (10) (10) (10) (10) (10) (10) (10) (10) (10) (10) (10) (10) (10) (10) (10) W=40mils 51_0402_1% 51_0402_1% (10) H_CTLIP0 (10) H_CTLIN0 H_CTLIP1 H_CTLIN1 P3 P4 H_CTLIP0 H_CTLIN0 N1 P1 L0_CTLOUT_H1 L0_CTLOUT_L1 T5 R5 L0_CTLIN_H0 L0_CTLOUT_H0 L0_CTLIN_L0 L0_CTLOUT_L0 FOX_PZ63823-284S-41F R2 R3 L0_CTLIN_H1 L0_CTLIN_L1 B H_CTLOP0 H_CTLON0 +VCC_FAN1 FAN1 +3VS R88 10K_0402_5% C510 10U_0805_10V4Z C509 1000P_0402_50V7K D21 BAS16_SOT23-3 Update Footprint JP16 (27,28) FAN_SPEED1 C ACES_85205-03001 C52 1000P_0402_50V7K U11 +5VS +VCC_FAN1 (27,28) EN_DFAN1 (10) (10) (10) (10) EN_DFAN1 R1431 R1421 D20 1SS355_SOD323-2 H_CADOP15 H_CADON15 H_CADOP14 H_CADON14 H_CADOP13 H_CADON13 H_CADOP12 H_CADON12 H_CADOP11 H_CADON11 H_CADOP10 H_CADON10 H_CADOP9 H_CADON9 H_CADOP8 H_CADON8 H_CADOP7 H_CADON7 H_CADOP6 H_CADON6 H_CADOP5 H_CADON5 H_CADOP4 H_CADON4 H_CADOP3 H_CADON3 H_CADOP2 H_CADON2 H_CADOP1 H_CADON1 H_CADOP0 H_CADON0 L0_CADIN_H15 L0_CADIN_L15 L0_CADIN_H14 L0_CADIN_L14 L0_CADIN_H13 L0_CADIN_L13 L0_CADIN_H12 L0_CADIN_L12 L0_CADIN_H11 L0_CADIN_L11 L0_CADIN_H10 L0_CADIN_L10 L0_CADIN_H9 L0_CADIN_L9 L0_CADIN_H8 L0_CADIN_L8 L0_CADIN_H7 L0_CADIN_L7 L0_CADIN_H6 L0_CADIN_L6 L0_CADIN_H5 L0_CADIN_L5 L0_CADIN_H4 L0_CADIN_L4 L0_CADIN_H3 L0_CADIN_L3 L0_CADIN_H2 L0_CADIN_L2 L0_CADIN_H1 L0_CADIN_L1 L0_CADIN_H0 L0_CADIN_L0 N5 P5 M3 M4 L5 M5 K3 K4 H3 H4 G5 H5 F3 F4 E5 F5 N3 N2 L1 M1 L3 L2 J1 K1 G1 H1 G3 G2 E1 F1 E3 E2 +5VS H_CADIP15 H_CADIN15 H_CADIP14 H_CADIN14 H_CADIP13 H_CADIN13 H_CADIP12 H_CADIN12 H_CADIP11 H_CADIN11 H_CADIP10 H_CADIN10 H_CADIP9 H_CADIN9 H_CADIP8 H_CADIN8 H_CADIP7 H_CADIN7 H_CADIP6 H_CADIN6 H_CADIP5 H_CADIN5 H_CADIP4 H_CADIN4 H_CADIP3 H_CADIN3 H_CADIP2 H_CADIN2 H_CADIP1 H_CADIN1 H_CADIP0 H_CADIN0 VLDT_B3 VLDT_B2 VLDT_B1 VLDT_B0 H_CADIP15 H_CADIN15 H_CADIP14 H_CADIN14 H_CADIP13 H_CADIN13 H_CADIP12 H_CADIN12 H_CADIP11 H_CADIN11 H_CADIP10 H_CADIN10 H_CADIP9 H_CADIN9 H_CADIP8 H_CADIN8 H_CADIP7 H_CADIN7 H_CADIP6 H_CADIN6 H_CADIP5 H_CADIN5 H_CADIP4 H_CADIN4 H_CADIP3 H_CADIN3 H_CADIP2 H_CADIN2 H_CADIP1 H_CADIN1 H_CADIP0 H_CADIN0 VLDT_A3 VLDT_A2 VLDT_A1 VLDT_A0 C533 4.7U_0805_10V4Z AE5 AE4 AE3 AE2 HTT Interface (10) (10) (10) (10) (10) (10) (10) (10) (10) (10) (10) (10) (10) (10) (10) (10) (10) (10) (10) (10) (10) (10) (10) (10) (10) (10) (10) (10) (10) (10) (10) (10) D4 D3 D2 D1 VEN VIN VO VSET GND GND GND GND G993P1UF_SOP8 C310 10U_0805_10V4Z FAN1 Conn H_CTLOP0 (10) H_CTLON0 (10) B Athlon 64 S1 Processor Socket +1.2V_HT C542 4.7U_0805_10V4Z C541 4.7U_0805_10V4Z C536 0.22U_0402_10V4Z C539 180P_0402_50V8J 1 2 C540 0.22U_0402_10V4Z 2 C538 180P_0402_50V8J LAYOUT: Place bypass cap on topside of board NEAR HT POWER PINS THAT ARE NOT CONNECTED DIRECTLY TO DOWNSTREAM HT DEVICE, BUT CONNECTED INTERNALLY TO OTHER HT POWER PINS PLACE CLOSE TO VLDT0 POWER PINS A A Compal Secret Data Security Classification 2006/08/18 Issued Date 2007/8/18 Deciphered Date Title AMD CPU HT I/F THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Size Document Number Custom ICW50 / ICY70 Date: Rev 1.0 LA-3581P Sheet Friday, April 20, 2007 of 42 A B C D E Processor DDR2 Memory Interface JP22C +1.8V +0.9VREF_CPU +0.9V JP22B 10:8:10:8:10 R388 39.2_0402_1%~D PLACE THEM CLOSE TO CPU WITHIN 1" Y10 AE10 AF10 (8) (8) (8) (8) DDR_CS3_DIMMA# DDR_CS2_DIMMA# DDR_CS1_DIMMA# DDR_CS0_DIMMA# (9) (9) (9) (9) DDR_CS3_DIMMB# DDR_CS2_DIMMB# DDR_CS1_DIMMB# DDR_CS0_DIMMB# (9) DDR_CKE1_DIMMB (9) DDR_CKE0_DIMMB (8) DDR_CKE1_DIMMA (8) DDR_CKE0_DIMMA (8) DDR_A_MA[15 0] MA0_CS_L3 MA0_CS_L2 MA0_CS_L1 MA0_CS_L0 DDR_CS3_DIMMB# DDR_CS2_DIMMB# DDR_CS1_DIMMB# DDR_CS0_DIMMB# Y26 J24 W24 U23 MB0_CS_L3 MB0_CS_L2 MB0_CS_L1 MB0_CS_L0 DDR_CKE1_DIMMB DDR_CKE0_DIMMB DDR_CKE1_DIMMA DDR_CKE0_DIMMA H26 J23 J20 J21 MB_CKE1 MB_CKE0 MA_CKE1 MA_CKE0 DDR_A_MA15 DDR_A_MA14 DDR_A_MA13 DDR_A_MA12 DDR_A_MA11 DDR_A_MA10 DDR_A_MA9 DDR_A_MA8 DDR_A_MA7 DDR_A_MA6 DDR_A_MA5 DDR_A_MA4 DDR_A_MA3 DDR_A_MA2 DDR_A_MA1 DDR_A_MA0 K19 K20 V24 K24 L20 R19 L19 L22 L21 M19 M20 M24 M22 N22 N21 R21 MA_ADD15 MA_ADD14 MA_ADD13 MA_ADD12 MA_ADD11 MA_ADD10 MA_ADD9 MA_ADD8 MA_ADD7 MA_ADD6 MA_ADD5 MA_ADD4 MA_ADD3 MA_ADD2 MA_ADD1 MA_ADD0 DDR_A_BS#2 DDR_A_BS#1 DDR_A_BS#0 K22 R20 T22 MA_BANK2 MA_BANK1 MA_BANK0 DDR_A_RAS# DDR_A_CAS# DDR_A_WE# T20 U20 U21 (8) DDR_A_RAS# (8) DDR_A_CAS# (8) DDR_A_WE# Y16 AA16 E16 F16 MB0_CLK_H2 MB0_CLK_L2 MB0_CLK_H1 MB0_CLK_L1 AF18 DDR_B_CLK2 AF17 DDR_B_CLK#2 A17 DDR_B_CLK1 A18 DDR_B_CLK#1 M_ZN M_ZP V19 J22 V22 T19 (8) DDR_A_BS#2 (8) DDR_A_BS#1 (8) DDR_A_BS#0 MA0_CLK_H2 MA0_CLK_L2 MA0_CLK_H1 MA0_CLK_L1 VTT_SENSE DDR_CS3_DIMMA# DDR_CS2_DIMMA# DDR_CS1_DIMMA# DDR_CS0_DIMMA# D10 C10 B10 AD10 W10 AC10 AB10 AA10 A10 MA_RAS_L MA_CAS_L MA_WE_L FOX_PZ63823-284S-41F Athlon 64 S1 Processor Socket DDR_A_CLK2 DDR_A_CLK#2 DDR_A_CLK1 DDR_A_CLK#1 (8) (8) (8) (8) DDR_B_CLK2 DDR_B_CLK#2 DDR_B_CLK1 DDR_B_CLK#1 (9) (9) (9) (9) MB0_ODT1 MB0_ODT0 MA0_ODT1 MA0_ODT0 W23 W26 V20 U19 DDR_B_ODT1 DDR_B_ODT0 DDR_A_ODT1 DDR_A_ODT0 MB_ADD15 MB_ADD14 MB_ADD13 MB_ADD12 MB_ADD11 MB_ADD10 MB_ADD9 MB_ADD8 MB_ADD7 MB_ADD6 MB_ADD5 MB_ADD4 MB_ADD3 MB_ADD2 MB_ADD1 MB_ADD0 J25 J26 W25 L23 L25 U25 L24 M26 L26 N23 N24 N25 N26 P24 P26 T24 DDR_B_MA15 DDR_B_MA14 DDR_B_MA13 DDR_B_MA12 DDR_B_MA11 DDR_B_MA10 DDR_B_MA9 DDR_B_MA8 DDR_B_MA7 DDR_B_MA6 DDR_B_MA5 DDR_B_MA4 DDR_B_MA3 DDR_B_MA2 DDR_B_MA1 DDR_B_MA0 MB_BANK2 MB_BANK1 MB_BANK0 K26 DDR_B_BS#2 T26 DDR_B_BS#1 U26 DDR_B_BS#0 DDR_B_BS#2 (9) DDR_B_BS#1 (9) DDR_B_BS#0 (9) MB_RAS_L MB_CAS_L MB_WE_L U24 DDR_B_RAS# V26 DDR_B_CAS# U22 DDR_B_WE# DDR_B_RAS# (9) DDR_B_CAS# (9) DDR_B_WE# (9) DDR_B_ODT1 (9) DDR_B_ODT0 (9) DDR_A_ODT1 (8) DDR_A_ODT0 (8) DDR_B_MA[15 0] (9) (9) DDR_B_DM[7 0] DDR_A_CLK2 DDR_B_CLK2 DDR_A_CLK#2 C336 1.5P_0402_50V8C DDR_B_CLK#2 DDR_A_CLK1 C349 1.5P_0402_50V8C DDR_B_CLK1 DDR_A_CLK#1 DDR_A_CLK2 DDR_A_CLK#2 DDR_A_CLK1 DDR_A_CLK#1 To reverse SODIMM socket VTT_SENSE TP2 M_ZN M_ZP 2 PAD VTT1 VTT2 VTT3 VTT4 VTT5 VTT6 VTT7 VTT8 VTT9 M_VREF DDRII Cmd/Ctrl//Clk W17 R386 39.2_0402_1%~D C344 1.5P_0402_50V8C DDR_B_CLK#1 PLACE CLOSE TO PROCESSOR WITHIN 1.2 INCH C348 1.5P_0402_50V8C PLACE CLOSE TO PROCESSOR WITHIN 1.2 INCH (9) (9) (9) (9) (9) (9) (9) (9) (9) (9) (9) (9) (9) (9) (9) (9) DDR_B_DQS7 DDR_B_DQS#7 DDR_B_DQS6 DDR_B_DQS#6 DDR_B_DQS5 DDR_B_DQS#5 DDR_B_DQS4 DDR_B_DQS#4 DDR_B_DQS3 DDR_B_DQS#3 DDR_B_DQS2 DDR_B_DQS#2 DDR_B_DQS1 DDR_B_DQS#1 DDR_B_DQS0 DDR_B_DQS#0 DDR_B_D63 DDR_B_D62 DDR_B_D61 DDR_B_D60 DDR_B_D59 DDR_B_D58 DDR_B_D57 DDR_B_D56 DDR_B_D55 DDR_B_D54 DDR_B_D53 DDR_B_D52 DDR_B_D51 DDR_B_D50 DDR_B_D49 DDR_B_D48 DDR_B_D47 DDR_B_D46 DDR_B_D45 DDR_B_D44 DDR_B_D43 DDR_B_D42 DDR_B_D41 DDR_B_D40 DDR_B_D39 DDR_B_D38 DDR_B_D37 DDR_B_D36 DDR_B_D35 DDR_B_D34 DDR_B_D33 DDR_B_D32 DDR_B_D31 DDR_B_D30 DDR_B_D29 DDR_B_D28 DDR_B_D27 DDR_B_D26 DDR_B_D25 DDR_B_D24 DDR_B_D23 DDR_B_D22 DDR_B_D21 DDR_B_D20 DDR_B_D19 DDR_B_D18 DDR_B_D17 DDR_B_D16 DDR_B_D15 DDR_B_D14 DDR_B_D13 DDR_B_D12 DDR_B_D11 DDR_B_D10 DDR_B_D9 DDR_B_D8 DDR_B_D7 DDR_B_D6 DDR_B_D5 DDR_B_D4 DDR_B_D3 DDR_B_D2 DDR_B_D1 DDR_B_D0 AD11 AF11 AF14 AE14 Y11 AB11 AC12 AF13 AF15 AF16 AC18 AF19 AD14 AC14 AE18 AD18 AD20 AC20 AF23 AF24 AF20 AE20 AD22 AC22 AE25 AD26 AA25 AA26 AE24 AD24 AA23 AA24 G24 G23 D26 C26 G26 G25 E24 E23 C24 B24 C20 B20 C25 D24 A21 D20 D18 C18 D14 C14 A20 A19 A16 A15 A13 D12 E11 G11 B14 A14 A11 C11 MB_DATA63 MB_DATA62 MB_DATA61 MB_DATA60 MB_DATA59 MB_DATA58 MB_DATA57 MB_DATA56 MB_DATA55 MB_DATA54 MB_DATA53 MB_DATA52 MB_DATA51 MB_DATA50 MB_DATA49 MB_DATA48 MB_DATA47 MB_DATA46 MB_DATA45 MB_DATA44 MB_DATA43 MB_DATA42 MB_DATA41 MB_DATA40 MB_DATA39 MB_DATA38 MB_DATA37 MB_DATA36 MB_DATA35 MB_DATA34 MB_DATA33 MB_DATA32 MB_DATA31 MB_DATA30 MB_DATA29 MB_DATA28 MB_DATA27 MB_DATA26 MB_DATA25 MB_DATA24 MB_DATA23 MB_DATA22 MB_DATA21 MB_DATA20 MB_DATA19 MB_DATA18 MB_DATA17 MB_DATA16 MB_DATA15 MB_DATA14 MB_DATA13 MB_DATA12 MB_DATA11 MB_DATA10 MB_DATA9 MB_DATA8 MB_DATA7 MB_DATA6 MB_DATA5 MB_DATA4 MB_DATA3 MB_DATA2 MB_DATA1 MB_DATA0 DDR_B_DM7 DDR_B_DM6 DDR_B_DM5 DDR_B_DM4 DDR_B_DM3 DDR_B_DM2 DDR_B_DM1 DDR_B_DM0 AD12 AC16 AE22 AB26 E25 A22 B16 A12 MB_DM7 MB_DM6 MB_DM5 MB_DM4 MB_DM3 MB_DM2 MB_DM1 MB_DM0 DDR_B_DQS7 DDR_B_DQS#7 DDR_B_DQS6 DDR_B_DQS#6 DDR_B_DQS5 DDR_B_DQS#5 DDR_B_DQS4 DDR_B_DQS#4 DDR_B_DQS3 DDR_B_DQS#3 DDR_B_DQS2 DDR_B_DQS#2 DDR_B_DQS1 DDR_B_DQS#1 DDR_B_DQS0 DDR_B_DQS#0 AF12 AE12 AE16 AD16 AF21 AF22 AC25 AC26 F26 E26 A24 A23 D16 C16 C12 B12 MB_DQS_H7 MB_DQS_L7 MB_DQS_H6 MB_DQS_L6 MB_DQS_H5 MB_DQS_L5 MB_DQS_H4 MB_DQS_L4 MB_DQS_H3 MB_DQS_L3 MB_DQS_H2 MB_DQS_L2 MB_DQS_H1 MB_DQS_L1 MB_DQS_H0 MB_DQS_L0 MA_DATA63 MA_DATA62 MA_DATA61 MA_DATA60 MA_DATA59 MA_DATA58 MA_DATA57 MA_DATA56 MA_DATA55 MA_DATA54 MA_DATA53 MA_DATA52 MA_DATA51 MA_DATA50 MA_DATA49 MA_DATA48 MA_DATA47 MA_DATA46 MA_DATA45 MA_DATA44 MA_DATA43 MA_DATA42 MA_DATA41 MA_DATA40 MA_DATA39 MA_DATA38 MA_DATA37 MA_DATA36 MA_DATA35 MA_DATA34 MA_DATA33 MA_DATA32 MA_DATA31 MA_DATA30 MA_DATA29 MA_DATA28 MA_DATA27 MA_DATA26 MA_DATA25 MA_DATA24 MA_DATA23 MA_DATA22 MA_DATA21 MA_DATA20 MA_DATA19 MA_DATA18 MA_DATA17 MA_DATA16 MA_DATA15 MA_DATA14 MA_DATA13 MA_DATA12 MA_DATA11 MA_DATA10 MA_DATA9 MA_DATA8 MA_DATA7 MA_DATA6 MA_DATA5 MA_DATA4 MA_DATA3 MA_DATA2 MA_DATA1 MA_DATA0 AA12 AB12 AA14 AB14 W11 Y12 AD13 AB13 AD15 AB15 AB17 Y17 Y14 W14 W16 AD17 Y18 AD19 AD21 AB21 AB18 AA18 AA20 Y20 AA22 Y22 W21 W22 AA21 AB22 AB24 Y24 H22 H20 E22 E21 J19 H24 F22 F20 C23 B22 F18 E18 E20 D22 C19 G18 G17 C17 F14 E14 H17 E17 E15 H15 E13 C13 H12 H11 G14 H14 F12 G12 DDR_A_D63 DDR_A_D62 DDR_A_D61 DDR_A_D60 DDR_A_D59 DDR_A_D58 DDR_A_D57 DDR_A_D56 DDR_A_D55 DDR_A_D54 DDR_A_D53 DDR_A_D52 DDR_A_D51 DDR_A_D50 DDR_A_D49 DDR_A_D48 DDR_A_D47 DDR_A_D46 DDR_A_D45 DDR_A_D44 DDR_A_D43 DDR_A_D42 DDR_A_D41 DDR_A_D40 DDR_A_D39 DDR_A_D38 DDR_A_D37 DDR_A_D36 DDR_A_D35 DDR_A_D34 DDR_A_D33 DDR_A_D32 DDR_A_D31 DDR_A_D30 DDR_A_D29 DDR_A_D28 DDR_A_D27 DDR_A_D26 DDR_A_D25 DDR_A_D24 DDR_A_D23 DDR_A_D22 DDR_A_D21 DDR_A_D20 DDR_A_D19 DDR_A_D18 DDR_A_D17 DDR_A_D16 DDR_A_D15 DDR_A_D14 DDR_A_D13 DDR_A_D12 DDR_A_D11 DDR_A_D10 DDR_A_D9 DDR_A_D8 DDR_A_D7 DDR_A_D6 DDR_A_D5 DDR_A_D4 DDR_A_D3 DDR_A_D2 DDR_A_D1 DDR_A_D0 MA_DM7 MA_DM6 MA_DM5 MA_DM4 MA_DM3 MA_DM2 MA_DM1 MA_DM0 Y13 AB16 Y19 AC24 F24 E19 C15 E12 DDR_A_DM7 DDR_A_DM6 DDR_A_DM5 DDR_A_DM4 DDR_A_DM3 DDR_A_DM2 DDR_A_DM1 DDR_A_DM0 MA_DQS_H7 MA_DQS_L7 MA_DQS_H6 MA_DQS_L6 MA_DQS_H5 MA_DQS_L5 MA_DQS_H4 MA_DQS_L4 MA_DQS_H3 MA_DQS_L3 MA_DQS_H2 MA_DQS_L2 MA_DQS_H1 MA_DQS_L1 MA_DQS_H0 MA_DQS_L0 W12 W13 Y15 W15 AB19 AB20 AD23 AC23 G22 G21 C22 C21 G16 G15 G13 H13 DDR_A_DQS7 DDR_A_DQS#7 DDR_A_DQS6 DDR_A_DQS#6 DDR_A_DQS5 DDR_A_DQS#5 DDR_A_DQS4 DDR_A_DQS#4 DDR_A_DQS3 DDR_A_DQS#3 DDR_A_DQS2 DDR_A_DQS#2 DDR_A_DQS1 DDR_A_DQS#1 DDR_A_DQS0 DDR_A_DQS#0 DDR_A_D[63 0] (8) To normal SODIMM socket (9) DDR_B_D[63 0] DDRII Data VDD_VTT_SUS_CPU IS CONNECTED TO THE VDD_VTT_SUS POWER SUPPLY THROUGH THE PACKAGE OR ON THE DIE IT IS ONLY CONNECTED ON THE BOARD TO DECOUPLING NEAR THE CPU PACKAGE DDR_A_DM[7 0] DDR_A_DQS7 DDR_A_DQS#7 DDR_A_DQS6 DDR_A_DQS#6 DDR_A_DQS5 DDR_A_DQS#5 DDR_A_DQS4 DDR_A_DQS#4 DDR_A_DQS3 DDR_A_DQS#3 DDR_A_DQS2 DDR_A_DQS#2 DDR_A_DQS1 DDR_A_DQS#1 DDR_A_DQS0 DDR_A_DQS#0 (8) (8) (8) (8) (8) (8) (8) (8) (8) (8) (8) (8) (8) (8) (8) (8) (8) FOX_PZ63823-284S-41F Athlon 64 S1 Processor Socket +1.8V R228 +0.9VREF_CPU 1K_0402_1% CPU_VREF_REF C358 C363 A1 C345 1 2 C357 A26 C350 R222 2 1000P_0402_50V7K 0.1U_0402_16V4Z 1U_0402_6.3V4Z Athlon 64 S1g1 1K_0402_1% 1000P_0402_50V7K 1000P_0402_50V7K uPGA638 Top View VDD_VREF_SUS_CPU LAYOUT:PLACE CLOSE TO CPU AF1 Compal Secret Data Security Classification Issued Date 2006/08/18 Deciphered Date 2007/8/18 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C D Title AMD CPU DDRII MEMORY I/F Size Document Number Custom ICW50 / ICY70 Date: Rev 1.0 LA-3581P Friday, April 20, 2007 Sheet E of 42 ATHLON Control and Debug LAYOUT: ROUTE VDDA TRACE APPROX 50 mils WIDE (USE 2x25 mil TRACES TO EXIT BALL FIELD) AND 500 mils LONG R155 300_0402_5% +2.5VS FCM2012C-800_0805 22U_0805_6.3V6M C276 4.7U_0805_10V4Z D C271 0.22U_0603_16V7K C277 3300P_0402_50V7K R370 R371 +1.8V (15) CPU_SIC (15) CPU_SID R369 R368 1 +3VS CPU_HT_RESET# CPU_ALL_PWROK CPU_LDTSTOP# 300_0402_5% 300_0402_5% 2 CPU_SIC_R CPU_SID_R 0_0402_5% 0_0402_5% 2 R378 R376 +1.2V_HT +1.8V 1 44.2_0603_1% 44.2_0603_1% CPU_HTREF1 CPU_HTREF0 +1.8V A place them to CPU within 1" PAD PAD P B B7 A7 F10 RESET_L PWROK LDTSTOP_L SIC SID TP3 TP1 G Y R383 C5451 (10) CPUCLK CPU_ALL_PWROK 0_0402_5% @ HTREF1 HTREF0 F6 E6 VDD_FB_H VDD_FB_L CPU_PRESENT_L W9 Y9 NC7SZ08P5X_NL_SC70-5 @ R380 0_0402_5% C5441 (10) CPUCLK# CPU_CLKIN_SC_P CPU_CLKIN_SC_N 3900P_0402_50V7K R382 169_0402_1% A9 A8 R184 300_0402_5% G10 DBRDY CPU_TMS CPU_TCK CPU_TRST# CPU_TDI AA9 AC9 AD9 AF9 TMS TCK TRST_L TDI E9 E8 G9 H10 AA7 C2 D7 E7 F7 C7 AC8 TEST25_H TEST25_L TEST19 TEST18 TEST13 TEST9 TEST17 TEST16 TEST15 TEST14 TEST12 B A C3 AA6 W7 W8 Y6 AB6 TEST7 TEST6 THERMDC THERMDA TEST3 TEST2 P20 P19 N20 N19 RSVD0 RSVD1 RSVD2 RSVD3 U9 P 2 R189 CPU_LDTSTOP# 0_0402_5% @ NC7SZ08P5X_NL_SC70-5 @ R183 C G Y (10) HTCPU_STOP# 0_0402_5% CPU_THERMDC CPU_THERMDA +1.8V 10:10 R373 300_0402_5% MCP_PWRGD_R B Y A (10) HTCPU_RST# U25 P (15,18,27,28) MCP_PWRGD +1.8V G @ +1.8V R375 0_0402_5% R377 CPU_HT_RESET# 0_0402_5% @ NC7SZ08P5X_NL_SC70-5 @ R374 CPU_TEST26_BURNIN# CPU_PRESENT# CPU_TEST25_H_BYPASSCLK_H R199 R198 R188 300_0402_5% 1K_0402_5% 510_0402_5% CPU_TEST21_SCANEN CPU_TEST25_L_BYPASSCLK_L CPU_TEST19_PLLTEST0 CPU_TEST18_PLLTEST1 R197 R387 R385 R215 2 2 1 1 300_0402_5% 510_0402_5% 300_0402_5% 300_0402_5% R26 R25 P22 R22 0_0402_5% A5 C6 A6 A4 C5 B5 VID5 VID4 VID3 VID2 VID1 VID0 AC6 CPU_PRESENT# A3 PSI# R156 300_0402_5% VID5 VID4 VID3 VID2 VID1 VID0 D (41) (41) (41) (41) (41) (41) PSI# (41) CLKIN_H CLKIN_L CPU_DBRDY CPU_TEST25_H_BYPASSCLK_H CPU_TEST25_L_BYPASSCLK_L CPU_TEST19_PLLTEST0 CPU_TEST18_PLLTEST1 +1.8V PSI_L AF6 H_THERMTRIP_S# AC7 CPU_PROCHOT#_1.8 VDDIO_FB_H VDDIO_FB_L 3900P_0402_50V7K +1.8V VID5 VID4 VID3 VID2 VID1 VID0 P6 R6 U26 2 (10) HTCPU_PWRGD CPU_VCC_SENSE CPU_VSS_SENSE (41) CPU_VCC_SENSE (41) CPU_VSS_SENSE THERMTRIP_L PROCHOT_L AF4 AF5 5:10 R381 C543 0.1U_0402_16V4Z 4.7K_0402_5% @ R379 300_0402_5% VDDA2 VDDA1 DBREQ_L TDO TEST29_H TEST29_L MISC C266 F8 F9 +2.5VS_VDDA JP22D W=50mils L28 +1.8V E10 CPU_DBREQ# AE9 CPU_TDO C9 C8 CPU_TEST29_H_FBCLKOUT_P CPU_TEST29_L_FBCLKOUT_N 5:5:5 TEST24 TEST23 TEST22 TEST21 TEST20 AE7 AD7 AE8 AB8 CPU_TEST21_SCANEN AF7 TEST28_H TEST28_L TEST27 TEST26 TEST10 TEST8 J7 H8 AF8 AE6 CPU_TEST26_BURNIN# K8 C4 RSVD4 RSVD5 RSVD6 RSVD7 R384 80.6_0402_1% RSVD8 RSVD9 H16 B18 RSVD10 RSVD11 B3 C1 RSVD12 RSVD13 RSVD14 H6 G6 D5 RSVD15 RSVD16 RSVD17 RSVD18 RSVD19 RSVD20 R24 W18 R23 AA8 H18 H19 ROUTE AS 80 Ohm DIFFERENTIAL PAIR PLACE IT CLOSE TO CPU WITHIN 1" C FOX_PZ63823-284S-41F 1 +3V NOTE: HDT TERMINATION IS REQUIRED FOR REV Ax SILICON ONLY R116 10K_0402_5% 3V_LDT_RST# R113 220_0402_5% HT@ Q16 H_THERMTRIP_S# R535 0_0402_5% @ 1H_THERMTRIP# MMBT3904_SOT23 R115 B R117 @ 1K_0402_5% R127 1K_0402_5% 2 +3V +3VS 2 10 12 14 16 18 20 22 24 26 11 13 15 17 19 21 23 G R159 +3V Q15 MMBT3904_SOT23 @ MAINPWON (35,36,37) 0_0402_5% @ CPU_HT_RESET# H_THERMTRIP# (10) S 220_0402_5%HT@ R160 +1.8V R114 300_0402_5% JP7 D 220_0402_5%HT@ R161 +1.8V +1.8V 220_0402_5%HT@ R162 HDT Connector 220_0402_5% R163 CPU_DBREQ# CPU_DBRDY CPU_TCK CPU_TMS CPU_TDI CPU_TRST# CPU_TDO B 220_0402_5%HT@ HT@ AMD NPT S1 SOCKET Processor Socket +1.8V Q14 SAMTEC_ASP-68200-07 @ 2N7002_SOT23 HT@ +1.8V +3VS (27,28) EC_SMB_DA2 CPU_THERMDA D+ VDD1 CPU_THERMDC D- ALERT# THERM# GND EC_SMB_CK2 SCLK EC_SMB_DA2 SDATA Q19 (10) PROCHOT# R141 CPU_PROCHOT#_1.8 0_0402_5% @ MMBT3904_SOT23 C (27,28) EC_SMB_CK2 E U4 2200P_0402_50V7K A R186 @ 10K_0402_5% 0.1U_0402_16V4Z C269 B C275 R130 4.7K_0402_5% 2CPU_PH_G R133 10K_0402_5% +3VS 1 PVT Modify 2007/03/22 EC_THERM# (15,27,28) A Connect to MCP67 ADM1032ARM_RM8 Compal Secret Data Security Classification U2 CLOSE CPU, CPU_THERMDA&CPU_THERMDC PLACE CLOSE TO PROCESSOR WITHIN 1" INCH Issued Date 2006/08/18 Deciphered Date 2007/8/18 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title AMD CPU CTRL & DEBUG Size C Date: Document Number Rev 1.0 ICW50 / ICY70 LA-3581P Sheet Friday, April 20, 2007 of 42 +CPU_CORE 1 + C548 + C550 470U_D2E_2VM_R9 + C546 470U_D2E_2VM_R9 + C547 470U_D2E_2VM_R9 330U_D2E_2.5VM_R9 D D +CPU_CORE +CPU_CORE C287 10U_0805_10V6M 1 PROCESSOR POWER AND GROUND C288 10U_0805_10V6M 1 C289 10U_0805_10V6M 1 + 2 C279 10U_0805_10V6M 2 C280 10U_0805_10V6M 2 C282 10U_0805_10V6M C551 820U_E9_2.5V_M_R7 45@ 2 C281 10U_0805_10V6M JP22F VDD43 VDD44 VDD45 VDD46 VDD47 VDD48 VDD49 VDD50 VDD51 VDD52 VDD53 VDD54 V12 V14 W4 Y2 J15 K16 L15 M16 P16 T16 U15 V16 VDDIO1 VDDIO2 VDDIO3 VDDIO4 VDDIO5 VDDIO6 VDDIO7 VDDIO8 VDDIO9 VDDIO10 VDDIO11 VDDIO12 VDDIO13 VDDIO14 VDDIO15 VDDIO16 VDDIO17 VDDIO18 VDDIO19 VDDIO20 VDDIO21 VDDIO22 VDDIO23 VDDIO24 VDDIO25 VDDIO26 VDDIO27 H25 J17 K18 K21 K23 K25 L17 M18 M21 M23 M25 N17 P18 P21 P23 P25 R17 T18 T21 T23 T25 U17 V18 V21 V23 V25 Y25 +1.8V FOX_PZ63823-284S-41F Athlon 64 S1 Processor Socket B A1 A26 Athlon 64 S1g1 uPGA638 VSS1 VSS66 VSS2 VSS67 VSS3 VSS68 VSS4 VSS69 VSS5 VSS70 VSS6 VSS71 VSS7 VSS72 VSS8 VSS73 VSS9 VSS74 VSS10 VSS75 VSS11 VSS76 VSS12 VSS77 VSS13 VSS78 VSS14 VSS79 VSS15 VSS80 VSS16 VSS81 VSS17 VSS82 VSS18 VSS83 VSS19 VSS84 VSS20 VSS85 VSS21 VSS86 VSS22 VSS87 VSS23 VSS88 VSS24 VSS89 VSS25 VSS90 VSS26 VSS91 VSS27 VSS92 VSS28 VSS93 VSS29 VSS94 VSS30 VSS95 VSS31 VSS96 VSS32 VSS97 VSS33 VSS98 VSS34 VSS99 VSS35 VSS100 VSS36 VSS101 VSS37 VSS102 VSS38 VSS103 VSS39 VSS104 VSS40 VSS105 VSS41 VSS106 VSS42 VSS107 VSS43 VSS108 VSS44 VSS109 VSS45 VSS110 VSS46 VSS111 VSS47 VSS112 VSS48 VSS113 VSS49 VSS114 VSS50 VSS115 VSS51 VSS116 VSS52 VSS117 VSS53 VSS118 VSS54 VSS119 VSS55 VSS120 VSS56 VSS121 VSS57 VSS122 VSS58 VSS123 VSS59 VSS124 VSS60 VSS125 VSS61 VSS126 VSS62 VSS127 VSS63 VSS128 VSS64 VSS129 VSS65 FOX_PZ63823-284S-41F Ground AA4 AA11 AA13 AA15 AA17 AA19 AB2 AB7 AB9 AB23 AB25 AC11 AC13 AC15 AC17 AC19 AC21 AD6 AD8 AD25 AE11 AE13 AE15 AE17 AE19 AE21 AE23 B4 B6 B8 B9 B11 B13 B15 B17 B19 B21 B23 B25 D6 D8 D9 D11 D13 D15 D17 D19 D21 D23 D25 E4 F2 F11 F13 F15 F17 F19 F21 F23 F25 H7 H9 H21 H23 J4 +CPU_CORE Power C +CPU_CORE JP22E AC4 VDD1 AD2 VDD2 G4 VDD3 H2 VDD4 J9 VDD5 J11 VDD6 J13 VDD7 K6 VDD8 K10 VDD9 K12 VDD10 K14 VDD11 L4 VDD12 L7 VDD13 L9 VDD14 L11 VDD15 L13 VDD16 M2 VDD17 M6 VDD18 M8 VDD19 M10 VDD20 N7 VDD21 N9 VDD22 N11 VDD23 P8 VDD24 P10 VDD25 R4 VDD26 R7 VDD27 R9 VDD28 R11 VDD29 T2 VDD30 T6 VDD31 T8 VDD32 T10 VDD33 T12 VDD34 T14 VDD35 U7 VDD36 U9 VDD37 U11 VDD38 U13 VDD39 V6 VDD40 V8 VDD41 V10 VDD42 10/2 Modify J6 J8 J10 J12 J14 J16 J18 K2 K7 K9 K11 K13 K15 K17 L6 L8 L10 L12 L14 L16 L18 M7 M9 M11 M17 N4 N8 N10 N16 N18 P2 P7 P9 P11 P17 R8 R10 R16 R18 T7 T9 T11 T13 T15 T17 U4 U6 U8 U10 U12 U14 U16 U18 V2 V7 V9 V11 V13 V15 V17 W6 Y21 Y23 N6 CPU SOCKET S1 DECOUPLING +CPU_CORE C315 22U_0805_6.3V6M C326 22U_0805_6.3V6M C332 10U_0805_10V6M C333 22U_0805_6.3V6M C327 10U_0805_10V6M +CPU_CORE C318 0.22U_0402_10V4Z C328 10U_0805_10V6M C324 10U_0805_10V6M C316 10U_0805_10V6M C334 22U_0805_6.3V6M C +1.8V C308 0.22U_0402_10V4Z 1 C319 180P_0402_50V8J 2 C309 0.01U_0402_16V7K C353 10U_0805_10V6M C343 10U_0805_10V6M C361 0.22U_0402_10V4Z C356 0.22U_0402_10V4Z DECOUPLING BETWEEN PROCESSOR AND DIMMs PLACE CLOSE TO PROCESSOR AS POSSIBLE +1.8V C352 4.7U_0805_10V4Z C342 4.7U_0805_10V4Z C351 4.7U_0805_10V4Z C388 4.7U_0805_10V4Z C362 0.22U_0402_10V4Z C386 0.22U_0402_10V4Z C383 0.22U_0402_10V4Z B C381 0.22U_0402_10V4Z C385 0.01U_0402_16V7K C382 0.01U_0402_16V7K C340 C360 180P_0402_50V8J 2 180P_0402_50V8J Athlon 64 S1 Processor Socket Top View +0.9V AF1 2 C304 4.7U_0805_10V4Z C299 1000P_0402_50V7K C320 4.7U_0805_10V4Z 2 C303 4.7U_0805_10V4Z C300 1000P_0402_50V7K 2 C302 4.7U_0805_10V4Z C307 1000P_0402_50V7K 2 C313 0.22U_0402_10V4Z C306 1000P_0402_50V7K 2 C305 C312 0.22U_0402_10V4Z 180P_0402_50V8J 2 0.22U_0402_10V4Z C297 C314 180P_0402_50V8J 2 C296 C298 0.22U_0402_10V4Z 180P_0402_50V8J C295 180P_0402_50V8J A A Compal Secret Data Security Classification Issued Date 2006/08/18 Deciphered Date 2007/8/18 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title AMD CPU PWR & GND Size C Date: Document Number Rev 1.0 ICW50 / ICY70 LA-3581P Friday, April 20, 2007 Sheet of 42 +1.8V +1.8V +DIMM_VREF +1.8V C428 C579 +1.8V DDR_A_D2 DDR_A_D3 DDR_A_D8 DDR_A_D9 DDR_A_DQS#1 DDR_A_DQS1 4.7U_0805_10V4Z C417 C418 4.7U_0805_10V4Z C415 C416 4.7U_0805_10V4Z 2 2 1 C422 + 2 150U_D2_6.3VM C447 C448 C449 C450 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z C451 DDR_A_DQS#5 DDR_A_DQS5 DDR_A_D46 DDR_A_D47 DDR_A_D52 DDR_A_D53 47_0404_4P2R_5% 47_0404_4P2R_5% 47_0404_4P2R_5% 47_0404_4P2R_5% 47_0404_4P2R_5% 47_0404_4P2R_5% 47_0404_4P2R_5% 47_0402_1% 47_0402_1% DDR_A_MA14 DDR_A_MA15 47_0404_4P2R_5% DDR_A_MA7 DDR_CKE1_DIMMA 47_0404_4P2R_5% DDR_A_MA6 DDR_A_MA11 47_0404_4P2R_5% DDR_A_MA2 DDR_A_MA4 47_0404_4P2R_5% DDR_A_BS#1 DDR_A_MA0 47_0404_4P2R_5% DDR_CS0_DIMMA# DDR_A_RAS# 47_0404_4P2R_5% DDR_A_MA13 DDR_A_ODT0 47_0404_4P2R_5% RP15 RP16 RP17 RP20 RP18 RP19 RP21 B +1.8V 2 2 2 C444 C442 C441 0.1U_0402_16V4Z 0.1U_0402_16V4Z C440 DDR_A_DQS#7 DDR_A_DQS7 C446 DDR_A_D60 DDR_A_D61 0.1U_0402_16V4Z DDR_A_D54 DDR_A_D55 0.1U_0402_16V4Z DDR_A_CLK2 (5) DDR_A_CLK#2 (5) DDR_A_DM6 +0.9V A Layout Note: Place one 0.1uF cap close to every pullup resistors terminated to +0.9V DDR_A_D62 DDR_A_D63 Compal Secret Data Security Classification Issued Date DIMM1 REV H:5.2mm (BOT) 0.1U_0402_16V4Z DDR_CS3_DIMMA# (5) DDR_A_D44 DDR_A_D45 10K_0402_5% 10K_0402_5% 0.1U_0402_16V4Z RP10 RP11 DDR_A_MA9 DDR_A_MA8 RP12 DDR_A_MA5 DDR_A_MA3 RP13 DDR_A_MA1 DDR_A_MA10 RP14 DDR_A_BS#0 DDR_A_WE# RP9 DDR_A_CAS# DDR_CS1_DIMMA# RP8 DDR_A_ODT1 R277 DDR_CS3_DIMMA# R280 DDR_A_BS#2 DDR_A_MA12 DDR_A_D38 DDR_A_D39 1 C452 DDR_CKE0_DIMMA DDR_CS2_DIMMA# DDR_A_ODT0 (5) DDR_A_DM4 R281 R282 +0.9V DDR_A_BS#1 (5) DDR_A_RAS# (5) DDR_CS0_DIMMA# (5) DDR_A_D36 DDR_A_D37 DDR_A_CLK2 DDR_A_CLK#2 0.1U_0402_16V4Z DDR_CS3_DIMMA# C453 DDR_A_ODT0 DDR_A_MA13 FOX_AS0A426-M2RN-7F + C628 220U_D2_4VM_R15 Layout Note: Place one cap close to every pullup resistors terminated to +0.9V DDR_A_MA4 DDR_A_MA2 DDR_A_MA0 DDR_A_BS#1 DDR_A_RAS# DDR_CS0_DIMMA# 0.1U_0402_16V4Z DDR_A_MA11 DDR_A_MA7 DDR_A_MA6 C429 0.1U_0402_16V4Z C412 2 C445 0.1U_0402_16V4Z MEM_SMBDATA MEM_SMBCLK +3VS C439 (9,15) MEM_SMBDATA (9,15) MEM_SMBCLK DDR_A_MA15 DDR_A_MA14 0.1U_0402_16V4Z DDR_A_D58 DDR_A_D59 DDR_CKE1_DIMMA (5) C438 A DDR_CKE1_DIMMA 0.1U_0402_16V4Z DDR_A_DM7 DDR_A_D30 DDR_A_D31 C443 DDR_A_D56 DDR_A_D57 1 C 0.1U_0402_16V4Z DDR_A_D50 DDR_A_D51 +0.9V 0.1U_0402_16V4Z DDR_A_DQS#6 DDR_A_DQS6 4.7U_0805_10V4Z DDR_A_D48 DDR_A_D49 DDR_A_DQS#3 DDR_A_DQS3 C432 DDR_A_D42 DDR_A_D43 DDR_A_DQS#[0 7] C431 DDR_A_DM5 DDR_A_MA[0 15] 0.1U_0402_16V4Z DDR_A_D40 DDR_A_D41 C411 DDR_A_D34 DDR_A_D35 4.7U_0805_10V4Z DDR_A_DQS#4 DDR_A_DQS4 (5) DDR_A_DQS#[0 7] 0.1U_0402_16V4Z B 4.7U_0805_10V4Z DDR_A_D32 DDR_A_D33 DDR_A_D28 DDR_A_D29 C433 DDR_A_ODT1 (5) DDR_A_ODT1 DDR_A_DQS[0 7] (5) DDR_A_DQS[0 7] (5) DDR_A_MA[0 15] C434 DDR_A_CAS# DDR_CS1_DIMMA# 0.1U_0402_16V4Z (5) DDR_A_CAS# (5) DDR_CS1_DIMMA# C435 DDR_A_MA10 DDR_A_BS#0 DDR_A_WE# (5) DDR_A_BS#0 (5) DDR_A_WE# 0.1U_0402_16V4Z DDR_A_MA5 DDR_A_MA3 DDR_A_MA1 (5) DDR_A_DM[0 7] DDR_A_D22 DDR_A_D23 C436 DDR_A_MA12 DDR_A_MA9 DDR_A_MA8 0.1U_0402_16V4Z DDR_CS2_DIMMA# DDR_A_BS#2 DDR_A_DM[0 7] C437 (5) DDR_CS2_DIMMA# (5) DDR_A_BS#2 0.1U_0402_16V4Z (5) DDR_CKE0_DIMMA DDR_CKE0_DIMMA DDR_A_D[0 63] (5) DDR_A_D[0 63] 0.1U_0402_16V4Z DDR_A_D26 DDR_A_D27 +1.8V DDR_A_CLK1 (5) DDR_A_CLK#1 (5) C410 DDR_A_DM3 1K_0402_1% 4.7U_0805_10V4Z C DDR_A_DM2 D R274 DDR_A_D14 DDR_A_D15 DDR_A_D20 DDR_A_D21 C573 0.22U_0603_16V7K 2 2 2 2 2 2 2 C413 C398 C424 C426 C578 C576 C574 4.7U_0805_6.3V6K 4.7U_0805_6.3V6K 0.01U_0402_16V7K10P_0402_50V8K 0.22U_0603_16V7K0.22U_0603_16V7K0.22U_0603_16V7K C409 DDR_A_D24 DDR_A_D25 VSS DQ20 DQ21 VSS NC DM2 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DQS3# DQS3 VSS DQ30 DQ31 VSS NC/CKE1 VDD NC/A15 NC/A14 VDD A11 A7 A6 VDD A4 A2 A0 VDD BA1 RAS# S0# VDD ODT0 NC/A13 VDD NC VSS DQ36 DQ37 VSS DM4 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DQS5# DQS5 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS CK1 CK1# VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS7# DQS7 VSS DQ62 DQ63 VSS SAO SA1 DDR_A_CLK1 DDR_A_CLK#1 1K_0402_1% 4.7U_0805_10V4Z DDR_A_D18 DDR_A_D19 VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 NC VSS DQ26 DQ27 VSS CKE0 VDD NC BA2 VDD A12 A9 A8 VDD A5 A3 A1 VDD A10/AP BA0 WE# VDD CAS# NC/S1# VDD NC/ODT1 VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS NC,TEST VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SDA SCL VDDSPD DDR_A_DM1 C408 DDR_A_DQS#2 DDR_A_DQS2 DDR_A_D12 DDR_A_D13 4.7U_0805_10V4Z DDR_A_D16 DDR_A_D17 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 DDR_A_D6 DDR_A_D7 C407 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 DDR_A_DM0 4.7U_0805_10V4Z DDR_A_D10 DDR_A_D11 DDR_A_D4 DDR_A_D5 DDR_A_DQS#0 DDR_A_DQS0 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 VSS DQ4 DQ5 VSS DM0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 VSS CK0 CK0# VSS DQ14 DQ15 VSS 0.1U_0402_16V4Z D VREF VSS DQ0 DQ1 VSS DQS0# DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS DQ10 DQ11 VSS 4.7U_0805_10V4Z 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 C399 C414 C427 C425 C577 C575 4.7U_0805_6.3V6K 4.7U_0805_6.3V6K 0.01U_0402_16V7K10P_0402_50V8K 0.22U_0603_16V7K0.22U_0603_16V7K 1 1 1 1 1 1 R275 JP28 DDR_A_D0 DDR_A_D1 2006/08/18 2007/8/18 Deciphered Date Title DDR2 SO-DIMM I THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Size Document Number Custom ICW50 / ICY70 Date: Rev 1.0 LA-3581P Sheet Friday, April 20, 2007 of 42 +1.8V +1.8V DDR_B_D[0 63] (5) DDR_B_D[0 63] +DIMM_VREF +1.8V DDR_B_DM[0 7] (5) DDR_B_DM[0 7] DDR_B_D8 DDR_B_D9 2 C655 1000P_0402_50V7K D 1 + C629 220U_D2_4VM_R15 C631 C630 4.7U_0805_10V4Z C633 C632 4.7U_0805_10V4Z 4.7U_0805_10V4Z 2 2 2 C C461 C462 C463 C465 DDR_CS3_DIMMB# C464 C466 DDR_B_ODT0 DDR_B_MA13 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z DDR_CKE1_DIMMB (5) 0.1U_0402_16V4Z DDR_B_BS#1 DDR_B_RAS# DDR_CS0_DIMMB# Layout Note: Place one cap close to every pullup resistors terminated to +0.9V +0.9V DDR_CS2_DIMMB# DDR_CKE0_DIMMB DDR_B_BS#1 (5) DDR_B_RAS# (5) DDR_CS0_DIMMB# (5) DDR_B_MA12 DDR_B_BS#2 DDR_B_ODT0 (5) DDR_B_MA8 DDR_B_MA9 DDR_CS3_DIMMB# (5) DDR_B_MA3 DDR_B_MA5 DDR_B_D36 DDR_B_D37 DDR_B_DM4 DDR_B_MA10 DDR_B_MA1 DDR_B_D38 DDR_B_D39 DDR_B_WE# DDR_B_BS#0 DDR_B_D44 DDR_B_D45 DDR_CS0_DIMMB# DDR_B_RAS# DDR_B_DQS#5 DDR_B_DQS5 DDR_B_ODT1 DDR_CS3_DIMMB# RP22 RP23 RP24 RP25 RP26 RP27 RP29 R286 R287 47_0404_4P2R_5% 47_0404_4P2R_5% 47_0404_4P2R_5% 47_0404_4P2R_5% 47_0404_4P2R_5% 47_0404_4P2R_5% 47_0404_4P2R_5% 47_0402_1% 47_0402_1% DDR_CKE1_DIMMB DDR_B_MA15 47_0404_4P2R_5% DDR_B_MA14 DDR_B_MA11 47_0404_4P2R_5% DDR_B_MA7 DDR_B_MA6 47_0404_4P2R_5% DDR_B_MA4 DDR_B_MA2 47_0404_4P2R_5% DDR_B_MA0 DDR_B_BS#1 47_0404_4P2R_5% DDR_B_CAS# DDR_CS1_DIMMB# 47_0404_4P2R_5% DDR_B_ODT0 DDR_B_MA13 47_0404_4P2R_5% RP30 RP31 RP32 RP33 RP34 RP28 RP35 B DDR_B_D46 DDR_B_D47 DDR_B_D52 DDR_B_D53 +1.8V 1 2 2 2 C484 C485 C486 C477 C458 0.1U_0402_16V4Z 0.1U_0402_16V4Z Layout Note: Place one 0.1uF cap close to every pullup resistors terminated to +0.9V DDR_B_D62 DDR_B_D63 10K_0402_5% 10K_0402_5% +0.9V DDR_B_DQS#7 DDR_B_DQS7 R289 R288 C470 DDR_B_D60 DDR_B_D61 0.1U_0402_16V4Z DDR_B_D54 DDR_B_D55 0.1U_0402_16V4Z DDR_B_DM6 0.1U_0402_16V4Z C457 DDR_B_CLK2 (5) DDR_B_CLK#2 (5) 0.1U_0402_16V4Z C469 DDR_B_CLK2 DDR_B_CLK#2 Change PCB Footprint DDR_B_MA4 DDR_B_MA2 DDR_B_MA0 DIMM0 REV H:9.2mm (BOT) DDR_B_MA11 DDR_B_MA7 DDR_B_MA6 C456 0.1U_0402_16V4Z DDR_B_MA15 DDR_B_MA14 FOX_AS0A426-MARG-7F 0.1U_0402_16V4Z DDR_CKE1_DIMMB C471 +3VS DDR_B_D30 DDR_B_D31 0.1U_0402_16V4Z MEM_SMBDATA MEM_SMBCLK (8,15) MEM_SMBDATA (8,15) MEM_SMBCLK DDR_B_DQS#3 DDR_B_DQS3 C472 DDR_B_D58 DDR_B_D59 DDR_B_D28 DDR_B_D29 0.1U_0402_16V4Z DDR_B_DM7 A DDR_B_D22 DDR_B_D23 C476 DDR_B_D56 DDR_B_D57 +0.9V 0.1U_0402_16V4Z DDR_B_D50 DDR_B_D51 DDR_B_DM2 0.1U_0402_16V4Z DDR_B_DQS#6 DDR_B_DQS6 C626 DDR_B_D48 DDR_B_D49 4.7U_0805_10V4Z DDR_B_D42 DDR_B_D43 C478 DDR_B_DM5 4.7U_0805_10V4Z DDR_B_D40 DDR_B_D41 DDR_B_D20 DDR_B_D21 0.1U_0402_16V4Z DDR_B_D34 DDR_B_D35 C627 DDR_B_DQS#4 DDR_B_DQS4 4.7U_0805_10V4Z DDR_B_D32 DDR_B_D33 B C479 DDR_B_ODT1 (5) DDR_B_ODT1 C622 DDR_B_CAS# DDR_CS1_DIMMB# C480 (5) DDR_B_CAS# (5) DDR_CS1_DIMMB# 0.1U_0402_16V4Z DDR_B_MA10 DDR_B_BS#0 DDR_B_WE# (5) DDR_B_BS#0 (5) DDR_B_WE# 4.7U_0805_10V4Z DDR_B_MA5 DDR_B_MA3 DDR_B_MA1 C623 DDR_B_MA12 DDR_B_MA9 DDR_B_MA8 DDR_B_D14 DDR_B_D15 C481 DDR_CS2_DIMMB# DDR_B_BS#2 DDR_B_CLK1 (5) DDR_B_CLK#1 (5) 0.1U_0402_16V4Z (5) DDR_CS2_DIMMB# (5) DDR_B_BS#2 DDR_B_CLK1 DDR_B_CLK#1 C482 (5) DDR_CKE0_DIMMB DDR_CKE0_DIMMB DDR_B_DM1 C483 DDR_B_D26 DDR_B_D27 +1.8V 4.7U_0805_10V4Z DDR_B_DM3 DDR_B_D12 DDR_B_D13 0.1U_0402_16V4Z C C656 1000P_0402_50V7K C653 1000P_0402_50V7K C624 DDR_B_D24 DDR_B_D25 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 (5) DDR_B_DQS#[0 7] 0.1U_0402_16V4Z DDR_B_D18 DDR_B_D19 VSS DQ20 DQ21 VSS NC DM2 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DQS3# DQS3 VSS DQ30 DQ31 VSS NC/CKE1 VDD NC/A15 NC/A14 VDD A11 A7 A6 VDD A4 A2 A0 VDD BA1 RAS# S0# VDD ODT0 NC/A13 VDD NC VSS DQ36 DQ37 VSS DM4 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DQS5# DQS5 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS CK1 CK1# VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS7# DQS7 VSS DQ62 DQ63 VSS SAO SA1 DDR_B_DQS#[0 7] 4.7U_0805_10V4Z DDR_B_DQS#2 DDR_B_DQS2 VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 NC VSS DQ26 DQ27 VSS CKE0 VDD NC BA2 VDD A12 A9 A8 VDD A5 A3 A1 VDD A10/AP BA0 WE# VDD CAS# NC/S1# VDD NC/ODT1 VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS NC,TEST VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SDA SCL VDDSPD DDR_B_MA[0 15] (5) DDR_B_MA[0 15] 0.1U_0402_16V4Z 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 DDR_B_D16 DDR_B_D17 DDR_B_D6 DDR_B_D7 C625 DDR_B_D10 DDR_B_D11 DDR_B_DM0 4.7U_0805_10V4Z DDR_B_DQS#1 DDR_B_DQS1 DDR_B_D4 DDR_B_D5 (5) DDR_B_DQS[0 7] C459 DDR_B_D2 DDR_B_D3 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 C455 DDR_B_DQS#0 DDR_B_DQS0 VSS DQ4 DQ5 VSS DM0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 VSS CK0 CK0# VSS DQ14 DQ15 VSS 0.1U_0402_16V4Z DDR_B_D0 DDR_B_D1 D VREF VSS DQ0 DQ1 VSS DQS0# DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS DQ10 DQ11 VSS 4.7U_0805_10V4Z JP29 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 C654 1000P_0402_50V7K DDR_B_DQS[0 7] +3VS Compal Secret Data Security Classification Issued Date 2006/08/18 2007/8/18 Deciphered Date Title DDR2 SO-DIMM II THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A Size Document Number Custom ICW50 / ICY70 Date: Rev 1.0 LA-3581P Sheet Friday, April 20, 2007 of 42 U23A D (4) (4) (4) (4) (4) (4) (4) (4) (4) (4) (4) (4) (4) (4) (4) (4) H_CADOP0 H_CADON0 H_CADOP1 H_CADON1 H_CADOP2 H_CADON2 H_CADOP3 H_CADON3 H_CADOP4 H_CADON4 H_CADOP5 H_CADON5 H_CADOP6 H_CADON6 H_CADOP7 H_CADON7 (4) (4) (4) (4) (4) (4) (4) (4) (4) (4) (4) (4) (4) (4) (4) (4) H_CADOP8 H_CADON8 H_CADOP9 H_CADON9 H_CADOP10 H_CADON10 H_CADOP11 H_CADON11 H_CADOP12 H_CADON12 H_CADOP13 H_CADON13 H_CADOP14 H_CADON14 H_CADOP15 H_CADON15 (4) (4) (4) (4) H_CLKOP0 H_CLKON0 H_CLKOP1 H_CLKON1 MCP67 PART OF H_CADOP0 H_CADON0 H_CADOP1 H_CADON1 H_CADOP2 H_CADON2 H_CADOP3 H_CADON3 H_CADOP4 H_CADON4 H_CADOP5 H_CADON5 H_CADOP6 H_CADON6 H_CADOP7 H_CADON7 AF16 AG16 AH16 AJ16 AJ15 AK15 AK16 AL16 AG17 AF17 AL17 AK17 AL18 AK18 AJ19 AK19 HT_MCP_RXD0_P HT_MCP_RXD0_N HT_MCP_RXD1_P HT_MCP_RXD1_N HT_MCP_RXD2_P HT_MCP_RXD2_N HT_MCP_RXD3_P HT_MCP_RXD3_N HT_MCP_RXD4_P HT_MCP_RXD4_N HT_MCP_RXD5_P HT_MCP_RXD5_N HT_MCP_RXD6_P HT_MCP_RXD6_N HT_MCP_RXD7_P HT_MCP_RXD7_N H_CADOP8 H_CADON8 H_CADOP9 H_CADON9 H_CADOP10 H_CADON10 H_CADOP11 H_CADON11 H_CADOP12 H_CADON12 H_CADOP13 H_CADON13 H_CADOP14 H_CADON14 H_CADOP15 H_CADON15 AD14 AE14 AF14 AG14 AH14 AJ14 AL13 AK13 AC15 AD15 AD16 AE16 AE17 AD17 AB17 AC17 HT_MCP_RXD8_P HT_MCP_RXD8_N HT_MCP_RXD9_P HT_MCP_RXD9_N HT_MCP_RXD10_P HT_MCP_RXD10_N HT_MCP_RXD11_P HT_MCP_RXD11_N HT_MCP_RXD12_P HT_MCP_RXD12_N HT_MCP_RXD13_P HT_MCP_RXD13_N HT_MCP_RXD14_P HT_MCP_RXD14_N HT_MCP_RXD15_P HT_MCP_RXD15_N H_CLKOP0 H_CLKON0 H_CLKOP1 H_CLKON1 AJ17 AH17 AL14 AK14 HT_MCP_RX_CLK0_P HT_MCP_RX_CLK0_N HT_MCP_RX_CLK1_P HT_MCP_RX_CLK1_N H_CTLOP0 H_CTLON0 AH19 AG19 AC18 AD18 HT_MCP_RXCTL0_P HT_MCP_RXCTL0_N HT_MCP_RXCTL1_P/RESERVED HT_MCP_RXCTL1_N/RESERVED AC13 AB13 THERMTRIP#/GPIO_58 PROCHOT#/GPIO_20 +3.3V_PLL_CPU AB16 +3.3V_PLL_CPU +1.2V_PLL_CPU_HT AB15 +1.2V_PLL_CPU_HT HT_MCP_TXD0_P HT_MCP_TXD0_N HT_MCP_TXD1_P HT_MCP_TXD1_N HT_MCP_TXD2_P HT_MCP_TXD2_N HT_MCP_TXD3_P HT_MCP_TXD3_N HT_MCP_TXD4_P HT_MCP_TXD4_N HT_MCP_TXD5_P HT_MCP_TXD5_N HT_MCP_TXD6_P HT_MCP_TXD6_N HT_MCP_TXD7_P HT_MCP_TXD7_N AK27 AJ27 AK26 AL26 AK25 AL25 AL24 AK24 AK22 AL22 AK21 AL21 AH21 AJ21 AL20 AM20 H_CADIP0 H_CADIN0 H_CADIP1 H_CADIN1 H_CADIP2 H_CADIN2 H_CADIP3 H_CADIN3 H_CADIP4 H_CADIN4 H_CADIP5 H_CADIN5 H_CADIP6 H_CADIN6 H_CADIP7 H_CADIN7 HT_MCP_TXD8_P HT_MCP_TXD8_N HT_MCP_TXD9_P HT_MCP_TXD9_N HT_MCP_TXD10_P HT_MCP_TXD10_N HT_MCP_TXD11_P HT_MCP_TXD11_N HT_MCP_TXD12_P HT_MCP_TXD12_N HT_MCP_TXD13_P HT_MCP_TXD13_N HT_MCP_TXD14_P HT_MCP_TXD14_N HT_MCP_TXD15_P HT_MCP_TXD15_N AG27 AH27 AF25 AG25 AH25 AJ25 AE23 AF23 AD21 AE21 AF21 AG21 AC20 AD20 AE19 AF19 H_CADIP8 H_CADIN8 H_CADIP9 H_CADIN9 H_CADIP10 H_CADIN10 H_CADIP11 H_CADIN11 H_CADIP12 H_CADIN12 H_CADIP13 H_CADIN13 H_CADIP14 H_CADIN14 H_CADIP15 H_CADIN15 HT_MCP_TX_CLK0_P HT_MCP_TX_CLK0_N HT_MCP_TX_CLK1_P HT_MCP_TX_CLK1_N AK23 AJ23 AG23 AH23 H_CLKIP0 H_CLKIN0 H_CLKIP1 H_CLKIN1 HT_MCP_TXCTL0_P HT_MCP_TXCTL0_N RESERVED/HT_MCP_TXCTL1_P RESERVED/HT_MCP_TXCTL1_N AK20 AJ20 AD19 AC19 H_CTLIP0 H_CTLIN0 HT_MCP_REQ# HT_MCP_STOP# HT_MCP_RST# HT_MCP_PWRGD AD23 AB20 AC21 AD22 CLKOUT_200MHZ_P CLKOUT_200MHZ_N AL28 AM28 CLKOUT_25MHZ AK28 HT H_CADIP0 H_CADIN0 H_CADIP1 H_CADIN1 H_CADIP2 H_CADIN2 H_CADIP3 H_CADIN3 H_CADIP4 H_CADIN4 H_CADIP5 H_CADIN5 H_CADIP6 H_CADIN6 H_CADIP7 H_CADIN7 (4) (4) (4) (4) (4) (4) (4) (4) (4) (4) (4) (4) (4) (4) (4) (4) H_CADIP8 H_CADIN8 H_CADIP9 H_CADIN9 H_CADIP10 H_CADIN10 H_CADIP11 H_CADIN11 H_CADIP12 H_CADIN12 H_CADIP13 H_CADIN13 H_CADIP14 H_CADIN14 H_CADIP15 H_CADIN15 (4) (4) (4) (4) (4) (4) (4) (4) (4) (4) (4) (4) (4) (4) (4) (4) H_CLKIP0 H_CLKIN0 H_CLKIP1 H_CLKIN1 (4) (4) (4) (4) D C C (6) H_THERMTRIP# (6) PROCHOT# +3VS L7 MBK1608121YZF_0603 C46 4.7U_0805_10V4Z C43 0.1U_0402_16V4Z HTCPU_REQ# HTCPU_STOP# HTCPU_RST# HTCPU_PWRGD CPUCLK (6) CPUCLK# (6) R366 HT_MCP_COMP_VDD AL12 150_0402_1% HT_MCP_COMP_GND CPU_SBVREF AG28 CLK200_TERM_GND AJ28 TP4 MCP67-MV_PBGA836 PAD B R123 2.37K_0402_1% L13 MBK1608121YZF_0603 C141 10U_0805_10V4Z C101 1 0.1U_0402_16V4Z AM12 150_0402_1% B +1.2V_HT +1.2V_HT R364 R164 22K_0402_5% HTCPU_STOP# (6) HTCPU_RST# (6) HTCPU_PWRGD (6) +1.2V_HT H_CTLIP0 (4) H_CTLIN0 (4) +3VS (4) H_CTLOP0 (4) H_CTLON0 9/25 Modify TO +3VS 2 C136 0.1U_0402_16V4Z A A Compal Secret Data Security Classification 2006/08/18 Issued Date 2007/8/18 Deciphered Date Title MCP67 HT LINK THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Size Document Number Custom ICW50 / ICY70 Date: Rev 1.0 LA-3581P Sheet Friday, April 20, 2007 10 of 42 +3VALW KSI[0 7] (27,29,30) +EC_VCCA (27) EC_SMB_DA2 EC_SMB_CK2 EC_SMB_DA1 EC_SMB_CK1 (15,27) PM_SLP_S3# (15,27) PM_SLP_S5# (15,27) EC_SMI# (27,30,33) LID_SW# (23,26,27,34,38) SUSP# (15,27) PBTN_OUT# (13,27) EC_PME# KSI0/GPIO30 KSI1/GPIO31 KSI0/GPIO32 KSI3/GPIO33 KSI4/GPIO34 KSI5/GPIO35 KSI6/GPIO36 KSI7/GPIO37 KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 KSO16 KSO17 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 89 90 KSO0/GPIO20 KSO1/GPIO21 KSO2/GPIO22 KSO3/GPIO23 KSO4/GPIO24 KSO5/GPIO25 KSO6/GPIO26 KSO7/GPIO27 KSO8/GPIO28 KSO9/GPIO29 KSO10/GPIO2A KSO11/GPIO2B KSO12/GPIO2C KSO13/GPIO2D KSO14/GPIO2E KSO15/GPIO2F KSO16/GPIO48 KSO17/GPIO49 E51TXD_P80DATA E51RXD_P80CLK NUM_LED# BATT_GRN_LED# CAPS_LED# BATT_AMB_LED# PWR_LED SYSON 0_0402_5% PM_SLP_S3# PM_SLP_S5# EC_SMI# LID_SW# SUSP# PBTN_OUT# EC_PME# EC_CRY2 EC_CRY1 (27) EC_CRY2 (27) EC_CRY1 88 87 86 85 34 35 40 99 100 101 102 104 16 17 18 19 20 21 22 23 138 139 75 DA0/GPO3C DA1/GPO3D DA2/GPO3E DA3/GPO3F DA output or GPO 76 78 79 80 DAC_BRIG EN_DFAN1 IREF PWM1/GPIO0F PWM2/GPIO10 PWM3/GPIO11 PWM4/GPIO19 FANPWM1/GPIO12 FANPWM2/GPIO13 FANFB1/GPIO14 FANFB2/GPIO15 25 27 29 38 30 31 32 33 INVT_PWM BEEP# PSCLK1/GPIO4A PSDAT1/GPIO4B PSCLK2/GPIO4C PSDAT2/GPIO4D PSCLK3/GPIO4E PSDAT3/GPIO4F 91 92 93 94 95 96 EC_MUTE USB_EN# WL_LED# BT_LED# TP_CLK TP_DATA ADB0/GPXID0/SDIDI ADB1/GPXID1 ADB2/GPXID2 ADB3/GPXID3 ADB4/GPXID4 ADB5/GPXID5 ADB6/GPXID6 ADB7/GPXID7 KBA0/GPXOA00/SDICS# KBA1/GPXOA01/SDICLK KBA2/GPXOA02/SDIDO KBA3/GPXOA03 KBA4/GPXOA04 KBA5/GPXOA05 KBA6/GPXOA06 KBA7/GPXOA07 KBA8/GPXOA08 KBA9/GPXOA09 KBA10/GPXOA10 KBA11/GPXOA11 KBA12/GPXOA12 KBA13/GPXOA13 KBA14/GPXOA14 KBA15/GPXOA15 KBA16/GPXOA16 KBA17/GPXOA17 KBA18/GPXOA18 KBA19/GPIO51/A19 125 126 128 130 131 132 133 134 111 112 113 114 115 116 117 118 119 120 121 122 123 124 110 109 108 107 106 98 ADB0 @ R250 ADB1 @ R439 ADB2 @ R257 ADB3 @ R251 ADB4 @ R258 ADB5 @ R252 ADB6 @ R259 ADB7 @ R253 KBA0 @ R244 KBA1 @ R260 KBA2 @ R256 KBA3 @ R448 KBA4 @ R261 KBA5 @ R246 KBA6 @ R262 KBA7 KBA8 @ R248 KBA9 @ R254 KBA10 @ R249 KBA11 @ R255 KBA12 KBA13 KBA14 KBA15 KBA16 KBA17 KBA18 MXM_THERM# GPIO58/SPICLK RD#/SPIDI WR#/SPIDO SPICS# 142 135 136 144 EC_SI_SPI_SO/FRD# EC_SO_SPI_SI/FWR# EC_SPICS#/FSEL# GPIO18 GPIO1B GPIO1C GPIO1E GPIO1F GPIO42 SELIO2#/GPIO43 SELIO#/GPIO50 XCLK32K/GPIO57 GPIO59 36 41 43 45 46 83 84 97 137 143 ON/OFF @ R433 @ R440 81 82 EC_RCIRRX FAN/PWM ps2 interface key Matrix scan Data BUS Address BUS SM BUS GPIO16/E51TXD GPIO17/E51CLK/E51RXD GPIO1A/NUMLED# GPIO52/E51CS# GPIO53/CAPSLED# GPIO54 GPIO55/SCORLED# GPIO56 GPIO02 GPIO03 GPIO04 GPIO06 GPIO07 GPIO08 GPIO09 GPIO0A GPIO0B/ESB_CLK GPIO0C/ESB_DAT GPIO0D XCLKI XCLKO V18R 129 103 13 28 39 140 SDA2/GPIO47 SCL2/GPIO46 SDA1/GPIO45 SCL1/GPIO44 BATT_TEMP BATT_OVP AGND R245 63 64 65 66 67 68 69 70 71 72 73 74 Host INTERFACE 77 @ (15,27) EC_RSMRST# KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 EC_SMB_DA2 EC_SMB_CK2 EC_SMB_DA1 EC_SMB_CK1 (25,27) E51TXD_P80DATA (25,27) E51RXD_P80CLK (27,30) NUM_LED# (27,30,33) BATT_GRN_LED# (27,30) CAPS_LED# (27,30,33) BATT_AMB_LED# (27,30) PWR_LED (26,27,34,40) SYSON B EC_SCI# AD0/GPI38 AD1/GPI39 AD2/GPI3A AD3/GPI3B AD INtput or GPI PWR GND GND GND GND GND C LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0 GA20/ GPIO00 KBRST#/GPIO01 SERIRQ LFRAME# LAD3 LAD2 LAD1 LAD0 PCICLK PCIRST#/GPIO05 ECRST# SCI#/GPIO0E CLKRUN#/GPIO1D VCC VCC VCC VCC VCC VCC U16 10 12 14 15 42 24 44 AVCC 11 26 37 105 127 141 KSO[0 17] (27,29,30) (15,27) EC_GA20 (15,27) EC_KBRST# (13,23,27) SERIRQ (13,14,27) LPC_FRAME# (13,27) LPC_AD3 (13,27) LPC_AD2 (13,27) LPC_AD1 (13,27) LPC_AD0 (13,27) CLK_PCI_LPC (13,27) PLT_RST# (27) EC_RST# (15,27) EC_SCI# (13,23,27) PM_CLKRUN# (6,27) (6,27) (18,27,29,37) (18,27,29,37) ADB[0 7] ADB[0 7] KSO[0 17] D KBA[0 19] KBA[0 19] KSI[0 7] CIR_RX/GPIO40 CIR_RLC_TX/GPIO41 AD_BID0 BATT_TEMP (27,37) BATT_OVP (27,38) ADP_I (27,38) AD_BID0 (27) DAC_BRIG (20,27) EN_DFAN1 (4,27) IREF (27,38) CHGSEL (27,38) INVT_PWM (20,27) BEEP# (27,32) EC_THERM# (6,15,27) PWR_SUSP_LED (27,30) ENCODER_DIR (27,33) ACOFF (27,35,38) FAN_SPEED1 (4,27) BT_ON# (27,30) PWR_SUSP_LED FAN_SPEED1 BT_ON# FSTCHG MCP_PWRGD D EC_MUTE (27,33) USB_EN# (25,26,27) WL_LED# (27,30) BT_LED# (27,30) TP_CLK (27,29) TP_DATA (27,29) 2 2 2 2 2 2 2 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 2 2 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% TV_THERM# (25,27) SKU_ID (27) ENBKL (12,18,27) IDE_LED# (21,27) SATA_LED# (14,27) 5IN1_LED# (23,27) EAPD (27,32) ARCADE# (27,30) 3S/4S# (27,38) 65W/90W# (27,38) SBPWR_EN (22,27,34,40) EC_RSMRST# (15,27) EC_LID_OUT# (15,27) EC_ON (27,31) EC_SWI# (15,27) SKU_ID ENBKL IDE_LED# SATA_LED# EAPD SBPWR_EN EC_LID_OUT# EC_ON BKOFF# WL_OFF# MEDIA_LED# C BKOFF# (20,27) WL_OFF# (25,27) MEDIA_LED# (27,30) CALIBRATE (27,38) MXM_THERM# (18,27) EC_SPICLK (27,29) EC_SI_SPI_SO/FRD# (27,29) EC_SO_SPI_SI/FWR# (27,29) EC_SPICS#/FSEL# (27,29) B ON/OFF (27,31) 0_0402_5% EC_ON 0_0402_5% SBPWR_EN EC_ON (27,31) SBPWR_EN (22,27,34,40) DPST_PWM (12,20,27) POUT (27,41) FSTCHG (27,38) MCP_PWRGD (6,15,18,27) ACIN (15,18,27,37) EC_RCIRRX (27) ENCODER_PULSE (27,33) KB925QFA0_LQFP144_22x22 @ 20mil ECAGND ECAGND (27) A A Compal Electronics, Inc Compal Secret Data Security Classification 2006/08/18 Issued Date Deciphered Date 2007/8/18 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title EC ENE KB910L/925(Reserved) Size B Date: Document Number Rev 1.0 ICW50 / ICY70 LA-3581P Friday, April 20, 2007 Sheet 28 of 42 +5VALW 0.1U_0402_16V4Z R182 100K_0402_5% A0 A1 A2 GND JP6 +5VS (27,28) TP_DATA (27,28) TP_CLK AT24C16AN-10SI-2.7_SO8 TP_DATA TP_CLK TP_DATA TP_CLK VCC WP SCL SDA @ U8 C259 (18,27,28,37) EC_SMB_CK1 (18,27,28,37) EC_SMB_DA1 To TP/B Conn +5VALW ACES_85201-0605 R196 100K_0402_5% D3 @ PSOT24C_SOT23 +5VS TP_DATA C208 @ 100P_0402_50V8J TP_CLK @ 100P_0402_50V8J C207 1 Update Footprint C209 Update Footprint 0.1U_0402_16V4Z 9/25 Added for EMI +3VALW C258 0.1U_0402_16V4Z CE# WP# HOLD# VSS VDD SCK SI SO R166 R167 R208 0_0402_5% 0_0402_5% 0_0402_5% EC_SPICLK (27,28) EC_SO_SPI_SI/FWR# (27,28) EC_SI_SPI_SO/FRD# (27,28) (Left) KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 KSO16 KSO17 KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 PVT Net Name Modify 2007/3/12 U37 CE# WP# HOLD# VSS VDD SCK SI SO KSI[0 7] (27,28,30) KSO[0 17] KSO[0 17] (27,28,30) JP5 MX25L8005M2C-15G_SOP8 +3VALW (27,28) EC_SPICS#/FSEL# KSI[0 7] INT_KBD Conn U10 (27,28) EC_SPICS#/FSEL# EC_SPICLK (27,28) EC_SO_SPI_SI/FWR# (27,28) EC_SI_SPI_SO/FRD# (27,28) MX25L8005M2C-15G_SOP8 @ 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 (Right) 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 G2 G1 28 27 ACES_85201-26051 C91 100P_0402_50V8J KSO7 C83 100P_0402_50V8J KSO14 C90 100P_0402_50V8J KSO6 C82 100P_0402_50V8J KSO13 C89 100P_0402_50V8J KSO5 C81 100P_0402_50V8J KSO12 C88 100P_0402_50V8J KSO4 C80 100P_0402_50V8J KSI0 C92 100P_0402_50V8J KSO3 C79 100P_0402_50V8J KSO11 C87 100P_0402_50V8J KSI4 C96 100P_0402_50V8J KSO10 C86 100P_0402_50V8J KSO2 C78 100P_0402_50V8J KSI1 C93 100P_0402_50V8J KSO1 C77 100P_0402_50V8J KSI2 C94 100P_0402_50V8J KSO0 C76 100P_0402_50V8J KSO9 C85 100P_0402_50V8J KSI5 C97 100P_0402_50V8J KSI3 C95 100P_0402_50V8J KSI6 C98 100P_0402_50V8J KSO8 C84 100P_0402_50V8J KSI7 C99 100P_0402_50V8J Compal Electronics, Inc Compal Secret Data Security Classification Issued Date KSO15 2006/08/18 Deciphered Date 2007/8/18 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title BIOS, I/O Port & K/B Connector Size B Date: Document Number Rev 1.0 ICW50 / ICY70 LA-3581P Monday, April 23, 2007 Sheet 29 of 42 +3VS +5VS +5VALW PVT2 Modify 2007/4/10 JP2 BT_BTN# KSI3 EMAIL_BTN# KSI4 IE_BTN# KSI5 E-KEY_BTN# 17 18 Check 15.4" K/B Matrix G17 G18 +5VS C28 1U_0402_6.3V4Z PWR_LED# WL_R_LED# BT_LED# PWR_SUSP_LED# KSO0 KSI1 KSI2 KSI3 KSI4 +3V MDC Conn ON/OFFBTN# (31) BT_LED# (27,28) KSO0 (27,28,29) KSI1 (27,28,29) KSI2 (27,28,29) KSI3 (27,28,29) KSI4 (27,28,29) +5VALW ACES_85201-16051 HDA_SDOUT_MDC (14) HDA_SDOUT_MDC (14) HDA_SYNC_MDC (14) HDA_SDIN1 (14) HDA_RST_MDC# C657 100P_0402_50V8J R112 33_0402_5% 11 +3VALW 100K_0402_5% D17 ARCADE_BTN# ARCADE# (27,28) 51ON# 51ON# (31,35) DAN202UT106_SC70-3 +3VALW R111 0_0402_5% @ C27 1U_0402_6.3V4Z KSO0 (27,28,29) KSI5 (27,28,29) LID_SW# (27,28,33) +3VALW +5VS 13 14 15 16 17 18 ARCADE_BTN# KSO0 KSI5 2 0_0402_5% C154 1U_0603_10V4Z +3V HDA_BITCLK_MDC (14) R538 0_0402_5% ACES_88018-124G C155 Connector for MDC Rev1.5 R317 MEDIA_LED# (27,28) CAPS_LED# (27,28) NUM_LED# (27,28) R467 10 12 GND1 RES0 IAC_SDATA_OUT RES1 GND2 3.3V IAC_SYNC GND3 IAC_SDATA_IN GND4 IAC_RESET# IAC_BITCLK HDA_SDOUT_MDC JP36 12 11 10 1 20mil JP17 KSI2 10 11 12 13 14 15 16 WL_BTN# GND GND GND GND GND GND KSO0 KSI1 10 11 12 13 14 15 16 22P_0402_50V8J C137 10P_0402_50V8J @ 2 ACES_85201-1205 Update Footprint PWR_LED# C663 @ 100P_0402_50V8J ON/OFFBTN# C664 @ 100P_0402_50V8J LID_SW# C665 100P_0402_50V8J WL_R_LED# C666 @ 100P_0402_50V8J KSI5 C667 100P_0402_50V8J BT_LED# C668 @ 100P_0402_50V8J PWR_SUSP_LED#C669 @ 100P_0402_50V8J ARCADE_BTN# C670 100P_0402_50V8J NUM_LED# C672 100P_0402_50V8J @ 100P_0402_50V8J CAPS_LED# C674 100P_0402_50V8J C675 @ 100P_0402_50V8J MEDIA_LED# C676 100P_0402_50V8J C677 @ 100P_0402_50V8J C678 @ 100P_0402_50V8J KSO0 C671 KSI1 C673 KSI2 KSI3 WL_LED# (27,28) @ MINI1_LED# MINI1_LED# (25) 0_0402_5% Bluetooth Conn +3VALW +3VS +BT_VCC R295 100K_0402_5% @ C473 BT@ 0.1U_0402_16V4Z KSI4 100P_0402_50V8J WL_LED# 0_0402_5% R292 G (27,28) BT_ON# 2 10K_0402_5% PWR_SUSP_LED# PWR_LED# BT@ D R520 R521 WL_R_LED# S EMI PVT Modify 2007/3/12 C474 JP12 C475 BT@ 1U_0603_10V4Z Q37 AO3413_SOT23-3 BT@ G S Q47 2N7002_SOT23 10 ACES_87213-0800G BT@ R296 300_0603_5% BT@ L37 USB20_N5 USB20_P5 3 USB20_N5_R 2 USB20_P5_R (27,28) PWR_LED GND GND 1 C487 BT@ BT@ 4.7U_0805_10V4Z 0.1U_0402_16V4Z S Q40 2N7002_SOT23 1 G (27,28) PWR_SUSP_LED (25) WLAN_BT_DATA (25) WLAN_BT_CLK +BT_VCC C489 D (14) USB20_P5 (14) USB20_N5 BT@ USB20_P5_R USB20_N5_R BT@ W=40mils BT@ 0.1U_0402_16V4Z D 0_0402_5% R290 R291 0_0402_5% D G S Q38 2N7002_SOT23 BT@ WCM2012F2S-900T04_0805 @ 9/25 Added for EMI PWR_LED# PWR_LED# (33) A PWR_SUSP_LED# PWR_SUSP_LED# (33) HT-297DQ/GQ_AMB/YG_0603 D S G Q52 2N7002_SOT23 @ LED2 BATT_GRN_LED# BATT_GRN_LED# (27,28,33) A +5VALW R294 300_0402_5% R435 453_0402_1% YG +5VALW +BT_VCC @ R522 10K_0402_5% BT_LED# (27,28) +5VALW LED1 YG +5VS R293 300_0402_5% R436 453_0402_1% 2 BATT_AMB_LED# BATT_AMB_LED# (27,28,33) PVT Modify 2007/3/12 HT-297DQ/GQ_AMB/YG_0603 PVT Value Modify to 453E 2007/3/12 Compal Footprint Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2006/08/18 Deciphered Date 2007/8/18 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title MDC / BT / CIR / LED Size B Date: Document Number Rev 1.0 ICW50 / ICY70 LA-3581P Friday, April 20, 2007 Sheet 30 of 42 TOP Side +3VALW @ 10K_0603_5% @ 10K_0603_5% Power Button R533 R534 R213 Bottom Side 100K_0402_5% D7 ON/OFFBTN# (30) ON/OFFBTN# ON/OFF (27,28) 51ON# 51ON# (30,35) DAN202UT106_SC70-3 Update Footprint 2 G R195 10K_0402_5% S C325 1000P_0402_50V7K D8 RLZ20A_LL34 EC_ON (27,28) EC_ON D 2N7002_SOT23 Q24 Power ON Circuit +5VALW +3V +1.8V +5VALW +3V 2 C70 0.1U_0402_16V4Z 2 Q36 MMBT3904_SOT23 MEM_VLD D Q35 BSS138_SOT23 G S HT_VLD (11,15) R278 47K_0402_5% D R279 47K_0402_5% R276 47K_0402_5% C430 0.1U_0402_16V4Z Q12 MMBT3904_SOT23 HT_VLD Q11 BSS138_SOT23 G R107 47K_0402_5% R105 47K_0402_5% C69 0.1U_0402_16V4Z R98 47K_0402_5% 1 1 +1.2V_HT S MEM_VLD (15,40) C454 0.1U_0402_16V4Z NEAR PU10 Compal Secret Data Security Classification Issued Date 2006/08/18 Deciphered Date 2007/8/18 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title PWR_OK CIRCUIT/ BTN Size Document Number Custom ICW50 / ICY70 Date: Rev 1.0 LA-3581P Friday, April 20, 2007 Sheet 31 of 42 C D E F G 28.7K for Module Design (VDDA = 4.702) +VDDA +5VAMP 1 C612 1U_0603_10V4Z U29 L45 KC FBM-L11-201209-221LMAT_0805 VIN 1 L46 C605 C602 KC FBM-L11-201209-221LMAT_0805 10U_0805_10V4Z 2 0.1U_0402_16V4Z DELAY ERROR SD R434 C E R431 D23 RB751V_SOD323 R432 10K_0402_5% HD Audio Codec C594 LINE_L (33) LINE_L C583 LINE_R (33) LINE_R C582 MIC1_L (33) MIC1_L C587 MIC1_R (33) MIC1_R C584 2 2 2 (33) HP_PLUG# R415 5.1K_0402_1% (33) LINEIN_PLUG# (33) MIC_PLUG# R419 R413 2 10K_0402_1% 20K_0402_1% (27,28) EAPD (33) SPDIF EAPD 2SPDIF_R FBM-L11-160808-800LMT_0603 L53 Codec Signals PORT-A (PIN 39, 41) 20K PORT-B (PIN 21, 22) 10K PORT-C (PIN 23, 24) 5.1K PORT-D (PIN 35, 36) 39.2K PORT-E (PIN 14, 15) 20K PORT-F (PIN 16, 17) 10K PORT-G (PIN 43, 44) 5.1K PORT-H (PIN 45, 46) DVDD 25 38 AVDD2 LINE_OUT_L 35 HP_LEFT LINE_OUT_R 36 HP_RIGHT MIC2_L HP_OUT_L 39 AMP_LEFT MIC2_R HP_OUT_R 41 AMP_RIGHT LINE1_L NC 45 LINE1_R DMIC_CLK 46 CD_L NC 43 20 CD_R NC 44 19 CD_GND SENSE_A NC 10 BIT_CLK SDATA_IN R424 MIC1_R 10U_0805_10V4Z HP_LEFT (33) HP_RIGHT (33) AMP_LEFT (33) AMP_RIGHT (33) C608 0_0402_5% 1 22P_0402_50V8J HDA_BITCLK_AUDIO PCBEEP MONO_OUT 29 GPIO1 31 MIC1_VREFO_L 28 SYNC SDATA_OUT GPIO0 GPIO3 SENSE A SENSE B 47 EAPD 48 SPDIFO 33_0402_5% 37 LINE1_VREFO RESET# R421 (14) MIC1_VREFO_R 32 MIC2_VREFO 30 VREF 27 JDREF 40 DVSS1 DVSS2 DGND +3VS 10mil MIC1_VREFO_L MIC1_VREFO_R 10mil NC 33 AVSS1 AVSS2 26 42 C585 10U_0805_10V4Z R409 20K_0402_1% AGND 1000P_0402_50V7K C688 1000P_0402_50V7K C689 1000P_0402_50V7K C690 1000P_0402_50V7K R404 0_0805_5% R406 0_0805_5% R405 Issued Date C D 0_0805_5% GND E GNDA Compal Electronics, Inc Compal Secret Data 2006/08/18 2007/8/18 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC B C687 +5VS MIC2_VREFO CODEC_VREF Security Classification A EMI Added 2007/4/12 HDA_SDIN0 (14) WOOFER_MONO (33) ALC268-GR_LQFP48_9X9 C387 22P_0402_50V8J +3VS C610 MIC1_L 13 34 C609 L47 MBK1608301YZF_0603 0.1U_0402_16V4Z NC 11 (14) HDA_SDOUT_AUDIO 15 MIC1_C_L 21 4.7U_0805_6.3V6K MIC1_C_R 22 4.7U_0805_6.3V6K MONO_IN 12 (14) HDA_SYNC_AUDIO C607 14 MIC2_C_L 16 4.7U_0805_6.3V6K MIC2_C_R 17 4.7U_0805_6.3V6K LINE_C_L 23 4.7U_0805_6.3V6K LINE_C_R 24 4.7U_0805_6.3V6K 18 (14) HDA_RST_AUDIO# U30 +3VS_DVDD 0.1U_0402_16V4Z (33) INT_MIC_R 39.2K 20mil 40mil 0.1U_0402_16V4Z L44 FBM-L11-160808-800LMT_0603 1 C590 C586 C589 10U_0805_10V4Z 2 0.1U_0402_16V4Z C597 SENSE B R407 10K_0402_1% PVT Modify 2007/3/12 1U_0603_10V4Z R427 2SC2411K_SOT23 2.4K_0402_5% AVDD1 SENSE A C588 10U_0805_10V4Z 47K_0402_5% +VDDA Impedance C601 MONO_IN +AVDD_AC97 Sense Pin R518 0.1U_0402_16V4Z C611 DVDD_IO 560_0402_5% C617 1U_0603_10V4Z (15) MCP_SPKR GND 4.85V 47K_0402_5% CNOISE +VDDA R408 30K_0402_1% 2 Q42 B 560_0402_5% R517 SENSE or ADJ 40mil 2 C634 1U_0603_10V4Z SI9182DH-AD_MSOP8 R428 10K_0402_5% (27,28) BEEP# VOUT +5VS (output = 250 mA) 60mil R418 10K_0402_5% H B A F Title HD Audio Codec ALC268 Size B Document Number Rev 1.0 ICW50 / ICY70 LA-3581P Date: Friday, April 20, 2007 G Sheet 32 H of 42 A B C D PVT Modify 2007/3/12 E Speaker Conn FBM-11-160808-700T_0603 L63 +3VS R523 0_0603_5% +5VAMP R524 0_0603_5% @ C679 0.1U_0402_16V4Z HPF Fc = 604Hz +5VAMP W=40mil 1 G1 G2 ACES_88266-02001 L66 VDD 19 20 10 PVDD PVDD 11 U31 HVDD 1 AMP_LEFT_C-1 C599 0.47U_0603_16V4Z R414 R416 (32) AMP_LEFT SPKR+ SPKR- AMP_RIGHT_C 1U_0603_10V4Z AMP_LEFT_C 1U_0603_10V4Z C604 C600 JP3 SPK_L+ SPK_L2 FBM-11-160808-700T_0603 1 L65 AMP_RIGHT_C-1 CVDD (32) AMP_RIGHT L64 C606 C595 0.1U_0402_16V4Z 2 4.7U_0805_10V4Z C603 0.47U_0603_16V4Z SPKL+ SPKL- FBM-11-160808-700T_0603 SPK_R+ SPK_R2 FBM-11-160808-700T_0603 1 JP34 20mil 2 G1 G2 ACES_88266-02001 VOL_AMP 26 17 18 CVSS 15 VSS 16 GND PGND PGND CGND GND 23 13 29 /SD R422 30K_0402_5% C592 1U_0603_10V4Z VOL_AMP S 2 C598 R420 100K_0402_1% C680 0.01U_0402_16V7K D 28 BEEP 12 14 CP+ CP- 25 BIAS SPDIF_PLUG# C591 1U_0603_10V4Z Q43 AO3413_SOT23-3 2.2U_0805_10V6K 2 G Q53 2N7002_SOT23 S/PDIF Out JACK LINE Out/Headphone Out C468 (27,28) EC_MUTE +3VALW EC_MUTE 31 51_0402_1% HPOUT_L_1 51_0402_1% HPOUT_R_1 JP4 0.1U_0402_16V4Z BATT_GRN_LED# (27,28,30) BATT_AMB_LED# (27,28,30) PWR_LED# (30) PWR_SUSP_LED# (30) +3VALW LID_SW# (27,28,30) +5VALW 2 G1 G2 MIC_R L57 L58 INT_MIC_R 2MBK1608121YZF_0603 MBK1608121YZF_0603 C460 C65 SINGA_2SJ-E373-T01 JP33 15mil LINEIN_PLUG# (32) LINEIN_PLUG# LINE_R LINE_L (32) LINE_L L51 FBM-11-160808-700T_0603 LINE_R_R L48 LINE_L_R FBM-11-160808-700T_0603 1 MIC_R 220P_0402_50V7K (32) LINE_R C613 220P_0402_50V7K @ PSOT24C-LF-T7_SOT23-3 D28 SINGA_2SJ-E351-S03 C614 220P_0402_50V7K LINE-IN JACK (HDA Jack) SW1 XRE094PHDINB1-2-12-E-7016_3P U28 C562 (32) MIC1_R U27 CD1# D1 CP1 SD1# Q1 Q1# GND VCC CD2# D2 CP2 SD2# Q2 Q2# 14 13 12 11 10 09 08 (32) MIC1_L TC74LCX74FT_TSSOP14 2 FBM-11-160808-700T_0603 C616 220P_0402_50V7K MIC2_R_1 1 C615 220P_0402_50V7K SINGA_2SJ-E351-S01 MIC JACK (HDA Jack) ENCODER_DIR (27,28) ENCODER_PULSE (27,28) Volume Control Circuit Compal Electronics, Inc Compal Secret Data Security Classification 2006/08/18 Issued Date 2007/8/18 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A MIC_PLUG# MIC2_L_1 FBM-11-160808-700T_0603 C558 1 L49 L50 (32) MIC_PLUG# R425 2.2K_0402_5% R426 2.2K_0402_5% NC7SZ14P5X_NL_SC70-5 R399 10K_0402_5% C559 +3VS 0.1U_0402_16V4Z C563 Y JP32 MIC1_VREFO_R 1 P NC 0.1U_0402_16V4Z G A MIC1_VREFO_L 2 R402 10K_0402_5% 0.1U_0402_16V4Z GND B +3VS COM C557 0.01U_0402_16V7K A R403 100K_0402_5% R401 10K_0402_5% 2 GND R400 10K_0402_5% 0.01U_0402_16V7K 1 +3VS INT_MIC_R (32) 15mil +3VS JP31 100P_0402_50V8J ACES_88266-02001 0.1U_0402_16V4Z HP_PLUG# (32) 20_0402_5% 10 C620 S/PDIF Jack LINE-IN Jack MIC-IN Jack Sub-Woofer Lid Switch L36 L35 R106 2.2K_0402_5% C621 R565 (32) SPDIF +5VSPDIF +5VAMP BATT_GRN_LED# BATT_AMB_LED# PWR_LED# PWR_SUSP_LED# ACES_88107-30001 2 GNDGND 32 MIC2_VREFO +5VSPDIF SPDIF_PLUG# HPP_PLUG# LINEIN_PLUG# MIC_PLUG# @ 0_0402_5% R5641 330P_0402_50V7K 1 330P_0402_50V7K HPP_PLUG# HPOUT_L_2 FBM-11-160808-700T_0603 HPOUT_R_2 FBM-11-160808-700T_0603 SPDIF_PLUG# MIC2_R_1 MIC2_L_1 HPOUT_R PVT Modify 2007/3/12 FOR EMI 0.1U_0402_16V4Z +5VAMP (32) WOOFER_MONO R284 Int MIC Conn C488 SPDIF C467 JP13 10 12 14 16 18 20 22 24 26 28 30 2N7002_SOT23 To AUDIO/B Connector 11 13 15 17 19 21 23 25 27 29 2N7002_SOT23 S PVT Modify 2007/3/12 R285 LINE_R_R LINE_L_R S 20mil HPOUT_L HPOUT_L_2 HPOUT_R_2 D D APA2057A_TSSOP28 EC_MUTE +5VSPDIF 10 12 14 16 18 20 22 24 26 28 30 G Q61 G Q60 +5VSPDIF PVT Modify 2007/3/12 11 13 15 17 19 21 23 25 27 29 R549 100K_0402_5% R468 100K_0402_5% 39K_0402_5% HP_R HP_L HP_RIGHT_R 39K_0402_5% HP_LEFT_R MP Modify 2007/4/12 HP_PLUG# INR_H INL_H HPOUT_R HPOUT_L +5VAMP +5VAMP 1 SPKL+ SPKL- HP EN +5VAMP 2.2U_0805_10V6K HP_RIGHT_C 1 2.2U_0805_10V6K R412 HP_LEFT_C 1 R410 LOUT+ LOUT- 24 SPKR+ SPKR- 2 100K_0402_5% 22 21 /AMP EN R417 ROUT+ ROUT- (32) HP_LEFT 27 (32) HP_RIGHT +5VAMP 2 C596 HP_RIGHT C593 HP_LEFT INR_A INL_A 100K_0402_5% D Gain= 14dB R423 S 560_0402_5% G 560_0402_5% B C D Title Amplifier & Audio Jack Size B Date: Document Number Rev 1.0 ICW50 / ICY70 LA-3581P Friday, April 20, 2007 Sheet E 33 of 42 A B C D E +5VALW +1.2VALW TO +1.2V_HT +3VALW TO +3VS +1.2V_HT R39 10K_0402_5% +3VS D SUSP G Q5 2N7002_SOT23 Q6 2N7002_SOT23 +VSB 10U_0805_10V4Z R330 @ 1M_0402_1% C505 0.1U_0603_25V7K S D 2VLDT_EN# G Q7 2N7002_SOT23 S R31 100K_0402_5% 2N7002_SOT23 VLDT_EN# G Q41 2N7002_SOT23 S D D 1 R326 100K_0402_5% 1.2VHT_GATE SI4800BDY_SO8 C49 G Q8 (15) VLDT_EN +5VALW 2 S S SUSP R20 @ 1M_0402_1% C24 0.1U_0603_25V7K 10U_0805_10V4Z C19 2 D G 1 SI4800BDY_SO8 S S S G +VSB D D D D 5VS_GATE 20K_0402_1% U2 VLDT_EN# R42 470_0402_5% 10U_0805_10V4Z C32 R22 470_0402_5% R21 100K_0402_5% 1U_0603_10V4Z R28 +1.2VALW 2 S S S G 1U_0603_10V4Z C33 D D D D 1 10U_0805_10V4Z +3VS C21 U1 C15 1 +3VALW +1.2V_HT +1.2VALW TO +1.2VS +5VALW TO +5VS D 5VS_GATE SUSP G Q32 2N7002_SOT23 2 C158 10U_0805_10V4Z 1U_0603_10V4Z SUSP G Q13 2N7002_SOT23 R363 60.4K_0402_1% R227 10K_0402_5% G Q25 +3VALW TO +3V_SB(MCP67 AUX Power) +3VALW +1.8VS 4.7U_0805_10V4Z 1U_0603_10V4Z C638 C636 10U_0805_10V4Z 2 1U_0603_10V4Z 10U_0805_10V4Z D 5VS_GATE C392 0.1U_0603_25V7K D S SBPWR_EN# Q49G 2N7002_SOT23 S 2 SBPWR_EN# G Q48 2N7002_SOT23 R457 10K_0402_5% C639 0.1U_0603_25V7K SBPWR_EN# (13) SBPWR_EN# 1 +5VALW R266 60.4K_0402_1% 3V_GATE R447 200K_0402_5% +VSB 2 SUSP G Q31 2N7002_SOT23 S R446 470_0603_5% D C395 4.7U_0805_10V4Z 2 S S S G SI4800BDY_SO8 C390 SI4856ADY-T1-E3_SO8 C637 D D D D C391 R264 470_0402_5% 1 +1.8VS 1 S 2N7002_SOT23 U35 U17 S S S G D +1.8V D D D D R223 100K_0402_5% +3V SYSON SYSON# +1.8V TO +1.8VS C515 0.1U_0603_25V7K (26,27,28,40) SYSON A S D SUSP G Q17 2N7002_SOT23 D SYSON# G Q20 2N7002_SOT23 @ S B Compal Secret Data Security Classification 1 R185 470_0402_5% S 3 S D SUSP G Q22 2N7002_SOT23 R153 470_0402_5% @ D R458 100K_0402_5% 2 1 R131 470_0402_5% R180 470_0402_5% +1.8V 2 +0.9V +1.5VS D G Q51 S 2N7002_SOT23 (22,27,28,40) SBPWR_EN +2.5VS +5VALW 5VS_GATE (39) SYSON# S 2N7002_SOT23 D S C423 0.1U_0603_25V7K R272 100K_0402_5% R109 470_0402_5% C517 22U_0805_6.3V6M 1 C521 S +1.2VS SI4856ADY-T1-E3_SO8 C419 4.7U_0805_10V4Z S S S G 2 1U_0603_10V4Z D D D D 4.7U_0805_10V4Z R267 470_0402_5% C400 D C401 G Q34 (23,26,27,28,38) SUSP# 2 SI4800BDY_SO8 U24 2 S S S G D D D D +1.2VS U19 SUSP (39) SUSP +1.2VALW +5VS +5VS +5VALW R273 10K_0402_5% SYSON# G Q23 2N7002_SOT23 2006/08/18 Issued Date Deciphered Date 2007/8/18 C Title DC INTERFACE THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC D Size B Date: Document Number Rev 1.0 ICW50 / ICY70 LA-3581P Friday, April 20, 2007 Sheet E 34 of 42 A B C D PJP1 1 PR2 1K_1206_5% PD1 RLZ24B_LL34 B+ 100K_0402_5% PR7 1K_1206_5% PR6 E&T_4510-E04C-01R PR4 1K_1206_5% 2 RLS4148_LLDS2 PQ1 TP0610K-T1-E3_SOT23-3 PR5 1 100K_0402_5% PR3 1K_1206_5% PD2 VIN 560P_0402_50V7K PR1 10_1206_5% PC4 2 PC3 2 12P_0402_50V8J 3 PC2 VIN FBMA-L18-453215-900LMA90T_1812 12P_0402_50V8J PL1 ADPIN PC1 G1 560P_0402_50V7K G2 PR8 100K_0402_5% (27,28,38) ACOFF PR9 33_1206_5% VS PQ3 DTC115EUA_SC70-3 2 PQ2 DTC115EUA_SC70-3 RLS4148_LLDS2 1 PD4 RB751V-40TE17_SOD323-2 BATT+ PD3 VIN (30,31) 51ON# 2 3 PQ4 TP0610K-T1-E3_SOT23-3 PC6 0.1U_0603_25V7K PR11 22K_0402_5% 2 PR10 100K_0402_5% 0.22U_1206_25V7K PC5 1 CHGRTCP B+ PR12 2.2M_0402_5% VL PR13 499K_0402_1% ACIN 2006/09/01 B PACIN (37,38) 1 S PQ6 DTC115EUA_SC70-3 @ PR22 66.5K_0402_1% +5VALW 2 Deciphered Date Compal Electronics, Inc 2007/09/01 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A PR21 47K_0402_5% 2PQ5 G RHU002N06_SOT323-3 Compal Secret Data Security Classification Issued Date D RTCVREF PR20 34K_0402_1% BATT ONLY Precharge detector Min typ Max H >L 6.138V 6.214V 6.359V L >H 7.196V 7.349V 7.505V PR19 499K_0402_1% Precharge detector Min typ Max H >L 14.589V 14.84V 15.243V L >H 15.562V 15.97V 16.388V PR18 191K_0402_1% PC9 0.01U_0402_25V7K PC10 0.1U_0603_25V7K PRG++ - 32.4 RB715F_SOT323-3 PC7 1U_0805_25V4Z + O PC11 1000P_0402_50V7K (38) ACON P GND 2 PU2A LM393DR_SO8 G IN OUT 2 560_0603_5% 560_0603_5% 2 PD5 PR17 PC8 1 4.7U_0805_6.3V6K PR16 +CHGRTC (6,36,37) MAINPWON PU1 G920AT24U_SOT89-3 PR14 100K_0402_1% PR15 200_0805_5% RTCVREF 3.3V 1 VS C Title DCIN/DECTOR Size B Date: Document Number Rev 1.0 ICW50/ICY70 Sheet Friday, April 20, 2007 D 35 of 42 A B C D MAX8744_B+ B+ MAX8744_B+ PL2 PC16 2200P_0402_50V7K D D D D PQ8 SI4800BDY-T1-E3_SO8 G S S S PC15 4.7U_1206_25V6K PC14 4.7U_1206_25V6K S S S G D D D D 1 PQ7 SI4800BDY-T1-E3_SO8 PC13 4.7U_1206_25V6K PC12 2200P_0402_50V7K FBMA-L18-453215-900LMA90T_1812 MAX8744ETJ+_TQFN32_5X5 PGND 19 29 CSH3 CSH5 12 CSH5 CSL5 13 CSL5 FB5 11 FB5 LDO5 20 SKIP 10 CSL3 30 FB3 PGOOD3 27 PGOOD5 14 ON5 ON3 2 PC29 1U_0603_6.3V6M GND ILIM 1 ILM FSEL 2VREF_8744 @ ONA PR40 PR41 @ 47K_0402_5% 2 1 2VREF_8744 (6,35,37) MAINPWON SPOK (37,40) PR36 0.22U_0603_10V7K + PR70 0_0402_5% SHDN 1000P_0402_50V7K 2VREF_8744 @ PR32 0_0402_5% FBA 0_0402_5% PC28 PGOODA 4.7U_0805_6.3V6K 2 31 22 PC26 OUTA PC25 PR33 10K_0402_1% 32 VL +5VALWP DRVA REF A3 modify PR35 200K_0402_5% PR34 100K_0402_5% 21 2 499K_0402_1% PR37 2VREF_8744 PC24 0.22U_0603_16V7K 2 @ PC97 0.1U_0603_25V7K CSL3 28 PL4 S COIL 8.2UH +-20% MPL73-8R2 4A CSH3 A2 modify 18 DL5 PC27 150U_D2_6.3VM DL3 PR31 15.4K_0402_1% 23 PR29 825_0402_1% 17 LX5 PR27 2.21K_0402_1% 1 LX3 @ PC22 0.22U_0603_16V7K 24 DL3 0.1U_0603_25V7K LX5 LX3 12VREF_8744 0_0402_5% +5VALWP Ipeak = 7.49A ; Imax = 5.3A DCR = 68m ohm(max) ; Rcs = 16.04m ohm DCR = 64m ohm(typical) ; Rcs = 15.06m ohm Ilimit = 185mV/16.04m ~ 215mV/15.06m = 11.53A ~ 14.28A @ PC30 0.047U_0402_16V7K Iocp(mean) = Ilimit -Delta I/2 =10.032A~12.782A Delta I=((Vin-Vo)*D)/(F*L) =((19-3.3)*(3.3/19))/(300K*8.2U) =1.108A Delta I=((Vin-Vo)*D)/(F*L) =((19-5)*(5/19))/(300K*8.2U) =1.498A Notes : PR177 4.7_1206_5% PR25 BST5A 2.2_0402_5% 15 1 BST5 PC20 DCR = 68m ohm(max) ; Rcs = 16.04m ohm Ilimit = 185mV/16.04m ~ 215mV/15.06m = 11.53A ~ 14.28A Iocp(mean) = Ilimit -Delta I/2 =10.442A~13.172A BST3 @ 26 DH5 PC138 680P_0402_50V7K BST3A 2.2_0402_5% @ PR38 0_0402_5% DCR = 64m ohm(typical) ; Rcs = 15.06m ohm 16 PR39 0_0402_5% +3VALWP Ipeak = 8.57A; Imax = 6A DH5 0.1U_0603_25V7K PZD1 RLZ5.1B_LL34 DH3 PQ9 25 SI4810BDY-T1-E3_SO8 G D S D S D S D DH3 FB3 21 PC19 0.1U_0603_25V7K PC23 1000P_0402_50V7K IN EP PQ10 SI4810BDY-T1-E3_SO8 S D S D S D G D 33 PR24 @ PC93 VS PC17 1U_1206_25V7K PU3 2 PC21 0.22U_0603_16V7K 680P_0402_50V7K PC137 PR176 4.7_1206_5% PR28 825_0402_1% 2 A2 modify PR30 10K_0402_1% + PR26 6.81K_0402_1% 2 PC18 330U_D3L_6.3VM_R25M +3VALWP PR23 2.21K_0402_1% PL3 S COIL 8.2UH +-20% MPL73-8R2 4A fESR3.3V starts up delay 2ms after 5V starts up Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2006/09/01 Deciphered Date 2007/09/01 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C Title +5VALWP/+3VALWP Size Document Number Custom ICW50/ICY70 Date: Rev 1.0 Sheet Friday, April 20, 2007 D 36 of 42 A B BATT++ C BATT+ PH1 under CPU botten side : CPU thermal protection at 90 degree C Recovery at 70 degree C 1 PL7 HCB4532KF-800T90_1812 D PC56 0.01U_0402_25V7K 2 PC57 1000P_0603_50V7K VL SUYIN_200275MR007G161ZL 1 PC59 1000P_0402_50V7K +3VALWP PR73 150K_0402_1% + - P TM_REF1 O MAINPWON (6,35,36) PU2B LM393DR_SO8 PR81 150K_0402_1% VL 1 PR82 1K_0603_1% PR77 82.5K_0603_1% 2 6.49K_0603_1% PR80 PR76 442K_0603_1% PC60 1U_0805_16V7K PH1 100K_0603_1%_TH11-4H104FT 100_0603_1% PR78 2 PR79 SMART Battery: 1.BATT+ 2.BATT+ 3.TS 4.SMC 5.SMD 6.GND 7.GND 100_0603_1% PJP2 battery connector PC58 0.1U_0603_25V7K PR75 9.76K_0402_1% G TSA EC_SMC1 EC_SMD1 1 2 PR83 150K_0402_1% 2 2 VL VS PJP2 BATT_TEMP (27,28) EC_SMB_CK1 (18,27,28,29) EC_SMB_DA1 (18,27,28,29) PR84 1M_0402_1% VIN 1 VIN S P PACIN (35,38) 1 G LM393DR_SO8 PR90 10K_0402_5% PZD2 RLZ4.3B_LL34 RTCVREF PQ26 RHU002N06_SOT323-3 G (36,40) SPOK D ACIN (15,18,27,28) PACIN + - PU6B P G O Vin Detector Min typ Max H >L 16.976V 17.257V 17.728V L >H 17.430V 17.901V 18.384V PR94 100K_0402_5% PR95 0_0402_5% ACIN PC64 0.1U_0603_25V7K PR87 10K_0402_5% O PR92 10K_0402_5% 1 - PU6A 2 PR93 22K_0402_5% VL PC63 0.22U_1206_25V7K + PC62 0.1U_0603_25V7K PR91 100K_0402_5% 2 B+ PR89 20K_0402_1% PQ25 TP0610K-T1-E3_SOT23-3 +VSBP PC61 1000P_0402_50V7K PR88 22K_0402_5% PR86 10K_0402_5% VS PR85 84.5K_0402_1% LM393DR_SO8 PC65 0.1U_0603_25V7K Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2006/09/01 Deciphered Date 2007/09/01 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C Title BATTERY CONN / OTP Size B Date: Document Number Rev 1.0 ICW50/ICY70 Sheet Friday, April 20, 2007 D 37 of 42 A B CP = 85%*Iada ; CP = 4.07A B+ PL5 CSIN 1 2 ACSET ACPRN 23 EN 22 CSIN VCOMP CSIP 19 PC44 0.1U_0603_25V7K LX_CHG DH_CHG PQ20 SI4800BDY-T1-E3_SO8 D PR64 274K_0402_1% PQ24 SI2301BDS-T1-E3_SOT23-3 ACLIM VDDP 15 VADJ LGATE 14 GND PGND 13 G S S S Normal 4S LI-ON Cells 16800mV LOW HIGH 16.80V Normal 3S LI-ON Cells 12600mV HIGH HIGH 12.60V HIGH HIGH 12.60V - A Issued Date 2006/09/01 (27,28) 65W/90W# Deciphered Date C UMA@ G PQ47 RHU002N06_SOT323-3 D S Compal Electronics, Inc 2007/09/01 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC B PC55 0.01U_0402_25V7K 1 PR69 200K_0402_1% LM358ADR_SO8 PR174 20K_0402_1% 2 Compal Secret Data Security Classification 6251aclim 11.5K_0402_1% - PR60 6251VREF PR67 300K_0603_0.1% P G PU5A + BATT-OVP=0.1487*BATT+ Wake up charge while no communication 1 LI-3S :13.50V BATT-OVP=2.007V PR66 845K_0603_1% LM358ADR_SO8 BATT-OVP=0.1487*BATT+ - LI-4S :18.0V BATT-OVP=2.677V BATT+ P 12.90V PU5B + G 17.20V PC54 0.01U_0402_25V7K LOW (27,28) BATT_OVP PR68 10K_0402_5% PC53 0.01U_0402_25V7K LOW @ PQ46 2SC2411K_SOT23-3 @ PR171 20K_0402_1% CV mode VS 6251_EN @ S PC133 0.01U_0402_25V7K A3 modify PR170 100K_0402_1% @ C B E VS CHGSEL LOW PQ45 RHU002N06_SOT323-3 G (27,28) Calibrate 3S/4S# HIGH OVP voltage : PR63 UMA@ 2.37K_0402_1% 13050mV PC136 680P_0402_50V7K @ PC52 4.7U_0805_6.3V6K D CSON 2800mAH 3S pack PR56 0.02_2512_1% IREF=0.43V~3.24V 17400mV ISL6251AHAZ-T_QSOP24 IREF=0.7224*Icharge 2800mAH 4S pack 26251VDD 4.7_0603_5% PR62 6251VREF CC=0.6~4.48A Charging Voltage (0x15) 6251VDDP DL_CHG PR169 274K_0402_1% (27,28) CHGSEL BATT Type BST_CHG 2.2_0603_5% BATT+ 10 PR175 4.7_1206_5% @ 16 BOOT CHLIM PC48 BST_CHGA 0.1U_0603_25V7K PD9 RB751V-40TE17_SOD323-2 PL6 10UH_PCMB104T-100MS_6A_20% CHG D D D D 17 2.2_0603_5% G S S S UGATE PR173 PQ22 SI4800BDY-T1-E3_SO8 VREF 12 G CP mode Iinput=(1/0.02)(0.05*Vaclm/2.39+0.05) where Vaclm=1.502V, Iinput=4.07A PHASE 11 PR65 100K_0402_1% 6251aclim S 6251VREF ICM 18 PACIN G PQ18 RHU002N06_SOT323-3 2 (27,28,35) ACOFF 0.01U_0402_25V7K PR61 100K_0402_1% PR58 0.1U_0603_25V7K PQ23 DTC115EUA_SC70-3 6251VREF PC47 PR59 80.6K_0402_1% 1 (27,28) IREF PR55 100_0402_1% CSOP PR53 20_0603_5% PQ21 RHU002N06_SOT323-3 (27,28) ADP_I PC51 ACON PR54 10K_0402_1% PC46 100P_0402_50V8J S ICOMP 20 D 21 CSOP CELLS CSON 1SS355_SOD323-2 PR172 20_0603_5% PC41 0.047U_0603_16V7K PR52 20_0603_5% CSON PC37 0.1U_0603_25V7K DCIN PC50 10U_1206_25V6M 24 DCIN VIN 200K_0402_1% PQ15 DTC115EUA_SC70-3 PD8 2 PC49 10U_1206_25V6M VDD 1 2.2U_0603_6.3V6K PR47 S G (35) ACON D (35,37) PACIN PR57 22K_0402_5% PACIN ACOFF (27,28,35) PU4 S PC45 2 SUSP# (23,26,27,28,34) 0.01U_0402_25V7K 1SS355_SOD323-2 RB715F_SOT323-3 6251_EN PC43 6800P_0402_25V7K VIN PD6 PR46 10K_0402_1% 100K_0402_1% PR50 @ PC42 @PC42 680P_0402_50V7K CSON 2 PR45 47K_0402_1% 2FSTCHG PR51 150K_0402_1% (27,28) 3S/4S# PQ17 DTC115EUA_SC70-3 D 1 6251VDD PR49 47K_0402_5% PQ19 RHU002N06_SOT323-3 PR48 10K_0402_5% PC132 0.1U_0402_16V7K (27,28) FSTCHG 2 G 100K_0402_1% A3 modify PD15 PD14 1SS355TE-17_SOD323-2 6251VDD 2 PQ44 DTC115EUA_SC70-3 PR168 PC38 PQ14 DTA144EUA_SC70-3 A3 modify DCIN P3 PR167 100K_0402_1% PR44 200K_0402_1% PQ16 DTC115EUA_SC70-3 PC31 10U_1206_25V6M PQ43 TP0610K-T1-E3_SOT23-3 PC36 5600P_0402_25V7K CSIP 2 PC35 0.1U_0603_25V7K PR43 47K_0402_1% PC40 0.1U_0603_25V7K PQ13 AO4407_SO8 CHG_B+ FBMA-L18-453215-900LMA90T_1812 4 1 PR42 0.02_2512_1% P3 PQ12 AO4407_SO8 PC34 2200P_0402_25V7K 1 D D D D P2 PC33 0.1U_0603_25V7K ADP_I = 19.9*Iadapter*Rsense PQ11 AO4407_SO8 VIN D PC32 10U_1206_25V6M Iada=0~4.74A(90W) C Title CHARGER Size Document Number Rev 1.0 ICW50/ICY70 Date: Friday, April 20, 2007 Sheet D 38 of 42 1 +3VALW PJP3 JUMP_43X118 PJP4 JUMP_43X118 GND +2.5VSP VFB AGND VTT VCCA VTT REFEN 2 PC74 0.1U_0603_25V7K 1 PC72 22U_1206_10V6M PR98 60.4K_0402_1% PC73 0.047U_0402_16V7K 1 RHU002N06_SOT323-3 PC70 22U_1206_10V6M +0.9VP 2 G PQ27 PC71 0.1U_0603_25V7K S PR100 1K_0402_1% 1 (34) SYSON# D RT9173DPSP_SO8 PR99 0_0402_5% PGND PC69 1U_0603_16V6K NC VIN 2 VOUT PR96 1K_0402_1% 1 NC PC68 1U_0603_6.3V6M REFEN PU8 CM8562IS_PSOP8 PR101 200K_0402_1% NC +3VALW PR97 10_0603_1% GND RTCVREF VCNTL 2 PC67 10U_0805_6.3V6M VIN 1 PU7 AGND +1.8V D +5VALW D PC66 10U_0805_6.3V6M 1 2 +1.8V D C S 2PQ28 G RHU002N06_SOT323-3 PR102 0_0402_5% SUSP (34) C +1.8V 2 +3VALW +1.8VP 1 2 +1.8V PJP6 PJP7 JUMP_43X118 PJP5 1 +3VALWP JUMP_43X118 JUMP_43X118 JUMP_43X118 2 +1.5VS VIN PGND VFB AGND VTT VCCA VTT REFEN PJP11 +VSBP PJP12 1 2 +VSB PJP13 B PR104 60.4K_0402_1% PC78 0.047U_0402_16V7K 1 PC77 22U_1206_10V6M +0.9V 2 +1.5VSP JUMP_43X118 PC79 0.1U_0603_25V7K 1 RTCVREF PC76 1U_0603_16V6K +1.5VSP +1.2VALW +5VALW PU9 CM8562IS_PSOP8 PR105 51K_0402_1% PR103 10_0603_1% +2.5VS 1 JUMP_43X118 JUMP_43X118 +0.9VP JUMP_43X118 PJP10 B PJP9 AGND +2.5VSP PJP8 PC75 10U_0805_6.3V6M +5VALW 2 +1.2VALWP 2 +5VALWP JUMP_43X118 D S 2PQ29 G RHU002N06_SOT323-3 PR106 0_0402_5% SUSP (34) A A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2006/09/01 2007/09/01 Deciphered Date +0.9VSP/+1.5VSP/+2.5VSP THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Size Document Number Custom ICW50/ICY70 Date: Rev 1.0 Friday, April 20, 2007 Sheet 39 of 42 +5VALW 1 +3VALW BST_1.8V-1 LX_1.2V 11 VCCA2 FB_1.2V 12 FB2 13 PGD2 ILIM2 18 VDDP2 17 ILIM_1.2V PR119 30.1K_0402_1% +5VALW DL2 16 DL_1.2V PGND2 15 SC413TSTRT_TSSOP28 +3VALW 2 G S S S + PC98 1U_0603_10V6K PR121 10K_0402_1% PC99 0.1U_0603_25V7K @ PR123 100K_0402_5% (26,27,28,34) SYSON to VSSA1 and VOUT1 PIN FB_1.2V VFB=0.5V Close to IC Side Differential routing of feedback VSSA2 PC95 33P_0402_50V8K (22,27,28,34) SBPWR_EN 14 PQ33 SI4810BDY-T1-E3_SO8 +1.2VALWP Vout_1.2VALWP PC96 19 330U_D2_2.5VY_R15M LX2 Maximum continuous current=>6A PL10 1.8UH_SIL104R-1R8PF_9.5A_30% PR120 15K_0402_1% VOUT2 VCCA_1.2 PR117 0_0402_5% 2DH_1.2V-1 0.1U_0603_25V7K 20 21 DH2 C (36,37) SPOK PR165 0_0402_5% PR122 0_0402_5% BST_1.2V PR115 2.2_0402_5% DH_1.2V BST2 TON2 EN/PSV2 PC91 2 22 PQ31 SI4800BDY-T1-E3_SO8 EN/PSV1 BST1 PR112 820K_0402_5% Vout_1.8V 23 SC413_B+ PC88 4.7U_1206_25V6K 24 TON1 4.7U_1206_25V6K VOUT1 DH1 PC87 LX1 SC413_B+ VCCA_1.8 25 D D D D VCCA1 @ B ILIM1 MEM_VLD (15,31) PC86 1000P_0402_50V7K S S S PC94 1000P_0402_50V7K Vout_1.2VALWP 10 FB_1.8V 26 PR116 1M_0402_5% G PR118 10K_0402_1% 2 SC413_B+ FB1 VDDP1 D D D D 0.1U_0603_25V7K PQ32 FDS6670AS_NL_SO8 27 G S S S D D D D FB_1.8V DH_1.8V PR114 BST_1.8V 2.2_0402_5% 28 PGD1 DL1 2 0_0402_5% @ PR166 0_0402_5% VSSA1 PGND1 Close to IC Side B Differential routing of feedback to VSSA2 and VOUT2 PIN 2 PC100 0.1U_0603_25V7K PR124 0_0402_5% 1 DH_1.8V-1 1 2 + PC90 33P_0402_50V8K @ PR109 100K_0402_5% S S S G DL_1.8V PC85 +5VALW 1U_0603_10V6K ILIM_1.8V PR111 30.1K_0402_1% LX_1.8V PC89 2 PC92 330U_D2_2.5VY_R15M PR113 26.1K_0402_1% Vout_1.8V C PL9 1UH_SIL104-1R0-R_11A_30% +1.8VP BST_1.2V-1 PQ30 SI4800BDY-T1-E3_SO8 PR110 Maximum continuous current=>6A VCCA_1.2 VCCA_1.8 PU10 D D D D PC84 4.7U_1206_25V6K PC83 4.7U_1206_25V6K FBMA-L11-322513-151LMA50T_1210 SC413_B+ PL8 PD13 CHP202UPT_SOT323-3 2 B+ PR108 10_0603_5% PR107 10_0603_5% PC82 1U_0603_10V6K PC80 2.2U_0603_6.3V6K PC81 1U_0603_10V6K D D @ PR164 0_0402_5% VFB=0.5V VFB=0.5V Vo=VFB*(1+PR120/PR121)=1.25V Vo=VFB*(1+PR122/PR127)=1.805V Ipeak=8.54A, Imax=6A Ipeak=13.82A, Imax=9.68A Ton=(3.3E-12*(PR116+37K)*(Vout/VBat))+50ns Ton=(3.3E-12*(PR112+37K)*(Vout/VBat))+50ns =0.2661us =3.3E-12*(820K+37K)*(1.805/19)+50ns=0.319us SI4810BDY:Rds(on)=>Typ:16 mOhm FDS6670AS:Rds(on)=>Typ:9 mOhm Max:20 mOhm Max:11.5 mOhm Ivalleymin=9E-6*(PR119/Rds(ON)max*1.3)=10.419A Iocp=Ivalley+Iripple/2 Ivalleymax=11E-6*(PR119/Rds(ON)typ*1.1)=18.8125A Iripple=(vin-vout)*(Ton/L)=5.485A Iripple=(vin-vout)*(Ton/L)=2.631A A Ivalleymin=9E-6*(PR106/Rds(ON)max*1.4)=16.826A A Iocp=Ivalley+Iripple/2 Ivalleymax=11E-6*(PR106/Rds(ON)typ*1.2)=30.657A OCP==>11.7345A~20.128A OCP==>19.5685A~33.3995A Compal Electronics, Inc Compal Secret Data Security Classification 2006/09/01 Issued Date Deciphered Date 2007/09/01 +1.8VALWP/+1.2VALWP THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Size Document Number Custom ICW50/ICY70 Date: Friday, April 20, 2007 Rev 1.0 Sheet 40 of 42 B+ CPU_B+ +5VS DH2 21 DH2 TON LX2 22 LX2 OFS DL2 24 DL2 VRHOT# PGND2 23 CSP2 13 CSN2 14 39 SKIP# PC121 220P_0402_50V8J D S PQ40 FDV301N_NL_SOT23-3 PC105 100U_25V_M 1 PR137 4.22K_0402_1% 2 PQ38 SI7686DP-T1-E3_SO8 PR158 0_0402_5% 3 CPU_B+ PR161 10_0402_5% (6) PC115 0.22U_0603_16V7K PR149 0_0402_5% 1 2 (6) PSI# 0_0402_5% PQ41 FDS6676AS_SO8 G D S D S D S D PQ39 RHU002N06_SOT323-3 G PR147 C 220P_0402_50V8J PR156 100_0402_1% PC126 4700P_0603_50V7K PC120 PR155 200K_0402_1% B 20 @ PC129 @PC129 4700P_0402_25V7K CPU_VSS_SENSE (6) CPU_VCC_SENSE B REF PC117 BST2 10_0402_5% POUT PR140 PC125 0.01U_0402_25V7K CCI PL13 P_0.36H_ETQP4LR36WFC_24A_20% 2 CCV @PC131 @ PC131 1U_0805_16V7K PR160 4.22K_0402_1% PH3 PR162 10KB_0603_5%_ERTJ1VR103J 2.1K_0402_1% 2 FB PC128 680P_0603_50V7K TIME 11 PC114 4700P_0402_25V7K PR146 20K_0402_1% 2 470P_0603_50V8J PC113 680P_0603_50V7K PR144 2K_0603_1% FB PC122 40 PR139 PH2 2.1K_0402_1% 10KB_0603_5%_ERTJ1VR103J 2 2200P_0402_50V7K PC123 4.7U_1206_25V6K PC124 4.7U_1206_25V6K IC PR159 4.7_1206_5% SHDN# @ AGND 38 1 PR157 200K_0402_1% PC101 4.7U_1206_25V6K PC102 4.7U_1206_25V6K PC103 0.01U_0402_25V7K PC104 2200P_0402_50V7K PC134 330P_0402_50V7K PC135 330P_0402_50V7K 18 PR134 4.7_1206_5% 1 15 GND PC110 220P_0402_50V8J PC111 220P_0402_50V8J FDS6676AS_SO8 CSN1 TWO-PH FDS6676AS_SO8 PQ36 G D S D S D S D PHASEGD 37 17 16 D D D D CSP1 PQ35 PWRGD G S S S 27 PC112 4700P_0402_25V7K PGND1 PC109 0.22U_0603_16V7K D5 PQ37 +3VS RHU002N06_SOT323-3 G PC108 0.01U_0402_25V7K DL1 36 PQ42 FDS6676AS_SO8 G D S D S D S D S 26 EP D LX1 DL1 MAX8774_REF 10 0.1U_0603_25V7K PR153 0_0402_5% PR152 169K_0603_1% 28 D4 200K_0402_1% D3 MAX8774GTL+_TQFN40 LX1 35 PL12 P_0.36H_ETQP4LR36WFC_24A_20% MAX8774_REF PR151 31.6K_0402_1% PC119 PR150 CPU_B+ 71.5K_0402_1% PC116 150P_0402_50V8J 1 PC118 0.1U_0603_25V7K 34 D +CPU_CORE 100K_0402_5% PR148 10K_0402_1% (27,28) POUT DH1 PR145 100_0402_1% PR143 2 29 MAX8774_VCC @ PR142 @PR142 DH1 PU11 12 (15) VR_ON D2 41 C 33 + PR131 0_0402_5% 0.22U_0603_16V7K +3VS PR141 0_0402_5% 30 PQ34 SI7686DP-T1-E3_SO8 PR154 2.2_0402_5% (15) VGATE BST1 PC127 (6) VID5 THRM D1 (6) VID4 D0 32 (6) VID3 PR129 2.2_0402_5% 31 (6) VID2 25 (6) VID1 VDD GNDS PR127 0_0402_5% PR128 0_0402_5% PR130 0_0402_5% PR132 0_0402_5% PR133 0_0402_5% PR135 0_0402_5% PR136 0_0402_5% PR138 100K_0402_1% (6) VID0 VCC MAX8774_VCC 19 PC107 2.2U_0603_10V6K D PC106 2.2U_0603_6.3V6K PR125 10_0402_5% +3VS PR126 10K_0402_5% PL11 FBMA-L18-453215-900LMA90T_1812 PC130 0.22U_0603_16V7K CSP2 PR163 0_0402_5% A A 2006/09/01 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification Deciphered Date 2007/09/01 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title +CPU_CORE Size Document Number Custom ICW50/ICY70 Date: Rev 1.0 Friday, April 20, 2007 Sheet 41 of 42 Version change list (P.I.R List) Item Fixed Issue Rev PG# Page of for HW Modify List Date Phase D C B D BOM Change 0.4 12 Remove R144, R372, C160, C528 PVT Added SSC for Lan TXCLK (EMI Request) 0.4 12 Added U40, R525, R526, R527, R528, C682 PVT Improve Samsung Memory Module compatibility 0.4 15 Added R540,R541 2.2K pull up +3VS PVT Design Modify.(SCH Change) 0.4 15 Change CRT_DET form GPIO_5 to LID#, Add R78 10K (Bios Request) PVT BCIC0172 : When Reset or Cold Boot MCP67 ACIN 會漏電到EC 0.4 15 D24 反向, 47K Pull High移除.Added R283 200K Pull Down PVT RTC Battery 電壓過低 0.4 16 Added R539 1K PVT Design Modify.(SCH Change) 0.4 22 Change Q50.G Pin Net Name to SBPWR_EN PVT Added R-C for BUF_25Mhz (EMI Request) 0.4 22 Added R530,C684 PVT Design Modify for EMI 0.4 22 Added L59, L60, L61, L62, C685, C686 PVT 10 解決+3VS 漏電 when enter S3 Mode 0.4 25,26 Added Q56, Q57, Q58, Q59, R536, R537 PVT 11 Design Modify for Acer WLAN LED 0.4 25 JP21.44 Pin Added MINI1_LED# Net, Added R520, R521 PVT 12 防止 BATT_TEMP, BATT_OVP, ACIN 被干擾 0.4 27 Added C660, C661, C662 PVT 13 Design Modify for Power (65W/95W Detect Function) 0.4 27 U15.98 Pin Added 65W/95W# Net, Added R519 100K to +3VALW PVT 14 Design Modify for EMI 0.4 30 Added C663~C678 PVT 15 For AUDIO EA Test 0.4 32 Change C582, C583, C584, C587,C594, C597 to 4.7uF PVT 16 解決關機 bo bo 聲問題 0.4 33 Added Q53,C680 PVT 17 Design Modify for EMI 0.4 33 Added L57, L58 for Mic L63, L64, L65, L66 for SPK D28 for ESD PVT 18 Change Codec Amp to APA2057RI-TRL_TSSOP28 0.4 33 Change U31 to SA00001QD00, added R523,R524 PVT 19 Remove PJP14 0.4 34 Remove PJP14 PVT 20 Change MCP67-MV form A01 to A02 0.4 10~17 Change MCP67-MV form A01 to A02 PVT 21 解決系統時間延遲問題 0.4 15 Change C503, C504 form 18pF to 6.8pF PVT 22 Improve WLAN Module compatibility 0.3 11,25 Change WLAN Port form PCIE4 to PCIE2 DVT2 23 Fixed LAN LED work abnormal 0.3 22 Added D25,D27,D27, U39 DVT2 24 Change LAN to RTL8211B 0.2 22 Change Page 22 all compnent C B A A DVT1 Compal Electronics, Inc Title PIR (HW) Size Document Number Date: Friday, April 20, 2007 LA-3581P ICW50 Sheet 42 of 42 Rev 1.0 ... ( 10 ) ( 10 ) ( 10 ) ( 10 ) ( 10 ) ( 10 ) ( 10 ) ( 10 ) ( 10 ) ( 10 ) ( 10 ) ( 10 ) ( 10 ) ( 10 ) ( 10 ) ( 10 ) ( 10 ) ( 10 ) ( 10 ) ( 10 ) ( 10 ) ( 10 ) ( 10 ) ( 10 ) ( 10 ) ( 10 ) ( 10 ) ( 10 ) W=40mils 51_ 04 02 _1% 51_ 04 02 _1% ( 10 ) H_CTLIP0 ( 10 ) H_CTLIN0... 99 10 1 10 3 10 5 10 7 10 9 11 1 11 3 11 5 11 7 11 9 12 1 12 3 12 5 12 7 12 9 13 1 13 3 13 5 13 7 13 9 14 1 14 3 14 5 14 7 14 9 15 1 15 3 15 5 15 7 15 9 16 1 16 3 16 5 16 7 16 9 17 1 17 3 17 5 17 7 17 9 18 1 18 3 18 5 18 7 18 9 19 1 19 3 19 5... 0. 1U _04 02 _16 V7K 0. 1U _04 02 _16 V7K 0. 1U _04 02 _16 V7K 0. 1U _04 02 _16 V7K 0. 1U _04 02 _16 V7K 0. 1U _04 02 _16 V7K 0. 1U _04 02 _16 V7K 0. 1U _04 02 _16 V7K 0. 1U _04 02 _16 V7K 0. 1U _04 02 _16 V7K 0. 1U _04 02 _16 V7K 0. 1U _04 02 _16 V7K 0. 1U _04 02 _16 V7K