acer aspire 4740 4745 5740 5745 compal la 5681p rev 1 0

A B C D E 1 Compal Confidential 2 NAL90/NALG0 M/B Schematics Document Intel Auburndale/Clarksfield Processor with DDRIII + Ibex Peak-M 2009-10-20 3 REV:1.0 4 2009/5/12 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2010/04/15 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Cover Page NALG0 M/B LA-5681P Schematic Date: A B C D Friday, October 23, 2009 Sheet E of 60 Rev 1.0 A B C D E Clock Generator Compal Confidential IDT: 9LRS3199AKLFT SILEGO: SLG8SP587 Model Name NALG0 File Name : LA5681P 133/120/100/96/14.318MHZ to PCH Fan Control 48MHZ to CardReader page 41 page 12 1 PEG(DIS) 100MHz PCI-E 2.0x16 5GT/s PER LANE Nvidia N11MGE1 HDMI(DIS) Memory BUS(DDRIII) Intel 204pin DDRIII-SO-DIMM X2 Dual Channel page 10,11 Auburndale / Clarksfield BANK 0, 1, 2, 1.5V DDRIII 800/1066/1333 (UMA/DIS) (DIS) 6.4G/8.5G/10.6G 133MHz LVDS(DIS) CRT(DIS) page 22,23,24,25,26,27 100M/133M/166M(CFD) Processor rPGA988A page 4,5,6,7,8,9 CRT Conn HDMI Conn page 30 page 29 CRT SW page 29 LVDS Conn FDI x8 (UMA) LVDS SW page 28 page 28 DMI x4 100MHz 100MHz 2.7GT/s 1GB/s x4 LVDS(UMA) Intel Ibex Peak-M CRT(UMA) Level Shift HDMI(UMA) page 30 port 2,4 page 13,14,15,16,17 18,19,20,21 port MINI Card x2 LAN(GbE) WLAN, TV BCM57780 page 32 Bluetooth Conn CMOS Camera USB port 10 USB port page 35 USBx14 3.3V 48MHz HD Audio 3.3V 24MHz page 35 USB port 11 page 28 page USB/B page 35 page 35 port port SATA HDD Conn SATA ODD Conn eSATA Conn page 31 page 31 page 35 Audio AMP APA2051 page 41 33MHz Int Speaker page 41 page 37 Touch Pad Int.KBD page 38 Power On/Off CKT page MDC page 39 page 40 LPC BUS NALG0 Sub-board LS-5682P USB/B page 36 ALC888 ENE KB926 RTC CKT USB port HDA Codec page 13 page 34 NAL90 Sub-board LS-5682P Card Reader page 35 SPI SPI ROM x2 RJ45 Finger Printer port page 33 USB port HS USB Port (eSATA) USB port (sub board) SATA x (GEN1 1.5GT/S ,GEN2 3GT/S) 100MHz PCH PCI-Express x (ABD PCIE1 2.5GT/S CKD PCIE1/2 2.5/5GT/S) 100MHz USB conn x2 page 38 LS-4493P Media/B BIOS ROM page 38 page 38 DC/DC Interface CKT LS-5683P LS-5683P Function/B Function/B page 38 page 38 page 42 LS-5681P Power Circuit DC/DC LS-5681P Finger Printer/B Finger Printer/B page 35 page 35 2009/5/12 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification page 2010/04/15 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C D Block Diagrams Document Number NALG0 M/B LA-5681P Schematic Friday, October 23, 2009 Sheet E of 60 Rev 1.0 A B C D SIGNAL STATE Voltage Rails Full ON HIGH HIGH HIGH ON ON ON ON HIGH HIGH HIGH ON ON ON LOW N/A N/A S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF N/A N/A S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF S3 Adapter power supply (19V) N/A B+ AC or battery power rail for power circuit N/A +CPU_CORE Core voltage for CPU ON ON OFF +GFX_core Core voltage for CPU ON OFF OFF +1.1VS_VTT 1.1V switched power rail (1.05 for AUB CPU) ON OFF OFF +VGA_CORE Core voltage for N11M VGA ON OFF OFF +1.05VS 1.05V switched power rail for PCH ON OFF OFF +1.5VS 1.5V power rail for DDRIII ON ON OFF +0.75VS 0.75V switched power rail for DDR terminator ON OFF OFF Vcc Ra/Rc/Re +1.5VS 1.5V switched power rail ON OFF OFF Board ID +1.8VS 1.8V switched power rail ON OFF OFF +3VALW 3.3V always on power rail ON ON ON* +3V_LAN 3.3V power rail for LAN ON ON ON* +3VS 3.3V switched power rail ON OFF OFF +5VALW 5V always on power rail ON ON ON* +5VS 5V switched power rail ON OFF OFF +VSB VSB always on power rail ON ON ON* +RTCVCC RTC power ON ON ON 3.3V +/- 5% 100K +/- 5% Rb / Rd / Rf 8.2K +/- 5% 18K +/- 5% 33K +/- 5% 56K +/- 5% 100K +/- 5% 200K +/- 5% NC Smart Battery 0001 011X b Interrupts Device Address USB 2.0 USB 1.1 Port UHCI0 VGA UHCI1 EHCI1 UHCI2 Ibex SM Bus address Address Clock Generator (9LRS3199AKLFT, SLG8SP587) 1101 0010b DDR DIMM0 1001 000Xb DDR DIMM2 1001 010Xb UHCI3 UHCI4 EHCI2 Mini card BTO Item UMA UMA only DIS DIS Only Switchable UHCI5 UHCI6 4 External USB Port Ext4 HS USB sub Board S3 power Camera 1st Min-Card 2st Min-Card Caps@ X76@ HDCP@ AMIC@ S3@ non S3@ BOM Config UMA only UMA@/UMA only@/FP@/Dmic@/XDP@/S3@ 10 11 12 13 BOM Structure UMA@ UMA only@ DIS@ DIS only@ SG@ XDP@ NonSG@ MINI2@ FP@ eDriver@ Dmic@ USB Port Table PCH Device V AD_BID max V 0.289 V 0.538 V 0.875 V 1.264 V 1.759 V 2.341 V 3.300 V BTO Option Table PCB Revision 0.1 0.2 0.3 1.0 External PCI Devices Address V AD_BID typ V 0.250 V 0.503 V 0.819 V 1.185 V 1.650 V 2.200 V 3.300 V BOARD ID Table Device V AD_BID V 0.216 V 0.436 V 0.712 V 1.036 V 1.453 V 1.935 V 2.500 V Board ID EC SM Bus2 address Board ID / SKU ID Table for AD channel Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF Clock LOW VIN EC SM Bus1 address +VS HIGH S1 REQ#/GNT# +V S1(Power On Suspend) Description IDSEL# +VALW S5 Power Plane Device SLP_S1# SLP_S3# SLP_S4# SLP_S5# E Ext4 HS USB Card Reader Blue Tooth Finger Print DIS ONLY DIS@/DIS only@/FP@/Dmic@/XDP@/S3@ Switchable Graphics SG@/UMA@/DIS@/FP@/Dmic@/XDP@/S3@ Note:do cost BOM add X76@ 2009/5/12 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification Deciphered Date 2010/04/15 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C D Notes List Document Number Rev 1.0 NALG0 M/B LA-5681P Schematic Friday, October 23, 2009 Sheet E of 60 JCPU1E DMI_PTX_HRX_P0 DMI_PTX_HRX_P1 DMI_PTX_HRX_P2 DMI_PTX_HRX_P3 B24 D23 B23 A22 DMI_RX[0] DMI_RX[1] DMI_RX[2] DMI_RX[3] DMI_HTX_PRX_N0 DMI_HTX_PRX_N1 DMI_HTX_PRX_N2 DMI_HTX_PRX_N3 D24 G24 F23 H23 DMI_TX#[0] DMI_TX#[1] DMI_TX#[2] DMI_TX#[3] DMI_HTX_PRX_P0 DMI_HTX_PRX_P1 DMI_HTX_PRX_P2 DMI_HTX_PRX_P3 D25 F24 E23 G23 DMI_TX[0] DMI_TX[1] DMI_TX[2] DMI_TX[3] E22 D21 D19 D18 G21 E19 F21 G18 FDI_TX#[0] FDI_TX#[1] FDI_TX#[2] FDI_TX#[3] FDI_TX#[4] FDI_TX#[5] FDI_TX#[6] FDI_TX#[7] H_FDI_TXP0 H_FDI_TXP1 H_FDI_TXP2 H_FDI_TXP3 H_FDI_TXP4 H_FDI_TXP5 H_FDI_TXP6 H_FDI_TXP7 D22 C21 D20 C18 G22 E20 F20 G19 FDI_TX[0] FDI_TX[1] FDI_TX[2] FDI_TX[3] FDI_TX[4] FDI_TX[5] FDI_TX[6] FDI_TX[7] F17 E17 FDI_FSYNC[0] FDI_FSYNC[1] H_FDI_INT C17 FDI_INT 15 H_FDI_LSYNC0 15 H_FDI_LSYNC1 F18 D17 FDI_LSYNC[0] FDI_LSYNC[1] C 15 H_FDI_FSYNC0 15 H_FDI_FSYNC1 15 Intel(R) FDI H_FDI_TXN0 H_FDI_TXN1 H_FDI_TXN2 H_FDI_TXN3 H_FDI_TXN4 H_FDI_TXN5 H_FDI_TXN6 H_FDI_TXN7 B PCI EXPRESS GRAPHICS DMI_RX#[0] DMI_RX#[1] DMI_RX#[2] DMI_RX#[3] DMI D A24 C23 B22 A21 PEG_IRCOMP R520 49.9_0402_1% EXP_RBIAS R535 750_0402_1% PEG_ICOMPI PEG_ICOMPO PEG_RCOMPO PEG_RBIAS B26 A26 B27 A25 PEG_RX#[0] PEG_RX#[1] PEG_RX#[2] PEG_RX#[3] PEG_RX#[4] PEG_RX#[5] PEG_RX#[6] PEG_RX#[7] PEG_RX#[8] PEG_RX#[9] PEG_RX#[10] PEG_RX#[11] PEG_RX#[12] PEG_RX#[13] PEG_RX#[14] PEG_RX#[15] K35 J34 J33 G35 G32 F34 F31 D35 E33 C33 D32 B32 C31 B28 B30 A31 PEG_GTX_C_HRX_N15 PEG_GTX_C_HRX_N14 PEG_GTX_C_HRX_N13 PEG_GTX_C_HRX_N12 PEG_GTX_C_HRX_N11 PEG_GTX_C_HRX_N10 PEG_GTX_C_HRX_N9 PEG_GTX_C_HRX_N8 PEG_GTX_C_HRX_N7 PEG_GTX_C_HRX_N6 PEG_GTX_C_HRX_N5 PEG_GTX_C_HRX_N4 PEG_GTX_C_HRX_N3 PEG_GTX_C_HRX_N2 PEG_GTX_C_HRX_N1 PEG_GTX_C_HRX_N0 PEG_RX[0] PEG_RX[1] PEG_RX[2] PEG_RX[3] PEG_RX[4] PEG_RX[5] PEG_RX[6] PEG_RX[7] PEG_RX[8] PEG_RX[9] PEG_RX[10] PEG_RX[11] PEG_RX[12] PEG_RX[13] PEG_RX[14] PEG_RX[15] J35 H34 H33 F35 G33 E34 F32 D34 F33 B33 D31 A32 C30 A28 B29 A30 PEG_GTX_C_HRX_P15 PEG_GTX_C_HRX_P14 PEG_GTX_C_HRX_P13 PEG_GTX_C_HRX_P12 PEG_GTX_C_HRX_P11 PEG_GTX_C_HRX_P10 PEG_GTX_C_HRX_P9 PEG_GTX_C_HRX_P8 PEG_GTX_C_HRX_P7 PEG_GTX_C_HRX_P6 PEG_GTX_C_HRX_P5 PEG_GTX_C_HRX_P4 PEG_GTX_C_HRX_P3 PEG_GTX_C_HRX_P2 PEG_GTX_C_HRX_P1 PEG_GTX_C_HRX_P0 PEG_TX#[0] PEG_TX#[1] PEG_TX#[2] PEG_TX#[3] PEG_TX#[4] PEG_TX#[5] PEG_TX#[6] PEG_TX#[7] PEG_TX#[8] PEG_TX#[9] PEG_TX#[10] PEG_TX#[11] PEG_TX#[12] PEG_TX#[13] PEG_TX#[14] PEG_TX#[15] L33 M35 M33 M30 L31 K32 M29 J31 K29 H30 H29 F29 E28 D29 D27 C26 PEG_HTX_GRX_N15 PEG_HTX_GRX_N14 PEG_HTX_GRX_N13 PEG_HTX_GRX_N12 PEG_HTX_GRX_N11 PEG_HTX_GRX_N10 PEG_HTX_GRX_N9 PEG_HTX_GRX_N8 PEG_HTX_GRX_N7 PEG_HTX_GRX_N6 PEG_HTX_GRX_N5 PEG_HTX_GRX_N4 PEG_HTX_GRX_N3 PEG_HTX_GRX_N2 PEG_HTX_GRX_N1 PEG_HTX_GRX_N0 C473 C475 C470 C458 C454 C447 C460 C455 C448 C464 C477 C463 C450 C482 C480 C468 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K PEG_HTX_C_GRX_N15 PEG_HTX_C_GRX_N14 PEG_HTX_C_GRX_N13 PEG_HTX_C_GRX_N12 PEG_HTX_C_GRX_N11 PEG_HTX_C_GRX_N10 PEG_HTX_C_GRX_N9 PEG_HTX_C_GRX_N8 PEG_HTX_C_GRX_N7 PEG_HTX_C_GRX_N6 PEG_HTX_C_GRX_N5 PEG_HTX_C_GRX_N4 PEG_HTX_C_GRX_N3 PEG_HTX_C_GRX_N2 PEG_HTX_C_GRX_N1 PEG_HTX_C_GRX_N0 PEG_TX[0] PEG_TX[1] PEG_TX[2] PEG_TX[3] PEG_TX[4] PEG_TX[5] PEG_TX[6] PEG_TX[7] PEG_TX[8] PEG_TX[9] PEG_TX[10] PEG_TX[11] PEG_TX[12] PEG_TX[13] PEG_TX[14] PEG_TX[15] L34 M34 M32 L30 M31 K31 M28 H31 K28 G30 G29 F28 E27 D28 C27 C25 PEG_HTX_GRX_P15 PEG_HTX_GRX_P14 PEG_HTX_GRX_P13 PEG_HTX_GRX_P12 PEG_HTX_GRX_P11 PEG_HTX_GRX_P10 PEG_HTX_GRX_P9 PEG_HTX_GRX_P8 PEG_HTX_GRX_P7 PEG_HTX_GRX_P6 PEG_HTX_GRX_P5 PEG_HTX_GRX_P4 PEG_HTX_GRX_P3 PEG_HTX_GRX_P2 PEG_HTX_GRX_P1 PEG_HTX_GRX_P0 C472 C474 C471 C465 C456 C451 C466 C457 C452 C469 C476 C462 C449 C481 C479 C467 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K PEG_HTX_C_GRX_P15 PEG_HTX_C_GRX_P14 PEG_HTX_C_GRX_P13 PEG_HTX_C_GRX_P12 PEG_HTX_C_GRX_P11 PEG_HTX_C_GRX_P10 PEG_HTX_C_GRX_P9 PEG_HTX_C_GRX_P8 PEG_HTX_C_GRX_P7 PEG_HTX_C_GRX_P6 PEG_HTX_C_GRX_P5 PEG_HTX_C_GRX_P4 PEG_HTX_C_GRX_P3 PEG_HTX_C_GRX_P2 PEG_HTX_C_GRX_P1 PEG_HTX_C_GRX_P0 AP25 AL25 AL24 AL22 AJ33 AG9 M27 L28 J17 H17 G25 G17 E31 E30 10 H_DIMMA_REF 11 H_DIMMB_REF R74 3.01K_0402_1% @ CFG0 R72 3.01K_0402_1% R75 3.01K_0402_1% DIS@ @ 2 CFG3 CFG4 R71 3.01K_0402_1% @ CFG7 WW41 Recommend not pull down PCIE2.0 Jitter is over on ES1 R557 0_0402_5% @ @ H_RSVD17_R H_RSVD18_R R548 0_0402_5% DMI_PTX_HRX_N[0 3] 15 DMI_PTX_HRX_P[0 3] 15 15 15 PEG_GTX_C_HRX_N[0 15] 22 PEG_GTX_C_HRX_P[0 15] 22 PEG_HTX_C_GRX_N[0 15] 22 PEG_HTX_C_GRX_P[0 15] 22 CFG[0] CFG[1] CFG[2] CFG[3] CFG[4] CFG[5] CFG[6] CFG[7] CFG[8] CFG[9] CFG[10] CFG[11] CFG[12] CFG[13] CFG[14] CFG[15] CFG[16] CFG[17] RSVD_TP_86 B19 A19 RSVD15 RSVD16 A20 B20 RSVD17 RSVD18 U9 T9 RSVD19 RSVD20 AC9 AB9 RSVD21 RSVD22 C1 A3 DMI_HTX_PRX_N[0 3] 15 DMI_HTX_PRX_P[0 3] 15 H_FDI_TXN[0 7] H_FDI_TXP[0 7] AM30 AM28 AP31 AL32 AL30 AM31 AN29 AM32 AK32 AK31 AK28 AJ28 AN30 AN32 AJ32 AJ29 AJ30 AK30 H16 RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 RSVD6 RSVD7 RSVD8 SA_DIMM_VREF SB_DIMM_VREF RSVD11 RSVD12 RSVD13 RSVD14 RSVD32 RSVD33 AJ13 AJ12 RSVD34 RSVD35 AH25 AK26 RSVD36 RSVD_NCTF_37 AL26 AR2 RSVD38 RSVD39 AJ26 AJ27 (CFD Only) (CFD Only) RESERVED JCPU1A DMI_PTX_HRX_N0 DMI_PTX_HRX_N1 DMI_PTX_HRX_N2 DMI_PTX_HRX_N3 RSVD_NCTF_40 RSVD_NCTF_41 AP1 AT2 RSVD_NCTF_42 RSVD_NCTF_43 AT3 AR1 RSVD45 RSVD46 RSVD47 RSVD48 RSVD49 RSVD50 RSVD51 RSVD52 RSVD53 RSVD_NCTF_54 RSVD_NCTF_55 RSVD_NCTF_56 RSVD_NCTF_57 RSVD58 AL28 AL29 AP30 AP32 AL27 AT31 AT32 AP33 AR33 AT33 AT34 AP35 AR35 AR32 RSVD_TP_59 RSVD_TP_60 KEY RSVD62 RSVD63 RSVD64 RSVD65 E15 F15 A2 D15 C15 AJ15 AH15 RSVD_TP_66 RSVD_TP_67 RSVD_TP_68 RSVD_TP_69 RSVD_TP_70 RSVD_TP_71 RSVD_TP_72 RSVD_TP_73 RSVD_TP_74 RSVD_TP_75 AA5 AA4 R8 AD3 AD2 AA2 AA1 R9 AG7 AE3 RSVD_TP_76 RSVD_TP_77 RSVD_TP_78 RSVD_TP_79 RSVD_TP_80 RSVD_TP_81 RSVD_TP_82 RSVD_TP_83 RSVD_TP_84 RSVD_TP_85 V4 V5 N2 AD5 AD7 W3 W2 N3 AE5 AD9 RSVD_NCTF_23 RSVD_NCTF_24 J29 J28 RSVD26 RSVD27 A34 A33 RSVD_NCTF_28 RSVD_NCTF_29 C35 B35 RSVD_NCTF_30 RSVD_NCTF_31 IC,AUB_CFD_rPGA,R1P0 CONN@ VSS D C R214 0_0402_5% RSVD64_R @ RSVD65_R @ R213 0_0402_5% 1 B AP34 IC,AUB_CFD_rPGA,R1P0 CONN@ A eDP Signals eDP Singal eDP_TX0 eDP_TX#0 eDP_TX1 eDP_TX#1 eDP_TX2 eDP_TX#2 eDP_TX3 eDP_TX#3 eDP_AUX eDP_AUX# eDP_HPD# MAPPING PEG Singals PEG_HTX_C_GRX_P15 PEG_HTX_C_GRX_N15 PEG_HTX_C_GRX_P14 PEG_HTX_C_GRX_N14 PEG_HTX_C_GRX_P13 PEG_HTX_C_GRX_N13 PEG_HTX_C_GRX_P12 PEG_HTX_C_GRX_N12 PEG_GTX_C_HRX_P13 PEG_GTX_C_HRX_N13 PEG_GTX_C_HRX_P12 Lane Reversal PEG_HTX_C_GRX_P0 PEG_HTX_C_GRX_N0 PEG_HTX_C_GRX_P1 PEG_HTX_C_GRX_N1 PEG_HTX_C_GRX_P2 PEG_HTX_C_GRX_N2 PEG_HTX_C_GRX_P3 PEG_HTX_C_GRX_N3 PEG_GTX_C_HRX_P2 PEG_GTX_C_HRX_N2 PEG_GTX_C_HRX_P3 H_FDI_FSYNC0 H_FDI_FSYNC1 R163 DIS only@ 1K_0402_5% R166 DIS only@ 1K_0402_5% H_FDI_INT R171 DIS only@ 1K_0402_5% H_FDI_LSYNC0 H_FDI_LSYNC1 R167 DIS only@ 1K_0402_5% R172 DIS only@ 1K_0402_5% CFG0 - PCI-Express Configuration Select CFG4 - Display Port Presence *1:Single PEG 0:Bifurcation enabled *1:Disabled; No Physical Display Port attached to Embedded Display Port 0:Enabled; An external Display Port device is connected to the Embedded Display Port CFG3 - PCI-Express Static Lane Reversal *:Default *1 :Normal Operation :Lane Numbers Reversed 15 -> 0, 14 -> 1, CheckList0.8 1.22 Auburndale Graphics Disable Compal Electronics, Inc Compal Secret Data Security Classification 2009/5/12 Issued Date Deciphered Date 2010/04/15 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A Title PROCESSOR (1/6) DMI,FDI,PEG Size B Date: Document Number Rev 1.0 NALG0 M/B LA-5681P Schematic Friday, October 23, 2009 Sheet of 60 JCPU1B COMP1 AT26 COMP0 AH24 SKTOCC# AK14 CATERR# H_PECI_R AT15 PECI H_PROCHOT# R211 0_0402_5% 18 H_THERMTRIP# H_CPURST# AP26 RESET_OBS# H_PM_SYNC_R AL15 PM_SYNC R215 0_0402_5% H_CPUPW RGD_1 AN14 VCCPWRGOOD_1 2 PM_DRAM_PW RGD_R R742 @ H_PW RGD_XDP R452 0_0402_5% H_CPUPW RGD_0 AN27 VCCPWRGOOD_0 PM_DRAM_PW RGD_R AK13 SM_DRAMPWROK CPU_VTTPW RGD 0_0402_5% 2 AM15 VTTPWRGOOD H_PW RGD_XDP_R AM26 TAPPWRGOOD PLT_RST#_R AL14 RSTIN# AR30 AT30 CLK_CPU_ITP_R CLK_CPU_ITP#_R R506 XDP@ R515 XDP@ 0_0402_5% 0_0402_5% PEG_CLK PEG_CLK# E16 D16 CLK_CPU_DMI_R CLK_CPU_DMI#_R R577 R571 0_0402_5% 0_0402_5% DPLL_REF_SSCLK DPLL_REF_SSCLK# A18 A17 CLK_CPU_DP_R CLK_CPU_DP#_R R563 UMA@ 0_0402_5% R568 UMA@ 0_0402_5% BCLK_ITP BCLK_ITP# SM_DRAMRST# F6 2009/2/4 #414044 DG Update Rev1.11 SM_RCOMP_0 SM_RCOMP_1 SM_RCOMP_2 PM_EXT_TS#[0] PM_EXT_TS#[1] AN15 AP15 PM_EXTTS#0 PM_EXTTS#1_R PRDY# PREQ# AT28 AP27 XDP_PRDY# XDP_PREQ# TCK TMS TRST# AN28 AP28 AT27 XDP_TCLK XDP_TMS XDP_TRST# TDI TDO TDI_M TDO_M AT29 AR27 AR29 AP29 XDP_TDI_R XDP_TDO_R XDP_TDI_M XDP_TDO_M DBR# AN25 XDP_DBR#_R BPM#[0] BPM#[1] BPM#[2] BPM#[3] BPM#[4] BPM#[5] BPM#[6] BPM#[7] AJ22 AK22 AK24 AJ24 AJ25 AH22 AK23 AH23 CLK_CPU_XDP CLK_CPU_XDP# CLK_CPU_DMI 14 CLK_CPU_DMI# 14 CLK_CPU_DP_R CLK_CPU_DP#_R CLK_CPU_DP 14 CLK_CPU_DP# 14 R561 DIS only@ 0_0402_5% R569 DIS only@ 0_0402_5% D +1.1VS_VTT R591 R586 R594 10K_0402_5% 10K_0402_5% 0_0402_5% XDP_PRDY# XDP_TMS XDP_TDI_R XDP_PREQ# XDP_TCLK R147 R38 R537 R152 R446 XDP_TRST# R145 51_0402_5% XDP_TDI_R XDP_TDO_M R525 R514 @ 0_0402_5% 0_0402_5% 1 1 @ @ @ @ @ 2 2 51_0402_5% 51_0402_5% 51_0402_5% 51_0402_5% 51_0402_5% PM_EXTTS#0_1 10,11 R151 0_0402_5% XDP_DBRESET# XDP_TDI XDP_TDO R522 0_0402_5% XDP_DBRESET# 15 XDP_TDI_M XDP_TDO_R XDP_OBS0 XDP_OBS1 XDP_OBS2 XDP_OBS3 XDP_OBS4 XDP_OBS5 XDP_OBS6 XDP_OBS7 C @ R524 R150 2 0_0402_5% 0_0402_5% JTAG MAPPING 2009/2/4 Delete dampling resistor for power noise and Layout space issue IC,AUB_CFD_rPGA,R1P0 CONN@ Scan Chain (Default) STUFF -> R653, R657, R662 NO STUFF -> R655, R660 CPU Only STUFF -> R653, R655 NO STUFF -> R657, R660, R662 GMCH Only STUFF -> R660, R662 NO STUFF -> R653, R655, R657 R182 750_0402_1% CLK_CPU_BCLK 18 CLK_CPU_BCLK# 18 SM_DRAMRST# 11 AL1 AM1 AN1 SM_RCOMP[0] SM_RCOMP[1] SM_RCOMP[2] R181 1.5K_0402_1% 17,33,37 PLT_RST# THERMTRIP# R216 0_0402_5% 15 PM_DRAM_PW RGD AK15 R212 0_0402_5% R210 0_0402_5% 18 H_CPUPW RGD H_THERMTRIP#_R PROCHOT# 0_0402_5% 0_0402_5% +1.1VS_VTT PWR MANAGEMENT 15 H_PM_SYNC AN26 CLOCKS H_CATERR# R578 R581 1 G16 H_COMP0 CLK_CPU_BCLK_R CLK_CPU_BCLK#_R H_COMP1 A16 B16 BCLK BCLK# DDR3 MISC 55 H_PROCHOT# C COMP2 THERMAL R595 0_0402_5% H_PECI AT24 SKTOCC#_R D 18 COMP3 H_COMP2 JTAG & BPM @ AT23 MISC PAD T5 H_COMP3 +3VS 2009/4/13 Intel Suggestion by Desige guide V1.52 B A Y 2K_0402_5% R747 1K_0402_1% H_VTTPW RGD XDP_PREQ# XDP_PRDY# XDP_OBS0 XDP_OBS1 NC7SZ08P5X_NL_SC70-5 U48 CPU_VTTPW RGD P Test: change R203 to 750 ohm del R217 pop R736 +1.5V +1.5V_CPU G JP5 XDP_OBS2 XDP_OBS3 R217 1.1K_0402_1% non S3@ 1 B R746 R735 1.1K_0402_1% P 2 S3@ 1.5K_0402_1% R203 3K_0402_1% non S3@ H_CATERR# H_PROCHOT# H_CPURST# A H_COMP0 H_COMP1 H_COMP2 H_COMP3 R203 A H_VTTPW RGD R204 R155 R156 @ R526 R179 R541 R544 1 1 49.9_0402_1% 68_0402_5% 68_0402_5% 2 2 C435 0.1U_0402_16V4Z @ XDP_OBS6 XDP_OBS7 2 12 XDP_SDATA 12 XDP_SCLK 49.9_0402_1% 49.9_0402_1% 20_0402_1% 20_0402_1% XDP Connector GND0 OBSFN_A0 OBSFN_A1 GND2 OBSDATA_A0 OBSDATA_A1 GND4 OBSDATA_A2 OBSDATA_A3 GND6 OBSFN_B0 OBSFN_B1 GND8 OBSDATA_B0 OBSDATA_B1 GND10 OBSDATA_B2 OBSDATA_B3 GND12 PWRGOOD/HOOK0 HOOK1 VCC_OBS_AB HOOK2 HOOK3 GND14 SDA SCL TCK1 TCK0 GND16 CONN@ 2009/5/12 Issued Date 100_0402_1% 24.9_0402_1% 130_0402_1% GND1 OBSFN_C0 OBSFN_C1 GND3 OBSDATA_C0 OBSDATA_C1 GND5 OBSDATA_C2 OBSDATA_C3 GND7 OBSFN_D0 OBSFN_D1 GND9 OBSDATA_D0 OBSDATA_D1 GND11 OBSDATA_D2 OBSDATA_D3 GND13 ITPCLK/HOOK4 ITPCLK#/HOOK5 VCC_OBS_CD RESET#/HOOK6 DBR#/HOOK7 GND15 TD0 TRST# TDI TMS GND17 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 H_RESET#_R Deciphered Date R49 1K_0402_5% XDP@ @ H_CPURST# PLT_RST# R50 0_0402_5% CLK_CPU_XDP CLK_CPU_XDP# H_RESET#_R XDP_DBRESET# XDP_TDO XDP_TRST# XDP_TDI XDP_TMS +1.1VS_VTT XDP@ XDP@ R46 1K_0402_5% R43 51_0402_5% +3VS Leakage Issue +1.1VS_VTT A SAMTE_BSH-030-01-L-D-A Compal Electronics, Inc 2010/04/15 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC B Compal Secret Data Security Classification SM_RCOMP_0 R636 SM_RCOMP_1 R632 SM_RCOMP_2 R629 H_PW RGOOD_R PBTN_OUT#_XDP 0_0402_5% H_PW RGD_XDP XDP_TCLK SD034750080 15,37 PBTN_OUT# +1.1VS_VTT R457 1K_0402_5% H_CPUPW RGD XDP@ XDP@ R455 S3@ 750_0402_1% H_VTTPW RGD 53 NC7SZ08P5X_NL_SC70-5 U46 +1.1VS_VTT @ S3@ C713 0.1U_0402_16V4Z B Y 1 R736 G PM_DRAM_PW RGD_R XDP_OBS4 XDP_OBS5 @ +3VS 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 Title PROCESSOR (2/6) CLK,JTAG Size B Date: Document Number Rev 1.0 NALG0 M/B LA-5681P Schematic Friday, October 23, 2009 Sheet of 60 B 10 10 10 DDR_A_BS0 DDR_A_BS1 DDR_A_BS2 10 DDR_A_CAS# 10 DDR_A_RAS# 10 DDR_A_W E# A10 C10 C7 A7 B10 D10 E10 A8 D8 F10 E6 F7 E9 B7 E7 C6 H10 G8 K7 J8 G7 G10 J7 J10 L7 M6 M8 L9 L6 K8 N8 P9 AH5 AF5 AK6 AK7 AF6 AG5 AJ7 AJ6 AJ10 AJ9 AL10 AK12 AK8 AL7 AK11 AL8 AN8 AM10 AR11 AL11 AM9 AN9 AT11 AP12 AM12 AN12 AM13 AT14 AT12 AL13 AR14 AP14 DDR_A_BS0 DDR_A_BS1 DDR_A_BS2 AC3 AB2 U7 DDR_A_CAS# DDR_A_RAS# DDR_A_W E# AE1 AB3 AE9 SA_CK[0] SA_CK#[0] SA_CKE[0] SA_DQ[0] SA_DQ[1] SA_DQ[2] SA_DQ[3] SA_DQ[4] SA_DQ[5] SA_DQ[6] SA_DQ[7] SA_DQ[8] SA_DQ[9] SA_DQ[10] SA_DQ[11] SA_DQ[12] SA_DQ[13] SA_DQ[14] SA_DQ[15] SA_DQ[16] SA_DQ[17] SA_DQ[18] SA_DQ[19] SA_DQ[20] SA_DQ[21] SA_DQ[22] SA_DQ[23] SA_DQ[24] SA_DQ[25] SA_DQ[26] SA_DQ[27] SA_DQ[28] SA_DQ[29] SA_DQ[30] SA_DQ[31] SA_DQ[32] SA_DQ[33] SA_DQ[34] SA_DQ[35] SA_DQ[36] SA_DQ[37] SA_DQ[38] SA_DQ[39] SA_DQ[40] SA_DQ[41] SA_DQ[42] SA_DQ[43] SA_DQ[44] SA_DQ[45] SA_DQ[46] SA_DQ[47] SA_DQ[48] SA_DQ[49] SA_DQ[50] SA_DQ[51] SA_DQ[52] SA_DQ[53] SA_DQ[54] SA_DQ[55] SA_DQ[56] SA_DQ[57] SA_DQ[58] SA_DQ[59] SA_DQ[60] SA_DQ[61] SA_DQ[62] SA_DQ[63] SA_BS[0] SA_BS[1] SA_BS[2] SA_CAS# SA_RAS# SA_WE# AA6 AA7 P7 Y6 Y5 P6 DDR_A_CLK1 10 DDR_A_CLK1# 10 DDR_A_CKE1 10 SA_CS#[0] SA_CS#[1] AE2 AE8 DDR_A_CS0# 10 DDR_A_CS1# 10 SA_ODT[0] SA_ODT[1] AD8 AF9 DDR_A_ODT0 10 DDR_A_ODT1 10 B9 D7 H7 M7 AG6 AM7 AN10 AN13 DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63 DDR_A_CLK0 10 DDR_A_CLK0# 10 DDR_A_CKE0 10 SA_CK[1] SA_CK#[1] SA_CKE[1] SA_DM[0] SA_DM[1] SA_DM[2] SA_DM[3] SA_DM[4] SA_DM[5] SA_DM[6] SA_DM[7] DDR SYSTEM MEMORY A C DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63 DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7 SA_DQS#[0] SA_DQS#[1] SA_DQS#[2] SA_DQS#[3] SA_DQS#[4] SA_DQS#[5] SA_DQS#[6] SA_DQS#[7] C9 F8 J9 N9 AH7 AK9 AP11 AT13 DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7 SA_DQS[0] SA_DQS[1] SA_DQS[2] SA_DQS[3] SA_DQS[4] SA_DQS[5] SA_DQS[6] SA_DQS[7] C8 F9 H9 M9 AH8 AK10 AN11 AR13 DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7 SA_MA[0] SA_MA[1] SA_MA[2] SA_MA[3] SA_MA[4] SA_MA[5] SA_MA[6] SA_MA[7] SA_MA[8] SA_MA[9] SA_MA[10] SA_MA[11] SA_MA[12] SA_MA[13] SA_MA[14] SA_MA[15] Y3 W1 AA8 AA3 V1 AA9 V8 T1 Y9 U6 AD4 T2 U3 AG8 T3 V9 DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15 11 11 11 DDR_B_BS0 DDR_B_BS1 DDR_B_BS2 11 DDR_B_CAS# 11 DDR_B_RAS# 11 DDR_B_W E# JCPU1D 11 DDR_B_D[0 63] 11 DDR_B_DM[0 7] 11 DDR_B_DQS#[0 7] 11 DDR_B_DQS[0 7] 11 DDR_B_MA[0 15] JCPU1C 10 DDR_A_D[0 63] 10 DDR_A_DM[0 7] 10 DDR_A_DQS#[0 7] 10 DDR_A_DQS[0 7] 10 DDR_A_MA[0 15] D B5 A5 C3 B3 E4 A6 A4 C4 D1 D2 F2 F1 C2 F5 F3 G4 H6 G2 J6 J3 G1 G5 J2 J1 J5 K2 L3 M1 K5 K4 M4 N5 AF3 AG1 AJ3 AK1 AG4 AG3 AJ4 AH4 AK3 AK4 AM6 AN2 AK5 AK2 AM4 AM3 AP3 AN5 AT4 AN6 AN4 AN3 AT5 AT6 AN7 AP6 AP8 AT9 AT7 AP9 AR10 AT10 SB_DQ[0] SB_DQ[1] SB_DQ[2] SB_DQ[3] SB_DQ[4] SB_DQ[5] SB_DQ[6] SB_DQ[7] SB_DQ[8] SB_DQ[9] SB_DQ[10] SB_DQ[11] SB_DQ[12] SB_DQ[13] SB_DQ[14] SB_DQ[15] SB_DQ[16] SB_DQ[17] SB_DQ[18] SB_DQ[19] SB_DQ[20] SB_DQ[21] SB_DQ[22] SB_DQ[23] SB_DQ[24] SB_DQ[25] SB_DQ[26] SB_DQ[27] SB_DQ[28] SB_DQ[29] SB_DQ[30] SB_DQ[31] SB_DQ[32] SB_DQ[33] SB_DQ[34] SB_DQ[35] SB_DQ[36] SB_DQ[37] SB_DQ[38] SB_DQ[39] SB_DQ[40] SB_DQ[41] SB_DQ[42] SB_DQ[43] SB_DQ[44] SB_DQ[45] SB_DQ[46] SB_DQ[47] SB_DQ[48] SB_DQ[49] SB_DQ[50] SB_DQ[51] SB_DQ[52] SB_DQ[53] SB_DQ[54] SB_DQ[55] SB_DQ[56] SB_DQ[57] SB_DQ[58] SB_DQ[59] SB_DQ[60] SB_DQ[61] SB_DQ[62] SB_DQ[63] DDR_B_BS0 DDR_B_BS1 DDR_B_BS2 AB1 W5 R7 SB_BS[0] SB_BS[1] SB_BS[2] DDR_B_CAS# DDR_B_RAS# DDR_B_W E# AC5 Y7 AC6 SB_CAS# SB_RAS# SB_WE# DDR SYSTEM MEMORY - B SB_CK[0] SB_CK#[0] SB_CKE[0] W8 W9 M3 DDR_B_CLK0 11 DDR_B_CLK0# 11 DDR_B_CKE0 11 SB_CK[1] SB_CK#[1] SB_CKE[1] V7 V6 M2 DDR_B_CLK1 11 DDR_B_CLK1# 11 DDR_B_CKE1 11 SB_CS#[0] SB_CS#[1] AB8 AD6 DDR_B_CS0# 11 DDR_B_CS1# 11 SB_ODT[0] SB_ODT[1] AC7 AD1 DDR_B_ODT0 11 DDR_B_ODT1 11 SB_DM[0] SB_DM[1] SB_DM[2] SB_DM[3] SB_DM[4] SB_DM[5] SB_DM[6] SB_DM[7] D4 E1 H3 K1 AH1 AL2 AR4 AT8 DDR_B_DM0 DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7 SB_DQS#[0] SB_DQS#[1] SB_DQS#[2] SB_DQS#[3] SB_DQS#[4] SB_DQS#[5] SB_DQS#[6] SB_DQS#[7] D5 F4 J4 L4 AH2 AL4 AR5 AR8 DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7 SB_DQS[0] SB_DQS[1] SB_DQS[2] SB_DQS[3] SB_DQS[4] SB_DQS[5] SB_DQS[6] SB_DQS[7] C5 E3 H4 M5 AG2 AL5 AP5 AR7 DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7 SB_MA[0] SB_MA[1] SB_MA[2] SB_MA[3] SB_MA[4] SB_MA[5] SB_MA[6] SB_MA[7] SB_MA[8] SB_MA[9] SB_MA[10] SB_MA[11] SB_MA[12] SB_MA[13] SB_MA[14] SB_MA[15] U5 V2 T5 V3 R1 T8 R2 R6 R4 R5 AB5 P3 R3 AF7 P5 N1 DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15 D C B IC,AUB_CFD_rPGA,R1P0 CONN@ IC,AUB_CFD_rPGA,R1P0 CONN@ A Compal Electronics, Inc Compal Secret Data Security Classification 2009/5/12 Issued Date Deciphered Date 2010/04/15 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A Title PROCESSOR (3/6) DDRIII Size B Date: Document Number Rev 1.0 NALG0 M/B LA-5681P Schematic Friday, October 23, 2009 Sheet of 60 JCPU1F WW15 MOW +CPU_CORE Peak 21A A VTT0_1 VTT0_2 VTT0_3 VTT0_4 VTT0_5 VTT0_6 VTT0_7 VTT0_8 VTT0_9 VTT0_10 VTT0_11 VTT0_12 VTT0_13 VTT0_14 VTT0_15 VTT0_16 VTT0_17 VTT0_18 VTT0_19 VTT0_20 VTT0_21 VTT0_22 VTT0_23 VTT0_24 VTT0_25 VTT0_26 VTT0_27 VTT0_28 VTT0_29 VTT0_30 VTT0_31 VTT0_32 VTT0_33 VTT0_34 VTT0_35 VTT0_36 VTT0_37 VTT0_38 VTT0_39 VTT0_40 VTT0_41 VTT0_42 VTT0_43 VTT0_44 PSI# POWER B +1.1VS_VTT 10U_0805_6.3V6M 10U_0805_6.3V6M AH14 AH12 AH11 AH10 J14 J13 H14 H12 G14 G13 G12 G11 F14 F13 F12 F11 E14 E12 D14 D13 D12 D11 C14 C13 C12 C11 B14 B12 A14 A13 A12 A11 10U_0805_6.3V6M +CPU_CORE C228 1 C209 C222 C226 10U_0805_6.3V6M C224 C212 10U_0805_6.3V6M 10U_0805_6.3V6M C204 10U_0805_6.3V6M 10U_0805_6.3V6M C185 10U_0805_6.3V6M C195 10U_0805_6.3V6M C203 C207 10U_0805_6.3V6M 10U_0805_6.3V6M C217 10U_0805_6.3V6M C196 10U_0805_6.3V6M C187 C202 10U_0805_6.3V6M C218 10U_0805_6.3V6M (Place these capacitors between inductor and socket on Bottom) +1.1VS_VTT +CPU_CORE 330U_X_2VM_R6M + C250 C248 + C249 @ 10U_0805_6.3V6M + 1 C220 C192 10U_0805_6.3V6M C221 C208 C191 C219 2 330U_X_2VM_R6M 10U_0805_6.3V6M C216 2 2 2 330U_X_2VM_R6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M (Place these capacitors under CPU socket, top layer) CSC (Current Sense Configuration) 8/25 +1.1VS_VTT VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6] PROC_DPRSLPVR VTT_SELECT C231 C232 R412 R413 @ 1K_0402_1% 1K_0402_1% CPU_VID1 R415 R416 @ 1K_0402_1% 1K_0402_1% 2 22U_0805_6.3V6M CPU_VID2 R419 R420 @ 1K_0402_1% 1K_0402_1% CPU_VID3 R422 @ R423 1K_0402_1% 1K_0402_1% CPU_VID4 R425 @ R426 1K_0402_1% 1K_0402_1% CPU_VID5 R428 R429 @ 1K_0402_1% 1K_0402_1% CPU_VID6 C502 H_PSI# AK35 AK33 AK34 AL35 AL33 AM33 AM35 AM34 CPU_VID0 55 CPU_VID1 55 CPU_VID2 55 CPU_VID3 55 CPU_VID4 55 CPU_VID5 55 CPU_VID6 55 H_DPRSLPVR 55 H_VTTVID1 R432 @ R433 1K_0402_1% 1K_0402_1% H_DPRSLPVR R435 R436 @ 1K_0402_1% 1K_0402_1% H_PSI# 1K_0402_1% 1K_0402_1% R437 @ R438 VTT_SENSE VSS_SENSE_VTT AJ34 AJ35 B15 A15 C501 C499 22U_0805_6.3V6M C498 22U_0805_6.3V6M C497 2 22U_0805_6.3V6M (Place these capacitors on CPU cavity, Bottom Layer) +CPU_CORE 22U_0805_6.3V6M C524 C529 22U_0805_6.3V6M C528 C527 22U_0805_6.3V6M C526 22U_0805_6.3V6M C525 2 22U_0805_6.3V6M (Place these capacitors on CPU cavity, Bottom Layer) B VTT Rail pop 330u 6mohm p/n: SGA00001Q80 +CPU_CORE IMVP_IMON 55 VCCSENSE_R R466 VSSSENSE_R R465 C165 0_0402_5% 0_0402_5% VTT_SENSE 53 VSS_SENSE_VTT R585 x 470uF(4.5mohm@100kHz; 4.0mohm@SRF) 1 R464 VCCSENSE VSSSENSE 100_0402_1% R463 100_0402_1% +CPU_CORE VCCSENSE 55 VSSSENSE 55 + C171 330U_X_2VM_R6M + C172 470U_D2T_2VM~D + C173 470U_D2T_2VM~D + C170 @ 470U_D2T_2VM~D + C174 @ 470U_D2T_2VM~D 470U_D2T_2VM~D 0_0402_5% 2009/5/12 Issued Date C,uF ESR, mohm 4X330uF 6m ohm/4 16X22uF 3m ohm/12 16X10uF 3m ohm/16 Stuffing Option 4X330uF A Compal Electronics, Inc Compal Secret Data Security Classification 2010/04/15 Deciphered Date Title PROCESSOR (4/6) PWR,Bypass THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC NALG0 M/B LA-5681P Schematic Date: + TOP side (under inductor) +CPU-CORE Decoupling SPCAP,Polymer IC,AUB_CFD_rPGA,R1P0 CONN@ 22U_0805_6.3V6M Auburndale +1.1VS_VTT=1.05V Clarksfield +1.1VS_VTT=1.1V VCC_SENSE VSS_SENSE C500 22U_0805_6.3V6M 55 H_VTTVID1 = high, 1.05V AN35 22U_0805_6.3V6M H_VTTVID1 53 H_VTTVID1 = low, 1.1V ISENSE C +CPU_CORE 22U_0805_6.3V6M AN33 G15 CPU_VID0 22U_0805_6.3V6M AF10 AE10 AC10 AB10 Y10 W10 U10 T10 J12 J11 J16 J15 MLCC 0805 X5R D +1.1VS_VTT CPU VIDS C VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCC18 VCC19 VCC20 VCC21 VCC22 VCC23 VCC24 VCC25 VCC26 VCC27 VCC28 VCC29 VCC30 VCC31 VCC32 VCC33 VCC34 VCC35 VCC36 VCC37 VCC38 VCC39 VCC40 VCC41 VCC42 VCC43 VCC44 VCC45 VCC46 VCC47 VCC48 VCC49 VCC50 VCC51 VCC52 VCC53 VCC54 VCC55 VCC56 VCC57 VCC58 VCC59 VCC60 VCC61 VCC62 VCC63 VCC64 VCC65 VCC66 VCC67 VCC68 VCC69 VCC70 VCC71 VCC72 VCC73 VCC74 VCC75 VCC76 VCC77 VCC78 VCC79 VCC80 VCC81 VCC82 VCC83 VCC84 VCC85 VCC86 VCC87 VCC88 VCC89 VCC90 VCC91 VCC92 VCC93 VCC94 VCC95 VCC96 VCC97 VCC98 VCC99 VCC100 SENSE LINES D CPU CORE SUPPLY AG35 AG34 AG33 AG32 AG31 AG30 AG29 AG28 AG27 AG26 AF35 AF34 AF33 AF32 AF31 AF30 AF29 AF28 AF27 AF26 AD35 AD34 AD33 AD32 AD31 AD30 AD29 AD28 AD27 AD26 AC35 AC34 AC33 AC32 AC31 AC30 AC29 AC28 AC27 AC26 AA35 AA34 AA33 AA32 AA31 AA30 AA29 AA28 AA27 AA26 Y35 Y34 Y33 Y32 Y31 Y30 Y29 Y28 Y27 Y26 V35 V34 V33 V32 V31 V30 V29 V28 V27 V26 U35 U34 U33 U32 U31 U30 U29 U28 U27 U26 R35 R34 R33 R32 R31 R30 R29 R28 R27 R26 P35 P34 P33 P32 P31 P30 P29 P28 P27 P26 Continuous 18A 1.1V RAIL POWER 48A Friday, October 23, 2009 Sheet of 60 Rev 1.0 2 +1.5V_CPU JCPU1G UMA@ C198 UMA@ C507 UMA@ C523 UMA@ + + R549 0_0402_5% DIS only@ C206 @ 330U_X_2VM_R6M C205 330U_X_2VM_R6M UMA@ C J24 J23 H25 VTT1_45 VTT1_46 VTT1_47 15A 3A +1.1VS_VTT 22U_0805_6.3V6M 2 C234 FDI C233 1 +1.5VS JUMP_43X118 GRAPHICS 1 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 10U_0805_6.3V6M VAXG1 VAXG2 VAXG3 VAXG4 VAXG5 VAXG6 VAXG7 VAXG8 VAXG9 VAXG10 VAXG11 VAXG12 VAXG13 VAXG14 VAXG15 VAXG16 VAXG17 VAXG18 VAXG19 VAXG20 VAXG21 VAXG22 VAXG23 VAXG24 VAXG25 VAXG26 VAXG27 VAXG28 VAXG29 VAXG30 VAXG31 VAXG32 VAXG33 VAXG34 VAXG35 VAXG36 VAXG_SENSE VSSAXG_SENSE AR22 AT22 VCC_AXG_SENSE 54 VSS_AXG_SENSE 54 GFX_VID[0] GFX_VID[1] GFX_VID[2] GFX_VID[3] GFX_VID[4] GFX_VID[5] GFX_VID[6] AM22 AP22 AN22 AP23 AM23 AP24 AN24 GFX_VR_EN GFX_DPRSLPVR GFX_IMON AR25 AT25 AM24 - 1.5V RAILS C213 DDR3 C214 @ SENSE LINES C215 @ AT21 AT19 AT18 AT16 AR21 AR19 AR18 AR16 AP21 AP19 AP18 AP16 AN21 AN19 AN18 AN16 AM21 AM19 AM18 AM16 AL21 AL19 AL18 AL16 AK21 AK19 AK18 AK16 AJ21 AJ19 AJ18 AJ16 AH21 AH19 AH18 AH16 GRAPHICS VIDs C199 @ 10U_0805_6.3V6M POWER C200 @ D 22U_0805_6.3V6M 22U_0805_6.3V6M @ JUMP_43X118 PJ28 @ 2 1 +VGFX_CORE 22U_0805_6.3V6M PJ27 22U_0805_6.3V6M VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15 VDDQ16 VDDQ17 VDDQ18 AJ1 AF1 AE7 AE4 AC1 AB7 AB4 Y1 W7 W4 U1 T7 T4 P1 N7 N4 L1 H1 VTT0_59 VTT0_60 VTT0_61 VTT0_62 P10 N10 L10 K10 GFXVR_VID_0 GFXVR_VID_1 GFXVR_VID_2 GFXVR_VID_3 GFXVR_VID_4 GFXVR_VID_5 GFXVR_VID_6 GFXVR_DPRSLPVR_R R536 PJ29 @ D +1.5V JUMP_43X118 54 54 54 54 54 54 54 PJ30 @ 1 JUMP_43X118 @ R739 4.7K_0402_5% GFXVR_EN 54 GFXVR_DPRSLPVR 54 GFXVR_IMON 54 0_0402_5% DIS only@2 R146 1K_0402_5% 1U_0402_6.3V4Z 1U_0402_6.3V4Z +1.5V_CPU 22U_0805_6.3V6M C252 C259 C253 1U_0402_6.3V4Z C251 2 1U_0402_6.3V4Z C262 C271 C258 + C269 330U_X_2VM_R6M 1U_0402_6.3V4Z 22U_0805_6.3V6M C +1.1VS_VTT +1.1VS_VTT C235 10U_0805_6.3V6M 2 B C238 22U_0805_6.3V6M VTT1_63 VTT1_64 VTT1_65 VTT1_66 VTT1_67 VTT1_68 J22 J20 J18 H21 H20 H19 VCCPLL1 VCCPLL2 VCCPLL3 L26 L27 M26 C236 22U_0805_6.3V6M B +1.8VS 0.6A 1.8V 22U_0805_6.3V6M VTT1_48 VTT1_49 VTT1_50 VTT1_51 VTT1_52 VTT1_53 VTT1_54 VTT1_55 VTT1_56 VTT1_57 VTT1_58 PEG & DMI C237 K26 J27 J26 J25 H27 G28 G27 G26 F26 E26 E25 1.1V +1.1VS_VTT 2.2U_0603_6.3V6K +1.8VS_VCCSFR C189 1U_0402_6.3V4Z IC,AUB_CFD_rPGA,R1P0 CONN@ C186 C197 2 1U_0402_6.3V4Z C193 R157 1 2 22U_0805_6.3V6M 0_0805_5% C194 4.7U_0805_10V4Z A A Compal Electronics, Inc Compal Secret Data Security Classification 2009/5/12 Issued Date Deciphered Date 2010/04/15 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title PROCESSOR (5/6) PWR Size Document Number Custom Rev 1.0 NALG0 M/B LA-5681P Schematic Date: Friday, October 23, 2009 Sheet of 60 D C B VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 JCPU1I VSS VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98 VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160 AE34 AE33 AE32 AE31 AE30 AE29 AE28 AE27 AE26 AE6 AD10 AC8 AC4 AC2 AB35 AB34 AB33 AB32 AB31 AB30 AB29 AB28 AB27 AB26 AB6 AA10 Y8 Y4 Y2 W35 W34 W33 W32 W31 W30 W29 W28 W27 W26 W6 V10 U8 U4 U2 T35 T34 T33 T32 T31 T30 T29 T28 T27 T26 T6 R10 P8 P4 P2 N35 N34 N33 N32 N31 N30 N29 N28 N27 N26 N6 M10 L35 L32 L29 L8 L5 L2 K34 K33 K30 K27 K9 K6 K3 J32 J30 J21 J19 H35 H32 H28 H26 H24 H22 H18 H15 H13 H11 H8 H5 H2 G34 G31 G20 G9 G6 G3 F30 F27 F25 F22 F19 F16 E35 E32 E29 E24 E21 E18 E13 E11 E8 E5 E2 D33 D30 D26 D9 D6 D3 C34 C32 C29 C28 C24 C22 C20 C19 C16 B31 B25 B21 B18 B17 B13 B11 B8 B6 B4 A29 A27 A23 A9 IC,AUB_CFD_rPGA,R1P0 CONN@ VSS161 VSS162 VSS163 VSS164 VSS165 VSS166 VSS167 VSS168 VSS169 VSS170 VSS171 VSS172 VSS173 VSS174 VSS175 VSS176 VSS177 VSS178 VSS179 VSS180 VSS181 VSS182 VSS183 VSS184 VSS185 VSS186 VSS187 VSS188 VSS189 VSS190 VSS191 VSS192 VSS193 VSS194 VSS195 VSS196 VSS197 VSS198 VSS199 VSS200 VSS201 VSS202 VSS203 VSS204 VSS205 VSS206 VSS207 VSS208 VSS209 VSS210 VSS211 VSS212 VSS213 VSS214 VSS215 VSS216 VSS217 VSS218 VSS219 VSS220 VSS221 VSS222 VSS223 VSS224 VSS225 VSS226 VSS227 VSS228 VSS229 VSS230 VSS231 VSS232 VSS233 D C VSS NCTF JCPU1H AT20 AT17 AR31 AR28 AR26 AR24 AR23 AR20 AR17 AR15 AR12 AR9 AR6 AR3 AP20 AP17 AP13 AP10 AP7 AP4 AP2 AN34 AN31 AN23 AN20 AN17 AM29 AM27 AM25 AM20 AM17 AM14 AM11 AM8 AM5 AM2 AL34 AL31 AL23 AL20 AL17 AL12 AL9 AL6 AL3 AK29 AK27 AK25 AK20 AK17 AJ31 AJ23 AJ20 AJ17 AJ14 AJ11 AJ8 AJ5 AJ2 AH35 AH34 AH33 AH32 AH31 AH30 AH29 AH28 AH27 AH26 AH20 AH17 AH13 AH9 AH6 AH3 AG10 AF8 AF4 AF2 AE35 VSS_NCTF1 VSS_NCTF2 VSS_NCTF3 VSS_NCTF4 VSS_NCTF5 VSS_NCTF6 VSS_NCTF7 AT35 AT1 AR34 B34 B2 B1 A35 H_NCTF1 H_NCTF2 @ @ PAD T14 PAD T19 H_NCTF6 H_NCTF7 @ @ PAD T18 PAD T13 B IC,AUB_CFD_rPGA,R1P0 CONN@ A A Compal Electronics, Inc Compal Secret Data Security Classification 2009/5/12 Issued Date Deciphered Date 2010/04/15 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title PROCESSOR (6/6) VSS Size Document Number Custom Rev 1.0 NALG0 M/B LA-5681P Schematic Date: Friday, October 23, 2009 Sheet of 60 +1.5V JDIMM1 DDR_A_DQS#[0 7] +1.5V H_DIMMA_REF H_DIMMA_REF R324 @ VREF_DQA 0_0402_5% DDR_A_D[0 63] DDR_A_D0 DDR_A_D1 DDR_A_DM[0 7] R312 R325 +V_DDR3_DIMM_REF 2 0_0402_5% DDR_A_DM0 DDR_A_DQS[0 7] +V_DDR3_DIMM_REF 1K_0402_1% DDR_A_D2 DDR_A_D3 DDR_A_MA[0 15] +V_DDR3_DIMM_REF +1.5V DDR_A_D8 DDR_A_D9 R319 D C322 1K_0402_1% 0.1U_0402_16V4Z 1 2 DDR_A_DQS#1 DDR_A_DQS1 C321 2.2U_0805_16V4Z DDR_A_D10 DDR_A_D11 DDR_A_D16 DDR_A_D17 DDR_A_DQS#2 DDR_A_DQS2 DDR_A_D18 DDR_A_D19 DDR_A_D24 DDR_A_D25 VREF_DQA DDR_A_DM3 G DDR_A_D26 DDR_A_D27 +V_DDR3_DIMM_REF R738 100K_0402_5% D @ H_DIMMA_REF S @ Q64 BSS138_NL_SOT23-3 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 VREF_DQ VSS DQ0 DQ1 VSS DM0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS DQ10 DQ11 VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 VSS DQ26 DQ27 VSS 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203 CKE0 VDD NC BA2 VDD A12/BC# A9 VDD A8 A5 VDD A3 A1 VDD CK0 CK0# VDD A10/AP BA0 VDD WE# CAS# VDD A13 S1# VDD TEST VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SA0 VDDSPD SA1 VTT VSS DQ4 DQ5 VSS DQS0# DQS0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 RESET# VSS DQ14 DQ15 VSS DQ20 DQ21 VSS DM2 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DQS3# DQS3 VSS DQ30 DQ31 VSS 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 DDR_A_D4 DDR_A_D5 DDR_A_DQS#0 DDR_A_DQS0 DDR_A_D6 DDR_A_D7 DDR_A_D12 DDR_A_D13 D DDR_A_DM1 DIMM_RST# DIMM_RST# 11 DDR_A_D14 DDR_A_D15 DDR_A_D20 DDR_A_D21 DDR_A_DM2 DDR_A_D22 DDR_A_D23 DDR_A_D28 DDR_A_D29 DDR_A_DQS#3 DDR_A_DQS3 DDR_A_D30 DDR_A_D31 @ C R725 DDR_A_CKE0 DDR_A_BS2 DDR_A_CKE0 R323 DDR_A_BS2 DDR_A_MA12 DDR_A_MA9 +DDR_VREF_CA DDR_A_MA8 DDR_A_MA5 1K_0402_1% DDR_VREF_CA_DIMMA R726 DDR_A_MA3 DDR_A_MA1 0_0402_5% R496 6 DDR_A_CLK0 DDR_A_CLK0# 1K_0402_1% DDR_A_CLK0 DDR_A_CLK0# 6 6 DDR_A_MA10 DDR_A_BS0 DDR_A_BS0 DDR_A_WE# DDR_A_CAS# DDR_A_WE# DDR_A_CAS# DDR_A_MA13 DDR_A_CS1# DDR_A_CS1# DDR_A_D32 DDR_A_D33 Layout Note: Place near JDIMM1 DDR_A_DQS#4 DDR_A_DQS4 DDR_A_D34 DDR_A_D35 Layout Note: Place these Caps near Command and Control signals of DIMMA DDR_A_D40 DDR_A_D41 B +1.5V DDR_A_DM5 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 0.1U_0402_16V4Z 0.1U_0402_16V4Z DDR_A_D42 DDR_A_D43 C309 C310 C285 10U_0805_6.3V6M C290 C295 10U_0805_6.3V6M C311 10U_0805_6.3V6M 1 2 C326 0.1U_0402_16V4Z C325 C323 C324 + DDR_A_D48 DDR_A_D49 C300 330U_X_2VM_R6M DDR_A_DQS#6 DDR_A_DQS6 DDR_A_D50 DDR_A_D51 0.1U_0402_16V4Z DDR_A_D56 DDR_A_D57 DDR_A_DM7 DDR_A_D58 DDR_A_D59 Layout Note: Place near JDIMM1.203 & JDIMM1.204 R335 10K_0402_5% +0.75VS C344 2.2U_0603_6.3V4Z 1U_0603_10V4Z 1U_0603_10V4Z 1 2 C345 +3VS R332 0.1U_0402_16V4Z 205 207 C624 2 1 C629 C625 C680 BOSS1 BOSS2 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 DDR_A_CKE1 DDR_A_CKE1 DDR_A_MA15 DDR_A_MA14 DDR_A_MA11 DDR_A_MA7 C DDR_A_MA6 DDR_A_MA4 DDR_A_MA2 DDR_A_MA0 DDR_A_CLK1 DDR_A_CLK1# DDR_A_CLK1 DDR_A_CLK1# DDR_A_BS1 DDR_A_RAS# DDR_A_BS1 DDR_A_RAS# DDR_A_CS0# DDR_A_ODT0 DDR_A_CS0# DDR_A_ODT0 DDR_A_ODT1 DDR_A_ODT1 +DDR_VREF_CA DDR_A_D36 DDR_A_D37 DDR_A_DM4 DDR_A_D38 DDR_A_D39 C318 DDR_A_D44 DDR_A_D45 1 2 C317 0.1U_0402_16V4Z B DDR_A_DQS#5 DDR_A_DQS5 DDR_A_D46 DDR_A_D47 DDR_A_D52 DDR_A_D53 DDR_A_DM6 DDR_A_D54 DDR_A_D55 DDR_A_D60 DDR_A_D61 DDR_A_DQS#7 DDR_A_DQS7 DDR_A_D62 DDR_A_D63 PM_EXTTS#0_1 D_CK_SDATA D_CK_SCLK PM_EXTTS#0_1 5,11 D_CK_SDATA 11,12 D_CK_SCLK 11,12 +0.75VS 206 208 DDR3 SO-DIMM A Standard Type FOX_AS0A626-U2SN-7F_204P C291 CONN@ A 10U_0805_6.3V6M Compal Secret Data Security Classification 1U_0603_10V4Z GND1 GND2 10K_0402_5% A CKE1 VDD A15 A14 VDD A11 A7 VDD A6 A4 VDD A2 A0 VDD CK1 CK1# VDD BA1 RAS# VDD S0# ODT0 VDD ODT1 NC VDD VREF_CA VSS DQ36 DQ37 VSS DM4 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DQS5# DQS5 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS7# DQS7 VSS DQ62 DQ63 VSS EVENT# SDA SCL VTT 2.2U_0603_6.3V4Z 0_0402_5% 11,18 RST_GATE +1.5V 2009/5/12 Issued Date 1U_0603_10V4Z 2010/04/15 Deciphered Date Title Compal Electronics, Inc DDRIII-SODIMM SLOT1 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Rev 1.0 NALG0 M/B LA-5681P Schematic Date: Friday, October 23, 2009 Sheet 10 of 60 ISL6237_B+ ISL6237_B+ PR39 0_0805_5% PJ16 PHASE2 PHASE1 16 LX5 LGATE1 18 DL5 23 LGATE2 Rds(on)=15m ohm(typ) 18m ohm(max) VL 30 OUT2 32 REFIN2 PGND 22 OUT1 10 FB1 11 BYP SKIP 29 Rds(on)=15m ohm(typ) 18m ohm(max) LDOREFIN @ PR48 GND ILIM1 12 ILIM2 31 ILIM2 PR52 330K_0402_1% 2 PC27 2200P_0402_50V7K 45,46 pull high VL=5V B PR53 330K_0402_1% ISL6237IRZ-T_QFN32_5X5 PR57 0_0402_5% +5VALWP Ipeak=7A ; Imax=4.9A Choke DCRmax=40m ohm, DCRtyp=37m ohm Rds(on)=18m ohm(max) ; Rds(on)=15m ohm(typical) Vlimit=(5E-06 * 330K)/10=165mV Ilimit=165mV/18m ~ 165mV/15m =9.167A ~ 11A Iocp=Ilimit+Delta I/2 =10.147A ~ 11.980A Delta I=1.96A (Freq=400KHz) PC40 1U_0603_10V6K 2VREF_ISL6237 VL SPOK ILM1 21 EN2 27 TON 13 1 POK1 0_0402_5% 0_0402_5% @ PC42 0.047U_0402_16V7K PQ13 TP0610K-T1-E3_SOT23-3 A A EN_LDO EN1 PR55 0_0402_5% 2 @ PR59 47K_0402_5% PC41 0.047U_0402_16V7K 18,46,49 MAINPWON 28 14 @ PR54 0_0402_5% PR56 806K_0603_1% POK2 2VREF_ISL6237 PC39 0.22U_0603_25V7K NC 1 PR51 200K_0402_5% PR58 0_0402_5% PC26 4.7U_1206_25V6K REF NC 20 PR50 100K_0402_1% VL + PC37 C 150U_D2E_6.3VM_R18 FB5 PR49 PD15 1SS355_SOD323-2 0.22U_0603_10V7K PD6 GLZ5.1B_LL34-2 2 PQ12 AO4712_SO8 25 DL3 PC38 B PR44 2.2_0603_5% BST5A PR45 63.4K_0402_1% 17 PR47 10K_0402_1% BOOT1 DCR=37m ohm(typ) 40m ohm(max) PR42 4.7_1206_5% BOOT2 DH5 PL4 4.7UH_PCMC063T-4R7MN_5.5A_20% PC36 680P_0402_50V7K 15 2VREF_ISL6237 +3.3VALWP Ipeak=7A ; Imax=4.9A Choke DCRmax=40m ohm, DCRtyp=37m ohm Rds(on)=18m ohm(max) ; Rds(on)=15m ohm(typical) Vlimit=(5E-06 * 330K)/10=165mV Ilimit=165mV/18m ~ 165mV/15m =9.167A ~ 11A VS Iocp=Ilimit+Delta I/2 =10.134A ~ 11.967A Delta I=1.934A (Freq=300KHz) UGATE1 LDO UGATE2 PC31 1U_0603_10V6K PC34 0.1U_0603_25V7K LX3 FB3 @ PR46 10K_0402_1% PC30 4.7U_0603_6.3V6M PC29 1U_0603_10V6K VCC 24 19 PC33 0.1U_0603_25V7K PC35 680P_0402_50V7K PVCC 1 2 C PR43 BST3A 2.2_0603_5% 26 +5VALWP PQ11 AO4712_SO8 PR40 0_0402_5% + PC32 330U_D2E_6.3VM_R25M DH3 TP PQ10 AO4466_SO8 PR41 4.7_1206_5% 1 PU4 33 VIN PL3 4.7UH_PCMC063T-4R7MN_5.5A_20% +3VALWP 2 DCR=37m ohm(typ) 40m ohm(max) PC28 0.1U_0603_25V7K PQ9 AO4466_SO8 @ PC22 4.7U_1206_25V6K PC21 2200P_0402_50V7K @ VL PC25 4.7U_1206_25V6K D PC24 2200P_0402_50V7K 1 PC23 4.7U_1206_25V6K 2 JUMP_43X118 PC20 2200P_0402_50V7K D B+ Compal Electronics, Inc Compal Secret Data Security Classification 2007/09/20 Issued Date Deciphered Date 2008/09/20 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title +5VALWP/+3VALWP Size Document Number Custom Date: Rev 0.1 NALG0 Friday, October 23, 2009 Sheet 47 of 60 A B Iada=0~4.74A(90W/19V=4.736A) Iada=0~3.42A(90W/19V=3.421A) P2 B+ P3 PQ15 AO4407A_SO8 CHG_B+ B+ PR60 0.02_2512_1% PQ16 AO4407A_SO8 PJ17 23 EN CSON 22 CELLS CSOP 21 ICOMP CSIN 20 VCOMP CSIP 19 ICM PHASE 18 PR72 20_0402_5% PC53 0.047U_0402_16V7K PR73 20_0402_5% PR74 PC56 20_0402_5% 0.1U_0603_25V7K PR76 2_0402_5% LX_CHG PR77 100_0402_1% VREF UGATE 17 DH_CHG CHLIM BOOT 16 ACLIM VDDP 15 VADJ LGATE 14 GND PGND 13 CP mode Iinput=(1/0.02)(0.05*Vaclm/2.39+0.05) where Vaclm=1.502V, Iinput=4.07A 37 65W/90W# D 3 PQ29 G S 12 PR86 4.7_0603_5% PC64 4.7U_0603_6.3V6M 2N7002W -T/R7_SOT323-3 Per cell=3.5V Vcell = (0.175 * Vadj) + 3.99 4.35V 37 BATT_OVP PR91 499K_0402_1% + - Normal 3S LI-ON Cells 12600mV PC66 0.01U_0402_25V7K PR93 105K_0402_1% CV mode 1 4.20V PU1B LM358DT_SO8 1.899V PR92 10K_0402_1% P 3.3V Pre Cell G CALIBRATE# PR89 340K_0402_1% BATT-OVP=0.1112*VMB 1 IREF=0.7224*Icharge VS LI-3S :13.5V BATT-OVP=1.5012V PC65 0.01U_0402_25V7K PR88 15.4K_0402_1% VMB 0826 PR88 18.2K change to 15.4K CALIBRATE# = 1.899V Kv=9.451 PR90 31.6K_0402_1% Charging Voltage (0x15) @ ISL6251AHAZ-T_QSOP24 CC=0.6~4.48A BATT Type 2 RB751V-40_SOD323-2 26251VDD 6251VDDP DL_CHG 12.60V Issued Date Compal Electronics, Inc Compal Secret Data Security Classification - 2007/09/20 Deciphered Date 2008/09/20 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A BATT+ PR78 0.02_1206_1% PQ27 @ AO4466_SO8 11 CHG 37 CALIBRATE# IREF=0.43V~3.24V PL5 10UH_PCMB104T-100MS_6A_20% 10 TCR=50ppm / C PC59 0.1U_0603_25V7K BST_CHGA PD12 6251aclim 20K_0402_1% PR87 11.5K_0402_1% PACIN 2N7002W -T/R7_SOT323-3 G S PR84 6251VREF PQ23D 0.1U_0402_16V7K PR82 0_0603_5% BST_CHG PQ25 AO4466_SO8 6251VREF PC58 PR85 2.37K_0402_1% PR83 100K_0402_1% CSOP IREF ADP_I 1 37 CSON 2 10K_0402_1% PC57 @ 100P_0402_50V8J PR81 80.6K_0402_1% PC63 10U_1206_25V6M ACSET ACPRN PC62 10U_1206_25V6M 2 24 VIN PD11 PR80 4.7_1206_5% DCIN ACOFF 1SS355_SOD323-2 PR67 200K_0402_1% 1SS355_SOD323-2 VDD PD8 PC61 680P_0402_50V7K DCIN wrong Value PC50 0.1U_0603_25V7K 2 37 PR79 22K_0402_5% ACOFF PR75 PC55 0.01U_0402_25V7K PC60 0.01U_0402_25V7K PACIN PQ20 PDTC115EU_SOT323 VIN FSTCHG 37 SUSP# 37,39,43,50 6251_EN 6800P_0402_25V7K S ACON PQ28 PDTC115EU_SOT323 ACOFF 2N7002W -T/R7_SOT323-3 PACIN D SUSP# 1 PC54 FSTCHG PR61 47K_0402_1% 1 PU5 3S/4S# PR65 10K_0402_1% BAS40CW _SOT323-3 PC49 2.2U_0603_6.3V6K 1 2 100K_0402_1% S ACON 37,49 37 PQ26 G 45,49 2 PQ24 PDTC115EU_SOT323 49 PR66 D 2N7002W -T/R7_SOT323-3 PQ22 G PC51 0.1U_0402_16V7K PR70 47K_0402_5% 100K_0402_1% 1 PR69 150K_0402_1% PR68 10K_0402_5% FSTCHG PQ18 PDTC115EU_SOT323 PD9 PR71 37 6251VDD DCIN PD10 1SS355_SOD323-2 6251VDD 47K PQ21 PDTC115EU_SOT323 P3 PR64 100K_0402_1% 1 PC48 0.1U_0603_25V7K 2 PR63 200K_0402_1% PQ17 TP0610K-T1-E3_SOT23-3 PQ19 PDTA144EU_SOT323-3 47K CSIP PC43 5600P_0402_25V7K 4 PR62 47K_0402_1% CSIN JUMP_43X118 1 3 PC52 0.1U_0603_25V7K 2 1 PC47 2200P_0402_25V7K PC46 0.1U_0603_25V7K 1 1 PC45 10U_1206_25V6M PC44 10U_1206_25V6M VIN D CP = 85%*Iada ; CP = 4.07A CP = 85%*Iada ; CP = 2.91A ADP_I = 19.9*Iadapter*Rsense PQ14 AO4407A_SO8 C B C CHARGER Rev 0.1 NALG0 Friday, October 23, 2009 D Sheet 48 of 60 VS P + G PU6A D - O D LM393DG_SO8 B+ PR95 2.2M_0402_5% PR94 1K_1206_5% 2 1 PR102 PR105 100K_0402_5% 1 2 C PQ31 PDTC115EU_SOT323 PR107 47K_0402_5% 2 2N7002W -T/R7_SOT323-3 G 37,48 ACOFF PQ33 PDTC115EU_SOT323 PACIN 45,48 PQ32D B+ 1 PR106 34K_0402_1% PC69 0.01U_0402_25V7K PR104 499K_0402_1% 2 PR103 191K_0402_1% PRG++ LM393DG_SO8 PC67 0.1U_0603_25V7K RTCVREF 32.4 - O 2 BAS40CW _SOT323-3 PC68 1000P_0402_50V7K P ACON + G 48 PR100 1K_1206_5% PU6B PR99 1K_1206_5% PD14 LL4148_LL34-2 18,46,47 MAINPWON TP0610K-T1-E3_SOT23-3 PQ30 PR97 1K_1206_5% PD13 100K_0402_5% VS PR98 100K_0402_1% C VIN PR96 499K_0402_1% 100K_0402_5% PR101 VL S PQ57 PDTC115EU_SOT323 @ PR108 66.5K_0402_1% +5VALW 3 ACIN B Precharge detector Min typ Max H >L 14.589V 14.84V 15.243V L >H 15.562V 15.97V 16.388V B BATT ONLY Precharge detector Min typ Max H >L 6.138V 6.214V 6.359V L >H 7.196V 7.349V 7.505V A A 2007/09/20 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification Deciphered Date 2008/09/20 Title PRECHARGE THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: Rev 0.1 NALG0 Friday, October 23, 2009 Sheet 49 of 60 B+ 1 PC71 4.7U_0805_25V6-K @ PC76 4.7U_0805_10V6K Rds(on)=15m ohm(typ) 18m ohm(max) +1.5V GND EN/SYNC SW IN SW IN POK PC79 4.7U_0603_6.3V6M NC REFEN NC VOUT NC PR119 1K_0402_1% GND PR120 change to 12.4K PC82 0.1U_0402_16V7K PR121 2N7002W -T/R7_SOT323-3 S 1K_0402_1% +0.75VSP 1 D 39,43 SUSP PQ60 G PC81 0.1U_0402_16V7K MP2121DQ-LF-Z_QFN10_3X3 PR120 12.4K_0402_1% 2 B340A_SMA2 B @ PD16 11 TP BS PC124 10U_0805_10V4Z PC123 10U_0805_10V4Z B PC80 1U_0402_6.3V6K APL5336KAI-TRL SO8 +5VALW +3VALW VS_ON 39,51,53 @ PC73 0.1U_0402_16V7K VCNTL GND 2 2 10 GND VIN 2 FB PU8 1 SUSP# 37,39,43,48 1U_0402_16V7K PC127 PJ19 JUMP_43X79 PU17 @ PR111 0_0402_5% 1 +1.8VSP PR110 0_0402_5% @ PR171 0_0402_5% PR173 402K_0402_1% JUMP_43X118 1.8V_EN PR174 316K_0402_1% VFB=0.8V LX_1.8V-1 1 PR113 47K_0402_5% 2 @ C Cesr=15m ohm Ipeak=3.98A Imax=2.786A Delta I=((19-1.8)*(1.8/19))/(L*Freq)=2.469A Vtrip=Rtrip*10uA=0.0768V Iocp-min=Vtrip/(Rds(on)(max)*1.2)+Delta I / = 4.79A Iocp-max=Vtrip/(Rds(on)(typ)*1.2)+Delta I / = 5.5A Iocp=4.79~5.5A @ PJ33 PC219 22U_0805_6.3V6M VFB=0.75V Vo=VFB*(1+PR117/PR118)=1.8V Ton=19E-12*Ron*(((2/3)*Vo+100mV)/Vin)+50ns=4.14E-7 Freq=282KHz @ @ PR118 41.2K_0402_1% PC218 22U_0805_6.3V6M @ PC75 680P_0603_50V8J VFB=0.75V PC74 330U_6.3V_M + RT8209BGQW _W QFN14_3P5X3P5 LG_1.8V @ PR114 4.7_1206_5% @ PQ59 AO4712_SO8 LGATE +5VALW VDDP 10 0_0603_5% @ 11 CS @ PR170 LX_1.8V +1.8VSP 12 PHASE PL6 2.2UH_MSCDRI-74A-2R2M-E_6.5A_20% LX_1.8V-1 0.1U_0603_25V7K @ PR117 59K_0402_1% C @ 14 NC PGND FB UG_1.8V PC72 VDD UGATE 13 @ BST_1.8V-1 PR112 0_0603_5% BOOT VOUT @ PC78 47P_0402_50V8J DCR=18m ohm(typ) 20m ohm(max) @ @ PC77 4.7U_0603_6.3V6K 15 TON open-drain PGOOD Layout Note: Place near V5FILT Pin EN/DEM GND @ PR115 100_0603_1% @ D BST_1.8V @ PU7 JUMP_43X118 1.8V_EN +5VALW PR109 280K_0402_1% @ @ PQ58 AO4466_SO8 PR116 7.68K_0402_1% D EN_PSV GND=>Disable SMPS FLOAT=>PWM_only mode HIGH=>Auto_skip mode PC70 4.7U_0805_25V6-K @ PJ18 51117_1.8V_B+ PC83 10U_0805_6.3V6M PC127 change to SE076104K80 A A 2007/09/20 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification Deciphered Date 2008/09/20 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: +1.8VSP/+0.75VSP Rev 0.1 NALG0 Friday, October 23, 2009 Sheet 50 of 60 A B C D B+ PC85 4.7U_0805_25V6-K 1 RT8209BGQW _W QFN14_3P5X3P5 PC90 4.7U_0805_10V6K + PR297 11K_0402_1% LG_1.5V PC88 330U_D2E_2.5VM VFB=0.75V Vo=VFB*(1+PR298/PR299)=1.52V Ton=19E-12*Ron*(((2/3)*Vo+100mV)/Vin)+50ns=3.8E-7 Freq=282KHz(min) , 300KHz(typ) @ PC89 680P_0603_50V8J NC PGND LGATE @ PR295 4.7_1206_5% PQ62 AO4456_SO8 VDDP 10 +5VALW +1.5VP LX_1.5V 11 Cesr=15m ohm Ipeak=15.58A Imax=10.906A Delta I=((19-1.5)*(1.5/19))/(L*Freq)=4.61A Vtrip=Rtrip*10uA=0.11V Iocp-min=Vtrip/(Rds(on)(max)*1.2)+Delta I / 2= 18.674A Iocp-max=Vtrip/(Rds(on)(typ)*1.2)+Delta I / 2=22.675A Iocp=18.674~22.675A Rds=4.5mΩ(Typ) 5.6mΩ(Max) VFB=0.75V PR298 59K_0402_1% 12 CS PHASE 0.1U_0603_25V7K PC91 4.7U_0603_6.3V6K @ PC92 47P_0402_50V8J Layout Note: Place near V5FILT Pin open-drain PGOOD +5VALW FB GND PR296 100_0603_1% VDD UGATE UG_1.5V PL7 1UH_PCMB103T-1R0MS_13A_20% PC86 VOUT BOOT TON 13 2 PR125 0_0603_5% 2BST_1.5V-1 14 EN/DEM @ PC87 0.1U_0402_16V7K @ PR124 47K_0402_5% 15 BST_1.5V PU9 37,43 SYSON JUMP_43X118 1.5V_EN PR123 0_0402_5% 2 PR122 280K_0402_1% 2 PQ61 AO4466_SO8 51117_1.5V_B+ PC84 4.7U_0805_25V6-K @ PJ20 EN_PSV GND=>Disable SMPS FLOAT=>PWM_only mode HIGH=>Auto_skip mode 2 PR299 57.6K_0402_1% B+ PR300 280K_0402_1% LX_1.05V 11 VDDP 10 RT8209BGQW _W QFN14_3P5X3P5 @ PR307 23.7K_0402_1% PR308 24K_0402_1% 2 + PR306 7.32K_0402_1% PGND LG_1.05V PC99 4.7U_0805_10V6K PC97 330U_D2E_2.5VM @ PC98 680P_0603_50V8J VFB=0.75V Vo=VFB*(1+PR308/PR309)=1.05V Ton=19E-12*Ron*(((2/3)*Vo+100mV)/Vin)+50ns=2.74E-07 Freq=282KHz , 300KHz(typ) Cesr=15m ohm Ipeak=10.9A Imax=7.63A Delta I=((19-1.05)*(1.05/19))/(L*Freq)=1.837A Vtrip=Rtrip*10uA=0.0732V Iocp-min=Vtrip/(Rds(on)(max)*1.2)+Delta I / 2= 11.81A Iocp-max=Vtrip/(Rds(on)(typ)*1.2)+Delta I / 2=14.47A Iocp=11.81~14.47A PQ64 AO4456_SO8 Rds(on)=4.5m ohm(typ) 5.6m ohm(max) VFB=0.75V PR309 59K_0402_1% +1.05VS @ PC101 47P_0402_50V8J LGATE @ PR304 4.7_1206_5% +5VALW PC100 4.7U_0603_6.3V6K open-drain PGOOD Layout Note: Place near V5FILT Pin FB +1.05VSP 12 CS +5VALW PR305 100_0603_1% GND PHASE 0.1U_0603_25V7K 15 14 UG_1.05V VDD 13 VOUT UGATE PL8 1.8UH_MSCDRI-104A-1R8N-E_9.5A_30% PC95 1 BOOT TON PR302 0_0603_5% 2BST_1.05V-1 2 NC PC96 1U_0402_6.3V6K @ PR303 47K_0402_5% BST_1.05V EN/DEM PU10 ,53 VS_ON 1.05V_EN PR301 9.76K_0402_1% 2 JUMP_43X118 PC94 4.7U_1206_25V6K PQ63 AO4466_SO8 EN_PSV GND=>Disable SMPS FLOAT=>PWM_only mode HIGH=>Auto_skip mode PC93 4.7U_1206_25V6K @ PJ21 51117_1.05V_B+ Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2008/08/10 Deciphered Date 2009/08/10 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C 1.5VP / 1.05VSP Rev 0.1 NALG0 Friday, October 23, 2009 D Sheet 51 of 60 B+ VGA@ PJ24 2 B+_core VGA_CORE Ipeak=16A Imax=11.2A Delta I / = 3.33A , Freq=1/ 75E-12*PR153=230K Hz Iocp(min)=1.1*Ipeak+Delta I / = 20.93A Rsen=Iocp(min)*1.2*Rds(on)(max)/ISEN(min)=3.57K ohm ISEN(min)=19uA , Rds(on)=5.6m ohm(max) ,4.5m ohm(typ) Iocp(max)=ISEN(min)*Rsen/(1.2*Rds(on)(typ))=25.12A Iocp=22.97~25.12A VGA@ LX_VCORE VGA@ PR310 DH_VCORE VGA@ PR311 0_0603_5% BST_VCORE 2.2_0603_5% 14,39 VGA_PWROK DH_VCORE-1 VGA@ VGA@ PC104 0.1U_0603_25V7K +5VS open-drain D PC103 10U_1206_25V6M PC102 10U_1206_25V6M JUMP_43X118 15 16 BOOT UG VIN PVCC VGA@ PR313 6269_VCORE 14 6269_VCORE 4.7_0603_5% 2VGA@ PC105 VGA@ PQ42 3 PHASE +3VS PGOOD GND PU15 VGA@ PR312 0_0603_5% D 2.2U_0603_6.3V6K DCR=1.6m ohm TPCA8030-H_SOP-ADV8-5 VGA@ PR315 4.7_1206_5% 3.57K_0402_1% VGA@ PC206 VGA@ 680P_0603_50V7K Rds=4.5mΩ(Typ) 5.6mΩ(Max) +NVVDD_SENSE 23 C Material Note: 330uF/6 mΩ, number are 3, Power 1, HW VGA@ PR151 2.4K_0402_1% 1 2 +3VS_DELAY VFB=0.6V VGA@ PC208 0.01U_0402_25V7K VGA@ VGA@ PR154 23.7K_0402_1% @ PR155 57.6K_0402_1% GPU_VID1 22 VGA@ PR158 10K_0402_1% VGA@ PC210 0.022U_0402_25V7K 2 6.98K_0402_1% VGA@ PR157 D VGA@ PQ45 10K_0402_1% 2 2N7002W-T/R7_SOT323-3 G S VGA@ PR156 VGA@ 10K_0402_5% 1 PC209 PR153 VGA@ PR152 22K_0402_1% 2 2200P_0402_25V7K 22P_0402_50V8J PC207 VGA@ VGA@ PC107 330U_6.3V_M 10_0402_1% VGA@ ISL6268CAZ-T_SSOP16 + 2 VGA@ PR150 10 0.1U_0402_16V7K C VGA@ PQ44 AO4456_SO8 VO VGA@ PC108 11 8 ISEN 30K_0402_1% EN FSET VGA@ PQ43 AO4456_SO8 VGA@ PR148 ISEN_VCORE 2 12 +VGA_COREP 0.56UH_ETQP4LR56WFC_21A_20% PR149 PGND DL_VCORE 0_0402_5% 13 FB VGA_ON COMP 9,43 VGA_ON LG VCC @ PR314 10K_0402_5% VGA@ PR316 VGA@ PL15 VGA@ PC106 2.2U_0603_6.3V6K +1.5V +3VS_DELAY VGA@ PR159 6.34K_0402_1% +3VS FB VIN @ PR164 10K_0402_1% VGA@ PC213 22U_0805_6.3V6M GPU_VID1 Core Voltage Level 0 0.8 V 0.85 V 1.03 V 1 reserve 2 VGA@ PC214 GPU_VID0 0.01U_0402_25V7K VGA@ PR166 1.15K_0402_1% S IC APL5913-KAC-TRL SO 8P @ PC215 22U_1206_6.3V6M FB=0.8V A A VGA@ PC217 0.022U_0402_25V7K N11M +1.05VSDGPU GPU_VID0 22 VOUT VGA@ PC212 4.7U_0603_6.3V6M VOUT 10K_0402_1% VIN VGA@ PC216 0.1U_0402_16V7K EN VGA@ PR162 2 G VGA@ PC211 1U_0402_6.3V6K 1 GND VGA_ON 10K_0402_1% 24,39,43 VGA_ON POK VCNTL VGA@ PU16 10K_0402_5% VGA@ PR165 10K_0402_5% VGA@ PQ46 D 2N7002W-T/R7_SOT323-3 S @ PR163 0824 PR159 13K(0.9V) change to 6.34K for 1.033V @ PJ23 JUMP_43X118 B VGA@ PR160 @ PR161 4.7K_0402_5% 2 +5VS B 0824 change to 3.65K for 1.05V Vout=FB*(1+PR166/PR167) PR167=3K, Vo=1.1V PR167=3.65K, Vo=1.05V VGA@ PR167 3.65K_0402_1% Compal Secret Data Security Classification Issued Date 2007/12/18 2008/12/18 Deciphered Date Title Compal Electronics, Inc VGA_COREP/+1.1VSDGPU THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Rds=4.5mΩ(Typ) 5.6mΩ(Max) Date: Rev 0.1 NALG0 Friday, October 23, 2009 Sheet 52 of 60 PJ22 6268_B+ LX_1.1VS_VTT @ PR130 1K_0402_1% DH_1.1VS_VTT VIN BOOT PHASE UG 15 16 PGOOD PVCC PGND 12 ISEN 11 Layout Note: Close IC PC112 2.2U_0603_6.3V6K DL_1.1VS_VTT Rds=2.3mΩ(Typ) 3.2mΩ(Max) 2 PR138 57.6K_0402_1% +3VS B PR145 100K_0402_5% VTT_SENSE 1 @ 1 PR146 10K_0402_5% PR147 100K_0402_5% 2 PC121 0.01U_0402_16V7K PQ37 2N7002W-T/R7_SOT323-3 PC120 0.1U_0402_16V7K G S PR143 6.49K_0402_1% C PQ36 TPCA8028-H_SOP-ADVANCE8-5 +1.1VS_VTTP PR142 180K_0402_1% 1 PR144 4.7K_0402_5% D PC116 330U_D2_2V_Y 單單單單單單Pin15 +3VS PR141 78.7K_0402_1% + Material Note: 330uF/9 mΩ, number are 3, Power 1, HW PR168 10_0402_1% VFB=0.6V @ PC114 680P_0603_50V7K Layout Note: Close IC PQ38 PMBT2222A_SOT23-3 PR137 90.9K_0402_1% 2 PC119 6800P_0402_25V7K 22P_0402_50V8J PC117 PC118 0.01U_0402_25V7K 3 ISL6268CAZ-T_SSOP16 PR139 0_0402_5% B PR135 2.05K_0402_1% PR140 4.99K_0402_1% +1.1VS_VTT Ipeak=18.06A Imax=12.642A Delta I / = 2.176A , Freq=230K Hz Iocp(min)=Ipeak + Delta I / = 20.236A Rsen=Iocp(min)*1.2*Rds(on)(max)/ISEN(min)=2.05K ohm ISEN(min)=19uA , Rds(on)=3.2m ohm(max) ,2.3m ohm(typ) Iocp(max)=ISEN(min)*Rsen/(1.2*Rds(on)(typ))=28.225A Iocp=20.236~28.225A ISEN_1.1VS_VTT VO 10 FB COMP PC115 0.1U_0402_16V7K FSET EN Layout Note: Close IC +1.1VS_VTTP PQ35 TPCA8028-H_SOP-ADVANCE8-5 C @ PR136 10K_0402_5% PL9 1UH_PCMB103E-1R0MS_20A_20% @ PR133 4.7_1206_5% PR134 57.6K_0402_1% PC113 2.2U_0603_6.3V6K 39,50,51 VS_ON DCR=2.7mΩ(Typ) 3.0mΩ(Max) 13 PQ34 SI7686DP-T1-E3_SO8 PR132 4.7_0603_5% 6268_VCORE_1.1VS_VTT 14 LG D PR131 0_0603_5% 6268_VCORE_1.1VS_VTT VCC PC111 0.1U_0603_25V7K +5VS GND PU11 DH_1.1VS_VTT-1 PR128 PR129 0_0603_5% BST_1.1VS_VTT 0_0603_5% H_VTTPWRGD 5 PC110 10U_1206_25V6M PC109 10U_1206_25V6M D Layout Note: Place near high-side MOS Drain and low-side MOS Source +3VS PR126 0_0402_5% 1 1 2 JUMP_43X118 PR127 2K_0402_1% B+ H_VTTVID1 Voltage Select VID Vout High 1.06 V Low 1.1 V 0724 1.05V change to 1.06V A A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2009/4/15 2010/04/15 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: +1.1VS_VTTP Rev 0.1 NALG0 Friday, October 23, 2009 Sheet 53 of 60 Intel Auburndale CPU(Integrate Graphics) Imax=15A OCP calculation : Assume DCR=1.1m ohm G1=Rn/(Rn+Rsum)=0.617 where Rn=PR277 // (PR274+PH3)=5.875k ohm Rsum=PR269=3.65k ohm LL=2*Rdroop*G1*DCR/Ri= 6.96m V/A where Rdroop=PR271=8.66k ohm, Ri=PR283=1.69k ohm Iocp=OCP Threshold*Rdroop/LL=24.89A B+ D @ PJP3 GFX_B+ 2 UMA@ PC191 0.22U_0402_6.3V6K GFXVR_IMON ISUMBST_GFX 1 14 2 UMA@ PR274 UMA@ PH3 2 UMA@ PC198 2.2U_0603_6.3V6K @ PC199 470P_0603_50V8J Rds=4.5mOHM(typ) Rds=5.6mOHM(max) UMA@ PR270 0_0402_5% + UMA@ PC130 330U 2V M X LESR6M SX H1.9 2.61K_0402_1% 10K +-5% TSM0A103J4302RE 0402 UMA@ PR277 11K_0402_1% Layout Note: Place near Choke Material Note: 330uF/6 mΩ, number are 3, PW 1, HW 1, of HW is backup UMA@ PC202 1U_0402_16V7K UMA@ UMA@ UMA@ UMA@ UMA@ UMA@ UMA@ UMA@ UMA@ PR280 PR281 PR282 PR285 PR286 PR287 PR289 PR290 PR291 GFXVR_VID_0 GFXVR_VID_1 GFXVR_VID_2 GFXVR_VID_3 GFXVR_VID_4 GFXVR_VID_5 GFXVR_VID_6 GFXVR_EN GFXVR_DPRSLPVR B UMA@ PC203 1U_0402_16V7K UMA@ PR283 1.69K_0402_1% UMA@ PR288 82.5_0402_1% 2 UMA@ PC204 0.01U_0402_16V7K @ PR284 100_0402_1% 2 2 2 2 2 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% GFX_CORE_PWRGD B +5VALW @ PR279 10K_0402_1% UMA@ PR269 3.65K_0805_1% 21 +VGFX_COREP UMA@ PQ41 AO4456_SO8 VID2 VID3 VID4 @ PR268 2.2_1206_5% UMA@ PR273 0_0603_5% 1 UMA@ PQ40 AO4456_SO8 19 20 8 18 DL_GFX VID1 17 12 11 10 13 IMON VIN VDD RTN ISUM ISUM+ BOOT 16 LX_GFX UMA@ PR276 8.06K_0402_1% UMA@ PL10 0.45UH_PCMB104T-R45MN_25A_20% 15 DH_GFX 22 C UMA@ PR275 17.8K_0402_1% VID0 CLK_EN# UMA@ PQ39 FDMS8692 1N UMA@ PC200 150P_0402_50V8J PGOOD 23 VCCP 24 +VGFX_COREP RBIAS VID5 UMA@ PC196 100P_0402_50V8J UMA@ PC201 22P_0402_50V8J LGATE 25 147K for CPU 47K for GPU VSSP VW VID6 PHASE COMP 28 2 1 UMA@ PC197 1000P_0402_50V7K VR_ON UMA@ PR294 47K_0402_1% UMA@ PC193 0.22U_0603_25V7K DCR=1.1 mOHM UGATE UMA@ PU12 ISL62881HRZ-T_QFN28_4X4 FB DPRSLPVR UMA@ PR272 825K_0402_1% VSEN 26 27 UMA@ PR271 8.66K_0402_1% 29 UMA@ PC195 330P_0402_50V7K AGND UMA@ PR293 10_0402_1% 2 UMA@ PR266 0_0603_5% UMA@ PC194 330P_0402_50V7K VSS_AXG_SENSE VCC_AXG_SENSE ISUM+ UMA@ PC192 1000P_0402_50V7K C +VGFX_COREP UMA@ PR265 22.6K_0402_1% UMA@ PR292 10_0402_1% 2 UMA@ PC189 1U_0402_6.3V6K VSS_AXG_SENSE 1 UMA@ PR263 0_0603_5% UMA@ PR264 1_0603_5% UMA@ PC190 0.22U_0603_25V7K +5VALW 1 @ PC188 0.1U_0402_25V6 2 UMA@ PC126 10U_1206_25V6M 2 PAD-OPEN 4x4m UMA@ PC125 10U_1206_25V6M 1 UMA@ PC187 2200P_0402_50V7K D ISUM+ @ PC205 180P 50V J NPO 0402 ISUM- A A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2009/4/15 Deciphered Date 2010/04/15 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title GFX_COREP Size C Date: Document Number Rev 0.1 NALG0 Friday, October 23, 2009 Sheet 54 of 60 PR219 499_0402_1% PC157 0.22U_0603_25V7K 4 2 3 VGA@ PQ52 TPCA8028-H_SOP-ADVANCE8-5 @ PD7 RB751V-40TE17_SOD323-2 Pull up 3V PR235 VSSSENSE PQ53 TPCA8030-H_SOP-ADV8-5 UGATE1 PR261 10_0402_1% 2 PR251 2.61K_0402_1% 1 PHASE1 PH6 10K_0402_1%_TSM0A103F34D1RZ PR255 1_0402_5% @ PR259 0_0402_5% PQ56 TPCA8028-H_SOP-ADVANCE8-5 Layout Note: Place near Phase1 Choke VSUM+ PC184 680P_0402_50V7K +CPU_CORE V1N PR252 2.2_1206_5% 2 LGATE1 1 2 C PR256 1.21K_0402_1% @ PC185 1200P_0402_50V7K @ PQ54 TPCA8030-H_SOP-ADV8-5 VGA@ PQ55 TPCA8028-H_SOP-ADVANCE8-5 PR258 11K_0402_1% 1 2 PC182 1000P_0402_50V7K 0_0402_5% PC183 330P_0402_50V7K B PR260 VSSSENSE PC176 0.22U_0603_25V7K BOOT1_1 PL14 0.36UH_PCMC104T-R36MN1R17_30A_20% GNDA_VCORE PR249 2.2_0603_5% 1 PC181 2 PC180 330P_0402_50V7K PC179 0.068U_0603_16V7K 2 0_0402_5% PC178 0.22U_0603_10V7K PR248 PR250 1 VCCSENSE @ PC177 2700P_0402_50V7K 2 10_0402_1% 0.01U_0402_25V7K PR247 +CPU_CORE C 82.5_0402_1% VSUM+ 1 2 PR246 8.25K_0402_1% PC175 10U_1206_25V6M D GNDA_VCORE PC170 0.22U_0603_25V7K VSUM- PC169 1U_0603_10V6K 1 +CPU_B+ PR254 10K_0402_5% 1_0402_5% +5VALW IMVP_IMON @ PC172 0.1U_0603_25V7K PR245 0_0402_5% 0_0402_5% +CPU_B+ PR241 BOOT1 Layout Note: PH5 place near Phase1 L-MOS +5VALW PC163 1U_0603_10V6K ISEN2 ISEN1 E PR240 PR242 412K_0402_1% PR234 0_0402_5% 0_0402_5% 2 GNDA_VCORE VSUM- ISL62883HRZ-T_QFN40_5X5~D 11 12 13 14 15 16 17 18 19 20 AGND 30 29 28 27 26 25 24 23 22 21 390P_0402_50V7K PR239 2.61K_0402_1% 2 PC166 150P_0402_50V8J BOOT2 UGATE2 PHASE2 VSSP2 LGATE2 VCCP PWM3 LGATE1 VSSP1 PHASE1 PGOOD PSI# RBIAS VR_TT# NTC VW COMP FB ISEN3 ISEN2 PC168 0.22U_0402_10V6K PC164 2 41 PC167 0.22U_0402_10V6K PR237 8.06K_0402_1% PR238 562_0402_1% 2 PC165 10P_0402_50V8J PC161 22P_0402_50V8J ISEN2 PC158 680P_0402_50V7K 1 @ PR236 249K_0402_1% H_PROCHOT#_R PH5 470KB_0402_5%_ERTJ0EV474J GNDA_VCORE D 10 0_0402_5% PR232 56P_0402_50V8 4.02K_0402_1% 2 V1N VSUM+ PC159 1U_0603_10V6K 68_0402_5% CLK_EN# DPRSLPVR VR_ON VID6 VID5 VID4 VID3 VID2 VID1 VID0 PU14 PC162 1000P_0402_50V7K GNDA_VCORE PR233 PR231 H_PROCHOT# E PR223 1_0402_5% @ PR225 0_0402_5% F 1 +1.1VS_VTT @ PC160 0_0402_5% PC171 0.22U_0603_25V7K 1 PR230 40 39 38 37 36 35 34 33 32 31 +1.1VS_VTT H_PSI# PR229 147K_0402_1% GNDA_VCORE +CPU_CORE V2N @ PR228 100K_0402_5% ISEN1 VSEN RTN ISUMISUM+ VDD VIN IMON BOOT1 UGATE1 F LGATE2 1 CLK_ENABLE# 2 VGATE PR220 2.2_1206_5% PR226 1.91K_0402_1% 12,15 PQ51 TPCA8028-H_SOP-ADVANCE8-5 PR224 1.91K_0402_1% PR227 0_0402_5% PC122 220U_25V_M G PHASE2 12 CLK_ENABLE# +3VS H + PL13 0.36UH_PCMC104T-R36MN1R17_30A_20% UGATE2 PR222 10K_0402_5% H_DPRSLPVR BOOT2_2 B+ G PR217 2.2_0603_5% BOOT2 1 VR_ON @ PQ50 TPCA8030-H_SOP-ADV8-5 PR218 0_0402_5% 37 2 PC156 10U_1206_25V6M 2 PR216 0_0402_5% PC155 10U_1206_25V6M PR215 0_0402_5% PC174 10U_1206_25V6M CPU_VID6 PQ49 TPCA8030-H_SOP-ADV8-5 CPU_VID5 PR221 3.65K_0805_1% PC173 2200P_0402_50V7K CPU_VID4 PR214 0_0402_5% PR253 3.65K_0805_1% PR213 0_0402_5% CPU_VID3 CPU_VID2 PR212 0_0402_5% PR211 0_0402_5% PL12 FBMA-L18-453215-900LMA90T_1812 CPU_VID1 +CPU_B+ CPU_VID0 3 Intel Auburndale CPU(Integrate Graphics) , Ipeak = 48A OCP calculation : Assume DCR=1.1m ohm G1=Rn/(Rn+Rsum/2)=0.763 where Rn=PR258 // (PR251+PH6)=5.875k ohm Rsum=PR221, PR253 =3.65k ohm LL = 2*Rdroop*G1*(DCR/2)/Ri = 1.81mV/A where Rdroop=PR239=2.61k ohm , Ri=PR256=1.21k ohm Iocp= OCP Threshold*Rdroop/LL=40E-06*2.61E03/1.81E-03=57.68A PR210 0_0402_5% H PC154 2200P_0402_50V7K @ PC153 0.1U_0603_25V7K V2N VSUM- B ISEN1 VSUM- @ PR262 100_0402_1% PJP5 PC186 0.1U_0402_16V7K GNDA_VCORE PAD-OPEN1x1m A GNDA_VCORE GNDA_VCORE 2009/4/15 Issued Date Deciphered Date 2010/04/15 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC +CPU_CORE Size C Date: A Compal Electronics, Inc Compal Secret Data Security Classification Document Number Rev 0.1 NALG0 Friday, October 23, 2009 Sheet 55 of 60 Version change list (P.I.R List) Item D C Page of for PWR Fixed Issue Reason for change design change Rev PG# 0.1 48 Modify chager circuit Modify 1.8V V5FILT PIN Modify 1.5V V5FILT PIN Modify 1.05V V5FILT PIN Modify VGA_COREP circuit Modify +1.1VS_VTTP circuit design change 0.1 53 Modify OTP circuit Link right component 0.1 Modify 5V/3V circuit Delete component 0.1 Modify List Date Change PR60 to SD000001F00(0.02_2512_1%) Phase 09/06/23 EVT 09/07/21 DVT 09/07/21 DVT 09/07/21 DVT 09/06/23 EVT Cahnge PR168 to SD034100A80 (S RES 1/16W 10 +-1% 0402) 09/06/23 EVT 46 Add PH1 to SL210031F00 (S THERM_ 100K +-1% TH11-4H104FT 0603) 09/06/25 EVT 47 Delete PC42 to SE076473K80 (S CER CAP 047U 16V K X7R 0402) 09/06/25 EVT Change PU16, PR165, PR166, PR167, PC211, PC212, PC213, PC214, PC215, PC216 BOM structure to VGA@ 09/06/26 EVT 09/06/26 EVT 09/06/30 EVT 09/06/30 EVT D Cahnge PR115 to SD014100080 (S RES 1/10W 100 +-1% 0603 ) 0.1 Avoid 2’nd source RT8209B can no power on 50 Cahnge PC77 to SE107475K80 (S CER CAP 4.7U 6.3V K X5R 0603) Cahnge PR296 to SD014100080 (S RES 1/10W 100 +-1% 0603 ) Avoid 2’nd source RT8209B can no power on 0.1 51 Cahnge PC91 to SE107475K80 (S CER CAP 4.7U 6.3V K X5R 0603) Cahnge PR305 to SD014100080 (S RES 1/10W 100 +-1% 0603 ) 0.1 Avoid 2’nd source RT8209B can no power on 51 Cahnge PC100 to SE107475K80 (S CER CAP 4.7U 6.3V K X5R 0603) Cahnge PR149 to SD028000080 (S RES 1/16W +-5% 0402) design change 0.1 52 Cahnge PR150 to SD034100A80 (S RES 1/16W 10 +-1% 0402) Cahnge PR139 to SD028000080 (S RES 1/16W +-5% 0402) Modify 1.1VSDGPU circuit design change 0.1 52 10 Modify chager circuit design change 0.1 48 11 Modify VGA_COREP circuit 12 Modify VGA_COREP circuit 13 Modify OTP circuit design change 0.2 46 Add PR169 to SD034100480 (S RES 1/16W 1M +-1% 0402) 14 Modify 1.5VP circuit design change 0.2 51 Change PL7 to SH000009U00(S COIL 1UH +-20% FDUE1040D-1R0M=P3 21.3A) 15 Modify VGA_COREP circuit design change 0.2 52 16 Modify +1.1VS_VTTP circuit design change 0.2 53 17 Modify VGA_COREP circuit design change 0.2 52 18 Modify 1.8V circuit design change 0.2 50 19 Modify CPU circuit design change 0.2 55 20 Modify +1.1VS_VTTP circuit design change 0.2 53 21 Modify CPU circuit design change 0.2 55 22 Modify chager circuit design change 0.2 48 23 Modify 1.1VSDGPU circuit design change 0.2 52 B Change PR78 to SD012200D80(S RES 1/2W 0.02 +-1% 1206) C Cahnge PR151 to SD034240180 (S RES 1/16W 2.4K +-1% 0402) design change(Voltage Level) 0.1 52 Cahnge PR156 to SD000002680 (S RES 1/16W 6.98K +-1% 0402) Cahnge PR154 to SD034237280 (S RES 1/16W 23.7K +-1% 0402) design change(Voltage Level) 0.1 52 Cahnge PR159 to SD034130280 (S RES 1/16W 13K +-1% 0402) Cahnge PQ6 to SB000006800 (S TR 2N7002W T/R7 1N SOT-323) 09/07/13 09/07/20 09/07/20 Cahnge PR153 to SD034576280 (S RES 1/16W 57.6K +-1% 0402) DVT DVT DVT B Cahnge PQ35 to SB00000GL00 (S TR TPCA8028-H 1N SOP ADVANCE) 09/07/20 Cahnge PQ36 to SB00000GL00 (S TR TPCA8028-H 1N SOP ADVANCE) Cahnge PC107 to SF000002000 (S ELE CAP 330U 6.3V M 6.3X5.9 LESR15M VU) 09/07/20 Cahnge PC74 to SF000002000 (S ELE CAP 330U 6.3V M 6.3X5.9 LESR15M VU) and BOM structure to @ 09/07/20 DVT DVT DVT 09/07/20 DVT Cahnge PC116 to SGA20331E10 (S POLY C 330U 2V Y D2 LESR9M EEFSX H1.9) 09/07/21 DVT Cahnge PC179 to SE026683K80 (S CER CAP 068U 16V K X7R 0603) 09/07/22 DVT 09/07/22 DVT 09/07/22 DVT Cahnge PR226 to SD000009O80 (S RES 1/16W 1.91K +-1% 0402) Cahnge PC53 to SE076473K80 (S CER CAP 047U 16V K X7R 0402) A Cahnge PC212 to SE107475M80 (S CER CAP 4.7U 6.3V M X5R 0603 H0.8) 2007/09/20 Deciphered Date 2008/09/20 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A Compal Electronics, Inc Compal Secret Data Security Classification Issued Date Cahnge PC64 to SE107475M80 (S CER CAP 4.7U 6.3V M X5R 0603 H0.8) PIR (PWR) Friday, October 23, 2009 Rev 0.1 Sheet 56 of 60 Version change list (P.I.R List) Item D C Fixed Issue Reason for change design change Rev PG# 0.2 54 24 Modify GFX_COREP circuit 25 Modify 1.8V circuit 26 Modify 1.8V circuit design change 0.2 50 27 Modify 1.8V circuit design change 0.2 50 28 Modify 1.8V circuit design change 0.2 50 29 Modify 1.8V circuit design change 0.2 50 30 Modify 5V/3V circuit 31 Modify VGA_COREP circuit design change 0.2 add snubber(PR42 PC36),(PR41 PC35) add boost PR43, PR44 0.2 add snubber(PR315 PC206) add boost PR311 0.2 50 Modify List Page of for PWR Date Cahnge PC189 to SE000000K80 (S CER CAP 1U 6.3V K X5R 0402) Add PR170 to SD013000080 (S RES 1/10W +-5% 0603)and BOM structure to @ Change PR109, PR117, PC72, PQ58, PQ59 BOM structure to @ Add PU17 to SA00003KL00(S IC MP2121DQ-LF-Z QFN 10P PWM) Add PD16 to SCS00001I80(S SCH DIO B340A SMA VISHAY) BOM structure to @ Add PR173 to SD034402380(S RES 1/16W 402K +-1% 0402) Add PR174 to SD034316380(S RES 1/16W 316K +-1% 0402) Add PR171 to SD028000080(S RES 1/16W +-5% 0402)BOM structure to @ Add PR113 to SD028470280(S RES 1/16W 47K +-5% 0402) Add PC123,PC124 to SE053106Z80(S CER CAP 10U 10V Z Y5V 0805) Add PC127 to SE076103K80(S CER CAP 01U 16V K X7R 0402) Add PC218, PC219 to SE000000I10(S CER CAP 22UF 6.3V M X5R 0805 H1.25) Phase 09/07/22 DVT 09/07/28 DVT 09/07/28 DVT 09/07/28 DVT 09/07/28 DVT 09/07/28 DVT 47 Add PR41, PR42 to SD001470B80(S RES 1/4W 4.7 +-5% 1206) Add PC35, PC36 to SE074681K80(S CER CAP 680P 50V K X7R 0402) Add PR43, PR44 to SD013220B80(S RES 1/10W 2.2 +-5% 0603) 09/07/28 DVT 52 Add PR311 to SD013220B80(S RES 1/10W 2.2 +-5% 0603)and BOM structure to VGA@ Change PR315 PC206 BOM structure to VGA@ 09/07/28 DVT 0.2 55 Add PR220, PR252 to SD011220B80(S RES 1/4W 2.2 +-5% 1206) Add PC158, PC184 to SE074681K80(S CER CAP 680P 50V K X7R 0402) Add PR217, PR249 to SD013220B80(S RES 1/10W 2.2 +-5% 0603) Cahnge PR141 to SD034787280(S RES 1/16W 78.7K +-1% 0402) Cahnge PR143 to SD034649180(S RES 1/16W 6.49K +-1% 0402) 32 Modify CPU circuit add snubber(PR220 PC158),(PR252 PC184) add boost PR217, PR249 33 Modify +1.1VS_VTTP circuit design change 0.2 53 34 Modify OTP circuit design change 0.2 46 Modify +1.1VS_VTTP circuit design change(OCP) 0.2 53 36 Modify GFX_COREP circuit design change 0.2 54 Cahnge PH3 to SL200000Y00(10K +-5% TSM0A103J4302RE 0402) 09/07/29 DVT 37 Modify CPU circuit design change 0.2 55 Cahnge PH6 to SL200000W00(10K +-1% TSM0A103F34D1RZ 0402) 09/07/29 DVT 38 Modify 1.5V circuit Change to 3mm height choke for thermal issue 0.2 51 Cahnge PL7 to SH00000AB00(S COIL 1UH +-20% PCMB103T-1R0MS 13A) 09/08/06 DVT 39 Modify VGA_COREP circuit design change (GS sample define 1.03V,+1.05VSDGPU Vo=1.05V) 0.3 52 Cahnge PR159 to SD034634180(S RES 1/16W 6.34K +-1% 0402) Cahnge PR167 to SD034365180(S RES 1/16W 3.65K +-1% 0402) 09/08/24 PVT 40 Modify 1.8V circuit design change 0.3 50 Cahnge PC127 to SE076104K80(S CER CAP 1U 16V K X7R 0402) 09/08/24 PVT 41 Modify chager circuit design change 0.3 48 Cahnge PR88 to SD034154280(S RES 1/16W 15.4K +-1% 0402) Change PR81 to SD034154380(S RES 1/16W 154K +-1% 0402) 09/08/26 PVT 42 Modify VGA_COREP circuit design change 0.3 52 Change PR160 BOM structure to VGA@ VID pull high voltage change to +3VS_DELAY 09/09/03 PVT 43 Modify +1.1VS_VTTP circuit design change 0.3 53 09/09/03 PVT 44 Modify 0.75V circuit design change 0.3 50 Cahnge PR120 to SD034280180(S RES 1/16W 2.8K +-1% 0402) 09/09/11 PVT 45 Modify VGA_COREP circuit design change 0.3 52 Cahnge PR316 to SD034300280(S RES 1/16W 30K +-1% 0402) Change PR164 BOM structure to @ 09/09/11 PVT 46 Modify +1.1VS_VTTP circuit design change 0.3 53 Cahnge PR135 to SD034205180(S RES 1/16W 2.05K +-1% 0402) 35 Cahnge PH1 to SL200000U00(S THERM_ 100K +-1% TSM0B104F4251RZ 0402) Cahnge PH2 to SL200000U00(S THERM_ 100K +-1% TSM0B104F4251RZ 0402) Cahnge PR135 to SD034280180(S RES 1/16W 2.8K +-1% 0402) 09/07/28 DVT 09/07/28 DVT 09/07/28 DVT 09/07/29 DVT D C B B Change PR130 BOM structure to @ A A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2007/09/20 Deciphered Date 2008/09/20 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: PIR (PWR) Friday, October 23, 2009 Rev 0.1 Sheet 57 of 60 Version change list (P.I.R List) Item Page of for PWR Fixed Issue Reason for change Rev PG# Modify List Date Phase 47 Modify OTP circuit design change 0.3 46 Change PR23 to SD00000AJ80(S RES 1/16W 12.4K +-1% 0402) Change PR26 to SD034158280(S RES 1/16W 15.8K +-1% 0402) 09/09/14 PVT 48 Modify 1.8V circuit design change 0.3 50 Change PL6 to SH000009Q00(S COIL 2.2UH 20% MSCDRI-74A-2R2M-E 6.5A) 09/09/16 PVT 09/09/16 PVT 09/10/08 PVT D D Change PU4 to SA00001TN00(S IC ISL6237IRZ-T QFN 32P) 49 Modify 5V/3V circuit design change 0.3 47 Change PR120 to SD00000AJ80(S RES 1/16W 12.4K +-1% 0402) 50 Modify 0.75V circuit design change 0.3 50 51 52 53 C 54 C 55 56 57 58 59 60 B 61 B 62 63 64 65 66 67 68 A A 69 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2007/09/20 Deciphered Date 2008/09/20 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: PIR (PWR) Friday, October 23, 2009 Rev 0.1 Sheet 58 of 60 Version change list (P.I.R List) Item Page of for HW Fixed Issue Reason for change Rev PG# D C B Modify List Date R72 bom structure Phase D 7/23 0.2 reserve R735 7/23 0.2 rename CPU VDDQ from +1.5V to +1.5V_CPU 7/23 0.2 R146 BOM structure 7/23 0.2 11 reserve S3 power consumptiosn circuit 7/23 0.2 12 change Y1 Y4 Y6 footprint 7/23 0.2 13 add ME_EN# from EC to PCH 7/23 0.2 14 pop Y6,C254,C255 , and project ID pin 7/23 0.2 17 change USB port to port , port to port 7/23 0.2 10 18 GPIO35 pin(VGa presetnt) modfiy 7/23 0.2 11 19 R605 and R628 BOM structure modify 7/23 0.2 12 22 add VGA thermal sensor from EC to VGA 7/23 0.2 13 23 pop R479,del R491 7/23 0.2 14 29 L29~L34 change from 0805 to 0603 7/23 0.2 15 30 Q45,Q47 gate voltage change from +3VS to +3VS_delay 7/23 0.2 16 37 change R306 to 8.2K, add D29, rename EC_MUTE 7/23 0.2 17 38 Jfun1 pin3 change form KSO1 to KSO3 7/23 0.2 18 39 del SW2 7/23 0.2 19 41 change R333, R336 to 39k,15k, add R681,C707 7/23 0.2 20 43 reserve Q58,Q59,R728,R326, change U26,R688 7/23 0.2 21 24 reserve C710 7/23 0.2 22 28 reserve U44,U45 7/23 0.2 23 19 update L7,L8,L10,L11 footprint 7/23 0.2 C B A A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2008/07/01 Deciphered Date 2009/12/31 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: PIR (HW) Rev 1.0 NALG0 M/B LA-5681P Schematic Friday, October 23, 2009 Sheet 59 of 60 Version change list (P.I.R List) Item Page of for HW Fixed Issue Reason for change Rev PG# D C B 1 30 Modify List Date pop R248, R271,R265 Phase D 7/23 0.2 pop C165, del C170 7/23 0.2 18 unpop R532, R86 7/23 0.2 add R472 and C713 8/31 0.3 11 add C714 8/31 0.3 12 add C715 8/31 0.3 17 USB20 port change to USB20 port 8/31 0.3 24 3VS_delay related circuit 8/31 0.3 30 del R236,C257 , pop R254,C268 in all sku 8/31 0.3 10 33 unpop R3 , U1, pop R6 , change R306 to 18K 8/31 0.3 11 37 ME_EN change from U25,75 to U25.16 8/31 0.3 12 29 pop Q6,Q7 in all sku 8/31 0.3 13 29 change L29~L34 footprint 8/31 0.3 14 41 del D25,D26,D27 8/31 0.3 15 43 update C705,C706 BOM structure 8/31 0.3 16 14 unpop R112 8/31 0.3 17 change C165 p/n 8/31 0.3 18 40 9/10 0.3 pop C353 change R157,R527,R570,R575,R582,R634,R239,R64 to ohm 19 C B 0.3 20 add R746,R747 9/10 0.3 21 12 U27 clk gen change to siligo 9/10 0.3 22 40 del C371,C372 9/10 0.3 23 Modify BOM Config add S3@ on all SKU 10/20 1.0 A A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2008/07/01 Deciphered Date 2009/12/31 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: PIR (HW) Rev 1.0 NALG0 M/B LA-5681P Schematic Friday, October 23, 2009 Sheet 60 of 60 Version change list (P.I.R List) Item Page of for HW Fixed Issue Reason for change Rev PG# D C B Modify List Change R209,C254,C255,Y6 BOM config to UMA@ Date Phase 10/20 1.0 D 14 19 Added C257 10/20 1.0 22 Change N11 to A2 (P/N SA00003HZ10) 10/20 1.0 22 Added R748 and R749 as I2C pull high resistor 10/20 1.0 22 Pop R36,R37 as DIS@ 10/20 1.0 28 Change Q11,Q19 BOM config to SG@ 10/20 1.0 28 Change R502,R484 BOM config to DIS only@ 10/20 1.0 37 Change R306 to 33k(Board ID) 10/20 1.0 38 Change LED9 PN to SC5191UD00 10/20 1.0 10 43 Change R296 to 47K,R295 to 470 10/20 1.0 11 44 Change LED Resistors: 10/20 1.0 12 R373 to 243,R381 and R383 to 100,R377 to 243, 13 R375 and R376 to 470,R349 to 100,R350 to 191 14 R304 to 499 C 1.0 15 17 Change C256 to 22u 10/22 16 18 ADD R750 10K pull hig resistor 10/22 B 1.0 17 18 19 20 21 22 A A 23 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2008/07/01 Deciphered Date 2009/12/31 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: PIR (HW) Rev 1.0 NALG0 M/B LA-5681P Schematic Friday, October 23, 2009 Sheet 60 of 60 ... DVO 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0. 1U _04 02 _16 V7K 0. 1U _04 02 _16 V7K 0. 1U _04 02 _16 V7K 0. 1U _04 02 _16 V7K 0. 1U _04 02 _16 V7K 0. 1U _04 02 _16 V7K 0. 1U _04 02 _16 V7K 0. 1U _04 02 _16 V7K 0. 1U _04 02 _16 V7K 0. 1U _04 02 _16 V7K... 90 92 94 96 98 10 0 10 2 10 4 10 6 10 8 11 0 11 2 11 4 11 6 11 8 12 0 12 2 12 4 12 6 12 8 13 0 13 2 13 4 13 6 13 8 14 0 14 2 14 4 14 6 14 8 15 0 15 2 15 4 15 6 15 8 16 0 16 2 16 4 16 6 16 8 17 0 17 2 17 4 17 6 17 8 18 0 18 2 18 4 18 6 18 8... 10 3 10 5 10 7 10 9 11 1 11 3 11 5 11 7 11 9 12 1 12 3 12 5 12 7 12 9 13 1 13 3 13 5 13 7 13 9 14 1 14 3 14 5 14 7 14 9 15 1 15 3 15 5 15 7 15 9 16 1 16 3 16 5 16 7 16 9 17 1 17 3 17 5 17 7 17 9 18 1 18 3 18 5 18 7 18 9 19 1 19 3 19 5 19 7 19 9