Acer e5 473 compal LA c341p rev 1 0 схема

A B C D E Compal Confidential Model Name : A4WAB File Name : LA-C341P 1 Compal Confidential 2 M/B Schematics Document Intel Broadwell ULT (Broadwell + Wildcat point) Nvidia N16S-GT / N16V-GM 2015-03-18 3 REV:1.0 4 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2014/09/16 2014/05/24 Deciphered Date Cover Page Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size DocumentNumber AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C D A4WAB M/B LA-C341P Wednesday, March 18, 2015 Sheet E Rev 0.2 of 56 A B VGA C D eDP E Fan Control page 40 page 31 page 28 HDMI Conn DP to VGA RTD2168 eDP 1.35V DDR3L 1333/1600 204pin DDR3L-SO-DIMM X1 page 30 DP x lanes HDMI x lanes NGFF Card WLAN USB port Processor OPI Nvidia N16S-GT / N16V-GM with DDR3 x4 or page 34 DDI page 18 BANK 4, 5, 6, Broadwell ULT page 29 page 17 BANK 0, 1, 2, Dual Channel Intel Broadwell ULT USB 3.0 conn x2 USB 2.0 conn x1 USB port 0, USB/B (port 2) CMOS Camera USB port page 19~27 PCIe 2.0 5GT/s PCIe 2.0 x4 5GT/s port port 204pin DDR3L-SO-DIMM X1 Memory BUS Touch Screen Wildcat point Flexible IO USBx8 PCH PCIe 2.0 5GT/s I2C (PORT0) USB (port 5) page 37 page 37 Page 28 page 28 48MHz port port LAN(GbE)/ Card Reader Realtek 8411B SATA HDD Conn HD Audio port SATA CDROM Conn in (SD) page 06~16 RJ45 conn page 36 LPC BUS page 36 ENE KB9022 page 33 ALC255 SPI SPI ROM x1 CLK=24MHz page 33 RTC CKT HDA Codec 1168pin BGA page 29 Card Reader 3.3V 24MHz Int Speaker page page 35 page 35 Int MIC Universal Jack USB/B page 35 page 36 page 38 Sub Board page LS-C341P Power On/Off CKT Touch Pad Int.KBD page 39 page 39 PS2 / I2C USB/B page 37 page 39 DC/DC Interface CKT page 41 4 Power Circuit DC/DC page 42~53 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2014/09/16 2014/05/24 Deciphered Date Title Block Diagrams THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size DocumentNumber AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C D A4WAB M/B LA-C341P Wednesday, March 18, 2015 Sheet E Rev 0.2 of 56 A B C Voltage Rails Power Plane VIN D SIGNAL STATE Description Adapter power supply (19V) S1 S3 S5 N/A N/A N/A E SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS HIGH HIGH HIGH HIGH ON ON ON ON S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF LOW LOW LOW LOW ON OFF OFF OFF Full ON BATT+ Battery power supply (12.6V) N/A N/A N/A +19VB AC or battery power rail for power circuit N/A N/A N/A +CPU_CORE Core voltage for CPU ON OFF OFF +VGA_CORE Core voltage for GPU ON OFF OFF +0.675VS +0.675VS power rail for DDR3L terminator ON OFF OFF S5 (Soft OFF) OFF Board ID / SKU ID Table for AD channel +1.05VS_VTT +1.05V power rail for CPU ON OFF +1.05VSDGPU +1.05VSDGPU switched power rail for GPU ON OFF OFF +1.35V +1.35V power rail for DDR3L ON ON OFF +1.5VSDGPU +1.5VSDGPU power rail for GPU ON OFF OFF +1.5VS +1.5V power rail for CPU ON OFF OFF +3VALW +3VALW always on power rail ON ON ON* +3VLP B+ to +3VLP power rail for suspend power ON ON ON +3VS +3VALW to +3VS power rail ON OFF OFF +3VSDGPU +3VS to +3VSDGPU power rail for GPU ON OFF OFF +5VALW +5VALWP to +5VALW power rail ON ON ON* +5VS +5VALW to +5VS power rail ON OFF OFF +RTCVCC RTC power ON ON ON Clock Vcc Ra/Rc/Re Board ID 10 11 12 13 Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF 3.3V +/- 5% 100K +/- 5% Rb / Rd / Rf 12K +/- 5% 15K +/- 5% 20K +/- 5% 27K +/- 5% 33K +/- 5% 43K +/- 5% 56K +/- 5% 75K +/- 5% 100K +/- 5% 130K +/- 5% 160K +/- 5% 200K +/- 5% 240K +/- 5% V AD_BID V 0.347 V 0.423 V 0.541 V 0.691 V 0.807 V 0.978 V 1.169 V 1.398 V 1.634 V 1.849 V 2.015 V 2.185 V 2.316 V V AD_BID typ V 0.354 V 0.430 V 0.550 V 0.702 V 0.819 V 0.992 V 1.185 V 1.414 V 1.650 V 1.865 V 2.031 V 2.200 V 2.329 V V AD_BID max V 0.360 V 0.438 V 0.559 V 0.713 V 0.831 V 1.006 V 1.200 V 1.430 V 1.667 V 1.881 V 2.046 V 2.215 V 2.343 V USB Port Table USB 2.0 EHCI1 USB 3.0 XHCI BTO Option Table Port Port 3 External USB Port BTO Item USB Port (3.0 left front) USB Port (3.0 left back) USB Port(Right 2.0) Mini Card (WLAN+BT) Touch Screen Camera USB Port (3.0 left front) USB Port (3.0 Left back) BOARD ID Table Board ID PCB Revision 0.1 0.2 0.3 0.4 0.5 1.0 Unpop Connector UMA Component GPU On Board HDD Wire HDD EMI Component EMI Reserve ESD Component ESD Reserve TPM Module VRAM Selection DGPU_IDEN CPU_IDEN GC6 2.0 non GC6 EA40 VA50 Power BTN for debug For 15" V3 series G-Sensor BOM Structure @ CONN@ UMA@ VGA@ HDD1@ HDD2@ EMI@ XEMI@ ESD@ XESD@ TPM@ X76@ VGL@, VGM@, SGT@ HW@, BW@ GC6@ NGC6@ 1DMIC@ 2DMIC@ DB@ V3@ GSEN@ Compal Electronics, Inc Compal Secret Data Security Classification Issued Date 2014/09/16 2014/05/24 Deciphered Date Notes List Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size DocumentNumber AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C D A4WAB M/B LA-C341P Wednesday, March 18, 2015 Sheet E Rev 0.2 of 56 A B C D E 2.2K 2.2K F2 PCH_I2C0_SDA F3 PCH_I2C0_SCL +3VS ohm ohm Touch Screen 2.2K 2.2K G4 PCH_I2C1_SDA F1 PCH_I2C1_SCL 2.2K +3VS +3V_PTP 2.2K D_CK_SDAT A DMN63D8LDW PTP D_CK_SCLK Dual channel NMOS 2.2K SOC 2.2K AH1 PCH_SMB_DAT A AP2 PCH_SMBCLK 2.2K +3VALW_PCH +3VS 2.2K D_CK_SDAT A 2 SODIMM DMN63D8LDW D_CK_SCLK Dual channel NMOS G-sensor 2.2K 2.2K AK1 SOC_SML0DAT A AN1 SOC_SML0CLK +3VALW_PCH 2.2K 2.2K BH10 SOC_SML1CLK BG12 SOC_SML1DAT A 2.2K +3VALW_PCH 2.2K KBC SDA1 @ ohm DMN63D8LDW DP to CRT CRT EC_SMB_DA2 Dual channel NMOS 2.2K SCL1 +HDMI_5V_OUT 2.2K @ ohm EC_SMB_CK2 +3VALW_EC 77 EC_SMB_CK1 100 ohm 78 EC_SMB_DA1 100 ohm EC SM Bus1 address EC SM Bus2 address BATTERY CONN Device Address Smart Battery 0x16 Device Address On Board Thermal Senser 0x96 VGA Internal Thermal Senser 0x9E KB9022 2.2K 2.2K 2.2K SCL2 SDA2 79 80 +3VS 2.2K PCH SM Bus address +3VSDGPU_AON Device EC_SMB_CK2 EC_SMB_DA2 DMN63D8LDW Address ChannelA DIMM 1010 0000 JDIMM ChannelB DIMM 1010 0010 JDIMM VGA Dual channel NMOS Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2013/04/12 2014/04/12 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size DocumentNumber AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C D SMB/I2C A4WAB M/B LA-C341P Wednesday, March 18, 2015 Sheet E Rev 0.2 of 56 A B VR_ON ISL95813HRZ-T (PU801) +3VSDGPU_MAIN_EN RT8813AGQW (PU1201) +1.5VS_DGPU_PW R_EN ADAPTER SY8208DQNC (PU101) SUSP# SY8208DQNC (PU601) +19VB BATTERY SYSON 12000mA D E +CPU_CORE +VGA_CORE +1.5VSDGPU +1.05VSP +1.35VP RT8207MZQW (PU501) SUSP# C +0.675VP CHARGER SPOK SY8208DQNC +5VALWP (PU402) SUSP# +5VS TPS22966DPUR U11 +3VLP +3VS SPOK SY8208DQNC +3VALWP (PU401) R-Short (R126) +3V_SPI JUMP (J8) +3VALW_PCH R-Short (R126) +5VS_HDD JUMP (J8) +5VS_ODD PCH_ENVDD +LCDVDD (U8) LAN_PW R_EN U2504 or R2551 +3V_LAN 3 W LAN_ON +3V_WLAN U9 or R 4 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2013/04/12 2014/04/12 Deciphered Date Power Rail Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size DocumentNumber AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C D A4WAB M/B LA-C341P Wednesday, March 18, 2015 Sheet E Rev 0.2 of 56 D D U1A C54 C55 B58 C58 B55 A55 A57 B57 SOC_DP1_N0 SOC_DP1_P0 SOC_DP1_N1 SOC_DP1_P1 DP to CRT C51 C50 C53 B54 C49 B50 A53 B53 CPU_DP2_N0 CPU_DP2_P0 CPU_DP2_N1 CPU_DP2_P1 CPU_DP2_N2 CPU_DP2_P2 CPU_DP2_N3 CPU_DP2_P3 HDMI BDW_ULT_DDR3L(Interleaved) DDI1_TXN0 DDI1_TXP0 DDI1_TXN1 DDI1_TXP1 DDI1_TXN2 DDI1_TXP2 DDI1_TXN3 DDI1_TXP3 eDP reserve to support 4K2K EDP_TXN0 EDP_TXP0 EDP_TXN1 EDP_TXP1 DDI EDP_TXN2 EDP_TXP2 EDP_TXN3 EDP_TXP3 EDP DDI2_TXN0 DDI2_TXP0 DDI2_TXN1 DDI2_TXP1 DDI2_TXN2 DDI2_TXP2 DDI2_TXN3 DDI2_TXP3 EDP_AUXN EDP_AUXP EDP_RCOMP EDP_DISP_UTIL C45 B46 A47 B47 EDP_TXN0 EDP_TXP0 EDP_TXN1 EDP_TXP1 C47 C46 A49 B49 eDP Panel EDP_TXN2 EDP_TXP2 EDP_TXN3 EDP_TXP3 A45 B45 EDP_AUXN EDP_AUXP D20 A43 EDP_COMP R1 24.9_0402_1% +VCCIOA_OUT Trace width=20 mils,Spacing=25mil,Max length=100mils C C OF 19 BDW-ULT-DDR3L-IL_BGA1168 @ +1.35V +1.05VS_VTT R184 470_0603_5% R68 62_0402_5% DIMM_DRAMRST# H_PROCHOT# ESD@ C95 C96 1U_0402_16V7K ESD@ T20 T2 H_PECI @ @ D61 K61 N62 R8 56_0402_5% H_PROCHOT#_R K63 1U_0402_16V7K 1U_0402_16V7K R6 ESD@ C60 BDW_ULT_DDR3L(Interleaved) U1B 10K_0402_5% H_CPUPWRGD C61 PROC_DETECT CATERR PECI PROCHOT PROCPWRGD MISC PRDY PREQ PROC_TCK PROC_TMS PROC_TRST PROC_TDI PROC_TDO JTAG THERMAL R11 R13 R41 B 1 200_0402_1% SM_RCOMP0 AU60 120_0402_1% SM_RCOMP1 AV60 100_0402_1% SM_RCOMP2 AU61 DIMM_DRAMRST#AV15 DDR_PG_CTRL AV61 DDR_PG_CTRL SM_RCOMP0 SM_RCOMP1 SM_RCOMP2 SM_DRAMRST SM_PG_CNTL1 XDP_PRDY#_R XDP_PREQ#_R XDP_TCK_R XDP_TMS_R XDP_TRST#_R XDP_TDI_R XDP_TDO_R @ @ @ @ @ @ @ T157 T158 T159 T160 T161 T162 T163 @ @ T164 T165 PW R BPM#0 BPM#1 BPM#2 BPM#3 BPM#4 BPM#5 BPM#6 BPM#7 Close to AV15 DDR3 Compensation Signals Trace width=12~15 mil, Spcing=20 mils Max trace length= 500 mil J62 K62 E60 E61 E59 F63 F62 DDR3L J60 H60 H61 H62 K59 H63 K60 J61 XDP_BPM#0_R XDP_BPM#1_R @ T148 @ T149 @ T150 @ T151 @ T152 @ T153 B OF 19 BDW-ULT-DDR3L-IL_BGA1168 @ U1 U1 U1 PCB A4WAB LA-C341P LS-C341P CPU_Boardwell intel QH18 i3 2.0G QH18@ CPU_Boardwell intel QH17 i5 2.0G QH17@ CPU_Boardwell intel QH15 i7 2.2G QH15@ DAZ1C700100 SA000083D40 SA000083C10 SA000083A10 U1 U1 U1 CPU_Boardwell intel SR244 i3 2.0G SR244@ CPU_Boardwell intel SR23Yi5 2.2G SR23Y@ CPU_Boardwell intel SR23W i7 2.4G SR23W@ SA000083EB0 SA000089960 SA000089A70 ZZZ A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2014/09/16 A 2014/05/24 Deciphered Date Title BDW MCP(1/11) DDI,MSIC,XDP THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size DocumentNumber AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A4WAB M/B LA-C341P Wednesday, March 18, 2015 Sheet Rev 0.2 of 56 DDR interleave routing D DDR interleave routing U1D U1C DDR_A_D[0 15] DDR_A_D[16 31] C DDR_A_D[32 47] DDR_A_D[48 63] B DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63 AH63 AH62 AK63 AK62 AH61 AH60 AK61 AK60 AM63 AM62 AP63 AP62 AM61 AM60 AP61 AP60 AY58 AW58 AY56 AW56 AV58 AU58 AV56 AU56 AY54 AW54 AY52 AW52 AV54 AU54 AV52 AU52 AY31 AW31 AY29 AW29 AV31 AU31 AV29 AU29 AY27 AW27 AY25 AW25 AV27 AU27 AV25 AU25 AY23 AW23 AY21 AW21 AV23 AU23 AV21 AU21 AY19 AW19 AY17 AW17 AV19 AU19 AV17 AU17 SA_DQ0 SA_DQ1 SA_DQ2 SA_DQ3 SA_DQ4 SA_DQ5 SA_DQ6 SA_DQ7 SA_DQ8 SA_DQ9 SA_DQ10 SA_DQ11 SA_DQ12 SA_DQ13 SA_DQ14 SA_DQ15 SA_DQ16 SA_DQ17 SA_DQ18 SA_DQ19 SA_DQ20 SA_DQ21 SA_DQ22 SA_DQ23 SA_DQ24 SA_DQ25 SA_DQ26 SA_DQ27 SA_DQ28 SA_DQ29 SA_DQ30 SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37 SA_DQ38 SA_DQ39 SA_DQ40 SA_DQ41 SA_DQ42 SA_DQ43 SA_DQ44 SA_DQ45 SA_DQ46 SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55 SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63 SA_CLK#0 SA_CLK0 SA_CLK#1 SA_CLK1 SA_CKE0 SA_CKE1 SA_CKE2 SA_CKE3 SA_CS#0 SA_CS#1 SA_ODT0 SA_RAS SA_WE SA_CAS SA_BA0 SA_BA1 SA_BA2 SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7 SA_MA8 SA_MA9 SA_MA10 SA_MA11 SA_MA12 SA_MA13 SA_MA14 SA_MA15 DDR CHANNEL A SA_DQSN0 SA_DQSN1 SA_DQSN2 SA_DQSN3 SA_DQSN4 SA_DQSN5 SA_DQSN6 SA_DQSN7 SA_DQSP0 SA_DQSP1 SA_DQSP2 SA_DQSP3 SA_DQSP4 SA_DQSP5 SA_DQSP6 SA_DQSP7 SM_VREF_CA SM_VREF_DQ0 SM_VREF_DQ1 AU37 AV37 AW36 AY36 SA_CLK_DDR#0 SA_CLK_DDR0 SA_CLK_DDR#1 SA_CLK_DDR1 AU43 AW43 AY42 AY43 DDRA_CKE0_DIMMA DDRA_CKE1_DIMMA AP33 AR32 DDRA_CS0_DIMMA# DDRA_CS1_DIMMA# AP32 @ @ @ SA_CLK_DDR#0 SA_CLK_DDR0 SA_CLK_DDR#1 SA_CLK_DDR1 DDR_B_D[0 15] DDRA_CKE0_DIMMA DDRA_CKE1_DIMMA T0501 T0502 DDRA_CS0_DIMMA# DDRA_CS1_DIMMA# T0503 AY34 AW34 AU34 DDR_A_RAS# DDR_A_WE# DDR_A_CAS# AU35 AV35 AY41 DDR_A_BS0 DDR_A_BS1 DDR_A_BS2 AU36 AY37 AR38 AP36 AU39 AR36 AV40 AW39 AY39 AU40 AP35 AW41 AU41 AR35 AV42 AU42 DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15 AJ61 AN62 AV57 AV53 AW30 AV26 AW22 AV18 DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7 AJ62 AN61 AW57 AW53 AV30 AW26 AV22 AW18 DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7 AP49 AR51 AP51 SM_DIMM_VREFCA SA_DIMM_VREFDQ SB_DIMM_VREFDQ DDR_A_RAS# DDR_B_D[16 31] DDR_A_WE# DDR_A_CAS# DDR_A_BS0 DDR_A_BS1 DDR_A_BS2 DDR_A_MA[0 15] DDR_B_D[32 47] DDR_A_DQS#[0 1] DDR_A_DQS#[2 3] DDR_A_DQS#[4 5] DDR_A_DQS#[6 7] DDR_B_D[48 63] DDR_A_DQS[0 1] DDR_A_DQS[2 3] DDR_A_DQS[4 5] DDR_A_DQS[6 7] SM_DIMM_VREFCA SA_DIMM_VREFDQ SB_DIMM_VREFDQ Trace width >= 10mils DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63 AP58 AR58 AM57 AK57 AL58 AK58 AR57 AN57 AP55 AR55 AM54 AK54 AL55 AK55 AR54 AN54 AK40 AK42 AM43 AM45 AK45 AK43 AM40 AM42 AM46 AK46 AM49 AK49 AM48 AK48 AM51 AK51 AM29 AK29 AL28 AK28 AR29 AN29 AR28 AP28 AN26 AR26 AR25 AP25 AK26 AM26 AK25 AL25 AR21 AR22 AL21 AM22 AN22 AP21 AK21 AK22 AN20 AR20 AK18 AL18 AK20 AM20 AR18 AP18 D BDW_ULT_DDR3L(Interleaved) BDW_ULT_DDR3L(Interleaved) SB_DQ0 SB_DQ1 SB_DQ2 SB_DQ3 SB_DQ4 SB_DQ5 SB_DQ6 SB_DQ7 SB_DQ8 SB_DQ9 SB_DQ10 SB_DQ11 SB_DQ12 SB_DQ13 SB_DQ14 SB_DQ15 SB_DQ16 SB_DQ17 SB_DQ18 SB_DQ19 SB_DQ20 SB_DQ21 SB_DQ22 SB_DQ23 SB_DQ24 SB_DQ25 SB_DQ26 SB_DQ27 SB_DQ28 SB_DQ29 SB_DQ30 SB_DQ31 SB_DQ32 SB_DQ33 SB_DQ34 SB_DQ35 SB_DQ36 SB_DQ37 SB_DQ38 SB_DQ39 SB_DQ40 SB_DQ41 SB_DQ42 SB_DQ43 SB_DQ44 SB_DQ45 SB_DQ46 SB_DQ47 SB_DQ48 SB_DQ49 SB_DQ50 SB_DQ51 SB_DQ52 SB_DQ53 SB_DQ54 SB_DQ55 SB_DQ56 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63 SB_CK#0 SB_CK0 SB_CK#1 SB_CK1 SB_CKE0 SB_CKE1 SB_CKE2 SB_CKE3 SB_CS#0 SB_CS#1 SB_ODT0 SB_RAS SB_WE SB_CAS SB_BA0 SB_BA1 SB_BA2 DDR CHANNEL B SB_MA0 SB_MA1 SB_MA2 SB_MA3 SB_MA4 SB_MA5 SB_MA6 SB_MA7 SB_MA8 SB_MA9 SB_MA10 SB_MA11 SB_MA12 SB_MA13 SB_MA14 SB_MA15 SB_DQSN0 SB_DQSN1 SB_DQSN2 SB_DQSN3 SB_DQSN4 SB_DQSN5 SB_DQSN6 SB_DQSN7 SB_DQSP0 SB_DQSP1 SB_DQSP2 SB_DQSP3 SB_DQSP4 SB_DQSP5 SB_DQSP6 SB_DQSP7 AM38 AN38 AK38 AL38 SB_CLK_DDR#0 SB_CLK_DDR0 SB_CLK_DDR#1 SB_CLK_DDR1 AY49 AU50 AW49 AV50 DDRB_CKE0_DIMMB DDRB_CKE1_DIMMB AM32 AK32 DDRB_CS0_DIMMB# DDRB_CS1_DIMMB# SB_CLK_DDR#0 SB_CLK_DDR0 SB_CLK_DDR#1 SB_CLK_DDR1 @ @ AL32 @ AM35 AK35 AM33 DDR_B_RAS# DDR_B_WE# DDR_B_CAS# AL35 AM36 AU49 DDR_B_BS0 DDR_B_BS1 DDR_B_BS2 AP40 AR40 AP42 AR42 AR45 AP45 AW46 AY46 AY47 AU46 AK36 AV47 AU47 AK33 AR46 AP46 DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15 AM58 AM55 AL43 AL48 AN28 AN25 AN21 AN18 DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7 AN58 AN55 AL42 AL49 AM28 AM25 AM21 AM18 DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7 DDRB_CKE0_DIMMB DDRB_CKE1_DIMMB T0504 T0505 DDRB_CS0_DIMMB# DDRB_CS1_DIMMB# T0506 DDR_B_RAS# DDR_B_WE# DDR_B_CAS# DDR_B_BS0 DDR_B_BS1 DDR_B_BS2 DDR_B_MA[0 15] C DDR_B_DQS#[0 1] DDR_B_DQS#[2 3] DDR_B_DQS#[4 5] DDR_B_DQS#[6 7] DDR_B_DQS[0 1] DDR_B_DQS[2 3] DDR_B_DQS[4 5] DDR_B_DQS[6 7] B OF 19 BDW-ULT-DDR3L-IL_BGA1168 OF 19 BDW-ULT-DDR3L-IL_BGA1168 @ @ A A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2014/09/16 2014/05/24 Deciphered Date Title BDW MCP(2/11) DDRIII THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size DocumentNumber AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A4WAB M/B LA-C341P Wednesday, March 18, 2015 Sheet Rev 0.2 of 56 PCH_RTCX1 RTC X'tal R101 10M_0402_5% Y1 C153 15P_0402_50V8J 32.768KHZ_12.5PF_9H03200042 1 C154 18P_0402_50V8J D PCH_RTCX2 D For BDW, Crystal change to SJ10000LV00 (ESR=50k Ohm) RTC Reset +RTCVCC R69 20K_0402_1% 2 R70 20K_0402_1% C150 1U_0402_6.3V6K C149 1U_0402_6.3V6K PCH_SRTCRST# 1 PCH_RTCRST# @ JCMOS2 0_0603_5% U1E @ JCMOS1 0_0603_5% AW5 AY5 AU6 AV7 AV6 AU7 PCH_RTCX1 PCH_RTCX2 SM_INTRUDER# PCH_INTVRMEN PCH_SRTCRST# PCH_RTCRST# R72 1M_0402_5% JCMOS1 close RAM door RTCX1 RTCX2 INTRUDER INTVRMEN SRTCRST RTCRST C INTVRMEN +RTCVCC R73 R74 1 EC_RTCRST# 330K_0402_5% 330K_0402_5% @ Integrated VRM enable * HL：：Integrated VRM disable S HDA_SDIN0 AW8 AV11 AU8 AY10 AU12 AU11 AW10 AV10 AY8 HDA_BIT_CLK HDA_SYNC HDA_RST# HDA_SDIN0 @ HDA_SDOUT @ @ @ T6 HDA_BCLK/I2S0_SCLK HDA_SYNC/I2S0_SFRM HDA_RST/I2S_MCLK AUDIO HDA_SDI0/I2S0_RXD HDA_SDI1/I2S1_RXD HDA_SDO/I2S0_TXD HDA_DOCK_EN/I2S1_TXD HDA_DOCK_RST/I2S1_SFRM I2S1_SCLK SATA HDA_RST_AUDIO# HDA_BITCLK_AUDIO HDA_SDOUT_AUDIO HDA_SYNC_AUDIO @ SATA0GP/GPIO34 SATA1GP/GPIO35 SATA2GP/GPIO36 SATA3GP/GPIO37 0_0402_5% RP14 EMI@ HDA_RST# HDA_BIT_CLK HDA_SDOUT HDA_SYNC T95 T110 T21 T19 T15 T10 T11 T22 T12 33_0804_8P4R_5% @ @ @ @ @ @ @ @ @ PCH_JTAG_RST# PCH_JTAG_TCK PCH_JTAG_TDI PCH_JTAG_TDO PCH_JTAG_TMS PCH_TCK_JTAGX SATA_RN2/PERN6_L1 SATA_RP2/PERP6_L1 SATA_TN2/PETN6_L1 SATA_TP2/PETP6_L1 SATA_RN3/PERN6_L0 SATA_RP3/PERP6_L0 SATA_TN3/PETN6_L0 SATA_TP3/PETP6_L0 ME Debug R122 HDA_SDO B SATA_RN1/PERN6_L2 SATA_RP1/PERP6_L2 SATA_TN1/PETN6_L2 SATA_TP1/PETP6_L2 Q52 @ L2N7002LT1G_SOT23-3 T7 T8 T9 HDA for AUDIO SATA_RN0/PERN6_L3 SATA_RP0/PERP6_L3 SATA_TN0/PETN6_L3 SATA_TP0/PETP6_L3 RTC D G PCH_INTVRMEN BDW_ULT_DDR3L(Interleaved) +RTCVCC AU62 AE62 AD61 AE61 AD62 AL11 AC4 AE63 AV2 PCH_TRST PCH_TCK PCH_TDI PCH_TDO PCH_TMS RSVD RSVD JTAGX RSVD SATA_IREF RSVD RSVD SATA_RCOMP SATALED JTAG J5 H5 B15 A15 SATA_PRX_DTX_N0 SATA_PRX_DTX_P0 SATA_PTX_DRX_N0 SATA_PTX_DRX_P0 J8 H8 A17 B17 HDD C SATA_PRX_DTX_N1 SATA_PRX_DTX_P1 SATA_PTX_DRX_N1 SATA_PTX_DRX_P1 ODD J6 H6 B14 C15 F5 E5 C17 D17 V1 U1 V6 AC1 PCH_GPIO34 PCH_GPIO35 PCH_GPIO36 PCH_GPIO37 PCH_GPIO34 PCH_GPIO35 PCH_GPIO36 PCH_GPIO37 A12 SATA_IREF L11 @ T13 K10 @ T14 C12 SATA_RCOMP U3 R10 10K_0402_5% R75 R2 @ +1.05VS_ASATA3PLL 0_0603_5% 3.01K_0402_1% +3VS SA TA_RCOMP, IREF Trace width=12~15 mil, Spcing=12 mils Max trace length= 500 mil B RTC Battery OF 19 BDW-ULT-DDR3L-IL_BGA1168 W =20mils trace width 10mil +RTCBATT +CHGRTC D23 @ W =20mils +RTCVCC BAS40-04_SOT23-3 C151 1U_0402_16V7K A A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2014/09/16 2014/05/24 Deciphered Date Title BDW MCP(3/11) RTC,SATA,XDP THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size DocumentNumber AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A4WAB M/B LA-C341P Sheet Wednesday, March 18, 2015 Rev 0.2 of 56 BDW_ULT_DDR3L(Interleaved) U1F D XTAL24_IN 1M_0402_5% R48 PCIE LAN WLAN C2 15P_0402_50V8J C3 15P_0402_50V8J 2 Y2 24MHZ_12PF_X3G024000DC1H CLK_PCIE_LAN# CLK_PCIE_LAN +3VS LAN_CLKREQ# CLK_PCIE_MINI1# CLK_PCIE_MINI1 MINI1_CLKREQ# CLK_PEG_VGA# CLK_PEG_VGA VGA PCH_GPIO23 CLK_PCIE_LAN# CLK_PCIE_LAN R52 CLKOUT_PCIE_N0 CLKOUT_PCIE_P0 PCIECLKRQ0/GPIO18 B41 A41 Y5 PCH_GPIO19 PCH_GPIO19 XTAL24_OUT C43 C42 U2 PCH_GPIO18 PCH_GPIO18 CLKOUT_PCIE_N2 CLKOUT_PCIE_P2 PCIECLKRQ2/GPIO20 B38 C37 N1 CLK_PCIE_MINI1# CLK_PCIE_MINI1 MINI1_CLKREQ# CLK_PEG_VGA# CLK_PEG_VGA VGA_CLKREQ# A39 B39 U5 PCH_GPIO23 B37 A37 T2 A25 B25 XTAL24_IN XTAL24_OUT C35 C34 AK8 AL8 TESTLOW_C35 TESTLOW_C34 TESTLOW_AK8 TESTLOW_AL8 CLOCK SIGNALS CLKOUT_PCIE_N3 CLKOUT_PCIE_P3 PCIECLKRQ3/GPIO21 1 1 2 2 CLKOUT_LPC0 CLKOUT_LPC1 B35 A35 CLKOUT_ITPXDP CLKOUT_ITPXDP_P T16 T17 XCLK_BIASREF R140 R141 R142 R148 AN15 AP15 CLKOUT_LPC_0 CLKOUT_LPC_1 CLKOUT_PCIE_N4 CLKOUT_PCIE_P4 PCIECLKRQ4/GPIO22 XTAL24_IN XTAL24_OUT K21 @ M21 @ C26 RSVD RSVD DIFFCLK_BIASREF CLKOUT_PCIE_N1 CLKOUT_PCIE_P1 PCIECLKRQ1/GPIO19 C41 B42 10K_0402_5% AD1 R78 3.01K_0402_1% +1.05VS_AXCK_LCPLL D 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% R390 R395 CLK_BCLK_ITP# CLK_BCLK_ITP EMI@ 22_0402_5% TPM@ 22_0402_5% @ @ CLK_PCI_LPC CLK_PCI_TPM T184 T183 CLKOUT_PCIE_N5 CLKOUT_PCIE_P5 PCIECLKRQ5/GPIO23 OF 19 BDW-ULT-DDR3L-IL_BGA1168 @ U1G LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 LPC_FRAME# +3VS C LAD0 LAD1 LAD2 LAD3 LFRAME BDW_ULT_DDR3L(Interleaved) LPC SMBUS L2N7002LT1G_SOT23-3 VGA_CLKREQ# 1 D PEG_CLKREQ# AA3 Y7 Y4 AC2 AA2 PCH_SPI_MOSI AA4 PCH_SPI_MISO Y6 PCH_SPI_WP1# PCH_SPI_HOLD1# AF1 PCH_SPI_CLK PCH_SPI_CS0# R115 10K_0402_5% VGA@ Q2 S Pull high @ VGA side G VGA_PWROK LPC_AD0 AU14 AW12 LPC_AD1 AY12 LPC_AD2 AW11 LPC_AD3 LPC_FRAME# AV12 R112 2.2K_0402_5% @ SPI PCH_GPIO11 PCH_SMBCLK PCH_SMBDATA PCH_GPIO60 SOC_SML0CLK SOC_SML0DATA PCH_GPIO73 SOC_SML1CLK SOC_SML1DATA AF2 AD2 AF4 CL_CLK CL_DATA CL_RST C-LINK @ @ @ PCH_GPIO11 PCH_GPIO60 C PCH_GPIO73 T23 T24 T25 OF 19 2 R107 2.2K_0402_5% @ SPI_CLK SPI_CS0 SPI_CS1 SPI_CS2 SPI_MOSI SPI_MISO SPI_IO2 SPI_IO3 AN2 AP2 AH1 AL2 AN1 AK1 AU4 AU3 AH3 SMBALERT/GPIO11 SMBCLK SMBDATA SML0ALERT/GPIO60 SML0CLK SML0DATA SML1ALERT/PCHHOT/GPIO73 SML1CLK/GPIO75 SML1DATA/GPIO74 BDW-ULT-DDR3L-IL_BGA1168 @ SPI ROM +3VALW_PCH SMBUS +3VS B PCH_SPI_IO2_1 PCH_SPI_IO3_1 +3VALW R116 4.7K_0402_5% Q7A L2N7002DW1T1G_SC88-6 +3V_SPI PCH_SMBDATA @ D_CK_SDATA SOC_SML1CLK SOC_SML1DATA R114 R113 B 2.2K_0804_8P4R_5% D_CK_SDATA 0_0402_5% 2.2K_0402_5% 2.2K_0402_5% R126 SOC_SML0CLK PCH_SMBCLK PCH_SMBDATA SOC_SML0DATA R119 4.7K_0402_5% 1K_0402_5% 1K_0402_5% R105 R106 for Share EC ROM, +3VS change to +3VALW +3V_SPI +3VS RP8 +3V_SPI U6 /CS DO(IO1) /WP(IO2) GND VCC /HOLD(IO3) CLK DI(IO0) 1U_0402_16V7K PCH_SPI_IO3_1 PCH_SPI_CLK_1 PCH_SPI_MOSI_1 R108 15_0402_5% PCH_SPI_IO2_1 PCH_SPI_IO3_1 PCH_SPI_CLK_1 PCH_SPI_MOSI_1 PCH_SPI_MISO_1 W25Q64FVSSIQ_SO8 Reserve for EMI(Near SPI ROM) A C152 10P_0402_50V8J 2 PCH_SPI_CLK_1 R104 33_0402_5% XEMI@ XEMI@ PCH_SPI_MOSI_1 PCH_SPI_CLK_1 PCH_SPI_MISO_1 PCH_SPI_CS0# R498 R500 R502 R505 1 1 DDR , G-Sensor PCH_SPI_HOLD1# PCH_SPI_CLK PCH_SPI_MOSI PCH_SPI_MISO EMI@ 15_0804_8P4R_5% 2 2 4D_CK_SCLK D_CK_SCLK Q7B L2N7002DW1T1G_SC88-6 RP19 @ @ @ @ PCH_SMBCLK PCH_SPI_WP1# 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% +3VS SPI ROM Q8A L2N7002DW1T1G_SC88-6 EC_SPI_SO EC_SPI_CLK EC_SPI_SI EC_SPI_CS# SOC_SML1CLK PU 2.2K at EC side (+3VS) From EC (For share ROM) EC_SMB_CK2 PCH_SPI_CS0# PCH_SPI_MISO_1 PCH_SPI_IO2_1 C66 SPI ROM ( 8MByte ) VGA, EC SOC_SML1DATA 10/20: 2015 project not implement auto load, change R498, R500, R502, R502 to non-pop A EC_SMB_DA2 Q8B L2N7002DW1T1G_SC88-6 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2014/09/16 2014/05/24 Deciphered Date Title BDW MCP(4/11) CLK,SPI,SMBUS THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size DocumentNumber AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A4WAB M/B LA-C341P Wednesday, March 18, 2015 Sheet Rev 0.2 of 56 System Power Management R117 PCH_RSMRST# 10K_0402_5% D D +3VALW_PCH ACIN D21 R245 100K_0402_5% @ Note: Deep Sx need use EC GPIO for ACPRESENT function PCH_ACIN DSW ODVREN - On Die DSW VR Enable Enable(DEFAULT) * HL：：Disable RB751V-40SOD-323 U1H @ R65 0_0402_5% R124 R125 SYSTEM POWER MANAGEMENT PCH_PWROK 1 1 @ @ @ @ 2 2 @ 0_0402_5% @ R110 @ 0_0402_5% PCH_RSMRST#_R SUSWARN# 0_0402_5% PBTN_OUT#_R PCH_ACIN 8.2K_0402_5% PCH_BATLOW# T31 @ SUSWARN# R206 R227 +3VS SYS_PWROK R61 R62 PCH_PWROK R63 VCCST_PG_EC SYS_PWROK R207 10K_0402_5% PCH_PWROK_R R64 SUSACK# SYS_RESET# SYS_PWROK_R PCH_PWROK_R PM_APWROK 0_0402_5% 10K_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% R79 C R2634 0_0402_5% R156 +3VALW_PCH SUSACK SYS_RESET SYS_PWROK PCH_PWROK APWROK PLTRST DSWVRMEN DPWROK WAKE CLKRUN/GPIO32 SUS_STAT/GPIO61 SUSCLK/GPIO62 SLP_S5/GPIO63 PLT_RST# PLT_RST# PCH_RSMRST# SUSWARN# PBTN_OUT# AK2 AC3 AG2 AY7 AB5 AG7 AW6 AV4 AL7 AJ8 AN4 AF3 AM5 +RTCVCC BDW_ULT_DDR3L(Interleaved) RSMRST SUSWARN/SUSPWRDNACK/GPIO30 PWRBTN ACPRESENT/GPIO31 BATLOW/GPIO72 SLP_S0 SLP_WLAN/GPIO29 SLP_S4 SLP_S3 SLP_A SLP_SUS SLP_LAN 330K_0402_5% 330K_0402_5% @ AW7 DSWODVREN AV5 PCH_RSMRST#_R AJ5 PCH_PCIE_WAKE# R120 R157 V5 AG4 AE6 AP5 CLKRUN# AJ6 AT4 AL5 AP4 AJ7 PM_SLP_S4# PM_SLP_S3# @ @ PM_SLP_LAN# 1K_0402_5% +3VALW_PCH 8.2K_0402_5% +3VS CLKRUN# SUSCLK PM_SLP_S5# @ @ SUSCLK PM_SLP_S5# T27 T28 T30 T96 R118 @ 10K_0402_5% @ T29 PM_SLP_S4# PM_SLP_S3# C +3VALW_PCH +3VS not support Deep S4,S5 can NC OF 19 P B BDW-ULT-DDR3L-IL_BGA1168 @ PLT_RST_BUF# Y A R416 100K_0402_5% G PLT_RST# U30 @ MC74VHC1G08DFT2G_SC70-5 BDW_ULT_DDR3L(Interleaved) U1I B8 A9 C6 PCH_INV_PWM ENBKL PCH_ENVDD +3VS 10/15 : RP27 pin remove G_SEN_INT# pull high RP27 PCH_GPIO80 MINI1_CLKREQ# DEVSLP0 10K_0804_8P4R_5% MINI1_CLKREQ# DEVSLP0 EC_TP_INT# R210 +3VS R210 NGC6@ R2629 VGA@ D22 R2057 0_0402_5% GC6@ U6 PCH_GPIO77 P4 DGPU_PWR_EN DGPU_HOLD_RST# N4 N2 PCH_GPIO80 AD4 @ T26 RB751V-40_SOD323-2 U7 TP_INT# TP_INT# L1 G_SEN_INT G_SEN_INT L3 Project_ID1 R5 PCH_GPIO51 PCH_GPIO51 L4 Project_ID0 GC6_FB_EN DGPU_PWR_EN DGPU_HOLD_RST# B PCH_GPIO77 10K_0402_5% DGPU_HOLD_RST# 10K_0402_5% UMA@ SD028100280 EDP_BKLCTL EDP_BKLEN EDP_VDDEN PIRQA/GPIO77 PIRQB/GPIO78 PIRQC/GPIO79 PIRQD/GPIO80 PME DDPB_CTRLCLK DDPB_CTRLDATA DDPC_CTRLCLK DDPC_CTRLDATA eDP SIDEBAND DISPLAY PCIE GPIO55 GPIO52 GPIO54 GPIO51 GPIO53 DDPB_AUXN DDPC_AUXN DDPB_AUXP DDPC_AUXP DDPB_HPD DDPC_HPD EDP_HPD C5 B6 B5 A6 SOC_DP1_AUXN SOC_DP1_AUXP C8 A8 D6 B SOC_DP1_AUXN SOC_DP1_AUXP SOC_DP1_HPD CPU_HDMI_HPD CPU_EDP_HPD DDPB_CTRLDATA: Port B Detected OF 19 BDW-ULT-DDR3L-IL_BGA1168 10K_0402_5% +3VS B9 C9 2.2K_0402_5% R271 D9 DDI2_CTRL_CK DDI2_CTRL_CK D11 DDI2_CTRL_DATA DDI2_CTRL_DATA DDPC_CTRLDATA: P ort C Detected @ * 1: Port B or C is detected 0: Port B or C is not detected (Have internal PD) 2 R214 10K_0402_5% R215 10K_0402_5% Project_ID0 Project_ID1 Project ID A @ R204 10K_0402_5% @ R205 10K_0402_5% +3VS +3VS * A4WAB Reserved Reserved Reserved Project_ID1 Project_ID0 GPIO54 GPIO53 0 1 1 A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2014/09/16 2014/05/24 Deciphered Date Title BDW MCP(5/11) PM,GPIO,DDI THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size DocumentNumber AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A4WAB M/B LA-C341P Wednesday, March 18, 2015 Sheet Rev 0.2 10 of 56 A B 100_0402_1% 100_0402_1% EC_SMB_CK1 2 MAINPWON PR212 100K_0402_5% D S G BI_GATE +17.4V_BA TT+ EMI@ PL201 5A_Z120_25M_0805_2P VCC TMSNS1 GND RHYST1 OT1 TMSNS2 OT2 RHYST2 @ PR207 47K_0402_1% @ PH201 100K_0402_1%_NCP15WF104F03RC G718TM1U_SOT23-8 @ @ PU201 PQ201 BSS138LT1G_SOT23-3 @ PR205 10K_0402_1% 1 @ PR206 100K_0402_1% MAINPWON ACES_50458-00801-001 @ PR204 10K_0402_1% +RTCVCC 1 BATT_TEMP 1K_0402_1% PR209 @ PC202 0.1U_0603_25V7K EC_SMB_DA1-1 EC_SMB_CK1-1 BATT_TS BATT_B/I +3VLP 2 PJP201 1 2 3 4 5 6 7 8 GND 10 GND +3VLP EC_SMB_DA1 PR211 6.49K_0402_1% D PR208 PR210 C 2013/10/28 update PH201 chang Common part SL200002H00 +17.4V_BA TT EMI@ PL202 5A_Z120_25M_0805_2P PC201 EMI@ 1000P_0603_50V7K 2 2 PC205 @EMI@ 0.01U_0603_25V7K 2014/09/30 update Active For KB9022 sense 20mΩ Recovery 45W PR202 58.5W,0.61V 45W,0.47V 10K ohm SD034100280 65W PR202 84.5W,0.61V 65W,0.47V 19.1K ohm SD034191280 PH202 under CPU botten side : CPU thermal protection at 90 degree C ( shutdown ) Recovery at 56 degree C +EC_VCCA 2013/10/02 Add for ENE9022 Battery Voltage drop detection Connect to ENE9022 pin64 AD1 65W@ PR202 19.1K_0402_1% +19VB_5V @ PR230 80.6K_0402_1% VCIN0_PH @ PR229 0_0402_5% VCIN1_PROCHOT VCIN1_BATT_DROP 1 PR202 10K_0402_1% 45W@ PR216 18.2K_0402_1% Battery is 3-cell design B+=9V ADP_I B value:4250K±1% @ T201 @ 2013/10/28 update PH202 chang Common part SL200002H00 T202 1 10K_0402_1% 0.1U_0402_25V6 PH202 100K_0402_1%_NCP15WF104F03RC @ PR228 @ PC203 PR203 10K_0402_1% PR225 0_0402_5% For 65W adapter==>action 70W , Recovery 54W For 40W adapter==>action 52W , Recovery 40W 4 @ ECAGND Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2013/10/01 Deciphered Date 2014/05/24 Title BATTERY CONN / OTP THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL DocumentNumber AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C Wednesday, March 18, 2015 D Sheet 43 Rev 1.0 of 56 A B C D PQ301 Protection for reverse input G S 2N7002KW_SOT323-3 PR302 3M_0402_5% +19V_P2 ILIM 10 SDA SCL @ PR324 316K_0402_1% 1 +3VALW PR316 316K_0402_1% +19V_VIN PC320 0.01U_0402_25V7K BQ24725A_ACDET EC_SMB_DA1 @ PR320 0_0402_5% ADP_I PQ307 LTC015EUBFS8TL_UMT3F PR323 100K_0402_1% EC_SMB_CK1 PC322 100P_0402_50V8J 1 PR319 66.5K_0402_1% 1 2 BATT_4S 2 PC321 2200P_0402_50V7K PR321 2M_0402_1% PR322 @ 0_0402_5% Vin Dectector D G SUSP# PQ308 S 2N7002KW_SOT323-3 L >H H >L Min 17.16V 16.76V Typ 17.63V 17.22V PC323 @ 100P_0402_50V8J 2 PC315 10U_0805_25V6K 1 PC314 10U_0805_25V6K CSON1 PR311 0.01_1206_1% **Design Notes** #For 65 /90W system, 3S1P/3S2P battery Maximum Charging current 3.5A Battery discharge power 55W #Register Setting 0X12 bit8 set (default 1) to disable IFAULT HI if add ISN choke 0X12 bit3 set (default 0) to enable turbo boost function Disable turbo when AC only #Circuit Design ACOK,ILIM pull high voltage need base on 3/5V enable control Use 10X10 choke and 3X3 H/L side MOSFET Charge current 3.5A Power loss : 1.82W Power density : 0.81 (15X15) If use 4S per cell 4.35V battery, need additional circuit for ACDET(PR218/PR220/PR222 change to 0.1%, parallel resistors with PR222 for ACDET setting) PC223 2200p is for quick response when AC plug out For hybrid design, need double check PQ202,PQ203,PQ204,PQ205 component rating #Protect function ACOVP : ACDET voltage > 3.14V Charger timeout : No communication within 175s(default) ACOC : 3.33 X Input current DAC setting(default) CHGOCP : 3/4.5/6A based on current current setting BATOVP : 103-106% BATLOWV : 2.5V TSHUT : 155C IFAULT HI : 750mV (default) IFAULT LOW : 110mV (default) Max 18.12V 17.70V Compal Secret Data Security Classification VILIM = 20*ILIM*Rsr ILIM = 3.3*100/(100+316)/20/0.01 = 3.966 A Issued Date 2013/10/01 Deciphered Date 2014/05/24 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A PC307 0.01U_0402_50V7K CSOP1 1 PR312 4.7_1206_5% @EMI@ CHG1 PC316 0.1U_0402_25V6 2 +17.4V_BATT Close EC chip PQ305 MDV1528URH_PDFN33-8-5 PC319 0.1U_0603_16V7K PR318 422K_0402_1% 2 BQ24725A_BATDRV +3VLP PR317 100K_0402_1% For 4S per cell 4.35V battery PL302 10UH_PCMB063T-100MS_4A_20% 11 BQ24725A_ILIM BQ24735A_V2.mdd ACIN BATDRV Support max charge 3.5A Power loss: 0.245W CSR rating: 1W VSRP-VSRN spec < 81.28mV 7*7*3 SRN ACOK 2013/11/29 update PL302 change Common part SH00000YB00 PC318 680P_0402_50V7K @EMI@ ACDRV 2BQ24725A_BATDRV_1 12 PR313 10_0603_1% CSOP1 SRP1 PR314 6.8_0603_1% CSON1 SRN1 14 13 SRP DL_CHG PQ306 MDV1528URH_PDFN33-8-5 15 16 CMSRC BQ24725A_ACDET PR305 4.12K_0603_1% BQ24725A_LX GND IOUT BQ24735A_V1.mdd 100K_0402_1% PC313 1U_0603_25V6K ACP Module model information PR315 @ PR308 0_0603_5% 1 LODRV BQ24725A_IOUT +3VLP DH_CHG ACN ACDET BQ24725A_ACDRV BQ24725A_REGN PD302 RB751V-40_SOD323-2 REGN PR307 2.2_0603_5% BQ24725A_BST BTST DH_CHG 18 17 BQ24725A_LX VF = 0.37V BQ24735RGRR_QFN20_3P5X3P5 BQ24725A_CMSRC 2 PAD HIDRV 19 PU301 20 1U_0603_25V6K BQ24725A_BATDRV Rds(on) = 30mohm max Vgs = 20V Vds = 30V ID = 7A (Ta=70C) PC311 0.047U_0402_25V7K PHASE 2 1 BQ24725A_VCC2 1 PC312 21 VF = 0.5V PD301 BAS40CW_SOT323-3 VCC PC309 0.1U_0402_25V6 PR310 4.12K_0603_1% BQ24725A_ACN BQ24725A_ACP PR309 4.12K_0603_1% PC308 0.1U_0402_25V6 BQ24725A_ACDRV_1 +19V_VIN @EMI@PC306 0.1U_0402_25V6 Isat: 4A DCR: 27mohm 2 PQ304 AON7506_DFN33-8-5 +19VB_CHG EMI@ PL301 1UH +-30% 2.8A EMI@ PC305 2200P_0402_25V7K PR303 0.02_1206_1% 1 PC310 0.1U_0402_25V6 @ PR304 0_0402_5% PC302 0.1U_0402_25V6 PQ302 MDU1512RH_POWERDFN56-8-5 PC301 2200P_0402_50V7K 2 +19V_P1 PC304 10U_0805_25V6K PQ303 MDV1526URH_PDFN33-8-5 2014/09/30 update PQ303&PQ304 change Common part SB0000010A00 2014/01/21 update PL301 change Common part SH00000YG00 PC303 10U_0805_25V6K +19V_VIN Need check the SOA for inrush PR306 10_1206_1% 1M_0402_5% PC317 0.1U_0402_25V6 PR301 2013/10/14 PR303 10m ohm chang >20m ohm +19VB SD00000S120 Vgs = 20V Vds = 60V Id = 250mA D B C Compal Electronics, Inc Document Number CHARGER Rev 1.0 Common Circuit Wednesday, March 18, 2015 D Sheet 44 of 56 A B C D E Module model information SY8208B_V2.mdd SY8208C_V2.mdd EN1 and EN2 dont't floating +19VB 3.3V LDO 150mA~300mA PC426 4.7U_0402_6.3V6M PC409 22U_0603_6.3V6M PC408 22U_0603_6.3V6M PC410 22U_0603_6.3V6M +3V AL WP @ PJ401 2 +3VALW JUMP_43X118 @ PR407 0_0603_5% PC416 0.1U_0603_25V7K +5V AL WP @ PJ402 2 +5VALW JUMP_43X118 BS VL @ PC427 22U_0603_6.3V6M @ PC428 22U_0603_6.3V6M PC423 22U_0603_6.3V6M PC422 22U_0603_6.3V6M PC421 22U_0603_6.3V6M 21 PC420 22U_0603_6.3V6M 16 +5V ALWP 35.2 17 PR408 @EMI@ @EMI@ PC419 5V LDO 150mA~300mA LDO 15 18 PC424 4.7U_0603_6.3V6M FF PL404 1.5UH_6A_20%_5X5X3_M LX_5V 4.7U_0603_6.3V6M NC GND 14 NC OUT VCC 19 680P_0603_50V7K 4.7_1206_5% IN PG 5*5*3 20 Vout is 4.998V~5.202V Ipeak=7A Imax=4.9A Iocp=10A PC413 PR406 1000P_0402_25V8J 1K_0402_5% 2 5V_FB 5V_EN IN GND ENLDO_3V5V PR409 2.2K_0402_5% @ PR410 0_0402_5% LX GND 13 10 GND 11 @ PR413 0_0402_5% IN IN LX EN1 SPOK LX EN2 12 LX_5V 5V_EN @EMI@ PC418 0.1U_0402_25V6 EMI@ PC417 2200P_0402_50V7K PC415 10U_0805_25V6K Ipeak=7A Imax=4.9A Iocp=10A PU402 SY8286CRAC_QFN20_3X3 PR411 1M_0402_1% BST_5V Vout is 3.234V~3.366V PC402 PR403 1000P_0402_25V8J 1K_0402_5% 2 3V_FB +19VB_5V @ PC407 22U_0603_6.3V6M PC411 4.7U_0402_6.3V6M @EMI@ PC412 680P_0603_50V7K 13V_SN 21 +19VB_5V EMI@ PL403 5A_Z120_25M_0805_2P 2 150K_0402_1% PR404 +3VLP 16 +3V ALWP 35.2 @EMI@ PR405 4.7_1206_5% 17 PL402 1.5UH_6A_20%_5X5X3_M LX_3V 18 NC 19 15 12 11 20 PC425 15V_SN +19VB PC414 10U_0805_25V6K GND +19VB 3V_EN NC Check pull up resistor of SPOK at HW side EC_ON LDO NC SPOK MAINPWON PC403 0.1U_0603_25V7K BS PG PR412 100K_0402_5% @ PR401 0_0603_5% BST_3V1 ENLDO_3V5V +3V ALWP IN GND OUT GND EN2 LX 14 10 LX GND FF LX 13 IN LX_3V IN IN PC405 10U_0805_25V6K @EMI@ PC401 0.1U_0402_25V6 EMI@ PC404 2200P_0402_50V7K +19VB_3V PU401 SY8286BRAC_QFN20_3X3 EN1 EMI@ PL401 5A_Z120_25M_0805_2P 2 PR402 499K_0402_1% ENLDO_3V5V 1 EC VDD0 is +3VL, PC426 UNPOP EC VDD0 is +3VALW, PC426 POP Compal Secret Data Security Classification 2013/10/01 Issued Date 2014/05/24 Deciphered Date Title Compal Electronics, Inc +3VALW/+5VALW THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size DocumentNumber AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C D Wednesday, March 18, 2015 Rev 1.0 Sheet E 45 of 56 Module model information RT8207M_V1.mdd RT8207M_V2.mdd For Single layer For Dual layer D D Note: S3 - sleep ; S5 - power off PR507 887K_0402_1% +19VB_1.35V PC507 10U_0805_6.3V6K VTT +1.35VP FB PR506 8.2K_0402_1% PC510 0.033U_0402_16V7K +1.35VP B @ PR509 0_0402_5% MOSFET: 3x3 DFN H/S Rds(on): 27mohm(Typ), 34mohm(Max) L/S Rds(on): 22mohm(Typ), 13.5mohm(Max) @ PC514 0.1U_0402_16V4Z @ PR510 0_0402_5% SUSP# DDR_VTT_PG_CTRL @ PR511 0_0402_5% @ PJ501 +1.35VP Switching Frequency: 285kHz Ipeak=5.4A Delta I =4.4A Iocp=9.15~6.58A OVP: 110%~120% VFB=0.75V, Vout=1.364V PR508 10K_0402_1% 2 SYSO N Choke: 7x7x3 Rdc=8.3mohm(Typ), 10mohm(Max) VTTREF_1.35V 20 19 VLDOIN 18 BOOT VTTREF_1.5V off on on +0.75VSP off off on 2 Level L L H 17 +5VALW Mode S5 S3 S0 FB_1.35V PQ502 SI7716ADN-T1-GE3_POWERPAK8-5 2013/10/14 update PQ502 AON7702A EOL change >AON7506_SB000010A00 B C 2.2_0402_1% PR505 21 2014/10/09 Vout=0.675V Imax=0.84A Via=2 PC513 1U_0603_10V6K VDDQ S3 VDD EN_0.675VSP 11 VDD_1.35V VTTREF S5 VDDP TON 1 +5VALW GND RT8207MZQW_WQFN20_3X3 CS 12 UGATE 16 13 PR504 5.1_0603_5% @EMI@ PC512 680P_0402_50V7K @EMI@ PR503 4.7_1206_5% + PC511 330U_2.5V_ESR17M_6.3X4.5 VTTSNS 35.4 CS_1.35V PC508 1U_0603_10V6K PAD VTTGND PGND EN_1.35V LGATE TON_1.35V PR502 13.7K_0402_1% PQ501 MDV1528URH_PDFN33-8-5 15 PHASE DL_1.35V PU501 PC506 10U_0805_6.3V6K 2014/10/16 update Setting OCP PR502 >9.1K 2014/10/09 Vout=1.35V Imax=3.78A Via=8 +0.675VSP PGOOD PC505 10U_0805_25V6K +1.35VP +1.35VP SW_1.35V 14 PL502 1.5UH_9A_20%_7X7X3_M 1.01% BOOT_1.35V PC501 0.1U_0603_25V7K 1.364V DH_1.35V Common Part ESR=15m ohm BST_1.35V C H=4.5 SF000002Z00 0.75Volt +/- 5% TDC 0.7A Peak Current 1A PR501 2.2_0603_5% PC504 10U_0805_25V6K 2 2014/10/09 Vin=14.8V Iin=0.431A Via=2 (No includ +0.675VSP) +19VB_1.35V 10 EMI@ PC503 2200P_0402_50V7K @EMI@ PC502 0.1U_0402_25V6 +19VB Pin19 need pull separate from +1.5VP If you have +1.5V and +0.75V sequence question, you can change from +1.5VP to +1.5VS EMI@ PL501 5A_Z120_25M_0805_2P 2 +1.35V JUMP_43X118 @ PJ502 @ PC515 0.1U_0402_16V4Z 1 2 JUMP_43X118 @ A5WAH PVT: ESD request add 0.1u +0.675VSP PJ503 2 +0.675VS JUMP_43X39 A Compal Secret Data Security Classification Issued Date 2013/10/01 Deciphered Date 2014/05/24 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Compal Electronics, Inc +1.35VP/+0.675VSP Size Document Number Custom Date: A Wednesday, March 18, 2015 Rev 1.0 Sheet 46 of 56 D D Module model information SY8208D_V1.mdd EN pin don't floating If have pull down resistor at HW side, pls delete PR2 VC CS T _ PW R G D PR608 10K_0402_5% +3VS C EMI@ PL601 5A_Z120_25M_0805_2P @ PC602 0.22U_0402_10V6K PC614 1U_0402_6.3V6K NC PAD @ PR607 16 1 (R1) PR606 15.4K_0402_1% PL602 from SH00000PJ00 change to common part SH00000YE00 2013/10/23 PC613 2.2U_0402_6.3V6M @ @ PC616 22U_0603_6.3V6M BYP 12 PC615 22U_0603_6.3V6M NC 10 PC612 22U_0603_6.3V6M ILMT +1.05VSP PCMB063T-1R0MS12A LDO_3V 1.01% 2 NC 17 1.062V PC611 22U_0603_6.3V6M VCC EN FB_1.05V GND FB LX_1.05V PC610 22U_0603_6.3V6M GND 20 14 LX PL602 GND TDC 8A 19 PC609, PC610 from 47U_0603_6.3V6M change to 22U_0603_6.3V6M 2013/10/23 21 SY8288RAC_QFN20_3X3 2 15 +3VALW PR606 part count reduce ILMT_1.05V PR603 1M_0402_1% 0_0402_5% 1 @ PR605 13 LX BST_1.05V PC609 22U_0603_6.3V6M 11 ILMT_1.05V IN 18 @ PR602 0_0402_5% LX BS IN PC608 330P_0402_50V7K PG IN @EMI@ PR604 @EMI@ PC603 4.7_1206_5% 680P_0603_50V7K 2SNB_1.05V IN PC601 0.1U_0603_25V7K 1 10U_0805_25V6K PC604 @ PR601 0_0603_5% 2 S U SP # LDO_3V C PU601 +19VB_1.05V @EMI@ PC606 0.1U_0402_25V6 EMI@ PC605 2200P_0402_50V7K +19VB FB = 0.6V 0_0402_5% PR609 20K_0402_1% B VFB=0.6V Vout=0.6V* (1+R1/R2) Vout=1.062V +1.05VSP (R2) PJ601 2 JUMP_43X118 +1.05VS_VTT @ B Module model information The current limit is set to 8A, 12A or 16A when this pin is pull low, floating or pull high SY8208D_V1.mdd A A Compal Secret Data Security Classification Issued Date 2013/10/01 Deciphered Date 2014/05/24 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title +1.05VSP Size C Date: Compal Electronics, Inc Document Number Rev 1.0 Wednesday, March 18, 2015 Sheet 47 of 56 2014/10/09 Vin=3.3V Iin=0.091A Via=2 @ PJ701 JUMP_43X39 D PC702 1U_0402_6.3V6K D 1 Rup PC704 0.01U_0402_25V7K @ PJ702 2 +1.5VS 2014/10/09 Vout=1.5V Imax=0.161A Via=2 PC705 22U_0603_6.3V6M Rdown +1.5VSP JUMP_43X39 2 GND 1.053% +1.5VSP PU701 G971ADJF11U_SO8 VO ADJ 1 VEN PR705 22.6K_0402_1% 2 PR704 47K_0402_5% PC701 0.1U_0402_16V7K SUSP# VO 1.507V PR703 20K_0402_1% VIN TPAD VPP POK PC703 4.7U_0805_6.3V6K Ultra Low Dropout 0.23V(typical) at 3A Output Current PR701 100K_0402_5% +3VS +5V ALW C C Vout=0.8V* (1+Rup/Rdown) Ultra Low Dropout 0.23V(typical) at 3A Output Current B B A A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2013/10/01 2014/05/24 Deciphered Date Title +1.5VSP THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL DocumentNumber AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: Rev 1.0 Wednesday, March 18, 2015 Sheet 48 of 56 Base on BDW PDDG Rev_0_73 Module model information: ISL95813 (for 15W & 28W CPU) 15W Location D PC802 1U_0402_6.3V6K PR802 130_0402_1% PR803 54.9_0402_1% VR_SVID_DATA Note: VR_SVID_ALRT# Pull high on HW side H-side MOS: MDV1525URH Rds(on):