Lời giải chương 7 Counters and Registers bộ môn Hệ thống số

Lời giải chương 7 Counters and Registers bộ môn Hệ Thống Số. Lời giải bao gồm các bài tập trong sách Digital Systems Principles and Applications 11th edition giúp sinh viên rèn luyện thêm khả năng tư duy giải bài tập

Instructor's Resource Manual – Digital Systems Principles and Applications - 11th edition CHAPTER SEVEN - Counters and Registers 7.1 (a) 250 kHz; 50% (b) same as (a) (c) MHz (d) 32 7.2 Need to divide by 64; use MOD-64, 6-bit counter 7.3 100002 7.4 (a) 1024 (b) 250 Hz (c) 50% (d) 3E8 7.5 1000 and 0000 states never occur 7.6 (a) 12.5 MHz (b) 8.33 MHz 7.7 (a) See schematic (b) 33 MHz A B C D ABCD ABC A AB A B B C E J D CLK E J C CLK K D CLR J B J CLK K C CLR A CLK K CLR B K CLR J CLK A K CLR CLK 7.8 (a) Add one more FF & gate to Problem 7-7(a) schematic (b) 33 MHz A ABCDE F B C D E J CLK F K CLR CLK _ 101 Instructor's Resource Manual – Digital Systems Principles and Applications - 11th edition 7.9 (a) CLK A B C D (b) (c) (d) Frequency at D = 100 Hz 0010 0101 7.10 (a) CLK A B C D (b) (c) (d) Frequency at D = 5000 Hz 1000 1011 7.11 Replace 4-input NAND with a 3-input NAND driving all FF CLRs and whose inputs are Q5, Q4, and Q1 7.12 Q5 Q4 Q3 Q2 Q1 Q0 Q4Q3Q2Q1 Q0 Q3 Q2 Q1 Q0 Q2 Q1 Q0 Q1 Q0 Q0 10 kHz Q6 J CLK Q5 J CLK K CLR Q4 J CLK K CLR Q3 J CLK K CLR Q2 J CLK K CLR Q1 Q0 J CLK K CLR J CLK K K CLR CLR MHz Q6 Q5 Q2 _ 102 Instructor's Resource Manual – Digital Systems Principles and Applications - 11th edition 7.13 _ A _ B _ C _ ABCD _ A _ B _ C _ ABC D E J D CLK E J K D _ B C J CLK CLR _ A AB B J CLK K C K CLR A CLK B K CLR J CLK A CLR K CLR CLK 7.14 dir C B A _ C B A B A _ B _ A A _ A C C J CLK _ C J B J CLK _ C K CLR A CLK K CLR _ B K CLR J CLK _ A K CLR CLOCK 7.15 Counter switches states between 000 and 111 on each clock pulse 7-16 CLK PL 101 010 Q0 Q1 Q2 _ 103 Instructor's Resource Manual – Digital Systems Principles and Applications - 11th edition 7.17 CLK _ CLR _ LOAD ENT ENP DCBA 0111 1101 QD QC QB QA RCO 7.18 CLK _ CLR _ LOAD ENT ENP DCBA 0110 0101 0100 QD QC QB QA RCO _ 104 Instructor's Resource Manual – Digital Systems Principles and Applications - 11th edition 7.19 CLK _ D/U _ LOAD _ CTEN QD QC QB QA MAX/MIN RCO 7.20 CLK _ D/U _ LOAD _ CTEN QD QC QB QA MAX/MIN RCO 7.21 (a) (b) (c) (d) 7.22 (a) (b) (c) (d) 0000, 0001, 0010, 0011, 0100, 0101, 0110, 0111, 1000, 1001, 1010, 1011, & repeat MOD-12 frequency at QD (MSB) is 1/12 of CLK frequency 33.3% 0000, 0001, 0010, 0011, 0100, 0101, 0110, 1001, 1010, 1011, 1100, 1101, 1110, 0001, & repeat MOD-12 frequency at QD (MSB) is 1/12 of CLK frequency 50% _ 105 Instructor's Resource Manual – Digital Systems Principles and Applications - 11th edition 7.23 (a) CLK QA QB QC QD (b) (c) (d) MOD-10 10 down to Can produce MOD-10, but not same sequence 7.24 (a) Output will be 0000 as long as ST ART is LOW (b) Counter will count from 0000 up to 1001 on each CLK pulse and stop at 1001 (c) MOD-10; it is a self-stopping counter not a recycling counter 7.25 (a) (b) _ 106 Instructor's Resource Manual – Digital Systems Principles and Applications - 11th edition 7.26 (a) (b) (c) _ 107 Instructor's Resource Manual – Digital Systems Principles and Applications - 11th edition 7.27 CLK 74HC161 CLK ENT ENP _ CLR _ LOAD EN _ CLR 74HC161 CLK ENT ENP _ CLR _ LOAD RCO RCO 0 D C QD QC Q3 Q2 0 D C QD QC Q6 (MSB) 0 B A QB QA Q1 Q0 0 B A QB QA Q5 Q4 Q6 Q5 Q1 Q0 7.28 CLK 74ALS160 or 74ALS162 EN 1 LD CLK ENT ENP _ CLR _ LOAD 74ALS160 or 74ALS162 RCO 1 CLK ENT ENP _ CLR _ LOAD RCO D3 D QD Q3 D7 D QD Q7 D2 C QC Q2 D6 C QC Q6 D1 B QB Q1 D5 B QB Q5 D0 A QA Q0 D4 A QA Q4 ten's digit 7.29 Output: Frequency: Duty Cycle: QA MHz 50% QB 1.5 MHz 50% QC 750 kHz 50% QD 375 kHz 50% RCO 375 kHz 6.25% 7.30 Output: Frequency: Duty Cycle: QA MHz 50% QC 600 kHz 40% QD 600 kHz 20% RCO 600 kHz 10% Output QB has an irregular pattern _ 108 Instructor's Resource Manual – Digital Systems Principles and Applications - 11th edition 7.31 Frequency at fout1 = 500 kHz, at fout2 = 100 kHz 7.32 Frequency at fout1 = 100 kHz, at fout2 = 10 kHz 7.33 12M/8 = 1.5M 1.5M/10 = 150k 1.5M/15 = 100k 1.5MHz 74HC162 CLK ENT ENP U1 _ CLR _ LOAD 74HC163 12MHz CLK ENT ENP U1 _ CLR _ LOAD RCO D C QD QC B A QB QA RCO D C QD QC B A QB QA 150kHz 74HC163 CLK 1 ENT ENP U2 _ CLR _ LOAD RCO D C QD QC B A QB QA 100kHz _ 109 Instructor's Resource Manual – Digital Systems Principles and Applications - 11th edition 7.34 12M/12 = 1M 12M/15 = 800k 800k/8 = 100k 74HC161 12MHz 74HC161 CLK ENT ENP U1 _ CLR _ LOAD CLK ENT ENP U2 _ CLR _ LOAD RCO D C QD QC B A QB QA RCO 800kHz 74HC161 D C B QD QC QB A QA CLK ENT ENP U1 _ CLR _ LOAD RCO D QD C B A QC QB QA 100kHz 1MHz 7.35 _ D C B A _ D C B A D C B A D C B A 12 _ D C B A _ D C B A D C B A D C B A 13 _ D C B A _ D C B A D C B A 10 D C B A 14 _ D C B A _ D C B A D C B A 11 D C B A 15 7.36 _ D C B A _ D C B A _ D C B A _ D C B A _ D C B A _ D C B A _ D C B A D C B A _ D C B A D C B A _ 110 Instructor's Resource Manual – Digital Systems Principles and Applications - 11th edition The register is cleared immediately when Master Reset is active 7.66 CP _ MR D5 - D0 110011 010010 101001 010110 001110 100011 Q5 Q4 Q3 Q2 Q1 Q0 clock pulses are needed to serially load a 74166 since there are FFs in the chip 7.67 7.68 CLK CLR SER QH _ 139 Instructor's Resource Manual – Digital Systems Principles and Applications - 11th edition 7.69 CP SH/LD P0 - P7 1100 1010 0011 0101 (Q0) (Q1) (Q2) (Q3) (Q4) (Q5) (Q6) Q7 7.70 CLK CLK INH SH/LD CLR ABCD EFGH 0101 0011 1001 0010 SER (QA) (QB) (QC) (QD) (QE) (QF) (QG) QH _ 140 Instructor's Resource Manual – Digital Systems Principles and Applications - 11th edition 7.71 (a) (b) asynch True part (c) (d) (e) (f) (g) 7.72 (a) (b) (c) (d) (e) (f) (g) (h) Starting at: 1011 1011 1011 1011 1011 After CLK: 0111 0101 0110 1011 0111 After CLKs: 1111 0010 0110 1011 1110 After CLKs: 1111 0001 0110 1011 1101 After CLKs: 1111 0000 0110 1011 1011 Loads 00000000 Loads 11111111 Shifts in a Shifts in a Output will change states if input is switched to the same logic level (in = out) Input logic level must be maintained for at least clock pulses The output will not switch states Output will not switch states until input signal is stable; pulsing input condition will not be recognized 7.73 +VCC 1k 74ALS14 0.001 F PRE J PRE Q4 CLK K PRE Q3 J CLK Q4 CLR J K PRE Q2 CLK Q3 K CLR PRE Q1 CLK Q2 CLR J K Q0 CLK Q1 CLR J K Q0 CLR CLK _ 141 Instructor's Resource Manual – Digital Systems Principles and Applications - 11th edition 7.74 +VCC 1k 74ALS14 0.001 F +VCC PRE J PRE Q4 J CLK PRE Q3 J CLK K Q4 K CLR PRE Q2 J CLK Q3 J CLK K CLR PRE Q1 Q2 J CLK K CLR PRE Q0 Q1 K CLR Q5 CLK Q0 K CLR Q5 CLR +VCC CLK Q5 Q4 Q5 Q3 Q5 Q2 Q5 Q1 Q5 Q0 Q5 Q4 Q5 Q3 Q5 Q2 Q5 Q1 Q5 Q0 7.75 +VCC 1k 74ALS14 CLK 0.001 F CLK CLR 74HC164 A & B Q0 Q1 Q0 Q4 Q0 Q4 Q0 Q1 Q1 Q0 Q0 Q1 Q2 Q2 Q2 Q2 Q3 Q3 Q1 Q1 Q4 Q5 Q6 Q7 Q4 Q3 Q3 Q2 Q2 Q4 Q4 Q3 Q3 7.76 Hz, 50% duty cycle 7.77 output of 3-in AND or J, K inputs to FF D shorted to ground, FF D output shorted to ground, CLK input on FF D open, B input to NAND is open 7.78 Output of 2-input AND or J, K inputs shorted to VCC, output from 2-input AND is open _ 142 Instructor's Resource Manual – Digital Systems Principles and Applications - 11th edition 7.79 (a) (b) SUBDESIGN siso8_ahdl ( clk, en, ser :INPUT; qout :OUTPUT; ) VARIABLE q[7 0] :DFF; BEGIN q[].clk = clk; qout = q0.q; IF (en == GND) THEN q[7 0].d = (ser, q[7 1].q); ELSE q[7 0].d = (q[7 0].q); END IF; END; ENTITY PORT ( siso8_vhdl IS clk, en, ser :IN BIT; qout :OUT BIT ); END siso8_vhdl; ARCHITECTURE vhdl OF siso8_vhdl IS BEGIN PROCESS (clk) VARIABLE q :BIT_VECTOR (7 DOWNTO 0); BEGIN qout q(7 DOWNTO 4)); lsn: univ_shift_vhdl PORT MAP (clock => clock, din => din(3 DOWNTO 0), ser_in => ser_lsn, mode => mode, q => q(3 DOWNTO 0)); END byte; ENTITY univ_shift_vhdl IS PORT ( clock :IN BIT; din :IN BIT_VECTOR (3 DOWNTO 0); ser_in :IN BIT; mode :IN INTEGER RANGE TO 3; q :OUT BIT_VECTOR (3 DOWNTO 0)); END univ_shift_vhdl; ARCHITECTURE vhdl OF univ_shift_vhdl IS BEGIN PROCESS (clock) VARIABLE ff :BIT_VECTOR (3 DOWNTO 0); BEGIN IF (clock'EVENT AND clock = '1') THEN CASE mode IS WHEN => ff := ff; hold data WHEN => ff(2 DOWNTO 0) := ff(3 DOWNTO 1); shift right ff(3) := ser_in; WHEN => ff(3 DOWNTO 1) := ff(2 DOWNTO 0); shift left ff(0) := ser_in; WHEN => ff := din; parallel load END CASE; END IF; q