Chapter Eight Conclusion A study of the hot-carrier performance in advanced NMOSFET is presented in this thesis. The focus is on the understanding of the physical mechanisms involving the hot-carrier induced degradation observed in the experiments. These mechanisms are unique in advanced devices, as the level of supply voltage is lower than the oxide potential barrier. This thesis is divided into three major parts. The first part deals with the shift in the worst-case hot-carrier degradation in deep submicrometer n-channel transistors. By applying a reverse bias to the substrate during hot-carrier stress, the population of high-energy-tail electrons increases and as a result the shift is observed. The corresponding degradation could not be explained on the basis of the classical model where the maximum amount of damage occurred at the maximum substrate current. It is observed that there is negligible increase in substrate current while the gate current could increase about two orders of magnitude. We attribute the increased injection efficiency of gate current to the increasingly attractive oxide field near the drain region as Vg approaches Vd. We argue that the degradation as a result of other mechanisms such as substrate hot-electron injection, which only contributed to less than pA increase in Icp., hardly explains the extent of the observed parametric shift when the substrate bias is applied. This strongly suggests the increased injection efficiency of Chapter Conclusion 198 the gate current is mainly responsible for the shift in the worst-case hot-carrier degradation. The reduction in the oxide potential barrier as indicated by the slope n, again lending support to more favorable condition for electron to inject over the barrier. Making use of the above conclusion, we evaluated the role of high-energy tail electrons in NMOSFET degradation in the sub-3 V regime. The interface trap generation, monitored via the charge-pumping technique, revealed a composite interface trap generation mode. Our analysis indicated that a significant part of the interface trap generated in the 2-3 V stress Vd regime is contributed by the majority of the channel electrons. However, the growing influence of high-energy tail electrons is evident when the stress Vd is decreased. As a result of this composite interface trap generation mode, the accuracy of the hot-carrier reliability projections maybe greatly affected. The second part of the thesis discusses the characteristics of more advanced device such as the strained-Si/SiGe NMOSFET. The initial focus is to establish the importance of dopant profile on the electrical characteristics of narrow width transistor. It was implied that the abundance of interstitials located at the STI/active regions enhanced the diffusion of boron towards these corners. Thus, it resulted in the contrasting trend in the width dependence of threshold voltage relative to bulk Si. Similarly, the importance of dopant diffusivity in strained-Si/SiGe demarcated the behavior of high-energy tail electrons in strained-Si/SiGe with respect to that in bulk Si. Our finding indicated that these electrons are significantly lessened when the reverse bias is applied to the substrate. In order to establish the main hot-carrier degradation mechanism in strained-Si, the effects related to the underlying SiGe is studied in detail since thermal conductivity of this alloy is approximately fifteen times lower than that of the crystalline silicon. High channel temperature arises from poor heat dissipation in the thin strained-Si film when the device is electrically biased or more commonly known as the self-heating effect is observed. We adopted a simple Chapter Conclusion 199 and yet realistic technique to measure the channel temperature of the strained-Si/SiGe devices, which agrees with the experimental results. This technique is of reasonable accuracy when compared to a well-established pulse I-V measurement method. Based on this measurement, it was found that the channel temperature in the strained-Si/SiGe NMOSFET is significantly higher than that in the bulk Si devices when the devices are subjected to hot-carrier stress. With the above finding on the channel temperature, we focus on the parametric degradation of the strained-Si/SiGe transistor subjected to the channel hot-electron stress. Our results revealed that the channel is substantially damaged even at short stress interval. Through critical analysis, a mechanism solely responsible for this nonlocalized interface state generation is singled out. This mechanism involves the highenergy tail electrons present in the channel and the number of these electrons increases with channel temperature. This mechanism is further supported by the evidence of lower degradation for transistors under ac stress with smaller duty cycle. This has a practical implication. If we were to subject transistors with high channel temperature (eg. SOI, strained-Si/SiGe, SGOI, HVMOS, etc.) to hot-carrier stress, we could obtain a wide spread increase of interface trap density in the channel and therefore the application of classical hot-carrier mechanisms has to be reconsidered. The last part of the thesis focuses on the physical analysis via energy dispersive x-ray spectrometry of the strained-Si/SiGe devices, particularly, the interface between strained-Si and underlying SiGe alloy layer. A comparison was made between the stressed devices and that of the fresh ones. We observed significant fractional increase in Ge concentration near the surface, especially those in the channel where the temperature is highest. Furthermore, the strained-Si/SiGe interface after hot-carrier stress is no longer abrupt. On the other hand, the interface state generation as a result of this Ge outdiffusion is negligibly small. Thus, its effect on the identified mechanism remains secondary. Chapter Conclusion 200 In future work, the focus shall be on the process of the device on various substrates so that theories presented in this work can be tested. For instance, the channel temperature can be measured on devices fabricated on SSGOI (StrainedSi/SiGe-On-Insulator) or SOI with source/drain SiGe stressor wafers. The SSGOI and SOI with source/drain stressor are expected to have higher channel temperature, and hence more Ge outdiffusion during stress. Moreover, for the discussion on the shift in worst-case hot-carrier degradation, the dependence of the dielectric can be confirmed experimentally, if more combinations of the device gate oxide materials are available. The theory developed in this work can also be further refined. List of Publications [1] D. S. Ang, T. W. H. Phua, H. Liao, and C. H. Ling, “High-energy tail electrons as the mechanism for the worst-case hot-carrier stress degradation of the deep submicrometer NMOSFET,” IEEE Electron Device Lett., vol. 24, pp. 469-471, Jul. 2003. [2] D. S. Ang, H. Liao, T. W. H. Phua and C. H. Ling, “Evidence for a composite interface state generation mode in the CHE-stressed deep-submicrometer nMOSFET,” IEEE Trans. Electron Devices, vol. 51, pp. 2246-2248, Dec. 2004. [3] W. H. T. Phua, D. S. Ang, C. H. Ling, and K. J. Chiu, “STI-induced damage and hot-carrier reliability in the narrow width short channel NMOSFET fabricated using global strained-Si technology,” Proceedings of European Solid-State Device Research Conference. pp. 533-536, 2005. [4] T. W. H. Phua, D. S. Ang, and C. H. Ling, “Self-heating induced Germanium outdiffusion and non-local channel degradation in the strained-Si/SiGe NMOSFET subjected to channel hot-electron stress,” Proceedings of the International Conference on Solid State Devices and Materials, p. E-5-2, 2006. [5] D. S. Ang, T. W. H. Phua, and C. H. Ling, “Self-heating induced spatial spread of interface state generation by hot-electron effect: Role of the high-energy tail electron,” IEEE Electron Device Lett., accepted for publication. . A study of the hot-carrier performance in advanced NMOSFET is presented in this thesis. The focus is on the understanding of the physical mechanisms involving the hot-carrier induced degradation. Conclusion 198 the gate current is mainly responsible for the shift in the worst-case hot-carrier degradation. The reduction in the oxide potential barrier as indicated by the slope n, again lending. importance of dopant diffusivity in strained-Si/SiGe demarcated the behavior of high-energy tail electrons in strained-Si/SiGe with respect to that in bulk Si. Our finding indicated that these electrons