Hot carrier mechanisms in advanced NMOS transistors 3

Chapter Two Experimental Setup Hot-carrier stress is known to generate interface traps and oxide charge near the drain region of the MOS transistor [1]. It is essential to study the influence of these defects on the device operation. The degradation of key transistor parameters such as threshold voltage, subthreshold leakage current, transconductance, etc. have been well characterized, both as a function of time and stress voltages [2]-[5]. As a matter of fact, there is a standard protocol documented by Joint Electron Device Engineering Council (JEDEC) on the characterization of hot-carrier degradation in MOS transistors. This well-recorded procedure is widely used by the industry to assess the impact of hotcarrier degradation on new technologies or products with a set of criteria. It is of great interest that the experiments conducted in this work adhered to this standard methodology. On the other hand, due to the generality of the protocol, characterization techniques such as that used to measure interface state generation or that used to derive hot-carrier damage locations are not compulsory criteria to assess the hot-carrier resilient of new technologies. It should, however, be highlighted that these techniques probe the fundamental reliability physics involved in the hot-carrier stress degradation. Chapter Experimental Setup 59 This chapter offers an overview of the experiment setup used in this work for the hot-carrier characterization of NMOSFET. In the first section, the schematic of the automated measurement setup is discussed. Next, the concept of charge-pumping technique that is used to characterize interface state generation is elaborated. This is followed by a brief illustration of an improved method to measure interface traps in ultra-thin oxide. Lastly, a consistent and reliable technique used to probe the damage creation in the channel and that under the spacer region is illustrated. 2.1 Automated Measurement Setup A series of hot-carrier stress experiments were carried out via an automated measurement setup. A block diagram of the measurement system is exhibited in Fig. 2.1. The setup mainly consists of (i) a pulse generator (HP8112A), (ii) a semiconductor parameter analyzer (HP4156A), (iii) a temperature controller (KT-20) and (iv) a lowtemperature micromanipulator prober. The last two items are provided by MMR Technologies Inc. The automation is controlled through the personal computer via the IEEE-488 standard interface. The prober includes a refrigerator stage, where the sample is placed. This stage also allows the temperature to be varied over a wide range, from as low as 77 to 573 K. High-vacuum thermal grease is used to minimize thermal resistance. A vacuum pump is connected to the prober, which has the ability to provide a moderate vacuum level of less than 10 mTorr. This allows the desired local ambient temperature to fluctuate within a range of ±0.1 K. Nonetheless, temperatures below 273 K are not utilized in this thesis. Chapter Experimental Setup 60 Personal Computer IEEE-488 Bus Controller IEEE-488 BUS Voltage Waveform Generator (HP8112A) Semiconductor Parameter Analyzer (HP4156A) Output Temperature Controller (KT-20) SMU Triaxial and Coaxial Connector Interface S G D B Low-Temperature Micromanipulator Prober Rotary Vacuum Pump Fig. 2.1 Block diagram of the experimental setup adopted in the study of hot-carrier effects in MOSFET. The HP4156A semiconductor parameter analyzer from Hewlett-Parkard is used to perform all current-voltage measurements. This equipment has the capability to perform low current measurement using the Kelvin probe technology [6], with a resolution of fA. In our experiment setup considering the prober and all the connections, the best sensitivity achieved is about fA. Good quality triaxial and coaxial cables are used to minimize leakage and noise. The prober is further insulated from external interferences via a grounded Faraday cage. The HP8112A pulse generator Chapter Experimental Setup 61 is used in the charge pumping current measurements, allowing the flexibility in manipulating the waveform characteristics. The details of charge-pumping technique shall be elaborated in the next section. 2.2 Charge-pumping Current as a Measure of Interface State Generation The damage created near the drain region does not allow a straightforward measure of interface traps via current-voltage measurements [7]. Fortunately, a consistent and reliable method called charge-pumping (CP) technique was later evolved to characterize the interface state generation [8]. As a matter of fact, this technique is widely used to monitor the interface traps generation during hot-carrier stress [9]-[11]. Owing to its simple implementation and direct relation to interface trap density, this method serves as a sensitive tool to quantify the localized oxide damage. Fig 2.2 shows the charge-pumping measurement configuration. The gate terminal of the transistor is connected to a pulse generator and an oscilloscope. A reverse bias is applied to the source and drain diode junction, at the same time, the substrate current is monitored. By pulsing the gate terminal of the transistor between inversion and accumulation via a trapezoidal waveform, the subsequent charging and discharging of the interface traps yield a substrate recombination current. This current is directly proportionate to the trap density, gate area and the pulse frequency and is given as I cp = qfWLN it (2.1) where q is the electron charge, f is the frequency, W is device width, L is device length, Nit is the interface trap density [14] Chapter Experimental Setup 62 Pulse Generator Oscilloscope Gate Source Oxide N+ Drain N+ P-Substrate DC Ammeter Fig. 2.2 Basic experimental setup for charge pumping measurement [8]. Fig. 2.3 Schematics showing the measurement method used in NMOSFET. By varying the pulse base level Vbase with constant amplitude, five operating regions are established [8]. Chapter Experimental Setup 63 The salient feature of this technique is the unique characteristics of the substrate current or charge pump current (Icp) as a function of the base level (Vbase) of the gate pulse as shown in Fig. 2.3. There are five operating regions that can explain the different behavior of substrate current at various base levels of the gate pulse. These five regions will be briefly discussed. 1) Region (Icp = Icp,max): When the base level (Vbase) is lower than the flat-band voltage (Vfb) while the top level of the pulse (Vtop) is higher than the threshold voltage (Vt), the conventional CP effects occurs. In other words, a net amount of charge is transferred (“pumped”) from the source and drain to the substrate via the fast interface traps whenever the transistor is pulsed from inversion towards accumulation and back. It is worth mentioning that the threshold voltage in a CP curve must be defined as the gate voltage at which the free electron concentration at the surface (ne) is sufficiently large so that the fast interface traps below the Fermi level can capture electrons during the time the gate voltage is applied. The time constant for electron capture (determined by the gate pulse frequency) is given by τe = υ th ⋅ σ n ⋅ ne (2.2) where υth is the thermal carrier velocity, σn is the capture cross section for electron, and ne is the electron concentration at the surface. Assuming σn = σp where σp is the capture cross section for hole, flat-band voltage can be defined as the gate voltage that accumulates the same amount of holes at the same given gate pulse frequency. Chapter Experimental Setup 2) 64 Regions and (Icp = 0): In region 2, the top and base levels of the gate pulse train are below the flat-band voltage. Hence, the fast interface traps are permanently filled with holes. As a result, no recombination current is measured. In region 3, the channel is permanently under inversion mode, so no holes could reach the surface at anytime. The measured substrate current consists of only the source and drain leakage currents in both cases. 3) Regions and (0 < Icp < Icp,max): In region 4, the CP current increases from zero (region 2) to a saturation level (region 1). From the concept of CP effect, it is easily understood that the recombination process disappears when transitioning from region to region 2. This is because the electron concentration at the interface during the inversion part of the gate pulse reduces significantly when the top level does not reach Vt. In other word, the rising edge of the Icp curve is located at Vt - ∆VA where VA is the amplitude of the gate pulse. Hence, the recombination process in weak inversion would determine the profile of the CP current in this transition zone. Similarly, the falling edge of the CP characteristic is located at Vfb, since the recombination current disappears when the channel can no longer be flooded with holes. Fig. 2.4 (a) shows the comparison between measured and calculated characteristics of the CP curve. Indeed, the profile matches the five distinctive regions described above. However, it was observed that the rising and falling edges of the experimental CP curve are not symmetrical. This asymmetry is caused by larger than expected rise in CP current at the lower base level of the gate pulse. The major reason for this phenomenon was attributed to the spatial variation of the surface potential or Chapter Experimental Setup 65 the lateral variation of Vt and Vfb near the source and drain junction as depicted in Fig. 2.4 (b). (a) (b) Fig. 2.4 (a) Comparison between experimental charge-pumping curve and that of the calculated one, taking into account the recombination process in weak inversion and accumulation (b) results of MINIMOS simulations for threshold and flat-band voltages, as defined by the capture time for electrons and holes, respectively, as a function of the distance from a source or drain junction along the channel. ∆l is the region in the vicinity of the junction where charge pumping occurs for a gate pulse amplitude ∆VA [8]. Chapter Experimental Setup 66 Fig. 2.4 (b) shows the simulated surface potential in the vicinity of the source and drain junctions. It was explained that the fast interface traps located at a certain position in the channel or in the source or drain region will contribute to the CP current when the gate pulse is such that the base level of the pulse is below the local flat-band voltage, while the top level is above the local threshold voltage. Thus, for a certain gate pulse amplitude ∆VA, the total area of the channel (∆l times the device width W) that contributes to the pumping current can be extracted for each gate pulse base level. In order words, the additional current component at the rising transition of the CP curve arises from the earlier “onset” of the recombination process occurring near the source and drain regions. In order to reduce this additional current, a reverse bias applied at source and drain terminals of the transistor is thus needed [8]. Fig. 2.5 Summary of the expected influence of the interface trapped charge on the CP curve. Curve a is the CP curve for a low interface trap density; curve b for a high density of donor-type interface traps; curve c for a high density of acceptor-type interface traps [8]. Apart from the different rising and falling slope, the shape of the CP curve can be commonly observed in most MOS transistors. Nevertheless, when the transistors are subjected to stress condition, this profile is distorted. In relation to damage creation Chapter Experimental Setup 67 during electrical stress, an increase in the level of the Icp indicates an increase of the interface trap concentration. In addition, a shift of the edges toward more negative voltages is indicative for a net positive charge at the interface, while a shift to more positive voltages indicates the presence of a net negative charge as shown in Fig. 2.5. This behavior of Icp is easy to interpret when degradation is uniformly distributed in the transistor. Unfortunately, in the case where the transistor is under hot-carrier stress condition, the damage created in the channel is highly localized. This yielded a distortion of the Icp versus Vbase curve. Although such a distorted curve contains much information of interest, it is often difficult to interpret [8]-[11]. The challenge in this technique arises from the fact that both the flat band voltage Vfb and threshold voltage Vt are probed at the same time. They usually have different lateral distributions across the channel as shown in Fig. 2.4 (b). As a result, it is difficult, if not impossible, to segregate the Vfb and Vt from Icp versus Vbase curves. Fortunately, Chen et al. presented an improved version of the method by keeping the base level constant and vary the top level of the gate pulses as illustrated in Fig. 2.6 [12]. As a result of this constant gate base approach, only the part of the channel where Vt is covered by the top level can contribute to Icp. In other words, each increase in top level covers an additional incremental portion of the channel. This would give an incremental charge pumping current ∆ Icp corresponding to the interface traps in that portion of the channel. Thus, this technique is very suitable for characterizing hot-carrier induced degradation. In retrospect, it was cautioned that the presence of oxide trapped charges and the reverse bias applied at the source and drain junctions could vary the Vfb and Vt lateral profiles in the channel. As a result, the actual Icp could be distorted by contributions from Chapter Experimental Setup 68 these effects when the constant base approach is used. In spite of this, this method has since served as a framework for subsequent work in improving the efficiency of the charge-pumping technique. (a) (b) Fig. 2.6 Schematic illustration of the principle of the technique. (a) Vh of the gate pulse string is lower than flatband voltage and the varying Vh probes the interface traps in regions that have threshold voltages lower than Vh. (b) shows the Icp versus Vh curve and its derivative. Take for instance, Lee et al. provided a more straightforward setup by keeping source and drain biased at zero volts [13][14]. In doing so, the variation of Vfb and Vt near the source and drain regions during inversion and accumulation half cycles could be prevented, making the analysis of the measured interface trap density more meaningful. Despite of the popularity of the constant base approach, it faces another challenge as the CMOS technology continues to scale, especially the thinning down of gate dielectric. In principle, charge-pumping technique does not take into account of the gate Chapter Experimental Setup 69 leakage current when calculating interface trap density. This leakage current, however, cannot be ignored when the gate dielectric is below nm as depicted in Fig. 2.7 [15]. As the oxide thickness is reduced to 1.2 nm, the leakage current tunneling between the gate and substrate became significant. This will affect the calculation accuracy of the interface traps since it is proportional to the value of measured Icp. In order to remove the leakage current during the CP measurement, a dual frequencies methodology was developed [15]. Fig 2.8 shows the CP characteristics measured at two different frequencies and the resultant CP curve after adopting the dual frequencies approach. By subtracting the leakage component measured at low frequency from that measured at high frequency, the constant base CP technique could still be useful to monitor the interface properties in the ultra thin oxide regime. For the devices used in this thesis, the gate oxide thickness is nm. Hence, the constant base approach was adopted since the leakage component is not significant. Fig. 2.7 Measured CP current for ultra thin (12-16 A) gate oxide. Note that 12 A gate has large leakage currents for Vgh < 0V [15]. Chapter Experimental Setup 70 Fig. 2.8 Shows the dual frequency methodology- Using two-leakages CP curves to obtain a correct CP curve [15]. 2.3 Method to Probe Hot-Carrier Damage in a Transistor Charge-pumping technique is a powerful tool that probes the oxide interface properties and it was even adopted in reliability physics studies for sub-nanometer technology [15][17]. The wide application of this approach includes lateral profiling or the time-evolution of interface state generation during hot-carrier stress [12][14]. Nonetheless, additional and complex simulation work is needed if these approaches are used in device characterization. As a result, simple and direct methods are desirable to provide reliable analysis. Indeed, the novel work by Ang et al. can help to resolve the complexity involved in simulation and yet provides the damage location as a result of hot-carrier stress [17]. This method can probe the hot-carrier damage in regions under the spacer and that in the gate overlap. The principle of this method is based on the change in resistance in the channel and that in the drain regions with hot-carrier stress degradation. By extracting the drain current at two different gate voltages from the drain current versus gate voltage (IdVg) curve, the degradation in these regions could be quantified as depicted in Fig. 2.9. Chapter Experimental Setup 71 Fig. 2.9 Linear drain current degradation as a function of stress time, monitored at high and low gate bias Vg for different stress drain voltages [17]. Fig. 2.9 shows the fractional shift in the drain current measured in the linear region as a function of hot-carrier stress duration. The drain current degradation was extracted at high (6 V) and low (1 V) Vg regimes. The drain current extracted at high Vg probes the degradation under the spacer oxide, while the drain current extracted at low Vg regime probes the damage at the gate overlap region. The linear current degradation measured at high Vg is the result of drain series resistance increasing more than channel resistance when the transistor is under hot-carrier stress. The increase in the former has been attributed to interface state generation in the spacer. On the other hand, mobility degradation by interface traps located in the overlap/channel region has been responsible for the drain current degradation at low Vg [17]. This original work was indeed a simple approach with no additional simulation work needed to characterize interface state generation in various regions of the transistor. As a matter of fact, it was also used to characterize new hot-carrier injection mode for memory devices [18]. Hence, it is intuitive to use this approach in this thesis. Chapter Experimental Setup 72 2.4 Summary A general overview of the measurement setup used in this work is provided. This setup is able to monitor the change in transistor electrical parameters with hot-carrier stress. Apart from the measurement of transistor’s current-voltage characteristics, the setup was able to measure interface trap density via charge-pumping technique. The classic concept of this method was described for pulses having constant amplitude applied at the gate terminal. However, interpreting data measured via this approach remains a challenge especially when the degradation is non-uniform. In an attempt to provide more straightforward analysis, the constant gate base methodology was introduced [12]. In other words, charge-pumping current is measured with the base level of the gate pulse kept constant while the top level is varied. The increase in top level of the gate pulse corresponds to the additional interface trap measurement area in the channel. Thus, the incremental increase in charge-pumping current is interpreted as the interface traps present in that portion of the channel. This technique was well received for hot-carrier investigations since the analysis of the data for non-uniform degradation is simple. From then on, significant improvement has been made on this approach and it was even applied in sub-nanometer transistor characterization. It is worth to mention that the work by Lee et al. helped to eliminate the profile variation of Vfb and Vt near the source and drain junctions [13]. In reality, this technique was used in this thesis. Although the charge-pumping technique is able to characterize oxide interfacial properties, additional work is needed if information such as the damage creation site is required. Complex modeling involving physical channel dimension and time scale proved Chapter Experimental Setup 73 to be tedious for such information to be extracted via charge-pumping method. This shortfall was, nevertheless, addressed by the original work by Ang et al. [17]. The degradation in the gate overlap region and that under the spacer oxide was quantified via the simple resistance-based measurement. This reliable technique was used in this work especially in the characterization of damage location when the transistor is subjected to hot-carrier stress. Chapter Experimental Setup 74 2.5 References [1] P. Heremans, R. Bellens, G. Groeseneken, and H. E. Maes, “Consistent model for the hot-carrier degradation in n-channel and p-channel MOSFET’s,” IEEE Trans. Electron Devices, vol. 35, pp. 2194-2209, Dec. 1988. [2] E. Takeda, and N. Suzuki, “An empirical model for device degradation due to hot-carrier injection,” IEEE Electron Device Lett., vol. 4, pp. 111-113, Apr. 1983. [3] C. Hu, S. C. Tam, F. –C. Hsu, P. K. Ko, T. –Y. Chan, and K. W. Terrill, “Hotelectron-induced MOSFET degradation – Model, monitor, and improvement,” IEEE Trans. Electron Devices, vol. 32, pp. 375-385, Feb. 1985. [4] M. Brox, A. Schwerin, Q. Wang, and W. Weber, “A model for the time- and biasdependent of p-MOSFET degradation,” IEEE Trans. Electron Devices, vol. 41, pp. 1184-1196, Jul. 1994. [5] R. Woltjer, A. Hamada, and E. Takeda, “Time dependence of p-MOSFET hotcarrier degradation measured and interpreted consistently over tens of order of magnitude,” IEEE Trans. Electron Devices, vol. 40, pp. 392-401, Feb. 1993. [6] “HP4156A Precision Semiconductor Parameter Analyzer – User’s Manual”, Hewlett Parkard, 1995. [7] H. Haddara, and S. Cristoloveauu, “Two-dimensional modeling of locally damaged short-channel MOSFET’s operating in the linear region,” IEEE Trans. Electron Devices, vol. 34, pp. 378-385, Feb. 1987. Chapter Experimental Setup [8] 75 P. Heremans, J. Writters, G. Groeseneken, and H. E. Maes, “Analysis of the charge pumping technique and its application for the evaluation of MOSFET degradation,” IEEE Trans. Electron Devices, vol. 36, pp. 1318-1335, Jul. 1989. [9] M. G. Ancona, N. S. Saks, and D. McCarthy, “Lateral distribution of hot-carrierinduced interface traps in MOSFET’s,” IEEE Trans. Electron Devices, vol. 35, pp. 2221-2228, Dec. 1988. [10] M. Brox, A. Schwerin, Q. Wang, and W. Weber, “A model for the time- and biasdependent of p-MOSFET degradation,” IEEE Trans. Electron Devices, vol. 41, pp. 1184-1196, Jul. 1994. [11] M. Tsuchiaki, H. Hara, T. Morimoto, and H. Iwai, “A new charge pumping method for determining the spatial distribution of hot-carrier induced fixed charge in p-MOSFET’s,” IEEE Trans. Electron Devices, vol. 40, pp. 1768-1779, Aug. 1993. [12] W. Chen, A. Balasinski, and T. P. Ma, “Lateral profiling of oxide and interface traps near MOSFET junctions,” IEEE Trans. Electron Devices, vol. 40, pp. 187196, Jan. 1993. [13] R. G.-H. Lee, J. -S. Su, and S. S. Chung, “A new method for characterizing the spatial distributions of interface states and oxide-trapped charges in LDD nMOSFET’s,” IEEE Trans. Electron Devices, vol. 43, pp. 81-89, Jan. 1996. Chapter Experimental Setup [14] 76 R. G.-H. Lee, J. -P. Wu, and S. S. Chung, “An efficient method for characterizing time-evolutional interface states and its correlation with the device degradation in LDD nMOSFET’s ,” IEEE Trans. Electron Devices, vol. 43, pp. 898-903, Jun. 1996. [15] S. S. Chung, H. J. Feng, Y. S. Hsieh, A. Liu, W. M. Lin, D. F. Chen, J. H. Ho, K. T. Huang, C. K. Yang, O. Cheng, Y. C. Sheng, D. Y. Wu, W. T. Shiau, S. C. Chien, K. Liao, and S. W. Sun, “Low leakage reliability characterization methodology for advanced CMOS with gate oxide in the nm range,” in Proc. Int. Electron Devices Meeting Tech. Digest, pp. 477-480, 2004. [16] S.S. Chung, Y.R. Liu, S.J. Wu, C.S. Lai, Y.C. Liu, D.F. Chen, H.S.Lin, W.T. Shiau, C.T. Tsai, S.C. Chien, S.W. Sun, “A new insight into the degradation mechanisms of various mobility-enhanced CMOS devices with different substrate engineering,” in Proc. Int. Electron Devices Meeting Tech. Digest, pp. 4, 2005. [17] D. S. Ang, and C. H. Ling, “A unified model for the self-limiting hot-carrier degradation in LDD n-MOSFET’s,” IEEE Trans. Electron Devices, vol. 45, pp. 149-159, Jan. 1998. [18] F. Driussi, D. Esseni, and L. Selmi, “On the electrical monitor for device degradation in the CHISEL stress regime,” IEEE Electron Device Lett., vol. 5, pp. 357-359, May. 2003. [...]... damage location as a result of hot- carrier stress [17] This method can probe the hot- carrier damage in regions under the spacer and that in the gate overlap The principle of this method is based on the change in resistance in the channel and that in the drain regions with hot- carrier stress degradation By extracting the drain current at two different gate voltages from the drain current versus gate voltage... S.J Wu, C.S Lai, Y.C Liu, D.F Chen, H.S.Lin, W.T Shiau, C.T Tsai, S.C Chien, S.W Sun, “A new insight into the degradation mechanisms of various mobility-enhanced CMOS devices with different substrate engineering,” in Proc Int Electron Devices Meeting Tech Digest, pp 4, 2005 [17] D S Ang, and C H Ling, “A unified model for the self-limiting hot- carrier degradation in LDD n-MOSFET’s,” IEEE Trans Electron... Morimoto, and H Iwai, “A new charge pumping method for determining the spatial distribution of hot- carrier induced fixed charge in p-MOSFET’s,” IEEE Trans Electron Devices, vol 40, pp 1768-1779, Aug 19 93 [12] W Chen, A Balasinski, and T P Ma, “Lateral profiling of oxide and interface traps near MOSFET junctions,” IEEE Trans Electron Devices, vol 40, pp 187196, Jan 19 93 [ 13] R G.-H Lee, J -S Su, and S S Chung,... charge-pumping current is measured with the base level of the gate pulse kept constant while the top level is varied The increase in top level of the gate pulse corresponds to the additional interface trap measurement area in the channel Thus, the incremental increase in charge-pumping current is interpreted as the interface traps present in that portion of the channel This technique was well received for hot- carrier. .. “Consistent model for the hot- carrier degradation in n-channel and p-channel MOSFET’s,” IEEE Trans Electron Devices, vol 35 , pp 2194-2209, Dec 1988 [2] E Takeda, and N Suzuki, “An empirical model for device degradation due to hot- carrier injection,” IEEE Electron Device Lett., vol 4, pp 111-1 13, Apr 19 83 [3] C Hu, S C Tam, F –C Hsu, P K Ko, T –Y Chan, and K W Terrill, “Hotelectron-induced MOSFET degradation... Maes, “Analysis of the charge pumping technique and its application for the evaluation of MOSFET degradation,” IEEE Trans Electron Devices, vol 36 , pp 131 8- 133 5, Jul 1989 [9] M G Ancona, N S Saks, and D McCarthy, “Lateral distribution of hot- carrierinduced interface traps in MOSFET’s,” IEEE Trans Electron Devices, vol 35 , pp 2221-2228, Dec 1988 [10] M Brox, A Schwerin, Q Wang, and W Weber, “A model... degradation in these regions could be quantified as depicted in Fig 2.9 Chapter 2 Experimental Setup 71 Fig 2.9 Linear drain current degradation as a function of stress time, monitored at high and low gate bias Vg for different stress drain voltages [17] Fig 2.9 shows the fractional shift in the drain current measured in the linear region as a function of hot- carrier stress duration The drain current... versus Vh curve and its derivative Take for instance, Lee et al provided a more straightforward setup by keeping source and drain biased at zero volts [ 13] [14] In doing so, the variation of Vfb and Vt near the source and drain regions during inversion and accumulation half cycles could be prevented, making the analysis of the measured interface trap density more meaningful Despite of the popularity of the... challenge as the CMOS technology continues to scale, especially the thinning down of gate dielectric In principle, charge-pumping technique does not take into account of the gate Chapter 2 Experimental Setup 69 leakage current when calculating interface trap density This leakage current, however, cannot be ignored when the gate dielectric is below 3 nm as depicted in Fig 2.7 [15] As the oxide thickness... approach includes lateral profiling or the time-evolution of interface state generation during hot- carrier stress [12][14] Nonetheless, additional and complex simulation work is needed if these approaches are used in device characterization As a result, simple and direct methods are desirable to provide reliable analysis Indeed, the novel work by Ang et al can help to resolve the complexity involved in simulation . surface potential in the vicinity of the source and drain junctions. It was explained that the fast interface traps located at a certain position in the channel or in the source or drain region will. corresponds to the additional interface trap measurement area in the channel. Thus, the incremental increase in charge-pumping current is interpreted as the interface traps present in that portion of. probe the hot-carrier damage in regions under the spacer and that in the gate overlap. The principle of this method is based on the change in resistance in the channel and that in the drain regions