Hot carrier mechanisms in advanced NMOS transistors 6

Chapter Five Channel Temperature in the Strained-Si/SiGe MOSFET In spite of the benefits gained from the downscaling of device dimensions, there is a growing concern in the upward trend of power consumption. This increment effectively results in more intense heating of the devices [1]. In more advanced technologies such as the silicon-on-insulator (SOI) and the strained-Si/SiGe, the channel is thermally insulated from the underlying substrate, yielding substantially higher channel temperature than that in the bulk Si. This is known as the self-heating effect and it could seriously impact the device electrical characteristics and reliability such as hot-carrier degradation [2][3]. The severity of hot-carrier degradation varies with channel temperature. This is attributed to the temperature dependent mobility and energy of electrons in the channel. Typically, the ambient temperature is equal to the channel temperature in bulk Si transistors as there is no trapped heat in the Si substrate. On the other hand, the channel temperature is higher in strained-Si/SiGe transistor relative to bulk Si at a given ambient temperature. Due to the nature of the SiGe alloy, the thermal conductivity of the strained-Si/SiGe substrate is much lower than that of the crystalline Chapter Channel Temperature Measurement 133 Si. Jenkins et al. reported that the channel temperature under nominal operating condition is much higher in the strained-Si/SiGe transistors than that in the bulk Si [4]. However, there is no report on the corresponding temperature when the device is subjected to hot-carrier stress. It is therefore essential to quantify the channel temperature under both nominal and stress conditions, before embarking on the hotcarrier study. In this chapter, we extracted the channel temperature from the measured current-voltage characteristics at different temperatures, utilizing a semi- phenomenological model [5]. This method is termed as the thermal resistance Rth extraction technique and it required simple and inexpensive equipment setup, with no additional structures or layout. This method is derived and discussed in the next section. Section 5.4 shows the extraction of channel temperature in both bulk Si and strained-Si/SiGe NMOSFET using this method over a wide range of gate width and power. The result is, in general, consistent with the previously reported values. Furthermore, the accuracy of this technique is compared to that made via pulse I–V in section 5.5. Despite the channel temperature measured by pulse I–V is ~0.6 time lower than that in the Rth technique, the temperature of the strained-Si/SiGe is still significantly higher than that of the bulk Si under the hot-carrier stress condition. We start this chapter with a brief review of some channel temperature measurement techniques. 5.1 Brief Review of Channel Temperature Measurement Techniques Generally, channel temperature measurement techniques are needed to quantify the amount of heat trapped in the transistor. This trapped heat can alter the electrical Chapter Channel Temperature Measurement 134 parameters which are temperature dependent hence affecting the transistor performance. To determine the severity of self-heating effect, the thermal resistance must be determined beforehand and it could relate to both the channel temperature Tc and the power dissipated Pd by the device through the simple equation Tc = Ta + Rth • Pd (5.1) where Ta is the ambient temperature, or the temperature independent of the device selfheating, Rth is the thermal resistance between the channel and the point where Ta is measured. It is worthy to note that Rth itself is to some degree a function of temperature, for the thermal conductivity of all materials is temperature dependent. Albeit Rth could be estimated from numerical simulations, the complexity involved in the simulation of large three-dimensional structures made it a challenging task. The experimental techniques, however, are the more widely used approach, and generally fall into three categories. 1) Approaches that involved specific layout or additional structure. For instance, the use of temperature-sensitive device, typically a diode, could be used to obtain Tc and hence Rth after performing some calibration [6]. The fact that additional structures are required limits the application of this technique in the manufacturing environment. Besides, these devices are often placed at a distance away from the area of interest, yielding a temperature that is different if not lower than the actual value. Chapter Channel Temperature Measurement 135 2) Approaches based on pulsed measurement. The notion of these techniques is simple and general: if voltages are applied to the device in short enough pulses, the thermal capacitance could be short-circuited, and then the isothermal electrical characteristics can be measured as a function of Ta. Subsequently, a comparison could be made with the DC characteristics to obtain the Tc [4][7]. 3) Direct measurement methods. These approaches, such as the infrared thermal scanning or micro raman spectroscopy are the most popular. The poor spatial resolution, however, limits the application in deep submicrometer devices [8]. The use of atomic force microscopy could improve the spatial resolution, nonetheless, at the cost of sophisticated and expensive equipment [9]. 5.2 The Rth Measurement Technique Consider a bias point in the saturation regime, defined by an ambient temperature Ta0, a gate voltage Vg0, a drain voltage Vd0, a drain current Id0 and a corresponding channel temperature Tc0. If the ambient temperature Ta is increased over Ta0, and assuming a linear dependence of the drain current on Ta, we can write I d (Vd , Ta ) = I d ⋅ (1 + h ⋅ (Ta − Ta )) (5.2) and ∂I d (Vd , Ta ) = Id0 ⋅ h ∂Ta (5.3) Chapter Channel Temperature Measurement 136 The parameter h can be obtained by plotting Id(Vd0,Ta) as a function of Ta, and taking the slope of the linear regression line. Now, assuming in the same Ta range, the drain current is a linear function of the channel temperature Tc and can be expressed as I d (Vd , Tc ) = I d ⋅ (1 + h'⋅(Tc − Tc )) (5.4) Tc − Tc = Ta − Ta + Rth ⋅ Vd ⋅ ( I d (V d , Ta ) − I d ) (5.5) However which can be substituted into (5.4), thus obtaining I d (Vd , Ta ) = I d ⋅ (1 + h'⋅(Ta − Ta + Rth ⋅ Vd ⋅ ( I d (V d , Ta ) − I d )) (5.6) Taking the derivative of (5.6) with respect to Ta and rearranging, we get ∂I d (V d , Ta ) I d ⋅ h' = ∂Ta − I d 0⋅h'⋅Rth ⋅ Vd (5.7) Since the left-hand side of (5.7) must be equal to that of (5.3), we may write 1 = − Rth ⋅ I d ⋅ V d h h' (5.8) This procedure is repeated for different values of Vd > Vd0, and consequently a more general equation: 1 = − Rth ⋅ I d (Vd , Ta ) ⋅ V d h h' = − Rth ⋅ Pd (V d , Ta ) h' (5.9) where Pd is the dissipated power. Therefore, a plot of 1/h with respect to Pd(Vd,Ta0) should result in a straight line, from the slope of which Rth could be obtained. Chapter Channel Temperature Measurement 137 Some assumptions and simplifications related to the derivation of (5.9) must be highlighted before this technique is applied to an MOSFET. 1) The drain current is linearly dependent on the ambient temperature as shown in (5.2). In principle, it is possible to limit the temperature range so that Id is a linear function of Ta with a desired accuracy. In this experiment, the temperature range from 273 K to 298 K is used. If the temperature range is reduced, then higher accuracy and resolution are needed from the temperature control and the measurement equipment. It is noteworthy that in this model, due to the constant Rth [see point (2) below] assumed, the linearity of Id over a range of Ta as written in (5.2) implied that of Id on Tc illustrated in (5.4), and vice versa. 2) Upon taking the derivative of (5.6) to obtain (5.7), it is implicitly assumed that Rth is independent of Ta. The accuracy of this approximation is, nonetheless, inversely proportionate to the size of the Ta range. In the 273293 K range used for the extraction, it is plausible to estimate that the total channel-to-extension thermal resistance of the devices under test should vary by only a few percent in the chosen temperature range. 3) It is also implicitly assumed that the Rth expressed in (5.9) is independent of the dissipated power. This is only valid to certain extent, since increasing Vd, therefore dissipated power, the channel temperature rises, resulting in the increase in Rth as well. The neglected Rth variation with dissipated power is estimated not to exceed a few percent based on the considerations mentioned in point (2) above. Chapter Channel Temperature Measurement 138 5.3 Experimental Devices with gate length L of 0.18 µm and gate width W ranging from 0.5 to 20 µm were evaluated. In order to extract the Rth, measurement was carried out at temperature ranging from 273 to 298 K. The channel temperature due to self-heating effect Tch is measured under the nominal operating condition (Vg = Vd = 1.8 V) and that under hot-carrier stress condition (Vg = Vd = 2.7 V). So as to verify the accuracy of the Rth technique, pulse I–V characteristics are measured via Keithley 4200-SCS Semiconductor Characterization System (SCS) and the setup is shown in Fig. 5.1. This setup involves the 4200-PG2 pulse generator, 4200-SCP2 scope, 4200-RBT remote Bias Tees. The SCS can automatically characterize I-V and C-V characteristics of semiconductor devices and test structures, using up to eight Source-Measure Units (SMUs). The 4200-RBT is a coupler for DC bias voltage from an SMU and pulse output of a 4200-PG2 channel. The output of the 4200-RBT provides pulse output riding on the DCV bias. The 3-Port Power Divider is used in the AC (pulse) signal path to the gate of the FET. It divides the electrical power equally among its three connectors using a 16.67Ω resistor in each “leg” to provide 50Ω impedance matching. The Keithley 4200-PG2 is a two-channel, high speed, voltage pulse generator. The pulse generator can be programmed for continuous pulse output or set to output a finite number of pulses (burst mode). Nominally, pulse amplitude can be set from 100mV up to 40V. Pulse period can be set from 20ns to 1s with a minimum pulse width of 10ns. Pulse rise and fall times can be independently set from 10ns to 1s. Chapter Channel Temperature Measurement 139 The 4200-SCP2 is an 8-bit, 1.25 billion samples-per-second (GS/s) Digital Storage Oscilloscope (DSO). It uses a high speed memory digitizer (DC to 700MHz) and embedded Digital Signal Processor (DSP). The 4200-SCP2 has two input channels to capture and analyze a variety of time-varying signals. Fig. 5.1 Schematics of the pulse I-V measurement setup [10]. During the pulse I-V measurement, the SCS uses SMU2 to perform a DC linear voltage sweep on the drain of transistor while the gate is being activated by a pulsed bias as shown in Fig. 5.2. The drain current measurements in this case are made using the scope (channel 2). For proper PIV operation when using the RBTs, the duty cycle should not be greater than 0.1%. SMU1 is used to apply a fixed 0V bias on the gate of the FET. During the drain sweep, drain current measurements are performed at each of the 41 sweep points. These measurements are a number of consecutive measurements that are then averaged to yield a single reading. The 41 averaged readings are placed in the data sheet and graphed. Drain current and drain voltage are measured at each of the 41 measure points. The 41 current and voltage measurements for each sweep are then used to plot the Id-Vd graph. Chapter Channel Temperature Measurement 140 For this pulse I-V experiment, the transistor is biased at Vs = Vb = V while Vd =1.8 V and Vg is pulsed with an amplitude of 1.8 V and having a range of pulse widths Wp from 40 to 250 ns at a frequency of 10 KHz. Fig. 5.2 Example of how the pulse amplitude sweeps at the gate terminal of the transistor [10]. 5.4 Extraction of the Rth in bulk Si and Strained-Si/SiGe NMOSFET Based on the experimental data, the linear dependence of the drain current with the ambient temperature Ta in (5.2) is consistent and it is exhibited in Fig. 5.3. The slope of the Id − Ta characteristics for each Vd is used to obtain the h parameter subsequently. The typical Id-Vd plot with the ambient temperature Ta as the parameter for all substrates is shown in Fig. 5.4. The characteristic typical of that of the control and strained-Si/SiGe with different Ge concentrations are depicted in Fig. 5.3 (a), (b) and (c) respectively. The temperature dependence of the drain current in strained-Si/SiGe transistors are similar to that of the control. This indicates that the reduction in drain current is phonon-limited [11]. The higher drive current in strained-Si/SiGe transistor Chapter Channel Temperature Measurement 12.5 141 (a) Drain Current, Id (mA) 1.8V 12.0 11.5 Control Vg = 1.8V 11.0 270 280 290 300 Ambient Temperature, Ta (K) 15.5 (c) (b) Drain Current, Id (mA) 14.5 Vd = 1V Vd = 1V Vd = 1V 15.0 14.0 13.5 270 1.8V 1.8V 285 300 270 285 Ambient Temperature, Ta (K) 14.5 300 Fig. 5.3 Drain current Id as a function of ambient temperature Ta with drain voltage Vd as the parameter for (a) control (b) 15 % Ge (c) 20 % Ge devices having L = 0.18 µm and W = 20 µm. relative to the control is the result of lower strain-induced effective mass of electrons. Higher Ge concentration results in larger strain hence the enhancement. On the other hand, self-heating effect is apparent when drive current reduces at high drain voltage Chapter Channel Temperature Measurement -700 1/h (°C) -800 144 Control 15% Ge 20% Ge -900 -1000 -1100 -1200 10 15 20 25 30 Dissipated Power, Pd (Vd,Ta0) (mW) Fig. 5.5 Extraction of Rth for the transistors having W = 20 µm width transistors. The lines denote the linear best fits, the slope of which yields Rth. Fig. 5.6 depicts the dependence of 1/h on Pd for all four device width. The linear relationship of (5.9) holds well for strained-Si devices. The slight non-linearity in control devices is attributed to the variation of Rth in the channel-to-flange of the devices as mentioned in page 136. It is worthy to note that h’, which can be extracted as the reciprocal of the intercept of each interpolating line, is almost the same for the different transistors. In this case, the value of 1/h’ for both strained-Si and bulk Si is approximately -710. This is an indication of the consistency in the technique, since h’ in (5.4) is the coefficient relating the current with the channel temperature Tc. It is expected that h’ could vary with device technology, but not with the size in the same technology. Fig. 5.7 is another sign of well-behaved and reliable results: the extracted thermal conductance Rth-1 scales with the gate width W as Chapter Channel Temperature Measurement 145 (5.10) 1 = + k ⋅W Rth Rt h -700 1/h (K) -800 Control W= 0.5µm 4µm 10µm 20µm -900 15% Ge -1000 -1100 20% Ge -1200 -5 10 15 20 25 30 Dissipated Power, Pd (Vds, Ta0) Fig. 5.6 Extraction of Rth for devices with different gate width W for filled symbols defined for control; unfilled symbols for 15% Ge and lines for 20% Ge devices. 0.4 Control 15% Ge 20% Ge 1/Rth (mW/K) 0.3 0.2 0.1 0.0 10 15 20 Gate Width, W (µm) Fig. 5.7 Thermal conductance 1/Rth as a function of the gate width W. Chapter Channel Temperature Measurement 146 It follows from (5.10) that at a constant dissipated power density pd = Pd/W = (Vd⋅Id)/W, larger devices will operate at a higher temperature, because (5.11) Rth ⋅ W ⋅ pd + k ⋅ W ⋅ Rth which is a monotonically increasing function of the gate width W. It should, however, Tc = Ta + Rth ⋅ p d ⋅ W = Ta + be noted that the channel temperature due to self-heating Tch =Tc-Ta remains fairly constant for W beyond 0.5 µm as depicted in Fig. 5.8. This weak device width dependence is similarly observed by Sinha et al. [12]. Control 15% Ge 1050 Open: Vg = Vd = 2.7 V 20% Ge Half-filled: Vg = Vd = 2.7 V @ T=100 °C Increase in Channel Temperature, Tch (°C) Filled: Vg = Vd = 1.8 V 700 350 10 15 20 Channel Width, W (µm) Fig. 5.8 Increase in channel temperature Tch as a function of channel width W for strainedSi and bulk-Si N-MOSFETs biased at Vg = Vd = 1.8 V and Vg = Vd = 2.7 V (stress condition). Filled and unfilled symbols denote Tch obtained at chuck temperature T = 30 oC; half-filled symbols denote Tch extracted for T =100 oC based on T = 30 oC. The weak W dependence of Tch is related to the competing mechanism of increasing dissipated power with W and the effect of thermal healing length l. The distance from a heating source over which the channel temperature decays to the Chapter Channel Temperature Measurement 147 substrate temperature [13] is known as thermal healing length and it can be modeled for strained-Si/SiGe devices in the similar way as k ⋅t ⋅t  l = =  Si Si SiGe  m  k SiGe  (5.12) where kSi, kSiGe are the thermal conductivity and tSi, tSiGe the thickness of silicon and SiGe respectively. In bulk Si transistor, rise in channel temperature is assumed to be negligible small and it decayed to the substrate temperature almost immediately. In this case, (5.12) tends to zero and majority of the heat dissipates through the substrate. On the contrary, the heat dissipation occurs more readily in the laterally direction in strained-Si/SiGe devices and the effect of channel-to-contact spacing to the thermal healing length becomes dominant. For this set of devices, tSi and tSiGe are 15 x 10-7 cm and x 10-4 cm respectively. Using 1.41 and 0.1 W/cm for the thermal conductivities of Si and SiGe respectively [7], thermal healing length I value of 0.65 µm was obtained. This means that if the channel-to-contact spacing is comparable or smaller than 0.65 µm, then the contacts become the heat sink. When the trapped heat in the channel is more intense and spatially distributed, more heat will sink through the contacts. Indeed, this explanation is confirmed in the TEM of the strained-Si/SiGe device in Fig. 5.9 indicating the channel-to-contact spacing ~0.2 µm. Additional heat conduction path through the field oxide to overlapping aluminum contacts could also help to reduce the temperature [14]. Despite the weak W dependence, it is noteworthy that the Tch in strainedSi/SiGe devices is significantly higher as compared to the bulk Si as illustrated in Fig. 5.8. There is a slight dependence of the Tch on the Ge concentration. Under nominal Chapter Channel Temperature Measurement 148 operating condition Vg = Vd = 1.8 V, the bulk Si and the strained-Si/SiGe devices exhibited Tch ~60 °C and ~390 °C respectively. For devices which were under hot-carrier stress condition, channel temperatures in all substrates have increased. Nevertheless, the corresponding rise in channel temperature of stained-Si/SiGe devices is more critical. Take the devices with W = 20 µm for instance, the Tch in bulk Si is ~160 °C which is only slightly higher than the typical maximum operating temperature of most bulk Si devices. In the case of strained-Si/SiGe, the Tch could reach as high as 760 °C. To ensure the result from this technique is realistic, another set of devices is used to measure the channel temperature via pulse I-V measurement technique and this is discussed in the next section. Fig. 5.9 TEM image of device used in the channel temperature measurement. Chapter Channel Temperature Measurement 149 5.5 Verification with Pulsed I–V Technique In order to find out if the data extracted using the Rth measurement technique is reasonable, an independent measurement such as the pulse I–V measurement technique is used. Fig. 5.10 shows a typical comparison plot between pulse I-V and that under DC bias condition for a control device. The difference between Id measured under pulse and that under DC bias is attributed to self-heating. It is apparent that some selfheating is present only at high gate and high drain bias condition for control device. On the contrary, significant self-heating is present in strained-Si/SiGe transistor as shown in Fig. 5.11. At low gate voltage, there is already some self-heating present and this Drain Current, Id (mA) effect increases as the drain and gate biases increase. DC Pulsed IV 12 0.0 0.5 1.0 1.5 2.0 Drain Voltage, Vd (V) Fig. 5.10 Typical I-V curve measured under pulse and that under DC bias condition for control device with W = 20 µm and L = 0.18 µm at ambient temperature Ta of 25 °C. For pulse measurement technique, careful selection of pulse width is desired so as to prevent any heat build up during the “ON” state which would result in lower Id Chapter Channel Temperature Measurement 150 [7]. This impact could cause the actual channel temperature to be underestimated. Hence, Id is measured for a range of pulse widths Wp in this experiment to obtain the preferred Wp. Fig. 5.12 shows the ratio R (ratio of drain current measured via pulse I–V method Id(pulse) to that of drain current via the normal DC bias Id(DC)) as a function of Wp. Drain Current, Id (mA) 16 DC Pulsed IV 12 0.0 0.5 1.0 1.5 2.0 Drain Voltage, Vd (V) Fig. 5.11 Typical I-V curve measured under pulse and that under DC bias condition for strained-Si device with W = 20 µm and L = 0.18 µm at ambient temperature Ta of 25 °C. In general, the ratio R in the control device is near to unity. For Wp ranging from 200 to 250 ns, R < can be attributed to the effect of load capacitance on the gate voltage waveform [15] as shown in Fig. 5.13. Thus, Wp in this range would not be used for this experiment. For the range of Wp from 60 to 120 ns, the R is slightly larger than unity indicating finite self-heating effect even in bulk Si device. Ratio of Pulsed-to-DC Drain Current, R(Id(Pulsed)/Id(DC)) Chapter Channel Temperature Measurement 151 1.2 1.1 1.0 Cn 15% Ge DC Value 0.9 50 100 150 200 250 Pulsed Width, Wp (ns) Fig. 5.12 Ratio R = Id(pulsed)/Id(DC) as a function of pulse width Wp measured on W = 20 µm and L = 0.18 µm at ambient temperature Ta of 25 °C (Id extracted at Vg = Vd = 1.8 V). In the case for strained-Si, R increases non-linearly as Wp reduces. The ratio R in strained-Si is also much larger than unity for all Wp values indicating self-heating is causing the measured Id via DC biasing to be significantly smaller than that via pulse I–V. In addition, self-heating effect in strained-Si is also compounded into the measured Id in the range of Wp = 60 – 120 ns. This can be deduced from the steeper slope of the ratio in strained-Si relative to the control. Ideally, the desired Wp to measure channel temperature should be as small as possible to prevent self heating in the channel and it should be in the range of few nanoseconds [7]. Nonetheless, this range of Wp is beyond the current equipment capability. As such, the channel temperature is measured for a range of Wp from 60 to 120 ns. By plotting the response of the channel temperature to various Wp, an estimated channel temperature can be Chapter Channel Temperature Measurement 152 obtained. This estimated channel temperature has negligible self-heating effect because it is extrapolated to the Wp with negligible self-heating effect. In order to obtain the channel temperature of the stained-Si device, a series of pulse I-V measurement needs to be performed at different ambient temperature Ta. The channel temperature is known to be equal to Ta under pulse measurement. Subsequently, a comparison is made between this set of pulse I-V curves and the I-V curve measured under DC bias condition at ambient temperature Ta of 25 °C as shown in Fig. 5.14. When the DC I–V curve intersects one of the pulse I–V curves, it is known that the channel temperature must be the same with the ambient temperature at that particular Id condition. 2.1 (b) (a) PW = 250ns PW = 250 ns 1.9 PW = 60ns -0.1 1.8 PW = 60 ns 0.0 0.1 0.2 0.3 Time (µs) 0.0 0.1 0.2 Voltage (V) Voltage (V) 2.0 1.7 Time (µs) Fig. 5.13 (a) Gate voltage waveform for pulse width Wp of 60 ns and 250ns and the corresponding (b) voltage drop on the top portion of the waveform is due the effects on load capacitance on the waveform [15]. Drain Current, Id (mA) Chapter Channel Temperature Measurement 153 DC Pulsed IV 14 Ta=25-150 °C at steps of 25 °C 0.0 0.7 1.4 Drain Voltage, Vd (V) Fig. 5.14 Typical plot of I–V curve measured under DC bias and pulse condition for W = 20 µm and L = 0.18 µm strained-Si device. Pulse I-V curves are obtained at a range of ambient temperature Ta from 25 to 150 °C at steps of 25 °C. After obtaining the intersected Id and the corresponding Vd at each ambient temperature, a plot of channel temperature Tch as a function of dissipated power Pd can then be obtained as illustrated in Fig. 5.15. Subsequently, a regression line can be plotted to find the slope and the y-intersect. Lastly, the channel temperature is acquired by inserting the dissipated power under DC bias condition at Ta of 25 °C into the equation. Channel Temperature, Tch (°C) Chapter Channel Temperature Measurement 154 160 140 120 100 80 60 40 Tch= 15.19+18.49(Pdc) 20 10 12 Dissipated Power, Pd (mW) Fig. 5.15 Channel temperature Tch as a function of dissipated power Pd. The equation of the regression line is used to obtain the channel temperature of the strained-Si device at ambient temperature Ta of 25 °C. This sequence is repeated for each Wp ranging from 60 to 120 ns as depicted in Fig. 5.16. As expected, Tch increases as Wp reduces indicating that the channel temperature is underestimated at large Wp. It is also apparent that wider device, for example W = 20 µm, suffers a higher channel temperature for the same nominal operating condition of Vg =Vd = 1.8 V. The Tch for devices under Vg = Vd = 2.7 V condition is also increased significantly. A regression line is finally plotted to extrapolate the channel temperature to Wp of ns where self-heating is negligible. Table 5.1 shows the corresponding channel temperature obtained using the Rth and the pulse I-V techniques. In general, the channel temperature obtained using pulse I-V technique is ~0.43 – 0.53 times and ~0.58 times lower than that using Rth extraction method for nominal operating condition and hot-carrier stress condition respectively. It should, however, be highlighted that the pulse width used in our measurement is similar with if not shorter than the thermal time constant of 50-100 ns [16]. Hence, channel heating could already occur, rendering the channel temperature to be underestimated. In summary, the Rth extraction technique is fairly comparable to the pulse I-V method. Channel Temperature, Tch (°C) Chapter Channel Temperature Measurement 155 Vg=Vd=1.8V 300 Vg=Vd=2.7V 200 100 0 50 100 150 Pulsed Width, Wp (ns) Fig. 5.16 Channel temperature as a function of pulse width Wp. A regression line is used to obtain the channel temperature at Wp of ns where channel heating is insignificant. Filled square symbol denotes the channel temperature of transistor having transistor width of 20 µm; circle symbol denotes that of transistor width of µm. Device Width, Tch (°C) via Tch (°C) via W (µm) Technique A Technique B (Vg=Vd=1.8 V) 362.7 170 (Vg=Vd=2.7 V) 690 288 20 (Vg=Vd=1.8 V) 361.6 207 Table 5.1 Summary of extracted channel temperature in strained-Si/SiGe via different methods. Technique A (Rth extraction method) and Technique B (Pulse I-V method). Chapter Channel Temperature Measurement 156 5.6 Summary In this chapter, the channel temperature due to self-heating is measured for bulk Si and strained-Si/SiGe devices. Based on the semi-phenomenological model, we extracted the thermal resistance in both substrates. Although it is generally conceded that channel temperature is proportionate to the dissipated power, a weak device width dependence of the channel temperature is observed for this set of devices. This behavior could happen when the contact-to-gate spacing is within the thermal diffusion length where the contacts act as the heat sink. Despite of this weak dependence, the estimated rise in channel temperature due to self-heating for strained-Si/SiGe is ~760 °C during hot-carrier stress while it is only ~150 °C for the bulk Si. This result is verified through a separate set of measurement using pulse I-V technique. It was found that Rth extraction method is fairly comparable to the pulse I-V method. In reliability aspect such as the hot-carrier performance, the effect of channel temperature on the amount of degradation at the oxide interface remains vital and this is discussed in the next chapter. Chapter Channel Temperature Measurement 157 5.7 References [1] E. Pop, K. Banerjee, P. Sverdrup, R. Dutton, and K. Goodson, “Localized heating effects and scaling of sub-0.18 micron CMOS devices,” in Proc. Int. Electron Devices Meeting Tech. Digest, pp. 677-680, 2001. [2] L. J. McDaid, S. Hall, P. Mellor, W. Eccleston, and J. Alderman, “Physical origin of the negative differential resistance in SOI transistors,” IEEE Electron Device Lett., vol. 25, pp. 827-829, 1989. [3] P. Su, K. Goto, T. Sugii, and C. Hu, “Excess hot-carrier currents in SOI MOSFETs and its implications,” in Proc. Int. Rel. Phys. Sym., pp. 93-97, 2002. [4] K. A. Jenkins, and K. Rim, “Measurement of the effect of self-heating in strained-silicon MOSFETs,” IEEE Electron Device Lett., vol. 23, pp. 360-362, Jun. 2002. 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Hu, “Ultrafast measurement on NBTI,” IEEE Electron Device Lett., vol. 30, pp. 275-277, Mar. 2009. Chapter Channel Temperature Measurement [16] 159 K. A. Jenkins, and R. L. Franch, “Impact of self-heating on digital SOI and strained-silicon CMOS circuits,” in Proc. SOI Conf., pp. 161-163, 2003. [...]... reduces The ratio R in strained-Si is also much larger than unity for all Wp values indicating self-heating is causing the measured Id via DC biasing to be significantly smaller than that via pulse I–V In addition, self-heating effect in strained-Si is also compounded into the measured Id in the range of Wp = 60 – 120 ns This can be deduced from the steeper slope of the ratio in strained-Si relative to... of impact ionization in strained-Si,” IEEE Tran Electron Devices, vol 52, pp 162 7- 163 3, Jul 2005 [12] S P Sinha, M Pellela, C Tretz, and C Riccobene, “Assessing circuit level impact of self-heating in 0.13 µm SOI CMOS,” in Proc IEEE Int SOI Conf., pp 101-102, 2001 [13] L T Su, J E Chung, D A Antoniadis, K E Goodson, and M I Flik, “Measurement and modeling of self-heating in SOI NMOSFET’s,” IEEE Tran... temperatures in all substrates have increased Nevertheless, the corresponding rise in channel temperature of stained-Si/SiGe devices is more critical Take the devices with W = 20 µm for instance, the Tch in bulk Si is ~ 160 °C which is only slightly higher than the typical maximum operating temperature of most bulk Si devices In the case of strained-Si/SiGe, the Tch could reach as high as 760 °C To ensure... attributed to self-heating It is apparent that some selfheating is present only at high gate and high drain bias condition for control device On the contrary, significant self-heating is present in strained-Si/SiGe transistor as shown in Fig 5.11 At low gate voltage, there is already some self-heating present and this Drain Current, Id (mA) effect increases as the drain and gate biases increase DC Pulsed... Fig 5 .6 depicts the dependence of 1/h on Pd for all four device width The linear relationship of (5.9) holds well for strained-Si devices The slight non-linearity in control devices is attributed to the variation of Rth in the channel-to-flange of the devices as mentioned in page 1 36 It is worthy to note that h’, which can be extracted as the reciprocal of the intercept of each interpolating line, is... devices,” in Proc Int Electron Devices Meeting Tech Digest, pp 67 7 -68 0, 2001 [2] L J McDaid, S Hall, P Mellor, W Eccleston, and J Alderman, “Physical origin of the negative differential resistance in SOI transistors, ” IEEE Electron Device Lett., vol 25, pp 827-829, 1989 [3] P Su, K Goto, T Sugii, and C Hu, “Excess hot- carrier currents in SOI MOSFETs and its implications,” in Proc Int Rel Phys Sym.,... become the heat sink When the trapped heat in the channel is more intense and spatially distributed, more heat will sink through the contacts Indeed, this explanation is confirmed in the TEM of the strained-Si/SiGe device in Fig 5.9 indicating the channel-to-contact spacing ~0.2 m Additional heat conduction path through the field oxide to overlapping aluminum contacts could also help to reduce the... happen when the contact-to-gate spacing is within the thermal diffusion length where the contacts act as the heat sink Despite of this weak dependence, the estimated rise in channel temperature due to self-heating for strained-Si/SiGe is ~ 760 °C during hot- carrier stress while it is only ~150 °C for the bulk Si This result is verified through a separate set of measurement using pulse I-V technique It was... 25 °C In general, the ratio R in the control device is near to unity For Wp ranging from 200 to 250 ns, R < 1 can be attributed to the effect of load capacitance on the gate voltage waveform [15] as shown in Fig 5.13 Thus, Wp in this range would not be used for this experiment For the range of Wp from 60 to 120 ns, the R is slightly larger than unity indicating finite self-heating effect even in bulk... nominal operating condition of Vg =Vd = 1.8 V The Tch for devices under Vg = Vd = 2.7 V condition is also increased significantly A regression line is finally plotted to extrapolate the channel temperature to Wp of 7 ns where self-heating is negligible Table 5.1 shows the corresponding channel temperature obtained using the Rth and the pulse I-V techniques In general, the channel temperature obtained . V). In the case for strained-Si, R increases non-linearly as W p reduces. The ratio R in strained-Si is also much larger than unity for all W p values indicating self-heating is causing the. drain current in strained-Si/SiGe transistors are similar to that of the control. This indicates that the reduction in drain current is phonon-limited [11]. The higher drive current in strained-Si/SiGe. 1 36 The parameter h can be obtained by plotting I d (V d0 ,T a ) as a function of T a , and taking the slope of the linear regression line. Now, assuming in the same T a range, the drain