Hot carrier mechanisms in advanced NMOS transistors 1

i ACKNOWLEDGMENTS My foremost gratitude must go to my project main supervisor, Professor Ling Chung Ho. Without his guidance and coaching throughout the course of this project, I would not have come to this stage. His continuous support and encouragement have been one of the prime motivating factors for me in years. I am also deeply indebted to my project co-supervisor, Dr. Ang Diing Shenp. He is always willing to share his knowledge and experience with me. Working alongside with him, I have learnt a lot of practical skills, such as creative thinking and problem solving, which cannot be learnt from any textbook. My sincere thanks go to my colleague in the MOS Device Lab, Madam Ah Lian Kiat, and many more. My thanks extend to everyone who has contributed to my project in one way or another. Last but not least, I must acknowledge the most important persons in my life, my wife Wei Mein and my three lovely children, Sherlyn, Shaun and Sherman. Their understanding, support and existence carry me through all the difficult times. ii TABLE OF CONTENTS ACKNOWLEDGMENTS i TABLE OF CONTENTS ii LIST OF SYMBOLS v LIST OF FIGURES vii LIST OF TABLES xvii Chapter 1.1 INTRODUCTION Impact of CMOS Technology Scaling on the Hot-Carrier Effects 1.1.1 Bulk Si CMOS Technology Trend 1.1.2 The Change in CMOS Scaling Approach 1.1.3 Hot-Carrier Degradation in Bulk Si NMOSFET 1.1.4 Worst Case Degradation 1.1.5 Hot-Carrier Degradation at Low Drain Voltage 14 Extension of CMOS Technology Roadmap - Strained-Si Technology 18 1.2.1 The Role of SiGe Buffer Layer 19 1.2.2 Current Enhancement in Strained-Si NMOSFET 21 1.2.3 The Self-Heating Effect 27 1.2.4 Process Induced Strain Relaxation 29 1.3 Hot-Carrier Degradation in Strained-Si/SiGe NMOSFET 30 1.4 Summary and Motivation 37 1.5 Organization of the Thesis and the Original Contributions 40 1.6 References 42 1.2 iii Chapter EXPERIMENT SETUP 58 2.1 Automated Measurement Setup 59 2.2 Charge-pumping Current as a Measure of Interface State Generation 61 2.3 Method to Probe Hot-Carrier Induced Damage in a Transistor 70 2.4 Summary 72 2.5 References 74 Chapter MECHANISMS FOR N-MOSFET HOT-CARRIER DEGRADATION AT OPERATING VOLTAGE BELOW OXIDE POTENTIAL BARRIER 77 3.1 Experimental 80 3.2 Mechanism for the Worst-Case Hot-Carrier Stress Degradation 81 3.3 Composite Interface State Generation under CHE Stressed Condition 87 3.4 Summary 94 3.5 References 96 Chapter THE CHANNEL DOPING IN STRAINED-SI/SIGE NMOSFET: EFFECT ON NARROW WIDTH DEVICE CHARACTERISTICS AND THE INJECTION EFFICIENCY OF HIGH-ENERGY TAIL ELECTRONS 101 4.1 Experimental 105 4.2 Width Dependence of Threshold Voltage in NMOSFET 105 4.2.1 Effective Width of Narrow Width NMOSFET 110 Injection Efficiency of High-Energy Tail Electrons 112 4.3.1 Impact Ionization Feedback 114 4.4 Substrate Hot-Electron (SHE) 117 4.5 Summary 124 4.6 References 126 4.3 iv Chapter CHANNEL TEMPERATURE IN THE STRAINED-SI/SIGE MOSFET 132 5.1 Brief Review of Channel Temperature Measurement Techniques 133 5.2 The Rth Measurement Technique 135 5.3 Experimental 138 5.4 Extraction of the Rth in bulk Si and Strained-Si/SiGe NMOSFET 140 5.5 Verification with Pulsed I–V Technique 149 5.6 Summary 156 5.7 References 157 Chapter SELF-HEATING INDUCED SPATIAL SPREAD OF INTERFACE STATE GENERATION BY HOT-ELECTRON EFFECT: ROLE OF THE HIGH-ENERGY TAIL ELECTRONS 160 6.1 Experimental 161 6.2 Non-Local Interface State Generation via Channel-Hot-Electron Stress 162 6.3 AC Gate Stress Induced Degradation 172 6.4 Summary 175 6.5 References 177 Chapter EVIDENCE OF GERMANIUM OUTDIFFUSION AS A RESULT OF HIGH CHANNEL TEMPERATURE 182 7.1 Device Fabrication and Experimental Setup 184 7.2 Energy Dispersive X-Ray Spectrometry (EDS) 184 7.3 Results and Discussion 186 7.4 Summary 193 7.5 References 194 Chapter CONCLUSION LIST OF PUBLICATIONS 197 201 v LIST OF SYMBOLS aGe Lattice constant of Germanium aSi Lattice constant of Silicon CGe Average Germanium concentration Dstr Stress duty cycle Em Channel electric field Gm, gm Transconductance Icp Charge pumping current Id Drain current Id,sat Drain current when transistor is under saturation mode Ion Drain current per unit gate width when transistor is ON state Ioff Drain current per unit gate width when transistor is OFF state Ig Gate current Ige Hot electron gate current Igmax Maximum gate current Isubmax Maximum substrate current Ib, Isub Substrate current m0 Mass of electron in free space ml Mass of electron in longitudinal direction mt Mass of electron in transverse direction m* Conductivity effective mass of electron L, Lg Gate/channel length Nsub Si substrate doping concentration Not Oxide trap density Nit Interface trap density Pd Dissipated power by a device vi pd Dissipated power density of a device q Electron charge Rth Thermal resistance Rsd Source-Drain resistance T Chuck temperature Ta Ambient temperature Tc Channel temperature Tch Channel temperature due to self-heating tf Gate pulse fall time tr Gate pulse rise time TSi Strained silicon film thickness Tstr Stress duration Vdd Power supply voltage Vd, VDS Drain voltage Vg, VGS Gate voltage Vgt Gate top voltage Vgb Gate base voltage Vsub, Vb, VBS Substrate voltage Vth Threshold voltage W Gate width Xox Oxide thickness Xj Junction depth τ* Momentum scattering time τ Hot-carrier lifetime vii LIST OF FIGURES Fig 1.1 Evolution of silicon logic device platform. Fig 1.2 Logic technology node and physical gate length as a function of year of introduction. Fig 1.3 Trend of drain current per unit gate width under the supply voltage specified. All the drive current value published in conference. Fig 1.4 The scaling trend of the power supply voltage Vdd and the gate length Lg for the past decades. Fig 1.5 Conceptual view of the hot-electron problem. Fig 1.6 Schematic diagram for the hot-carrier effect in the NMOSFET. Also shown is the position of the peak lateral electric field within the channel. Fig 1.7 Fractional change in transconductance as a function of stress gate voltage for an NMOSFET. A close correspondence between the interface state generation and the substrate current is observed. 10 Fig 1.8 Hot-carrier lifetime plot evaluated with the charge pump current. HH – stress at 295K, lifetime evaluation at 295K; LL – stress at 77K, lifetime evaluation at 77K; LH – stress at 77K, lifetime evaluation at 295K after warm-up. 12 Fig 1.9 Increase in charge-pumping current as a function of gate stress voltage (b) the corresponding substrate current as a function of gate stress voltage. The filled symbols denote the stress conditions that are higher than the critical field; the unfilled symbols represent the stress conditions that fall below the critical field. 12 Fig. 1.10 Time dependence of the interface trap increment for NMOSFET annealed at 450 °C for hrs in 100 % H2 and 100 % D2. The devices were stressed such that the hot electrons were directed only towards the interface from the substrate. These hot electrons are confined to the immediate region of the interface because of the low gate voltage 13 Fig 1.11 Electron energy distributions near the drain in a 0.07µm gate length NMOSFET with drain voltage of 1.5 V. The dashed line denotes the data obtained without considering EE scattering; full line denotes data obtained when EE scattering is considered. 15 viii Fig 1.12 Diagram illustrates the impact ionization feedback mechanism in the NMOSFET. 16 Fig 1.13 Effect of VBS on distribution function integrated along the Si/SiO2 interface. 16 Fig 1.14 (a) Introduction of larger Ge atoms into the silicon in order to form alloy (b) larger lattice spacing in SiGe alloy in the lateral direction (c) introduction of Si on top of the alloy (d) formation of a thin layer of strained-Si on the SiGe alloy. 20 Fig 1.15 (a) schematic illustrating the extension of the threading dislocation towards the relaxed SiGe alloy and (b) the corresponding TEM image before the strained-Si growth. 21 Fig 1.16 Comparison of the conduction band structure of the bulk Si with that of the tensile strained-Si. The six-fold degenerate valley in bulk Si is split into four- and two-fold valleys when the Si exhibits tensile strain. 22 Fig 1.17 (a) Effective electron mobility enhancement in strained-Si (b) 24 improvement of Ion-Ioff characteristics in the strained-Si. Fig 1.18 NMOS mobility enhancement in the strained-Si NMOSFET as a function of Ge content in the virtual substrate. 25 Fig 1.19 Energy band diagram for NMOSFET under inversion condition. 27 Fig 1.20 Threshold voltage as a function of gate length. 27 Fig 1.21 Drain current as a function of drain voltage with gate voltage as the parameter for (a) bulk Si (b) strained-Si NMOSFET. The apparent reduction of drain current at high drain voltage for strained-Si is attributed to the self-heating effect. 28 Fig 1.22 (a) Ge depth profile with annealing temperature as the parameter (b) Raman spectra of the samples heated at various anneal temperatures (c) high resolution spectra of the peaks from the strained-Si. 30 Fig 1.23 Fractional decrease in the bandgap as a function of the Ge concentration. The increase in Ge concentration results in an increase in strain level [110]. The line denotes the calculation based on the model in [111]. 31 ix Fig 1.24 (a) Impact ionization efficiency as a function of lateral field with ambient temperature as the parameter. The positive temperature coefficient of impact ionization in the strained-Si/SiGe is apparent with respect to the small and opposite trend in that of the bulk Si (b) impact ionization efficiency as a function of temperature with Ge concentration as the parameter. 34 Fig. 1.25 (a) Gate and substrate current as a function of gate voltage (b) degradation of saturation current as a function of gate stress voltage in bulk Si and strained-Si 35 Fig. 1.26 (a) Simulated Fowler-Nordheim tunneling plot indicating an increase in the oxide potential barrier height in strained-Si relative to bulk Si. (b) actual degradation of saturation current as a function of stress time in strained-Si and bulk Si 35 Fig. 1.27 (a) Activation energy as a function of drain stress voltage in strained-Si devices [101] (b) similar activation energy versus drain stress voltage 37 Fig 2.1 Block diagram of the experimental setup adopted in the study of hot-carrier effects in MOSFET. 60 Fig. 2.2 Basic experimental setup for charge pumping measurement Fig 2.3 Schematics showing the measurement method used in NMOSFET. By varying the pulse base level Vbase with constant amplitude, five operating regions are established 62 Fig. 2.4 (a) Comparison between experimental charge-pumping curve and that of the calculated one, taking into account the recombination process in weak inversion and accumulation (b) results of MINIMOS simulations for threshold and flat-band voltages, as defined by the capture time for electrons and holes, respectively, as a function of the distance from a source or drain junction along the channel. ∆l is the region in the vicinity of the junction where charge pumping occurs for a gate pulse amplitude ∆VA. 65 Fig. 2.5 Summary of the expected influence of the interface trapped charge on the CP curve. Curve a is the CP curve for a low interface trap density; curve b for a high density of donor-type interface traps; curve c for a high density of acceptor-type interface traps 66 Fig. 2.6 Schematic illustration of the principle of the technique. (a) Vh of the gate pulse string is lower than flatband voltage and the varying Vh probes the interface traps in regions that have threshold voltages lower than Vh. (b) shows the Icp versus Vh curve and its derivative 68 62 x Fig. 2.7 Measured CP current for ultra thin (12-16 A) gate oxide. Note that 12 A gate has large leakage currents for Vgh < 0V 69 Fig. 2.8 Shows the dual frequency methodology- Using two-leakages CP curves to obtain a correct CP curve 70 Fig. 2.9 Linear drain current degradation as a function of stress time, monitored at high and low gate bias Vg for different stress drain voltages 71 Fig. 3.1 NMOSFET Idsat degradation after 100 channel hot-carrier stress versus channel length. Devices were stressed at either Ibpeak or at Vg=Vd. Technology A denotes devices processed using 0.25 µm technology. Technology B denotes devices processed using 0.1 µm technology 78 Fig. 3.2 Comparison of maximum impact ionization point for (a) drain avalanche hot-carrier (b) channel hot-carrier stress modes for 0.15µm NMOSFET 79 Fig. 3.3 (a) Threshold voltage shift ∆Vth and percentage decrease in the saturation drain current ∆Id,sat / Ido,sat as a function of gate stress voltage Vg. Filled triangular symbols denote the forward mode characteristics while the open triangular symbols denote the reverse mode characteristics of ∆Id,sat / Ido,sat (b) shows the corresponding increase in charge pumping current ∆Icp and the percentage decrease in maximum linear transconductance ∆gm / gmo. Also shown in the same plot is the substrate current Ib versus Vg characteristics (dashed line; Vd = 2.7 V). The dotted lines correspond to the Vg value that gives maximum Ib. 82 Fig. 3.4 (a) Increase in charge pumping current ∆Icp (symbol) and percentage decrease in maximum linear transconductance ∆gm / gmo (solid line) as a function of gate stress voltage Vg, with substrate bias Vb as the parameter. (b) The corresponding threshold voltage shift ∆Vth (symbol) and percentage decrease in saturation drain current ∆Id,sat / Ido,sat (reverse mode; solid line). 85 Fig. 3.5 (a) Substrate (Ib) and gate (Ig) currents as a function of drain voltage Vd, with substrate bias Vb as the parameter. During measurement, the gate voltage Vg was set equal to Vd. The thick solid line at the bottom right-hand corner shows much smaller Ig for Vd = 0, where no dependence on Vb is found. (b) Normalized gate current (Ig / Id) versus normalized substrate current (Ib / Id) characteristics (Vb = 0), with Vg − Vd as the parameter. 86 xi Fig 3.6 (a) Substrate (Ib) and hot-electron gate (Ige) current versus gate voltage Vg characteristics, with the substrate bias (Vb) as the parameter. The drain bias Vd = 2.7 V. Also shown for comparison is the gate tunneling leakage characteristics (Vd = Vb = 0). (b) Increase in the gate tunneling leakage ∆Ig / Igo (partially filled symbols) and charge pumping current ∆Icp (open symbols) versus stress time t characteristics for conventional (Vb = 0) (∆ ) and reverse substrate-biased Vb = –1.8 V (□ ) CHE stress (Vg = 0.5Vd = 1.5 V). 88 Fig 3.7 (a) Threshold voltage shift ∆Vth and fractional decrease in the drain current ∆Id / Ido as a function of stress time t. The linear ∆Id / Ido was measured at Vg = 0.6 V (~ Vth), Vd = 0.1 V, while the saturation ∆Id / Ido was measured at Vg = Vd = 1.8 V in the reverse mode. (b) The corresponding forward saturation ∆Id / Ido and linear ∆Id / Ido (measured at Vg = 1.8 V) characteristics. Also shown is the fractional decrease in the linear transconductance ∆gm / gmo. 89 Fig 3.8 Ratio ∆DR, given by ∆D(Vb = –1.8 V)/∆D(Vb = 0), as a function of the drain stress voltage Vd. ∆D is the parametric shift of interest, extracted after 104 s stress. The open (filled) symbols and dashed (solid) line denote the characteristics obtained from Vg = 0.5Vd (Vg = Vd) stress. Legends: Reverse saturation drain current decrease ∆Id (○ ●), threshold voltage shift ∆Vth (□ ■), and charge pumping current increase ∆Icp (solid and dashed lines). The inset shows the hot-electron gate (Ige) current versus Vg (= Vd) characteristics, under reverse substrate biasing: Vb = (○), –0.9 V (dashed line), and –1.8 V (●). Also shown are the corresponding substrate current characteristics denoted by solid lines. 91 Fig 3.9 Hot-carrier lifetime τ (@ saturation ∆Id / Ido = %) as a function of Ib / Id. The open (filled) symbols denote Vb = (–0.9 V) CHE stress at the Vg = Vd condition. The inset shows the corresponding τ versus / Vd plots. 93 Fig. 4.1 SIMS profile of As with different Ge concentrations. It is observed that the junction depth is increased significantly when the Ge concentration in the SiGe layer is varied from 14% to 29% 103 Fig. 4.2 Capacitance-voltage characteristics of the different substrates for 100 µm (W) x 10 µm (L) NMOSFET 106 Fig. 4.3 Drain current Id versus drain voltage Vd with gate overdrive Vg - Vt as the parameter for 1.2 µm (W) x 0.18 µm (L) NMOSFET. 106 Fig. 4.4 Comparison of the threshold voltage Vt versus device width W for 0.18 µm (L) NMOSFET. 107 xii Fig. 4.5 Normalized charge-pumping current Icp versus gate top voltage Vgt with W as the parameter for (a) control (b) 15% Ge and 20% Ge transistors with L of 0.18 µm. W is reduced from 20 µm to 0.5 µm 108 Fig. 4.6 Fractional difference in the average maximum charge-pumping current 〈Icp,max〉 for 0.18 µm (L) NMOSFET. Dashed line denotes the control used as the reference. 109 Fig. 4.7 The Y-Y’ line indicates the device cross-section in the width dimension. The shaded regions are the STI/gate edges. 109 Fig. 4.8 Comparison of the channel width deviation ∆W for 0.22 µm (W) x 20 µm (L) NMOSFET. 110 Fig. 4.9 Possible boron diffusion occurring at the STI/gate edge of a narrow width (a) control (b) strained-Si device. This is a blow up of the shaded region depicted in Fig. 4.6. The dashed double-arrowed lines indicate the Weff and the W. The ∆W (-) and the ∆W (+) denote the extension of the ∆W. 111 Fig 4.10 Normalized hot-electron gate current Ig/Id as a function of normalized substrate current Ib/Id at the Vg = Vd bias condition, Vb = V for 10 µm (W) x 0.5 µm (Lch) N-MOSFET. 113 Fig 4.11 Gate tunneling current Igt characteristics of 100 µm (W) x 10 µm (Lch) N-MOSFET. 113 Fig 4.12 (a) Gate injection current Ige and substrate current Ib as a function of Vg (=Vd) bias with reverse body bias Vb as the parameter. Symbols denote data from Vb = V measurement. (b) The corresponding Ige/Id vs Ib/Id characteristics of 10 µm (W) x 0.18 µm (Lch) control N-MOSFET. 115 Fig 4.13 (a) Gate injection current Ige and substrate current Ib as a function of Vg (=Vd) bias with reverse body bias Vb as the parameter. Symbols denote data from Vb = V measurement. (b) The corresponding Ige/Id vs Ib/Id characteristics of 10 µm (W) x 0.18 µm (Lch) 20 % Ge N-MOSFET. 116 Fig 4.14 (a) Gate injection current Ige and substrate current Ib as a function of Vg (=Vd) bias with reverse body bias Vb as the parameter. Symbols denote data from Vb = V measurement. (b) The corresponding Ige/Id vs Ib/Id characteristics of 10 µm (W) x 0.18 µm (Lch) 15 % Ge N-MOSFET. 117 xiii Fig 4.15 (a) Gate injection current Ige and substrate current Ib as a function of Vg (=Vd) bias with reverse body bias Vb as the parameter for control NMOSFET. Symbols denote data from Vb = V measurement. (b) The corresponding Ige and Ib characteristics of the strained-Si devices. Symbols denote the 15 % Ge device and lines denote the 20 % Ge device. All data are measured on 10 µm (W) x 0.5 µm (Lch) NMOSFET. 118 Fig 4.16 Gate injection current IgSHE and substrate current IbSHE as a function of reverse body bias Vb for 10 µm (W) x 1.2 µm (Lch) control N-MOSFET. Device is subjected to substrate-hot-electron biasing mode. The arrow indicates a second “step-like” increase in IbSHE at Vb ≈ -8 V, corresponding to the onset of secondary impact ionization near the Si/SiO2 interface. 119 Fig 4.17 Comparison of gate injection current IgSHE and substrate current IbSHE characteristics of 10 µm (W) x 1.2 µm (Lch) N-MOSFET. Device is subjected to substrate-hot-electron biasing mode. 120 Fig 4.18 Comparison of gate injection current IgSHE and substrate current IbSHE characteristics of 10 µm (W) x 0.16 µm (Lch) NMOSFET. Device is subjected to substrate-hot-electron biasing mode. 121 Fig 4.19 Gate injection current IgSHE extracted at Vb = -10 V as a function of channel length Lch for the control and the strained-Si devices. 122 Fig 4.20 Threshold voltage Vt as a function of channel length Lch. The data is the average of devices having width W = 20 µm. 122 Fig. 5.1 Schematics of the pulse I-V measurement setup Fig. 5.2 Example of how the pulse amplitude sweeps at the gate terminal of the transistor 140 Fig 5.3 Drain current Id as a function of ambient temperature Ta with drain voltage Vd as the parameter for (a) control (b) 15 % Ge (c) 20 % Ge devices having Lg = 0.18 µm and W = 20 µm. 141 Fig 5.4 Drain current Id as a function of drain voltage Vd with ambient temperature Ta as the parameter for (a) control (b) 15 % Ge (c) 20 % Ge devices having L = 0.18 µm and W = 20 µm. The gate voltage Vg is 1.8 V and Vd = to 1.8 V is used for Rth extraction. 143 Fig 5.5 Extraction of Rth for the 20 µm width transistors. The lines denote the linear best fits, the slope of which yields Rth. 144 139 xiv Fig 5.6 Extraction of Rth for devices with different gate widths W. 145 Fig 5.7 Thermal conductance 1/Rth as a function of the gate width W. 145 Fig 5.8 Increase in channel temperature ∆Tch as a function of channel width W for strained-Si and bulk-Si N-MOSFETs biased at Vg = Vd = 1.8 V and Vg = Vd = 2.7 V (stress condition). Filled and unfilled symbols denote ∆Tch obtained at chuck temperature T = 30 oC; half-filled symbols denote ∆Tch extracted 146 for 100 oC based on T = 30 oC. Fig 5.9 TEM image of device used in the channel temperature measurement 148 Fig. 5.10 Typical I-V curve measured under pulse and that under DC bias condition for control device with W = 20 µm and L = 0.18 µm at ambient temperature Ta of 25 °C 149 Fig. 5.11 Typical I-V curve measured under pulse and that under DC bias condition for strained-Si device with W = 20 µm and L = 0.18 µm at 150 ambient temperature Ta of 25 °C. Fig. 5.12 Ratio R = Id(pulsed)/Id(DC) as a function of pulse width Wp measured on W = 20 µm and L = 0.18 µm at ambient temperature Ta of 25 °C (Id extracted at Vg = Vd = 1.8 V). R at Wp = 40 ns is normalized by assuming the Id under DC bias equals to that under pulse condition for control device. 151 Fig. 5.13 (a) Gate voltage waveform for pulse width Wp of 60 ns and 250ns and the corresponding (b) voltage drop on the top portion of the waveform is due the effects on load capacitance on the waveform 152 Fig. 5.14 Typical plot of I–V curve measured under DC bias and pulse condition for W = 20 µm and L = 0.18 µm strained-Si device. Pulse I-V curves are obtained at a range of ambient temperature Ta from 25 to 150 °C at steps of 25 °C. 153 Fig. 5.15 Channel temperature Tch as a function of dissipated power Pd. The equation of the regression line is used to obtain the channel temperature of the strained-Si device at ambient temperature Ta of 25 °C. 154 Fig. 5.16 Channel temperature as a function of pulse width Wp. A regression line is used to obtain the channel temperature at Wp of ns where channel heating is insignificant. 155 xv Fig 6.1 Time dependent fractional degradation of the linear drain current, ∆Id/Ido. The strained-Si N-MOSFET exhibits a very significant shift in ∆Id/Ido (@ Vgm1 ~Vto) at short stress time, indicating substantial generation of interface states in the channel. 163 Fig. 6.2 Local threshold voltage and the corresponding derivative as a function of distance x 164 Fig. 6.3 Increase in charge pumping current ∆Icp and the corresponding derivative 165 d∆Icp/dVgt as a function of gate top voltage Vgt. Fig 6.4 Spatial distributions of the stress induced interface state density, extracted from charge pumping current measurement. The result confirms that hotelectron induced interface damage in the strained-Si device spread over a significant part of the channel at very short stress time. 166 Fig 6.5 Fractional degradation of linear current ∆Id/Ido and shift in charge pump current ∆Icp as a function of stress time t. NMOSFET of 10 µm (W) x 0.5 µm (L) are subjected to Fowler-Nordheim injection stress of Vg = 2.7 V. Note that square symbol () and dashed line denote the current degradation and increase in charge pump current in strained-Si respectively. Correspondingly, triangle symbol (∆) and full line denote that for bulk Si.167 Fig 6.6 Channel temperature Tch (in kelvin), normalized to the Tch of the bulk-Si NMOSFET of width W = 20 µm. Significant self-heating in the strained-Si device result in a Tch much larger than that of the bulk-Si device. 168 Fig 6.7 Impact ionization rate Ib/Id versus gate voltage Vg, showing excess hotcarrier current in the strained-Si device due to self-heating. The Ib/Id of the W = 20 µm and 0.5 µm strained-Si devices are comparable, while the Tch of the latter is ~1.4 x smaller than that of the former. The drawn channel length of all devices is 0.18 µm. 169 Fig 6.8 Time dependent fractional degradation of the linear drain current, ∆Id/Ido. The N-MOSFETs have drawn channel width of 0.5 µm. Trap generation in the channel of the narrow-width strained-Si devices is reduced as compared to the wide-channel counterpart shown in Fig. 6.1. 170 Fig 6.9 Schematic illustration of the impact of the high-energy “tail” on the spatial spread of the hot-electron induced oxide damage. Ecrit denotes the critical electron energy for trap generation. Solid line and denote the respective electron energy distribution (EED) at x = m (middle of the channel) and x = L (drain) for a relatively low lattice temperature. 171 Fig. 6.10 Increase in temperature as a function of time with the duty cycle as the parameter. This plot shows temperature reaches steady state if the thermal time constant is much greater than clock period 173 xvi Fig. 6.11 Fractional degradation in linear Id, ∆Id/Ido of (a) bulk-Si and (b) strained-Si N-MOSFETs subjected to dc and ac gate stress (varying stress duty cycles Dstr), as a function of effective stress time Tstr(eff) (= t x Dstr). Filled symbol denotes dc stress; unfilled symbol denotes 50% duty cycle stress; cross symbol denotes 10% duty cycle stress. 173 Fig. 6.12 The corresponding shift in charge pump current, ∆Icp for N-MOSFETs subjected to dc and ac gate stress (varying stress duty cycles Dstr), as a function of effective stress time Tstr(eff) (= t x Dstr). Filled symbol denotes dc stress; unfilled symbol denotes 50% duty cycle stress; cross symbol denotes 10% duty cycle stress 174 Fig 7.1 An example of an x-ray florescence in a scanning electron microscope system (SEM) 185 Fig 7.2 An example of a X-ray spectra taken Fig 7.3 Drain current Id as a function of drain voltage Vd with gate overdrives Vg-Vt as the parameter for strained-Si and bulk-Si N-MOSFETs. W = 20 µm; Tox = nm. 187 Fig 7.4 (a) TEM cross-section of 20% Ge strained-Si N-MOSFET with channel width W = 20 µm; open circles denote positions at which Ge concentrations are measured; horizontal demarcates the strained-Si (thickness 15 nm) / SiGe interface. (b) Variation of average Ge concentration CGe as a function of depth TSi at the gate edges and channel region of fresh strained-Si NMOSFETs. (c) Statistical variation of CGe extracted at TSi = nm 188 Fig 7.5 Threshold voltage variation of fresh strained-Si N-MOSFETs Fig 7.6 (a) Fractional increase in Ge concentration ∆CGe/CGeo at the gate edges and channel region as a function of depth TSi. The strained-Si N-MOSFETs with W = 20 µm were stressed at Vg = Vd = 2.7 V for 7×104 s. (b) Statistical variation of ∆CGe / CGeo extracted at TSi = nm. CGeo denotes the average Ge concentration of fresh devices. 191 Fig 7.7 Variation in the interface state density and fixed oxide charge density as a function of Ge concentration at the strained Si/SiO2 interface. The Ge concentrations at the surface have been calculated using TCAD simulation. Interface trap density and fixed oxide charge density significantly increased when Ge concentration at the surface becomes higher than 6% 192 186 189 xvii LIST OF TABLES Table 5.1 Summary of extracted channel temperature in strained-Si/SiGe via different methods. Technique A (Rth extraction method) and Technique B (Pulse I-V method). 155 [...]... Si/SiO2 interface 11 9 Fig 4 .17 Comparison of gate injection current IgSHE and substrate current IbSHE characteristics of 10 µm (W) x 1. 2 µm (Lch) N-MOSFET Device is subjected to substrate -hot- electron biasing mode 12 0 Fig 4 .18 Comparison of gate injection current IgSHE and substrate current IbSHE characteristics of 10 µm (W) x 0 .16 µm (Lch) NMOSFET Device is subjected to substrate -hot- electron biasing... varied from 14 % to 29% 10 3 Fig 4.2 Capacitance-voltage characteristics of the different substrates for 10 0 m (W) x 10 m (L) NMOSFET 10 6 Fig 4.3 Drain current Id versus drain voltage Vd with gate overdrive Vg - Vt as the parameter for 1. 2 m (W) x 0 .18 m (L) NMOSFET 10 6 Fig 4.4 Comparison of the threshold voltage Vt versus device width W for 0 .18 m (L) NMOSFET 10 7 xii Fig 4.5 Normalized charge-pumping current... width Wp A regression line is used to obtain the channel temperature at Wp of 7 ns where channel heating is insignificant 15 5 xv Fig 6 .1 Time dependent fractional degradation of the linear drain current, ∆Id/Ido The strained-Si N-MOSFET exhibits a very significant shift in ∆Id/Ido (@ Vgm1 ~Vto) at short stress time, indicating substantial generation of interface states in the channel 16 3 Fig 6.2 Local threshold... full line denote that for bulk Si .16 7 Fig 6.6 Channel temperature Tch (in kelvin), normalized to the Tch of the bulk-Si NMOSFET of width W = 20 m Significant self-heating in the strained-Si device result in a Tch much larger than that of the bulk-Si device 16 8 Fig 6.7 Impact ionization rate Ib/Id versus gate voltage Vg, showing excess hotcarrier current in the strained-Si device due to self-heating The... device and lines denote the 20 % Ge device All data are measured on 10 µm (W) x 0.5 µm (Lch) NMOSFET 11 8 Fig 4 .16 Gate injection current IgSHE and substrate current IbSHE as a function of reverse body bias Vb for 10 µm (W) x 1. 2 µm (Lch) control N-MOSFET Device is subjected to substrate -hot- electron biasing mode The arrow indicates a second “step-like” increase in IbSHE at Vb ≈ -8 V, corresponding to the... corresponding derivative as a function of distance x 16 4 Fig 6.3 Increase in charge pumping current ∆Icp and the corresponding derivative 16 5 d∆Icp/dVgt as a function of gate top voltage Vgt Fig 6.4 Spatial distributions of the stress induced interface state density, extracted from charge pumping current measurement The result confirms that hotelectron induced interface damage in the strained-Si device... 0 V for 10 µm (W) x 0.5 µm (Lch) N-MOSFET 11 3 Fig 4 .11 Gate tunneling current Igt characteristics of 10 0 µm (W) x 10 µm (Lch) N-MOSFET 11 3 Fig 4 .12 (a) Gate injection current Ige and substrate current Ib as a function of Vg (=Vd) bias with reverse body bias Vb as the parameter Symbols denote data from Vb = 0 V measurement (b) The corresponding Ige/Id vs Ib/Id characteristics of 10 µm (W) x 0 .18 µm (Lch)... The gate voltage Vg is 1. 8 V and Vd = 1 to 1. 8 V is used for Rth extraction 14 3 Fig 5.5 Extraction of Rth for the 20 µm width transistors The lines denote the linear best fits, the slope of which yields Rth 14 4 13 9 xiv Fig 5.6 Extraction of Rth for devices with different gate widths W 14 5 Fig 5.7 Thermal conductance 1/ Rth as a function of the gate width W 14 5 Fig 5.8 Increase in channel temperature... (a) control (b) 15 % Ge and 20% Ge transistors with L of 0 .18 m W is reduced from 20 m to 0.5 m 10 8 Fig 4.6 Fractional difference in the average maximum charge-pumping current 〈Icp,max〉 for 0 .18 m (L) NMOSFET Dashed line denotes the control used as the reference 10 9 Fig 4.7 The Y-Y’ line indicates the device cross-section in the width dimension The shaded regions are the STI/gate edges 10 9 Fig 4.8 Comparison... deviation ∆W for 0.22 m (W) x 20 m (L) NMOSFET 11 0 Fig 4.9 Possible boron diffusion occurring at the STI/gate edge of a narrow width (a) control (b) strained-Si device This is a blow up of the shaded region depicted in Fig 4.6 The dashed double-arrowed lines indicate the Weff and the W The ∆W (-) and the ∆W (+) denote the extension of the ∆W 11 1 Fig 4 .10 Normalized hot- electron gate current Ig/Id as a . Chapter 1 INTRODUCTION 1 1. 1 Impact of CMOS Technology Scaling on the Hot-Carrier Effects 1 1. 1 .1 Bulk Si CMOS Technology Trend 2 1. 1.2 The Change in CMOS Scaling Approach 5 1. 1.3 Hot-Carrier. Layer 19 1. 2.2 Current Enhancement in Strained-Si NMOSFET 21 1. 2.3 The Self-Heating Effect 27 1. 2.4 Process Induced Strain Relaxation 29 1. 3 Hot-Carrier Degradation in Strained-Si/SiGe NMOSFET. Degradation in Bulk Si NMOSFET 7 1. 1.4 Worst Case Degradation 9 1. 1.5 Hot-Carrier Degradation at Low Drain Voltage 14 1. 2 Extension of CMOS Technology Roadmap - Strained-Si Technology 18 1. 2 .1 The